MAX 3000A

Programmable Logic Device Family

Data Sheet

December 2002, ver. 3.2

Features...

Highperformance, lowcost CMOS EEPROMbased programmable logic devices (PLDs) built on a MAX architecture (see Table 1) 3.3-V in-system programmability (ISP) through the builtin IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability ISP circuitry compliant with IEEE Std. 1532 Builtin boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 Enhanced ISP features: Enhanced ISP algorithm for faster programming ISP_Done bit to ensure complete programming Pull-up resistor on I/O pins during insystem programming Highdensity PLDs ranging from 600 to 10,000 usable gates 4.5ns pintopin logic delays with counter frequencies of up to 227.3 MHz MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0V, 3.3V, and 2.5V logic levels Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic Jlead chip carrier (PLCC), and FineLine BGATM packages Hotsocketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance

Table 1. MAX 3000A Device Features Feature

Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tCO1 (ns) fCNT (MHz)

EPM3032A
600 32 2 34 4.5 2.9 3.0 227.3

EPM3064A
1,250 64 4 66 4.5 2.8 3.1 222.2

EPM3128A
2,500 128 8 96 5.0 3.3 3.4 192.3

EPM3256A
5,000 256 16 158 7.5 5.2 4.8 126.6

EPM3512A
10,000 512 32 208 7.5 5.6 4.7 116.3

Altera Corporation
DS-MAX3000A-3.2

MAX 3000A Programmable Logic Device Family Data Sheet

...and More Features

PCI compatible Busfriendly architecture including programmable slewrate control Opendrain output option Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable powersaving mode for a power reduction of over 50% in each macrocell Configurable expander productterm distribution, allowing up to 32 product terms per macrocell Programmable security bit for protection of proprietary designs Enhanced architectural features, including: 6 or 10 pin or logicdriven output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Programmable output slewrate control Software design support and automatic placeandroute provided by Alteras development systems for Windowsbased PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from thirdparty manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Programming support with the Altera master programming unit (MPU), MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from thirdparty manufacturers and any incircuit tester that supports JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf)

General Description

MAX 3000A devices are lowcost, highperformance devices based on the Altera MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 3000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 3000A devices in the 4, 5, 6, 7, and 10 speed grades are compatible with the timing requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

Table 2. MAX 3000A Speed Grades Device 4

EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A

Speed Grade 5 6 7 v v v v v v 10 v v v v v v v

The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and highdensity small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX 3000A devices are available in a wide range of packages, including PLCC, PQFP, and TQFP packages. See Table 3. Table 3. MAX 3000A Maximum User I/O Pins Device 44Pin PLCC
34 34

Note (1)

44Pin TQFP
34 34

100Pin 144Pin 208Pin 256-Pin TQFP TQFP PQFP FineLine BGA

66 80 96 116 158 172 208

EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Note:

(1)

When the IEEE Std. 1149.1 (JTAG) interface is used for insystem programming or boundaryscan testing, four I/O pins become JTAG pins.

MAX 3000A devices use CMOS EEPROM cells to implement logic functions. The userconfigurable MAX 3000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times.

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmableAND/fixedOR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. To build complex logic functions, each macrocell can be supplemented with shareable expander and highspeed parallel expander product terms to provide up to 32 product terms per macrocell. MAX 3000A devices provide programmable speed/power optimization. Speedcritical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. This speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50% or lower power while adding only a nominal timing delay. MAX 3000A devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when nonspeedcritical signals are switching. The output drivers of all MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are 2.5V, 3.3V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixedvoltage systems. MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, textincluding VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC and UNIXworkstationbased EDA tools. The software runs on Windowsbased PCs, as well as Sun SPARCstation, and HP 9000 Series 700/800 workstations.

f Functional Description

For more information on development tools, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. The MAX 3000A architecture includes the following elements:

Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array (PIA) I/O control blocks

The MAX 3000A architecture includes four dedicated inputs that can be used as generalpurpose inputs or as highspeed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 3000A devices.

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

Figure 1. MAX 3000A Device Block Diagram

INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1

INPUT/GCLRn 6 or 10 Output Enables (1) LAB A I/O Control Block 2 to 16 Macrocells 1 to 16 36 36 6 or 10 Output Enables (1) LAB B Macrocells 17 to 32 2 to 16 I/O Control Block

2 to 16 I/O

2 to 16 I/O

16 6 or 10 LAB C I/O Control Block 2 to 16 Macrocells 33 to 48 36 2 to 16 PIA

16 2 to 16 LAB D 36 Macrocells 49 to 64 2 to 16 I/O Control Block 6 or 10

2 to 16 I/O

2 to 16 I/O

16 6 or 10 2 to 16

16 2 to 16 6 or 10

Note:
(1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables.

Logic Array Blocks

The MAX 3000A device architecture is based on the linking of highperformance LABs. LABs consist of 16macrocell arrays, as shown in Figure 1. Multiple LABs are linked together via the PIA, a global bus that is fed by all dedicated input pins, I/O pins, and macrocells. Each LAB is fed by the following signals:

36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

Macrocells
MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, productterm select matrix, and programmable register. Figure 2 shows a MAX 3000A macrocell. Figure 2. MAX 3000A Macrocell
LAB Local Array Global Clear Parallel Logic Expanders (from other macrocells) Global Clocks 2 Programmable Register Register Bypass To I/O Control Block

PRN D/T Q

ProductTerm Select Matrix

VCC

Clock/ Enable Select

ENA CLRN

Clear Select

Shared Logic Expanders 36 Signals from PIA 16 Expander Product Terms

To PIA

Combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. The productterm select matrix allocates these product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinatorial functions, or as secondary inputs to the macrocells register preset, clock, and clock enable control functions. Two kinds of expander product terms (expanders) are available to supplement macrocell logic resources:

Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells

The Altera development system automatically optimizes productterm allocation according to the logic requirements of the design.
6 Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

For registered functions, each macrocell flipflop can be individually programmed to implement D, T, JK, or SR operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. Each programmable register can be clocked in three different modes:

Global clock signal mode, which achieves the fastest clocktooutput performance. Global clock signal enabled by an activehigh clock enable. A clock enable is generated by a product term. This mode provides an enable on each flipflop while still achieving the fast clocktooutput performance of the global clock. Array clock implemented with a product term. In this mode, the flipflop can be clocked by signals from buried macrocells or I/O pins.

Two global clock signals are available in MAX 3000A devices. As shown in Figure 1, these global clock signals can be the true or the complement of either of the two global clock pins, GCLK1 or GCLK2. Each register also supports asynchronous preset and clear functions. As shown in Figure 2, the productterm select matrix allocates product terms to control these operations. Although the producttermdriven preset and clear from the register are active high, activelow control can be obtained by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the activelow dedicated global clear pin (GCLRn).

Expander Product Terms

Although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. Another macrocell can be used to supply the required logic resources. However, the MAX 3000A architecture also offers both shareable and parallel expander product terms (expanders) that provide additional product terms directly to any macrocell in the same LAB. These expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

Shareable Expanders
Each LAB has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. Each shareable expander can be used and shared by any or all macrocells in the LAB to build complex logic functions. Shareable expanders incur a small delay (tSEXP). Figure 3 shows how shareable expanders can feed multiple macrocells. Figure 3. MAX 3000A Shareable Expanders
Shareable expanders can be shared by any or all macrocells in an LAB.

Macrocell Product-Term Logic

Product-Term Select Matrix

Macrocell Product-Term Logic

36 Signals from PIA

16 Shared Expanders

Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow up to 20 product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB.

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

The Altera development system compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (tPEXP ). For example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 tPEXP. Two groups of eight macrocells within each LAB (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. A macrocell borrows parallel expanders from lower numbered macrocells. For example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. Within each group of eight, the lowestnumbered macrocell can only lend parallel expanders and the highestnumbered macrocell can only borrow them. Figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. Figure 4. MAX 3000A Parallel Expanders
Unused product terms in a macrocell can be allocated to a neighboring macrocell.
From Previous Macrocell

Preset Producter Select Matrix Clock Clear

Macrocell ProductTerm Logic

Preset ProductT m Ter Select Matrix Clock Clear

Macrocell ProductTerm Logic

36 Signals from PIA

16 Shared Expanders

To Next Macrocell

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MAX 3000A Programmable Logic Device Family Data Sheet

Programmable Interconnect Array

Logic is routed between LABs on the PIA. This global bus is a programmable path that connects any signal source to any destination on the device. All MAX 3000A dedicated inputs, I/O pins, and macrocell outputs feed the PIA, which makes the signals available throughout the entire device. Only the signals required by each LAB are actually routed from the PIA into the LAB. Figure 5 shows how the PIA signals are routed into the LAB. An EEPROM cell controls one input to a two-input AND gate, which selects a PIA signal to drive into the LAB. Figure 5. MAX 3000A PIA Routing

To LAB

PIA Signals

While the routing delays of channelbased routing schemes in masked or FPGAs are cumulative, variable, and pathdependent, the MAX 3000A PIA has a predictable delay. The PIA makes a designs timing performance easy to predict.

I/O Control Blocks

The I/O control block allows each I/O pin to be individually configured for input, output, or bidirectional operation. All I/O pins have a tristate buffer that is individually controlled by one of the global output enable signals or directly connected to ground or VCC. Figure 6 shows the I/O control block for MAX 3000A devices. The I/O control block has 6 or 10 global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins, or a subset of the I/O macrocells.

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 6. I/O Control Block of MAX 3000A Devices

6 or 10 Global Output Enable Signals (1)

PIA
OE Select Multiplexer
VCC

to Other I/O Pins from Macrocell

GND

Open-Drain Output Slew-Rate Control

to PIA

Note:
(1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables.

When the tristate buffer control is connected to ground, the output is tri-stated (high impedance), and the I/O pin can be used as a dedicated input. When the tristate buffer control is connected to VCC, the output is enabled. The MAX 3000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic.

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MAX 3000A Programmable Logic Device Family Data Sheet

InSystem Programmability

MAX 3000A devices can be programmed insystem via an industry standard fourpin IEEE Std. 1149.1-1990 (JTAG) interface. In-system programmability (ISP) offers quick, efficient iterations during design development and debugging cycles. The MAX 3000A architecture internally generates the high programming voltages required to program its EEPROM cells, allowing insystem programming with only a single 3.3V power supply. During insystem programming, the I/O pins are tristated and weakly pulledup to eliminate board conflicts. The pullup value is nominally 50 k. MAX 3000A devices have an enhanced ISP algorithm for faster programming. These devices also offer an ISP_Done bit that ensures safe operation when insystem programming is interrupted. This ISP_Done bit, which is the last bit programmed, prevents all I/O pins from driving until the bit is programmed. ISP simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board (PCB) with standard pickandplace equipment before they are programmed. MAX 3000A devices can be programmed by downloading the information via incircuit testers, embedded processors, the MasterBlaster communications cable, the ByteBlasterMV parallel port download cable, and the BitBlaster serial download cable. Programming the devices after they are placed on the board eliminates lead damage on highpincount packages (e.g., QFP packages) due to device handling. MAX 3000A devices can be reprogrammed after a system has already shipped to the field. For example, product upgrades can be performed in the field via software or modem. The Jam STAPL programming and test language can be used to program MAX 3000A devices with incircuit testers, PCs, or embedded processors.

For more information on using the Jam STAPL programming and test language, see Application Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor), Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor) and AN 111 (Embedded Programming Using the 8051 and Jam Byte-Code). The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors.

Programming with External Hardware f

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MAX 3000A devices can be programmed on Windowsbased PCs with an Altera Logic Programmer card, MPU, and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. For more information, see the Altera Programming Hardware Data Sheet.
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MAX 3000A Programmable Logic Device Family Data Sheet

The Altera software can use text or waveformformat test vectors created with the Altera Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. Data I/O, BP Microsystems, and other programming hardware manufacturers also provide programming support for Altera devices.

f IEEE Std. 1149.1 (JTAG) BoundaryScan Support

For more information, see Programming Hardware Manufacturers. MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.11990. Table 4 describes the JTAG instructions supported by MAX 3000A devices. The pin-out tables found on the Altera web site (http://www.altera.com) or the Altera Digital Library show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins.

Table 4. MAX 3000A JTAG Instructions JTAG Instruction

SAMPLE/PRELOAD EXTEST BYPASS

Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins Allows the external circuitry and boardlevel interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins Places the 1bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation Selects the IDCODE register and places it between the TDI and TDO pins, allowing the IDCODE to be serially shifted out of TDO Selects the 32bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE value to be shifted out of TDO These instructions are used when programming MAX 3000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL file, JBC file, or SVF file via an embedded processor or test equipment

IDCODE USERCODE ISP Instructions

The instruction register length of MAX 3000A devices is 10 bits. The IDCODE and USERCODE register length is 32 bits. Tables 5 and 6 show the boundaryscan register length and device IDCODE information for MAX 3000A devices.

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 5. MAX 3000A BoundaryScan Register Length Device

EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A

BoundaryScan Register Length

96 192 288 480 624

Table 6. 32Bit MAX 3000A Device IDCODE Value Device Version (4 Bits)
EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Notes:
(1) (2)

Note (1)

IDCODE (32 bits) Part Number (16 Bits)

0111 0000 0011 0010 0111 0000 0110 0100 0111 0001 0010 1000 0111 0010 0101 0110 0111 0101 0001 0010

Manufacturers 1 (1 Bit) Identity (11 Bits) (2)

00001101110 00001101110 00001101110 00001101110 00001101110 1 1 1 1 1

0001 0001 0001 0001 0001

The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1.

See Application Note 39 (IEEE 1149.1 (JTAG) BoundaryScan Testing in Altera Devices) for more information on JTAG BST.

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 7 shows the timing information for the JTAG signals. Figure 7. MAX 3000A JTAG Waveforms
TMS

TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH

tJSZX

tJSCO

tJSXZ

Table 7 shows the JTAG timing parameters and values for MAX 3000A devices. Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 25 25 25

Parameter

Min
100 50 50 20 45

Max

Unit
ns ns ns ns ns

25 25 25

ns ns ns ns ns ns ns ns

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MAX 3000A Programmable Logic Device Family Data Sheet

Programmable Speed/Power Control

MAX 3000A devices offer a powersaving mode that supports low-power operation across userdefined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more because most logic applications require only a small fraction of all gates to operate at maximum frequency. The designer can program each individual macrocell in a MAX 3000A device for either highspeed or lowpower operation. As a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. Macrocells that run at low power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tACL, tEN, tCPPW and tSEXP parameters.

Output Configuration

MAX 3000A device outputs can be programmed to meet a variety of systemlevel requirements.

MultiVolt I/O Interface

The MAX 3000A device architecture supports the MultiVolt I/O interface feature, which allows MAX 3000A devices to connect to systems with differing supply voltages. MAX 3000A devices in all packages can be set for 2.5V, 3.3V, or 5.0V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). The VCCIO pins can be connected to either a 3.3V or 2.5V power supply, depending on the output requirements. When the VCCIO pins are connected to a 2.5V power supply, the output levels are compatible with 2.5V systems. When the VCCIO pins are connected to a 3.3V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0V systems. Devices operating with VCCIO levels lower than 3.0 V incur a nominally greater timing delay of tOD2 instead of tOD1. Inputs can always be driven by 2.5V, 3.3V, or 5.0V signals. Table 8 summarizes the MAX 3000A MultiVolt I/O support. Table 8. MAX 3000A MultiVolt I/O Support VCCIO Voltage 2.5
2.5 3.3 Note:
(1) When VCCIO is 3.3 V, a MAX 3000A device can drive a 2.5V device that has 3.3V tolerant inputs.

Input Signal (V) 3.3 v v 5.0 v v v v

Output Signal (V) 2.5 v v v v 3.3 5.0

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MAX 3000A Programmable Logic Device Family Data Sheet

OpenDrain Output Option

MAX 3000A devices provide an optional opendrain (equivalent to open-collector) output for each I/O pin. This opendrain output enables the device to provide systemlevel control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wiredOR plane. Open-drain output pins on MAX 3000A devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a high VIH. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby meeting CMOS requirements. The open-drain pin will only drive low or tri-state; it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor

SlewRate Control
The output buffer for each MAX 3000A I/O pin has an adjustable output slew rate that can be configured for lownoise or highspeed performance. A faster slew rate provides highspeed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. When the configuration cell is turned off, the slew rate is set for lownoise performance. Each I/O pin has an individual EEPROM bit that controls the slew rate, allowing designers to specify the slew rate on a pinbypin basis. The slew rate control affects both the rising and falling edges of the output signal.

Design Security

All MAX 3000A devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because programmed data within EEPROM cells is invisible. The security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. MAX 3000A devices are fully tested. Complete testing of each programmable EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in Figure 8. Test patterns can be used and then erased during early stages of the production flow.

Generic Testing

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 8. MAX 3000A AC Test Conditions

Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Largeamplitude, fast groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5V outputs. Numbers without brackets are for 3.3V devices or outputs.
VCC 703 [521 ] Device Output

To Test System

620 [481 ] Device input rise and fall times < 2 ns

C1 (includes jig capacitance)

Operating Conditions

Tables 9 through 12 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for MAX 3000A devices. Note (1) Min
0.5 2.0 25 No bias Under bias PQFP and TQFP packages, under bias 65 65

Table 9. MAX 3000A Device Absolute Maximum Ratings Symbol

VCC VI IOUT TSTG TA TJ

Parameter
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature

Conditions
With respect to ground (2)

Max
4.6 5.75 25 150 135 135

Unit
V V mA C C C

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 10. MAX 3000A Device Recommended Operating Conditions Symbol

VCCINT VCCIO

Parameter
Supply voltage for internal logic and (10) input buffers Supply voltage for output drivers, 3.3V operation Supply voltage for output drivers, 2.5V operation

Conditions

Min
3.0 3.0 2.3 3.0

Max
3.6 3.6 2.7 3.6 5.75 VCCIO 70 90 40 40

Unit
V V V V V V C C ns ns

VCCISP VI VO TA TJ tR tF

Supply voltage during ISP Input voltage Output voltage Ambient temperature Junction temperature Input rise time Input fall time For commercial use For commercial use (3)

0.5 0 0 0

Table 11. MAX 3000A Device DC Operating Conditions Symbol

VIH VIL VOH

Note (4) Min

1.7 0.5

Parameter
Highlevel input voltage Lowlevel input voltage 3.3V highlevel TTL output voltage 3.3V highlevel CMOS output voltage 2.5V highlevel output voltage

Conditions

Max
5.75 0.8

Unit
V V V V V V V

IOH = 8 mA DC, VCCIO = 3.00 V (5) IOH = 0.1 mA DC, VCCIO = 3.00 V (5) IOH = 100 A DC, VCCIO = 2.30 V (5) IOH = 1 mA DC, VCCIO = 2.30 V (5) IOH = 2 mA DC, VCCIO = 2.30 V (5)

2.4 VCCIO 0.2 2.1 2.0 1.7 0.4 0.2 0.2 0.4 0.7 10 10 20 10 10 74

VOL

3.3V lowlevel TTL output voltage IOL = 8 mA DC, VCCIO = 3.00 V (6) 3.3V lowlevel CMOS output voltage 2.5V lowlevel output voltage IOL = 0.1 mA DC, VCCIO = 3.00 V (6) IOL = 100 A DC, VCCIO = 2.30 V (6) IOL = 1 mA DC, VCCIO = 2.30 V (6) IOL = 2 mA DC, VCCIO = 2.30 V (6)

V V V V V A A k

II IOZ RI S P

Input leakage current Tristate output offstate current Value of I/O pin pullup resistor when programming insystem or during powerup

V I = 0.5 to 5.5 V (7) VI = 0.5 to 5.5 V (7) VC C I O = 2.3 to 3.6 V (8)

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 12. MAX 3000A Device Capacitance Symbol

CIN CI/O

Note (9) Conditions Min Max

8 8

Parameter
Input pin capacitance I/O pin capacitance

Unit
pF pF

VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz

Notes to tables:
(1) (2) See the Operating Requirements for Altera Devices Data Sheet. Minimum DC input voltage is 0.5 V. During transitions, the inputs may undershoot to 2.0 V or overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (4) These values are specified under the recommended operating conditions, as shown in Table 10 on page 19. (5) The parameter is measured with 50 % of the outputs each sourcing the specified current. The IOH parameter refers to highlevel TTL or CMOS output current. (6) The parameter is measured with 50% of the outputs each sinking the specified current. The IOL parameter refers to lowlevel TTL, PCI, or CMOS output current. (7) This value is specified during normal device operation. During power-up, the maximum leakage current is 300 A. (8) This pullup exists while devices are programmed insystem and in unprogrammed devices during powerup. (9) Capacitance is measured at 25 C and is sampletested only. The OE1 pin (highvoltage pin during programming) has a maximum capacitance of 20 pF. (10) The POR time for all MAX 3000A devices does not exceed 100 s. The sufficient VCCINT voltage level for POR is 3.0 V. The device is fully initialized within the POR time after VCCINT reaches the sufficient POR voltage level.

Figure 9 shows the typical output drive characteristics of MAX 3000A devices.

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 9. Output Drive Characteristics of MAX 3000A Devices

3.3 V
150

IOL

100

Typical IO Output Current (mA)

50

VCCINT = 3.3 V VCCIO = 3.3 V O Temperature = 25 C

IOH
0 0

VO Output Voltage (V)

2.5 V
150

IOL

Typical IO Output Current (mA)

100

VCCINT = 3.3 V VCCIO = 2.5 V O Temperature = 25 C

50

IOH
0 0

VO Output Voltage (V)

Power Sequencing & HotSocketing

Because MAX 3000A devices can be used in a mixedvoltage environment, they have been designed specifically to tolerate any possible powerup sequence. The VCCIO and VCCINT power planes can be powered in any order. Signals can be driven into MAX 3000A devices before and during power-up without damaging the device. In addition, MAX 3000A devices do not drive out during power-up. Once operating conditions are reached, MAX 3000A devices operate as specified by the user.

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Timing Model

MAX 3000A device timing can be analyzed with the Altera software, with a variety of popular industrystandard EDA simulators and timing analyzers, or with the timing model shown in Figure 10. MAX 3000A devices have predictable internal delays that enable the designer to determine the worstcase timing of any design. The software provides timing simulation, pointtopoint delay prediction, and detailed timing analysis for devicewide performance evaluation.

Figure 10. MAX 3000A Timing Model

Internal Output Enable Delay t IOE Input Delay t IN PIA Delay t PIA Global Control Delay t GLOB Logic Array Delay t LAD Register Control Delay t LAC tIC t EN Shared Expander Delay t SEXP

Parallel Expander Delay t PEXP

Register Delay t SU tH t PRE t CLR t RD t COMB

Output Delay t OD1 t OD2 t OD3 t XZ t Z X1 t Z X2 t Z X3 I/O Delay tI O

The timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. External timing parameters, which represent pintopin timing delays, can be calculated as the sum of internal parameters. Figure 11 shows the timing relationship between internal and external delay parameters.

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 11. MAX 3000A Switching Waveforms

tR & tF < 2 ns. Inputs are driven at 3 V for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V.

Combinatorial Mode
tIN Input Pin tIO I/O Pin tPIA PIA Delay tSEXP Shared Expander Delay tLAC , tLAD Logic Array Input tPEXP Parallel Expander Delay tCOMB Logic Array Output tOD Output Pin

Global Clock Mode

Global Clock Pin Global Clock at Register tSU Data or Enable (Logic Array Output) tR tIN tCH tCL tF

tGLOB tH

Array Clock Mode

tR Input or I/O Pin tIN tIO Clock into PIA Clock into Logic Array Clock at Register Data from Logic Array tRD Register to PIA to Logic Array tOD Register Output to Pin tOD tPIA tCLR , tPRE tPIA tPIA tACH tACL tF

tIC tSU tH

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Tables 13 through 20 show EPM3032A, EPM3064A, EPM3128A, EPM3256A, and EPM3512A timing information. Table 13. EPM3032A External Timing Parameters Symbol Parameter Conditions 4 Min
tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to non registered output I/O input to non registered output Global clock setup time C1 = 35 pF (2) C1 = 35 pF (2) (2) 2.9 0.0 1.0 2.0 2.0 1.6 0.3 1.0 2.0 2.0 (3) 2.0 4.4 227.3 4.4 227.3 138.9 138.9 7.2 103.1 4.3 (2) C1 = 35 pF (2) 3.0

Note (1) Speed Grade 7 Max

4.5 4.5 4.7 0.0 1.0 3.0 3.0 2.5 0.5 1.0 3.0 3.0 3.0 7.2 103.1 9.7 7.2 5.0

Unit 10

Min

Max
7.5 7.5

Min

Max
10 10 ns ns ns ns 6.7 ns ns ns ns ns 9.4 ns ns ns ns 9.7 ns MHz ns MHz

6.3 0.0 1.0 4.0 4.0 3.6 0.5 1.0 4.0 4.0 4.0

Global clock hold time (2) Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset

Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2)

Maximum internal (2), (4) array clock frequency

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 14. EPM3032A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions 4 Min
tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF

Note (1) Speed Grade 7 Max

0.7 0.7 1.9 0.5 1.5 0.6 0.0 0.8

Unit 10

Min

Max
1.2 1.2 3.1 0.8 2.5 1.0 0.0 1.3

Min

Max
1.5 1.5 4.0 1.0 3.3 1.2 0.0 1.8 ns ns ns ns ns ns ns ns

tOD2

C1 = 35 pF

1.3

1.8

2.3

ns

tOD3

C1 = 35 pF

5.8

6.3

6.8

ns

tZX1

Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time 1.3 0.6

4.0

4.0

5.0

ns

tZX2

4.5

4.5

5.5

ns

tZX3

9.0

9.0

10.0

ns

tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE

4.0 2.0 1.0 0.7 0.6 1.2 0.6 0.8 1.2

4.0 2.8 1.3 1.2 1.0 2.0 1.0 1.3 1.9

5.0

ns ns ns

1.5 1.3 2.5 1.2 1.9 2.6

ns ns ns ns ns ns

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 14. EPM3032A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions 4 Min
tCLR tPIA tLPA Register clear time PIA delay Lowpower adder (2) (5)

Note (1) Speed Grade 7 Max

1.2 0.9 2.5

Unit 10

Min

Max
1.9 1.5 4.0

Min

Max
2.6 2.1 5.0 ns ns ns

Table 15. EPM3064A External Timing Parameters Symbol Parameter Conditions

Note (1) Speed Grade 4 Min Max

4.5 4.5 2.8 0.0 1.0 2.0 2.0 3.1 4.7 0.0 1.0 3.0 3.0 2.6 0.4 4.3 1.0 3.0 3.0 3.0 4.5 222.2 4.5 222.2 135.1 135.1 7.4 100.0 7.4 100.0 10.0 7.2 5.1

Unit 10

7 Min Max
7.5 7.5 6.2 0.0 1.0 4.0 4.0 3.6 0.6 1.0 4.0 4.0 4.0

Min

Max
10.0 10.0 ns ns ns ns 7.0 ns ns ns ns ns 9.6 ns ns ns ns 10.0 ns MHz ns MHz

tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT

Input to nonregistered output

C1 = 35 pF (2)

I/O input to nonregistered C1 = 35 pF (2) output Global clock setup time Global clock hold time Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Maximum internal array clock frequency (3) (2) (2), (4) (2) (2) C1 = 35 pF (2) (2) (2)

Global clock to output delay C1 = 35 pF

1.6 0.3 1.0 2.0 2.0 2.0

Minimum array clock period (2) (2), (4)

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 16. EPM3064A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions 4 Min
tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF

Note (1) Speed Grade 7 Max

0.6 0.6 1.8 0.4 1.5 0.6 0.0 0.8

Unit 10

Min

Max
1.1 1.1 3.0 0.7 2.5 1.0 0.0 1.3

Min

Max
1.4 1.4 3.9 0.9 3.2 1.2 0.0 1.8 ns ns ns ns ns ns ns ns

tOD2

C1 = 35 pF

1.3

1.8

2.3

ns

tOD3

C1 = 35 pF

5.8

6.3

6.8

ns

tZX1

Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time 1.3 0.6

4.0

4.0

5.0

ns

tZX2

4.5

4.5

5.5

ns

tZX3

9.0

9.0

10.0

ns

tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR

4.0 2.0 1.0 0.7 0.6 1.2 0.6 1.0 1.3 1.3

4.0 2.9 1.3 1.2 0.9 1.9 1.0 1.5 2.1 2.1

5.0

ns ns ns

1.6 1.3 2.5 1.2 2.2 2.9 2.9

ns ns ns ns ns ns ns

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 16. EPM3064A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions 4 Min
tPIA tLPA PIA delay Lowpower adder (2) (5)

Note (1) Speed Grade 7 Max

1.0 3.5

Unit 10

Min

Max
1.7 4.0

Min

Max
2.3 5.0 ns ns

Table 17. EPM3128A External Timing Parameters Symbol Parameter Conditions

Note (1) Speed Grade 5 7 Max

5.0 5.0

Unit 10

Min
tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT Input to non registered output I/O input to non registered output Global clock setup time C1 = 35 pF (2) C1 = 35 pF (2) (2) 3.3 0.0 1.0 2.0 2.0 1.8 0.2 1.0 2.0 2.0 (3) 2.0 (2) C1 = 35 pF (2)

Min

Max
7.5 7.5

Min

Max
10 10 ns ns ns ns 6.6 ns ns ns ns ns 9.4 ns ns ns ns 10.2 ns MHz 10.2 ns MHz

4.9 0.0 3.4 1.0 3.0 3.0 2.8 0.3 4.9 1.0 3.0 3.0 3.0 5.2 7.7 129.9 5.2 7.7 129.9 7.1 5.0

6.6 0.0 1.0 4.0 4.0 3.8 0.4 1.0 4.0 4.0 4.0

Global clock hold time (2) Global clock to output C1 = 35 pF delay Global clock high time Global clock low time Array clock setup time (2) Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset

Minimum global clock (2) period Maximum internal (2), (4) global clock frequency Minimum array clock period (2) 192.3 192.3

98.0

Maximum internal (2), (4) array clock frequency

98.0

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 18. EPM3128A Internal Timing Parameters (Part 1 of 2) Symbol Parameter Conditions 5 Min
tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1 Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF

Note (1) Speed Grade 7 Max

0.7 0.7 2.0 0.4 1.6 0.7 0.0 0.8

Unit 10

Min

Max
1.0 1.0 2.9 0.7 2.4 1.0 0.0 1.2

Min

Max
1.4 1.4 3.8 0.9 3.1 1.3 0.0 1.6 ns ns ns ns ns ns ns ns

tOD2

C1 = 35 pF

1.3

1.7

2.1

ns

tOD3

C1 = 35 pF

5.8

6.2

6.6

ns

tZX1

Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, C1 = 35 pF slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, C1 = 35 pF slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay C1 = 5 pF Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time 1.4 0.6

4.0

4.0

5.0

ns

tZX2

4.5

4.5

5.5

ns

tZX3

9.0

9.0

10.0

ns

tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR

4.0 2.1 1.0 0.8 0.5 1.2 0.7 1.1 1.4 1.4

4.0 2.9 1.3 1.2 0.9 1.7 1.0 1.6 2.0 2.0

5.0

ns ns ns

1.6 1.3 2.2 1.3 2.0 2.7 2.7

ns ns ns ns ns ns ns

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 18. EPM3128A Internal Timing Parameters (Part 2 of 2) Symbol Parameter Conditions 5 Min
tPIA tLPA PIA delay Lowpower adder (2) (5)

Note (1) Speed Grade 7 Max

1.4 4.0

Unit 10

Min

Max
2.0 4.0

Min

Max
2.6 5.0 ns ns

Table 19. EPM3256A External Timing Parameters Symbol Parameter Conditions

Note (1) Speed Grade 7 Min Max

7.5 7.5 5.2 0.0 1.0 3.0 3.0 4.8 6.9 0.0 1.0 4.0 4.0 3.6 0.5 7.3 1.0 4.0 4.0 4.0 7.9 126.6 7.9 126.6 95.2 95.2 10.5 10.5 9.7 6.4

Unit 10

Min

Max
10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz

tPD1 tPD2 tSU tH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT

Input to nonregistered output

C1 = 35 pF (2)

I/O input to nonregistered C1 = 35 pF (2) output Global clock setup time Global clock hold time Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency (3) (2) (2), (4) (2) (2), (4) (2) (2) (2) (2) C1 = 35 pF

2.7 0.3 1.0 3.0 3.0 3.0

Array clock to output delay C1 = 35 pF (2)

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 20. EPM3256A Internal Timing Parameters Symbol Parameter

Note (1) Speed Grade 7 Min Max

0.9 0.9 2.8 0.5 2.2 1.0 0.0

Conditions

Unit 10

Min

Max
1.2 1.2 3.7 0.6 2.8 1.3 0.0 1.6 ns ns ns ns ns ns ns ns

tIN tIO tSEXP tPEXP tLAD tLAC tIOE tOD1

Input pad and buffer delay I/O input pad and buffer delay Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V C1 = 35 pF

1.2

tOD2

C1 = 35 pF

1.7

2.1

ns

tOD3

C1 = 35 pF

6.2

6.6

ns

tZX1 tZX2 tZX3

Output buffer enable delay, slow C1 = 35 pF slew rate = off VCCIO = 3.3 V Output buffer enable delay, slow C1 = 35 pF slew rate = off VCCIO = 2.5 V Output buffer enable delay, slow C1 = 35 pF slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer disable delay Register setup time Register hold time Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay Lowpower adder (2) (5) C1 = 5 pF 2.1 0.9

4.0 4.5 9.0

5.0 5.5 10.0

ns ns ns

tXZ tSU tH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA tLPA

4.0 2.9 1.2 1.2 0.8 1.6 1.0 1.5 2.3 2.3 2.4 4.0

5.0

ns ns ns

1.6 1.2 2.1 1.3 2.0 3.0 3.0 3.2 5.0

ns ns ns ns ns ns ns ns ns

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 21. EPM3512A External Timing Parameters Symbol Parameter

Note (1) Speed Grade -7 Min Max

7.5 7.5 5.6 0.0 3.0 0.0 7.6 0.0 3.0 0.0 4.7 1.0 4.0 4.0 3.5 0.3 7.8 1.0 4.0 4.0 4.0 8.6 116.3 8.6 116.3 87.0 87.0 11.5 11.5 10.4 6.3

Conditions

Unit -10

Min

Max
10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz

tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCPPW tCNT fCNT tACNT fACNT

Input to non-registered output I/O input to non-registered output Global clock setup time Global clock hold time Global clock setup time of fast input Global clock hold time of fast input Global clock to output delay Global clock high time Global clock low time Array clock setup time Array clock hold time Array clock to output delay Array clock high time Array clock low time Minimum pulse width for clear and preset Minimum global clock period Maximum internal global clock frequency Minimum array clock period Maximum internal array clock frequency

C1 = 35 pF (2) C1 = 35 pF (2) (2) (2)

C1 = 35 pF

1.0 3.0 3.0

(2) (2) C1 = 35 pF (2)

2.5 0.2 1.0 3.0 3.0

(3) (2) (2), (4) (2) (2), (4)

3.0

Table 22. EPM3512A Internal Timing Parameters (Part 1 of 3) Symbol Parameter Conditions

Note (1) Speed Grade -7 -10 Max

0.7 0.7 3.1

Unit

Min
tIN tIO tFIN Input pad and buffer delay I/O input pad and buffer delay Fast input delay

Min

Max
0.9 0.9 3.6 ns ns ns

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 22. EPM3512A Internal Timing Parameters (Part 2 of 3) Symbol Parameter Conditions

Note (1) Speed Grade -7 -10 Max

2.7 0.4 2.2 1.0 0.0

Unit

Min
tSEXP tPEXP tLAD tLAC tIOE tOD1 Shared expander delay Parallel expander delay Logic array delay Logic control array delay Internal output enable delay Output buffer and pad delay, slow slew rate = off VCCIO = 3.3 V Output buffer and pad delay, slow slew rate = off VCCIO = 2.5 V Output buffer and pad delay, slow slew rate = on VCCIO = 2.5 V or 3.3 V Output buffer enable delay, slow slew rate = off VCCIO = 3.3 V Output buffer enable delay, slow slew rate = off VCCIO = 2.5 V Output buffer enable delay, slow slew rate = on VCCIO = 3.3 V Output buffer disable delay Register setup time Register hold time Register setup time of fast input Register hold time of fast input Register delay Combinatorial delay Array clock delay Register enable time Global control delay Register preset time Register clear time PIA delay (2) C1 = 35 pF

Min

Max
3.5 0.5 2.8 1.3 0.0 1.5 ns ns ns ns ns ns

1.0

tOD2

C1 = 35 pF

1.5

2.0

ns

tOD3

C1 = 35 pF

6.0

6.5

ns

tZX1

C1 = 35 pF

4.0

5.0

ns

tZX2

C1 = 35 pF

4.5

5.5

ns

tZX3

C1 = 35 pF

9.0

10.0

ns

tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tPIA

C1 = 5 pF 2.1 0.6 1.6 1.4

4.0 3.0 0.8 1.6 1.4 1.3 0.6 1.8 1.0 1.7 1.0 1.0 3.0

5.0

ns ns ns ns ns

1.7 0.8 2.3 1.3 2.2 1.4 1.4 4.0

ns ns ns ns ns ns ns ns

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Table 22. EPM3512A Internal Timing Parameters (Part 3 of 3) Symbol Parameter Conditions

Note (1) Speed Grade -7 -10 Max

4.5

Unit

Min
tLPA
(1) (2) (3)

Min

Max
5.0 ns

Low-power adder

(5)

Notes to tables:
These values are specified under the recommended operating conditions, as shown in Table 10 on page 19. See Figure 11 on page 23 for more information on switching waveforms. These values are specified for a PIA fanout of one LAB (16 macrocells). For each additional LAB fanout in these devices, add an additional 0.1 ns to the PIA timing value. This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal path. These parameters are measured with a 16bit loadable, enabled, up/down counter programmed into each LAB. The tLPA parameter must be added to the tLAD , tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells running in lowpower mode.

(4) (5)

Power Consumption

Supply power (P) versus frequency (fMAX, in MHz) for MAX 3000A devices is calculated with the following equation: P = PINT + PIO = ICCINT VCC + PIO The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices). The ICCINT value depends on the switching frequency and the application logic. The ICCINT value is calculated with the following equation: ICCINT = (A MCTON) + [B (MCDEV MCTON)] + (C MCUSED fMAX togLC) The parameters in the ICCINT equation are:

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MAX 3000A Programmable Logic Device Family Data Sheet

MCTON MCDEV MCUSED fMAX togLC A, B, C

= = = = = =

Number of macrocells with the Turbo BitTM option turned on, as reported in the MAX+PLUS II Report File (.rpt) Number of macrocells in the device Total number of macrocells in the design, as reported in the RPT File Highest clock frequency to the device Average percentage of logic cells toggling at each clock (typically 12.5%) Constants (shown in Table 23)

Table 23. MAX 3000A ICC Equation Constants Device

EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A

A
0.85 0.85 0.85 0.85 0.85

B
0.36 0.36 0.36 0.36 0.36

C
0.017 0.017 0.017 0.017 0.017

The ICCINT calculation provides an ICC estimate based on typical conditions using a pattern of a 16bit, loadable, enabled, up/down counter in each LAB with no output load. Actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figures 12 and 13 show the typical supply current versus frequency for MAX 3000A devices.

Altera Corporation

35

MAX 3000A Programmable Logic Device Family Data Sheet

Figure 12. ICC vs. Frequency for MAX 3000A Devices

EPM3032A

V CC = 3.3 V

Room Temperature
70 60 50

Typical I CC Active (mA)

High Speed

40 30 20 10

227.3 MHz

144.9 MHz

Non-Turbo

50

100

150

200

250

Frequency (MHz)

EPM3064A

V CC = 3.3 V

Room Temperature
140 120 100

Typical I CC Active (mA) 80

60 40 20

High Speed

222.2 MHz

125.0 MHz

Non-Turbo
0
50 100

150

200

250

Frequency (MHz)

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 13. ICC vs. Frequency for MAX 3000A Devices

EPM3128A V CC = 3.3 V Room Temperature 210 180 150 Typical I CC Active (mA) 120 90 108.7 MHz 60 30 0 50

High Speed

192.3 MHz

Non-Turbo

100

150

200

250

Frequency (MHz)

EPM3256A V CC = 3.3 V Room Temperature 350 300 250 Typical I CC Active (mA) 172.4 MHz

High Speed
200 150 100 50 0 50 100 150 200 102.0 MHz

Non-Turbo

Frequency (MHz) EPM3512A

600

V CC = 3.3 V Room Temperature

116.3 MHz

500

400

High Speed

Typical I CC Active (mA)

300

76.3 MHz
200

Low Power
100

20

40

60

80

100

120

140

Frequency (MHz)

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Device PinOuts

See the Altera web site (http://www.altera.com) or the Altera Digital Library for pinout information. Figures 14 through 18 show the package pinout diagrams for MAX 3000A devices.

Figure 14. 44Pin PLCC/TQFP Package PinOut Diagram

Package outlines not drawn to scale.
INPUT/OE2/GCLK2 INPUT/OE2/GCLK2

INPUT/GCLRn

INPUT/GCLRn

INPUT/GCLK1

INPUT/GCLK1

INPUT/OE1

INPUT/OE1

GND

GND

VCC

VCC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Pin 1
39 38 37 36 35 I/O I/O/TDO I/O GND VCC I/O I/O I/O/TCK I/O GND I/O

Pin 34

6 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O GND 7 8 9 10 11 12 13 14 15 16 17

5 4

1 44 43 42 41 40 I/O/TDI I/O I/O GND I/O I/O I/O/TMS I/O VCC I/O GND I/O I/O/TDO I/O GND VCC

EPM3032A EPM3064A

34 33 32 31 30 29

EPM3032A EPM3064A

I/O I/O I/O/TCK I/O GND I/O

18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND

Pin 12

VCC

I/O

Pin 23

44-Pin PLCC

44-Pin TQFP

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 15. 100Pin TQFP Package PinOut Diagram

Package outline not drawn to scale.
Pin 1 Pin 76

EPM3064A EPM3128A

Pin 26

Pin 51

Figure 16. 144Pin TQFP Package PinOut Diagram

Package outline not drawn to scale.
Indicates location of Pin 1

Pin 1

Pin 109

EPM3128A EPM3256A

Pin 37

Pin 73

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 17. 208Pin PQFP Package PinOut Diagram

Package outline not drawn to scale.
Pin 1 Pin 157

EPM3256A EPM3512A

Pin 53

Pin 105

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MAX 3000A Programmable Logic Device Family Data Sheet

Figure 18. 256-Pin FineLine BGA Package Pin-Out Diagram

Package outline not drawn to scale.
A1 Ball Pad Corner

Indicates Location of Ball A1

A B C D E F G H

EPM3512A

J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Revision History

The information contained in the MAX 3000A Programmable Logic Device Data Sheet version 3.2 supersedes information published in previous versions. The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.2:

Version 3.2
Updated the EPM3512 ICC versus frequency graph in Figure 13.

Version 3.1
The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.1:

Updated timing information in Table 1 for the EPM3256A device. Updated Note (10) of Table 12.

Altera Corporation

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MAX 3000A Programmable Logic Device Family Data Sheet

Version 3.0
The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.0:

Added EPM3512A device. Updated Tables 2 and 3.

101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com

Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

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