Mahendra Engineering College

Mahendhirapuri

Department of ECE

EC1303 – Microprocessor and its applications

AIM
To learn the architecture, programming and interfacing of microprocessors and microcontrollers.

OBJECTIVES
• To introduce the architecture and programming of 8085 microprocessor.
• To introduce the interfacing of peripheral devices with 8085 microprocessor.
• To introduce the architecture and programming of 8086 microprocessor.
• To introduce the architecture, programming and interfacing of 8051 micro controller.

UNIT I 8085 CPU 9

8085 Architecture – Instruction set – Addressing modes – Timing diagrams – Assembly language
programming – Counters – Time Delays – Interrupts – Memory interfacing – Interfacing, I/O devices.

UNIT II PERIPHERALS INTERFACING 9

Interfacing Serial I/O (8251)- parallel I/O (8255) –Keyboard and Display controller (8279) – ADC/DAC
interfacing – Inter Integrated Circuits interfacing (I2C Standard)- Bus: RS232C-RS485-GPIB

UNIT III 8086 CPU 9

Intel 8086 Internal Architecture – 8086 Addressing modes- Instruction set- 8086 Assembly language
Programming–Interrupts.

UNIT IV 8051 MICROCONTROLLER 9

8051 Micro controller hardware- I/O pins, ports and circuits- External memory –Counters and Timers-Serial
Data I/O- Interrupts-Interfacing to external memory and 8255.

UNIT V 8051 PROGRAMMING AND APPLICATIONS 9

8051 instruction set – Addressing modes – Assembly language programming – I/O port programming -Timer
and counter programming – Serial Communication – Interrupt programming –8051 Interfacing: LCD, ADC,
Sensors, Stepper Motors, Keyboard and DAC.

TOTAL : 45
TEXT BOOKS

1. Ramesh S Gaonkar, Microprocessor Architecture, Programming and application with 8085, 4th Edition,
Penram International Publishing, New Delhi, 2000. (Unit I, II)
2. John Uffenbeck, The 80x86 Family, Design, Programming and Interfacing, Third Edition. Pearson
Education, 2002.
3. Mohammed Ali Mazidi and Janice Gillispie Mazidi, The 8051 Microcontroller and Embedded Systems,
Pearson Education Asia, New Delhi, 2003. (Unit IV, V)
UNIT I – INTEL 8085

1.1 INTRODUCTION TO MICROPROCESSOR BASED SYSTEM

The microprocessor is a semiconductor device (Integrated Circuit) manufactured by the VLSI (Very
Large Scale Integration) technique. It includes the ALU, register arrays and control circuit on a
single chip. To perform a function or useful task we have to form a system by using microprocessor
as a CPU and interfacing memory, input and output devices to it. A system designed using a
microprocessor as its CPU is called a microcomputer.

The Microprocessor based system (single board microcomputer) consists of microprocessor as

CPU, semiconductor memories like EPROM and RAM, input device, output device and interfacing
devices. The memories, input device, output device and interfacing devices are called peripherals.
The popular input devices are keyboard and floppy disk and the output devices are printer,
LED/LCD displays, CRT monitor, etc.

The above block diagram shows the organization of a microprocessor based system. In this system,
the microprocessor is the master and all other peripherals are slaves. The master controls all the
peripherals and initiates all operations.

The work done by the processor can be classified into the following three groups.
1. Work done internal to the processor
2. Work done external to the processor
3. Operations initiated by the slaves or peripherals.

The work done internal to the processors are addition, subtraction, logical operations, data transfer
operations, etc. The work done external to the processor are reading/writing the memory and
reading/writing the J/O devices or the peripherals. If the peripheral requires the attention of the
master then it can interrupt the master and initiate an operation.
The microprocessor is the master, which controls all the activities of the system. To perform a
specific job or task, the microprocessor has to execute a program stored in memory. The program
consists of a set of instructions. It issues address and control signals and fetches the instruction and
data from memory. The instruction is executed one by one internal to the processor and based on
the result it takes appropriate action.

BUSES:
The buses are group of lines that carries data, address or control signals.

• The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals.
The CPU interface is provided to demultiplex the multiplexed lines, to generate chip select
signals and additional control signals.

• The system bus has separate lines for each signal.

All the slaves in the system are connected to the same system bus. At any time instant
communication takes place between the master and one of the slaves. All the slaves have tri-
state logic and hence normally remain in high impedance state. Only when the slave is
selected it comes to the normal logic.

PERIPHERAL DEVICES:
• The EPROM memory is used to store permanent programs and data.
• The RAM memory is used to store temporary programs and data.
• The input device is used to enter the program, data and to operate the system.
• The output device is used for examining the results.
Since the speed of I/O devices does not match with the speed of microprocessor, an interface
device is provided between system bus and I/O devices. Generally I/O devices are slow
devices.

Advantages of Microprocessor based system

1. Computational/processing speed is high.
2. Intelligence has been brought to systems.
3. Automation of industrial processes and office administration.
4. Since the devices are programmable, there is flexibility to alter the system by changing the software
alone.
5. Less number of components, compact in size and cost less. Also it is more reliable.
6. Operation and maintenance are easier.

Disadvantages of Microprocessor based System

1. It has limitations on the size of data.
2. The applications are limited by the physical address space.
3. The analog signals cannot be processed directly and digitizing the analog signals introduces errors.
4. The speed of execution is slow and so real time applications are not possible.
5. Most of the microprocessors does not support floating point operations.
INTEL 8085 – Pin Diagram & Description

The INTEL 8085 is a 8-bit microprocessor.

It operates on 8-bit data and uses 16-bit address to access the memory.
With the help of 16-bit address, 8085 can access 216 = 65536 = 64K memory locations.
• It is a 40-pin DIP chip designed using NMOS.
• It operates with a power supply of +5 volts and GND.
• 8085 generates the clock signal internally by dividing the external supplied clock signal by
two.
INTEL 8085 ARCHITECTURE

The architecture of.8085 is shown in figure given below. The internal architecture of 8085 includes
the ALU, timing and control unit, instruction register and decoder, register array, interrupt control
and serial I/O control.

OPERATIONS PERFORMED BY 8085

The ALU performs the arithmetic and logical operations.
The operations performed by ALU of 8085 are addition, subtraction, increment, decrement,
logical AND, OR, EXCL U8IVE -OR, compare, complement and left / right shift. The
accumulator and temporary register are used to hold the data during an arithmetic / logical
operation. After an operation the result is stored in the accumulator and the flags are set or reset
according to the result of the operation.

FLAG REGISTER:
There are five flags in 8085, which are sign flag (8), zero flag (Z), auxiliary carry flag (AC),
parity flag (P) and carry flag (CY). The bit positions reserved for these flags in the flag register
are shown in figure below.
After an ALU operation, if the most significant bit of the result is 1, then sign flag is set. The zero
flag is set, if the ALU operation results in zero and it is reset if the result is non-zero. In an
arithmetic operation, when a carry is generated by the lower nibble, the auxiliary carry flag is set.
After an arithmetic or logical operation, if the result has an even number of 1 's the parity flag is set,
other wise it is reset.

If an arithmetic operation results in a carry, the carry flag is set other wise it is reset. Among the
five flags, the AC flag is used internally for BCD arithmetic and other four flags can be used by the
programmer to check the conditions of the result of an operation.

TIMING & CONTROL UNIT:

The timing and control unit synchronizes all the microprocessor operations with the clock and
generates the control signals necessary for communication between the microprocessor and
peripherals.

INSTRUCTION REGISTER & DECODER:

When an instruction is fetched from memory it is placed in instruction register. Then it is decoded
and encoded into various machine cycles.

REGISTER ARRAY:
• Apart from Accumulator (A-register), there are six general-purpose programmable registers
B, C, D, E, H and L.
• They can be used as 8-bit registers or paired to store l6-bit data. The allowed pairs are B-C,
D-E and H-L.
• The temporary registers W and Z are intended for internal use of the processor and it cannot
be used by the programmer.
• STACK POINTER (SP):
The stack pointer SP, holds the address of the stack top. The stack is a sequence of RAM
memory locations defined by the programmer. The stack is used to save the content of
registers during the execution of a program.
• PROGRAM COUNTER (PC):
The program counter (PC) keeps track of program execution. To execute a program the
starting address of the program is loaded in program counter. The PC sends out an address to
fetch a byte of instruction from memory and increment its content automatically. Hence,
when a byte of instruction is fetched, the PC holds the address of the next byte of the
instruction or next instruction.
INSTRUCTION EXECUTION AND DATA FLOW in 8085
The program instructions are stored in memory, which is an external device. To execute a program
in 8085, the starting address of the program should be loaded in program counter. The 8085 output
the content of program counter in address bus and asserts read control signal low. Also, the program
counter is incremented.

The address and the read control signal enable the memory to output the content of memory
location on the data bus. Now the content of data bus is the opcode of an instruction. The read
control signal is made high by timing and control unit after a specified time. At the rising edge of
read control signals, the opcode is latched into microprocessor internal bus and placed in instruction
register.

The instruction-decoding unit, decodes the instructions and provides information to timing and
control unit to take further actions.

INSTRUCTION FORMAT OF 8085

The 8085 have 74 basic instructions and 246 total instructions. The instruction set of 8085 is
defined by the manufacturer Intel Corporation. Each instruction of 8085 has 1 byte opcode. With 8
bit binary code, we can generate 256 different binary codes. In this, 246 codes have been used for
opcodes.

The size of 8085 instructions can be 1 byte, 2 bytes or 3 bytes.

• The 1-byte instruction has an opcode alone.
• The 2 bytes instruction has an opcode followed by an eight-bit address or data.
• The 3 bytes instruction has an opcode followed by 16 bit address or data. While storing the 3
bytes instruction in memory, the sequence of storage is, opcode first followed by low byte of
address or data and then high byte of address or data.
ADDRESSING MODES

Every instruction of a program has to operate on a data. The method of specifying the data to be
operated by the instruction is called Addressing. The 8085 has the following 5 different types of
addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

Immediate Addressing
In immediate addressing mode, the data is specified in the instruction itself. The data will be apart
of the program instruction. All instructions that have ‘I’ in their mnemonics are of Immediate
addressing type.
Eg. MVI B, 3EH - Move the data 3EH given in the instruction to B register.

Direct Addressing
In direct addressing mode, the address of the data is specified in the instruction. The data will be in
memory. In this addressing mode, the program instructions and data can be stored in different
memory blocks. This type of addressing can be identified by 16-bit address present in the
instruction.
Eg. LDA 1050H - Load the data available in memory location 1050H in accumulator.

Register Addressing
In register addressing mode, the instruction specifies the name of the register in which the data is
available. This type of addressing can be identified by register names (such as ‘A’, ‘B’, … ) in the
instruction.
Eg. MOV A, B -Move the content of B register to A register.

Register Indirect Addressing

In register indirect addressing mode, the instruction specifies the name of the register in which the
address of the data is available. Here the data will be in memory and the address will be in the
register pair. This type of addressing can be identified by letter ‘M’ present in the instruction.
Eg. MOV A, M - The memory data addressed by HL pair is moved to A register.

Implied Addressing
In implied addressing mode, the instruction itself specifies the type of operation and location of data
to be operated. This type of instruction does not have any address, register name, immediate data
specified along with it.
Eg. CMA - Complement the content of accumulator.
INSTRUCTION SET

The 8085 instruction set can be classified into the following five functional headings.

Group I - DATA TRANSFER INSTRUCTIONS:

Includes the instructions that moves ( copies) data between registers or between memory locations
and registers. In all data transfer operations the content of source register is not altered. Hence the
data transfer is copying operation.
Ex: i) MOV A,B ii) LDA 4600 iii) LHLD 4200

Group II - ARITHMETIC INSTRUCTIONS:

Includes the instructions which performs the addition, subtraction, increment or decrement
operations. The flag conditions are altered after execution of an instruction in this group.
Ex: i) ADD B ii) SUB C iii) INR D iv) INX H

Group III - LOGICAL INSTRUCTIONS:

The instructions which performs the logical operations like AND, OR, Exclusive-OR, complement,
compare and rotate instructions are grouped under this heading. The flag conditions are altered after
execution of an instruction in this group.
Ex: i) ORA B ii) XRA A iii) RAR

Group IV - BRANCHING INSTRUCTIONS:

The instructions that are used to transfer the program control from one memory location to another
memory location are grouped under this heading.
Ex: i) JZ 4200 ii) RST 7 iii) CALL 4300

Group V - MACHINE CONTROL INSTRUCTIONS:

Includes the instructions related to interrupts and the instruction used to halt program execution.
Ex: i) SIM ii) RIM iii) HLT

The 74 basic instructions of8085 are listed inTable-2.1. The opcode of each instruction, size,
machine cycles, number of T -state and the total number of instructions in each type are also shown
in table in next page. The instructions affecting the status flag are listed in table followed.
INTERRUPTS
NEED FOR INTERRUPTS
Interrupt is a signal send by an external device to the processor, to the processor to perform a
particular task or work. Mainly in the microprocessor based system the interrupts are used for data
transfer between the peripheral and the microprocessor.

When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate
signal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor
suspends its current activity and executes an interrupt service subroutine to complete the data
transfer between the peripheral and processor. After executing the interrupt service routine the
processor resumes its current activity. This type of data transfer scheme is called interrupt driven
data transfer scheme.

TYPES OF INTERRUPTS
The interrupts are classified into software interrupts and hardware interrupts.

• The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, lf a software interrupt instruction is
encountered, then the processor executes an interrupt service routine (ISR).

• The hardware interrupts are initiated by an external device by placing an appropriate

signal at the interrupt pin of the processor. If the interrupt is accepted, then the processor
executes an interrupt service routine (ISR).

SOFTWARE INTERRUPTS OF 8085

The software interrupts are program instructions. When the instruction is executed, the processor
executes an interrupt service routine stored in the vector address of the software interrupt
instruction. The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST
6 and RST 7.

The vector addresses of

software interrupts are
given in table below.
The software interrupt instructions are included at the appropriate (or required) place in the main
program. When the processor encounters the software instruction, it pushes the content of PC
(Program Counter) to stack. Then loads the Vector address in PC and starts executing the Interrupt
Service Routine (ISR) stored in this vector address. At the end of ISR, a return instruction - RET
will be placed. When the RET instruction is executed, the processor POP the content of stack to PC.
Hence the processor control returns to the main program after servicing the interrupt. Execution of
ISR is referred to as servicing of interrupt.

All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be masked
and they cannot be disabled.

The software interrupts are RST0, RST1, … RST7 (8 Nos).

HARDWARE INTERRUPTS OF 8085

An external device, initiates the hardware interrupts of 8O85 by placing an appropriate signal at the
interrupt pin of the processor. The processor keeps on checking the interrupt pins at the second T
-state of last machine cycle of every instruction. If the processor finds a valid interrupt signal and if
the interrupt is unmasked and enabled, then the processor accepts the interrupt. The acceptance of
the interrupt is acknowledged by sending an INTA signal to the interrupted device.

The processor saves the content of PC (program Counter) in stack and then loads the vector address
of the interrupt in PC. (If the interrupt is non-vectored, then the interrupting device has to supply the
address of ISR when it receives INTA signal). It starts executing ISR in this address. At the end of
ISR, a return instruction, RET will be placed. When the processor executes the RET instruction, it
POP the content of top of stack to PC. Thus the processor control returns to main program after
servicing interrupt.

The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

Further the interrupts may be classified into VECTORED and NON-VECTORED INTERRUPTS.

VECTORED INTERRUPT
In vectored interrupts, the processor automatically branches to the specific address in response to an
interrupt.

NON-VECTORED INTERRUPT
But in non-vectored interrupts the interrupted device should give the address of the interrupt service
routine (ISR).

In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control
is to be transferred. The vector addresses of hardware interrupts are given in table above in
previous page.
The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to
supply the address of ISR after receiving interrupt acknowledge signal.

The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085 are
defined by INTEL.

The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to
make a low to high transition and then it has to remain high until the interrupt is recognized.
The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt signal
has to make a low to high transition an it need not remain high until it is recognized.
The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the
interrupting signal should remain high, until it is recognized.

MASKABLE & NON-MASKABLE INETRRUPTS:

The hardware vectored interrupts are classified into maskable and non-maskable interrupts.

• TRAP is non-maskable interrupt

• RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt.

Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked
the processor will not accept the interrupt signal. The interrupts can be masked by moving an
appropriate data (or code) to accumulator and then executing SIM instruction. (SIM - Set Interrupt
Mask). The status of maskable interrupts can be read into accumulator by executing RIM instruction
(RIM - Read Interrupt Mask).

All the hardware interrupts, except TRAP are disabled, when the processor is resetted. They can
also be disabled by executing Dl instruction. (Dl-Disable Interrupt).

• When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5,
RST 6.5 and RST 7.5 are disabled by DI instruction and upon hardware reset).
• To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-
Enable Interrupt).
INTERRUPT DRIVEN DATA TRANSFER SCHEME

The interrupt driven data transfer scheme is the best method of data transfer for effectively utilizing
the processor time. In this scheme, the processor first initiates the I/O device for data transfer. After
initiating the device, the processor will continue the execution of instructions in the program. Also
at the end of an instruction the processor will check for a valid interrupt signal. If there is no
interrupt then the processor will continue the execution.

When the I/O device is ready, it will interrupt the processor. On receiving an interrupt signal, the
processor will complete the current instruction execution and saves the processor status in stack.
Then the processor calls an interrupt service routine (ISR) to service the interrupted device. At the
end of ISR the processor status is retrieved from stack and the processor starts executing its main
program. The sequence of operations for an interrupt driven data transfer scheme is shown in figure
below.
TIMING DIAGRAM for various machine cycles

The machine cycles are the basic operations performed by the processor, while instructions
are executed. The time taken for performing each machine cycle is expressed in terms of T-
states.

One T-state is the time period of one clock cycle of the microprocessor.

The various machine cycles are

1. Opcode fetch …………….. - 4/6T
2. Memory Read ……………. - 3T
3. Memory Write ……………. - 3T
4. I/O Read ………………….. - 3T
5. I/O Write …………………. - 3T
6. Interrupt Acknowledge …… - 6 / 12 T
7. Bus Idle …………………… - 2/3T
DELAY ROUTINE

Delay routines are subroutines used for maintaining the timings of various operations in
microprocessor.

In control applications, certain equipment needs to be ON/OFF after a specified time delay. In some
applications, a certain operation has to be repeated after a specified time interval. In such cases,
simple time delay routines can be used to maintain the timings of the operations.

DELAY ROUTINE PROCESS

A delay routine is generally written as a subroutine (It need not be a subroutine always. It can be
even a part of main program). In delay routine a count (number) is loaded in a register of
microprocessor. Then it is decremented by one and the zero flag is checked to verify whether the
content of register is zero or not. This process is continued until the content of register is zero.
When it is zero, the time delay is over and the control is transferred to main program to carry out
the desired operation.

The delay time is given by the total time taken to execute the delay routine. It can be computed by
multiplying the total number of T-states required to execute subroutine and the time for one T-state
of the processor. The total number of T-states can be computed from the knowledge of T-states
required for each instruction. The time for one T-state of the processor is given by the inverse of the
internal clock frequency of the processor.

For example, if the 8085 microprocessor has 5 MHz quartz crystal then,

The internal clock frequency = 5 / 2 = 2.5 MHz

Time for one T-state= 1 / 2.5 x 106 = 0.4µsec

• For small time delays (< 0.5 msec) an 8- bit register can be used.
• For large time delays (< 0.5 Sec) l6-bit register should be used.
• For very large time delays (> 0.5 sec), a delay routine can be repeatedly called in the main
program.

The disadvantage in delay routines is that the processor time is wasted. An alternate solution is to
use dedicated timer like 8253/8254 to produce time delays or to maintain timings of various
operations.

Two example delay routines are presented in this section with details of timing calculations.
EXAMPLE DELAY ROUTINE -1
Write a delay routine to produce a time delay of 0.5 msec in 8085 processor-based system whose
clock source is 6 MHz quartz crystal.

Solution
The delay required is 0.5 msec, hence an 8-bit register of8085 can be used to store a Count value
and then decrement to zero. The delay routine is written as a subroutine as shown below.

Delay routine
MVI D, N ; Load the count value, N in D-register.
Loop: DCR D ; Decrement the count.
JNZ Loop ; If count is zero go to
RET ; Return to main program.
The following table shows the T-state required for execution of the instructions in the subroutine.
T-State required for
Number of times the
Instruction execution of an Total T-States
instruction is executed
instruction
CALL addr16 18 1 18 x 1 = 18
MVI D, N 7 1 7x1=7
DCR D 4 N times 4 x N = 4N
JNZ LOOP 10 (or) (N-1) times 10 x (N-1) = 10N - 10
7 1 7x1=7
RET 10 1 10 x 1 = 10
TOTAL T-STATES FOR DELAY SUBROUTINE 14N + 32

Calculation to find the count value, N:

External clock frequency = 6 Mhz

Internal clock frequency = External Frequency / 2

=6/2
= 3 Mhz

Time period for 1 T-State = 1 / Internal clock frequency

= 1 / 3x106
= 0.333µS

No. of T-states required

for delay of 0.5mS = Required time delay / Time for one T-state
= 0.5mS / 0.333µS
= 1500.10
≈ 1500 = 150010

From above table, we know that;

14N + 32 = 1500
N = (1500 – 32) / 14 = 104.85710 ≈ 10510 = 69H
Therefore by replacing the count value, N by 69H in the above program , a delay of 0.5mSec can
be produced.
PROGRAMMING EXAMPLES:

1. Write an ALP using 8085 to multiply two 8-bit numbers by repeated addition.

MVI A, OO ; Accumulator contents are cleared

MVI C, OO ; C Register contents are cleared
MVI B, data#1 ; I Operand is loaded into B Register
MVI D, data#2 ; II Operand is loaded into D Register

Loop: ADD B |
JNC next |
INR C } Multiplication by repeated addition.
Next: DCR D |
JNZ loop |

STA 4200H ; Storing of results into memory location

MOV A,C
STA 4201H ; Storing of carry into next memory location

2. Write an ALP for 8085 to count from AAH to 00H, with a time delay of 2ms for each
count. Assume the external frequency given to the processor is 2MHz.

Internal Frequency in 8085 = External frequency / 2

ie., = 2Mhz / 2
= 1Mhz

1 T-State = 1 / f (internal frequency)

= 1µ S

Main program for counting from AA to 00

MVI C, AAH
Loop: CALL Delay
DCR C
JNZ Loop
HLT

Delay program for delay of 2ms

Delay: MVI D, 4AH
Next: NOP
NOP
NOP
NOP
DCR D
JNZ Next
RET
3. Write an ALP using 8085 to evaluate the expression C=A2+B2

Let ‘A’ be Data#1 and ‘B’ be Data#2

MVI B, Data#1 ; Data #1 is stored in register B

MOV C, B ; Copy of Data #1 is made in register C
MVI D, Data#2 ; Data #2 is stored in register D
MOV E,D ; Copy of Data #2 is made in register E

XRA A ; Accumulator content is cleared

Again: ADD B ]
DCR C } A2 is calculated by repeated Addition
JNZ Again ]

MOV H,A ; Calculated A2 value is stored in register H

XRA A ; Accumulator content is cleared

Loop: ADD D ]
DCR E } B2 is calculated by repeated Addition
JNZ Loop ]

ADD H ; A2+ B2 is determined,

by adding result in A
and register content H

STA 4200H ; Result is stored in memory location 4200H

INTERFACING EXAMPLES:

Draw the circuit diagram of an 8085 system, having a 4 KB EPROM and two 8 KB RAM ICs.
The starting address of the EPROM is 0000H and that of RAM is 8000H. The address of the
decoder circuits should be clearly shown.

Answer :
EPROM - 4 KB (Address lines required is 12 – A0 to A11 )
RAM-I - 8 KB (Address lines required is 13 – A0 to A12 )
RAM-II - 8 KB (Address lines required is 13 – A0 to A12 )

Mapping of Addresses to Memory Ics

Binary Address Hex

ICs Addres
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 s
0 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0000
EPRO 0 0 x x 0 0 0 0 0 0 0 0 0 0 0 1 0001
M . . . . . . . . . . . . . . . . .
4 KB . . . . . . . . . . . . . . . . .
0 0 x x 1 1 1 1 1 1 1 1 1 1 1 1 0FFF
0 1 x 0 0 0 0 0 0 0 0 0 0 0 0 0 4000
0 1 x 0 0 0 0 0 0 0 0 0 0 0 0 1 4001
RAM-I
. . . . . . . . . . . . . . . . .
8 KB
. . . . . . . . . . . . . . . . .
0 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 5FFF
1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 8000
1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 8001
RAM-II
. . . . . . . . . . . . . . . . .
8 KB
. . . . . . . . . . . . . . . . .
1 0 x 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFF
Part A:

1. State the function of HOLD and HLDA pins in 8085.

The HOLD and HLDA pins in 8085 are used in interfacing the 8257-DMA controller IC
with the processor.
A signal is sent by 8257 to HOLD pin in µ P, to request the µ P to stop its current process
and allocate the buses for DMA data transfer.
µ P acknowledges the request for DMA data transfer by 8257, by sending a signal in HLDA
to 8257.

2. Distinguish I/O mapped I/O and memory mapped I/O.

Mapping is the process by which the addresses are allocated to the I/O devices.
The two kinds of mapping are
a) Memory mapped I/O
b) I/O mapped I/O

S.No Memory mapped I/O I/O mapped I/O

16 bit address is given to each I/O 8 bit address is given to each I/O
1
device device
Each I/O device is treated like a
All I/O devices are accessed using
memory location and they are
2 only two instructions viz., IN and
accessed using instructions related to
OUT.
memory operations.
Data can be transferred between I/O Data can be transferred only between
3
devices and all registers in µ P. I/O devices and accumulator in µ P.
This scheme is used in system, where
This scheme is used in system, where
4 complete memory capacity is
memory requirement is small.
required.
Only Memory Read & Write machine Only I/O Read & Write machine
5 cycles are involved during data cycles are involved during data
transfer with I/O devices. transfer with I/O devices.
Only maximum of 256(=28 ) I/O
Large number of I/O devices can be
6 devices can be connected in this
connected in this scheme.
scheme.

3. Explain the execution of the instruction CMA instruction in 8085.

CMA instruction is used to perform 1’s complement of the contents of Accumulator in 8085.
 4. What is the function performed by SIM and RIM instruction.
SIM Instruction:
The SIM instruction is used to mask the hardware interrupts RST7.5, RST6.5 and RST5.5. It
is also used to send data through SOD line.

RIM Instruction:
The RIM instruction is used to check whether an interrupt (RST7.5, RST6.5 and RST5.5) is
masked or not. It is also used to read data from SID line.

5. What will be the outcome, in execution of instructions LXI H,4600H and LHLD 4600H?
When LXI H,4600 is executed, the number 4600 will be loaded to HL register pair.
When LHLD 4600 is executed, the contents of memory location 4600H will be transferred to
HL register pair.

6. Explain the concept of demultiplexing AD0-7 lines in 8085?

Demultiplexing is the process of separating the low byte address A0-7 and 8-bit data D0-7
from AD0-7 lines of 8085, using a latch and Address latch enable (ALE) signal.

D0-7

µ P AD0-7 74LS373
8085 Latch A0-7

EN
ALE

When low byte address (A0-7 ) comes out of AD0-7 lines, the processor asserts HIGH in the
ALE pin, enabling the latch to separate the low byte address.
7. Compare System bus and CPU bus.
Bus is a set of conducting wires in a microprocessor based system, which helps to carry
various information like DATA, ADDRESS and other CONTROL

Bus
System Bus CPU Bus
Internal External It will not be
It will be directly
directly connected
connected to CPU
to CPU
There will be
The data and
separate data,
CPU bus System Bus address may be
address & control
multiplexed
buses

8. State the significance of X1 and X2 pins of 8085.

The clock signal is supplied to the microprocessor 8085 by connecting quartz crystal
through the pins X1 and X2.
Quartz
X1
Crystal
µ P
808
5
X2

9. What is Processor (machine) cycle? List the various machine cycles with its T-states.
The machine cycles are the basic operations performed by the processor, while instructions
are executed. The time taken for performing each machine cycle is expressed in terms of T-
states.

The various machine cycles are

1. Opcode fetch …………….. - 4/6T
2. Memory Read ……………. - 3T
3. Memory Write ……………. - 3T
4. I/O Read ………………….. - 3T
5. I/O Write …………………. - 3T
6. Interrupt Acknowledge …… - 6 / 12 T
7. Bus Idle …………………… - 2/3T
10. List the various addressing modes in 8085 with two examples in each.

Addressing is the method of specifying the location of data in an instruction.

The different types of addressing modes in 8085 are

a) Direct:
The data is stored in memory and 16 bit address of data in memory location is specified
in the instruction.
Eg.: LDA 4500, LHLD 4200

b) Immediate:
The required data for processing is given next to the Opcode, in the instruction itself.
Eg.: MVI A, 55 CPI 64, ADI 0A

c) Register:
The data is placed in a register and the register name is given in the instruction to access
the data.
Eg.: MOV A,B ADD B, SUB C

d) Register Indirect:
The data is stored in memory and the 16-bit address of the data location in memory is
placed in a register pair. This register pair holding the 16-bit address is given in the
instruction to access the data.
Eg.: LXI, H 4250
MOV A, M

e) Implied:
The data location & the operation to be performed is given in the instruction itself.
Eg.: CMA, RAR, XCHG

11. Define stack and stack pointer.

Stack:
A small portion of the RAM memory is declared as stack and it is used for temporary
storage of the register contents, using instructions like PUSH and POP.
The contents are stored and retrieved in LIFO (Last In First Out) form.

Stack Pointer:
It is a 16-bit memory pointing register, having the last address of the stack in RAM.
12. Compare CALL and JMP instructions.
CALL Instruction:
Execution of a CALL instruction will transfer the program control from existing program to
another program. ie., Sub program specified by the 16-bit address in CALL instruction will
be executed. The called program should have RET – return instruction as its last instruction.
Time taken for its execution is 9 / 18 T
Main _________ addr16: _________
_________ _________
_________ _________
_________
CALL addr16 _________
_________ _________
_________ RET
_________

JMP Instruction
Execution of a JMP instruction will transfer the program control from one location to
another location within the same program. Time taken for its execution is 7 / 10 T
Main _________
_________
_________

JMP addr16
_________
_________
addr16:_________
_________

13. What is an interrupt and list the various interrupts in 8085.

Interrupt:
Interrupt is a signal send by an external device to the processor (or special instruction
executed in a program), to stop the execution of the current process in the microprocessor
and perform a particular task (ie., data transfer) to the called device.

Various HARDWARE interrupts are TRAP, RST7.5, RST6.5, RST5.5, INTR (5 Nos)

Various SOFTWARE interrupts are RST0, RST1, RST2 …… RST7 (8 Nos)

14. Explain the function of IN and OUT instructions.
Execution of an IN instruction will transfer one byte of data from an Input device to
Accumulator of microprocessor.

Execution of an OUT instruction will transfer one byte of data from Accumulator of
microprocessor to an Output device.

15. Write an ALP for time delay using a register pair available in 8085.
Main _________ Delay: LXI D, data16
_________ loop: NOP
_________ NOP
NOP
CALL Delay DCX D
_________ JNZ loop
_________ RET

The register pair used is DE.

The total time delay made is as follows.
One T-state = 1 / Finternal
T – states (in execution of one loop) = 4T + 4T + 4T + 4T + 7T = 23T
Total T-states = 23T x data16 (stored in DE register pair)

16. Write
an assembly language program to store the contents of the flag register in
memory location 2000H.
PUSH PSW - Stores the contents of Accumulator & Flag register in Stack
POP D - Restores the stored contents of stack to DE register pair
MOV A, E - Move the contents of E register to Accumulator
STA 2000H - Contents of Accumulator is now stored to memory location 2000H

17. Explain the Instruction format of 8085.

The 8085 have 74 basic instructions. The
size of 8085 instructions can be 1 byte, 2
bytes or 3bytes.
1 Byte instruction has Opcode alone.
2 Bytes instructions have 1 byte
Opcode followed by 8 bit data.
3 Bytes instruction have 1 byte
Opcode followed by 16 bit data.
18. Draw and label the flags in flag register of 8085.