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    Some Layout Design Tips: Amir M. Sodagar

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    The document provides layout design tips for transistors, inverters, and other digital circuits. It includes tips for compact layout, standard cell design, routing metal layers, pad frames, and floorplanning. General layout tools like DRC and circuit extraction are also discussed. Diagrams illustrate transistor layout, optimized inverter designs, routing strategies, and pad frame examples.

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    Some Layout Design Tips: Amir M. Sodagar

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    api-3804613
    33 views25 pages
    The document provides layout design tips for transistors, inverters, and other digital circuits. It includes tips for compact layout, standard cell design, routing metal layers, pad frames, and floorplanning. General layout tools like DRC and circuit extraction are also discussed. Diagrams illustrate transistor layout, optimized inverter designs, routing strategies, and pad frame examples.

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    Set 3

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    The document provides layout design tips for transistors, inverters, and other digital circuits. It includes tips for compact layout, standard cell design, routing metal layers, pad frames, and floorplanning. General layout tools like DRC and circuit extraction are also discussed. Diagrams illustrate transistor layout, optimized inverter designs, routing strategies, and pad frame examples.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    33 views25 pages

    Some Layout Design Tips: Amir M. Sodagar

    Uploaded by

    api-3804613
    The document provides layout design tips for transistors, inverters, and other digital circuits. It includes tips for compact layout, standard cell design, routing metal layers, pad frames, and floorplanning. General layout tools like DRC and circuit extraction are also discussed. Diagrams illustrate transistor layout, optimized inverter designs, routing strategies, and pad frame examples.

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    Some Layout Design Tips

    Amir M. Sodagar
    Spring 2003

    K.N.Toosi University of
    Amir M. Sodagar Technology ١
    Some layout design tips
    ‰ Layout of an NMOS transistor
    Metal 1
    N-Select

    Active Area
    Poly Contact Poly

    Active Contact

    Amir M. Sodagar K.N.Toosi University of Technology ٢


    Some layout design tips
    ‰ Layout of a PMOS transistor
    Metal 1
    P-Select
    N-Well
    Active Area
    Poly Contact Poly

    Active Contact

    Amir M. Sodagar K.N.Toosi University of Technology ٣


    Some layout design tips
    ‰ Substrate &
    N-Well N-Well
    Vdd
    Connections

    Vdd N-Select
    (N-Well tied to Gnd)

    P-Select
    (Substrate
    tied to Gnd)

    Gnd
    Amir M. Sodagar K.N.Toosi University of Technology ٤
    Some layout design tips
    ‰ Compact Layout For
    A CMOS Inverter
    N-Well Contact to Vdd Metal 1

    N-Well
    Active Contact

    P-Select Active
    N-Well
    Vdd

    N-Select

    (N-Well tied to Gnd)

    N-Select
    P-Select

    (Substrate tied to Gnd)

    Gnd

    Amir M. Sodagar K.N.Toosi University of Technology ٥


    Some layout design tips
    ‰ Inverter

    N-Well
    Vdd

    N-Select

    (N-Well tied to Gnd)

    P-Select

    Gnd

    Not Optimized Not Optimized Optimized

    Amir M. Sodagar K.N.Toosi University of Technology ٦


    Some layout design tips
    ‰ 2-input NAND

    Not Optimized Optimized


    Amir M. Sodagar K.N.Toosi University of Technology ٧
    Some layout design tips
    ‰ How to route Metal1 & Metal2

    Amir M. Sodagar K.N.Toosi University of Technology ٨


    Some layout design tips
    ‰ Two standard cells:

    NAND2C NOR3C
    Amir M. Sodagar K.N.Toosi University of Technology ٩
    Some layout design tips
    ‰ A row of several standard cells

    Amir M. Sodagar K.N.Toosi University of Technology ١٠


    Some layout design tips
    ‰ Core

    Amir M. Sodagar K.N.Toosi University of Technology ١١


    Some layout design tips
    ‰ Pad frame

    Amir M. Sodagar K.N.Toosi University of Technology ١٢


    Some layout design tips
    ‰ Pad frame along with the name of each pad

    Amir M. Sodagar K.N.Toosi University of Technology ١٣


    Some layout design tips
    ‰ A pad-limited design

    Amir M. Sodagar K.N.Toosi University of Technology ١٤


    Some layout design tips
    ‰ A core-limited design

    Amir M. Sodagar K.N.Toosi University of Technology ١٥


    Some layout design tips
    ‰ Different arrangements of pads leads to
    different chip area occupations

    ¾ Two 16-pad frames

    Amir M. Sodagar K.N.Toosi University of Technology ١٦


    Some layout design tips
    ‰ Additional pads may be
    o Connected to some test points
    o Connected to some test devices
    o Left unconnected

    Amir M. Sodagar K.N.Toosi University of Technology ١٧


    Some layout design tips
    ‰ General tools for layout design:
    ¾ DRC: Design Rule Check
    o Checks the correctness of layout in terms of layout
    design rules

    ¾ Circuit Extraction
    o Generates a circuit netlist according to the layout,
    which can be used for post-layout simulation, in
    order
    ƒ to ensure the designer about the correctness of the whole
    circuit and also
    ƒ to take parasitic resistances and capacitances caused by
    interconnections into account.

    Amir M. Sodagar K.N.Toosi University of Technology ١٨


    Some layout design tips
    ‰ General tools for layout design:
    ¾ Auto Placement & Routing
    o Automatically generates a layout for a (usually) digital
    circuit using standard cells or blocks based on a gate-
    level circuit description.

    ¾ LVS: Layout vs. Schematic


    o Compares the layout with a gate-level circuit
    description in order to ensure the designer about the
    correctness of the generated layout, and id especially
    useful for very large digital systems.

    Amir M. Sodagar K.N.Toosi University of Technology ١٩


    Some layout design tips
    ‰ Floorplanning

    ROM
    RAM

    Input/
    Address, Data, & Control Buses
    Output
    Control Unit
    Main
    Control Unit
    Other
    Circuitry

    Amir M. Sodagar K.N.Toosi University of Technology ٢٠


    Some layout design tips
    ‰ Floorplanning
    Timing
    Counter/Timer
    Comparator

    Data Select
    Logic Count
    Decoder

    Parity PLA
    Check Buffers

    Programmable
    Logic Array
    Data
    Register

    Amir M. Sodagar K.N.Toosi University of Technology ٢١


    Additional Slides

    Amir M. Sodagar K.N.Toosi University of Technology ٢٢


    Bipolar Layout
    ‰ Bipolar Transistor in a Planar Technology

    n+ diff. (Emitter)

    E
    p diff. (Base)

    B n epi. (Collector)

    Contact
    C

    Amir M. Sodagar K.N.Toosi University of Technology ٢٣


    Bipolar Layout
    ‰ Bipolar Transistor in a Planar Technology
    ¾ Design for improved β

    n+ diff. (Emitter)

    E p diff. (Base)

    B n epi. (Collector)

    Contact
    C

    Amir M. Sodagar K.N.Toosi University of Technology ٢٤


    Bipolar Layout
    ‰ Bipolar Transistor in a Planar Technology
    ¾ Interdigitated Structure

    n+ diff. (Emitter)
    B

    p diff. (Base)

    n epi. (Collector)

    Contact

    Amir M. Sodagar K.N.Toosi University of Technology ٢٥

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