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Fpga With ps2 Keyboard

The document describes a module that receives serial data input on each clock cycle, shifts the data into a register, and outputs the final registered data along with a parity bit. It uses counters to track the clock cycles and shift in the bits. When the shift is complete it sets flags to output the data and reset for the next input.

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Leslie Wright
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
193 views

Fpga With ps2 Keyboard

The document describes a module that receives serial data input on each clock cycle, shifts the data into a register, and outputs the final registered data along with a parity bit. It uses counters to track the clock cycles and shift in the bits. When the shift is complete it sets flags to output the data and reset for the next input.

Uploaded by

Leslie Wright
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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module ps2(output reg [7:0]data_out,output reg parity,input data_in,input clk);

reg start,stop;
reg [7:0] data_shift;
reg[3:0] data_count='b0;
reg enable;

always@(enable==1)data_out=data_shift;


always @(negedge clk)
begin
if(data_count<10)
data_count=data_count+1;
else
data_count=0;
end
always@(negedge clk)
if(data_count==0)
begin
start='b0;
stop='b0;
enable='b0;
end

else if(data_count<9)
begin
data_shift<={data_in,data_shift[7:1]};

// else if(data_count<10)
// begin
// data_shift[7]<=data_in;
// data_shift[6]<=data_shift[7];
// data_shift[5]<=data_shift[6];
// data_shift[4]<=data_shift[5];
// data_shift[3]<=data_shift[4];
// data_shift[2]<=data_shift[3];
// data_shift[1]<=data_shift[2];
// data_shift[0]<=data_shift[1];
end

else if(data_count==9)
begin
parity=^~(data_shift);
end

else if(data_count==10)
begin
start='b1;
stop='b1;
enable='b1;
end

else if
begin
data_shift='b0;
end
endmodule
//
//
//
//
//
//
//
//
//
//
//
//

//module ps2(
//input wire clk, // Clock pin form keyboard
//input wire data, //Data pin form keyboard
//output reg [7:0] led //Printing input data to led
//);
// reg [7:0] data_curr;
// reg [7:0] data_pre;
// reg [3:0] b;
// reg flag;
//
//initial
//begin
//b<=4'h1;
//flag<=1'b0;
//data_curr<=8'hf0;
//data_pre<=8'hf0;
//led<=8'hf0;
//end
//
//always @(negedge clk) //Activating at negative edge of clock from keyboard
//begin
//
//case(b)
//1:; //first bit
//2:data_curr[0]<=data;
//3:data_curr[1]<=data;
//4:data_curr[2]<=data;
//5:data_curr[3]<=data;
//6:data_curr[4]<=data;
//7:data_curr[5]<=data;
//8:data_curr[6]<=data;
//9:data_curr[7]<=data;
//10:flag<=1'b1; //Parity bit
//11:flag<=1'b0; //Ending bit
//
//endcase
// if(b<=10)
// b<=b+1;
//
// else if(b==11)
// b<=1;
//
//
//end
//
//always@(posedge flag) // Printing data obtained to led
//begin
//
// if(data_curr==8'hf0)
// led<=data_pre;
// else
// data_pre<=data_curr;
//end endmodule

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