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How To Use SHRB in Simatic Step 7

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Shift Functions

3.2

Bit Shift Register (SHRB): FC92

Description

The Bit Shift Register (SHRB) function shifts a bit into a shift register from
the indicated source in DATA. New data is read from the source each time
the instruction is executed, and this data is shifted into the shift register
starting location (S_BIT) while the RESET input has a signal state of 0. All
successive bits are shifted by one. The bit contained in the last location
(S_BIT+N) is lost after the shift. Whenever the RESET input is set to 1, the
locations in the table are set to 0 rather than being shifted.

Parameters

Table 3-2 describes the Bit Shift Register (SHRB) parameters.

Table 3-2 Bit Shift Register (FC92) Parameters


Parameter

Declaration

Data Type

Memory Area

Description

EN

Input

BOOL

I, Q, M, D, L

Enable input with signal state of 1 activates the box

ENO

Output

BOOL

I, Q, M, D, L

Enable output has a signal state of 1 if the function


is executed without error

DATA

Input

BOOL

I, Q, M, D, L

Source data bit

RESET

Input

BOOL

I, Q, M, D, L

Resets the shift register when set to 1

S_BIT

Input

Pointer*

I, Q, M, D

Points to the starting bit in the shift register

Input

WORD

I, Q, M, D, L, P

Length of the shift register (number of bits to be


shifted)

* Double word pointer format for area-crossing register indirect addressing

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Standard Software for S7-300 and S7-400 Standard Functions Part 2


A5E00066867-03

Shift Functions

Error Information

This function does not detect any error conditions.

Example

Figure 3-2 shows how the SHRB instruction works. If the signal state of input
I 0.0 is 1 (activated) the SHRB function is executed. The N parameter in this
example is set to 14 (E in hexadecimal notation), indicating that 14 bit
locations will be shifted, starting with the first bit at the S_BIT pointer
location. After the bits are shifted, the first location is filled with the data
indicated by the input DATA. The very last bit value is lost.
If the function is executed without error, the signal states of ENO and Q4.0
are set to 1.

SHRB
FC92
EN
ENO

I 0.0
0

DATA

RESET

P#DB1.DBX1.4
B#16#0E

Q 4.0

S_BIT
N

Before shifting:
S_BIT

After shifting:
S_BIT

1.0
1.7
0 0 1 1 1 0 1 0

1.0
1.7
0 1 1 0 1 0 1 0

2.7
2.0
0 0 1 1 1 0 1 0

2.7
2.0
0 1 1 1 0 1 0 0

3.0
3.7
0 0 1 1 1 0 1 0

3.0
3.7
0 0 1 1 1 0 0 0

Figure 3-2

Bit Shift Register (SHRB)

Standard Software for S7-300 and S7-400 Standard Functions Part 2


A5E00066867-03

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