Proceedings of ICALEPCS2011, Grenoble, France

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FLOATING-POINT-BASED HARDWARE ACCELATOR OF A BEAM

PHASE-MAGNITUDE DETECTOR AND FILTER FOR A BEAM PHASE
CONTROL SYSTEM IN A HEAVY-ION SYNCHROTRON APPLICATION
Faizal Arya Samman, Pongyupinpanich Surapong, Christopher Spies and Manfred Glesner
FG Mikroelektronische Systeme, Technische Universitat Darmstadt, Darmstadt, Germany
performed in a fixed-point implementation to accomodate
Abstract

INTRODUCTION
In a synchrotron, different modes of coherent longitudinal beam oscillations may occur due to an initial mismatch
or to non-linearities such as wake fields. These oscillations are characterized by their mode number m and n [4]
and take place at the characteristic synchrotron frequency,
which depends on the system state (more precisely, on the
magnetic flux derivative, accelerating voltage, and particle
energy). In order to eliminate undesired dipole oscillations,
a beam phase control system [5] has been devised, which
was initially designed to deal with in-phase dipole oscillations (m = 1, n = 0) only [5]. The addition of amplitude detectors is intended to make it suitable for damping
higher-order modes [4, 6].
This paper presents a new floating-point based architecture designed to improve both the precision and processing
speed of the digital controller over previous implementations [2, 11]. The floating-point arithmetic units are used
to overcome issues with explosive divergence and stalling
effects caused by fixed-point implementations [8]. Such
problems may arise due to input or output signal saturation caused by changes in the dynamic signal range at runtime. Using a floating-point representation eliminates the
need for input and output scaling that would have to be
The

work is supported by German Federal Ministry of Education and

Research in the frame of Project FAIR (Facility for Antiproton and Ion
Research), Grant Number 06DA9028I.

Hardware

these changes. A floating-point implementation can also be

adapted to different dynamic range requirements of other
control applications and is therefore more suitable for an
integrated circuit implementation (ASIC).
In the following section, the digital signal processing
chain of the beam phase control is presented. Its core components are phase and magnitude detectors and adaptive filter blocks, which are discussed in the subsequent sections.

BEAM PHASE CONTROL

BPM
fref
ugap

BPi

A
D

Analog
Pre
processing
A
D

GVi

COR MB
DIC
PB

PA
COR
DIC

Band
pass
Filter

Inte
grator

Band
pass
Filter

Ampli
fier

D
A

Figure 1: Block Diagram of the Beam Phase Signal Processing.

The signal processing pipeline implemented in the DSP
system is shown in Fig. 1. It performs the following steps:
1. Some analog preprocessing is performed on both the
gap voltage and the beam position signal [3]. Note
that the beam position signal is quite noisy and has a
high level of uncertainty since the bunch may have an
arbitrary shape.
2. Four successive samples are used to form the in-phase
and quadrature components of both signals.
3. The phase of both signals is computed using Alg. 3.
4. The phase difference is fed into a programmable FIR
filter in order to eliminate noise and other disturbances
in the phase difference. The filter is tuned to a frequency slightly above [5] the synchrotron frequency
and has to be re-tuned continuously since this frequency changes.
5. The output of the filter is fed into a variable-gain controller whose gain also depends on the characteristic
frequency. This controller yields a frequency correction which is then applied to the cavity in order to intentionally mistune it, thereby pulling the bunch back
to its desired position.
BP M is the signal from the beam position monitor. ugap
is the voltage across the gap of the reference cavity. fref is
the reference frequency (see [3]). Future extensions [6] are

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Copyright

A hardware implementation of an adaptive phase and

magnitude detector and filter of a beam-phase control system in a heavy ion synchrotron application is presented in
this paper. The main components of the hardware are adaptive LMS filters and phase and magnitude detectors. The
phase detectors are implemented by using a CORDIC algorithm based on 32-bit binary floating-point arithmetic data
formats. The floating-point-based hardware is designed to
improve the precision of the past hardware implementation that were based on fixed-point arithmetics. The hardware of the detector and the adaptive LMS filter have been
implemented on a programmable logic device (FPGA) for
hardware acceleration purpose. The ideal Matlab/Simulink
model of the hardware and the VHDL model of the adaptive LMS filter and the phase and magnitude detector are
compared. The comparison result shows that the output
signal of the floating-point based adaptive FIR filter as well
as the phase and magnitude detector agree with the expected output signal of the ideal Matlab/Simulink model.

Proceedings of ICALEPCS2011, Grenoble, France

PHASE-MAGNITUDE COMPUTATION
Architecture for Phase-Magnitude Computing
The phase and magnitude of the beam signal are detected by using a CORDIC (COordinate Rotation DIgital Computer) algorithm. The drawback of a conventional
CORDIC algorithm is its high computation latency [7]. To
accelerate the computation, an increment of rotation angle
on each iteration becomes one solution. A double-rotation
CORDIC algorithm is proposed as depicted in Alg. 1. In
the double-rotation CORDIC algorithm, the rotation angle
is extended two times (2) of the conventional CORDIC.
Algorithm 1 MICRO-DRCORDIC-VM

c 2011 by the respective authors cc Creative Commons Attribution 3.0 (CC BY 3.0)
Copyright

Input: : Xi , Yi , Zi , T , i
Output: : X, Y , Z, i+1
X = Xi 22i2 Xi i 2i Yi
Y = Yi 22i2 Yi + i 2i Xi
Z = Zi i 2 T

The double-rotation CORDIC algorithm using the redundant method was proposed by Takagi et al. [13]. With
the redundant method, the rotation direction of the doublerotation CORDIC algorithm is i {1, 0, 1}. However,
using the redundant method, the scaling factor is not constant and has to be calculated at run-time. To overcome
this problem, we propose the double-rotation CORDIC algorithm as presented in Alg. 2 using the non-redundant
method and with a constant scaling factor. Thereby, the online computation problem [1], as well as the scaling problem are also eliminated.

Kdr X02 + Y02

XN

0
(1)

YN =

Y0
ZN
arctan
X0
Algorithm 2 DRCORDIC-VM
Input: : Xin , Yin , N, LT AN, K 1
dr
Output: : Xout , Zout
X0 =Xin , Y0 =Yin , Zin =0, 0 =1 {Initialization}
if Y0 0 then
0 =1;
else
0 =-1;
end if
for i = 1toN do
[X, Y , Z]=MICRO-DRCORDIC-VM(Xo , Yo , Zo , T LU T (i), i )
if Y 0 then
i+1 =1;
else
i+1 =-1;
end if
X0 = X
Y0 = Y
Z0 = Z
end for
1
Xout = X Kdr ; Zout =Z

The constant scaling factor for the double-rotation

N
CORDIC is given by Kdr = i=1 (1 + 22i2 ) which
1
= 0.9219),
approximately equals 1.084727 (Kdr

684

and
maximum and minimum rotation angle

N the 1
(2i1 ) is in the range of [-0.9885,+0.9885].
i=1 2tan
Alg. 3 shows the computation of the beam phase and
magnitude based on online measurements of the gain voltages GVi and beam position BPi signals [2], which is
illustrated in Fig. 1. The beam phase difference signal
(P hase) is obtained from the difference between the
phase detection signals PA and PB of the gap voltages GVi
and beam positions BPi signals, respectively.
Algorithm 3 BEAM Phase and Magnitude
Input: : GV1 ,GV2 ,GV3 ,GV4 ,BP1 ,BP2 ,BP3 ,BP4
Output: : M,
Q1A = GV1 ; I1A = GV2 ; Q2A = GV3 ; I2A = GV4
Q1B = BP1 ; I1B = BP2 ; Q2B = BP3 ; I2B = BP4
XA = Q1A Q2A
YA = I1A I2A
1
[MA , PA ]=DRCORDIC-VM(XA , YA , N , T LUT ,Kdr
)
XB = Q1B Q2B
YB = I1B I2B
1
[MB , PB ]=DRCORDIC-VM(XB , YB , N , T LUT ,Kdr
)
M = MB
=PA PB

The architecture of the 3-stage double-rotation CORDIC

algorithm for the beam phase-magnitude detection is illustrated in Fig. 2. The 3-stage pipeline architecture is designed to improve the performance of the beam-phase detector.
xi

M2

SR

yi

M1

M2

SR

SR

zi

M1

tani

inv

SR

Dpath1
Sub

Sub

Sub

Dpath2
inv
m

inv

Add/Sub

Add

xo

yo

Dpath3
zo

Figure 2: The micro-rotation architecture of the 3-stage

double-rotation CORDIC algorithm, where M1 = i,
M2 = 2i 2 and d = i .
5

MAPE of mag.%

dashed. In order to enable real-time processing, the phase

detector and filtering blocks have been implemented on an
FPGA.

MAPE of phase %

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x 10

Doublerotation
Conventional

4
2
0
10

11

12

13
Iterations

14

0.4

15

16

Doublerotation
Conventional

0.3
0.2
0.1
0
10

11

12

13
Iterations

14

15

16

Figure 3: MAPE comparison of the conventional CORDIC

and the double-rotation CORDIC.
Figure 3 depicts the performance comparison between
the conventional and the double-rotation CORDIC algorithm by using the MAPE metric. MAPE stands for

Hardware

Proceedings of ICALEPCS2011, Grenoble, France

Figure 4: Beam input, reference and beam phase signals.

Table 1 shows the synthesis results of the micro-rotation
of the double rotation CORDIC algorithm onto a Xilinx
FPGA vlx110t-2ff1738 for different implementations (in
terms of the number of pipeline stages). Logic area comparisons between the conventional (CV) and the doublerotaion (DR) CORDIC architectures are presented in the
table.
Table 1: Synthesis Results on Xilinx FPGA vlx110t
Utilization
Min. Delay Max. Freq.
SReg SLUT LUT-FF
(ns)
(MHz)
1-state CV 252
0
0
4.68
213.668
2-state CV 258 343
231
3.05
327.836
3-state CV 273 355
239
2.94
340.513
1-state DR 663
0
0
7.713
129.653
2-state DR 258 698
230
5.045
198.210
3-state DR 746 1228
405
4.107
243.496
SReg=Slice Register, SLUT=Slice LUT
CORDIC

Hardware

The noise in the phase difference of the beam signal

shown in Alg. 3 is filtered by using adaptive FIR filter in
which the filter parameters are adaptively tuned by using a
least-mean-square (LMS) algorithm. The hardware architecture of the adaptive FIR filter is designed by using the
combination of serial and parallel structures. This combination is made to fulfill the time constraint of the application and the area constraint of the FPGA device. Figure 5
presents the serial-parallel architecture of the adaptive FIR
filter with 64 taps. Two registers are controlled by a control
unit and are used to store the sampled input signal x(k j)
and the filter parameters wj . The filter output computation
is implemented in serial, while the filter parameter adaptation algorithm is implemented in parallel.
Floating-point adder, multiplier and multiplieraccumulator units were used in the filter architecture.
The operands are IEEE single-precision binary floatingpoint numbers [12], i. e. they have 1 sign bit, 8 exponent
bits and 23 mantissa bits. The floating-point adder
architecture consists of three stages: exponent difference and alignment, adding/subtracting combined with
leading-on-detection and normalization stage.
The floating-point multiplier architecture also consists of
three stages: exponent adding and mantissa multiplication,
mantissa shifting and normalization stages. In the normalization stages, the arithmetic computing results are normalized into the standard 32-bit (single precision) binary floating point format. The normalization stages include also the
zero and infinity detections of the data values according to
the IEEE standard [12]. This approach is the same as the
one used in other projects documented in available literature [8].
Controller block
w1
w2
w3
w4
.........
wj
.........
w61
w62
w63
w64

x(k)
j

Control
Unit
xkj

wj

Mult
Add
y(k)
e(k)

Adaptive Algorithm block

Subs
y(k)

d(k)

x(k1)
x(k2)
x(k3)
x(k4)
.........
x(kj)
.........
x(k61)
x(k62)
x(k63)
x(k64)

Filter block

Figure 5: Adaptive FIR Filter architecture with 64 taps.

Simulation and Synthesis Results

Figure 6 shows the input-output signals of the adaptive
filter, the desired output signal and the error signal between
the filter output and the desired output signals. The main
challenge of the adaptive FIR filter hardware in practice

685

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Copyright

The simulation result of the double-rotation CORDIC algorithm for the beam phase signal detection is depicted in
Fig. 4. The figure presents the beam input signal, the reference signal and the the output of the phase detector. The
output of the beam phase detector (beam phase signal) is
interfered with noisy signal. Therefore, the noise signal
should be filtered to acquire the noise-free beam phase signal. The filtering issue is described in the next section.

Filter Architecture

FPMAC0

Simulation and Synthesis Results

PHASE DIFFERENCE SIGNAL

FILTERING

Adaptive LMS Algorithm

Mean Absolute Percentage Error and is a statistical measurement

the CORIDC output accuracy formulated by

n cof
1
s ms
s=1 | cs |, where n is the number of measurements,
n
cs is the CORDIC output and ms is the ideal output.
The figure shows that the double-rotation technique gives
better accuracy with the same number of iterations. In
other words, for the same MAPE value, the double-rotation
CORDIC requires less interations.

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WEMMU001

Proceedings of ICALEPCS2011, Grenoble, France

ply the adaptive FIR filter with an expected signal that is
not known a priori.

ACKNOWLEDGEMENTS
The author would like to thank German Federal Ministry of Education and Research (Bundesministerium fur
Bildung and Forschung) for supporting the work in the
framework of Project FAIR (Facility for Antiproton and Ion
Research), Grant Number 06DA9028I.

REFERENCES

c 2011 by the respective authors cc Creative Commons Attribution 3.0 (CC BY 3.0)
Copyright

Figure 6: Filter input-output signals.

Table 2: Synthesis Result on FPGA Virtex 5 Device
Utilization % of Total
Number of slice registers
38,549
31%
Number of slice LUTs
75,485
61%
Minimum Delay
7.462 ns
Maximum Frequency
134.018 MHz)
is the generation of the expected filter output. At present,
the expected signal is calculated off-line. In the simulation results shown above, the signal was captured from a
system model [9, 10]. We are working on a hardware implementation of a simplified system model that can serve
as a reference in the future.
The adaptive FIR filter with LMS algorithm has been
implemented on the Virtex5 FPGA device (device type
5vfx200tff1738-2). The device has a total number of 200k
logic gates. The synthesis result is shown in Table 2.

CONCLUSIONS AND OUTLOOKS

The beam phase-magnitude hardware detector based
on the double-rotation CORDIC algorithm has been presented. Compared to the conventional CORDIC algorithm,
the double-rotation CORDIC algorithm provides better accuracy. The adaptive FIR filter architecture that combine
serial and parallel computation modes is also presented.
The adaptive LMS algorithm is driven by the error signal
between the filter output and the desired signal. For now,
the desired signal is calculated off-line. In the future, we
plan to include a simplified system model in order to sup-

686

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Redundant and on-line
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Hardware