1

Memory BIST area estimator using Artificial

Neural Networks
Aymen Lamine, Nabil Chouba, and Laroussi Bouzaida,
{aymen.lamine, nabil.chouba, laroussi.bouzaida}@st.com
STMicroelectronics 2083 La Gazelle Ariana, Tunisia

specifications. Time-to-market constraints push more and

Abstract—Time to market constraints pushes more and more more designers to reduce designing time, and SOC is in a large
designers to make area estimations early during the design part contributing in this strategy, so it is not acceptable to
process. Estimating the Built-In Self Test (BIST) area is only spend a lot of time calculating BIST area overhead for different
possible once the different design memories BIST are synthesized. architectural configurations. Thus, there’s a need of a faster
This is time consuming and not realistic for a large circuit such as
way of estimation, let say an instant BIST area estimation for a
a SOC which can include hundreds of memories. In this paper we
given memory CUT.
propose a push button solution for BIST area estimation called
BARES based on Artificial Neuronal Networks handling.
Within STMICROELECTRONICS, a statistical based technique
Experiments have been performed on different has been developed to respond to this need, for confidentiality
STMICROELECTRONICS BIST memories and results prove the reasons we can’t reference it, but let say that it is able to
efficiency of the proposed method. furnish instantly the designer with a good estimation of the
BIST area but it has to be customized for each kind of memory
Index Terms—Artificial Neural Network, Area estimation, and in some case for some special configuration and this
Backpropagation algorithm, BIST, memory, Perceptron.
induces complexity and time consumption in the estimator
itself development. It is important to notice that there’s a large
subset of memories with different kinds of options in addition
I. INTRODUCTION
to new ones that are continuously implemented following
customer’s requests and technology evolutions.
B UILT-in self test (BIST) is the main DFT technique used
for memory testing [10, 11, 12, 13]. Compared to other
techniques, it is characterized by its good fault coverage, test
In this paper we present a new method implemented within
a tool we named BARES. This method is built around the
artificial neural networks (ANN) technique. BARES instantly and
speed and enabling direct test access to embedded memory; accurately approximates the bist area variation considering the
however it increases the area and gives small information for memories parameters. The area estimation is based on
diagnosis. Even though the BIST area is very small compared to multilayer neural networks integrated into the tool. These
the memory one, it represents a real issue in nowadays circuits networks are trained on different memory CUT BIST area with
(e.g. SOC) where the number of integrated memories is different parameters and BIST options using the
continuously growing and accumulating their BIST areas leads backpropagation learning algorithm. Experiments have been
to a significant global area overhead. performed on different STMICROELECTRONICS BIST memories
Considering BIST strategy, designers are facing a big and results prove the efficiency of the proposed method.
dilemma: How to estimate the total area overhead early in the This paper is organized as follows: the second section
design flow and hence the DFT memory cost? How to save test describes the issue and presents an overview of the proposed
run time and at the same time control the circuit overall area solution. The third section focuses on the memories parameters
overhead? The problem is that the best estimation of the BIST that can affect the BIST area and should be considered by our
area overhead, before going far in the design flow, is obtained estimator. The fourth section describes the neural networks
after RTL synthesis which is time and synthesis license learning and validation as well as their integration within the
consuming especially when the number of BIST in the design is tool. Next, we present the results of the experiments we
important leading designers to spend lot of time in exploring performed and the level of accuracy we reached. Finally,
BIST strategies [10, 11, 12, 13] and options as bitmap,
conclusions constitute the last part of the paper.
redundancy, etc…
Actually, SOC designers need to have, early during the
design flow, an area estimation in order to be able to make
some modifications or optimizations to full fit their
 2

II. ISSUE, STATE OF THE ART & PROPOSED SOLUTION For each memory, four ANN are obtained through a learning
phase:
A. Core issue • Standard configuration
For a given memory CUT (words number, bits number, • Mask_bits
MUX factor, etc…) calculate instantly, during the system level • Redundancy
design step and before synthesis, the area overhead due to BIST • Mask_bits and redundancy.
insertion. As a prelude, we decided that the rough calculation
delta between estimated area and the synthesis resulting one During the learning phase of those four ANN, the parameters,
should be less than 10%. Words, Bits and BIST frequency vary within limits we fix
As far as we know, such issue has never been treated in the according to memories and technologies constraints.
different IEEE publications. The unique project which
succeeded to deliver a solution has been conducted within one In another hand, it has been decided to ignore the MUX
of the STMICROELECTRONICS divisions. We will not go factor which doesn’t have any impact on the BIST area except
through its details; however in the introduction it has been in the specific case of small sized memories where the MUX
mentioned. factor can change the BIST configuration itself. The results
The solution we present uses an artificial neural networks presented in (Figure 1) show that:
technique. Several ANN are built and the principle is to make • In 97.4% of cases, the area variation due to MUX one
them learn the BIST area variation while varying some is lower than 4%.
parameters like the number of words or bits for and right • In 88.5% of cases, the area variation due to MUX one
through different memories or BIST specific configurations is lower than 2%
such as redundancy, mask_bits, and also synthesis constraints The average of variation is 1.06%.
like frequency.
Learning phase produces a set of small files storing the ANN
pertinent information (set of specific weights). BARES
assembles all those files, each one integrating an ANN of a
specific memory BIST configuration, and once invoked,
through a simple command, it uses the appropriated ANN
weights to calculate instantly the estimated area. For the
following, let’s make the convention that integrating a memory
within BARES means that we generate its ANN set of files and
we link them to BARES kernel.
Figure 1: BIST area variation for different memories with
III. PRELIMINARY STUDIES several mux factors compared to mux factor 4.
B. Targeted memories
In order to specify the different parameters that can have an
BARES targets SRAM memories:
influence on BIST area estimation we did several preliminary
studies. The idea was to only concentrate the learning phase on • Single port SRAM
those who really impact area when varying and in the same • Dual port SRAM
time increase the ANN convergence speed. Without going in C. Black boxes or synthesis memory synthesis models
details, let’s say that we reached the conclusion that the This study scope was to evaluate the influence, on the BIST
following memory or BIST specific characteristics have a real area, of synthesizing the BIST with, or without, a memory
impact on the area when we are varying: synthesis models. The obtained results (Table 1) show that, for
A. Memory & BIST specific parameters the targeted memories, the area variation between using a
memory synthesis model and considering the memory as black
• CMOS technology
box doesn’t exceed in any case 9%, while the average
• Words
variation is about 2%. The cases where the difference exceeds
• Bits
5% are very limited. This low variation allows us to consider
• BIST frequency
the use of black boxes instead of memory models. In fact, this
• Redundancy
will give us the possibility to easily and quickly build a large
• Mask_bits
database for the learning phase. We simply avoid memory
• Synthesis timing constraint
synthesis model generation for each element of the database
The synthesis timing constraints are related to slack
(long internal procedure).
problems on the memory busses. In order to avoid them we
fixed the maximum delay on those busses to 1.1 ns which
according to our specific case will avoid such problems.
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Table 1 : BIST area variation with and without use of on the learning convergence of each network (i.e. memory
memory model type). The neurons connection weights are all initialized to a
Synthesized BIST very small random values for all networks.
Memory
BIST area (µm2)
parameters Variation
frequency with without a) Learning rate
(%)
(MHz) memory memory The learning procedure requires that the change in weight
word bit mux
model model should be proportional to the error delta between two output
128 4 4 200 3320.24 3403.66 2.51 patterns. True gradient descent requires that infinitesimal steps
256 4 4 200 3404.75 3485.98 2.39 are considered. The constant of proportionality is the learning
2048 4 4 200 3641.83 3730.74 2.44 rate. For practical purposes we choose a learning rate as large
128 8 4 200 3521.11 3584.76 1.81 as possible while controlling at the same time the oscillations.
1024 4 4 200 3827.33 3822.94 0.15 In our case, we did choose a learning rate equal to 0.3; this is
256 32 4 200 4637.36 4788.83 3.27 coming from several experimental tests.
2048 32 4 200 4876.64 5024.81 3.04
4096 32 4 200 4949.08 5084.18 2.75 b) Building databases
128 64 4 200 6009.36 6150.97 2.35 As mentioned before, the use of ANN for the BIST area
512 64 4 200 6160.82 6315.59 2.51 estimation requires a large amount of data. These databases,
4096 64 4 200 6392.42 6560.35 2.63 containing massive information on a given memory in the
shape of CUTs configuration associated to their synthesized
IV. IMPLEMENTATION BIST area, are used for the learning step of an ANN. Those
databases are tabular files containing the inputs (words, bits,
A. The Multi-layer feed-forward networks mux and frequency) and outputs (BIST area) of the ANN. The
As mentioned before, the neuronal network used in our case same databases are used later in order to test and validate the
is the multilayer feed-forward network with a backpropagation built networks.
learning rule. A feed-forward network has a layered structure. The first step of a memory integration within BARES is
Each layer consists of units which receive their inputs from building the database. Making the decision to use black boxes
units from the layer below (n-1) and send their outputs to units for memories simplified a lot this step since we just need to
in a layer above (n+1). There are no connections within a synthesize BIST which we is generated automatically with our
layer. Although backpropagation can be applied to networks internal STMICROELECTRONICS BIST generator ( ugnBIST ).
with any number of layers, it has been shown in ([5], [6], [7] The task is done by an automatic database generator, which
and [8]) that only one layer of hidden units suffices to reads a specification file indicating the targeted memory and
approximate any function with finitely many discontinuities to the BIST specific configuration, and then goes through the
arbitrary precision, provided the activation functions of the synthesis flow and reports the areas.
hidden units are non-linear (the universal approximation The resulting database is then split into two parts, one used
theorem). In our application the feed-forward network with a for the learning phase (75% of the initial database) and the
three layers of hidden units is used with a sigmoid activation second one for test and validation (the remaining 25%). This
function for the units. split is randomly done.
The backpropagation algorithm [10] is a gradient-descent Finally, both databases are formatted to fit the input and
method minimizing the squared error cost function. It is the output format of the neural network where all the values must
algorithm used for the learning phase. be in the range] 0, 1[.

1) Networks architecture c) Learning step

In our specific application, each network has 5 layers and During this process, a network, defined by its architecture
each layer has a specific neurons number: and initial connections weight, is trained to a targeted
• Input layer: 3 neurons (fix). database. The learning phase of the multilayer feed-forward
• 3 hidden layers: 4, 6 and 3 neurons to start the ANN network is supervised since it uses the backpropagation
building flow, but their number can vary during learning rule. To get a sufficient control on the learning phase,
optimizations. we report, during this stage, both the error and the squared-
• Output layer: 1 neuron (fix). error. While the error is the principle criteria to end the
learning, the use of the squared-error makes us predict the
2) ANN building flow behavior of the network. Thus we can early decide whether the
network will converge or it needs more optimization
The number of neurons in each hidden layer is set equal for
all the ANN during the initial state. During learning phase the
number of neurons can be increased or decreased depending
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d) Learning optimization A. Single port

• Learning rate optimization The figures below (Figures 2, 3 and 4) show the obtained
One way to optimize the learning rate is to completely avoid results for different kind of single port memory CUT with
oscillations. This is done by making a correlation between the different BIST configurations:
new weights introduced in the network and the previous ones, For the SPSMALL memory BIST with default options,
by adding a momentum term. When no momentum term is shown in Figure 2, only 5% of memory CUT had a delta error
used, it takes long time before the minimum is reached with a greater than 2%. Moreover, in about 75% of cases the delta
low learning rate. For high learning rates the minimum is never error didn’t exceed 1%.
reached because of oscillations. When adding the momentum Figure 3 shows the results obtained for a SPHD memory
term, the minimum is reached faster and local minima are BIST which is larger than the SPSMALL one. We got only 7%
avoided. In our case we did set the momentum to 0.25. of cases were the delta error exceeded 2%, however, the cases
This optimization method is the first one we invoke for its where the delta error was lower than 1% decreased to 63%.
efficiency. Indeed, it is hard-coded in the backpropagation
algorithm.
• Network architecture optimization
This optimization is done manually by editing the network
architecture when the learning algorithm fails to converge or
when we observe an over learning. In both cases a
modification in the neurons number in each hidden layer is
necessary: in the first case we add some units while in the
second case, we remove some of them.
• Database random selection
As it is mentioned in section IV-1-b, the more randomly the
database patterns are selected, the more efficient the learning
will be. In case of a failing learning process, we can restart it,
without re-synthesizing, from the same initial database by
doing another random selection. This optimization is usually
used as last alternative and this was decided throughout
multiple experimental processes.
Figure 2: Error distribution for single port memory
3) Validation step
(SPSMALL) with default BIST options.
In this stage, each configured network is tested using the
validation database. For each memory CUT the synthesized
BIST area is compared to the estimated one and the difference
error is calculated. If the delta error exceeds the threshold
(%10), another neural network is built up with a different
architecture and trained again for the same memory CUT and
BIST configurations.
In case of complying results, the neural network and its
synaptic weight configuration is saved and integrated to
BARES.

V. RESULTS
The results shown in this section are the calculated delta
errors between synthesized and estimated BIST area as obtained
during the validation step (section IV-3). Histograms in figures
hereafter ( Figures 2 to 7) plot the error distribution for single
port memory BIST reporting the error percentile range on X
axis and the number of memory CUT on Y axis. Figure 3: Error distribution for single port memory
Experiments have been performed on a large set of (SPHD) with default BIST options.
STMICROELECTRONICS SRAM (single or dual port) memories.
The worst delta never exceeded 10%, (the threshold fixed The last example shown in Figure 4 is about the SPHS
for this estimator). Moreover, the maximum one was only 6% memory BIST used with both redundancy and mask_bits
and in about 90% of cases we got a delta under 2%. options.
With these configurations, this BIST is the biggest one
 5

amongst the ones shown for the single port memories. The The last example shown in Figure 7 is about the DPHS
obtained results show that in about 14% of cases we got delta memory BIST used with both redundancy and mask_bits
error greater than 2%. Meanwhile, the cases where the delta options. The obtained results show that in about 25% of cases
error didn’t exceed 1% were only about 60%. we got delta error greater than 2%. Meanwhile, the cases
where the delta error didn’t exceed 1% were only about 51%.

Figure 4: Error distribution for single port memory

(SPHS) with redundancy and mask_bits BIST options
enabled.

Figure 6: Error distribution for a dual port memory

B. Dual port
(DPHD) with mask_bits BIST option enabled.
The figures below (Figures 5, 6 and 7) show the obtained
results for different kind of dual port memory CUT with
different BIST configurations:
For the DPHD memory BIST with default options, shown in
Figure 5, only 11% of memory CUT had a delta error greater
than 2%. But, in about 60% of cases the delta error didn’t
exceed 1%.
Figure 6 shows the results obtained for the same type of
memory but with a different BIST configuration, actually
enabling the mask_bits option. We got only 17% of cases were
the delta error exceeded 2%. However, the cases where the
delta error was lower than 1% decreased to 52%.

Figure 7: Error distribution for dual port memory (DPHS)

with redundancy and mask_bits BIST options enabled.

VI. BARES MEMORY INTEGRATION PLATFORM

Now, BARES is used in two different divisions of

STMICROELECTRONICS worldwide and users are very satisfied
by its efficiency. As adding new memories is time consuming
we developed a complete automatic integration platform
(Figure 8). This includes databases generation, learning steps,
optimization and integration within the tool. For a new
memory, the user just needs to prepare a specification file
including all necessary information about the memory, its BIST,
the development platform and CAD tools (BIST generator &
Figure 5: Error distribution for a dual port memory synthesizer).
(DPHD) with default BIST options.
 6

[3] B.M. Wilamowski, O. Kaynak, S. Iplikci & M.Ö. Efe, “An algorithm
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Automatic neuronal network integration platform Page(s):91 - 96

Neuronal network topology

Synaptic weight

Result files used by BARES

Figure 8: Automatic integration platform flow

VII. CONCLUSIONS

In this paper we described the methodology we did follow

to build up our solution for BIST area estimation and the
different steps this one, implemented through a software tool,
follows in order to give accurate BIST area estimation for a
given memory and BIST configuration. This accuracy and
flexibility was made possible using the Artificial Neural
Networks concept.

Building ANN requires large databases which cover the

maximum of memories and BIST configuration. The integration
platform we deliver with BARES (section VI) overcomes this
constraint and offers the users an extensible tool giving very
efficient BIST area estimation.

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