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Ieee Ieee STD - LOGIC - 1164: Library Use ALL

This document contains the VHDL code for a 4x6 register file with read and write capabilities. It has 4 6-bit registers that can be written to or read from using 2-bit addresses. On a clock edge, it will write data to the register selected by the write address or output the data from the register selected by the read address. Clear resets all registers to zeros.

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cantone
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
20 views

Ieee Ieee STD - LOGIC - 1164: Library Use ALL

This document contains the VHDL code for a 4x6 register file with read and write capabilities. It has 4 6-bit registers that can be written to or read from using 2-bit addresses. On a clock edge, it will write data to the register selected by the write address or output the data from the register selected by the read address. Clear resets all registers to zeros.

Uploaded by

cantone
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Fri Nov 19 13:01:56 2010

regFile_4x6v2.vhd
1 --------------------------------------------------------------------
--------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 01:47:16 11/14/2010
6 -- Design Name:
7 -- Module Name: regFile_4x6v2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 --------------------------------------------------------------------
--------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity regFile_4x6v2 is
33 Port ( wr_addr : in STD_LOGIC_VECTOR (1 downto 0);
34 wr_en : in STD_LOGIC;
35 wr_data : in STD_LOGIC_VECTOR (5 downto 0);
36 rd_addr : in STD_LOGIC_VECTOR (1 downto 0);
37 rd_en : in STD_LOGIC;
38 clk : in STD_LOGIC;
39 clr_n : in STD_LOGIC;
40 rd_data : out STD_LOGIC_VECTOR (5 downto 0));
41 end regFile_4x6v2;
42
43 architecture regFile_4x6v2_a of regFile_4x6v2 is

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Fri Nov 19 13:01:56 2010
regFile_4x6v2.vhd
44 signal reg0 : std_logic_vector(5 downto 0);
45 signal reg1 : std_logic_vector(5 downto 0);
46 signal reg2 : std_logic_vector(5 downto 0);
47 signal reg3 : std_logic_vector(5 downto 0);
48 signal wrCtrl : std_logic_vector(3 downto 0);
49 signal rdIn : std_logic_vector(5 downto 0);
50 signal rdReg : std_logic_vector(5 downto 0);
51 begin
52
53 wrDecoder: process(clk, wr_addr) --Write address decoder
54 begin
55 CASE (wr_addr) IS
56 when "00" => wrCtrl <= "0001";
57 when "01" => wrCtrl <= "0010";
58 when "10" => wrCtrl <= "0100";
59 when "11" => wrCtrl <= "1000";
60 when others => wrCtrl <= "ZZZZ";
61 end case;
62 end process; --End of Write address decoder
63
64 process(clk, clr_n, wr_en, wr_data) --Write to register
65 begin
66 if(clr_n ='0') then
67 reg0 <= "000000";
68 reg1 <= "000000";
69 reg2 <= "000000";
70 reg3 <= "000000";
71 elsif(clk'event AND clk='1') then
72 if(wr_en = '1' And wrCtrl(0) = '1') then
73 reg0 <= wr_data;
74 end if;
75 if(wr_en = '1' And wrCtrl(1) = '1') then
76 reg1 <= wr_data;
77 end if;
78 if(wr_en = '1' And wrCtrl(2) = '1') then
79 reg2 <= wr_data;
80 end if;
81 if(wr_en = '1' And wrCtrl(3) = '1') then
82 reg3 <= wr_data;
83 end if;
84 end if;
85
86 end process; --End of Write to register
87
88 rdDecoder: process(rd_addr, reg0, reg1, reg2, reg3) --Read address

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regFile_4x6v2.vhd
decoder
89 begin
90 CASE (rd_addr) IS
91 when "00" => rdIn <= reg0;
92 when "01" => rdIn <= reg1;
93 when "10" => rdIn <= reg2;
94 when "11" => rdIn <= reg3;
95 when others => rdIn <= "ZZZZZZ";
96 end case;
97 end process; --End read address decoder
98
99 rd: process(clk, clr_n, rd_en) --Read register
100 begin
101 if(clr_n ='0') then
102 rdReg <= "000000";
103 elsif(clk'event AND clk='1') then
104 if(rd_en='1') then
105 rdReg <= rdIn;
106 end if;
107 end if;
108
109 end process; --End read register
110 rd_data<=rdReg;
111 end regFile_4x6v2_a;
112
113

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