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Manual - Proteus-Ares
Manual - Proteus-Ares
User Manual
Issue 6.0 - November 2002
© Labcenter Electronics
ICON REFERENCE CHART
Circular Square DIL SMT Edge Connector Pad Stack Polygonal SMT
2D Graphics Icons
Editing Commands
Block Copy Block Move Block Delete Block Rotate Pick Package Decompose Make Package
New Save Print Import Export Set Print CADCAM Gerber View &
Region Region Output Panelization
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Display Commands
Layout tools
INTRODUCTION...................................................................................... 1
WHAT IS ARES?..............................................................................................................1
Layout Editor Features ..................................................................................1
Auto-Placer ....................................................................................................2
Auto-Routing.................................................................................................2
Power Plane Support .....................................................................................2
HOW TO USE THIS MANUAL......................................................................................3
GETTING STARTED............................................................................... 5
INSTALLATION...............................................................................................................5
START UP OPTIONS.......................................................................................................5
SCREEN AND HARD COPY DRIVERS .........................................................................5
Graphics Driver..............................................................................................5
Printer & Plotter Drivers................................................................................5
SYSTEM INFORMATION...............................................................................................6
TUTORIAL ................................................................................................ 7
INTRODUCTION ..............................................................................................................7
OVERVIEW OF THE LAYOUT EDITOR.......................................................................7
BASIC PLACEMENT & ROUTING TECHNIQUES .....................................................8
Package Placement..........................................................................................9
Routing.........................................................................................................10
Annotation ...................................................................................................10
Board Outline...............................................................................................11
BLOCK EDITING FACILITIES......................................................................................12
ROUTE EDITING.............................................................................................................12
Via Placement ...............................................................................................12
Changing a Route's Width............................................................................13
Auto Track Necking.....................................................................................13
Tagging a Route............................................................................................13
Moving/Dragging a Tagged route..................................................................14
Deleting a Tagged Route...............................................................................14
The Context Menu.......................................................................................14
Re-routing.....................................................................................................15
Connectivity Highlight .................................................................................15
HARD COPY GENERATION.........................................................................................16
THE PACKAGE LIBRARY............................................................................................17
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NETLIST MANAGEMENT....................................................................63
NETLIST FEATURES .....................................................................................................63
The Load Netlist Command.........................................................................63
Using the Netlist Loader on an Empty Layout............................................63
The Netlist Loader & Existing Components................................................63
The Netlist Loader & Existing Tracking.......................................................64
Problems with Pin Numbers ........................................................................64
Packaging Considerations.............................................................................65
Connectivity Highlight .................................................................................66
RATSNEST FEATURES ................................................................................................66
Automatic Ratsnest Recalculation ...............................................................66
Force Vectors ...............................................................................................67
Ratsnest Mode.............................................................................................67
Manual Ratsnest Entry ................................................................................67
PIN_SWAP/GATE SWAP.............................................................................................69
Manual Pin-Swap/Gate-Swap......................................................................69
Automatic Gate-Swap Optimization...........................................................69
Synchronization with the Schematic............................................................70
ROUTING STRATEGIES................................................................................................71
Strategies and the Netlist..............................................................................71
Special Strategy Names ................................................................................72
Editing a Strategy .........................................................................................72
BACK ANNOTATION...................................................................................................74
Manual Re-Annotation ................................................................................74
Automatic Re-Annotation............................................................................74
Back-Annotation to ISIS..............................................................................74
REVERSE NETLISTING..................................................................................................75
SDFGEN - CONVERTING 3RD PARTY NETLISTS ...................................................75
AUTO-PLACEMENT.............................................................................77
INTRODUCTION ............................................................................................................77
USING THE AUTO-PLACER ........................................................................................77
THE AUTO-PLACER DIALOGUE................................................................................78
The Component Selector..............................................................................78
ARES
Design Rules.................................................................................................78
Trial Placement and Cost Weightings...........................................................78
Options ........................................................................................................80
OCCUPANCY DEFINITIONS........................................................................................80
LIMITATIONS ................................................................................................................81
AUTO-ROUTING....................................................................................83
INTRODUCTION ............................................................................................................83
THE AUTO-ROUTER COMMAND.............................................................................84
HINTS AND TIPS ABOUT AUTO-ROUTING...........................................................86
Single Sided Boards ......................................................................................86
Avoiding Using Component Pads as Through Holes...................................86
Off Grid Pads...............................................................................................87
Surface Mount Components........................................................................87
Routing to Internal Power Planes.................................................................88
TIDY PASS.......................................................................................................................89
POWER PLANES..................................................................................91
INTRODUCTION & BACKGROUND..........................................................................91
Grid Based Power Planes .............................................................................91
Negative Image Power Planes.......................................................................91
Polygonal Gridless Power Planes.................................................................92
Ground Planes Without a Netlist.................................................................93
USING POLYGONAL POWER PLANES .....................................................................93
The Power Plane Generator Command........................................................93
Zone Placement Mode .................................................................................94
Editing a Power Plane...................................................................................94
Deleting a Power Plane.................................................................................96
Automatic Regeneration of Power Planes ....................................................96
Quick Redraw Mode....................................................................................97
Auto-Routing & Power Planes.....................................................................97
Rotation......................................................................................................102
Reflection ...................................................................................................102
Scaling.........................................................................................................102
Layers.........................................................................................................102
PLOTTER OUTPUT......................................................................................................102
Plotter Pen Colours....................................................................................103
Plotter Tips................................................................................................103
POSTSCRIPT OUTPUT................................................................................................104
CLIPBOARD AND GRAPHICS FILE GENERATION..............................................104
Bitmap Generation.....................................................................................104
Metafile Generation ...................................................................................104
DXF File Generation..................................................................................105
EPS File Generation ...................................................................................105
Overlay Bitmap Generation.......................................................................105
INDEX ....................................................................................................131
INTRODUCTION
WHAT IS ARES?
ARES (Advanced Routing and Editing Software) forms the PCB layout module of the
PROTEUS system and offers netlist based PCB design complete with a suite of high
performance design automation tools.
The latest version, is compatible with Windows 98/Me/2k/XP and later. It includes a brand
new Auto-Placer, improved Auto-Routing, automatic Gate-Swap optimization and even more
powerful support for power planes.
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Auto-Placer
ARES includes an autoplacer module, an addition which in combination with the auto-router
makes it possible to create PCBs almost entirely automatically. Alternatively, you can use it
interactively, either by pre-placing critical components manually and auto-placing the rest, or
else by using it to place small sections of the design in turn with manual adjustments being
made after each section is placed.
The auto-placer is highly configurable and can be set up to handle a wide variety of board
types.
Auto-Routing
The most tedious, error prone and time consuming part of the traditional electronics
development process is undoubtedly routing the PCB. As a result, it is in this area that the
greatest benefits of Electronic Design Automation are to be found.
Our autorouter is the result of intensive (and continuing) research into techniques for getting
the highest completion rates and you will find it capable of near 100% completion of designs
that could take days by hand. On the harder jobs where some routes are left undone you will
find that Topological Route Editing is ideally suited to moving existing routes so that the
rest can be completed.
The latest version incorporates a rip-up & retry algorithm to ensure maximum possible
completion rate. At the same time, new algorithms have been added to generate fan-out
patterns for rows of off-grid surface mount pads.
The auto-router also includes a tidy pass which reduces track length and via count as well as
improving the aesthetic quality of the layout.
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quite - and also of the issues arising from rendering the computed shapes with a pen of some
minimum thickness.
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GETTING STARTED
INSTALLATION
ARES is installed by the PROTEUS installation program and the procedures for using this are
documented in the common installation instructions at the front of the binder. This
installation process will also copy files for ISIS and ProSpice if you have purchased them.
After you have completed the PROTEUS installation, you may also want to configure ARES
for your system and it is the procedures for this that are documented here.
START UP OPTIONS
The installation process will create a group called “Proteus 6 Professional” and ARES may be
started by double-clicking the ARES icon. In addition, the setup program installs appropriate
file-associations such that double-clicking on PCB layout files will also launch a copy of
ARES.
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SYSTEM INFORMATION
The System Info command on the System menu brings up details of the Release Number of the
system and to whom it is registered. Please have this information to hand when you call for
technical support.
The command also shows how much free RAM you have available - this includes both free
physical and virtual memory. Provided that you have a reasonable amount of free disk space,
you should not encounter memory shortages with ARES, although more memory may well
improve performance.
In addition, statistics about the number of components, pads, tracks etc. are displayed on this
form. Also displayed is the number of 'missing' connections, which equates to the number of
ratsnest lines displayed in the work area.
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TUTORIAL
INTRODUCTION
The purpose of this tutorial is to familiarize you as quickly as possible with the main features
of ARES to the point that you can use the package for real work. Users with modest computer
literacy should find it possible to learn the package and produce their first board within a day.
The tutorial proceeds by taking you through worked examples involving all the important
aspects of the package including:
• Basic techniques for placement and routing.
• Netlist based design including both manual and automatic routing .
• More advanced editing techniques such as block editing and route editing.
• Report generation - the CRC and DRC tools.
• Hard copy generation.
• Library part creation.
We do urge you to work right the way through the tutorial exercises as many things are
pointed out that if missed will result in much wasted time in the long run. Also, having worked
through the tutorial and thus got a basic grasp of the concepts behind the package you will
find it much easier to absorb the material presented in the reference chapters.
The smaller area at the top left of the screen is called the Overview Window. Not entirely
illogically, this is used to display an overview of the entire layout. You can move the work
area to a chosen part of the layout by pointing to where you want to go on the Overview
Window, and clicking left. The green box shows the area currently displayed in the Editing
Window.
Just below the Editing Window is the Layer Selector which determines the current layer or
layer set. The current layer applies both to the placement and selection of PCB objects.
Which layers are displayed can be adjusted by use of the Layers command on the View
menu.
Also at the bottom the screen is the co-ordinate display which reads out the position of the
cursor when appropriate. These reflect not the exact position of the pointer but the location to
which it has been snapped. Two things affect this:
• The currently selected snap grid. The options available appear on the View menu and
also through keys CTRL-F1 and F2 -F4 . You can re-define the snap values through the
Set Grids command on the System menu.
• Real Time Snap. When this feature is enabled, the cursor will lock onto pads and/or
tracks, even if they were not placed on the currently selected snap grid. RTS always
snaps to pads and vias, and will also snap to tracks when the Routing mode icon is
selected. RTS can be turned on and off using the Real-Time Snap command on the
Tools menu or by pressing CTRL+'S'.
ARES can be set to display an X cursor at the position to which it has snapped the pointer
through the X-Cursor command, key 'X'.
The co-ordinates can be in imperial or metric units as set by the Metric (key 'M') command.
You can also set a false origin using the Origin command (key 'O') in which case the co-
ordinates change colour from black to magenta.
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ARES
Package Placement
The most direct way to build up a rough layout of a board is to drive ARES in Package mode.
In this mode, you can pick component footprints or Packages directly from the library and
place them onto the work area.
In our simple example, three packages are used
CAP20
DIL08
RES40
and you can start by picking them from the package library. To do this, first click left on the
Package icon (see the icon sheet at the front of the manual). Next, click left on the 'P' toggle at
the top left of the Object Selector which is now displaying the word 'PACKAGES';. The
Library Pick form will appear and you can pick the required packages from it. When you have
done this, close down the form by clicking the close button (Windows) at the top left.
The three package names should now have appeared in the Object Selector, with the last one
you picked highlighted. Ensure that DIL08 is selected by clicking left on it, point somewhere
in the middle of the Editing Window and hold down the left mouse button. A green outline of
an 8 pin IC will appear which you can move about with the mouse. Position it roughly central
and release the mouse button. Now select the RES40 package and place the two resistors, 0.1"
apart (2 grid squares) and just above pin 8 of the IC. Similarly, place the capacitor outline just
below pin 1.
Unless you are quite adept, you may not have the components positioned quite correctly, so
we will now take a look at how to move things around. Point at a component outline (rather
than its pads) and click right. This will 'tag' it, and cause it to be highlighted. Now, still
keeping the pointer over it, hold the left button down and drag the mouse. This is one of the
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ways to move objects. Also, you can delete a tagged object by pointing at it and clicking
right. An Undo command is available from the Edit menu.
All the objects can be untagged by pointing at no object and clicking right.
Routing
Routing mode is commenced by clicking left on the Trace icon. The Object Selector will
change to display a list of 'Trace Styles' - the default selection of track widths. Select T20 for a
20 thou track.
Traces are placed by clicking left at each point along the required route, and clicking right to
finish.
Other points to note about routing mode:
• Clicking twice at the same point places a via and changes the current layer as defined by
the Set Layer Pairs command on the System menu. The selection of via types can be
displayed by clicking on the Via icon.
• Whilst routing, you can change the current layer by pressing the PGUP and PGDN keys.
In addition CTRL-PGUP selects the top layer and CTRL-PGDN selects the bottom layer.
.• Holding the CTRL key down allows you to place a curved track segment. The progress
of the arc (horizontal then vertical or vice versa) is determined by how you move the
mouse away from the fixed point. It is best to press and hold the CTRL key, then move
the mouse, then click left, then release the CTRL key.
Annotation
When components are placed in Package mode, they have no annotation information
associated with them - later on you will see how components are automatically annotated
when a netlist is used.
To annotate the components, select the Instant Edit icon and then click left on each
component in turn. Each time you do this, a form will appear with fields for the part ID and
value. You might find it easier to use only the keyboard when annotating: the cursor keys will
move the mouse pointer one grid step at a time and the ENTER key will do for the left mouse
button and the OK button on the dialogue forms.
Alternatively, the Auto Name Generator command may be used to generate numerical
sequences for component numbering.
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ARES
Part IDs and values can be moved by tagging the parent object and then pointing specifically
at the ID or value before dragging using the left mouse button. Bear in mind also that you can
set different snapping grids from the View menu or by using keys CTRL-F1 and F2-F4.
The default size for these labels can be determined using the Set Template command on the
System menu.
Board Outline
ARES has a special layer, the EDGE layer, which is intended for holding 2D graphics which
represent the board outline. Objects placed on the EDGE layer will appear on artwork
generated for any of the other layers.
In this case, the board outline is just a box.
To place a rectangular board edge:
1. Select the Box icon.
2. Select the EDGE layer from the Layer Selector.
3. Point at where you want the top left corner of the box, press the left mouse button and
drag out the box to enclose the layout.
4. If you need to resize the box, tag it by pointing at it and clicking right, and then drag the
sizing handles as required using the left mouse button.
Curved or irregularly shaped boards are fully supported; the boundary should be formed from
lines and arcs, or by selecting the Path icon and drawing a single path object.
When you have finished experimenting with this exercise, save it if you wish and then start a
new layout for the next exercise by using the New Layout command on the file menu.
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ROUTE EDITING
Powerful route editing facilities are a major feature of ARES and we shall now take a good
look at the features available in ARES.
Unlike many other PCB design packages, route editing in ARES is based around the topology
of the current tracking rather than depending in any way on how the sections of track were
laid down. In addition, modifications can be made to any part of a route, not just to sections
between 'nodes'.
Via Placement
In almost all circumstances, vias are placed automatically for you. To see this in operation,
select the Trace icon and place a route segment by clicking left at two points. Now click left
over the second point a second time, then at a third point and finally click right to terminate
the route. Clicking (left) at the same point twice causes ARES to place a via and change the
current layer so that (in this case) the next segment will be placed on the top copper layer. At
the same time, a via is placed at the point where the route changes layer.
Which layer is selected is determined by the Set Layer Pairs command on the System menu. It
is possible to define layer pairs, triples or whatever as required. You can also change layer
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ARES
manually whilst placing a route by using the PGDN and PGUP keys, but note that a via is not
placed in this case.
The type of via used can be changed by selecting the Via icon and choosing one of the via
styles from the Object Selector. You can also place, replace, tag, move and delete vias
manually in this mode. The left and right mouse buttons operate as for manipulating
components.
For multi-layer boards, you can select whether normal, blind or buried vias are placed by
selecting the Via icon and then adjusting the Layer Selector.
Tagging a Route
To re-route, delete or copy a section of tracking requires that you first tag it. In a similar
fashion to the object editing facilities, you do this by clicking right on it, though there are one
or two subtleties...
• ARES will only 'sense' tracking on the current layer so you must set the Layer Selector
to make the appropriate layer current. The space bar or the middle mouse button (if your
mouse has one) will cause the selection of the next layer in the layer-pair sequence as
defined by the Set Layer Pairs command. Alternatively, you can move up and down the
layers with PGUP and PGDN.
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• If you click on a via, or a point at which several tracks are joined, all tracks meeting at
that point are tagged.
As with object editing, pointing at nothing and clicking right untags the tagged route.
We suggest that you practice tagging and untagging the routes on the layout before
proceeding further - it is important, though not at all difficult, to grasp how this feature works.
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ARES
Re-routing
Finally, there is a very nice way of modifying the actual path taken by a route. Once you have
a tagged route, you can alter its path by simply placing a new section of tracking (in the usual
way) that starts and ends on the old one. ARES automatically computes which section of the
tagged route is shorted out, and removes it. This is a very natural way to work - all of the
route editing operations shown in the diagram below can easily be carried out with this
feature.
Note that vias which are made redundant (i.e. secondary vias) will also be removed, along
with the shorted out section.
You will find this feature especially useful for moving routes that turn out to be blocking
other ones towards the end of the routing process.
Connectivity Highlight
Although not strictly part of the route editing facilities, Connectivity Highlight does come in
most handy at the end of the routing process when you find yourself needing to check which
connections have and (more importantly) have not been made. For example, you might want
to know if a clock signal has been connected to all the chips requiring it.
To see the feature in operation, select the Connectivity Highlight icon. Click left on a
component pad with attached tracking and you will see that everything connected to that pad
will be highlighted in bright white. All such highlighted objects will remain highlighted,
irrespective of pan and zoom operations, until you invoke the Redraw command (key 'R').
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Also in this mode, clicking on the net selector toggle will highlight all objects
assigned/connected to the currently selected net.
Clicking on the Delete icon will delete traces or vias highlighted by either of the above
techniques thus providing the means to delete all or part of a net.
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The ISIS library parts already contain packaging information for the PCB, by virtue of their
PACKAGE properties. Thus, you can go straight into PCB design by selecting the Netlist to
ARES command from the Tools menu in ISIS.
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ARES
& For a fuller discussion of preparing schematics for PCB design, see the chapter entitled
ISIS & ARES in the ISIS manual.
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The Ratsnest
As you place the components, you will see that green 'ratsnest lines' or 'connections' appear
while the object is being placed It should be fairly intuitive that the longer the ratsnest lines,
the less optimum the components position and this is indeed the case - optimizing component
placement is equivalent to minimizing the total connection length. Unfortunately, solving this
problem is more an art than a science!
• Remember that the '+' and '-' keys will rotate each component whilst you are placing or
dragging it. Combined with the ratsnest display, this gives you a rapid means to
optimize the orientation of each part as you place it.
• Also worthy of note is the fact that this time there is no need to annotate the parts -
when you place U1 it comes out as a DIL08 and there is nothing else to do.
ARES re-calculates the ratsnest not only as components are placed, but also while they are
being dragged. This can mean that ratsnest lines may ‘jump about’ as the component’s pads
move between various possible connection points. It should be obvious, that with something
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ARES
like a decoupling capacitor, the nearest power pins to it will depend on the region of the board
in which it is located.
In addition, ARES shows Force Vectors for each placed component. These appear as yellow
arrows which point to the optimum location for the component. The shorter the force vectors,
the better the overall placement. The force vector for a component being dragged is also
updated in real time, although its effect on the force vectors of the other components is not
shown until it is placed. Once a component is tracked to, its force vector will automatically
disappear.
One final detail is to place the board edge. To do this, select the Graphics icon, the Box icon
and the EDGE layer on the Layer Selector. Then drag out a box for the board edge around all
the components.
You are now ready to begin routing.
Manual Routing
At this point, we suggest that you load the file PPSU.LYT which represents where you
should have got to so far. You will find this file in the "Samples\Tutorials" directory within
your Proteus installation..
You should now see that all Ratsnest interconnections are displayed. Select the Trace icon.
and click left on pin 4 of the op-amp. At this point several things will happen:
• A prompt message will appear in the status bar indicating that you are routing part of
the ground net.
• All three connections connecting to pin 4 will highlight, indicating which pins it is legal
to route to.
• The trace selector will automatically display trace style T25. This is associated with the
net-strategies feature, but for now simply take it that this has been predefined as the
default thickness for power nets.
Note that this only occurs if the Auto-Trace Selection option on the Tools menu is on.
• A green 'rubber' line will appear from pin 4 to the current mouse pointer position - this
shows you where a track segment would be placed if you clicked left.
• Point at the left hand pin of C1 and click left a second time. ARES will sense that you
have completed the route and will replace the connection line with a segment of 25 thou
tracking. Click left on U1 pin 4 again, move up 1 grid square, click left, move over to 1
square above the lower pin of R2 and then down onto the pin.
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Now make the connection for U1 pin 4 to Q2's emitter. In this case, note that you need not
take the route pin to pin - the Advanced Netlist Management features enable ARES to tell
which ratsnest line to remove, even if you take the route from Q2's emitter to the route corner
above U1 pin 4.
The next connection to do is the one from U1 pin 2 to R1. Assuming that we want to route
this on the top side of the board running above the lower row of U1's pins, press the space
bar or else the middle button of your mouse if it has one. This selects the other layer in the
current layer pair - in this case 'Top Copper'. Route the connection as before, noting that the
trace type selected is now DEFAULT as defined in the SIGNAL strategy. Also note that the
trace comes out in red, indicating (with the default colours) that it is on layer C1. Now
complete this net by making the connection to R2
It is in fact possible to route this board with no vias at all. However, for the purposes of
tutorial we shall route the connection from U1 pin 3 to C1 using two vias. Start by selecting
'Bottom Copper', click left on U1 pin 3 and then click left twice at the point two squares below.
Clicking left twice at a point places a via and also swaps the primary and secondary layers.
The via will take on a layer range determined by the current strategy's via mode (normal,
buried or blind). Having got one via, move across to the point two squares above the target
pin, click left twice and complete the route on the underside of the board.
Auto Routing
Using the auto-router is extremely simple - after all the whole point is for the computer to do
the work. To see it in action, start by re-loading PPSU.LYT and then invoke the Auto-Router
command from the Tools menu. The default settings will do for this example board so click on
OK, sit back and watch. The status display at the bottom of the screen shows what is
happening and how things are going. The yellow route is the one being considered for
routing. On modern PCs, this board will route to completion in the twinkling of an eye!
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ARES
Router Strategies
ARES handles the problem of routing different nets with different trace/via widths and so
forth in a very sophisticated and convenient manner. Each net in the design is assigned
(either implicitly or explicitly) a named strategy which defines how it is to be routed. In
practice this means that a net called 12VRAIL can be assigned the POWER strategy on the
schematic but that the details of POWER routing can be left undefined until the PCB begins
to take shape. At the same time, the need to allocate all sorts of separate properties to each
net in the design is avoided.
For a taste of what is possible, invoke the Set Strategies command from the System menu,
select the POWER strategy and then click on the selector toggle. The Edit Strategy form
allows you to determine how nets assigned to this strategy should be routed.
You will see that there are fields for the trace and via styles, the algorithm to use (i.e. POWER,
BUS or SIGNAL), controls for whether diagonals are allowed and whether corners should be
optimized (i.e. cut at 45 degrees). Up to 4 passes are allowed per strategy and each pass can
use different layers. If the H and V layers for a pass are the same then single sided routing will
be attempted.
You can also set individual design rules for each strategy. This can be useful where some
tracks must carry high voltages and need to be more widely spaced than those carrying only
low voltage signals.
Further details on all these features are to be found under NETLIST MANAGEMENT on page
63 and AUTO-ROUTING on page 83.
Power Planes
As an example of the sophisticated power plane capabilities, we will create a simple ground
plane for the PPSU board. Start as follows:
1. Load the file PPSU.LYT.
2. Route it with the autorouter.
3. Select the Connectivity Highlight icon.
4. Select the GND=POWER net in the Object Selector.
5. Click the 'T' for tag toggle on the Object Selector.
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REPORT GENERATION
Aside from Gerber Photoplot and Excellon NC Drill tool information which is really part of the
printing/plotting sub-system, ARES can generate two reports detailing how well the current
layout meets its specification:
• Connectivity Rule Check - Checks for electrical errors (extra/missing connections)
• Design Rule Check - Checks for physical errors (overly small copper clearances)
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ARES
DRC errors will also be flagged if two objects are physically touching but not 'properly'
connected - an example of this would be two pads which overlap but do not have a track
running between them. This type of error will also show up in the CRC report as a missing
connection.
Further details of these reports can be found in REPORT GENERATION on page 99.
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GENERAL CONCEPTS
SCREEN LAYOUT
The Menu Bar
The Menu Bar runs across the top row of the screen and its main purpose (the selection of
commands from the menus) is the same as with any other Windows application. In addition,
the title bar area above the menu names is used to display certain prompt messages which
indicate when the program has entered a particular editing or processing mode.
The Toolbars
As with other modern Windows applications, ARES provides access to a number of its
commands and modes through the use of toolbars. The toolbars can be dragged to any of the
four edges of the ARES application window.
Command Toolbars
The tools located along the top of the screen (by default) provide alternative access to the
menu commands, as follows:
File/Print commands
Display Commands
Editing Commands
Layout Tools
If you are working on a relatively small monitor, you can hide any or all of the command
toolbars using the Toolbars command on the View menu.
Mode Selector Toolbar
The toolbar located down the left hand edge of the screen select the editor mode, i.e. what
happens when you click the mouse on the Editing Window.
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Pad Placement
2D Graphics
Note that the mode toolbar cannot be hidden, as its functions are not duplicated on the
menus.
Orientation Toolbar
The orientation toolbar displays and controls the rotation and reflection for objects placed
onto the layout.
Rotation
Reflection
The edit box allows you type a rotation angle in directly; this is the only way to enter non-
orthogonal angles.
When an existing object is tagged, the rotation and reflections icons highlight in red to show
that they will modify the orientation of an object on the layout. When the icons are not
highlighted, they serve to determine the orientation for new objects.
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this serves as a prompt additional to the state of the Icon Panel as to which mode is current.
The width and position of the Object Selector can be adjusted in conjunction with the width
and height of the Overview Window, as described above.
Co-ordinate Display
The current co-ordinates of the mouse pointer are displayed down at the bottom right of the
screen by default. The read-out can be in imperial or metric units and a false origin may be set.
Further details are given under CO-ORDINATE SYSTEMS on page 30.
The X-Cursor command will display a small or large cross, in addition to the mouse arrow, at
the exact location of the current co-ordinates. This is particularly helpful when used in
conjunction with the Real Time Snap feature, since it gives you an immediate indication of
what ARES thinks you are pointing at.
CO-ORDINATE SYSTEMS
The fundamental unit of linear measurement in ARES is 10nm (ten nanometers). Given 32 bit
representation of the co-ordinates this allows a board size up to +/- 10m (ten meters) with
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some headroom for calculations. The 10nm unit divides exactly into both 1um (micron) and 0.1
thou (one ten thousandth of an inch) giving exact representations of both imperial and metric
dimensions to these resolutions.
Rotational angles are stored to 0.1degree.
The co-ordinate display can be switched to reading metric units by invoking the Metric
command or by pressing the 'M' key. Restoring imperial mode is achieved by invoking the
Metric command again.
Output Origin
For CADCAM output in particular, but also when working on a board which has to fit into a
pre-designed mechanical casing, it is useful to be able to define a reference point on the board
which relates to the mechanical design's co-ordinate system. The output origin defines this
point within ARES, and is drawn in blue on the Editing Window as a target symbol.
• You can re-position the output origin using the Output Origin command.
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• The output origin does not affect the co-ordinates used in Region files.
False Origin
Although the Origin command appears on the View menu, it should only be used via its
keyboard short cut (key 'O'). Its function is to zero the co-ordinate display at the current
mouse position, a feature that is most useful when laying out a complex pattern of pads given
a set of dimensions on a drawing of the component.
When a false origin is set, the co-ordinate display changes colour from black to magenta as a
reminder.
Cancelling a false origin is done by invoking the Origin command a second time.
Grid Dots
A grid of dots is displayed in the Editing Window - this can be toggled on and off using the
Display-Grid command. The spacing of the dots normally equals the current snap setting (see
below), but if you are zoomed out a good way, it will be multiplied by a factor of 2,4,8 etc. The
threshold at which this occurs can be adjusted on the Set Grids command on the System
menu.
Snapping Grids
Although the motion of the mouse arrow itself is smooth, you will see that the co-ordinates
normally jump in fixed multiples of, for example, 50 thou. The size of these multiples is set by
the Snap commands and the purpose of this is to facilitate the placement of objects on a fixed
grid.
Under normal circumstances, boards tend to be routed on a 50 or 25 thou grid.
Three snap grids for each of imperial and metric modes are available at any one time, though
you can redefine their values using the Set Grids command on the System menu. The current
snap options are selectable from the View menu or by using keys F2-F4.
The snapping points are computed starting from the current origin as set by the Set Origin
command. This provides the means to measure out pad placement for a new component, since
you can set the origin at the first pin, set one of the snap values to the pin spacing, and then
advance the cursor along the pad positions using the cursor keys.
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OBJECT PLACEMENT
There are five basic types of object in ARES:
Components
Packages
Pads
Graphics
Zones
All are placed in much the same way - select the appropriate object type from the toolbar and
then click left on the Editing Window to place the object. If you hold the left button down,
you can move the object around before actually placing it. Also, when appropriate, the
Rotation and Mirror icons can be used to pre-set the orientation of placed objects.
Placing Components
ARES makes a distinction between Components and Packages in that a component is a part
specified in the netlist whereas a package is not linked to the netlist, has no part ID, and plays
no part in netlist driven design verification / modification. Assuming you are using a netlist,
99% of the parts you place would usually be components. You would only use packages for
parts which, for whatever reason, were not entered on the schematic. Heatsinks are the most
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common example of this. If a netlist is in use, parts which are not specified in it must not be
given names.
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To place a component
1. Select the Component icon from the Mode Selector toolbar. In this mode, the Object
Selector lists all components not yet placed.
2. Choose the component you want to place from the Object Selector.
3. Set the Rotation and Mirror icons to determine the required orientation.
You can set the rotation to non-orthogonal angles by typing into the text edit-box.
4. Set the Layer Selector to determine the required layer. Note that the Layer Selector and
the Mirror icon are interlocked, since a reflected component must be on the underside
of the board.
5. Point at the desired position for the component on the board and press the left mouse
button.
6. If you hold the button down, you can drag the component around before it is placed; at
the same time, ARES will show ratsnest lines and/or a force vector to indicate how the
component connects to any others already placed.
Further, the '+' and '-' keys on the numeric keypad will rotate the component
anticlockwise and clockwise respectively in steps of 90 degrees.
Components on the underside of the board
When a component is placed on the solder side of the board, it is effectively 'turned over'.
This means that it suffers both a reflection in 2D space and an inversion of the layers of its
pads. More specifically:
• The silk screen legend moves from the Top Silk Screen to the Bottom Silk Screen.
• Pads on the Top Layer only, move to the Bottom Layer and vice versa. This caters for
underside placement of surface mount components.
• Pads on multiple layers - most commonly normal through hole pads - and padstacks are
left alone. On the assumption that a padstack has been defined in a particular way to
reflect the usage (signal, ground plane, etc.) of a particular layer, it would be unhelpful
to invert pad stacks for solder side placements.
Packages
As discussed above, the term Package is used to refer to a placed library part which has pins
but is not linked to the netlist. In ARES, they are useful in the following circumstances:
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• If no netlist is available, or you are doing a simple 'quick and dirty' job, you can lay out a
board by placing packages and wiring them up using traces and vias. In doing this, you
are using ARES as a computerised light box, rather than as a true EDA tool.
• Sometimes you need to place objects which have pads and graphics but are not actually
components in the electrical sense of the word. Heatsinks with mounting holes are a
common example of this. These can be placed as unlabeled packages, and as such, will
play no part in the netlist driven functions of the design work.
• In order to edit a library-package, it is necessary to place it as a package, tag it and then
decompose it using the Decompose command. The individual elements can then be
edited as required prior to re-making the library-package using the Make Package
command.
To place a package
1. Select the Package icon from the Mode Selector toolbar. In this mode, the Object
Selector lists all the packages picked from the libraries.
2. Assuming that the package you want has not yet been picked from the libraries, click the
'P' for pick toggle on the Object Selector.
3. Pick the package or packages you want from the Library Pick Form.
4. When you have finished picking packages, close the form in the usual way.
5. Highlight the package you want to place in the Object Selector.
6. Proceed from step [3] in To place a component above.
& Some further information on creating library-packages is available under THE
PACKAGE LIBRARY on page 58.
Pads
The main reason for placing lone pads is when defining a new library-package but they are
also useful for test points, drilling alignment targets and such like. ARES offers five shapes of
pad, namely: Circle, Square, DIL, SMT and Edge Connector.
In addition, ARES supports pad stacks, in which a different pad shape can appear on each
layer of the board.
The various pad shapes may be selected from the Mode Selector toolbar.
Given the selection of a pad shape, an actual pad style of that shape may be selected from the
Object Selector. You'll see that all the pad styles have names - this is a unique feature of
ARES and has two advantages over other systems:
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• There is less chance of confusion or error when choosing a style (provided that you use
sensible names!).
• There is no limit to the number of styles you can have.
Pads are placed in much the same way as components and packages. The Rotation icon
affects the placement of DIL, SMT and Edge Connector pads whilst the Layer Selector again
determines the layer-set of the pads.
You can edit a pad style by selecting it in the Object Selector and then clicking on the toggle.
Any changes to the pad dimensions take effect as soon as the display is redrawn - you can
force a redraw with the Redraw command. This feature is particularly powerful should you
find the need to tweak pad styles globally in order, for instance, to change the pad sizes used
in the standard package library.
New pad styles may be created using the New Pad Style command. See Style Management &
DEFAULT.STY on page 55 for more information on styles.
2D Graphics
The 2D drawing facilities are intended, in the main, for adding text and graphics to the silk
screen layers though they can also be placed on other layers. Objects placed on the Edge
layer appear on artwork produced from any of the other layers making it a suitable location to
draw the board outline.
There are 8 types of 2D graphic object, namely:
Line
Box
Circle
Arc
Path
Text
Symbol
Marker
The corresponding icons are contained in the Mode Selector toolbar.
• Lines are drawn by clicking left at each end.
• Boxes and circles are dragged out using the left button.
• Arcs are placed dragged out into a quadrant using the left button. They can be further
adjusted by tagging and dragging the four handles. ARES arcs are actually Bezier
curves.
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• Paths are closed figures with boundaries defined as multiple line and arc segments. Click
left at each required vertex and hold the CTRL key down to place arc sections. Further
adjustments may be made by tagging the path and moving the ‘handles’ about.
We strongly recommend that paths are not used to create copper fills as they are not-
recognized by the connectivity database. Use zones instead.
• Text is placed by clicking at the bottom left corner of the text region. A form then
appears which allows input of the text itself and also allows control of the text
dimensions. Text orientation can be set using the Rotation and Mirror Icons.
• Selecting the Symbol icon displays symbols in the Object Selector. Symbol selection is
identical to package selection as described earlier. More information on the symbol
library facility is contained in THE SYMBOL LIBRARY on page 62.
• Markers are used in the creation of library parts to define the origin, and also the
position for component labels.
Zones
Zones represent the means by which ARES handles power planes. In this section we will just
describe briefly how to place a simple power plane; further documentation on power planes is
given under POWER PLANES on page 91.
To place a simple power plane
1. Select the Zone icon from the Mode Selector toolbar.
2. Select the required boundary trace style for the zone from the Object Selector.
3. To define the zone boundary, either:
• Drag out a box with the left mouse button held down.
• Click at several points to form a polygonal boundary.
If a zone boundary is placed over existing tracking, it will pick up its net from that
tracking. This makes it quite easy to place lots of small zones in order to ‘fill in’ between
tracks.
4. Select the required net and hatch/fill style from the Edit Zone dialogue form, then click
OK.
5. ARES will generate the ground plane.
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OBJECT EDITING
Due to is its object oriented design, all objects in ARES are treated in much the same way and
we can discuss generally their dragging, copying, movement, rotation, deletion and editing.
You should note that traces and vias are not regarded as objects for this purpose; their
editing is dealt with further under Manual Routing on page 21. However, there are operations
where traces attached to objects are affected by operations performed on the object - such
cases are discussed here.
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Performing an explicit Redraw command (key 'R') will also untag all objects - this can be
handy if the board is very densely packed and there is nowhere free of objects on the screen.
Deleting an Object
Any tagged object can be deleted by pointing at it and clicking right. Any traces connected
to its pads will remain in place, allowing a different pad or package to be placed over them.
Dragging an Object
You can drag (i.e. re-position) any tagged object by pointing at it and then dragging the
mouse with the left button depressed.
Any traces attached to the object will be rubber banded (stretched) unless both ends connect
to it, in which case the route will be moved wholesale.
Editing an Object
Some objects, especially packages, components and graphics text have properties that can be
edited with a dialogue form. There are two ways to do this:
• A tagged object can be edited by pointing at it and then clicking left as if to drag it but
without moving it.
• If you have several objects to edit it may be more convenient to select the Instant Edit
icon. Clicking left on any editable object will then bring up its dialogue form.
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route is placed across several others which you failed to see. If such a violation is detected
ARES displays an error message and the tracking will be marked as dirty. Dirty tracking
flashes between bright yellow and its normal colours, except when it is tagged.
When Auto Track Necking is enabled, ARES also checks for physical design rule violations.
In the first instance, it will neck the track to avoid them, but if there is still a violation then it
displays a warning message and beeps. The route is, however, placed. This process can take
some time, and if you find that trace placement is becoming unduly tardy, you can try
disabling ATN from the Tools menu.
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To disable ATN totally, use the toggle command on the Tools menu. You may find this
speeds up route placement considerably, since the analysis involved in performing ATN can
be quite complex, even if the end result is that the route is OK.
When Trace Angle Lock is enabled, clicking over a pad or track in this circumstance will
activate Trace Angle Fixup. The result is that the previous node - in this case the route
corner, is moved so that trace angle lock rules can be maintained. The result is a tidy
connection as shown below overleaf.
Trace Angle Lock & Fixup are active by default. You can disable or re-enable them using the
Trace Angle Lock command on the Tools menu.
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Tagging a Route
To re-route, delete or copy a section of tracking requires that you first tag the route
containing it.
To tag a route
1. Select the Trace icon from the Mode Selector toolbar.
2. Set the Layer Selector to the layer on which the trace lies.
3. Point at a part of the route on the selected layer, and click right.
If you click on a via, or pin, or a point at which three or tracks meet, all the tracking originating
from that point will be selected.
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Modifying a Route
To rubber band a section of tracking
1. Tag the route as described under Tagging a Route on page 45.
2. Drag the segments and/or corners of the route using the left mouse button.
If you drag horizontal or vertical segments, they will move vertically or horizontally
respectively with adjacent segments between stretched to accommodate this. On the other
hand, if you drag on the route corners, then the adjacent segments will simply stretch
diagonally. Finally, if you drag in the middle of diagonal segments, a new corner will be
created.
To re-route a section of tracking
1. Tag the route as described under Tagging a Route on page 45.
2. Place a new section of tracking starting and finishing on the tagged route. ARES will
then remove the section of tracking that the new route shorts out.
Note that vias which are made redundant (i.e. secondary vias) will also be removed, along
with the shorted out section.
Copying a Route
To duplicate a route
1. Tag the route as described under Tagging a Route on page 45.
2. Click right on the tracking to display the context menu.
3. Select the Copy command.
4. Click left at each position for the duplicate routes; click right to finish.
This feature provides an excellent way do memory buses and other repeated patterns of
tracking.
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Deleting a Route
To delete a route
1. Tag the route as described under Tagging a Route on page 45.
2. Click right to display the context menu.
3. Select the Delete command.
Any interconnections specified in the netlist that were formed by the deleted tracking will
automatically appear as ratsnest lines.
Note that you can also delete all tagged tracking by using the Block Delete icon. This can be
quicker than the above procedure if no other tracking is tagged.
Block Copy
After creating a tag-box as described in Tagging a Group of Objects on page 39, clicking on
the Copy icon will cause a second box to appear over the tag-box which you can then
re-position using the mouse. Clicking left will cause a copy to be made of the objects within
the tag-box whilst clicking right will abort the operation.
Traces are only copied if both ends of them are inside the tag-box.
Beware that copying components will generally leave the netlist management out of kilter as
there will be multiple placements of the same component references. If, having routed a
module that is to be repeated several times, your intention is to copy it out to save re-routing,
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you should use the Auto Name Generator to renumber the components in the copied
section(s) and then re-load the netlist.
Block Move
After creating a tag-box as described in Tagging a Group of Objects on page 39, clicking on
the Move icon will cause a second box to appear over the tag-box which you can then
re-position using the mouse. Clicking left will cause the tag-box and its contents inside it to
be moved whilst clicking right will abort the operation.
Trace segments with one end only inside the tag-box will be rubber-banded.
Block Rotate
After creating a tag-box as described in Tagging a Group of Objects on page 39, clicking on
the Rotate icon will allow you to rotate and/or reflect the block by any angle.
• Trace segments with one end only inside the tag-box will be rubber-banded although
this generally leaves something of a mess - it's best to rotate only completely enclosed
sections of a layout.
• Rotation of whole groups of components to non-orthogonal angles (even 45°) creates
large numbers of off grid pads. Routing such boards can be very tricky, even with
features such as real time snap and trace angle fixup.
The autorouter, being grid based, will also perform poorly under such circumstances.
Block Delete
After creating a tag-box as described in Tagging a Group of Objects on page 39, clicking on
the Delete icon will delete all tagged objects.
Remember that you can tag objects and tracking in a number of ways:
• Using the right mouse button to select objects individually.
• Using the tag-box and tag-filter to select specified objects within an area.
• Using connectivity highlight to select tracking on particular nets, or running from
particular pins - see page 66 for more information.
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FILING COMMANDS
ARES makes use of the following file types:
Layout Files (.LYT)
Backup Files (.LBK)
Region Files (.RGN)
Library Files (.LIB)
Netlist Files (.SDF)
Layout files contain all the information about one board, and have the file extension 'LYT'.
They contain within them copies of all packages and styles used on the board, so the
complete design can be given to someone else solely by giving them a copy of the layout file.
Backup copies of layout files made when saving over an existing file are given the extension
"LBK".
A region of a board can be exported to a region file and subsequently read into another
layout. Region files have the extension 'RGN' and are read and written by the Import and
Export commands on the File menu. They are analogous to section files in ISIS. ARES region
files are in an ASCII format and for the advanced user, this opens the possibility of manually
editing the layout database, or else writing utility software to perform specialist operations on
it. Import of data from other PCB design packages is also a possibility. Contact our technical
support department or look on our Web Site if you want a copy of the format specification.
Package and symbol libraries have the extension 'LIB'. 6 libraries are supplied:
PACKAGE.LIB Standard through hole footprints
SMTDISC.LIB Discrete SMT footprints
SMTCHIP.LIB IC SMT footprints
USERPKG.LIB For your own footprints
SYSTEM.LIB Standard symbols
USERSYM.LIB For your own symbols.
Full details of library facilities are given under LIBRARY FACILITIES on page 57.
Native format netlist files have the extension 'SDF' standing for Schematic Description Format.
Netlisting features are covered in detail in NETLIST MANAGEMENT on page 63.
Loading a Layout
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Saving a Layout
You can save a board when quitting ARES via the Exit option, or at any other time, using the
Save Layout command.
• In both cases it is saved to the same file from which it was loaded; the old file being
re-named. On the first occasion that the file is saved, it is renamed to "Last Loaded
<filename>.LBK" whilst on subsequent occasions it is renamed to "Backup of
<filename>.LBK". This means that a copy of the file as it was at the start of an editing
session is always preserved.
• If no filename was given at load time or the New command was issued, the name
'UNTITLED.LYT' is used.
The Save As command allows you to save the layout to a file with a different name.
Import / Export
The Export Region command creates a region file out of all currently tagged objects. This file
can then be read into another layout using the Import Region command. After you have
chosen the region file, operation is identical to the block-copy function.
Some difficulty may arise if an attempt is made to import a region saved from a layout in
which the pad/trace/via styles in use are different from the current one.
A common difficulty arises from exporting a region file from a design where you have made
local changes to pad/trace styles. Region files do not save this information and so when you
import the region file all pad/trace styles will revert back to their default values. The solution
of course is to create new styles in the first instance reflecting the modifications that you
want to make. You can then safely create your board and export/import it via region files into
other designs.
Region files may also be loaded using the Load command, and this is done to facilitate the
loading of data produced by the external converters DXFCVT and GERBIT.
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Note that region files are not good way to panelize multiple boards for manufacture because
netlist information is lost and imported ground planes will lose connectivity as a result. The
Gerber Viewer provides a much better way to perform panelization.
Auto-Save
ARES has an auto-save facility whereby your work will be backed up automatically at regular
intervals. The interval defaults to 15 minutes and can be changed using the Set Environment
command on the System menu.
Should ARES terminate unexpectedly, the next time it starts it will look for the auto-save file
from the previous session and prompt to reload it.
The auto-save file will be stored in your Windows temporary directory, normally addressed
by the environment variable TEMP. PROTEUS auto-save files have the extension ‘ASV’.
This feature is not an excuse for not saving and backing up regularly - there is no
guarantee that the auto-save file will be recovered in all cases.
Pad Styles
ARES supports 7 types of pad, namely:
Circular PTH
Square PTH
DIL PTH
Circular SMT
Rectangular SMT
Polygonal SMT
Edge Connector
and the list of styles defined for each type displays in the Object Selector whenever the
appropriate pad icon is highlighted.
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When one of these lists is displayed, you can edit an existing pad style by highlighting it in
the selector and then clicking on the selector toggle (the 'E' symbol). All fields on the
resulting dialogue form have context sensitive help associated with them.
Polygonal Pads
ARES supports a user defined, polygonal pad style in order to cater for parts requiring
unusual pad shapes.
To define a new polygonal pad style
1. Using the 2D graphics Line, Arc or Path icons, draw a closed path to define the shape of
the new pad style. It does not matter which layer you draw on for this purpose.
2. Place an Origin marker within the closed path to specify the origin of the pad style. The
origin is used as the connection point for tracking, and also serves as the point of
alignment if the pad style is used within a pad stack.
Note that the origin must lie within the closed boundary i.e. within the copper area of the
pad.
3. Tag the 2D graphics and origin marker by drawing a tag-box with the right mouse
button.
4. Invoke the New Pad Style command from the Edit menu.
5. Enter a name for the new pad style.
6. Set the Polygonal pad style type under SMT.
7. Click OK.
8. Specify a Guard Gap for the pad style, if required.
9. If you wish to create the style only in the current layout, and not in DEFAULT.STY,
then select Local Edit instead of Update Defaults.
10. Click OK to create the new pad style.
Note that there is no method to change the outline of a polygonal pad once it has been made -
you must re-define it from scratch.
Pad Stacks
The ordinary through hole pad styles can be placed on a single layer or on all the copper
layers, but this does not provide a very convenient or satisfactory method for defining
component pins which have different pad shapes on different layers. In particular, the ARES
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connectivity system does not recognize connectivity between single layer pads on different
layers.
Instead, ARES provides the facility to define Pad-Stacks. There are several points about a
pad stack:
• A pad stack can have a circular hole, a rectangular slot or be surface only. The latter
type of pad stack is used where you wish to defined explicit styles for the solder resist
and/or solder paste mask apertures.
• For each layer, you can assign a different pad style, or no pad.
• For obvious reasons the hole or slot diameter of a pad stack is the same for all layers.
• You must use a pad stack to create a pad shape with a slotted hole. You cannot specifye
a slotted hole in an ordinary pad style.
To define a new pad stack
1. Select the Create New Pad Stack command from the Edit menu.
2. Enter a name for the pad stack, and a default pad style. All layers will start out with this
style of pad.
3. Click OK to proceed to the Edit Pad Stack dialogue.
4. On this form, you can adjust the pad-layer assignments, and also assign the layer-global
drill mark and drill hole/slot size.
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Guard Gap
Note that in the case of a pad stack, you can define the pad style used for the top and bottom
resist layers explicitly, using the selectors in the Edit Pad Stack dialogue form. Note that the
guard gap of this style is still applied in determining the final size of the aperture.
You can also specify a pad stack which has no solder resist - i.e. the pad will be covered by
the resist coating.
Trace Styles
Currently there is just one trace style, though in the future we may implement additional types
for micro-strip etc. The available trace styles are displayed when the Trace icon is selected.
You can then edit any the styles by highlighting its name and clicking on the selector toggle.
Trace styles have a single attribute which defines their width.
New trace styles can be created using the New Trace Styles command on the Edit menu.
There is no way to delete trace styles once they have been created.
Via Styles
Via styles are much the same as pad styles except that only circular or square vias are
permitted. The list of via styles is displayed when the Via icon is selected.
New via styles can be created using the New Via Styles command on the Edit menu. There is
no way to delete via styles once they have been created.
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LIBRARY FACILITIES
Library Discipline
USERSYM.LIB and USERPKG.LIB are set to read/write; the rest are set to read-only. The idea
is that you should only add things to USERSYM.LIB (new symbols) and USERPKG.LIB (new
packages). This means that we can supply you with updates to the parts we have defined
without risk of overwriting similarly named objects in your own libraries.
If you must change things in the read-only libraries, you can set them to read/write using the
Properties command in File Manager under Windows or with the DOS ATTRIB program.
The command
ATTRIB filename -R
sets a file to read/write whilst
ATTRIB filename +R
sets a file to read-only. Wildcards may also be used.
The Library Manager also includes an option to toggle the read/write status of libraries.
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Making a Package
To make a new library package:
1. Select the appropriate pad shape icons and place the pads of the package as required.
Use the Layer Selector to place the pads on the appropriate layers. See below for more
information.
2. By default, ARES will give the pins numbers from '1' upwards, numbering them in the
order they were placed. If this is not what is required, you must either renumber them
with the Auto Name Generator, or else edit them manually. See below for more
information.
2. Select the appropriate 2D graphics icons and place silk screen graphics as required. A
package can have legends on both the component side and solder side screens; these
will be swapped if the package is placed with the mirror icon active.
3. Tag all the objects by dragging a box round them.
4. Invoke the Make Package command on the Edit menu, type in a name and select the
library to store it in. The package will then be stored in the chosen library and added to
the contents of the Object Selector, ready for immediate placement.
5. The reference or 'anchor point' for a package can be determined by placing the ORIGIN
marker. If there is no ORIGIN marker, the reference will be the centre of first pin placed.
Markers are accessed by selecting the Marker icon.
6. It is also possible to define non-default positions for the reference and/or value labels.
To do this, place the REFERENCE or VALUE markers at the required position(s).
Choosing the Correct Layers for the Pins
Ordinary pad styles can be placed on single copper layers, or on all the copper layers as
defined by the current setting of the Layer Selector.
• For ordinary through hole parts, you should place the pads on all the layers.
• For SMT parts, you should place the pads on the top layer only. If such a part is placed
on the Solder Side, the pads will be automatically transferred to the bottom copper layer.
• For doubled sided edge connectors, you should place separate fingers on both the top
and bottom copper layers.
• If you need different shaped pads on different layers for a through hole pin, you should
use pad stacks as defined under Pad Stacks on page 52.
The Replicate Command
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Pin Numbering
When a netlist is loaded, ARES attempts to match pin numbers appearing in the netlist with
the pin numbers assigned to the pins of the component packages. Where a match cannot be
found, this is an error and either the ISIS library part or the ARES library part must be
changed.
When you are defining an ARES library part, there are three ways to control the pin
numbering:
• By default, the pins will be numbering from '1' upwards in the order that they were
placed.
• If you invoke the Auto Name Generator command on the Tools menu, you can then
click on the pads in any order you like to assign incrementing pin numbers.
• If you select the Instant Edit icon, you can click on each pin and key in the pin numbers
manually.
Note that trying to use a mix of default and manual pin numbering is likely to lead you to
confusion and mistakes.
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Other Points
ARES normally chooses locations for the part ID and value; these labels can always be
moved after a part has been placed by tagging it, pointing at the label you wish to move, and
dragging with the left mouse button depressed. The locations chosen will generally be good
enough as is, unless many components are closely packed together.
However, if you wish to force the label to a particular default position, you can use the
REFERENCE and VALUE markers, as described above.
The size of the labels is set by the Set Template command on the System menu. This will
apply globally except for labels whose size has been manually edited.
Editing a Package
To edit an existing library package,
1. Select the Main Mode and Package icons.
2. Pick the package to be edited from the library (using the toggle on the Object Selector)
and place it on the work area.
3. Tag the package and then invoke the Decompose command from the Edit menu. This
will break the package into its constituent pads and 2D graphics and also place an
ORIGIN marker at the location of the part's placement reference.
4. Edit the pads and graphics as required.
5. When you have finished you can use the Make Package command to re-store the
package either with the same name as before, or as a new part.
Of course, if the original package came from PACKAGE, which is normally read only, you will
have to store it back to USERPKG. We recommend against using Library Manager to re-
copy the part to PACKAGE as this can cause problems when we issue a new PACKAGE.LIB -
how are you going to sort out which parts have been edited by you in order to preserve
them?
Note that the pins will carry the pin numbers from the original package so decomposing a
DIL14, sticking two pins on the end, and then re-making is not the way to make a DIL16
unless you are prepared the to re-number all the pins manually.
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A symbol may be created by tagging the objects you wish to form it and then invoking the
Make Symbol command on the Edit menu. Layers are ignored for this purpose. A form will
appear allowing you to name the symbol which will then be stored in the Symbol Library and
made available for immediate placement from the Object Selector. If there is already a symbol
with the same name, it will be replaced.
ARES quite happily allows a symbol to contain other symbols and/or other graphic objects.
This allows you to make, for instance, a NAND gate out of the previously defined AND gate
plus a circle.
As with packages, the placement reference for a symbol may be determined by placing an
ORIGIN symbol.
ISIS and ARES symbols are essentially exchangeable, and all symbol libraries have the type
'PROTEUS SYMBOL LIBRARY'. However, ARES does not support all of the drawing
appearance features of ISIS, so correct rendering of ISIS symbols with complex fill patterns is
not guaranteed, especially for CADCAM output where we can say with some certainty that it
will not work !
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NETLIST MANAGEMENT
NETLIST FEATURES
A netlist produced using ISIS or some other schematic capture package contains as a
minimum, a list of the components used in the design and a specification of how their pins are
to be connected. The ability of ARES to use this kind of information distinguishes it from
budget packages which provide what amounts to a computerized version of rub-down
transfers and drafting film.
Our own netlist format is called SDF which stands for Schematic Description Format. As well
as component name and connectivity information, an SDF file can also detail information
concerning the package to be used for each component and the routing strategy to be used
for each net. As a result, it is possible to completely specify a PCB with an SDF file (and
therefore from within ISIS), save for the physical positions of the components and the
detailed routing of the interconnections.
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ARES checks to see if the library package specified for a component in the netlist matches
that of the placed component on the layout. If the specified package differs, one of two things
will happen:
• If the new package has the same number of pins as the existing one, then a replacement
will occur such that the new package is placed with its pin 1 lying over the old package's
pin 1. The component is tagged to highlight the fact that something has happened to it.
• If the new package has a different number of pins, the component is removed from the
layout and added to the Object Selector for manual replacement.
Unannotated packages are ignored by the netlist loader. This makes them a suitable way to
place footprints for parts which, for whatever reason, you do not want subject to full rigors of
netlist based design. You should also note that because their pins are not specified in the
netlist, they can be connected to anything without CRC violations occurring.
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in the library package then it displays an error message box and you must click OK to
acknowledge. Problems in this area usually arise from one of the following causes:
• Specifying the wrong package - e.g. a bipolar transistor outline for a regulator.
• Failing to manually number pads which require non numeric 'numbers'. A typical
example might be a DIN connector which has pin numbers like A1, A2 etc. Remember
that by default, ARES always numbers the pads in the order you placed them.
• Leaving spaces on the ends of ISIS device pin names/numbers or in ARES pin numbers.
This can be checked by editing the relevant object and examining closely the state of
the baseline of the Data Entry Field on which the text sits. If there are any gaps in it,
these designate the presence of spaces.
If you use the Packaging Tool in ISIS when creating new library parts, you should avoid any
of the above problems.
Packaging Considerations
At some point during the design process, it is necessary to specify the library-package to be
used for each component. With the ISIS/ARES system, this can be done:
• At the ISIS end by storing the package name in the PACKAGE property. This can be
done either manually by editing each part in turn, or automatically using the Property
Assignment Tool and/or ASCII Data Import facilities
This approach is by far the preferred one as it avoids having to re-enter data each time
the netlist is loaded.
• At the ARES end as the netlist is loaded.
In the latter case, ARES will prompt you for the package name to use for each component in
the netlist.
A limited facility is provided to automate this process for commonly used parts - the file
DEVICE.XLT can contain lines specifying device/package pairs such as
7400, DIL14
To use this feature, you must check the Enable Device->Package Lookup checkbox on the
Environment Settings dialogue form. This command resides on the System menu.
You can then add entries to the DEVICE.XLT file either with a text editor or by selecting the
Store button on the package input dialogue form.
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Connectivity Highlight
Connectivity Highlight mode is selected by clicking left on the Connectivity Highlight icon.
You can then:
• Highlight/tag a group of pads, tracks and vias connected to a pad by clicking left on the
pad.
• Highlight all pads, tracks and vias connected to a net by selecting the required net from
the Object Selector and then clicking left on the 'T' toggle.
• Delete all tagged pads, tracks and vias by clicking left on the Delete icon. Combined
with the above this provides the means to rip up all tracking associated with a given net.
• Untag all pads/tracks/vias by clicking right at a point where there is no object or else by
invoking the Redraw command.
RATSNEST FEATURES
The term Ratsnest is used to describe the pattern you get on the screen when the pin to pin
connections specified in the netlist are shown as single straight lines rather than copper
tracking. Once a netlist has been loaded and the components placed (or vice versa for that
matter) the ratsnest gives a good visual impression of the complexity of the routing task that
is before you or the autorouter. Furthermore, it gives an indication of the quality of
component placement since the presence of lots of long ratsnest lines suggests that some
components would be better placed closer together.
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Force Vectors
Force vectors are provided as a further aid to component placement. They appear as yellow
arrows which point from the centre of each component to the point where it’s ratsnest length
(as defined by its current ratsnest lines) would be shortest. Another way of thinking about
them is to consider each ratsnest line as a rubber band. The force vector then points to the
place where the component would move to if released (strictly speaking this would also
depend on the elastic linearity of the rubber bands, but we won’t get into that - it’s a good
analogy!)
One oddity that can arise is that if you move the component to the position marked by the tip
of its force vector, the ratsnest itself may change because a better minimum spanning tree
may then be found. This can mean that the force vector then points to somewhere slightly
different. We do not regard this as solvable; most PCB packages do not re-optimize the
ratsnest after each edit, so such effects would not be so obvious - but they are still there.
The force vectors can be turned off by using the checkbox on the Layers dialogue on the
Display menu.
Ratsnest Mode
Ratsnest mode is selected by clicking the Ratsnest icon. You can then
• Specify connections manually - useful if you are working without a schematic but still
wish to use the auto-router.
• Perform pin and gate-swaps (where legal) by dragging tagged ratsnest lines from one
pad to another.
• Tag a connection by pointing at it and clicking right.
• Tag all the connections for one net by selecting the net in the Object Selector and
clicking left on the 'T' toggle.
In conjunction with the autorouter's ability to route all, tagged or untagged connections,
ratsnest mode gives you the means to autoroute the board selectively.
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Note that where component pads are on single layers, you must use the layer selector to
select the correct layer for each pad. If a ratsnest line must change layer, then you can press
the SPACE bar to toggle between top and bottom whilst placing the ratsnest line.
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PIN_SWAP/GATE SWAP
When used in conjunction with ISIS, ARES supports pin-swap/gate-swap changes to the
connectivity whilst the layout is being routed. This means that you can choose to
interchange the wiring to like pins, and/or interchange the use of like elements of multi-
element parts. A full discussion of how to prepare your library parts to exploit this feature is
given in the ISIS manual, but from the ARES side there are two ways of using this feature:
Manual Pin-Swap/Gate-Swap
To perform a manual pin or gate swap
1. Select the Ratsnest icon.
2. Click right on the source pin. For a gate-swap, this can be any member of the gate. The
ratsnest lines connected to the pin will highlight. In addition, legal destination pins will
also highlight.
3. Hold down the left mouse button and drag the ratsnest lines to the required destination
pin.
4. Release the left button. ARES will make the change, updating the ratsnest and force
vectors as appropriate. In the case of a gate-swap, ARES will move other ratsnest lines
automatically.
It is possible to combine a pin-swap and a gate-swap in one operation - for example, swapping
input A gate 1 (pin 1) with input B gate 2 (pin 5) on a 7400 will do just this.
WARNING
Pin-swaps and Gate-swaps constitute changes to the connectivity of your design. ARES
uses the pin-swap and gate-swap data specified in the ISIS libraries to decide what is, and
is not, a valid swap. If there are errors in this data, then ARES may well suggest illegal
swaps. We will not, under any circumstances, be held liable for any costs incurred or losses
arising as result of such mishaps, whether the error be in your library parts or ours or in
the software itself. We strongly recommend that you check that the swaps you make are
really legal, and that your prototype your PCB prior to the manufacture of large
quantities.
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ROUTING STRATEGIES
In ARES a strategy defines everything about how the nets assigned to it are to be routed.
This information includes:
• The trace and via styles to use.
• The via type to use - normal, buried or blind.
• Assorted controls for the auto-router.
• The design rules for nets routed with this strategy.
The beauty of encapsulating all these properties in a single entity and then assigning nets to
it as opposed to assigning the properties separately to each net is that it greatly reduces the
amount of information that need be entered on the schematic.
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Editing a Strategy
Strategies are created automatically by the Netlist Loader as their names are encountered.
However, you will normally then need to edit them in order to set the various fields to
whatever you require.
Strategies may be edited using the Set Strategies command on the System menu.
The meaning of the various fields is explained below:
Name
Selects the strategy being edited. Selecting a different strategies saves the changes made to
the current one.
Priority
This is used by the auto-router - connections assigned to the highest priority (smallest
number) strategy will be routed first. Strategies with the same priority will be routed
simultaneously. This will probably result in the router spending much more time 'mapping',
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but may lead to higher completion rates than routing them in turn, especially on single sided
boards.
Trace Style
The name of the trace style to be used for connections assigned to this strategy.
Via Style
The name of the via style to be used for connections assigned to this strategy.
Power/Bus/Signal Switch
This is used by the auto-router as a guide to the type of connections to be made.
Corner Opt
This button determines whether the auto-router is to optimize corners by cutting them at 45
degrees.
Diagonal
This button determines whether the auto-router is allowed to use diagonal routes.
Pass H / Pass V
Each strategy can involve up to 8 layers on which connections assigned to it will be routed
by the auto-router.
The (H) layer is for predominantly horizontal routes and the (V) layer for predominantly
vertical routes. Single sided routing can be achieved by specifying the same layer for both H
and V routes.
Neck Style
If not blank, this field enables Auto Track Necking for the autorouter, and defines the style
which it will neck to.
Design Rules
These fields specify the minimum clearances allowable for nets that are associated with this
strategy. In the case that tracking on two nets with different strategies is in proximity, the
smaller clearances are used .
Hide Ratsnest
Check this box if you wish to hide the ratsnest lines for nets that are associated with this
strategy.
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BACK ANNOTATION
Back annotation is the process whereby changes to the component annotation on the PCB
can be fed back into the schematic. This would normally be done if it was felt that a particular
order of annotation on the PCB would aid the production department in making the board. In
fact, the most natural order for this purpose is if the placement path for placing the
components in successive order is a minimum.
Manual Re-Annotation
It is perfectly possible to re-annotate the board manually by editing each component
reference label as required. PROTEUS uses internal unique identifiers to track ‘was-is’ data so
it does not matter what changes you make, in what order, or when they are eventually read
back into ISIS.
The only restriction is that it is not advisable to renumber connectors made from Physical
Terminals in ISIS. This is because ISIS cannot re-annotate them - it would involve it finding
not only the terminals but also the references to the part name in the *FIELD blocks. The
work around is to manually re-annotate in both ISIS and ARES. A warning to this effect is
displayed if you attempt such a change.
Automatic Re-Annotation
Should your sole aim be to renumber the components to give a geometrically sensible
placement order, then the Component Re-Annotator command on the Tools menu will do this
for you.
The process starts at the top left of the board and proceeds for all components picking the
next nearest one not yet processed.
Back-Annotation to ISIS
Both changes to the component numbering and also changes to the connectivity caused by
pin-swap/gate-swap operations will be automatically picked up by ISIS. This works whether
ARES is running or not.
You have a choice of allowing these updates to occur entirely automatically (in which case,
your PCB will be saved when you switch to ISIS) or to do it manually, in which case ISIS will
prevent you from editing the schematic until the PCB is saved. This choice appears on the Set
Environment command on the System menu in ISIS.
Further discussion of this mechanism is provided in the ISIS manual in the chapter entitled
ISIS AND ARES.
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REVERSE NETLISTING
ARES can create a netlist from a placed and routed PCB. This has a number of uses:
• As a way to check the wiring where no schematic is available.
• In cases where you wish to re-route a board, without risking changing its connectivity,
and do not have the schematic.
• As an aid in reverse engineering designs brought in from Gerbit or elsewhere. (Some
day we may allow you to load the netlists back into ISIS!).
• As a debugging aid where there is some doubt about whether the PCB corresponds
with the schematic.
To create a netlist from a PCB
1. Load the PCB in the usual way.
2. Invoke the Save Netlist command from the File menu.
3. Choose a filename for the netlist.
4. Click OK
In cases where the layout file already contains a netlist, the net-names used in this netlist will
be used. Otherwise numeric net names will be generated automatically.
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AUTO-PLACEMENT
INTRODUCTION
As well as an auto-router, ARES incorporates an algorithm for automatic component
placement. As with auto-routing, this may not perform as well as a human operator in all
circumstances but on the other hand it can save an enormous amount of time an effort. In
addition, the resulting placement can usually be ‘hand tweaked’ - perhaps more so than can
be said of auto-routed tracking. At any rate, we would recommend that most users at least try
the auto-placer as a way of quickly achieving a starting point.
The overall system is now sufficiently developed that small-medium complexity boards such
as our CPU sample can be converted from schematic to PCB with no human interaction
whatsoever!
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9. Move and rotate the components as required and start the auto-placer again.
10. Once you have finished with the auto-placer manually place any remaining components
and start routing.
Design Rules
The Placement Grid defines the step size used by the auto-placer when trying to find a
position for each component. This should always be set to a multiple of the grid size you are
going to use for auto-routing. Values other than 100th, 50th or 25th would be highly unusual.
The Edge Boundary defines the minimum distance to be allowed between any component
and the edge of the board as drawn on the edge layer.
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the use of auto-placement. Secondly you can give the auto-placer a helping hand by telling it
which components are to be grouped together.
A particular problem arises with decoupling capacitors since the auto-placer will, other things
being equal, tend to place all of them in one place since this will give the most routable
solution! To prevent this you can use the GROUP property in ISIS. If the decoupling
capacitor C1 is intended to decouple the chip U1, then you should add the property
GROUP=U1
to the capacitor. Then, when the placer comes to place C1, it will give high costs to positions
which are far from U1 and a placement close to the device will result.
If a number of components are to be grouped together they may all be given a common group
name, rather than a component name, i.e. to group U1, U2, U3, C1 & C5 together you could
add the property “GROUP=TIMER” to each component.
Hint: To add properties to a large number of components use the Property Assignment Tool
in ISIS.
Ratsnest Length
Arguably the most important weighting factor in terms of routability, this assigns importance
to the minimisation of the length of inter-connectivity of components before routing. Note
however that in our experience this should be balanced with some knowledge of the number
of ratsnest crossings. A board with short total ratsnest length and a large number of
crossings can often be unroutable.
Ratsnest Crossings
This weighting defines the importance of minimising the number of ratsnest lines which cross.
As a component is moved around the board the ratsnest length and number of crossing
changes, both of these factors will affect the overall routability of the final placement. It is
important to get a good balance between this and ratsnest length.
Congestion
Small components such as resistors and capacitors may be encouraged to avoid highly
congested areas of the board by increasing the importance of the congestion weighting. Note
that when a small component has been associated with another component via the GROUP
property congestion is ignored for that component.
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DIL packages
Components which are allocated DIL packages are treated as a special case. It is seen as
desirable to align DIL packages such that they all have the same orientation. To this end a
number of controls on the dialogue are tailored to the placement of DIL packages. Preferred
DIL rotation is by default horizontal but the shape of your board may dictate that vertically
placed DIL packages may make better use of the available space. Two further controls in the
cost weightings group on the dialogue form define how heavily penalised a component will
be if the package is placed with either 90 or 180 degree rotation from the default. If you are not
concerned about the orientation of your DIL packages then set these costs to zero.
Alignment
A successful PCB layout is judged not only on routability but also on aesthetics. One key
factor in whether a PCB looks right is whether components are aligned. This weighting factor
stresses the importance of aligning component edges. Increased alignment can sometimes
also aid routing since if like components are aligned then it follows that their pins are also
aligned.
Options
Push & Shove
The auto-placer recognises two types of component, those initially placed by the user which
are deemed to be fixed and immovable and those placed by the auto-placer which may or may
not have been moved by the user. The latter will be pushed and shoved around the board
where possible in an attempt to best place the remaining components. This shuffling can
become restrictive and counter-productive on boards where the pre-placed components are in
the centre of the board. In such cases Push & Shove should be disabled.
Swap Pass
Since the components are placed sequentially, it may well be that further improvements can
be made to the placement by interchanging like package styles once all the parts are down.
This process can be enabled by selecting the Swap Pass checkbox.
OCCUPANCY DEFINITIONS
Each component that is placed on the board is treated as an obstacle for the remaining
components to be placed. By default the area which is occupied by a component is assumed
to be the smallest box which contains all silk screen graphics and component pins. Any two
such boxes may not touch or overlap.
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It is quite feasible that you will wish to modify the area taken by an object such that, for
example, a DIL package has additional space on the sides occupied by the pins, or that a
connector has increased occupancy on one side only. To achieve this ARES provides an
Occupancy layer onto which 2D graphics may be drawn in much the same way as silk screen
graphics are added.
Occupancy graphics are not normally seen but may be examined and edited by first
decomposing the package, amending or adding graphics as necessary and then invoking the
Make Package command from the Tools menu.
To add an occupancy definition to a package
1. Place a copy of the package on the layout.
2. Tag it and then invoke the Decompose command on the Edit menu.
3. Select the Graphics Mode icon.
4. Select the Occupancy layer in the Layer Selector.
5. Place either a box or a circle to define the occupancy.
6. Tag all the elements of the package.
7. Use the Make Package command to store your handiwork back the library.
The current implementation does not support the use of path objects in the context. Multiple
boxes and circles are allowed at present, but this may be dropped when we code support for
path objects as testing for multiple objects carries a speed penalty.
LIMITATIONS
The auto-placer is another very useful tool in the armoury provided by PROTEUS but there
are a number of limitations of which you should be aware:
• It can place components on the top of the board only. Boards requiring double sided
placement are beyond its scope at present.
• Whilst the auto-placer can operate on boards on which some components have been
pre-placed, our experience is that the more of these there are, the less well it performs. If
possible, it is better to let it place everything and then move things about afterwards.
Pre-placing components in the middle of the board will cripple its performance because
this interferes with its ability to shuffle the components about as placement proceeds. If
you must have pre-placed components in the middle you may find it does a little better if
the Push & Shove option is disabled but in general it will do badly.
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• Boards which are decidedly non-rectangular also interfere with the Push & Shove
mechanism and again the placer will perform badly in such cases. Boards with small cut-
outs etc. should not present a problem, however.
Naturally we hope to code around these limitations in a future version. Our current
assessment is that double sided placement is not too difficult an extension; the other issues
are more intractable.
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AUTO-ROUTING
INTRODUCTION
The ARES auto-router is the one of the most powerful tools in the PROTEUS system and is
capable of saving you an enormous amount of time and effort. However, you'll be glad to
know that despite its considerable internal sophistication, actually using it is very simple.
Features
• Grid based operation. The ARES auto-router divides the board into a grid of cells of
user selectable size and decides where it can and cannot place tracks and vias according
to whether the cells are 'free' or occupied by existing pads & tracking.
This approach limits the router to placing tracks at coordinates on the specified grid, but
special routines are included to deal with both single off grid pads and also rows of off
grid pads. The latter involves generating a 'fan out' from the pads to the nearest grid
squares and is especially effective for routing to surface mount chips.
Special code is also included to allow routing at 45 degrees, something which a number
of the recent 'shape based' routers are incapable of doing.
• Multi-strategy routing. There are a number of techniques by which a router can search
for a viable route for a connection and ARES tries different techniques in turn to find
the best connections. In broad terms, we use first a line search algorithm to establish
good horizontal & vertical discipline and then use a costed maze search to complete the
routing. A special route scheduling technique ensures that all connections are routed at
minimum cost to ensure best manufacturability.
• True multi-layer routing. The router can route on up to 8 layers simultaneously enabling
it to tackle the most densely packed boards and to make best use of multi-layer routing
space when available.
• Rip-up & retry operation. On the harder boards, the router may not manage to route all
the connections at the first attempt. In this case, the board is analysed for blockages
and having removed them, it then attempts to reroute the remaining connections using
the freed space. Clearly this is an iterative process but our code contains special logic to
prevent cyclical behaviour. The result is that the router can make headway from as low
as 80% initial completion to 100% completion given sufficient run time.
The operation of the auto-router is closely tied up with the netlisting and strategy
management features which are covered in the previous chapter.
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• Enable Map Cacheing - this basically makes the router run faster at the expense of
using more memory. If you have 8Mb or less and get out of memory messages or disk
‘thrashing’ whilst the router is running, try deselecting this option.
Once underway, the auto-router displays a status line indicating how routing is proceeding.
As well as the strategy of the connection being processed, the status line also displays:
• What the router is doing - this can be one of MAP, NOVIA, MAZE, NECK, RIPUP,
RETRY or TIDY. MAP means that the router is re-generating its copper utilization map,
NOVIA and MAZE are routing algorithms.
NECK is a further MAZE routing pass but using the NECK style (if any) for the current
strategy. In this mode, the router 'pretends' that it is routing with tracks in the neck
style, and then places them with the normal style. The Auto Track Necking feature then
ensures that the tracks are necked down where they pass between thin gaps.
RIPUP means that the router is analysing for routes blocking the track displayed in red,
and RETRY appears when the router is trying to replace tracks it has just ripped up.
• TR - the number of connections To Route.
• RC - the current number of Routes Completed.
• PK - the PeaK number of routes completed. Once rip-up & retry has been engaged, the
RC value can actually go down temporarily if several tracks are removed to get one new
one in. The PK value shows the best position achieved; this position is saved for later
retrieval if the routing process is interrupted.
• RF - the number of Routes Failed by the current pass.
• PC - the Percentage of connections Completed.
The connection currently being considered is drawn in yellow.
The auto-router can be stopped by pressing ESC. Where rip-up and retry mode is in progress,
you will get an option to retrieve the 'best position' which corresponds to the state of the
board when the Peak Routed value was last achieved.
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The way to achieve this is to redefine the component library parts to have pads on the
Bottom Copper layer only. The router will then only route to these pads from the underside.
The fanout logic also allows fan-ins so that the area inside the
chip can be utilized for routing too.
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style must be set such that a track can leave the SMT pad at 45 degrees without
violating the design rules. Since this width depends on the SMT pad spacing, the
design rules and the autorouter grid it is not possible for ARES to set it automatically –
instead, you should reduce it from the default value of 8th if you get DRC violations.
• The fanout logic operates outside of the autorouter code, and is therefore unable to
‘see’ objects placed without the fanout regions. Consequently, you must not place
objects (e.g. decoupling capacitors) in the fanout areas, as ARES may well just route
over them. This will, of course be picked up by a subsequent DRC check, but would
result in the need to re-work the board.
• For similar reasons to the above, it is not advisable to pre-route to SMT pads that will
be the subject of fanout processing. It is acceptable to pre-route a whole SMT chip, but
not to pre-route to only some of its pads. Again, the consequence will likely be that
ARES will place fanout segments over the manually laid tracking.
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TIDY PASS
ARES also incorporates a mode of operation in the auto-router which we call the Tidy Pass.
This is provided primarily as a means of tidying layouts produced by the auto-router but
there is nothing to stop you using it on manually auto-routed boards also.
To automatically tidy a PCB
1. Invoke the Auto-Router command from the Tools menu.
2. Select the Tidy Pass checkbox.
3. If tidying a manually routed board, deselect the Protect Manual Tracks checkbox.
4. Click OK.
The tidy pass can be run as part of the main auto-routing process or at a later time. It makes
no difference whatsoever.
The tidy process operates by ripping up each track in turn and then re-laying it using costing
heuristics that discourage vias but which also allow diagonal movement more cheaply. In
addition costs associated with anticipated board usage are removed such that kinks and
pointless detours in tracks are also removed. Of course, once a particular track is moved, it
may reveal a new and better route for another track that has already been tidied. The tidy
process thus iterates until no more tidying can occur. This does mean that the tidy process
can become equivalent to routing the board 5 or more times. If it is a large board, this may take
hours rather than minutes. In such cases, the best thing to do is leave it till it is convenient to
run the process overnight.
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POWER PLANES
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regions. If you are not allowed tracking on ground plane layers, then this usually forces
the use of a multi-layer board.
• Even if connectivity is achieved, it is possible for 'slivers' to exist where the enlarged
obstacle images nearly touch - perhaps leaving just 1 thou of copper between them.
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at the hole generation stage. But in addition, no polygon boundary can be less than a pen
width in thickness and so no slivers are created either.
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Layer
The layer on which the zone is placed. This can be any copper layer.
Boundary
The trace style in which the inner and outer boundaries of the zone are drawn. This also
determines the thinnest section of copper by which the power plane can make a connection.
Setting this larger will prevent the copper flowing through small gaps (e.g. between pins) but
making it smaller means that connectivity may be made only by thin sections of copper.
If the zone is hatched, the boundary style is also used for the internal hatching.
Relief
The trace style with which thermal relief connections to component pins are made.
Connection to vias are by direct contact.
Do not use a relief track style that is larger than the boundary thickness or the reliefs may
‘stick out’ of the boundary.
Type
This can be set to one of Solid, Outline, Hatched or Empty.
Solid and Hatched zones should be self-explanatory - the step for the latter being definable
by the Step field.
Outline zones draw only their outer boundaries. This option is provided mainly so that you
can turn off the redrawing of large zones which might otherwise obscure the view of
something else you are working on. However, you may find other applications…
Empty zones are intended to be used for creating holes in other zones - see Overlapping
Zones, below.
Clearance
The distance by which the power plane is separated from other copper objects.
Relieve Pins
If this option is selected, then pins which connect to the zone, and which are not individually
marked for Solid connection will be connected using thermal reliefs. If the option is
unchecked, then pads which connect to the zone, and which are not explicitly marked for
Thermal connection will be connected by solid copper.
It follows that you can achieve any desired mix of solid and thermal relief connections.
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Exclude Tracking
If checked, the zone will treat tracks on its own net as obstacles. Otherwise the zone flows
over such tracking, effectively ignoring it. Tracks on other nets, or loose pieces of track on no
net are always treated as obstacles.
Suppress Islands
If checked, the zone regeneration logic will not draw regions of copper that do not connect to
any pads, even if they touch the zones boundary box.
Route to this Zone
If checked, the auto-router will invoke its PPGVIA pass to attempt to complete connections
on the Zone's net by routing to vias placed within the zone's boundary.
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or:
• Redraws the zone in hatched form to show that it is invalid. In this case, all such invalid
zones can be regenerated by invoking the Regen command, key 'R'. This mode saves
much frustration if the zone regen times are rather long, as will be the case on slower
PCs or with complex boards.
You can toggle auto regeneration on and off using the Auto Zone Regen command on the
Tools menu, key 'Z'.
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REPORT GENERATION
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If you click on an entry, ARES will highlight the associated DRC flag, and if you double click
an entry, ARES will both highlight it and zoom to its location on the board.
One thing to beware of is objects which are touching but not (as far as ARES is concerned)
connected. This can happen if two large pads overlap or else a track does not terminate at the
centre of a pad. Such situations will be marked as DRC violations since ARES sees them as
two unconnected objects which are too close to each other. To eliminate such errors, make
sure that such objects are connected by tracking running from pad centre to pad centre.
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HARD COPY GENERATION
PRINTER OUTPUT
Output through standard Windows device drivers is performed using the Print command on
the Output menu whilst the device to print to may be selected using the Set Printer command.
This command also allows you access to the device driver specific setup dialogue form. The
Print dialogue itself has a number of options which are explained in the following sections.
Output Mode
Four modes are available:
ARTWORK This mode produces a normal PCB artwork with pads, tracking
and graphics drawn to specified dimensions. (The thickness of
silk screen graphics lines is set up on the Set Template
command).
RESIST This mode produces a negative image of the solder resist by
drawing pads, without drill mark holes, and enlarged in size by
the guard band value associated with each pad or via style. If
you don't want holes in the resist over the vias, then set the
guard bands of via styles to -1. Tracking and silk screen
graphics are not drawn in resist mode. Note also, that you would
only normally produce RESIST plots for the Top Copper and
Bottom Copper layers.
MASK This mode produces a negative image of the SMT solder paste
resist by drawing just the SMT pads at actual size. Again, you
would only normally produce MASK plots for the Top Copper
and Bottom Copper layers.
DRILL This mode produces a special plot with each size of drill hole
indicated by a different symbol. 15 such symbols are provided
by default with names $DRILL00 up to $DRILL14. If you manage
to create a board with more than 15 hole sizes, ARES will draw
the extra holes as circles of actual size. If you create additional
$DRILL symbols, these will be used automatically, although we
think the exercise will stretch your imagination!
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Rotation
The Virtual Graphics Device sub-system can produce output with the x dimension either
vertical or horizontal on your peripheral. This lets you orient your work most naturally within
the Layout Editor and still be able to make best use of the size of your peripheral when it
comes to producing artwork.
The terms x-horizontal and x-vertical will depend also on whether you have selected portrait
or landscape output mode for the print device itself. On a portrait page we define horizontal to
mean parallel to the short edge.
Reflection
ARES can produce normal (i.e. as seen on screen) or mirrored output. Choose whichever best
suits your PCB production process.
Incidently, Windows (apart from NT) cannot mirror TrueType fonts, so this is why ARES
does not support their use - there is no way to output them on reflected output, or to Gerber
files for that matter.
Scaling
You can scale the output from 1:1 up to 4:1. Obviously, there is a trade off between the final
board quality and the maximum size of board you can handle for a given sized peripheral. You
will have to experiment for best effect here.
Layers
Except for a drill plot, it is normal procedure to produce a different artwork for each layer of
the board - in ARES this means the copper and silk screen layers. Many people dispense with
the solder side silk screen - it is most useful if a board has components on both sides, or must
be tested or maintained solely from underneath.
PLOTTER OUTPUT
Windows support for Pen plotters is, unfortunately, very poor. Although drivers are supplied
for HPGL and other plotters, the implementation of these drivers is very sketchy. Better
drivers may be available for particular plotters, but we have not relied on this in designing the
plotter support within ARES for Windows. Instead, we rely on the Windows plotter driver
only to draw straight lines and then ARES itself does the rest. To do this, it uses the plotter
driver module from the DOS version. This module allows control of the following options
which are adjusted using the Set Plotter command on the System menu.
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Plotter Tips
On the Set Plotter command form are fields for Pen Width and Circle Step.
Pen width
This is a value in thou which should correspond (at least initially) to the width of pen you are
using.
Circle step
This value is the size of step (in thou) that ARES will use when plotting the outer radius of a 1
inch diameter pad. A smaller number results in faster but more jagged circular pads whilst a
value of 0 will instruct ARES to use the plotters internal circle drawing command. Whilst this
is generally fast and smooth, it does mean that the pen is picked up and put down for each
pass round the pad.
Getting high quality plots will require experiment with pens, film, ink, and the settings
described above. You may also find it necessary to tweak the sizes of some of the pad, via
and trace styles - the problem is that there are too many variables outside our control to
guarantee that the dimensions of plotted objects will accurately tie up with their nominal size.
As a starting point, we recommend a 0.25mm or 0.30mm tungsten carbide tipped pen,
professional drafting film (obtainable from a good stationers) and Marsplot 747 ink.
Finally, the Line Width command on the Set Template command form is ignored when plotting
- a single pass of the pen is used for all silk screen graphics for reasons of speed. If you need
a different line thickness, use a thicker pen for your silk screen plots!
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POSTSCRIPT OUTPUT
Postscript, invented by Adobe Inc, is most commonly used in professional DTP and
typesetting. However, it is an extremely flexible language well suited to accurately specifying
a PCB artwork. More importantly, the £10K photo-typesetters which are used by professional
publishers are capable of producing >1200dpi images on film. Access to these machines is
facilitated by the existence of bureaux and our experience is that they charge less than Gerber
Photoplotting bureaux for an equivalent plotted area. Try calling a few local printers from the
Yellow Pages to track down a local bureau.
Those of you with a Postscript laser printer will be able to proof your boards on it before
generating a file for photo-typesetting.
With ARES for Windows, you just select and install the appropriate Postscript printer driver,
and use the Print command in the normal way. If you use a local phototypesetting bureau,
they should be able to supply you with the correct driver for their phototypesetter.
Bitmap Generation
The Export Bitmap command on the Output menu will create a bitmap of the board and place
it either on the clipboard or in a disk file. You have the following additional options:
• Resolution - choose from 100 to 600 DPI. Memory usage increases in proportion to the
square of the resolution.
• Number of colours - mono resolution is simple black & white, display resolution uses
the same bitmap format as your display adaptor.
• Other options are as for PRINTER OUTPUT on page 101.
Metafile Generation
The Windows Metafile format has the advantage of being truly scalable where a bitmap is
not. However, not all Windows applications (e.g. Paintbrush) can read a metafile.
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The Export Metafile command on the Output menu will create a metafile of the board and
place it either on the clipboard or in a disk file. You have the following additional options:
• Colour - choose mono or colour output.
• Placeable header - if you are generating a disk file, there are two formats - one with a
placeable header and one without. Some applications need the header (e.g. Word) and
others will not load a metafile that has one!. All you can do is experiment.
• Black background - if checked, this option causes ARES to draw a black rectangle
before drawing anything else in the metafile.
• Enhanced - generated an Enhanced metafile. Enhanced metafiles are supported by
Window 95 and Windows NT applications only.
• Other options are as for PRINTER OUTPUT on page 101.
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106
CADCAM OUTPUT
GERBER OUTPUT
The Gerber format, named after Gerber Scientific Instruments Inc., is almost universal in the
PCB industry as regards specifying PCB artwork although we suspect that it may gradually be
superseded by Postscript.
A photoplotter is essentially the same as a pen plotter except that it writes with a light beam
on photographic film rather than with an ink pen on paper. The aperture through which the
beam shines can be varied, allowing it to expose a pad in a single flash and a track with just
one movement of the plotting head.
In order for a photoplot to be produced (usually by a bureau, as photoplotters are not cheap)
it is first necessary to set the machine up with a set of apertures corresponding to the various
pad shapes and track widths used on the board. Each different aperture is referenced by a so
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called D-Code in the Gerber file and a table listing D-Codes against aperture shape and size
must thus be compiled. This table is compiled automatically and then written out as part of
the tool information file.
ARES is clever enough to tell if two pad styles result in the same aperture, and it will only use
one D-code in this situation. Also, styles which are present in the selectors but not used on
the board do not waste table space.
Other points to bear in mind:
• An aperture cannot render the image of a pad with a centre hole - the piece of metal for
the hole would fall out! Photoplots thus come out with completely solid pads and
boards produced from them are very difficult to drill manually. This, among other things
is why Postscript is a much better format.
• Rectangular pads that are rotated to non-orthogonal angles have to be rendered by
hatching them with a fine line. Once again, Postscript overcomes this problem.
• Polygonal ground planes also have to hatched (even if you have selected them as solid)
and the resulting output files can be massive. However, the boundaries will be drawn
exactly as computed - using an aperture corresponding to the boundary thickness for
the zone - so there is no risk of design rule violations.
• The origin for the Gerber co-ordinate system is defined by the Set Output Origin
command on the Output menu.
NC DRILL OUTPUT
Many PCB manufacturers now have Numerically Controlled drilling machines which provided
with the positions and drill tools to use for each pad, can automatically drill a circuit board.
Nearly all these machines use the Excellon format, invented by Excellon Industries.
The format is very simple, consisting of the (x,y) locations of the holes and T-Codes
specifying which tools to use. As with Gerber Format, a table must be supplied to the
manufacturer listing the hole diameter corresponding with each T-Code. ARES handles this in
the same way as it handles each Gerber D-Code - it assigns a new T-Code for each new hole
size it encounters, and this information is also put in the tool information file.
ARES uses the same co-ordinate systems for Gerber and NC Drill output - based on the
position of the Output Origin - so your manufacturer should have no problem in aligning the
drilling machine with the artwork.
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The drill sizes used are taken from the Drill Hole attributes of the pad styles. Please make
sure that the default sizes we have allocated are suitable for your application before having
large numbers of boards manufactured.
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"U1","","DIL08",TOP,0,6000,5000
"Q1","","TO220",TOP,180,6050,5375
"D1","","DIODE30",TOP,180,6050,5250
"R1","","RES40",TOP,270,6300,5050
"R2","","RES40",TOP,270,6400,5050
"Q2","","TO92",TOP,90,5650,5050
"R3","","RES40",TOP,180,5800,4750
"C1","","CAP10",TOP,180,6200,4750
"C2","","CAP10",TOP,0,5650,5350
There are a number of points that must be appreciated about this file:
• The origin for the co-ordinates is the Output Origin - this is the same origin as is used
for the Gerber and Excellon outputs.
• The (x,y) coordinates are quantified in units of 1 thou and represent the centre of the
component’s package. This position may or may not correspond to the origin of the
component for auto-insertion, but it will be in approximately the correct place. Our
understanding is that this is helpful in that it provides a starting point for manual
alignment of the placement head.
• The rotations are in anti-clockwise values in degrees relative to the orientation of the
package when it was defined. Since there is no standard for default orientations of
packages these values may be of limited use unless they can be combined with a
translation table that is specific to ARES packages including ones you have defined
yourself. This is a matter between yourself and whoever is providing the auto-insertion
facility.
As far as we are concerned, this is an evolving and experimental area of the software; a
number of users have requested an output file of this nature but there is as yet no industry
standard for us to base it on. Any feedback on this issue will be greatly appreciated.
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GERBER VIEWING
Since photoplotting charges can be quite substantial, it is useful to be able to view Gerber
files to ensure that all is well prior to sending them to the bureau.
To facilitate this, ARES provides a Gerber View command which will load and display
selected files produced by the CADCAM command.
To view Gerber output files
1. Invoke the Gerber View command from the Output menu. If you have modified but not
saved the current design you will be prompted to do so, as the current design data is
lost when the Gerber files are read.
2. Choose an 'INF' file from the file selector. The Gerber View can only read Gerber files
produced by ARES for which an INF file exists.
3. ARES will then parse the file and display a dialogue form for selecting which layers to
view. By default, all available layers are loaded.
Although it is possible to perform editing operations on the Gerber View data, we do not
recommend or support this mode of operation, aside for panelization which is discussed in the
next section.
Do not confuse this feature with GERBIT (the Gerber Import Tool), which is available as an
optional extra. See GERBER IMPORT TOOL on page 119 for more information on GERBIT.
PANELIZATION
Panelization refers to the processes of combining several board artworks onto one panel in
order to reduce manufacturing costs. It is common practice to panelize both multiple copies of
the same board and/or several different boards.
ARES provides facilities to achieve this through the Gerber Viewer.
To create a panelized artwork
1. Use the CADCAM Output command to produce Gerber and Excellon files for each board
to be included on the panel.
2. Invoke the Gerber View command and choose the INF file of the first board to go on the
panel.
3. Accept the default settings for the layers (these should correspond with the layers you
chose to generate at step 1) and check the Panelization Mode checkbox.
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4. Click OK. ARES will import the CADCAM data for the board and display it as a tagged
set of objects.
5. Use the Set Work Area command on the System menu to specify the dimensions for the
panel.
6. Use the Block Move command to re-locate the board image to where you want it on the
panel.
7. If the panel is to contain multiple images of a single board only, you can now use the
Block Copy command to lay them out.
8. If the panel is to contain images of additional boards, you can import them into the panel
by returning to step 2 above.
9. When the panel is complete, use the CADCAM Output command to generate final
artwork files for the panel. It is these files that you need to send to your board
manufacturer.
There are a number of points to note about the panelization process:
• You can add additional text and graphics to the panel as required to designate board
IDs and other manufacturing information.
• When importing multiple board images, ARES will assign new pad and track style codes
(D-Codes) for each image. However, when the CADCAM files are re-generated, ARES
will re-combine styles that are actually the same, so that the total usage of aperture and
tool codes will not be excessive.
• The resulting set of files may be quite large - especially if the board contains ground
planes or non-orthogonal components. However, that is an inevitable consequence of
producing a file that contains multiple board images. Fortunately, the files are ASCII,
and will compress quite well with WINZIP or similar, should you need to transmit them
by email.
• The process is not suitable for panelizing boards containing buried or blind vias,
because the layer ranges of the drill holes are not preserved. If you need to do this, we
recommended you make use of a 3rd party Gerber viewer/editor package.
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DXF IMPORT TOOL
INTRODUCTION
The DXFCVT converter is fully integrated into ARES and is driven through the Import DXF
tool on the File menu. It facilitates the import of mechanical data in DXF format, and we
envisage it being used in situations where a board needs to be fitted into an existing
mechanical design. It could also be used to import other graphics such as company logos.
The conversion process is as follows:
• Generate the DXF file from your mechanical CAD application. This should, if possible,
be a 2D drawing. ARES cannot handle 3D data and the converter thus ignores all z co-
ordinates in the DXF file so 'flattening' 3D drawings to two dimensions.
• Determine the mechanical layers in the DXF file that are to be combined and placed on
particular ARES layers. The DXF Import dialogue form allows you to specify one or
more layer assignments with each assignment specifying which of the mechanical layers
in the DXF file are to be combined and placed on the specified ARES layer.
Note that it is particularly important that the correct units are used for DXF import. As per the
original DXF specification all co-ordinates are interpreted as being in inches. If after importing
your file you find that the graphics appear wildly out of scale then you probably have a DXF
file whose units are in millimetres and you will need to specify a scaling factor of 0.03937 .
This causes the importer to divide all co-ordinates by 25.4 (1” = 25.4mm).
You should appreciate that Autocad (the application around which the DXF format was
based) supports much more powerful mechanical drafting than that offered by ARES. Thus
some entities in a DXF file are ignored by DXFCVT, and others are approximated. However,
for the purpose of displaying simple cabinet internals and the like inside ARES, DXFCVT is
quite adequate to the task.
F See the Limitations section for specific information on the limitations of the DXFCVT
converter.
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SETTING UP
Generating The DXF File
The DXF file to be imported should be generated by the mechanical CAD application you
use. Consult the documentation or on-line help associated with the CAD application to
determine how best to do this.
As far our import converter is concerned, the only requirements are that:
• The file exported by the application be in plain ASCII and not in the alternative binary
(DXB) format.
• Co-ordinates in the DXF file are in floating-point inches with the value 1.0000 being
assumed as one inch - this is the norm for DXF files.
Layer Assignments
Having generated the DXF file you must now decide on what layer assignments you require.
Each layer assignment tells the converter which layers in the DXF file are to be combined and
placed on a single ARES layer. The controlling dialogue form is laid out in a fashion that
should make this process fairly transparent and Context Sensitive Help is provided for all
fields on the form should you encounter any problems.
Note that, for a given conversion, an ARES layer may only be assigned once. An attempt to
assign a layer twice will result in an error.
PERFORMING A CONVERSION
Basic Conversions
To perform a DXF file conversion you need to load the converter with the name of the DXF
file to be converted. This process is implicit with ARES V in that immediately on selecting the
Import DXF tool you will be asked to open the appropriate DXF file. A successful loading of
the file will result in the appearance of the DXF Import dialogue form. All available options on
the dialogue form are covered via Context Sensitive Help on the appropriate field.
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Conversion Errors
With regard to DXF file parsing errors, the converter has been written to be as fault-tolerant
as is consistent with reading a DXF file. Parsing errors are only generated when:
1. The DXF file doesn't contain an ENTITIES section. A DXF file without entities is
deemed 'empty', which makes conversion impossible.
2. The DXF file contains a section (e.g. HEADER, ENTITIES) or a primitive (e.g. LINE,
CIRCLE, etc.) that doesn't contain a single record. All sections should at least contain
an end-of-section record and all primitives should contain at least one record. This
implies the DXF file is corrupted.
3. The end of a BLOCK entity in a non-BLOCKS section or the end of the BLOCKS section
before the end of a BLOCK entity. This implies the DXF file is corrupted.
4. The failure to extract (parse) data of a type consistent with the group record code. For
example a record with a group code of 10 implies an integer value and a record with a
group code of 41 implies a floating point value. An error is generated if (regardless of
formatting) a value cannot be parsed.
Whenever an error occurs the converter reports the error in the form:
ERROR (000413): Entity Group Expected - EOF found?
and the conversion is aborted.
For file parsing errors, the number of the last line read from the DXF file is shown in brackets
after the ERROR keyword (note that the converter reads whole groups - two lines - from the
DXF file at a time, and so any error may be on the line indicated or the preceding line). For
non-parsing errors, the line number is displayed as dashes.
Conversion Warnings
Apart from errors (described above) all other reports of unusual or possibly erroneous
conversion behaviour are treated as warnings. Warnings are not fatal (they do not stop the
operation and completion of the converter) but are useful if the resulting region file is not
what was expected. In order to be complete, the converter issues warnings whenever it
encounters a situation that may or may not lead to unusual region files and this includes any
record it reads and discards as being either of unknown purpose or unconvertible. In order
not to slow the conversion down (with screens of scrolling text), warnings are only displayed
if requested (through the Generate Warnings checkbox on the dialogue form).
Warnings are displayed in a similar format to errors (described above) except that the DXF file
line number line and message text is preceded by the word WARNING.
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LIMITATIONS
The principle limitations of the DXFCVT converter are summarised as follows:
• DXF files must be in plain ASCII. The converter does not support the DXB binary file
format.
• Three-dimensional DXF drawings are flattened to two-dimensions ('plan' view) by the
converter as ARES only supports two dimensions.
• The only entities (alone or as part of a BLOCK entity) supported are the BLOCK, LINE,
POLYLINE, CIRCLE, ARC, TEXT, SOLID, TRACE, and INSERT entities. All other
entities are ignored and do not affect file conversion. The SOLID and TRACE entities
are converted as polygons. In particular, the DIMENSION entity is not supported.
• Only those attributes of an entity that can be honoured by ARES are converted. Thus
text attributes such as font face, weight (boldness) and italic slope angle are discarded
and do not affect the file conversion.
Other minor limitations include:
• Line types (dots, dashes, thicknesses, etc.) are lost. All lines are single-pixel.
• Colours are lost - all converted entities are displayed in a colour appropriate to the
ARES layer they are on.
• Text styles (from the DXF TABLES section) are ignored. The converter relies (for those
attributes it converts, such as rotation, mirroring, etc.) on these attributes being
specified as part of the TEXT entity - this is the norm.
• The conversion of DXF TEXT entities drawn in a proportional text style will convert to a
fixed-pitch font in ARES where the width of the characters may result in the overall
length of the string in ARES being different to the overall length of the string in the
DXF drawing. This may then lead to alignment problems unless the user has made
judicious use of the DXF text alignment flags (e.g. text that is specified as fitting
between two points).
As the ARES text primitive is limited to fixed-pitch characters which only allows for the
specification of a character height and character width for the text string, the only way
around this problem would be to adjust the ARES character width such that the number
of characters in the string multiplied by the adjusted character width is the same as the
overall length of the string in the DXF file. Unfortunately, except for certain
justifications, the DXF file does not contain the overall string length and so this isn't
possible.
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The actual behaviour of the converter is to calculate the character height as being equal
to the height of the DXF TEXT entity and the character width as being equal to the
TEXT entity height scaled by the TEXT entity's x-scaling factor (the latter defaults to
1.0).
• The following text attributes and properties are not converted:
? Vertical fonts (i.e. where characters are stacked on top of each other rather than
alongside each other).
? Obliquing angle (for italics).
? Styles - all text is in ARES's fixed-pitch vector font.
? Control characters. These occur in the DXF file as a caret followed by an ASCII
character - all such characters in the string are preserved.
The following text attributes and properties are converted:
? Rotation.
? X and Y mirroring.
? Justification, except attribute '5' ("Text is fit [sic] between two points (width
varies)") as it is ambiguous and hasn't been tested.
• Only the following entities are converted as noted.:
? LINE and 3DLINE entities.
? CIRCLE entities.
? ARC entities (by default, by linearisation to multiple chords).
? SOLID, TRACE and 3DFACE entities are converted to unfilled three/four sided
polygons. The 'hidden' attributes of 3DFACEs is not honoured.
? TEXT entities is converted as described above.
? BLOCK entities.
? INSERT entities are converted but any associated ATTRIB entities are discarded -
this leads to text declared in the INSERT via a ATTDEF entity being lost.
? POLYLINE and associated VERTEX entities. All polylines are assumed to be
continuous (i.e. not a mesh) and all VERTEX entities are assumed to be single point
(i.e. not Bezier or spline).
In addition to the above some other omissions are:
? DIMENSION entities - these are usually also exported as LINE, SOLID and TEXT
entities as well, so there should be no loss of visible information.
? ATTRIB and ATTDEF entities, as outlined above.
? SHAPE entities - these will (if a problem) be added in a future release.
• All DXF file co-ordinates are assumed to be mathematical, in inches, and with an implied
origin at (0,0). It is the user's responsibility to specify alternate scaling parameters (via
the appropriate options on the dialogue form) to comply with this assumption.
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GERBER IMPORT TOOL
INTRODUCTION
GERBIT is available as an optional extra - it is not part of the standard Proteus package. It
facilitates the conversion of PCBs designed with other CAD programs to ARES format. The
conversion process involves the following steps:
• Generating the required Gerber files with the source CAD system. At the same time, you
need to generate an aperture list so that you know which 'D-Codes' specify which pad
and track types.
• Creating new pad and trace styles in ARES to correspond with those used in the source
layout(s).
• Processing the sets of Gerber files with GERBIT to create a single ARES region file for
each layout.
• Where several boards are to be converted, it is often worthwhile generating a dummy
board in the source CAD system containing all the library parts used in the real ones.
This can then be converted and the library parts captured from it into the ARES
libraries.
• Reading each region file into ARES, and reconstituting its components by over-placing
library packages over their pads. It is for this reason that the previous step can often be
useful.
It is vital to appreciate that the Gerber format specifies the board at the level of individual
pads and tracks, and that all information pertaining to which pads belong to which
components is lost. The extent to which this matters depends on how much editing you want
to do on the imported boards, but ARES provides specific features & tools to help with the
reconstitution process. Nevertheless, reconstituting a board requires a considerable degree
of manual effort.
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• The ability to create a human readable aperture list corresponding to a batch of Gerber
files.
• At minimum, the system must be able to generate separate Gerber files for each of the
copper layers. Additionally, it will prove of great assistance if it can generate files for
the component and solder side silk screen layers. If it can generate a file with either pads
and vias only, or better still, component pads only, this will further facilitate the
conversion and capture of library parts.
• The system must be set so as not to create pads out of multiple flashes or, worse still,
draw strokes. The conversion process assumes that a flash corresponds to a single pad,
and a draw stroke corresponds to a track segment.
• If the system can produce an Excellon format NC drill file, this can be used to assist with
the combination of vertically aligned pads on each layer into single through hole pads
in ARES. If no drill file is available, GERBIT will perform this task by matching co-
ordinates, but this may lead to occasional problems if there are pads which are
coincident, but not through hole (e.g. SMT pads).
WARNING:
Note that the Gerber Import Tool will only work with files in the RS247D Gerber Format.
Files in the new RS274X format cannot be imported using this utility.
TUTORIAL
Before we discuss some of the more advanced issues involved in Gerber import, we will first
take you through an example conversion session.
This section presents a walk through using the ARES door bell sample. Note that this is
rather contrived since we have generated the GERBER files from ARES in the first place.
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same directory as your ARES program and contains definitions for all the pad and track styles
that ARES knows about.
Your are now presented with three views, the uppermost view is the file/layer view, the lower
left is the style/tool view and the lower right is the preview window.
In the File View window double click on the file entitled DBELL.INF. This will launch a text
viewer which allows examination of any ASCII file.
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File List
---------
Top Copper c:\Ares\dbell.TOP
Bottom Copper c:\Ares\dbell.BOT
Top Silk c:\Ares\dbell.TS
Drill c:\Ares\dbell.DRL
Photoplotter Setup
------------------
NC Drill Setup
--------------
Format: ASCII, 2.4, imperial, absolute, eob=<CR><LF>,
no zero suppression.
Notes: Tool sizes are diameters.
T01 20th
T02 30th
It is important to study this file before converting as it provides us with key information
regarding the conversion process. Firstly we can note that there are four GERBER files to
convert and secondly that they are in 2.4 imperial format.
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As is happens imperial 2.4 is the default so we do not need to change the resolution for this
project. We now have to place the GERBER files in the Layer view and this is achieved using
drag and drop. Left click on the file called DBELL.TOP and keep the left mouse button
pressed drag the file to the right until the top copper layer in the layer view window is
highlighted in blue. Now release the mouse button.
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To complete the process we must use the style and tool views to allocate the correct
apertures as defined in the DBELL.INF file. This is once more a drag and drop process. Select
the tool view window and drag the apertures from default to their appropriate tool codes such
that you have:
D10 T25
D11 T15
D12 T10
D13 C50
D14 C80
D15 S50
D16 C60
D17 S60
D18 C100
D70 T50
you will notice that DCODE 19 is defined as
D19 CIRCLE D=8th DRAW
this means a trace (DRAW) of thickness 8th and that no such style exists in ARES. This will
be a common problem and you will need to be aware of the range of pads and trace styles
which are used in you GERBER files. You can then define the required styles in ARES.
Alternatively you can create a pad or trace style specifically for this board. Simply select
Create New Trace Style (or Pad Style) from the options menu. You are then asked to name the
style and supply the required dimensions. When defining trace styles you only need to
define the track thickness. When defining pads the dialog box changes to reflect the
dimensions required for the pad style selected.
Once the new trace style has been defined it appears in the tool view along with tools defined
in the default.sty file.
As you drag each of these styles onto the tool view the preview will update to reflect the
changes. With off the tools in place you should see the following.
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All that now remains is to generate a region file to import into ARES and this is achieved by
selecting Options and then the Make Region File command .
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examine text files (usually information files) in a read only text window. Simply right click on
the file you wish to view and select view file, alternatively double click on the file to view.
The layer view also has a right hand mouse button menu, which has the following options.
Flip X flip the currently highlighted layers left to right.
Flip Y flip the currently highlighted layers top to bottom.
View Include/Exclude highlighted layers from graphic preview.
Clear Reset highlighted layer information to default settings and remove file
name.
Colour Define the graphic display colour of the currently selected layer.
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2inx2in may be zoomed to a ration of 10:1 whilst a board 4inx4in may only be zoomed to 7:1. A
board which is nominally larger than 32 in will not be previewed.
The primary usage of the preview window is to ensure correct orientation of the layers since
some cad systems flip tracking on the bottom copper. If you wish to see a more accurate view
of the board load the region file generated by Gerbit into Ares.
ADVANCED CONSIDERATIONS
The following topics may be relevant to you once you have mastered the basics of Gerber
import, or if you encounter difficulties with converting particular types of board.
Memory Usage
In general, ARES will need considerably more memory to handle a board during Gerber import,
than it would if the same board were created in the usual way. This is because all the silk
screen graphics are held in a much lower level way than they would be if they part of library
packages.
Another thing to bear in mind is that captured library parts will often be considerably larger
than they would be if they created from 2D graphics. This is particularly true for silk screen
outlines involving curves, as these will be rendered as lots of short straight lines in Gerber
format. Some CAD systems use an awful lot of lines too.
Finally, the Convert Vias command should be used on small numbers of vias at a time since
when a via is converted to a lone pad, the lone pad form uses about three times as much
memory.
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Pin Numbering
ARES uses the pin numbers assigned to library parts when it is loading a netlist in order to tie
up package pins with device pins in ISIS. Now it is perhaps unlikely that this will matter much
for imported boards, since you are unlikely to have an ISIS schematic. However, if you intend
using Gerber Import to capture library parts for future use with netlists then pin numbers do
matter.
If you simply convert a group of vias to pads, tweak the silk screen and invoke the Make
Package command, the pins of the package will be numbered in the order that they appeared
in the Gerber file. Unfortunately, this is in no way guaranteed to be the correct even for simple
packages like DIL outlines. The only way to find out is to use Make Package and then check
the assigned pin numbers by zooming in – the pin numbers will be drawn on the pads once
there is sufficient space for them to be legible.
On the (more than likely) assumption that the pin numbering is wrong, you will need to adopt
a slightly more involved approach to capturing packages. Having converted a set of vias to
pads, the additional steps required are as follows:
4. Select the Instant Edit icon.
5. Invoke the Auto Name Generator, set the prefix to the empty string and the
count to '1'.
6. Click on the pads in the order you want them numbered.
ARES will indicate the number it has assigned to each pin as you mark it.
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Alignment
Due to the number of stages through which design passes during Gerber import, the
alignment of its pads onto the absolute grid sometimes goes astray. For example, the relative
spacing of the pads might be 50 thou, but they might all be at multiples of 2 and 52 thou.
Although Real Time Snap will facilitate editing such a board to some extent, it will be better if
you re-align it. This can be done by tagging the entire board, and then invoking the Align
command on the Edit menu. This offsets all the tagged objects such that the majority of the
pads lie on the current snap grid.
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INDEX
on underside of board 34
A placing 19, 33
Align command unplaced 19
in Gerber import 125 Connections
Anchor point 17, 57 specifying manually 65
Annotation 10 Connectivity highlight 15, 64
Arcs 36 Connectivity rule check 24, 95
ARTWORK mode 97 CONNECTORS.LIB 55
ATTRIB 55 Coordinate Display 30
Auto Trace Selection 41 Coordinates
Auto Track Necking 13, 42 measuring 31
in autorouter 70 snapping 32
Auto Via Placement 10, 22, 41 Copy icon 46
Automatic Insertion Machines 105 Copying
Auto-Router command 80 area 46
Auto-Routing 22, 79 route 14, 45
single sided boards 82 CRC report 95
using pads as through holes 82 Creating library parts 57
with off grid pads 83 Cursor types 8, 30
Auto-Save 50 Curved tracks 10, 42
Cut-outs 105
B
D
Back-annotation 71
Bitmap 100 D-Codes 103
Blind vias 13 Decoupling capacitors 75
Block editing 12, 46 DEFAULT.STY file 54
BMP file 100, 101 Delete icon 47
Boxes 36 Deleting
Buried Vias 13 area 12, 47
library parts from selectors 56
C nets 15, 64
Power Planes 92
CADCAM output 103
route 14
Circle step 99
single object 39
Circles 36
vias 12
Clipboard 100
Design rules
Component Re-Annotator 71
checking 24, 96
Components
violation message 42
affect of loading new netlist 61
DEVICE.XLT file 63
and back annotation 71
Dimension fields 31
distinction from packages 33
Dirty tracks 40, 42
editing 20, 39
Dragging
highlight by name 40
objects 9
not in netlist 33, 35
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Truetype Fonts
non support of 98
Tutorial
basic techniques 8
block editing 12
introduction 7
making new packages 17
making new symbols 17
overview 7
printing 16
report generation 24
route editing 12
using a netlist 18
U
Untagging 38
USERPKG.LIB 55
USERSYM.LIB 55
Using the manual 3
V
Version information 6
Via styles 53
Vias
deleting 12
placing 10, 12, 22, 41
W
WMF file 100
Z
Zones 37
deleting 92
editing 90
placing 33
Zoom 29
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