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    4 Bit Adder

    Uploaded by

    salahuddin73
    This document contains code for a 7-bit adder module and a testbench module that simulates the adder over time. The adder module defines inputs and outputs for two 7-bit numbers and a carry input, and always adds the inputs and carry to produce a sum and carry output. The testbench instantiates the adder, sets up initial values for the inputs, and uses delays to simulate the adder over 800ns by changing the input values at different time points and observing the outputs.

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    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd

    4 Bit Adder

    Uploaded by

    salahuddin73
    71 views2 pages
    This document contains code for a 7-bit adder module and a testbench module that simulates the adder over time. The adder module defines inputs and outputs for two 7-bit numbers and a carry input, and always adds the inputs and carry to produce a sum and carry output. The testbench instantiates the adder, sets up initial values for the inputs, and uses delays to simulate the adder over 800ns by changing the input values at different time points and observing the outputs.

    Original Description:

    M.tech DSCE JNTUH Programs

    Original Title

    4 bit adder

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    © Attribution Non-Commercial (BY-NC)

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    This document contains code for a 7-bit adder module and a testbench module that simulates the adder over time. The adder module defines inputs and outputs for two 7-bit numbers and a carry input, and always adds the inputs and carry to produce a sum and carry output. The testbench instantiates the adder, sets up initial values for the inputs, and uses delays to simulate the adder over 800ns by changing the input values at different time points and observing the outputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    71 views2 pages

    4 Bit Adder

    Uploaded by

    salahuddin73
    This document contains code for a 7-bit adder module and a testbench module that simulates the adder over time. The adder module defines inputs and outputs for two 7-bit numbers and a carry input, and always adds the inputs and carry to produce a sum and carry output. The testbench instantiates the adder, sets up initial values for the inputs, and uses delays to simulate the adder over 800ns by changing the input values at different time points and observing the outputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    of 2

    module nBitAdder(f, cOut, a, b, cIn);

    parameter n = 7;
    output reg [n:0] f;
    output reg cOut;
    input [n:0] a;
    input [n:0] b;
    input cIn;
    always @(a, b, cIn)
    {cOut, f} = a + b + cIn;
    endmodule
    module tb_4ba;
    wire [7:0] f;
    wire cOut;
    reg [7:0] a = 8'b00000000;
    reg [7:0] b = 8'b00000000;
    reg cIn = 1'b0;
    nBitAdder UUT (
    .f(f),
    .cOut(cOut),
    .a(a),
    .b(b),
    .cIn(cIn));
    initial begin
    // ------------- Current Time: 100ns
    #100;
    cIn = 1'b1;
    b = 8'b00000100;
    // ------------------------------------// ------------- Current Time: 200ns
    #100;
    a = 8'b00000010;
    b = 8'b00000101;
    // ------------------------------------// ------------- Current Time: 300ns
    #100;
    a = 8'b00000011;
    // ------------------------------------// ------------- Current Time: 400ns
    #100;
    b = 8'b00000010;
    // ------------------------------------// ------------- Current Time: 500ns
    #100;
    a = 8'b00000001;
    b = 8'b00000011;
    // ------------------------------------// ------------- Current Time: 700ns
    #200;
    a = 8'b00000011;
    b = 8'b00000001;
    // ------------------------------------// ------------- Current Time: 800ns
    #100;

    b = 8'b00000010;
    end
    endmodule

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