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VHDL Implimentation of LZW Compression Algorithm

This document contains a summary of a VHDL implementation of the LZW compression algorithm. The LZW algorithm can compress various types of data like text, numbers, images by 40-60% compared to 20% for Huffman encoding. The algorithm uses simple logic that allows for inexpensive and fast hardware implementations using 9-16 bit codes. This project implemented the LZW algorithm in VHDL and verified the simulation results. Further work could focus on improving compression percentage using less circuitry.

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setsindia
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259 views

VHDL Implimentation of LZW Compression Algorithm

This document contains a summary of a VHDL implementation of the LZW compression algorithm. The LZW algorithm can compress various types of data like text, numbers, images by 40-60% compared to 20% for Huffman encoding. The algorithm uses simple logic that allows for inexpensive and fast hardware implementations using 9-16 bit codes. This project implemented the LZW algorithm in VHDL and verified the simulation results. Further work could focus on improving compression percentage using less circuitry.

Uploaded by

setsindia
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL IMPLIMENTATION OF LZW COMPRESSION ALGORITHM Abstract The adaptive Lempel-Ziv-Welch general-purpose algorithm and its implementation suitable for packet radio telephone transmission, and archival storage. While the statistical variablelength Huffman technique compresses text by 20%,the LZW technique can compress data (text, numeric, mixed, and bit-mapped images)by 40 to 60%. The adaptive LZW algorithm has very simple logic, leading to inexpensive and fast implementations. Good LXW implementations use 9- to 16-bit codes, handling most applications.A12-bit code is suitable for medium-size files. Efficiency improves with larger codes. A tight coding of the algorithm can compress 75 Kbytes in a second on a 1-MIPS machine. This project is implemented using VHDL &simulation results are verified. It encourages concurrent development in the area of data compression. The further enhancement of this project is to achieve more percentage of compression with less hardware.

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