SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES

SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

D Package Options Include Plastic

Small-Outline (D, NS, PS), Shrink Small-Outline (DB), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs
SN5400 . . . J PACKAGE SN54LS00, SN54S00 . . . J OR W PACKAGE SN7400, SN74S00 . . . D, N, OR NS PACKAGE SN74LS00 . . . D, DB, N, OR NS PACKAGE (TOP VIEW)

D Also Available as Dual 2-Input

Positive-NAND Gate in Small-Outline (PS) Package

SN74LS00, SN74S00 . . . PS PACKAGE (TOP VIEW)

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 4B 4A 4Y 3B 3A 3Y

1A 1B 1Y GND

1 2 3 4

8 7 6 5

VCC 2B 2A 2Y

SN5400 . . . W PACKAGE (TOP VIEW)

SN54LS00, SN54S00 . . . FK PACKAGE (TOP VIEW)

1A 1B 1Y VCC 2Y 2A 2B

1 2 3 4 5 6 7

14 13 12 11 10 9 8

4Y 4B 4A GND 3B 3A 3Y

1B 1A NC VCC 4B 1Y NC 2A NC 2B
3 4 5 6 7 8 2 1 20 19 18 17 16 15 14 9 10 11 12 13

4A NC 4Y NC 3B

NC No internal connection

description/ordering information
These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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2Y GND NC 3Y 3A
On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

Copyright 2003, Texas Instruments Incorporated

SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
description/ordering information (continued)
ORDERING INFORMATION
TA PACKAGE ORDERABLE PART NUMBER SN7400N PDIP N Tube Tube Tape and reel Tube SOIC D 0 C 70 C 0C to 70C Tape and reel Tube Tape and reel SN74LS00N SN74S00N SN7400D SN7400DR SN74LS00D SN74LS00DR SN74S00D SN74S00DR SN7400NSR SOP NS Tape and reel SN74LS00NSR SN74S00NSR SN74LS00PSR SOP PS SSOP DB Tape and reel Tape and reel SN74S00PSR SN74LS00DBR SNJ5400J CDIP J Tube SNJ54LS00J SNJ54S00J SNJ5400W 55C to 125C CFP W Tube SNJ54LS00W SNJ54S00W SNJ54LS00FK LCCC FK Tube SNJ54S00FK S00 SN7400 74LS00 74S00 LS00 S00 LS00 SNJ5400J SNJ54LS00J SNJ54S00J SNJ5400W SNJ54LS00W SNJ54S00W SNJ54LS00FK SNJ54S00FK LS00 7400 TOP-SIDE MARKING SN7400N SN74LS00N SN74S00N

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H

logic diagram, each gate (positive logic)

A B Y

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SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

schematic
00 VCC 4 k 1.6 k 130

A B

1 k GND

LS00 VCC 20 k 8 k 120 2.8 k

S00 VCC 900 50

A 3.5 k B 12 k 4 k Y A B Y

500

250

1.5 k

3 k GND

GND

Resistor values shown are nominal.

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SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage: 00, S00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V LS00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN5400 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.8 0.4 16 125 0 NOM 5 MAX 5.5 MIN 4.75 2 0.8 0.4 16 70 SN7400 NOM 5 MAX 5.25 UNIT V V V mA mA C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICCH ICCL VCC = MIN, VCC = MIN, VCC = MIN, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX, VCC = MAX, VI = 0 V VI = 4.5 V TEST CONDITIONS II = 12 mA VIL = 0.8 V, VIH = 2 V, VI = 5.5 V VI = 2.4 V VI = 0.4 V 20 4 SN5400 MIN TYP MAX 1.5 IOH = 0.4 mA IOL = 16 mA 2.4 3.4 0.2 0.4 1 40 1.6 55 8 18 4 2.4 3.4 0.2 0.4 1 40 1.6 55 8 22 MIN SN7400 TYP MAX 1.5 UNIT V V V mA A mA mA mA mA

12 22 12 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time.

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SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN RL = 400 , CL = 15 pF SN5400 SN7400 TYP 11 7 MAX 22 15 ns UNIT

A or B

recommended operating conditions (see Note 4)

SN54LS00 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.7 0.4 4 125 0 NOM 5 MAX 5.5 SN74LS00 MIN 4.75 2 0.8 0.4 8 70 NOM 5 MAX 5.25 UNIT V V V mA mA C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICCH ICCL VCC = MIN, VCC = MIN, VCC = MIN, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX, VCC = MAX, VI = 0 V VI = 4.5 V TEST CONDITIONS II = 18 mA VIL = MAX, VIH = 2 V VI = 7 V VI = 2.7V VI = 0.4 V 20 0.8 2.4 SN54LS00 MIN TYP MAX 1.5 IOH = 0.4 mA IOL = 4 mA IOL = 8mA 0.1 20 0.4 100 1.6 4.4 20 0.8 2.4 2.5 3.4 0.25 0.4 2.7 3.4 0.25 0.35 0.4 0.5 0.1 20 0.4 100 1.6 4.4 V mA A mA mA mA mA SN74LS00 MIN TYP MAX 1.5 UNIT V V

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SN54LS00 SN74LS00 MIN RL = 2 k, CL = 15 pF TYP 9 10 MAX 15 15 ns UNIT

A or B

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SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
recommended operating conditions (see Note 5)
SN54S00 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 4.5 2 0.8 1 20 125 0 NOM 5 MAX 5.5 MIN 4.75 2 0.8 1 20 70 SN74S00 NOM 5 MAX 5.25 UNIT V V V mA mA C

NOTE 5: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL IOS ICCH ICCL VCC = MIN, VCC = MIN, VCC = MIN, VCC = MAX, VCC = MAX, VCC = MAX, VCC = MAX VCC = MAX, VCC = MAX, VI = 0 V VI = 4.5 V TEST CONDITIONS II = 18 mA VIL = 0.8 V, VIH = 2 V, VI = 5.5 V VI = 2.7 V VI = 0.5V 40 10 SN54S00 MIN TYP MAX 1.2 IOH = 1 mA IOL = 20 mA 2.5 3.4 0.5 1 50 2 100 16 40 10 2.7 3.4 0.5 1 50 2 100 16 36 MIN SN74S00 TYP MAX 1.2 UNIT V V V mA A mA mA mA mA

20 36 20 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time.

switching characteristics, VCC = 5 V, TA = 25C (see Figure 1)

PARAMETER tPLH tPHL tPLH tPHL A or B Y FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN RL = 280 , RL = 280 , CL = 15 pF SN54S00 SN74S00 TYP 3 3 4.5 5 MAX 4.5 5 ns ns UNIT

A or B

CL = 50 pF

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SN5400, SN54LS00, SN54S00 SN7400, SN74LS00, SN74S00 QUADRUPLE 2 INPUT POSITIVE NAND GATES
SDLS025B DECEMBER 1983 REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION SERIES 54/74 DEVICES

VCC Test Point VCC VCC RL From Output Under Test CL (see Note A) RL (see Note B) From Output Under Test CL (see Note A) Test Point S2 Test Point RL S1 (see Note B) 1 k

From Output Under Test CL (see Note A)

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS Timing Input tsu 1.5 V Data Input 1.5 V

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V 1.5 V 0V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

1.5 V tw

1.5 V

Low-Level Pulse

1.5 V

VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) tPZL Waveform 1 (see Notes C and D) tPZH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Waveform 2 (see Notes C and D)

3V 1.5 V 1.5 V 0V tPLZ 1.5 V VOL tPHZ VOH 1.5 V VOH 0.5 V 1.5 V VOL + 0.5 V

3V Input 1.5 V 1.5 V 0V tPLH In-Phase Output (see Note D) tPHL Out-of-Phase Output (see Note D) 1.5 V tPHL VOH 1.5 V VOL tPLH

1.5 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7 ns for Series 54/74 devices and tr and tf 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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