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    Solution 1

    Uploaded by

    Kamran Sadiq
    This document discusses solutions to increasing computational density while maintaining flexibility in integrated circuit design. It defines flexibility based on the number of different operations available and the ratio of control information to data. It then analyzes the computational density of different processing elements by calculating the operations per second per square millimeter for processors, digital signal processors (DSPs), application-specific instruction-set processors (ASIPs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Flexibility decreases from processors to custom ICs while computational density increases, creating a design dilemma between performance and programmability.

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    Solution 1

    Uploaded by

    Kamran Sadiq
    95 views2 pages
    This document discusses solutions to increasing computational density while maintaining flexibility in integrated circuit design. It defines flexibility based on the number of different operations available and the ratio of control information to data. It then analyzes the computational density of different processing elements by calculating the operations per second per square millimeter for processors, digital signal processors (DSPs), application-specific instruction-set processors (ASIPs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Flexibility decreases from processors to custom ICs while computational density increases, creating a design dilemma between performance and programmability.

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    This document discusses solutions to increasing computational density while maintaining flexibility in integrated circuit design. It defines flexibility based on the number of different operations available and the ratio of control information to data. It then analyzes the computational density of different processing elements by calculating the operations per second per square millimeter for processors, digital signal processors (DSPs), application-specific instruction-set processors (ASIPs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Flexibility decreases from processors to custom ICs while computational density increases, creating a design dilemma between performance and programmability.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    95 views2 pages

    Solution 1

    Uploaded by

    Kamran Sadiq
    This document discusses solutions to increasing computational density while maintaining flexibility in integrated circuit design. It defines flexibility based on the number of different operations available and the ratio of control information to data. It then analyzes the computational density of different processing elements by calculating the operations per second per square millimeter for processors, digital signal processors (DSPs), application-specific instruction-set processors (ASIPs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Flexibility decreases from processors to custom ICs while computational density increases, creating a design dilemma between performance and programmability.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Solutions for Module 1: Introduction

    Pg 1 of 2

    Introduction: The System Design Dilemma Solution 1: Computational Density


    a) One possible definition of flexibility could be derived from an empiric metric for the number of different operations available on a general purpose computing device.
    Processing Element ALU Multiplier Special Execution Unit(s) LUT Standard Cell Transistor Amount of Variation very high high some some very low almost none

    # 1 2 3 4 5 6

    Element Processor DSP ASIP FPGA ASIC Full Custom

    # PEs very few very few few thousands millions 10 millions

    An alternative definition of flexibility could be the amount of control information versus the amount of data flowing into the device. In a processor, for every piece of data that is processed, one or more instructions (control information) are needed. In a full custom chip, no instructions are needed, since all data processing is hard wired. This definition will lead to the same order of flexibility as above.

    b) In a processor, the actual logic computation is carried out in the arithmetical/logical unit. The logic execution part only covers a fraction of the total chip area. The remainder of the chip delivers its flexibility.
    Since this one can ideally do two logical operations on 32-bit words every clock cycle, its raw CD becomes
    CD 2 32 op / Hz 9 mm
    2

    466 MHz
    2

    / 0 . 11

    40

    op s sq

    c) Cache misses (just 1% is enough!) and subsequent DRAM latencies cause the low value. The cache miss rate depends on the application. The effective CD can be calculated as
    CD 0 . 35 32 op / Hz
    2

    466 MHz
    2

    9 mm

    / 0 . 11

    op s sq

    d) ASIPs: Computation can be done as for processors, since they are per se processors with specialized instruction sets and execution units. Raw computational density is:

    Solutions for Module 1: Introduction

    Pg 2 of 2

    CD

    32

    311 MHz

    ( 0 . 11 m )
    2

    270

    op s sq

    0 . 45 mm

    e) FPGAs: Each LUT delivers (at most) one logic operation, thus:
    For the FPGA we get:
    CD 3333 op / Hz 7 mm
    2

    200 MHz
    2

    / 0 . 07

    467

    op s sq

    f)

    Standard cell ASICs: Every cell/flip-flop combination is assumed to deliver (again, at most) one logic operation.
    CD 90 10 1
    6

    mm

    / 0 . 07

    0 . 43 10

    0 . 13 s

    M op s sq

    r esea r ch: SoC

    Dr e a m Ch ip t m

    CPU
    Log F L E X I B I L I T Y

    DSP

    ASIP FPGA

    lo

    gi

    r r e ese co a r nf ch ig : ur ab

    ASIC
    Custom IC

    Log COMPUTATIONAL DENSITY = performance / area

    le

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