Pic 16 C 505

PIC16C505
14-Pin, 8-Bit CMOS Microcontroller

Device included in this Data Sheet:
PIC16C505
Special Microcontroller Features:

In-Circuit Serial Programming (ICSP) Power-on Reset (POR) Device Reset Timer (DRT) Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation Programmable Code Protection Internal weak pull-ups on I/O pins Wake-up from Sleep on pin change Power-saving Sleep mode Selectable oscillator options: - INTRC: Precision internal 4 MHz oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - HS: High speed crystal/resonator - LP: Power saving, low frequency crystal
High-Performance RISC CPU:

Only 33 instructions to learn Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Memory Device Program PIC16C505 1024 x 12 Data 72 x 8
Direct, indirect and relative addressing modes for data and instructions 12-bit wide instructions 8-bit wide data path 2-level deep hardware stack Eight special function hardware registers Direct, indirect and relative addressing modes for data and instructions All single cycle instructions (200 ns) except for program branches which are two-cycle
CMOS Technology:
Low-power, high-speed CMOS EPROM technology Fully static design Wide operating voltage range (2.5V to 5.5V) Wide temperature ranges - Commercial: 0C to +70C - Industrial: -40C to +85C - Extended: -40C to +125C - < 1.0 A typical standby current @ 5V Low power consumption - < 2.0 mA @ 5V, 4 MHz - 15 A typical @ 3.0V, 32 kHz for TMR0 running in SLEEP mode - < 1.0 A typical standby current @ 5V
Peripheral Features:
11 I/O pins with individual direction control 1 input pin High current sink/source for direct LED drive Timer0: 8-bit timer/counter with 8-bit programmable prescaler
Pin Diagram:
PDIP, SOIC, Ceramic Side Brazed
VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/VPP RC5/T0CKI RC4 RC3
14
2 3 4 5 6 7
13 12 11 10 9 8
VSS RB0 RB1 RB2 RC0 RC1 RC2
1999 Microchip Technology Inc.
PIC16C505
DS40192C-page 1
PIC16C505
TABLE OF CONTENTS
1.0 General Description..................................................................................................................................................................... 3 2.0 PIC16C505 Device Varieties ....................................................................................................................................................... 5 3.0 Architectural Overview ................................................................................................................................................................ 7 4.0 Memory Organization ................................................................................................................................................................ 11 5.0 I/O Port ...................................................................................................................................................................................... 19 6.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 23 7.0 Special Features of the CPU ..................................................................................................................................................... 27 8.0 Instruction Set Summary ........................................................................................................................................................... 39 9.0 Development Support................................................................................................................................................................ 51 10.0 Electrical Characteristics - PIC16C505 ..................................................................................................................................... 57 11.0 DC and AC Characteristics - PIC16C505.................................................................................................................................. 71 11.0 Packaging Information............................................................................................................................................................... 75 Index .................................................................................................................................................................................................... 79 On-Line Support................................................................................................................................................................................... 81 Reader Response ................................................................................................................................................................................ 82 PIC16C505 Product Identification System .......................................................................................................................................... 83
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DS40192C-page 2
PIC16C505
1.0 GENERAL DESCRIPTION
1.1 Applications
The PIC16C505 from Microchip Technology is a lowcost, high-performance, 8-bit, fully static, EPROM/ ROM-based CMOS microcontroller. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 s) except for program branches, which take two cycles. The PIC16C505 delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C505 product is equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are five oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC16C505 is available in the cost-effective OneTime-Programmable (OTP) version, which is suitable for production in any volume. The customer can take full advantage of Microchips price leadership in OTP microcontrollers, while benefiting from the OTPs flexibility. The PIC16C505 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a C compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM PC and compatible machines. The PIC16C505 fits in applications ranging from personal care appliances and security systems to lowpower remote transmitters/receivers. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller perfect for applications with space limitations. Low-cost, low-power, highperformance, ease of use and I/O flexibility make the PIC16C505 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of glue logic and PLDs in larger systems, and coprocessor applications).
DS40192C-page 3
PIC16C505
TABLE 1-1: PIC16C505 DEVICE
PIC16C505 Clock Memory Maximum Frequency of Operation (MHz) EPROM Program Memory Data Memory (bytes) Timer Module(s) Peripherals Wake-up from SLEEP on pin change I/O Pins Input Pins Features Internal Pull-ups In-Circuit Serial Programming Number of Instructions Packages 20 1024 72 TMR0 Yes 11 1 Yes Yes 33 14-pin DIP, SOIC, JW
The PIC16C505 device has Power-on Reset, selectable Watchdog Timer, selectable code protect, high I/O current capability and precision internal oscillator. The PIC16C505 device uses serial programming with data pin RB0 and clock pin RB1.
DS40192C-page 4
PIC16C505
2.0 PIC16C505 DEVICE VARIETIES
2.3
A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C505 Product Identification System at the back of this data sheet to specify the correct part number.
Quick-Turnaround-Production (QTP) Devices
2.1
UV Erasable Devices
The UV erasable version, offered in a ceramic windowed package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.
Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program medium to high quantity units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround Production (SQTPSM) Devices
Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry-code, password or ID number.
Microchips PICSTART PLUS and PRO MATE II programmers all support programming of the PIC16C505. Third party programmers also are available; refer to the Microchip Third Party Guide, (DS00104), for a list of sources.
2.2
One-Time-Programmable (OTP) Devices
The availability of OTP devices is especially useful for customers who need the flexibility of frequent code updates or small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.
DS40192C-page 5
PIC16C505
NOTES:
DS40192C-page 6
PIC16C505
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C505 can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C505 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MHz) except for program branches. The Table below lists program memory (EPROM) and data memory (RAM) for the PIC16C505. Memory Device Program PIC16C505 1024 x 12 Data 72 x 8 The PIC16C505 device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.
The PIC16C505 can directly or indirectly address its register files and data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C505 has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of special optimal situations make programming with the PIC16C505 simple yet efficient. In addition, the learning curve is reduced significantly.
DS40192C-page 7
PIC16C505
FIGURE 3-1: PIC16C505 BLOCK DIAGRAM
12 EPROM 1K x 12 Program Memory Program Counter Data Bus 8 PORTB RB0 RB1 RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN PORTC RC0 RC1 RC2 RC3 RC4 RC5/T0CKI
STACK1 STACK2
RAM 72 bytes File Registers RAM Addr 9
Program Bus
12
Instruction reg Direct Addr 5
Addr MUX Indirect 5-7 Addr FSR reg 8 3 STATUS reg
Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2 Timing Generation Power-on Reset 8 Watchdog Timer Internal RC OSC
MUX
ALU
W reg
Timer0
MCLR VDD, VSS
DS40192C-page 8
PIC16C505
TABLE 3-1:
Name RB0
PIC16C505 PINOUT DESCRIPTION

DIP Pin # 13 SOIC Pin # 13 I/O/P Type I/O Buffer Type Description
TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. TTL Bi-directional I/O port. TTL/ST Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pullup only when configured as RB3. ST when configured as MCLR. TTL Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator mode (XT and LP modes only, RB4 in other modes). Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. In EXTRC and INTRC modes, the pin output can be configured to CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.
RB1
12
12
I/O
RB2 RB3/MCLR/VPP
11 4
11 4
I/O I
RB4/OSC2/CLKOUT
I/O
RB5/OSC1/CLKIN
I/O
TTL/ST Bidirectional IO port/oscillator crystal input/external clock source input (RB5 in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when RB5, ST input in external RC oscillator mode. TTL TTL TTL TTL TTL ST Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Can be configured as T0CKI. Positive supply for logic and I/O pins Ground reference for logic and I/O pins
RC0 RC1 RC2 RC3 RC4 RC5/T0CKI VDD VSS
10 9 8 7 6 5 1 14
10 9 8 7 6 5 1 14
I/O I/O I/O I/O I/O I/O P P
Legend: I = input, O = output, I/O = input/output, P = power, = not used, TTL = TTL input, ST = Schmitt Trigger input
DS40192C-page 9
PIC16C505
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. An Instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC PC Fetch INST (PC) Execute INST (PC-1) PC+1 PC+2 Internal phase clock Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Fetch INST (PC+1) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1:
1. MOVLW 03H 2. MOVWF PORTB 3. CALL 4. BSF SUB_1
INSTRUCTION PIPELINE FLOW

Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
PORTB, BIT1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is flushed from the pipeline, while the new instruction is being fetched and then executed.
DS40192C-page 10
PIC16C505
4.0 MEMORY ORGANIZATION
FIGURE 4-1:
PIC16C505 memory is organized into program memory and data memory. For the PIC16C505, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. Data memory banks are accessed using the File Select Register (FSR).
PROGRAM MEMORY MAP AND STACK FOR THE PIC16C505

PC<11:0> 12 Stack Level 1 Stack Level 2
CALL, RETLW
4.1
Program Memory Organization
The PIC16C505 devices have a 12-bit Program Counter (PC). The 1K x 12 (0000h-03FFh) for the PIC16C505 are physically implemented. Refer to Figure 4-1. Accessing a location above this boundary will cause a wrap-around within the first 1K x 12 space. The effective reset vector is at 0000h, (see Figure 4-1). Location 03FFh contains the internal clock oscillator calibration value. This value should never be overwritten.
Reset Vector (note 1)
0000h
User Memory Space
01FFh 0200h
On-chip Program Memory
1024 Words
03FFh 0400h
7FFh
Note 1:
Address 0000h becomes the effective reset vector. Location 03FFh contains the MOVLW XX INTERNAL RC oscillator calibration value.
DS40192C-page 11
PIC16C505
4.2 Data Memory Organization
Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers and General Purpose Registers. The Special Function Registers include the TMR0 register, the Program Counter (PCL), the Status Register, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Function Registers are used to control the I/O port configuration and prescaler options. The General Purpose Registers are used for data and control information under command of the instructions. For the PIC16C505, the register file is composed of 8 Special Function Registers, 24 General Purpose Registers and 48 General Purpose Registers that may be addressed using a banking scheme (Figure 4-2). 4.2.1 GENERAL PURPOSE REGISTER FILE
The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register FSR (Section 4.8).
FIGURE 4-2:
PIC16C505 REGISTER FILE MAP

FSR<6:5> File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Fh 10h General Purpose Registers 1Fh Bank 0 Note 1: Not a physical register. 3Fh Bank 1 00 INDF(1) TMR0 PCL STATUS FSR OSCCAL PORTB PORTC General Purpose Registers Addresses map back to addresses in Bank 0. 20h 01 40h 10 60h 11
2Fh 30h General Purpose Registers
4Fh 50h General Purpose Registers 5Fh Bank 2
6Fh 70h General Purpose Registers 7Fh Bank 3
DS40192C-page 12
PIC16C505
4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Value on Power-On Reset xxxx xxxx xxxx xxxx 1111 1111
PAO TO PD Z DC C
Address
00h 01h 02h(1) 03h 04h 05h N/A N/A N/A 06h 07h
Name
INDF TMR0 PCL STATUS FSR OSCCAL TRISB TRISC OPTION PORTB PORTC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on All Other Resets(2) uuuu uuuu uuuu uuuu 1111 1111 q00q quuu(1) 11uu uuuu uuuu uu---11 1111 --11 1111 1111 1111 --uu uuuu --uu uuuu
Uses contents of FSR to address data memory (not a physical register) 8-bit real-time clock/counter Low order 8 bits of PC RBWUF
0001 1xxx 110x xxxx
Indirect data memory address pointer CAL5 RBWU CAL4 RBPU CAL3 CAL2 CAL1 CAL0
1000 00---11 1111 --11 1111
I/O control registers I/O control registers TOCS RB5 RC5 TOSE RB4 RC4 PSA RB3 RC3 PS2 RB2 RC2 PS1 RB1 RC1 PS0 RB0 RC0
1111 1111 --xx xxxx --xx xxxx
Legend: Shaded cells not used by Port Registers, read as 0, = unimplemented, read as 0, x = unknown, u = unchanged, q = depends on condition. Note 1: If reset was due to wake-up on pin change, then bit 7 = 1. All other rests will cause bit 7 = 0. Note 2: Other (non-power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.
DS40192C-page 13
PIC16C505
4.3 STATUS Register
This register contains the arithmetic status of the ALU, the RESET status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register, because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary.
REGISTER 4-1:
R/W-0 RBWUF bit7 R/W-0
STATUS REGISTER (ADDRESS:03h)

R/W-0 PA0 5 R-1 TO 4 R-1 PD 3 R/W-x Z 2 R/W-x DC 1 R/W-x C bit0
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
bit 7:
RBWUF: I/O reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset Unimplemented PA0: Program page preselect bits 1 = Page 1 (200h - 3FFh) 0 = Page 0 (000h - 1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 = A carry occurred 1 = A borrow did not occur 0 = A carry did not occur 0 = A borrow occurred RRF or RLF Load bit with LSB or MSB, respectively
bit 6: bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
DS40192C-page 14
PIC16C505
4.4 OPTION Register
Note: The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits. If TRIS bit is set to 0, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides OPTION control of RBPU and RBWU).
REGISTER 4-2:
W-1 RBWU bit7 W-1 RBPU 6
OPTION REGISTER
W-1 T0CS 5 W-1 T0SE 4 W-1 PSA 3 W-1 PS2 2 W-1 PS1 1 W-1 PS0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
bit 7:
RBWU: Enable wake-up on pin change (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled RBPU: Enable weak pull-ups (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin (overrides TRIS <RC57> 0 = Transition on internal instruction cycle clock, Fosc/4 T0SE: Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS<2:0>: Prescaler rate select bits Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6:
bit 5:
bit 4:
bit 3:
bit 2-0:
DS40192C-page 15
PIC16C505
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part, so it can be reprogrammed correctly later.
After you move in the calibration constant, do not change the value. See Section 7.2.5
REGISTER 4-3:
R/W-1 CAL5 bit7 R/W-0 CAL4
OSCCAL REGISTER (ADDRESS 05h) PIC16C505

R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 U-0 U-0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset
bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented read as 0
DS40192C-page 16
PIC16C505
4.6 Program Counter
4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4-3). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-3). Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5. Note: Because PC<8> is cleared in the CALL instruction or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction.) After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected. Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.
4.7
Stack
PIC16C505 devices have a 12-bit wide hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.
FIGURE 4-3:
LOADING OF PC BRANCH INSTRUCTIONS PIC16C505
GOTO Instruction
11 10 PC 9 8 7 PCL 0
Instruction Word PA0 7 0
Note 1: There are no STATUS bits to indicate stack overflows or stack underflow conditions. Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETLW, and instructions.
STATUS
CALL or Modify PCL Instruction

11 10 PC 9 8 7 PCL 0
Instruction Word Reset to 0 PA0 7 0
STATUS
DS40192C-page 17
PIC16C505
4.8 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
NEXT
EXAMPLE 4-1:
INDIRECT ADDRESSING
movlw movwf clrf incf btfsc goto : :
CONTINUE
Register file 07 contains the value 10h Register file 08 contains the value 0Ah Load the value 07 into the FSR register A read of the INDF register will return the value of 10h Increment the value of the FSR register by one (FSR = 08) A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.
The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. The device uses FSR<6:5> to select between banks 0:3.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Indirect Addressing 0 6 5 4 (FSR) 0
Direct Addressing (FSR) 6 5 4 (opcode)
bank select
location select 00 00h

Addresses map back to addresses in Bank 0.
bank 01 10 11
location select
Data Memory(1)
0Fh 10h
1Fh Bank 0
3Fh Bank 1
5Fh Bank 2
7Fh Bank 3
Note 1: For register map detail see Section 4.2.
DS40192C-page 18
PIC16C505
5.0 I/O PORT
5.4 I/O Interfacing
As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pins input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins except RB3, which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB3) can be programmed individually as input or output.
5.1
PORTB
PORTB is an 8-bit I/O register. Only the low order 6 bits are used (RB<5:0>). Bits 7 and 6 are unimplemented and read as '0's. Please note that RB3 is an input only pin. The configuration word can set several I/Os to alternate functions. When acting as alternate functions, the pins will read as 0 during port read. Pins RB0, RB1, RB3 and RB4 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as MCLR, weak pull-up is always off and wake-up on change for this pin is not enabled.
FIGURE 5-1:
Data Bus D WR Port
EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

Q Data Latch CK Q VDD P
5.2
PORTC
W Reg N D TRIS Latch TRIS f CK Q Q VSS I/O pin(1)
PORTC is an 8-bit I/O register. Only the low order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as 0s.
5.3
TRIS Registers
The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are RB3, which is input only, and RC5, which may be controlled by the option register. See Register 4-2. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.
Reset
(2)
RD Port Note 1: Note 2: I/O pins have protection diodes to VDD and VSS. See Table 3-1 for buffer type.
The TRIS registers are write-only and are set (output drivers disabled) upon RESET.
DS40192C-page 19
PIC16C505
TABLE 5-1: SUMMARY OF PORT REGISTERS
Value on Power-On Reset --11 1111 --11 1111
PSA PD RB3 RC3 PS2 Z RB2 RC2 PS1 DC RB1 RC1 PS0 C RB0 RC0
Address
N/A N/A N/A 03h 06h 07h
Name
TRISB TRISC OPTION STATUS PORTB PORTC
Bit 7
RBWU RBWUF
Bit 6
RBPU
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on All Other Resets --11 1111 --11 1111 1111 1111 q00q quuu(1) --uu uuuu --uu uuuu
I/O control registers I/O control registers TOCS PAO RB5 RC5 TOSE TO RB4 RC4
1111 1111 0001 1xxx --xx xxxx --xx xxxx
Legend: Shaded cells not used by Port Registers, read as 0, = unimplemented, read as 0, x = unknown, u = unchanged, q = depends on condition. Note 1: If reset was due to wake-up on pin change, then bit 7 = 1. All other rests will cause bit 7 = 0.
5.5
5.5.1
I/O Programming Considerations

BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wiredand). The resulting high output currents may damage the chip.
;Initial PORTB Settings ; PORTB<5:3> Inputs ; PORTB<2:0> Outputs ; ; PORTB latch PORTB pins ; ---------- ---------BCF PORTB, 5 ;--01 -ppp --11 pppp BCF PORTB, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS PORTB ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;RB5 to be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
DS40192C-page 20
PIC16C505
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 PC + 3 NOP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched RB<5:0> Port pin written here Instruction executed MOVWF PORTB (Write to PORTB) Port pin sampled here MOVF PORTB,W (Read PORTB) MOVWF PORTB PC + 1 MOVF PORTB,W PC + 2 NOP
This example shows a write to PORTB followed by a read from PORTB. Data setup time = (0.25 TCY TPD) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
NOP
DS40192C-page 21
PIC16C505
NOTES:
DS40192C-page 22
PIC16C505
6.0 TIMER0 MODULE AND TMR0 REGISTER
Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 6-1.
The Timer0 module has the following features: 8-bit timer/counter register, TMR0 - Readable and writable 8-bit software programmable prescaler Internal or external clock select - Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register.
FIGURE 6-1:
RC5/T0CKI Pin
TIMER0 BLOCK DIAGRAM

Data Bus FOSC/4 0 1 1 Programmable Prescaler(2) 0 PSout Sync with Internal Clocks 8 TMR0 reg
T0SE 3 T0CS(1) PS2, PS1, PS0(1) PSA(1)
PSout (2 TCY delay) Sync
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
DS40192C-page 23
PIC16C505
FIGURE 6-2:
PC (Program Counter) Instruction Fetch
T0
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Timer0 Instruction Executed
T0+1
T0+2
NT0
NT0+1
NT0+2
Write TMR0 executed
Read TMR0 Read TMR0 reads NT0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
FIGURE 6-3:
PC (Program Counter) Instruction Fetch Timer0 Instruction Execute
T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
NT0
NT0+1
T0
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0 + 1
TABLE 6-1:
Address 01h N/A N/A
REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on Power-On Reset Value on All Other Resets
TMR0 OPTION TRISC
Timer0 - 8-bit real-time clock/counter RBWU RBPU T0CS RC5 T0SE RC4 PSA RC3 PS2 RC2 PS1 RC1 PS0 RC0
xxxx xxxx uuuu uuuu 1111 1111 1111 1111 --11 1111 --11 1111
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged.
DS40192C-page 24
PIC16C505
6.1 Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 TIMER0 INCREMENT DELAY
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler Output (2) (1) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3)
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.
DS40192C-page 25
PIC16C505
6.2 Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (Section 7.6). For simplicity, this counter is being referred to as prescaler throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's. 6.2.1 SWITCHING PRESCALER ASSIGNMENT
CLRWDT MOVLW
RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.
EXAMPLE 6-1:
CHANGING PRESCALER (TIMER0WDT)
1.CLRWDT 2.CLRF TMR0 3.MOVLW '00xx1111b 4.OPTION
;Clear WDT ;Clear TMR0 & Prescaler ;These 3 lines (5, 6, 7) ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 6.MOVLW '00xx1xxxb ;Set Postscaler to 7.OPTION ; desired WDT rate
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 6-2:
CHANGING PRESCALER (WDTTIMER0)

;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source
The prescaler assignment is fully under software control (i.e., it can be changed on-the-fly during program execution). To avoid an unintended device
'xxxx0xxx'
OPTION
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Data Bus
TCY ( = Fosc/4) 0 1 M U X 1 0 T0SE M U X Sync 2 Cycles TMR0 reg 8
RC5/T0CKI Pin
T0CS
PSA
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS<2:0>
Watchdog Timer
PSA WDT Enable bit 0 MUX 1 PSA
WDT Time-Out Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
DS40192C-page 26
PIC16C505
7.0 SPECIAL FEATURES OF THE CPU
The PIC16C505 has a Watchdog Timer, which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS, XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC, there is an 18 ms delay only on VDD power-up. With this timer on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16C505 microcontroller has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: Oscillator selection Reset - Power-On Reset (POR) - Device Reset Timer (DRT) - Wake-up from SLEEP on pin change Watchdog Timer (WDT) SLEEP Code protection ID locations In-circuit Serial Programming Clock Out
7.1
Configuration Bits
The PIC16C505 configuration word consists of 12 bits. Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR enable bit. Seven bits are for code protection (Register 7-1).
REGISTER 7-1:
CP bit11 bit 5: CP 10
CONFIGURATION WORD FOR PIC16C505

CP 9 CP 8 CP 7 CP 6 MCLRE 5 CP 4 WDTE FOSC2 FOSC1 FOSC0 3 2 1 bit0 Register: CONFIG Address(2): 0FFFh
bit 11-6, 4: CP Code Protection bits (1)(2)(3) MCLRE: RB3/MCLR pin function select 1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC<1:0>: Oscillator Selection bits 111 = external RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 110 = external RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 101 = internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 100 = internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator 03FFh is always uncode protected on the PIC16C505. This location contains the MOVLWxx calibration instruction for the INTRC. Refer to the PIC16C505 Programming Specifications to determine how to access the configuration word. This register is not user addressable during device operation. All code protect bits must be written to the same value.
bit 3:
bit 2-0:
Note 1: 2: 3:
DS40192C-page 27
PIC16C505
7.2
7.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 7-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16C505

Cap. Range C1 Cap. Range C2
The PIC16C505 can be operated in four different oscillator modes. The user can program three configuration bits (FOSC<2:0>) to select one of these four modes: LP: XT: HS: INTRC: EXTRC: Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor
Osc Type
Resonator Freq
XT 4.0 MHz 30 pF 30 pF HS 16 MHz 10-47 pF 10-47 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 7-2:
7.2.2
CRYSTAL OSCILLATOR / CERAMIC RESONATORS Osc Type LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR PIC16C505

Cap.Range C1 Cap. Range C2
In HS, XT or LP modes, a crystal or ceramic resonator is connected to the RB5/OSC1/CLKIN and RB4/ OSC2/CLKOUT pins to establish oscillation (Figure 7-1). The PIC16C505 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS, XT or LP modes, the device can have an external clock source drive the RB5/OSC1/CLKIN pin (Figure 7-2).
Resonator Freq
FIGURE 7-1:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

OSC1
C1(1)
15 pF 15 pF 32 kHz(1) 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF HS 20 MHz 15-47 pF 15-47 pF Note 1: For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
PIC16C505
SLEEP
XTAL RS(2) C2(1) Note 1: 2: 3: OSC2
RF(3)
To internal logic
See Capacitor Selection tables for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF approx. value = 10 M.
FIGURE 7-2:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)

OSC1 PIC16C505
Clock from ext. system Open
OSC2
DS40192C-page 28
PIC16C505
7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 7.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-5 shows how the R/C combination is connected to the PIC16C505. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications section shows RC frequency variation from part to part due to normal process variation. The variation is larger for larger values of R (since leakage current variation will affect RC frequency more for large R) and for smaller values of C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications section for variation of oscillator frequency due to VDD for given Rext/Cext values, as well as frequency variation due to operating temperature for given R, C and VDD values.
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 7-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.
FIGURE 7-3:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other Devices
+5V 10k 4.7k 74AS04 74AS04 PIC16C505 CLKIN
10k XTAL 10k 20 pF 20 pF
Figure 7-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 7-5:
VDD Rext
EXTERNAL RC OSCILLATOR MODE
FIGURE 7-4:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT

330 74AS04 74AS04 To Other Devices PIC16C505 CLKIN
OSC1 N
Internal clock
Cext VSS FOSC/4
PIC16C505
330 74AS04 0.1 mF XTAL
OSC2/CLKOUT
DS40192C-page 29
PIC16C505
7.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25C, see Electrical Specifications section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the last address of memory, which contains the calibration value for the internal RC oscillator. This location is always protected, regardless of the code protect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will trim the internal oscillator to remove process variation from the oscillator frequency. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.
For the PIC16C505, only bits <7:2> of OSCCAL are implemented.
7.3
RESET
The device differentiates between various kinds of reset: a) Power on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) Wake-up from SLEEP on pin change Some registers are not reset in any way, they are unknown on POR and unchanged in any other reset. Most other registers are reset to reset state on poweron reset (POR), MCLR, WDT or wake-up on pin change reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are TO, PD and RBWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of reset. See Table 7-3 for a full description of reset states of all registers.
DS40192C-page 30
PIC16C505
TABLE 7-3: RESET CONDITIONS FOR REGISTERS
Address 00h 01h 02h 03h 04h 05h 06h 07h Power-on Reset qqqq qqqq(1) xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 110x xxxx 1000 00---xx xxxxx --xx xxxxx 1111 1111 --11 1111 --11 1111 MCLR Reset WDT time-out Wake-up on Pin Change qqqq qqqq(1) uuuu uuuu uuuu uuuu 1111 1111 q00q quuu(2,3) 11uu uuuu uuuu uu---uu uuuu --uu uuuu 1111 1111 --11 1111 --11 1111 Register W INDF TMR0 PC STATUS FSR OSCCAL PORTB PORTC OPTION TRISB TRISC Note 1: Note 2: Note 3:
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition. Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. See Table 7-7 for reset value for specific conditions. If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h PCL Addr: 02h 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Power on reset MCLR reset during normal operation MCLR reset during SLEEP WDT reset during SLEEP WDT reset normal operation Wake-up from SLEEP on pin change
0001 1xxx 000u uuuu 0001 0uuu 0000 0uuu 0000 uuuu 1001 0uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0.
DS40192C-page 31
PIC16C505
7.3.1 MCLR ENABLE This configuration bit when unprogrammed (left in the 1 state) enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD, and the pin is assigned to be a I/O. See Figure 7-6. The Power-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the onchip reset signal. A power-up example where MCLR is held low is shown in Figure 7-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 7-9, the on-chip Power-On Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be RB3.). The VDD is stable before the start-up timer times out and there is no problem in getting a proper reset. However, Figure 7-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip may not function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-9). Note: When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.
FIGURE 7-6:
RBWU MCLRE
MCLR SELECT
WEAK PULL-UP RB3/MCLR/VPP
INTERNAL MCLR
7.4
Power-On Reset (POR)
The PIC16C505 family incorporates on-chip Power-On Reset (POR) circuitry, which provides an internal chip reset for most power-up situations. The on chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program the RB3/MCLR/VPP pin as MCLR and tie through a resistor to VDD or program the pin as RB3. An internal weak pull-up resistor is implemented using a transistor. Refer to Table 10-1 for the pull-up resistor ranges. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 7-7.
For additional information refer to Application Notes Power-Up Considerations - AN522 and Power-up Trouble Shooting - AN607.
DS40192C-page 32
PIC16C505
FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up Detect VDD POR (Power-On Reset) Pin Change SLEEP RB3/MCLR/VPP Wake-up on pin change
WDT Time-out MCLRE 8-bit Asynch On-Chip DRT OSC Ripple Counter (Start-Up Timer) RESET
Q
CHIP RESET
FIGURE 7-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT INTERNAL RESET
FIGURE 7-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT
INTERNAL RESET
DS40192C-page 33
PIC16C505
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR INTERNAL POR TDRT
DRT TIME-OUT
INTERNAL RESET
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
7.5
Device Reset Timer (DRT)
7.6
Watchdog Timer (WDT)
In the PIC16C505, the DRT runs any time the device is powered up. DRT runs from RESET and varies based on oscillator selection and reset type (see Table 7-5). The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high (VIHMCLR) level. Thus, programming RB3/MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the RB3/ MCLR/VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip due to VDD, temperature and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake from SLEEP mode automatically. Reset sources are POR, MCLR, WDT time-out and Wake-up on pin change. (See Section 7.9.2, Notes 1, 2, and 3, page 37.)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the RB5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a 0 (Section 7.1). Refer to the PIC16C505 Programming Specifications to determine how to access the configuration word.
TABLE 7-5:
Oscillator Configuration IntRC & ExtRC HS, XT & LP
DRT (DEVICE RESET TIMER PERIOD)

POR Reset 18 ms (typical) 18 ms (typical) Subsequent Resets 300 s (typical) 18 ms (typical)
DS40192C-page 34
PIC16C505
7.6.1 WDT PERIOD 7.6.2 WDT PROGRAMMING CONSIDERATIONS The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-topart process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.
FIGURE 7-11: WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source (Figure 6-5)
0 Watchdog Timer 1 M U X 8 - to - 1 MUX WDT Enable Configuration Bit To Timer0 (Figure 6-4) 1 MUX Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. WDT Time-out PSA PSA PS<2:0> Postscaler Postscaler
TABLE 7-6:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on Power-On Reset 1111 1111 Value on All Other Resets 1111 1111
Address N/A
Name OPTION
Bit 7 RBWU
Bit 6 RBPU
Bit 5 T0CS
Bit 4 T0SE
Bit 3 PSA
Bit 2 PS2
Bit 1 PS1
Bit 0 PS0
Legend: Shaded boxes = Not used by Watchdog Timer, = unimplemented, read as '0', u = unchanged.
DS40192C-page 35
PIC16C505
7.7 Time-Out Sequence, Power Down, and Wake-up from SLEEP Status Bits (TO/PD/RBWUF) FIGURE 7-13: BROWN-OUT PROTECTION CIRCUIT 2
VDD VDD R1 Q1 MCLR(1) R2 40k* PIC16C505
The TO, PD, and RBWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset.
TABLE 7-7:
RBWUF TO
0 0 0 0 0 1 0 0 1 1 u 1
TO/PD/RBWUF STATUS AFTER RESET

PD
0 u 0 1 u 0
RESET caused by WDT wake-up from SLEEP WDT time-out (not from SLEEP) MCLR wake-up from SLEEP Power-up MCLR not during SLEEP Wake-up from SLEEP on pin change
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD R1 R1 + R2 = 0.7V
Note 1: Pin must be confirmed as MCLR.
Legend: u = unchanged Note 1: The TO, PD, and RBWUF bits maintain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO, PD, and RBWUF status bits.
FIGURE 7-14: BROWN-OUT PROTECTION CIRCUIT 3

VDD MCP809 VSS RST MCLR PIC12C5XX This brown-out protection circuit employs Microchip Technologys MCP809 microcontroller supervisor. There are 7 different trip point selections to accommodate 5V to 3V systems. bypass capacitor VDD
7.8
Reset on Brown-Out
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC16C505 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-12 and Figure 7-13.
VDD
FIGURE 7-12: BROWN-OUT PROTECTION CIRCUIT 1

VDD VDD 33k 10k Q1 MCLR(1) PIC16C505
40k*
This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). Note 1: Pin must be confirmed as MCLR.
DS40192C-page 36
PIC16C505
7.9 Power-Down Mode (SLEEP) 7.10 Program Verification/Code Protection
A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 7.9.1 SLEEP If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting.
The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the RB3/ MCLR/VPP pin must be at a logic high level (VIHMC) if MCLR is enabled. 7.9.2 WAKE-UP FROM SLEEP
7.11
ID Locations
Four memory locations are designated as ID locations where the user can store checksum or other codeidentification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as 0s.
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. An external reset input on RB3/MCLR/VPP pin, when configured as MCLR. A Watchdog Timer time-out reset (if WDT was enabled). A change on input pin RB0, RB1, RB3 or RB4 when wake-up on change is enabled.
These events cause a device reset. The TO, PD, and RBWUF bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The RBWUF bit indicates a change in state while in SLEEP at pins RB0, RB1, RB3 or RB4 (since the last file or bit operation on RB port). Caution: Right before entering SLEEP, read the input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake-up will occur immediately even if no pins change while in SLEEP mode. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source.
DS40192C-page 37
PIC16C505
7.12 In-Circuit Serial Programming
The PIC16C505 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB1 and RB0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB1 becomes the programming clock and RB0 becomes the programming data. Both RB1 and RB0 are Schmitt Trigger inputs in this mode. After reset, a 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C505 Programming Specifications. A typical in-circuit serial programming connection is shown in Figure 7-15.
FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION

To Normal Connections PIC16C505 VDD VSS MCLR/VPP RB1 RB0 VDD To Normal Connections
External Connector Signals +5V 0V VPP CLK Data I/O
DS40192C-page 38
PIC16C505
8.0 INSTRUCTION SET SUMMARY
Each PIC16C505 instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16C505 instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, f represents a file register designator and d represents a destination designator. The file register designator is used to specify which one of the 32 file registers is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is 0, the result is placed in the W register. If d is 1, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the number of the file in which the bit is located. For literal and control operations, k represents an 8 or 9-bit constant or literal value. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Figure 8-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where h signifies a hexadecimal digit.
FIGURE 8-1:
GENERAL FORMAT FOR INSTRUCTIONS

6 5 d 4 f (FILE #) 0
Byte-oriented file register operations 11 OPCODE
d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 8 7 5 4 b (BIT #) f (FILE #) 0
TABLE 8-1:
Field
f W b k
OPCODE FIELD DESCRIPTIONS

Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Dont care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d = 1 (store result in file register f) Default is d = 1 Label name Top of Stack Program Counter Watchdog Timer Counter Time-Out bit Power-Down bit Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier) 11
b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 8 OPCODE k = 8-bit immediate value Literal and control operations - GOTO instruction 11 OPCODE k = 9-bit immediate value 9 8 k (literal) 0 7 k (literal) 0
label TOS PC WDT TO PD
dest [ ] ( ) <>
italics
DS40192C-page 39
PIC16C505
TABLE 8-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW f,d f,d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, b f, b f, b f, b k k k k k k k f k
INSTRUCTION SET SUMMARY

12-Bit Opcode Description Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set AND literal with W Call subroutine Clear Watchdog Timer Unconditional branch Inclusive OR Literal with W Move Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W Cycles 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 2 1 2 1 1 1 2 1 1 1 MSb 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df LSb ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff Status Affected Notes C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z None None None None Z None TO, PD None Z None None None TO, PD None Z 1,2,4 2,4 4
2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 2,4 2,4
BIT-ORIENTED FILE REGISTER OPERATIONS 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff
LITERAL AND CONTROL OPERATIONS 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk 1
Note 1: The 9th bit of the program counter will be forced to a 0 by any instruction that writes to the PC except for GOTO. (Section 4.6) 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of PORTB. A 1 forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).
DS40192C-page 40
PIC16C505
ADDWF Syntax: Operands: Operation: Encoding: Description: Add W and f [ label ] ADDWF 0 f 31 d [0,1] (W) + (f) (dest)
0001 11df ffff
ANDWF f,d Syntax: Operands: Operation: Encoding: Description:
AND W with f [ label ] ANDWF 0 f 31 d [0,1] (W) .AND. (f) (dest)

0001 01df ffff
f,d
Status Affected: C, DC, Z Add the contents of the W register and register f. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 1 1
ADDWF 0x17 0xC2 0xD9 0xC2 FSR, 0
Status Affected: Z The contents of the W register are ANDed with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is '1', the result is stored back in register 'f'. 1 1
ANDWF 0x17 0xC2 0x17 0x02 FSR, 1
Words: Cycles: Example:

W = FSR = W = FSR =

W = FSR = W = FSR =
Before Instruction
Before Instruction
After Instruction
After Instruction
ANDLW Syntax: Operands: Operation: Encoding: Description:
And literal with W [ label ] ANDLW 0 k 255 (W).AND. (k) (W) k
BCF Syntax: Operands: Operation:
Bit Clear f [ label ] BCF 0 f 31 0b7 0 (f<b>)

0100 bbbf ffff
f,b
Status Affected: Z
1110 kkkk kkkk
Status Affected: None Encoding: Description: Words: Cycles: Example: 1 1

BCF FLAG_REG, 7
The contents of the W register are ANDed with the eight-bit literal 'k'. The result is placed in the W register. 1 1
ANDLW = = 0xA3 0x03 0x5F
Bit 'b' in register 'f' is cleared.

W W
Before Instruction
FLAG_REG = 0xC7
Before Instruction After Instruction
After Instruction
FLAG_REG = 0x47
DS40192C-page 41
PIC16C505
BSF Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example: 1 1
BSF FLAG_REG, 7
Bit Set f [ label ] BSF 0 f 31 0b7 1 (f<b>)

0101 bbbf ffff
BTFSS f,b Syntax: Operands: Operation: Encoding: Description:
Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 31 0b<7 skip if (f<b>) = 1
Status Affected: None Bit b in register f is set.
Status Affected: None

0111 bbbf ffff
Before Instruction
FLAG_REG = 0x0A
If bit b in register f is 1, then the next instruction is skipped. If bit b is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2 cycle instruction. 1 1(2)
HERE FALSE TRUE BTFSS GOTO FLAG,1 PROCESS_CODE
After Instruction
FLAG_REG = 0x8A
BTFSC Syntax: Operands: Operation: Encoding: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 31 0b7 skip if (f<b>) = 0 0110
Before Instruction
PC = = = = = address (HERE) 0, address (FALSE); 1, address (TRUE)
After Instruction
ffff If FLAG<1> PC if FLAG<1> PC

bbbf
If bit b in register f is 0, then the next instruction is skipped. If bit b is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction. 1 1(2)
HERE FALSE TRUE BTFSC GOTO
FLAG,1 PROCESS_CODE
Before Instruction
PC = = = = = address (HERE) 0, address (TRUE); 1, address(FALSE)
After Instruction
if FLAG<1> PC if FLAG<1> PC
DS40192C-page 42
PIC16C505
CALL Syntax: Operands: Operation: Subroutine Call [ label ] CALL k 0 k 255 (PC) + 1 Top of Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8>
1001 kkkk kkkk
CLRW Syntax: Operands: Operation:
Clear W [ label ] CLRW None 00h (W); 1Z

0000 0100 0000
Status Affected: Z Encoding: Description: Words: Cycles: Example:

W W Z = = =
Status Affected: None Encoding: Description: Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two cycle instruction. 1 2
HERE CALL THERE
The W register is cleared. Zero bit (Z) is set. 1 1

CLRW 0x5A 0x00 1

PC = PC = TOS =
Before Instruction
address (HERE) address (THERE) address (HERE + 1)
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD
0000 0000 0100
After Instruction
CLRF Syntax: Operands: Operation:
Clear f [ label ] CLRF 0 f 31 00h (f); 1Z

0000 011f ffff
Status Affected: TO, PD f Encoding: Description: The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. 1 1
CLRWDT ? 0x00 0 1 1
Status Affected: Z Encoding: Description: Words: Cycles: Example: The contents of register f are cleared and the Z bit is set. 1 1
CLRF = = = FLAG_REG 0x5A 0x00 1
Before Instruction
WDT counter =
Before Instruction
FLAG_REG
After Instruction
WDT counter WDT prescale TO PD = = = =
After Instruction
FLAG_REG Z
DS40192C-page 43
PIC16C505
COMF Syntax: Operands: Operation: Encoding: Description: Complement f [ label ] COMF 0 f 31 d [0,1] (f) (dest)
0010 01df ffff
DECFSZ f,d Syntax: Operands: Operation: Encoding: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 31 d [0,1] (f) 1 d;

0010
skip if result = 0
Status Affected: Z The contents of register f are complemented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in register f. 1 1
COMF = = = 0x13 0x13 0xEC REG1,0

11df ffff

REG1 REG1 W
Before Instruction Words: Cycles: Example: After Instruction
The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two cycle instruction. 1 1(2)
HERE DECFSZ GOTO CONTINUE = = = = = address (HERE) CNT - 1; 0, address (CONTINUE); 0, address (HERE+1) CNT, 1 LOOP
DECF Syntax: Operands: Operation: Encoding: Description:
Decrement f [ label ] DECF f,d 0 f 31 d [0,1] (f) 1 (dest)

0000 11df ffff PC CNT if CNT PC if CNT PC
Status Affected: Z Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1
DECF = = = = 0x01 0 0x00 1 CNT,
GOTO Syntax: Operands: Operation:
Unconditional Branch [ label ] GOTO k 0 k 511 k PC<8:0>; STATUS<6:5> PC<10:9>

101k kkkk kkkk

CNT Z CNT Z
Before Instruction
Status Affected: None Encoding: Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two cycle instruction. 1 2
GOTO THERE address (THERE)
After Instruction

PC =
After Instruction
DS40192C-page 44
PIC16C505
INCF Syntax: Operands: Operation: Encoding: Description: Increment f [ label ] 0 f 31 d [0,1] (f) + 1 (dest)
0010 10df ffff
INCFSZ Syntax: Operands: Operation: Encoding: Description:
Increment f, Skip if 0 [ label ] 0 f 31 d [0,1] (f) + 1 (dest), skip if result = 0

0011 11df ffff
INCF f,d
INCFSZ f,d
Status Affected: Z The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. 1 1
INCF = = = = CNT,
Status Affected: None The contents of register f are incremented. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two cycle instruction. 1 1(2)
HERE INCFSZ GOTO CONTINUE = = = = = address (HERE) CNT + 1; 0, address (CONTINUE); 0, address (HERE +1) CNT, LOOP 1

CNT Z CNT Z
1 Words: Cycles: Example:
Before Instruction
0xFF 0 0x00 1
After Instruction
Before Instruction
PC CNT if CNT PC if CNT PC
After Instruction
DS40192C-page 45
PIC16C505
IORLW Syntax: Operands: Operation: Encoding: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Operation:
kkkk kkkk 1101
MOVF Syntax: Operands:
Move f [ label ] 0 f 31 d [0,1] (f) (dest)

0010 00df ffff
MOVF f,d
Status Affected: Z The contents of the W register are ORed with the eight bit literal 'k'. The result is placed in the W register. 1 1
IORLW = = = 0x9A 0xBF 0 0x35
Status Affected: Z Encoding: Description: The contents of register 'f' are moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' = 1 is useful as a test of a file register since status flag Z is affected. 1 1
MOVF = FSR, 0

W W Z

W
After Instruction
value in FSR register
IORWF Syntax: Operands: Operation: Encoding: Description:
Inclusive OR W with f [ label ] 0 f 31 d [0,1] (W).OR. (f) (dest)

0001 00df ffff
IORWF
f,d
MOVLW Syntax: Operands: Operation: Encoding: Description:
Move Literal to W [ label ] k (W)

1100 kkkk kkkk
MOVLW k
0 k 255
Status Affected: Z Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. 1 1
IORWF 0x13 0x91 0x13 0x93 0 RESULT, 0
Status Affected: None The eight bit literal 'k' is loaded into the W register. The dont cares will assembled as 0s. 1 1
MOVLW = 0x5A 0x5A

W
After Instruction
Before Instruction
RESULT = W =
After Instruction
RESULT = W = Z =
DS40192C-page 46
PIC16C505
MOVWF Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example: Move W to f [ label ] 0 f 31 (W) (f)
0000 001f ffff
OPTION f Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example
Load OPTION Register [ label ] None (W) OPTION

0000 0000 0010
MOVWF
OPTION
Status Affected: None Move data from the W register to register f. 1 1

MOVWF = = = = TEMP_REG 0xFF 0x4F 0x4F 0x4F
Status Affected: None The content of the W register is loaded into the OPTION register. 1 1
OPTION
Before Instruction
W = 0x07 0x07
Before Instruction
TEMP_REG W
After Instruction
OPTION =
After Instruction
TEMP_REG W
RETLW Syntax: Operands: Operation:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC

1000 kkkk kkkk
NOP Syntax: Operands: Operation: Encoding: Description: Words: Cycles: Example:
No Operation [ label ] None No operation NOP
Status Affected: None Encoding: Description: The W register is loaded with the eight bit literal k. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. 1 2
CALL TABLE ;W contains ;table offset ;value. ;W now has table ;value. ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; RETLW kn ; End of table = = 0x07 value of k8

0000 0000 0000
No operation. 1 1
NOP
TABLE
Before Instruction
W W
After Instruction
DS40192C-page 47
PIC16C505
RLF Syntax: Operands: Operation: Encoding: Description: Rotate Left f through Carry [ label ] 0 f 31 d [0,1] See description below RLF f,d RRF Syntax: Operands: Operation: Encoding: Description: Rotate Right f through Carry [ label ] 0 f 31 d [0,1] See description below RRF f,d
Status Affected: C
0011 01df ffff
Status Affected: C
0011 00df ffff
The contents of register f are rotated one bit to the left through the Carry Flag. If d is 0, the result is placed in the W register. If d is 1, the result is stored back in register f. C
register f
The contents of register f are rotated one bit to the right through the Carry Flag. If d is 0, the result is placed in the W register. If d is 1, the result is placed back in register f. C
register f

REG1 C REG1 W C
1 1
RLF = = = = = REG1,0 1110 0110 0 1110 0110 1100 1100 1

REG1 C REG1 W C
1 1
RRF = = = = = REG1,0
Before Instruction
Before Instruction
1110 0110 0 1110 0110 0111 0011 0
After Instruction
After Instruction
DS40192C-page 48
PIC16C505
SLEEP Syntax: Operands: Operation: Enter SLEEP Mode [label] None 00h WDT; 0 WDT prescaler; 1 TO; 0 PD
0000 0000 0011
SUBWF Syntax: Operands: Operation: Encoding: Description:
Subtract W from f [label] SUBWF f,d 0 f 31 d [0,1] (f) (W) (dest)

0000 10df ffff
SLEEP
Status Affected: C, DC, Z Subtract (2s complement method) the W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1
SUBWF = = = = = = 3 2 ? 1 2 1 REG1, 1
Status Affected: TO, PD, RBWUF Encoding: Description: Time-out status bit (TO) is set. The power down status bit (PD) is cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP for more details. 1 1 SLEEP
Words: Cycles: Example 1:

REG1 W C REG1 W C
Before Instruction
After Instruction
; result is positive
Example 2: Before Instruction

REG1 W C REG1 W C = = = = = = 2 2 ? 0 2 1
After Instruction
; result is zero
Example 3: Before Instruction

REG1 W C REG1 W C = = = = = = 1 2 ? FF 2 0
After Instruction
; result is negative
DS40192C-page 49
PIC16C505
SWAPF Syntax: Operands: Operation: Swap Nibbles in f [ label ] SWAPF f,d 0 f 31 d [0,1] (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>)
0011 10df ffff
XORLW Syntax: Operands: Operation: Encoding: Description:
Exclusive OR literal with W [label] XORLW k 0 k 255 (W) .XOR. k (W)

1111 kkkk kkkk
Status Affected: Z The contents of the W register are XORed with the eight bit literal 'k'. The result is placed in the W register. 1 1 XORLW
= = 0xB5 0x1A
Status Affected: None Encoding: Description: The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in W register. If d is 1, the result is placed in register f. 1 1
SWAPF REG1 REG1 W = = =

W W
Words: Cycles: Example
0xAF
Before Instruction REG1, 0 After Instruction

0xA5 0xA5 0X5A
XORWF Syntax: Operands:
Exclusive OR W with f [ label ] XORWF 0 f 31 d [0,1] (W) .XOR. (f) (dest)

0001 10df ffff
f,d
TRIS Syntax: Operands: Operation: Encoding: Description:
Load TRIS Register [ label ] TRIS f=6 (W) TRIS register f

0000 0000 0fff
Operation: Encoding: Description:
Status Affected: Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. 1 1 XORWF
REG W REG W = = = = REG,1
Status Affected: None TRIS register f (f = 6 or 7) is loaded with the contents of the W register 1 1
TRIS W TRIS = = 0XA5 0XA5 PORTB
Before Instruction
0xAF 0xB5 0x1A 0xB5
After Instruction
DS40192C-page 50
PIC16C505
9.0 DEVELOPMENT SUPPORT
MPLAB allows you to: Edit your source files (either assembly or C) One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) Debug using: - source files - absolute listing file - object code The ability to use MPLAB with Microchips simulator, MPLAB-SIM, allows a consistent platform and the ability to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining.
The PICmicro microcontrollers are supported with a full range of hardware and software development tools: Integrated Development Environment - MPLAB IDE Software Assemblers/Compilers/Linkers - MPASM Assembler - MPLAB-C17 and MPLAB-C18 C Compilers - MPLINK/MPLIB Linker/Librarian Simulators - MPLAB-SIM Software Simulator Emulators - MPLAB-ICE Real-Time In-Circuit Emulator - PICMASTER/PICMASTER-CE In-Circuit Emulator - ICEPIC In-Circuit Debugger - MPLAB-ICD for PIC16F877 Device Programmers - PRO MATE II Universal Programmer - PICSTART Plus Entry-Level Prototype Programmer Low-Cost Demonstration Boards - SIMICE - PICDEM-1 - PICDEM-2 - PICDEM-3 - PICDEM-17 - SEEVAL - KEELOQ
9.2
MPASM Assembler
MPASM is a full featured universal macro assembler for all PICmicro MCUs. It can produce absolute code directly in the form of HEX files for device programmers, or it can generate relocatable objects for MPLINK. MPASM has a command line interface and a Windows shell and can be used as a standalone application on a Windows 3.x or greater system. MPASM generates relocatable object files, Intel standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file which contains source lines and generated machine code, and a COD file for MPLAB debugging. MPASM features include: MPASM and MPLINK are integrated into MPLAB projects. MPASM allows user defined macros to be created for streamlined assembly. MPASM allows conditional assembly for multi purpose source files. MPASM directives allow complete control over the assembly process.
9.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a Windowsbased application which contains: Multiple functionality - editor - simulator - programmer (sold separately) - emulator (sold separately) A full featured editor A project manager Customizable tool bar and key mapping A status bar On-line help
9.3
MPLAB-C17 and MPLAB-C18 C Compilers
The MPLAB-C17 and MPLAB-C18 Code Development Systems are complete ANSI C compilers and integrated development environments for Microchips PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
DS40192C-page 51
PIC16C505
9.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with precompiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. MPLIB manages the creation and modification of library files. MPLINK features include: MPLINK works with MPASM and MPLAB-C17 and MPLAB-C18. MPLINK allows all memory areas to be defined as sections to provide link-time flexibility. MPLIB features include: MPLIB makes linking easier because single libraries can be included instead of many smaller files. MPLIB helps keep code maintainable by grouping related modules together. MPLIB commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support new PICmicro microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft Windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. MPLAB-ICE 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems use the same processor modules and will operate across the full operating speed range of the PICmicro MCU.
9.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is a full-featured, professional quality emulator system. This flexible in-circuit emulator provides a high-quality, universal platform for emulating Microchip 8-bit PICmicro microcontrollers (MCUs). PICMASTER systems are sold worldwide, with a CE compliant model available for European Union (EU) countries.
9.8
ICEPIC
9.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code development in a PC host environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. The execution can be performed in single step, execute until break, or trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPLAB-C18 and MPASM. The Software Simulator offers the flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
ICEPIC is a low-cost in-circuit emulation solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X, and PIC16CXXX families of 8-bit one-timeprogrammable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules or daughter boards. The emulator is capable of emulating without target application circuitry being present.
9.9
MPLAB-ICD In-Circuit Debugger
9.6
MPLAB-ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of MPLAB-ICE is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, make and download, and source debugging from a single environment.
Microchips In-Circuit Debugger, MPLAB-ICD, is a powerful, low-cost run-time development tool. This tool is based on the flash PIC16F877 and can be used to develop for this and other PICmicro microcontrollers from the PIC16CXXX family. MPLAB-ICD utilizes the In-Circuit Debugging capability built into the PIC16F87X. This feature, along with Microchips In-Circuit Serial Programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in real-time. The MPLAB-ICD is also a programmer for the flash PIC16F87X family.
DS40192C-page 52
PIC16C505
9.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode the PRO MATE II can read, verify or program PICmicro devices. It can also set code-protect bits in this mode. the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.
9.14
PICDEM-2 Low-Cost PIC16CXX Demonstration Board
9.11
PICSTART Plus Entry Level Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus supports all PICmicro devices with up to 40 pins. Larger pin count devices such as the PIC16C92X, and PIC17C76X may be supported with an adapter socket. PICSTART Plus is CE compliant.
9.12
SIMICE Entry-Level Hardware Simulator
The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchips simulator MPLAB-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technologys MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchips PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry-level system development.
9.15
PICDEM-3 Low-Cost PIC16CXXX Demonstration Board
9.13
PICDEM-1 Low-Cost PICmicro Demonstration Board
The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchips microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with
The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
DS40192C-page 53
PIC16C505
9.16 PICDEM-17
The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code. In addition, PICDEM-17 supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emulator, and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
9.17
SEEVAL Evaluation and Programming System
The SEEVAL SEEPROM Designers Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system.
9.18
KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
DS40192C-page 54
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
MCP2510
TABLE 9-1:
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC12CXXX
MPLAB Integrated Development Environment
PIC16CXXX
MPLAB C17 Compiler
Software Tools
MPLAB C18 Compiler
Emulators
Programmers Debugger
Demo Boards and Eval Kits

PIC18CXX2
MPASM/MPLINK
MPLAB-ICE
**
PICMASTER/PICMASTER-CE
ICEPIC Low-Cost In-Circuit Emulator
MPLAB-ICD In-Circuit Debugger
PICSTARTPlus Low-Cost Universal Dev. Kit
**
PRO MATE II Universal Programmer
**
SIMICE
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEM-1
PICDEM-2
PICDEM-3
PICDEM-14A
PICDEM-17
KEELOQ Evaluation Kit
KEELOQ Transponder Kit
microID Programmers Kit
125 kHz microID Developers Kit
125 kHz Anticollision microID Developers Kit
13.56 MHz Anticollision microID Developers Kit
MCP2510 CAN Developers Kit
MCRFXXX
PIC16C505
DS40192C-page 55
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77 ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
PIC16C505
NOTES:
DS40192C-page 56
PIC16C505
10.0 ELECTRICAL CHARACTERISTICS - PIC16C505
Absolute Maximum Ratings
Ambient Temperature under bias ........................................................................................................... 40C to +125C Storage Temperature ............................................................................................................................. 65C to +150C Voltage on VDD with respect to VSS ....................................................................................................................0 to +7 V Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V Voltage on all other pins with respect to VSS ............................................................................... 0.6 V to (VDD + 0.6 V) Total Power Dissipation(1) ....................................................................................................................................700 mW Max. Current out of VSS pin ..................................................................................................................................150 mA Max. Current into VDD pin .....................................................................................................................................125 mA Input Clamp Current, IIK (VI < 0 or VI > VDD).................................................................................................................... 20 mA Output Clamp Current, IOK (VO < 0 or VO > VDD)............................................................................................................. 20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................25 mA Max. Output Current sourced by I/O port .............................................................................................................100 mA Max. Output Current sunk by I/O port ..................................................................................................................100 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
NOTICE:
Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
DS40192C-page 57
PIC16C505
FIGURE 10-1: PIC16C505 VOLTAGE-FREQUENCY GRAPH, 0C TA +70C
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 20 25
FIGURE 10-2: PIC16C505 VOLTAGE-FREQUENCY GRAPH, -40C TA 0C, +70C TA +125C

DS40192C-page 58
PIC16C505
FIGURE 10-3: PIC16LC505 VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
DS40192C-page 59
PIC16C505
10.1 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +125C (extended) Sym
VDD VDR VPOR SVDD IDD
DC Characteristics Power Supply Pins Parm. No.

D001 D002 D003 D004 D010
Characteristic
Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(3)
Min
3.0 0.05* 0 0 0 0
Typ(1)
Max
5.5
Units
V V V V/ms mA mA mA mA mA A A A A A A kHz MHz MHz MHz
Conditions
See Figure 10-1 through Figure 10-3 Device in SLEEP mode See section on Power-on Reset for details See section on Power-on Reset for details FOSC = 4MHz, VDD = 5.5V, WDT disabled (Note 4)* FOSC = 4MHz, VDD = 3.0V, WDT disabled (Note 4) FOSC = 10MHz, VDD = 3.0V, WDT disabled (Note 6) FOSC = 20MHz, VDD = 4.5V, WDT disabled FOSC = 20MHz, VDD = 5.5V, WDT disabled* FOSC = 32kHz, VDD = 3.0V, WDT disabled (Note 6) VDD = 3.0V (Note 6) VDD = 4.5V* (Note 6) VDD = 5.5V, Industrial VDD = 5.5V, Extended Temp. VDD = 3.0V (Note 6) All temperatures All temperatures All temperatures All temperatures
1.5* VSS 0.8 0.6 3 4 4.5 19 0.25 0.4 3 5 2.2
1.4 1.0 7 12 16 27 4 5.5 8 14 5 200 4 4 20
D020
Power-Down Current (5)
IPD
D022 1A
WDT Current(5) LP Oscillator Operating Frequency RC Oscillator Operating Frequency XT Oscillator Operating Frequency HS Oscillator Operating Frequency
IWDT Fosc
* These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 6: Commercial temperature range only.
DS40192C-page 60
PIC16C505
10.2 DC CHARACTERISTICS:
DC Characteristics Power Supply Pins Parm. No.
D001 D002 D003 D004 D010
PIC16LC505-04 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) 40C TA +85C (industrial) Sym
VDD VDR VPOR SVDD IDD
Characteristic
Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current(3)
Min
2.5 0.05*
Typ(1)
1.5* VSS 0.8 0.4 15 0.25 0.25 3 2.0
Max
5.5 1.4 0.8 23 3 4 8 4 200 4 4 4
Units
V V V V/ms mA mA A A A A A kHz MHz MHz MHz
Conditions
See Figure 10-1 through Figure 10-3 Device in SLEEP mode See section on Power-on Reset for details See section on Power-on Reset for details FOSC = 4MHz, VDD = 5.5V, WDT disabled (Note 4)* FOSC = 4MHz, VDD = 2.5V, WDT disabled (Note 4) FOSC = 32kHz, VDD = 2.5V, WDT disabled (Note 6) VDD = 2.5V (Note 6) VDD = 3.0V * (Note 6) VDD = 5.5V Industrial VDD = 2.5V (Note 6) All temperatures All temperatures All temperatures All temperatures
D020
Power-Down Current (5)
IPD
0 0 0 0
D022 1A
WDT Current(5) LP Oscillator Operating Frequency RC Oscillator Operating Frequency XT Oscillator Operating Frequency HS Oscillator Operating Frequency
IWDT FOSC
* These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 6: Commercial temperature range only.
DS40192C-page 61
PIC16C505
10.3 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended) PIC16LC505-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.3. Sym Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Characteristic Input Low Voltage I/O ports with TTL buffer
VIL VSS VSS VSS VSS VSS VIH

2.0 0.25VDD + 0.8VDD 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250
D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, RC5/T0CKI (in EXTRC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 D060 with Schmitt Trigger buffer MCLR, RC5/T0CKI OSC1 (XT, HS and LP) OSC1 (in EXTRC mode) GPIO weak pull-up current (Note 4) Input Leakage Current (Notes 2, 3) I/O ports
0.8V 0.15VDD 0.2VDD 0.2VDD 0.3VDD
V V V V V
For all 4.5 VDD 5.5V otherwise
Note1
VDD VDD VDD VDD VDD VDD 400 1 30 5 5
V V
4.5 VDD 5.5V
IPUR IIL
otherwise V For entire VDD range V V Note1 V A VDD = 5V, VPIN = VSS A Vss VPIN VDD, Pin at hi-impedance A Vss VPIN VDD A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration V V V V IOL = 8.5 mA, VDD = 4.5V, 40C to +85C IOL = 7.0 mA, VDD = 4.5V, 40C to +125C IOL = 1.6 mA, VDD = 4.5V, 40C to +85C IOL = 1.2 mA, VDD = 4.5V, 40C to +125C
D061 GP3/MCLRI (Note 5) D061A GP3/MCLRI (Note 6) D063 OSC1 Output Low Voltage I/O ports/CLKOUT
D080 D080A D083 D083A

Note 1: 2: 3: 4: 5: 6:
VOL
0.6 0.6 0.6 0.6
OSC2
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Does not include GP3. For GP3 see parameters D061 and D061A. This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up enabled. This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic.
DS40192C-page 62
PIC16C505
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating temperature 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +125C (extended) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.3. Sym Min Typ Max Units Conditions
Param No. D090 D090A D092 D092A OSC2
Characteristic Output High Voltage I/O ports/CLKOUT (Note 3)
VOH
VDD - 0.7 VDD - 0.7 VDD - 0.7 VDD - 0.7
V V V V
IOH = -3.0 mA, VDD = 4.5V, 40C to +85C IOH = -2.5 mA, VDD = 4.5V, 40C to +125C IOH = -1.3 mA, VDD = 4.5V, 40C to +85C IOH = -1.0 mA, VDD = 4.5V, 40C to +125C
D100
Capacitive Loading Specs on Output Pins OSC2 pin
COSC2
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1.
D101
Note 1: 2: 3: 4: 5: 6:
All I/O pins and OSC2
CIO
50
pF
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. Does not include GP3. For GP3 see parameters D061 and D061A. This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up enabled. This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic.
DS40192C-page 63
PIC16C505
TABLE 10-1:
VDD (Volts) 2.5
PULL-UP RESISTOR RANGES - PIC16C505

Temperature (C) 40 25 85 125 40 25 85 125 40 25 85 125 40 25 85 125 Min RB0/RB1/RB4 38K 42K 42K 50K 15K 18K 19K 22K RB3 285K 343K 368K 431K 247K 288K 306K 351K 42K 48K 49K 55K 17K 20K 22K 24K 346K 414K 457K 504K 292K 341K 371K 407K 63K 63K 63K 63K 20K 23K 25K 28K 417K 532K 532K 593K 360K 437K 448K 500K W W W W W W W W W W W W W W W W Typ Max Units
5.5
2.5
5.5
These parameters are characterized but not tested.
DS40192C-page 64
PIC16C505
10.4 Timing Parameter Symbology and Load Conditions - PIC16C505
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F pp 2 ck cy drt io S F H I L Fall High Invalid (Hi-impedance) Low P R V Z Period Rise Valid Hi-impedance to CLKOUT cycle time device reset timer I/O port mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer Frequency T Time Lowercase subscripts (pp) and their meanings:
Uppercase letters and their meanings:
FIGURE 10-4: LOAD CONDITIONS - PIC16C505
Pin CL VSS
CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
DS40192C-page 65
PIC16C505
10.5 Timing Diagrams and Specifications FIGURE 10-5: EXTERNAL CLOCK TIMING - PIC16C505
Q4 OSC1 1 2 3 3 4 4 Q1 Q2 Q3 Q4 Q1
TABLE 10-2:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505

Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), 40C TA +85C (industrial), 40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Characteristic
External CLKIN Frequency(2)
AC Characteristics
Parameter No.
1A
Sym
FOSC
Min
DC DC DC DC
Typ(1)

Max
4 4 20 200 4 4 4 200 10,000 250 250 DC
Units
Conditions
MHz XT osc mode MHz HS osc mode (PIC16C505-04) MHz HS osc mode (PIC16C505-20) kHz LP osc mode
Oscillator Frequency
(2)
DC 0.1 4 DC
MHz EXTRC osc mode MHz XT osc mode MHz HS osc mode (PIC16C505-04) kHz ns ns s ns ns ns ns s ns ns LP osc mode XT osc mode HS osc mode (PIC16C505-20) LP osc mode EXTRC osc mode XT osc mode HS ocs mode (PIC16C505-04) HS ocs mode (PIC16C505-20) LP osc mode
TOSC
External CLKIN
Period(2)
250 50
Oscillator Period
(2)
250 250 250 50 5
4/FOSC
TCY
Instruction Cycle Time
200
* These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
DS40192C-page 66
PIC16C505
TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 (CONTINUED)
Clock in (OSC1) Low or High Time
AC Characteristics
Parameter No.
3
Sym
TosL, TosH
Min
50* 2* 10
Typ(1)

Max

Units
ns s ns
Conditions
XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
TosR, TosF
Clock in (OSC1) Rise or Fall Time
25* 50* 15
ns ns ns
* These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
TABLE 10-3:
CALIBRATED INTERNAL RC FREQUENCIES - PIC16C505

Internal Calibrated RC Frequency Internal Calibrated RC Frequency
AC Characteristics
Parameter No.
Sym
Min*
3.65 3.55
Typ(1)
4.00 4.00
Max* Units
4.28 4.31
Conditions
MHz VDD = 5.0V MHz VDD = 2.5V
* These parameters are characterized but not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS40192C-page 67
PIC16C505
FIGURE 10-6: I/O TIMING - PIC16C505
Q4 OSC1 Q1 Q2 Q3
I/O Pin (input)

17 19 18 New Value 20, 21
I/O Pin (output)
Old Value
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-4:
TIMING REQUIREMENTS - PIC16C505

Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Characteristic OSC1 (Q1 cycle) to Port out valid(2,3) Min TBD TBD Typ(1) 10 10 Max 100* 25** 25** Units ns ns ns ns ns
AC Characteristics
Parameter No. 17 18 19 20 21
Sym TosH2ioV TosH2ioI TioV2osH TioR TioF
OSC1 (Q2 cycle) to Port input invalid (I/O in hold time)(2) Port input valid to OSC1 (I/O in setup time) Port output rise time(3) Port output fall time(3)
* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 10-4 for loading conditions.
DS40192C-page 68
PIC16C505
FIGURE 10-7: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505
VDD MCLR 30 Internal POR 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 I/O pin (Note 1) Note 1: 2: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. Runs in MCLR or WDT reset only in XT, LP and HS modes. 34
32
32
TABLE 10-5:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505
AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Parameter No.
30 31
Sym TmcL Twdt TDRT TioZ
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Device Reset Timer Period(2) I/O Hi-impedance from MCLR Low
Min 2000* 9* 9*
Typ(1) 18* 18*
Max 30* 30* 2000*
Units ns ms ms ns
Conditions VDD = 5.0 V VDD = 5.0 V (Commercial) VDD = 5.0 V (Commercial)
32 34
TABLE 10-6:
DRT (DEVICE RESET TIMER PERIOD - PIC16C505

POR Reset 18 ms (typical) 18 ms (typical) Subsequent Resets 300 s (typical) 18 ms (typical)
Oscillator Configuration IntRC & ExtRC XT, HS & LP
DS40192C-page 69
PIC16C505
FIGURE 10-8: TIMER0 CLOCK TIMINGS - PIC16C505
T0CKI 40 41
42
TABLE 10-7:
TIMER0 CLOCK REQUIREMENTS - PIC16C505

Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) 40C TA +85C (industrial) 40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1. Min
0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N
AC Characteristics
Parm Sym No.

40 Tt0H
Characteristic
T0CKI High Pulse Width No Prescaler With Prescaler
Typ(1) Max Units

ns ns ns ns ns
Conditions
41
Tt0L
T0CKI Low Pulse Width
No Prescaler With Prescaler
42
Tt0P
T0CKI Period
Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
DS40192C-page 70
PIC16C505
11.0 DC AND AC CHARACTERISTICS PIC16C505
FIGURE 11-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 2.5V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
4.50 4.40 4.30 4.20
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. Typical represents the mean of the distribution while max or min represents (mean + 3) and (mean 3) respectively, where is standard deviation.
Max.
Frequency (MHz)
4.10 4.00
FIGURE 11-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V) (INTERNAL RC IS CALIBRATED TO 25C, 5.0V)
4.50 4.40 4.30 4.20
3.90
3.80 3.70
3.60 3.50 -40
Min.
0 25 85 125
Max.
Temperature (Deg.C)
Frequency (MHz)
4.10 4.00
3.90
3.80 3.70
Min.
3.60 3.50 -40
25
85
125
Temperature (Deg.C)
DS40192C-page 71
PIC16C505
TABLE 11-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25C
Frequency 4 MHz 4 MHz 4 MHz 32 kHz 20 MHz VDD = 3.0V(1) 240 A 320 A 300 A 19 A N/A
(2)
Oscillator External RC Internal RC XT LP HS

Note 1: 2:
VDD = 5.5V 800 A(2) 800 A 800 A 50 A 4.5 mA
LP oscillator based on VDD = 2.5V Does not include current through external R&C.
FIGURE 11-3: WDT TIMER TIME-OUT PERIOD vs. VDD

55
FIGURE 11-4: SHORT DRT PERIOD VS. VDD

950 850
50 750 45 650 WDT period (S) WDT period (s) 40 35

Max +125C
550
Max +125C
450 350
Max +85C
30
Max +85C
25 250 20
Typ +25C
Typ +25C
MIn 40C
150 15
MIn 40C
0 0 2.5 3.5 4.5 5.5 6.5 VDD (Volts)
10 0 2.5 3.5 4.5 5.5 6.5 VDD (Volts)
DS40192C-page 72
PIC16C505
FIGURE 11-5: IOH vs. VOH, VDD = 2.5 V
0
FIGURE 11-7: IOL vs. VOL, VDD = 2.5 V

25
-1
20
-2
Max 40C
IOH (mA)
-3
15 IOL (mA)
Typ +25C
-4
125C Min +
10
Min +85C
-5
M
5C in +8
-6
Typ +25C
C Max 40
Min +125C
-7 500m
1.0
1.5
2.0
2.5
0 0 250.0m 500.0m 1.0 VOL (Volts)
VOH (Volts)
FIGURE 11-6: IOH vs. VOH, VDD = 5.5 V FIGURE 11-8: IOL vs. VOL, VDD = 5.5 V
0
50
-5
Max 40C
40
-10
IOH (mA)
30 IOL (mA)
-15
C 25 +1
Typ +25C
M
M
in
+2 5
+8 5 C
-20
in
20
Min +85C
Ty p
-25
4 0 C
Min +125C
-30 3.5 4.0 4.5 5.0 5.5
10
ax
VOH (Volts)
0 250.0m 500.0m 750.0m 1.0 VOL (Volts)
DS40192C-page 73
PIC16C505
NOTES:
DS40192C-page 74
PIC16C505
11.0
11.1
PACKAGING INFORMATION
Package Marking Information 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX AABBCDE
Example 16C505-04I/P BUILT 4 SPEED 9904SAZ
14-Lead SOIC (150 mil) XXXXXXXXXX AABBCDE
Example 16C505-04I 9904SAZ
14-Lead Windowed Ceramic (300 mil) XXX
Example JW
XXXXXX
16C505
Legend: MM...M XX...X AA BB C
D E Note:
Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week 01) Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5 Line S = 6 Line H = 8 Line Mask revision number Assembly code of the plant or country of origin in which part was assembled
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS40192C-page 75
PIC16C505
14-Lead Plastic Dual In-line (P) 300 mil (PDIP)
E1
2 n 1
E A A2
c eB A1 B1 B p
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010 (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
DS40192C-page 76
PIC16C505
14-Lead Plastic Small Outline (SL) Narrow, 150 mil (SOIC)
E E1
2 B n 1 h 45 c A A2
L A1
Number of Pins Pitch Overall Height A .053 .069 Molded Package Thickness A2 .052 .061 Standoff A1 .004 .010 Overall Width E .228 .244 Molded Package Width E1 .150 .157 Overall Length D .337 .347 Chamfer Distance h .010 .020 Foot Length L .016 .050 Foot Angle 0 8 c Lead Thickness .008 .010 Lead Width B .014 .020 Mold Draft Angle Top 0 15 Mold Draft Angle Bottom 0 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010 (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065
Units Dimension Limits n p
MIN
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
MIN
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15
DS40192C-page 77
PIC16C505
14-Lead Ceramic Side Brazed Dual In-line with Window (JW) 300 mil
E1
2 n U 1
A2
L A1 c eB Units Dimension Limits n p A A2 A1 E1 D L c B1 B eB W T U B1 B INCHES* NOM 14 .100 .142 .162 .100 .120 .025 .035 .280 .290 .693 .700 .130 .140 .008 .010 .052 .054 .016 .018 .296 .310 .161 .166 .440 .450 .260 .270 p MILLIMETERS NOM 14 2.54 3.61 4.11 2.54 3.05 0.64 0.89 7.11 7.37 17.60 17.78 3.30 3.56 0.20 0.25 1.32 1.37 0.41 0.46 7.52 7.87 4.09 4.22 11.18 11.43 6.60 6.86
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane Top of Body to Seating Plane Standoff Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Window Diameter Lid Length Lid Width *Controlling Parameter JEDEC Equivalent: MS-015 Drawing No. C04-107
.182 .140 .045 .300 .707 .150 .012 .056 .020 .324 .171 .460 .280
4.62 3.56 1.14 7.62 17.96 3.81 0.30 1.42 0.51 8.23 4.34 11.68 7.11
DS40192C-page 78
PIC16C505
INDEX A
ALU ....................................................................................... 7 Applications........................................................................... 3 Architectural Overview .......................................................... 7 Assembler MPASM Assembler..................................................... 51 Oscillator Types HS............................................................................... 28 LP ............................................................................... 28 RC .............................................................................. 28 XT ............................................................................... 28
P
Package Marking Information ............................................. 75 Packaging Information ........................................................ 75 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 53 PICDEM-2 Low-Cost PIC16CXX Demo Board................... 53 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 53 PICSTART Plus Entry Level Development System ......... 53 POR Device Reset Timer (DRT) ................................... 27, 34 PD............................................................................... 36 Power-On Reset (POR) .............................................. 27 TO............................................................................... 36 PORTB ............................................................................... 19 Power-Down Mode ............................................................. 37 Prescaler ............................................................................ 26 PRO MATE II Universal Programmer .............................. 53 Program Counter ................................................................ 17
B
Block Diagram On-Chip Reset Circuit ................................................. 33 Timer0......................................................................... 23 TMR0/WDT Prescaler................................................. 26 Watchdog Timer.......................................................... 35 Brown-Out Protection Circuit .............................................. 36
C
CAL0 bit .............................................................................. 16 CAL1 bit .............................................................................. 16 CAL2 bit .............................................................................. 16 CAL3 bit .............................................................................. 16 CALFST bit ......................................................................... 16 CALSLW bit ........................................................................ 16 Carry ..................................................................................... 7 Clocking Scheme ................................................................ 10 Code Protection ............................................................ 27, 37 Configuration Bits................................................................ 27 Configuration Word ............................................................. 27
Q
Q cycles .............................................................................. 10
R
RC Oscillator....................................................................... 29 Read Modify Write .............................................................. 20 Register File Map................................................................ 12 Registers Special Function ......................................................... 13 Reset .................................................................................. 27 Reset on Brown-Out ........................................................... 36
D
DC and AC Characteristics ................................................. 71 Development Support ......................................................... 51 Device Varieties .................................................................... 5 Digit Carry ............................................................................. 7
E
Errata .................................................................................... 2
S
SEEVAL Evaluation and Programming System .............. 54 SLEEP .......................................................................... 27, 37 Software Simulator (MPLAB-SIM) ...................................... 52 Special Features of the CPU .............................................. 27 Special Function Registers ................................................. 13 Stack................................................................................... 17 STATUS ............................................................................... 7 STATUS Register ............................................................... 14
F
Family of Devices PIC16C505 ................................................................... 4 FSR ..................................................................................... 18
I
I/O Interfacing ..................................................................... 19 I/O Ports .............................................................................. 19 I/O Programming Considerations........................................ 20 ID Locations .................................................................. 27, 37 INDF.................................................................................... 18 Indirect Data Addressing..................................................... 18 Instruction Cycle ................................................................. 10 Instruction Flow/Pipelining .................................................. 10 Instruction Set Summary..................................................... 40
T
Timer0 Switching Prescaler Assignment ................................ 26 Timer0 ........................................................................ 23 Timer0 (TMR0) Module .............................................. 23 TMR0 with External Clock .......................................... 25 Timing Diagrams and Specifications .................................. 66 Timing Parameter Symbology and Load Conditions .......... 65 TRIS Registers ................................................................... 19
K
KeeLoq Evaluation and Programming Tools.................... 54
L
Loading of PC ..................................................................... 17
W
Wake-up from SLEEP......................................................... 37 Watchdog Timer (WDT)................................................ 27, 34 Period ......................................................................... 35 Programming Considerations ..................................... 35 WWW, On-Line Support ....................................................... 2
M
Memory Organization.......................................................... 11 Data Memory .............................................................. 12 Program Memory ........................................................ 11 MPLAB Integrated Development Environment Software .... 51
Z
Zero bit ................................................................................. 7
O
OPTION Register ................................................................ 15 OSC selection ..................................................................... 27 OSCCAL Register ............................................................... 16 Oscillator Configurations ..................................................... 28
DS40192B-page 79
PIC16C505
NOTES:
DS40192B-page 80
PIC16C505
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchips development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-786-7302 for the rest of the world.
981103
Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, Users Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: Latest Microchip Press Releases Technical Support Section with Frequently Asked Questions Design Tips Device Errata Job Postings Microchip Consultant Program Member Listing Links to other useful web sites related to Microchip Products Conferences for products, Development Systems, technical information and more Listing of seminars and events
Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies.
DS40192C-page 81
PIC16C505
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C505 Questions: 1. What are the best features of this document? Y N Literature Number: DS40192C FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40192C-page 82
PIC16C505
PIC16C505 Product Identification System
PART NO. -XX X /XX XXX Pattern: Package: Special Requirements SL P JW I E 04 20 = 150 mil SOIC = 300 mil PDIP = 300 mil Windowed Ceramic Side Brazed = 0C to +70C = -40C to +85C = -40C to +125C = 4 MHz (XT, INTRC, EXTRC OSC) = 20 MHz (HS OSC)
c)
Examples
a) PIC16C505-04/P Commercial Temp., PDIP Package, 4 MHz, normal VDD limits PIC16C505-04I/SL Industrial Temp., SOIC package, 4 MHz, normal VDD limits PIC16C505-04I/P Industrial Temp., PDIP package, 4 MHz, normal VDD limits
b)
Temperature Range: Frequency Range: Device
PIC16C505 PIC16LC505 PIC16C505T (Tape & reel for SOIC only) PIC16LC505T (Tape & reel for SOIC only)
Please contact your local sales office for exact ordering procedures.
Sales and Support

Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS40192C-page 83
Note the following details of the code protection feature on PICmicro MCUs. The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Companys quality system processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001 certified.
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456
China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599
Taiwan
Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Microchip Technology SARL Parc dActivite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
New York
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
Germany
Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Hong Kong
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Italy
Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, OShaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02

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PIC16C505

14-Pin, 8-Bit CMOS Microcontroller

Special Microcontroller Features:

High-Performance RISC CPU:

VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/VPP RC5/T0CKI RC4 RC3

VSS RB0 RB1 RB2 RC0 RC1 RC2

1999 Microchip Technology Inc.

To Our Valued Customers

New Customer Notification System

Corrections to this Data Sheet

1999 Microchip Technology Inc.

1999 Microchip Technology Inc.

1999 Microchip Technology Inc.

Quick-Turnaround-Production (QTP) Devices

Serialized Quick-Turnaround Production (SQTPSM) Devices

One-Time-Programmable (OTP) Devices

1999 Microchip Technology Inc.

1999 Microchip Technology Inc.

1999 Microchip Technology Inc.

RAM 72 bytes File Registers RAM Addr 9

Instruction reg Direct Addr 5

Addr MUX Indirect 5-7 Addr FSR reg 8 3 STATUS reg

MCLR VDD, VSS

1999 Microchip Technology Inc.

PIC16C505 PINOUT DESCRIPTION

RC0 RC1 RC2 RC3 RC4 RC5/T0CKI VDD VSS

I/O I/O I/O I/O I/O I/O P P

1999 Microchip Technology Inc.

Fetch INST (PC+1) Execute INST (PC)

Fetch INST (PC+2) Execute INST (PC+1)

INSTRUCTION PIPELINE FLOW

1999 Microchip Technology Inc.

PROGRAM MEMORY MAP AND STACK FOR THE PIC16C505

Program Memory Organization

Reset Vector (note 1)

User Memory Space

On-chip Program Memory

1999 Microchip Technology Inc.

PIC16C505 REGISTER FILE MAP

2Fh 30h General Purpose Registers

4Fh 50h General Purpose Registers 5Fh Bank 2

6Fh 70h General Purpose Registers 7Fh Bank 3

1999 Microchip Technology Inc.

SPECIAL FUNCTION REGISTER (SFR) SUMMARY

0001 1xxx 110x xxxx

1000 00---11 1111 --11 1111

1111 1111 --xx xxxx --xx xxxx

1999 Microchip Technology Inc.

STATUS REGISTER (ADDRESS:03h)

1999 Microchip Technology Inc.

1999 Microchip Technology Inc.

OSCCAL REGISTER (ADDRESS 05h) PIC16C505

bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented read as 0

1999 Microchip Technology Inc.

LOADING OF PC BRANCH INSTRUCTIONS PIC16C505

Instruction Word PA0 7 0

CALL or Modify PCL Instruction

Instruction Word Reset to 0 PA0 7 0

1999 Microchip Technology Inc.