Lab 08
Lab 08
Lab 08
Introduction
In this lab you will build the MIPS single-cycle processor using Verilog. You will simulate a simple program running on your single-cycle processor. By the end of this lab, you should thoroughly understand the internal operation of the MIPS single-cycle processor. Please read and follow the instructions in this lab carefully. In the past, many students have lost points for silly errors like not printing all the signals requested. The lab will involve several steps. First, you will copy most of the Verilog code for the single-cycle processor from the supplementary lab material on the textbook website in the Labs/Lab08 directory. You will add your ALU Verilog module (from Lab 5) to the project. You will then add the instruction memory to the processor and extend the capabilities of the processor. Before starting this lab, you should be very familiar with the single-cycle implementation of the MIPS processor described in Section 7.3 of your text, Digital Design and Computer Architecture. We give the single-cycle processor schematic from the text in Figure 1 for your convenience. This version of the MIPS single-cycle processor can execute the following instructions: add, sub, and, or, slt, lw, sw, beq, addi, and j. Our model of the single-cycle MIPS processor divides the machine into two major units: the control and the datapath. In this lab, we give you the control unit in Verilog. You will complete the datapath and extend both the datapath and control units for additional instructions. Each unit is constructed from various functional blocks. For example, as shown in Figure 1, the datapath contains the 32-bit ALU that you designed in Lab 5, the register file, the sign extension logic, and five multiplexers. One mux each selects the register to write, the data to write, and the input to the second source of the ALU. Two multiplexers are used to select the next PC.
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Jump
31:26 5:0
MemtoReg Control MemWrite Unit Branch ALUControl2:0 Op Funct ALUSrc RegDst RegWrite
PCSrc
CLK A1 A2 A3 WD3
20:16
CLK WE3 RD1 RD2 Register File 0 WriteReg4:0 1 SrcA Zero ALUResult A WE RD Data Memory WD ReadData 0 Result 1
Instruction Memory
20:16
0 SrcB 1
WriteData
PCJump PCPlus4 4
27:0 31:28
15:11
ImmExt
15:0
Sign Extend
<<2 PCBranch
25:0
<<2
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20020005 20070003 2003000c 00e22025 00642824 00a42820 10a70008 0064302a 10c00001 2005000a 00e2302a 00c53820 00e23822 0800000f 8c070000 ac470047 Figure 2. Machine code MIPS program The machine code in Figure 2 corresponds to the assembly program given in Figure 3.
# test1.asm # 23 October 2005 David Harris David_Harris@hmc.edu # # Test MIPS instructions. #Assembly Code # Machine Code
main:
around:
end:
addi addi addi or and add beq slt beq addi slt add sub j lw sw
$2, $7, $3, $4, $5, $5, $5, $6, $6, $5, $6, $7, $7, end $7, $7,
$0, $0, $0, $7, $3, $5, $7, $3, $0, $0, $7, $6, $7,
0($0) 71($2)
# # # # # # # # # # # # # # # #
20020005 20070003 2003000c 00e22025 00642824 00a42820 10a70008 0064302a 10c00001 2005000a 00e2302a 00c53820 00e23822 0800000f 8c070000 ac470047
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This code can be found in the supplementary lab material provided on the textbook website under the Labs/Lab08 directory.
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Figure 4. Memory Editor Interface Click on Add Block to enter the Memory Block Name. Name it imem. Enter the Depth as 64 and the Data Width as 32. Make sure the Radix for the Data is 16 (i.e. hexadecimal). Under Configure COE File Parameter Names, choose MEMORY_INITIALIZATION_RADIX for Radix and MEMORY_INITIALIZATION_VECTOR for Data. Now enter the instruction codes (given in Figure 2) into the contents of the ROM. For example instruction 20020005 is entered at Address 00 (Indicated as row 0, offset +0 in the window) in the ROM, instruction 20070003 is at Address 01, and so forth. The first three entries in the ROM are shown in Figure 4. When you finish entering all the machine instructions at the corresponding addresses, save your memory configuration by choosing File Save Memory Definition. Now choose File Generate to generate a .coe file that can be read by CoreGen. Click on the top option, COE File(s), and click OK. It should now inform you that defintion1_imem.coe has been generated. This file can be imported later to set up the complete 64 word 32 bit instruction ROM. Now close the Memory Editor. You can now exit from the Memory Editor window by choosing File Exit. The main Core Generator window should still be open. Click on the Generated IP tab in the main window. Now right click on imem and select: Recustomize Under Current Project Settings. Click Next twice. In the last window, select Load Coefficients, and click on Load File. This will bring up a window that will allow you to browse for your .coe file that holds the definition of your ROM contents. Highlight the file and click Open.
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Now complete the setting of the ROM by clicking the Generate button. By doing so, the ROM imem is created with the stored instructions you entered and a symbol with the same name will also be ready to use in Verilog files. When you view the imem module in your Processes in Source window, there should now no longer be a question mark next to it. If there is still a question mark, you need fix your errors. You can edit your core generated module by double-clicking on it. You can also look at the equivalent Verilog code by choosing CoreGen View Verilog Functional Model.
2. Synthesis
Synthesize the highest level module, top, and view the RTL schematic. If it does not look as you expected, fix the errors and resynthesize. Notice that the only necessary inputs to the highest level module are clk and reset. The other signals are there for verification purposes only.
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During debug, youll likely want to view several internal signals. However, on the final waveform that you turn in, show ONLY the following signals in this order: clk, reset, pc, instr, aluout, writedata, memwrite, and readdata. All the values need to be output in hexadecimal and must be readable to get full credit. After you have fixed any bugs, print out your final waveform.
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Figure 5. MIPS assembly program: test2.asm test2.asm can be found in the supplementary lab material on the textbook website under the Labs/Lab08 directory. Again, for debugging, you might find it useful to make other signals from sub-modules visible in the higher-level module. However, in the final waveform that you turn in, only include the following signals in this order: clk, reset, pc, instr, aluout, writedata, memwrite, and readdata, in that order. Make sure all your waveforms are readable and show values in hexadecimal.
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What to Turn In
Please turn in each of the following items, clearly labeled and in the following order: 1. Please indicate how many hours you spent on this lab. This will not affect your grade, but will be helpful for calibrating the workload for next semesters labs. 2. Your commented test1.asm and test2.asm, including machine code. 3. A printout of your Verilog code and RTL schematic for your modified MIPS computer (including ori and bne functionality): top.v Any Verilog files you modified in part 3. Highlight any changes you made.
4. A copy of your hand-drawn MIPS schematic from part 3 that adds the ori and bne instructions. 5. Simulation waveforms of: top.v for test1.asm top.v for test2.asm (with your modified single-cycle MIPS processor)
The simulation waveforms should give the signal values in hexadecimal format and should be in the following order: clk, reset, pc, instr, aluout, writedata, memwrite, and readdata. Do not display any other signals in the waveform. Be sure the waveforms match your expectations. Check that the waveforms are zoomed out enough that the grader can read your bus values. Unreadable waveforms will receive no credit. Use several pages as necessary. 6. A completed version of Table 1.
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Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
reset 1 0 0 0
Pc 00 04 08 0C
Instr addi $2,$0,5 20020005 addi $7,$0,3 20070003 addi $3,$0,0xc 2003000c
branch 0 0 0
srca 0 0 0
srcb 5 3 12
Aluresult 5 3 12
zero 0 0 0
pcsrc 0 0 0
write data 0
Mem write 0
read data 0 0
Table 1. First fourteen cycles of executing assembly program test1.asm Remember, branch is asserted (1) when the instruction is a branch (beq) instruction. aluout is the output of the ALU at each cycle. zero is high (1) only if aluout is 0. pcsrc, a signal in the datapath, is low (0) when nextpc should be pc+4. pcsrc is high (1) when the nextpc should be the branch target address (pcbranch). You will notice that all of these signals are not available from the top-level module (mips). For debugging, you might want to be able to look at these signals and others.
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