White Paper

Technical Considerations for Implementing USB 3.0 on SoCs

May 2012

Authors
Gervais Fong Senior Product Marketing Manager, Synopsys, Inc. Eric Huang Senior Product Marketing Manager, Synopsys, Inc.

Introduction
The Universal Serial Bus (USB) protocol has been the standard way to connect computers to external devices for nearly two decades. The protocol continues to evolve to support the growing demands of consumer devices. With its simplicity of use, USB is the number one choice of connectivity protocols in the consumer world. Over the last decade, USB 2.0 successfully catered to diverse applications requiring a throughput up to 480 Mbps. More recently, higher performance consumer devicesHD video cameras, multi-megapixel digital cameras, terabit mass storage drives, and HD movies on flash drivesrequire higher throughput. These higher throughput demands, of gigabits per second, drove the definition of the next-generation USB protocol: USB 3.0, or SuperSpeed USB. USB 3.0, with 10X the throughput of USB 2.0 and with complete backward compatibility, will support the next decade of consumer electronics. USB 3.0 early adoption began in 2010. Now, key USB software and systems providers are shipping high volumes of products with USB 3.0. The ecosystem around USB 3.0 is in place. USB 3.0 is no longer just for cutting-edge applications. The time has come for all system-on-chip (SoC) designers to implement USB 3.0. This paper highlights the specific features and enhancements in the USB 3.0 protocol. These enhancements come with technical complexities, and this paper outlines complexities and the resulting design challenges. It shows how a USB 3.0 cores reconfigurability can broaden a designs potential applications and reuse. Finally, it talks about USB 3.0 selection and implementation considerations, from architecture, prototyping, and software, to testing and certification.

USB 3.0 Market Drivers

Consumer entertainment is the impetus behind developing the USB 3.0 standard. USB 2.0 offers throughput up to 480 Mbps, but that is not fast enough for users of high-performance consumer devices (such as HD webcams, Blu-ray and HD DVD players, and multi-megapixel digital cameras). For instance, a typical 27 GB movie takes about 14 minutes to load over a USB 2.0 connection. Upgrading to USB 3.0 offers almost 10X faster performance: the same 27 GB movie takes only 70 seconds over a USB 3.0 connection. In addition, the growing use of high-capacity solid-state drives is pushing PC manufacturers to incorporate USB 3.0 connectivity. With USB 3.0, PCs can transfer data at a rate comparable to internal storage. High capacity flash drives supporting USB 3.0 are already shipping in volume. These demand generators for USB 3.0 are driving implementation in the traditional PC and mobile PC products. Mobile multimedia devices, such as smart phones and tablets, will catch up; USB 3.0 adoption in mobile phones and tables started in 2012, and in 2015 alone, over 2 billion USB 3.0 devices will be shipped[1].

This fast-paced adoption of the USB 3.0 protocol is driving rapid growth of the USB 3.0 ecosystem. Early shipments of host controller discrete chips supporting USB 3.0 started over 3 years ago[2], and NEC/Renesas began early implementation of a host controller discrete chips supporting USB 3.0 in 2009[3]. These appeared on PC motherboards in late 2010 and laptops in early 2011, and mass production is ramping up. On the processor side, AMD implemented USB 3.0 in its Fusion APU, and its shipments started in Q2 2011[4]. One of the worlds largest makers of PC CPUs and chipsets began shipping USB 3.0 fully integrated into its Series 7 Ivy Bridge chipsets in April 2012. This makes USB 3.0 effectively free to laptop, ultrabook, and PC buyers this year[5]. The hardware ecosystem is growing, and the software ecosystem is also expanding. While everyone shipping USB 3.0 host includes Windows drivers for their PCs, expect widespread support from Microsoft and Linux in 2012. In 2011, Microsoft announced and demonstrated that it would include native USB 3.0 support in Windows 8. Microsoft demonstrated USB 3.0 at their Build conference in September[6]. At present, to support USB 3.0, many use third party vendors such as MCCI to develop the USB 3.0 driver stack. USB 3.0 peripheral manufacturers supply a USB 3.0 driver stack to run with Windows 7 and other operating systems. Third party and open source drivers for Linux also support USB 3.0. Apples Mac is expected to follow soon[7]. With PC chipset suppliers and software vendors shipping products, and mobile multimedia content creating immediate consumer demand, SoC designs starting today must support USB 3.0. It is critical to incorporate USB 3.0 into consumer products that will hit the market in the next 1-2 years.

Key Features of the USB 3.0 Protocol

Two primary enhancements defined in the USB 3.0 protocol address the PC and mobile market demands for higher performance and energy efficiencyadding a second physical datapath and replacing continuous polling with an interrupt-driven protocol. Understanding these enhancements helps developers appreciate the technical challenges behind building USB 3.0 IP, and focus on the key requirements for selecting the ideal third party IP for their applications. USB 3.0 supports 5 Gbps performance, which is 10X the performance of USB 2.0s 480 Mbps throughput. USB 3.0 technology achieves this performance by adding a second physical datapath that operates in parallel with a USB 2.0 data bus. At a physical layer level, this results in the addition of five extra wires to the USB cable and the connector. One differential pair is used for transmit; one pair is used for receive; and the remaining wire is for ground. When used to communicate to a USB 2.0 device, the USB 3.0 wires are not used. USB 3.0 also utilizes dual simplex data transfer, in contrast to USB 2.0, which uses half-duplex communication. With half-duplex mode, the USB 2.0 transmit and receive paths share one pair. With USB 3.0, transmit and receive pairs are separate, and the effective throughput is actually 20X when transmitting and receiving data back and forth. Power efficiency is the second key enhancement in the USB 3.0 specification. Power-hungry peripherals often need a dedicated power connection in addition to a USB 2.0 connection. USB 2.0 provides only 100mA in a low-power state vs. USB 3.0s 150mA, which is 50% more power. For a configured device (an active device), USB 2.0 supplies up to 500mA vs. USB 3.0s 900mA, which is 80% more and enables power-hungry devices to charge quickly using only bus power. In addition, the introduction of a B type connector in USB 3.0 provides up to 1000mA current. Hence, USB 3.0 significantly reduces the need for an additional power connection for most devices. Considerable power savings come from replacing USB 2.0s continuous-polling feature with an interrupt-driven protocol. In USB 2.0, the host continuously polls every connected PC peripheral if it has data to transmit to the host. Data is broadcast to every device plugged into USB 2.0. For example, if a USB 2.0 hard drive and printer are connected to a PC, data sent to the hard drive are also sent to the printer. USB 3.0 eliminates the need for broadcast packetsdata is transmitted only to the device that needs it. In USB 3.0, the host or the device

Technical Considerations for Implementing USB 3.0 on SoCs

can initiate a power saving mode. An idle USB 3.0 device will not drain power from the computer, but will go to a power saving state. This has a huge positive impact on a laptops battery life. In the USB 3.0 specification, devices can enter power-save states between isochronous transfers. These features, combined with updated power management features (idle, sleep and suspend states) at the link and device levels, allow USB 3.0 to support a 10X performance improvement over USB 2.0, with just a 2X increase in power. USB 3.0 is 100% backward compatible with USB 2.0. When a USB 3.0 device connects to a USB 2.0 port, only one pair of data lines is used and the SuperSpeed mode of operation is not used. The link and the PHY are implemented such that they operate in full compliance to the operational speed. Cable length is another change between USB 2.0 and USB 3.0. USB 3.0 supports a cable length of up to 3 meters. USB 2.0 supports a cable length of 5 meters. Typical USB 2.0 cables used are actually less than 2 meters in length, so the reduction in cable length makes little difference. For longer USB 3.0 cables, a device called an active cable actually allows for cable lengths of up to 13 meters. The incremental cost for adding this device is small if users need the length.

USB 3.0 IP Selection Challenges and Need for Quality IP

The architectural enhancements defined by the USB 3.0 protocol make the challenge of selecting IP for a given application complex and substantial. For example, the new power management and performance improvement features influence the IP design and test. Therefore, selecting USB 3.0 IP that implements these functionalities in a robust and an efficient manner is critical to developing a standard-compliant USB 3.0 SoC.
SoC USB 3.0 PHY USB 3.0 host controller USB 3.0 PHY USB 3.0 PHY USB 3.0 PHY SoC USB 3.0 device controller USB cable USB 3.0 PHY USB 3.0 device controller SoC

SoC USB 3.0 PHY USB 3.0 device controller

Figure 1: Reconfigurable USB 3.0 IP used in multiple product SoCs

As shown in Figure 1, USB 3.0 can be used in many volume applications and selecting IP that is proven to support these applications can be difficult. The time-to-market window for SoCs implementing USB 3.0 is typically only a few months, so SoC designers need to minimize the tasks required that differentiate their products while meeting aggressive schedules. For example, modifying the USB 3.0 core to match the end application, and integrating it into the SoC, is challenging and time-consuming. Second, getting the controller and the PHY IP to interoperate and provide a 100% compliant and fully integrated solution is another challenge. Ensuring that the USB 3.0 PHY has sufficient performance margin across process, voltage, and temperature (PVT) while maintaining signal integrity and minimizing EMI/RFI emissions across the range of operations is a third challenge. This includes ensuring IP availability in multiple process technologies and price points while proving performance in silicon. Fourth, availability of device drivers stacks is a key criterion. New driver stacks are required to handle the faster USB 3.0 speeds, and simply extending USB 2.0 architectures

Technical Considerations for Implementing USB 3.0 on SoCs

to support USB 3.0 would never reach USB 3.0 throughput. Lastly, stringent USB-IF certification demands rigorous simulation and FPGA validation before silicon implementation. Universality of the USB protocol requires that hosts are tested with hundreds of USB 2.0 devices and all available USB 3.0 devices. These tasks can take many engineering months for successful completion. For their first USB 3.0 designs, some designers try to add USB 3.0-capable register sets to an existing USB 2.0 controller architecture, in an attempt to reuse 10 years worth of USB 2.0 software written for USB 2.0 register sets. Unfortunately, extending the architecture of a USB 2.0 controller to be USB 3.0 capable will not work because a USB 3.0 MAC is different from a USB 2.0 MAC. A USB 3.0 MAC supports higher performance features like streams and bursts. Therefore, an extension of a USB 2.0 register set to USB 3.0 will never reach USB 3.0 speeds and a new USB 3.0 architecture is required. The advantage to a single USB 3.0 architecture is a single software stack can support all USB speeds. Building this new architecture and ensuring both USB 3.0 performance and USB 2.0 backward compatibility is a challenging task for a design team under pressure to deliver a complete SoC. A viable solution is to obtain proven third party USB IP, which can be cost competitive. High quality, certified controller and PHY IP cores are needed to address these complexities and meet the SoC time-to-market windows. The successful SoC designer will consider all these factors and implement a robust, flexible and reusable USB 3.0 solution.

Seven Requirements for Reusable USB 3.0 IP

This section describes seven technical requirements for choosing a standard-compliant USB 3.0 controller IP and PHY. It outlines the design considerations and the challenges involved in implementing the USB 3.0 protocol enhancements discussed earlier. It describes the development methodology needed, including design, test and certification processes, to build a USB 3.0 product.

1. Flexible USB 3.0 controller IP

The USB 3.0 controller IP designed for reuse should implement the functions defined in the protocol specification to support all application models. This requires the controller IP be configurable as a device, a host, or both (dual-role). A USB 3.0 device goes into peripherals, which range from the simple (flash drives) to the complex (mobile phones). A USB device core designed for one application cannot be incorporated directly into another application. For example, a USB IP core built for a flash drive cannot be transferred into a mobile phone. A USB 3.0 host goes into PCs, TVs, BluRay players, and game consoles. Hosts must support many USB peripherals simultaneously. In addition to SuperSpeed USB 3.0 and High-Speed USB 2.0 devices, a host must support devices of many speeds, like Low-Speed USB 1.1 mice and keyboards, or Full-Speed USB 1.1 speakers. A host must work with many drivers. A USB 3.0 dual-role device (DRD) goes into mobile phones, tablet PCs, and any product that can act as either a USB 3.0 host or a USB 3.0 device. Therefore, a USB 3.0 DRD must have the logic to be either a USB 3.0 host or device. The DRD IP should be configurable as a host, a device, or a dual-role.

Technical Considerations for Implementing USB 3.0 on SoCs

SoC bus (AHB/AXI/Native) System CPU System memory Master DWC_usb3 controller Slave USB 3.0 PHY (PIPE3 and UTMI+)

Application

Tx data FIFO RAM (single/2-port)

Rx data FIFO RAM (single/2-port)

Descriptor register cache RAM (single/2-port)

Figure 2: USB 3.0 system block diagram showing the controller IP and PHY IP cores and connectivity to processor and memory

Figure 2 shows the typical connectivity of the controller core to the PHY cores, memory and the SoC. It has two PHY interfaces: UTMI+/ULPI for USB 2.0 PHY connectivity and PIPE3 for USB 3.0 PHY communication. To support the USB 3.0 throughput of 5 Gbps, the system interface should be a high-performance industrystandard standard interface such as AXI. The interface bus widths should be configurable to match the operational mode. Todays design may use 32 bits, but later designs will move to a 64- or 128-bit interface. A memory management system that can handle USB 3.0 throughput speeds of 5 Gbps is critical to maximizing performance for USB 3.0 IP. Since the reusable IP will be used in several functional modes (host, device, and dual-role), memory sizes and types (SPRAM or DPRAM) and clocking speeds should be selectable to match the end-application needs. The buffer management scheme should take clocking speeds, memory types and system interfaces into account and define a low-latency memory system that can sustain the 5 Gbps throughput. In addition to hardcore configurability, the memory resource allocation needs to be done dynamically. For example, the endpoint mode needs to make sure that the FIFO buffers are appropriately allocated so that the data is fetched to meet the USB 3.0 turnaround times. The power management enhancements in the USB 3.0 specification affect datapaths and controller blocks. The power saving scheme at the link layer level varies based on the application. Therefore, power management state-machine design is different for each mode. For example, in USB 2.0 mode, IP implements the power-down scheme based on the link power management (LPM) token scheme, an enhancement to the original USB 2.0 link management scheme. In host and dual-role modes, the core needs to implement the xHCI specified power management schemes. The USB 3.0 protocol defines a system-level clock-gating scheme, referred to as the U0, U1, U2, and U3 states.

2. Robust USB 3.0 PHY IP

The USB 3.0 PHY is a highly complex mixed signal IP that needs to support 5 Gbps data rates with maximum signal integrity. It should be a compact design and provide performance margins to operate under worst case process, voltage and temperature variations. It should be easily integrated with the controller and the rest of the SoC, and be proven in a wide range of foundry processes.

Technical Considerations for Implementing USB 3.0 on SoCs

UTMI+/- Interface (HS)

DP0/DM0

Serial interface (LS/FS) USB 3.0 host/device controller PIPE3 interface Power, clock, external resistor USB 3.0 PHY tx0_p, tx0_m; rx0_p, rx0_m

Controls

Figure 3: USB 3.0 PHY interfaces

As shown in Figure 3, the USB 3.0 PHY has a line interface comprised of a 4-wire (two transmit and two receive) connection to support the USB 3.0 full-duplex mode. It uses a PIPE3 interface to connect to the USB 3.0 controller. It transmits and receives 480 Mbps data in USB 2.0 mode and 5 Gbps data in the USB 3.0 mode. On the receive side, it performs data recovery, alignment, decoding, de-serialization and adaptive equalization functions, and on transmit side, it serializes and sends data. One of the mandatory features to support the USB 3.0 protocol is spread-spectrum clock (SSC) generation and absorption. This clocking scheme reduces the EMI/RFI emissions by dithering the system clock and spreading the energy across the spectrum to reduce energy peaks. The PHY should provide an option to use a fixed-frequency reference clock and should be able to generate the modulated clock internally. It should handle a wide range of input clock frequencies to generate high-speed clocks for data transmission in all the modes. A single input reference clock is desirable for ease of use. These features make the PHY clocking architecture and test scheme more complex; however, they also simplify the IP integration and clock-routing tasks at the SoC level, which makes them important for successful PHY IP implementation. At USB 3.0 performance levels, signal integrity is a significant issuethe adaptive RX equalization function should be designed to adjust the receiver automatically to recover the 5 Gbps incoming data for channel lengths ranging from several centimeters to three meters. The PHY design should carefully match the controller design to prevent the false detection of electrical-idle on the data lines or low-frequency periodic signaling (LFPS) as defined in the PIPE3 specification. Similar to the controller, the PHY core needs to support the USB 3.0 compliant power management schemes (U0, U1, U2, and U3). The power-down modes vary based on the operating mode, i.e., SuperSpeed, Hi-Speed, Full-Speed, or On-the-Go (OTG) modes. The validation of the power-down functionality is complex but necessary for proper interoperability between the controller and PHY. The PHY needs to implement a robust electrostatic discharge (ESD) protection scheme as per the JEDEC class specifications and pass different ESD models (machine model, human body model, and charge device model). The design should allow sufficient metal widths in all the ESD paths. ESD protection devices should be designed into signal pads and power supply pads. The USB 3.0 PHY must be available in the foundry processes that meet the applications criteria such as wafer price, area, and power. Since multiple applications use USB 3.0, demand for the PHY ranges from low-cost 130-nm to state-of-the-art 28-nm processes. As a result, multiple USB 3.0 PHY architectures based on 3.3V I/O, 2.5V I/O, and 1.8V I/O devices are required depending on the process geometry. To minimize risk, thorough adherence to all foundry design, design-for-manufacturability rules, and long-term reliability rules are a requirement.

Technical Considerations for Implementing USB 3.0 on SoCs

3. USB 3.0 IP test and testability implementation

Silicon testing is an expensive but important step in taking a SoC to production. IP cores need to implement a spectrum of test and testability features to minimize the SoC test efforts and take the device to production in a timely manner. The test requirements for the USB 3.0 IP solution are particularly stringent due to the protocol complexity, operation speeds, and memory requirements. However, since USB 3.0 is used in many price sensitive applications, silicon test time needs to be very short and cost-effective. The controller and the PHY IP need to provide test features such as built-in test (BIST), internal scan, and JTAG for boundary scan. In addition, programmable loopback options to loop the transmit data back to the receive data path from several points in the data paths need to be implemented. The digital IP needs to implement JTAG per the IEEE 1149.1 specification and the TAP controller should have easy access to all the hardware resources including the registers and the RAM buffers. The PHY BIST features should include pseudo-random binary sequence (PRBS) support for bit error testing and the link integrity tests should provide flexible program parameters to validate channel performance margin.

4. Thorough verification flow

A reusable IP verification system should include a stand-alone test environment for the controller and the PHY. In addition, it should cover verification of the USB 3.0 controller and the PHY cores as an integrated USB solution. To ensure interoperability and performance, a thorough verification strategy to test the USB 3.0 IP is required. The verification environment and functional coverage plan must cover all the IP configurations and provide 100% coverage for compliance tests. A PHY verification system needs to simulate the PHYs analog functions as well as signal integrity and channel loss. The typical PHY simulator implements a 4-state simulation scheme but it should also effectively simulate the voltage and current changes on the signal-lines over time. Extensive signal integrity simulation using precise HSPICE models of TX and RX channels, including analog front ends and receive equalization, is necessary. Figure 4 shows the result of a signal integrity simulation using end-to-end channel models. Parameters such as RX eye-openings need to be measured across worst-case channel models.

Figure 4: Results of a signal integrity simulation using end-to-end channel model

5. FPGA prototyping and hardware validation

Design validation using FPGA systems is an integral part of the SoC design methodology. For complex IP such as USB 3.0, architectural details can be quickly fine-tuned using FPGA prototyping. Critical design issues can be identified before tape-out, minimizing the risk and time-to-market. The cores can be stressed tested for more USB transactions, than simulation. Simulation takes hours to run a few seconds of real-world traffic. Since USB 3.0 requires extensive software development to support the various device classes, FPGA prototyping enables concurrent development of USB 3.0 firmware.

Technical Considerations for Implementing USB 3.0 on SoCs

Figure 5: Example USB 3.0 FPGA validation platform

Figure 5 shows an example of a FPGA validation platform. It consists of the motherboard with an FPGA and a USB 3.0 PHY daughter card. The USB 3.0 controller core is mapped to the FPGA using a configuration file. When using such a validation platform, resets and clocks are sourced from the on-board clocking system to match the operational mode. The validation should be cycle-accurate and should support all types of USB 3.0 data transfers at-speed. Real world testing at USB 3.0 speeds helps to verify the architecture, such as memory management and interoperability tests for USB 3.0 standard compliance. Lastly, a FPGA validation platform can also be used for USB-IF certification of a prototype design.

6. Complete device drivers and programming models

Device drivers play a critical role in supporting USB applications and are highly complex due to the diversity of applications and the combinations of functionality. Device drivers that interface between the hardware components, i.e., the controller IP and the application-specific peripheral driver stack, are a key deliverable for USB IP. Device drivers program the cores registers. Its features and functionality correspond to the IP configuration mode, i.e., device, host, or dual-role. For example, in device mode, the device driver should support deviceinitiated disconnects by dynamically mapping physical endpoints to logical endpoints. When operating in the USB 3.0 mode, the device driver needs to support the stream protocol and implement a different class of devices. In USB 3.0 host mode, the host functionality should be implemented according the xHCI specification where both USB 2.0 and USB 3.0 operation can be simultaneously active to support USB 2.0 and USB 3.0 devices concurrently. In all configurations, the device driver should automatically build descriptors and a control buffer management structure. It needs to implement power management methods per the USB 3.0 specification and other IP-specific power management schemes. It should support bulk and isochronous type data transfers by managing command queuing, stream support, and out-of-order packet management.

7. USB-IF certification
The USB Implementers Forum (USB-IF) manages all aspects of the USB specification. The USB-IF oversees certification testing and authorizes third-party test labs. While certification applies primarily to end products, USB 3.0 digital and PHY IP can also be certified as part of a design. USB-IF certification is a critical and essential component of quality USB products. Through rigorous software and electrical testing, certification verifies compatibility with other USB devices. Built on 12 years of USB test knowledge, USB 3.0 certification includes protocol, link, physical, and electrical compliance tests. The USB-IF Platform Integration Lab (PIL) lists the tests based on the configuration of the USB core, which include device mode tests and hub configuration tests (e.g., cyclic redundancy check (CRC), packet robustness, U0/ U1/U2/U3 transitions, reset initiation, etc). Host certification involves xHCI host compliance tests and USB device specific tests for all speeds and tests as described in the USBCV chapter 9 (e.g., descriptors, suspend/

Technical Considerations for Implementing USB 3.0 on SoCs

resume, remote wake function, multiple enumeration of devices, etc). The connector and cable electrical tests include time domain measurements such as near-end cross talk, impedance measurement, and insertion loss. Interoperability tests include verifying the attach/detach functionality and various lower management modes such as suspend, hibernate, and hybrid sleep modes, and warm and cold boot. USB 2.0 compatibility is tested by connecting a USB 3.0 host to USB-IF specified sample of 150 devices. Certification is an extensive process that typically takes about three months.

USB 3.0 IP Selection

When selecting USB 3.0 controller and PHY IP, the seven technical requirements for reusable IP are not the only considerations. SoC designers must also consider the additional features and functionality that a technology and industry leader can bring to their design. This section highlights a few important features of the Synopsys DesignWare USB 3.0 IP solution, which will help designers implement a robust USB 3.0 solution. DesignWare USB 3.0 IP from Synopsys is a complete, certified solution consisting of the digital controller IP, the PHY IP, and the production-quality device drivers. The IP can be instantiated on the Synopsys HAPS FPGA-Based Prototyping Solution and verified with fully interoperable verification IP. The digital IP supports all modes of operation (device, host, and dual-role) and these modes are easily configurable. It also supports the OTG mode as an add-on feature. For each configuration, the functionality and performance can be optimized by fine-tuning parameters such as interface bus widths, clock rate, RAM mode and buffer sizes interactively to suit the SoCs end application. To connect with the rest of the system, the IP provides multiple interface options, including AXI, AHB, and a simple native interface. The USB 3.0 IP offers controllability through a set of registers and handles all the protocol functions. This minimizes the million instructions per second (MIPS) requirements on the application software. DesignWare USB 3.0 IP is designed for maximum power efficiency and ease-of-use, and supports USB 3.0 power modes U0, U1, U2, and U3. The IP has additional power management features designed for simple SoC integration. For example, the control module that detects the USB 3.0 wakeup condition is implemented as a separate module, providing flexibility for the SoC designer to place it in an always on SoC block and add voltage shifter cells and isolation cells as needed. In addition, its RTL modules are coded such that in normal operation of the flops render themselves for clock-gating when used with a power-optimization tool. When optimized with Power Compiler, the DesignWare USB 3.0 IP provides a 50% power reduction (vs. not performing power optimization) in all the configurations. Using Synopsys coreConsultant, a GUI-based menu driven interface, the core can be configured to suit a particular application in minutes. Default parameters (e.g., buffer sizes and types, system interface, etc.) are grouped and preset according to both operational modes and USB-IF class specifications. This grouping makes the configuration process very simple. coreConsultant outputs optimized RTL based on the configuration. Generated RTL follows coding standards specified in the Synopsys Reuse Methodology Manual. SoC designers can use coreConsultant to execute simulation, synthesis, and static timing, or they can generate scripts to help batch mode simulations and synthesis. The DesignWare USB 3.0 PHY is a compact and power-efficient design; it provides flexibility to adapt to diverse applications and SoC implementations. For example, it provides options to select bus widths and clock rates, yet it provides programmability to control SSC generation. The SSC-modulated clock can be sourced to the PHY, or the PHY can be programmed to generate the SSC modulated clock, from a fixedfrequency reference clock. The PHY implements robust ESD structures with additional protection circuits, such as back-to-back diodes to enable current flow between power domains and prevent ESD damage. Supporting a wide range of metal stacks and package types, the DesignWare USB 3.0 PHY IP is available today in popular silicon proven processes ranging from 130-nm to 28-nm. As shown in Figure 6, the DesignWare USB 3.0 PHY IP implementation on the 28-nm process provides excellent signal integrity.

Technical Considerations for Implementing USB 3.0 on SoCs

Figure 6: Eye diagram from 28-nm DesignWare USB 3.0 PHY

The DesignWare USB 3.0 controller IP is delivered with verification IP, which can be used at the block level or integrated into the SoC-level test bench implemented in Verilog, Vera, or VHDL. The extensive test suite is generated based on the configuration and it includes the USB 3.0 protocol and the IP-specific functions. The DesignWare USB 3.0 PHY verification methodology includes simulating analog functions such as RX equalization, LOS voltage setting, RX eye capture and I/O termination. Synopsys provides PHY models for SoC-level functional simulations and signal integrity simulations by providing link channel models, which are used for eye diagram and channel loss simulations. Several test and testability features are implemented in the DesignWare USB 3.0 IP. The digital IP implements JTAG as per IEEE 1149.1 specification and the TAP controller is designed to have easy access for all the hardware resources including the registers and the RAM buffers. It also implements the in-circuit emulator (ICE) function to assist debugging. The PHY BIST features includes pseudo-random binary sequence (PRBS) support for bit error testing. The link integrity tests provide flexible program parameters to validate the performance margin of the PHY. Comprehensive directed tests enable validation of the PHY during prototype development and volume production. The DesignWare USB 3.0 IP solution is prototyped and validated using the Synopsys HAPS FPGA-Based Prototyping Solution and the system is tested at-speed for functionality and performance. The HAPS Systems have the additional advantage that the USB 3.0 core is already pre-mapped to the FPGA, so clock speed, gate count, and other FPGA-specific considerations are not an issue. Synopsys provides example device drivers for the Linux operating system. It implements the USB-IF specified classes, which define the driver requirements for various device classes such as storage, human interface devices, card readers, and modems. The DesignWare USB 3.0 IP solution is USB-IF certified. In addition to certification in the USB PIL, the IP undergoes extensive interoperability testing in Synopsys state-of-the art in-house lab, where it is tested with over 200 USB devices. Synopsys also participates in PlugFests for interoperability testing with the latest consumer devices. This standard-compliant, feature-rich, and easy-to-use IP solution developed using advanced design methodology and stringent test and certification process enables a low-risk implementation of USB 3.0 in a SoC.

Summary
USB continues to be the de-facto standard for connecting consumer devices to PCs. Present day consumer entertainment applications such as HD movies, audio-video streaming, and state-of-the-art storage devices

Technical Considerations for Implementing USB 3.0 on SoCs

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need much higher bandwidth than the 480 Mbps supported by the USB 2.0 protocol. In addition, mobile devices such as smart phones and tablets are demanding more efficient data transfer and power management control to maximize battery life. With over 100 million USB 3.0 host chips shipped, integrated chipset support in 2012, and widespread support, anyone designing a USB product should upgrade their product to USB 3.0 now. USB 3.0 satisfies high performance and low power requirements by providing a 10X increase in throughput for just a 2X increase in power. These enhancements, along with backward compatibility with USB 2.0, make USB 3.0 a natural and obvious choice for USB SoC designers. USB 3.0 achieves its power-saving and throughput enhancements through new architectures in the link layer, the physical layer and the software. This results in significant design, verification, test, interoperability and certification challenges. Choosing reusable USB 3.0 IP is a low-risk and cost-effective option for an SoC designer. IP selection must take power and performance requirements into account, along with aggressive time-to-market windows. It is critical to select a silicon-proven and certified USB 3.0 IP that can be reused for multiple applications. Chief IP requirements include robust implementations of USB 3.0 features, along with backward compatibility to USB 2.0, test and certification. The digital core should be easily configurable to support multiple operational modes such as device and host, and the PHY should be compact and available in different process technologies. The PHY and the controller should be verified as a complete solution in various configurations. The cores and the test environment must render themselves for easy integration in to the SoC, and the IP supplier should include hardware validation using FPGA prototyping to complement simulations and to enable concurrent software development. The IP vendor also needs to provide a complete device driver stack that can interact with customers application software. Finally, USB-IF certification is a must. Choosing an IP solution such as the DesignWare USB 3.0 controller and PHY will enable SoC designers to develop a high-quality USB 3.0 silicon solution to meet growing market demands in a timely manner.

References
[1]

Agam Shah. High-Speed USB 3.0 to Reach Smartphones, Tablets by Year End. PCWorld. 8 Jan 2012. 13 March 2012 http://www.pcworld.com/article/247507/highspeed_usb_30_to_reach_smartphones_tablets_by_ year_end.html

[2]

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