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    VHDL Implementation of A Crossbar Packet Switch

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    Vikas Tarvecha
    The document discusses the implementation of a crossbar packet switch using VHDL. It describes the key components of the switch including input ports, a centralized scheduler, output ports, and a switch fabric. It also discusses different arbitration techniques that can be used for the switch fabric, including simple fixed priority arbitration, cyclic ripple carry arbitration, rectilinear propagation arbitration, and diagonal propagation arbitration. Each technique has advantages and disadvantages in terms of priority handling and feedback loops.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    VHDL Implementation of A Crossbar Packet Switch

    Uploaded by

    Vikas Tarvecha
    49 views1 page
    The document discusses the implementation of a crossbar packet switch using VHDL. It describes the key components of the switch including input ports, a centralized scheduler, output ports, and a switch fabric. It also discusses different arbitration techniques that can be used for the switch fabric, including simple fixed priority arbitration, cyclic ripple carry arbitration, rectilinear propagation arbitration, and diagonal propagation arbitration. Each technique has advantages and disadvantages in terms of priority handling and feedback loops.

    Original Description:

    Implementation of Switch in VHDL

    Original Title

    Switch Implementation

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    The document discusses the implementation of a crossbar packet switch using VHDL. It describes the key components of the switch including input ports, a centralized scheduler, output ports, and a switch fabric. It also discusses different arbitration techniques that can be used for the switch fabric, including simple fixed priority arbitration, cyclic ripple carry arbitration, rectilinear propagation arbitration, and diagonal propagation arbitration. Each technique has advantages and disadvantages in terms of priority handling and feedback loops.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    49 views1 page

    VHDL Implementation of A Crossbar Packet Switch

    Uploaded by

    Vikas Tarvecha
    The document discusses the implementation of a crossbar packet switch using VHDL. It describes the key components of the switch including input ports, a centralized scheduler, output ports, and a switch fabric. It also discusses different arbitration techniques that can be used for the switch fabric, including simple fixed priority arbitration, cyclic ripple carry arbitration, rectilinear propagation arbitration, and diagonal propagation arbitration. Each technique has advantages and disadvantages in terms of priority handling and feedback loops.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    VHDL Implementation of a Crossbar Packet Switch

    Maryam Keyvani and Ljiljana Trajkovic {mkeyvani, ljilja}@cs.sfu.ca http://www.ensc.sfu.ca/research/cnl Communication Networks Laboratory, School of Engineering Science, Simon Fraser University

    server_2

    client_2

    station_1

    switch_3 station_2 switch_1 server_1 station_3 client_1 switch_2

    Crossbar switch: Pros: non blocking Cons: complex control system Input buffers: input N-1 Pros: the fabric may have the input N same speed as the links Cons: head of line blocking (HOL) output 1 output 2 output N
    input 1

    An ATM switch is a network element that forwards ATM packets to their destinations.

    Input buffered crossbar switch

    Our switch consists of input ports, a centralized scheduler, output ports, and a switch fabric.

    output data request grant output port ID

    input data frame pulse Port1 port grant

    output data frame pulse out data valid port request fabric

    data out port1 data out fp out port1 data valid port1 incoming port to output1 output1 frame pulse out data and control signals 1 to 8 DEMUX

    to output port1 2 3 4 5 6 7 8

    Controller Main FIFO 2 KBytes VCI FIFO 128 Bytes Port LUT input data Input port

    c_bar request scheduler

    grant grant 64

    Crossbar fabric DEMUX for the packet switch

    2,4
    2,4

    3,3
    3,3 3,4

    3,4

    1,1

    1,2

    1,3

    1,4
    4,2 4,3 4,4

    4,2

    4,3

    4,4

    1,1
    2,1 2,2 2,3 2,4

    1,2

    1,3

    1,4
    1,1 1,2 1,3 1,4

    1,1

    1,2

    1,3

    1,4

    2,1
    3,1 3,2 3,3 3,4

    2,2

    2,3

    2,4
    2,1 2,2 2,3

    2,1

    2,2

    2,3

    2,4

    3,1

    3,2

    3,3

    3,4
    3,1 3,2

    3,1

    3,2

    3,3

    3,4

    4,1
    4,1 4,2 4,3 4,4

    4,2

    4,3

    4,4
    4,1

    4,1

    4,2

    4,3

    4,4

    1,1

    1,2

    1,3

    Simple 4x4 arbiter

    Logic inside an arbiter cell

    A cyclic two-dimensional ripple carry arbiter

    Rectilinear Propagation Arbiter (RPA) architecture

    Modified arbitration cell for RPA architecture

    Diagonal Propagation Arbiter (DPA) architecture

    2,1

    2,2

    3,1

    Shaded cells are cells with grants Disadvantage: fixed priority for 1,1 arbiter

    A grant signal is only issued when there are no grants issued for cells on the top and left

    Shaded cells are cells with grants, assuming (2,3) is the highest priority cell Disadvantage: combinational feedback loop

    Highest priority cell = (1,1)

    Reference: J. Hurt, A. May, X. Zhu, and B. Lin, Design and implementation of high-speed symmetric crossbar scheduler, Proc. ICC99, Vancouver, Canada, June 1999, s37-6.

    Shaded cells are cells that DPA architecture with have received grants priority rotation Disadvantage: first diagonal always has the Shaded cells are cells with highest priority grants, when the highest priority is the first diagonal

    ASI Exchange March 13, 2001

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