I.

INTRODUCTION to CMOS FABRICATION This paper aims to discuss the steps included in the production of integrated circuits. Production and usage of IC over other electronic devices have the following advantages: miniaturization and hence increased equipment density, cost reduction due to batch processing, increased system reliability due to the elimination of soldered jois, improved functional performance, matched devices, increased operating speeds and reduction in power consumption. It is essential for Electronic Engineers like us to know how a specific IC is made inorder for us to fully grasp its importance, function and uses. For proper operation of the device/circuit, the substrate material must have crystalline structure where all the atoms are aligned in a specific pattern. We will start our discussion with the most fundamental step in the unit processes of CMOS production which is the wafer manufacture. Wafer manufacture includes the extraction of Silicon, the most used element not only in fabrication of integrated circuits but also in numerous electronic components. Wafer manufacture is then combined with the other unit processes in order to produce the desired output, which is the CMOS integrated circuit. To sum it all up, an integrated circuit process is usually a structured sequence of operations such as the ability to deposit/modify thin films on the substrate, to apply a patterned mask on the films by photolithographic process, and to etch the films selectively to form actual devices. Some of the unit processes may be repeated in the process flow of fabrication.

II. RESEARCH CONTENTS A. CMOS Unit Processes 1. Wafer Manufacture Wafer manufacture begins with the extraction of Silicon, the second most abundant element in the Earths crust. But elemental silicon is a man-made material which is only refined from the compounds in nature, the most common of which is Silica (SiO2). Solid materials are classified by the way the atoms are arranged within the solid. Materials in which atoms are placed at random are called amorphous. Materials in which atoms are placed in a high ordered structure are called crystalline. Polycrystalline materials are materials with a high degree of short-range order and no long-range order. These materials consist of small crystalline regions with random orientation called grains, separated by grain boundaries. The basic semiconductor materials used in chips are crystalline silicon.

Arrangements of atoms in solids The crystal consists of two separate parts: the lattice and the basis. The lattice is an ordered arrangement of points in space, while the basis consists of the simplest arrangement of atoms which is repeated at every point in the lattice to build up the crystal structure.

a. Metallurgical Grade Silicon (MGS) The typical source material for commercial production of elemental silicon is quartzite gravel; a relatively pure form of sand (SiO2). Raw Si is abundantly available from steel industry and only a small part of it only required for the semiconductor industry. Since it is a byproduct from steel industry, it is commonly called Metallurgical Grade Silicon (MGS). MGS is poly crystalline material with a purity of about 99%.The first step in the synthesis of silicon is the melting and reduction of the silica in a submerged-electrode arc furnace. It is made by the reduction of SiO2 (quartz sand) with carbon (coal) in huge furnaces lined with carbon, with big graphite electrodes inside (carrying huge amounts of current) at about 2000C. The wood chips are also added to provide the necessary porosity such that the gases created during the reaction (SiO and CO) are able to flow through the bed. The reaction is C (s) + SiO2 (s) Si (l) + CO (g)

Care should be taken to suppress the other reaction occurring simultaneously (Si + C SiC), which will not only reduce the yield of Si, but clog up the furnace by SiC.

Schematic of submerged-electrode arc furnace for the production of metallurgical-grade silicon (MGS) The 9N purity (99.9999999) silicon is made essentially in three steps: Liquid Si reacts with all substances and is a universal solvent. This makes crystal growth from liquid Si somewhat difficult. Si is converted to SiHCl 3 via the reaction at around 300C Si (s) + 3HCl (g) SiHCl3 (g) + H2 (g) + heat

The resulting Trichlorosilane is already much purer than the raw Si; it is a liquid with a boiling point of 31.8C. The SiHCl3 is further distilled, resulting in extremely pure Trichlorosilane. Finally, high-purity Si is produced by a "Chemical Vapor Deposition" (CVD) process.

Often very small but precisely measured amounts of As, P or B can also be incorporated into the growing polysilicon. The drawbacks of the above process are that it is energy and raw material intensive. It is estimated that the production of one metric ton (1,000 kg) of MGS requires 2500 - 2700 kg quartzite, 600 kg charcoal, 600 - 700 kg coal or coke, 300 - 500 kg wood chips, and 500,000 kWh of electric power. Currently, approximately 500,000 metric tons of MGS are produced per year, worldwide. Most of the production (ca. 70%) is used for metallurgical applications (e.g.,

aluminum-silicon alloys are commonly used for automotive engine blocks) from whence its name is derived. Applications in a variety of chemical products such as silicone resins account for about 30%, and only 1% or less of the total production of MGS is used in the manufacturing of high-purity EGS for the electronics industry. The current worldwide consumption of EGS is approximately 5 x 106 kg per year.

b. Electronic Grade Silicon (EGS) Electronic-grade silicon (EGS), a polycrystalline material of high purity, is the raw material for the preparation of single-crystal silicon. Electronic properties of a semiconductor such as silicon are extremely sensitive to impurity concentrations. Impurity levels measured at parts per million or less can give dramatic effects on carrier mobilities, lifetimes, etc. It is therefore necessary to further purify the MGS to EGS. Obtaining EGS, requires a multi step process. First, metallurgical-grade silicon (MGS) with purity up to 99% is produced in submerged-electrode arc furnace. The furnace is charged with quartzite, a relatively pure form of sand, and carbon in the form of coal, coke, and wood chips. In the furnace a number of reactions take place, the overall reaction being SiC + SiO2 Si(liquid) + SiO(gas) + CO (gas)

The next process step is to pulverize the MGS mechanically and react it with anhydrous hydrogen chloride to form trichlorosilane (SiHCl 3) according to the reaction: Si(solid) + 3HCl(gas) SiHCl3 (gas) + H2 (gas) + heat

At this point the purification process occurs. Trichlorosilane(TCS) is a liquid at room temperature (boiling point 32C), as are many of the unwanted chlorides. Purification is therefore done by fractional distillation. EGS must have 99.999999999 % purity. EGS is prepared from the purified TCS in a chemical vapor deposition (CVD) process. The chemical reaction is a hydrogen reduction of trichlorosilane(TCS). 2SiHCl3(gas) + 2H2(gas) 2Si(solid) + 6HCl(gas)

An alternate process for the production of EGS that is starting to receive commercial attention is the pyrolysis of silane. The overall reaction is SiH4(gas) + heat Si(solid) + 2H2(gas)

The advantages of producing EGS from silane are potentially lower cost and less harmful byproducts. c. Czochralski (CZ) Growth and Wafer Formation

The Czochralski method, invented by the Polish scientist J. Czochralski in 1916, is the method of choice for high volume production of Si single crystals.

Czochralski method of crystal growth Essentially, a crystal is "pulled" out of a vessel containing liquid Si as shown in Fig 3.10. A seed crystal is dipped into the liquid and is subsequently slowly withdrawn from the melt. The pulling rate (usually a few mm/min) and the temperature profile determines the crystal diameter that can achieved. The solubility of impurity atoms in the melt is larger than in the solid. As a result, the crystal will be cleaner than the liquid and crystal growing is simultaneously a purification method. However the distribution of impurities vary along the length of a crystal and a homogeneous doping is difficult to achieve. Practically only As, P, and B is used for doping because of their segregation coefficient is close to 1. The segregation coefficient in thermodynamic equilibrium gives the relation between the concentration of impurity atoms in the growing crystal and that of the melt. It is usually much lower than 1 because impurity atoms prefer to stay in the melt. Oxygen is the most important impurity found in silicon and is from the quartz crucible in which the molten silicon is contained. The oxygen is typically at a level of about 5x1017/cm3 1018/cm3 in CZ silicon. Oxygen has three principal effects in the silicon crystal. In an as-grown crystal, the oxygen generally occupies interstitial positions in the silicon lattice and improves the yield strength by 25%. A small amount of the oxygen in the crystal forms SiO 4 complexes and act as donors. Even 1016 /cm3 donors can be formed, which is significant to increase the resistivity of lightly doped P-type wafers. During the CZ growth process, the crystal cools slowly through ~500C temperature and oxygen donors form. Typically annealing of the grown crystal is carried at temperatures above 500C and to remove these oxygen complexes. The oxygen can precipitate under normal device processing conditions, forming SiO2 regions inside the wafer. The

precipitation arises because the oxygen was incorporated at the melt temperature. Carbon is another impurity normally present in CZ grown silicon crystals. The carbon comes from the graphite components in the crystal pulling machine. For some applications, it is important to have even lower concentrations of impurity atoms like Oxygen and the Float Zone Crystal Growth is used.

2. Thermal Oxidation Thermal Oxidation of Silicon The oxide of silicon, or silicon dioxide (SiO2), is one of the most important ingredients in integrated circuits. Thermal SiO2 is amorphous. It has a density of 2.2 gm/cm3 and molecular density of 2.3x1022 molecules/cm3 . The crystalline SiO2 known as Quartz has a density of 2.65 gm/cm3. SiO2 has excellent properties which makes them necessary in every part of the integrated circuits. It is an excellent electrical insulator having energy gap ~ 9 eV with a resistivity greater than 10 20 ohm-cm and breakdown electric field greater than 10MV/cm. Si technology became popular because of the stable and reproducible Si/SiO2 interface. Conformal oxide growth on exposed Si surface is easily possible. SiO2 is a good diffusion mask for common dopants such as. B, P, As, Sb. In addition there exists good etching selectivity between Si and SiO2. The formation of SiO2 on a silicon surface is most often accomplished through a process called thermal oxidation. As its name implies, is a technique that uses extremely high temperatures (usually between 700-1200C) to promote the growth rate of oxide layers whose thicknesses range from 20 to 10000 angstroms. During the process, silicon substrate is exposed to a high purity oxidizing species like oxygen gas (dry oxidation) or water vapour (wet oxidation). The chemical reaction at the silicon surface for dry and wet oxidation is given as

Oxidation of silicon is not difficult, since silicon has a natural inclination to form a stable oxide even at room temperature, as long as an oxidizing ambient is present. In both cases the oxidizing species diffuses through the growing oxide and reacts with the silicon surface. These oxidation reactions occur at the Si-SiO2 interface, i.e., silicon at the interface is consumed as oxidation takes place. As the oxide grows the Si-SiO2 interface moves into the silicon substrate. As a result, the Si-SiO2 interface will always be below the original Si wafer surface. The SiO2 surface, on the other hand, is always above the original Si surface. SiO2 formation therefore proceeds in two directions relative to the original wafer surface as shown in Fig.3.12.

3. Doping Processes a. Ion Implantation

Ion Implantation Ion implantation is the introduction of atoms into a solid substrate by bombardment with ions in the keV to MeV energy range. Compared to diffusion, this technique provides wide selection of atomic species as well as external control of both the number the depth distribution of the implanted species. In a diffusion process, surface concentration is governed by the temperature and the depth distribution is determined by both the time and temperature. The initial impact of ion implantation in silicon technology was in charge control. This in combination with the fact that simple masking techniques can be used to define the geometrical area of the implanted region led to extensive to MOS technology. Presently implantation is the most common method of introducing dopant atoms for the fabrication of Si devices. Advantages Provides excellent dose control. Typical 1011 to 1016 cm-2. It has been possible to control the number of dopant atoms per cm 2 to about 1% over the surface of a wafer, and to control the number within 3% from wafer to wafer. The ion implantation results in less lateral diffusion i.e. diffusion of dopant atoms in the direction parallel to the surface of semiconductor compared to the vertical diffusion where diffusing species are moving in a direction normal to the wafer surface. The dopant elemental selection can be easily carried out by mass separation from impure sources and this helps in preventing contamination. The room temperature process allows resist to be used and it allows doping anytime during process. Modeling is very accurate Complex doping profiles can be made using multiple energy implants Highly abrupt junctions can be made Highly automatic parameters

b. Solid State Diffusion Solid state diffusion is a method for introducing and/or redistributing dopants. In typical CMOS process flows, dopants are introduced into localized regions via ion implantation where the subsequent processing often consists of high temperature processing. Solid state diffusion inherently occurs in these high

temperature steps, thus spreading out the implant profile in three dimensions.The net effect is to shift the boundary of the implant from its original implant-defined position, both laterally and vertically. This thermal smearing of the implant profiles must be accounted for during CMOS process flow development. If not, the final device characteristics can differ significantly from what was expected. Solid state diffusion (or simply diffusion) requires two conditions: 1) a dopant concentration gradient 2) thermal energy 4. Photolithography Fabrication of devices depends on selective processes such as removal of material (etching) addition of material (deposition) and modification of material (implantation, diffusion, etc.). One need to have defined areas on the substrate exposed to these processes and the rest of the substrate must be protected also during the same processes. These selected/unselected areas make up the pattern. Pattern definition takes place in the resist which is a thin layer of polymeric material coated on the substrate. The resist is modified so that it remains in some areas and is removed in others. Lithography in the integrated circuit technology context is typically the transfer of a pattern to a photosensitive material by selective exposure to a radiation source such as light.

Transfer of a pattern to a photosensitive material

A lithographic system includes exposure tool, mask, resist, and all of the processing steps to accomplish pattern transfer from a mask to a resist and then to devices. A photosensitive material is a material that experiences a change in its physical properties when exposed to a radiation source. If we selectively expose a photosensitive material to radiation (e.g. by masking some of the radiation), the pattern of the radiation on the material is transferred to the material exposed. If the resist is placed in a developer solution after selective exposure to a light source, it will etch away one of the two regions (exposed or unexposed). If the exposed material is etched away by the developer and the unexposed region is resilient, the material is considered a positive resist. If the exposed material is resilient to the developer and the unexposed region is etched away, it is considered a negative resist. a. Resolution Resolution is the minimum feature size, M, that can be printed on the surface of the wafer given by Where,

A = the wavelength of the ultraviolet light source, NA = numerical aperture of the projection lens c = constant whose value ranges from 0.5 to 1 The NA of a lens is given mathematically as NA=nsin n = index of refraction of the space between the wafer and the lens = acute angle between the focal point on the surface of the wafer and the edge of the lens radii. Notice that M is directly proportional to wavelength, hence diffraction effects are the primary limitation in printable feature size. To a limit, the NA of the projection lens can be increased to help combat the diffraction effects because large NA optics have an increased ability to capture diffracted light. At first glance, the minimum feature size cannot be less than the wavelength of the light, however, advance techniques such as optical proximity correction (OPC) and wavefront engineering of the photomasks have been developed to push the resolution limits below the wavelength. b. Depth of Focus The Depth of Focus (DOF) of the projection optics limits ones ability to patterm features at different features. Mathematically,

Relationship of the lens radii to the angle used to compute for NA c. Aligning Masks Each of Numerous mask levels during CMOs fabrication (active, poly, contacts, etc) printed on the wafer must be accurately aligned to one another. Registration is a measure of the lvel-to-level alignment error. It occurs in x, y, and z rotations.

5. Thin Film Removal a. Thin Film Etching Etching is a process that removes unwanted materials from the surface of a substrate by various dry and wet techniques. These techniques are used to remove silicon dioxide, silicon nitride, polysilicon, aluminum, tungsten, contamination particles, and other layer materials. This process step creates the layer definition that is based on the outcome of a previous photolithography process step. These etch processes transform a single layer of semiconductor material into the patterns, features, lines, and interconnects.

Etching Profiles before and after processing

A typical etching profile is given in Fig. 3.12. In this case the red region is the mask (protective layer) used, blue layer is to be removed selectively from regions not protected by mask and grey layer is the substrate which should not be etched. The profile after the etching indicates that there is a horizontal etching as well etching of underlying substrate. Selectivity is the characteristic of etch whereby the desired layer is etched without damaging the underlying or masking layers. The etching system's ability to do this depends on the ratio of etch rates in the two materials. b. Wet Etching Wet Etching is done by using a chemical solution to remove material. Wet cleaning processes are repeated numerous tines throughout a process flow, some of which targeted particulate removal while others are for organic and/or inorganic surface contaminants. Generally, wet etchants tend to be highly selective compared to dry etcg processes. They can be isotropic (etch rate is the same in all directions or anisotropic (etch rate differs in different directions). c. Dry Etching There are three general categories of dry etch techniques in CMOS fabrication namely the sputter etching, plasma etching, and reactive ion etching (RIE). Sputter Etching An inert gas (e.g., argon) is ionized where the ions are accelerated through an electric field established between two conductive electrodes, called the anode and the cathode. A vacuum in the range of millitorr must exist between the

plates to allow the appropriate ionization and transfer of ions. Under these conditions, a glow discharge, or plasma, is formed between the electrodes. In simple terms, the plasma consists of positively charged ions and electrons, which respond oppositely to the electric field. The wafer sits on the cathode where it is bombarded by the positively charged ions, causing material to be ejected off of the surface. Essentially, sputter etching is atomic-scale sandblasting. A DC power supply can be used for sputter etching substrates, while an RF supply is required through capacitive coupling for etching nonconductive substrates. Sputter etching tends not to be selective, but it is very anisotropic.

Plasma Etching A simplified diagram of a plasma etch system is shown below. A gas or mixture of gases (e.g., halogens) are ionized, producing reactive species called radicals. A glow discharge or plasma is formed between the electrodes. The radicals chemically react with the surface material forming reaction products in the gas phase which are pumped away through a vacuum system. Plasma etching can be very selective, but is typically highly isotropic.

Reactive Ion Etching (RIE). While sputter etching is a purely mechanical process and plasma etching is purely chemical, RIE is a combination of sputter etching and plasma etching, as schematically shown, a gas or mixture of gases (e.g., fluorocarbons) are ionized where radicals and ionized species are generated, both of which interact with the surface of the wafer. RIE is the dominant etch process because it can provide the benefits of both sputter etching and plasma etching. In other words, REE can be highly selective and highly anisotropic.

d. Chemical Mechanical Polishing In CMP, an abrasive chemical solution, called a slurry, is introduced between a polishing pad and the wafer. Material on the surface of the wafer is removed by both a mechanical polishing component and a chemical reaction component. In modern CMOS fabrication, CMP is a critical process that is used to planarize the surface of the wafer prior to photolithography. The planar surface allows the printed feature size to be decreased. CMP can be used to remove metals, semiconductors, and insulators.

6. Thin Film Deposition Thin films play a vital role in virtually every micro- and nanostructure. The thin films consists of wide range of materials systems such as conductors, insulators and semiconductors. Conductors such as metals and metal compounds are used for connecting transistors, for contacts and for device structures. It can be found that interconnection is much harder than making transistors. Insulators are required for electrical isolation, as dielectrics for MOS structures and for mask applications etc. Semiconductors are essential to make transistors, diodes, resistors, capacitors and are used in amorphous and polycrystalline forms for variety of applications such as solar cells, epitaxial layers and electrical contacts etc. Thin films made by a variety of means. Deposition technology can be classified in two groups i.e. depositions that happen because of a chemical reaction and that happen because of a physical reaction. Chemical Vapor Deposition, Electrodeposition, Epitaxy, and Thermal oxidation exploit the creation of solid materials directly from chemical reactions in gas and/or liquid compositions with the substrate material. In physical deposition technologies material is released from a source and transferred to the substrate. The most common examples are evaporation and sputtering. Atomic separation in a solid is about 0.3nm. The thin film thickness can range from nanometers (monolayers) to microns. Monolayers has high surface to volume ratio. Thin film properties are different from the bulk; however when hundreds of atomic layers forms micron layers, their properties are similar to that of bulk. Typically there is a critical thickness above which it behaves essentially as a bulk material. Variety of forms of thin films are possible based on their crystal structure, grain size, composition, defects, electro- chemical-mechanical-optical properties, adhesion, stress resulted etc. a. Physical Vapor Deposition (PVD)

In physical vapor deposition (PVD), physical processes produce the constituent atoms (or molecules), which pass through a low-pressure gas phase and subsequently condense on the surface of the substrate. The common PVD processes are evaporation and sputter deposition, both of which can be used to deposit a wide range of insulating, conductive, and semiconductive materials. One of the drawbacks of PVD is that the resultant films often have poor step coverage. Evaporation is one of the oldest methods of depositing thin-films of metals, insulators, and semiconductors. The basic process of evaporation is shown below. The material to be deposited is heated past its melting point in a high vacuum chamber where the vapor form of the material coats all exposed surfaces within the mean free path of the evaporant. The heat source can be of one of two types: heating filament or focused electron beam.

The figure below outlines a simplified sputter deposition process. An inert gas such as argon is ionized in a low pressure ambient where the positively charged ions are accelerated through the electric field towards the target. The target is an ultra-high purity disk of material to be deposited. The bombardment of ions with the target sputter (or eject) target atoms (or molecules), where they transit to the surface of the wafer forming a thin-film. Similar to sputter etching, a DC supply can be used for sputtering conductors; however, a capacitively coupled RF supply must be used for depositing non-conductive materials.

b. Chemical Vapor Deposition (CVD)

In chemical vapor deposition (CVD), reactant gases are introduced into a chamber where chemical reactions between the gases at the surface of the substrate produce a desired film. The common CVD processes are atmospheric pressure (APCVD), low pressure (LPCVD), and plasma enhanced (PECVD). Again, there are a wide variety of insulators, conductors, and semiconductors that can be deposited by CVD. Most importantly, the resultant films tend to have good step coverage compared to PVD processes. APCVD occurs in an apparatus similar to an oxidation tube furnace; however, an appropriate reactive gas is flowed over the wafers. APCVD is performed at relatively low temperatures. As depicted in Fig. 7.23, LPCVD occurs in a reactor in the pressure range of milliTorr to a few Torr. Compared to APCVD, the low pressure process can yield highly conformal films, but at the expense of a higher deposition temperature. A picture shows a schematic diagram of a PECVD reactor. In PECVD, a plasma imparts energy for the surface reactions, allowing for lower temperature deposition. By comparison, PECVD has the advantage of being low temperature and highly conformal.

Simplified schematic diagram of a LPCVD.

Simplified schematic diagram of a PECVD reactor

B. CMOS Process Integration 1. Frontend-of-the-Line Integration(FEOL) Generally, FEOL refers to all processes preceding salicidation (i.e., silicide formation). FEOL includes all processes required to fully form isolated CMOS transistors. In the figure below, we see that the FEOL begins with the selection of the starting material (i.e., type of silicon wafer to be used). Then, the shallow trench isolation (STI) module is implemented to form the regions of dielectric between regions of active area. Next, the wells (or tubs) are formed followed by the gate module, which includes all processes to properly define gate electrodes on a thin oxide. Finally, the FEOL concludes with the source/drain module, which includes the processes required for the formation of the low-doped drain extensions and the source/drain regions themselves. a. S h a l l o w T r e n c h I s o l a t i o n Module Shallow trench isolation (STI) is the dominant isolation technology for sub-half micron CMOS technologies. As the name implies, a shallow trench is etched into the surface of the wafer and then filled with a dielectric serving as the FOX. A From a processing perspective, STI is complex; however, it can be implemented with minimal active-area encroachment. Moreover, it has a relatively low thermal budget. The STI module begins with the thermal oxidation of the wafer surface, as shown in Fig. 7.28.

The resultant oxide serves as a film-stress buffer, called a pad oxide, between the silicon and the subsequently deposited iSiyV4 layer. Next, silicon nitride is deposited on the oxidized wafer by LPCVD, as shown in Fig. 7.29. Later, this nitride serves as both an implant mask and a CMP stop-layer.

As shown in Fig. 7.30, the photolithography (mask layer 1) produces the appropriate patterns in photoresist for defining the active areas.

Then, with end-point-detected RIE, the photoresist pattern is transferred into the underlying film stack of nitride and oxide. In Fig. 7.30 notice that the PMOS and NMOS devices will be fabricated on the left side and right side, respectively, under the photoresist. The region cleared of photoresist corresponds to the isolation regions. The 0.4 urn deep silicon trenches are formed by timed RIE with the photoresist softmask present, as shown in Fig 7.31. Although the etching can proceed without the resist, the sidewall profile can be tailored to a specific slope with the presence of the polymer during the etch process. At the cost of reduced packing density, the sloped sidewalls aid in the reduction of leakage current from the parasitic corner transistors.

Following the silicon etch, 02 plasma and wet processing strip the photoresist and etch by-products from the surface of the wafer. At this point, the general structural form of the STI is finished. b. Twin Tub Module CMOS can be implemented in four general forms: n-well, p-well, twinwell (called twin-tub), and triple-well. Following the STI module, the twin-tub

module begins with p-well photolithography (mask layer 2, second use) to generate a resist pattern that covers the PMOS active regions, but exposes the NMOS active areas, as depicted below.

A relatively high energy boron implant is performed into the NMOS active areas. Here the implant is blocked from the PMOS active area. The pad oxide that remained from the STI module now serves as the implant sacrificial oxide for the well implants. It should be pointed out that the p-well may be formed by a composition of several implants at different doses and energies to achieve the desired retrograde profile. Following the p-well implant, the resist is removed using 02 plasma and wet processing, resulting in the structure shown in Fig. 7.40.

Next, a complementary resist pattern is formed using the n-well mask and photolithography (mask layer 3, second use), as seen in Fig. 7.41.

Again, a relatively high energy implant, this time using phosphorus, is performed to generate the n-well. Similar to the p-well, a multitude of implants may be used to achieve the desired retrograde profile. Following the n-well implant, the resist is stripped using 02 plasma and wet processing, yielding the structure in Fig. 7.42. At this point, both the isolation and the wells are fully formed.

Figure 7.43 shows the cross section of the substrate following the twintub module. Notice that the net doping profile is given, thus highlighting both well and wall implants simultaneously. It should be emphasized that the PMOS are fabricated in the n-wells; the NMOS, in the p-wells.

c. Gate Module As depicted in Fig. 7.44, we begin the gate module with the buffered oxide etching of the remaining thin oxide in the active areas from the twin-tub module. Then, a sacrificial oxide is thermally grown. This oxide serves as a threshold adjust implant oxide and a pre-gate oxidation "clean-up."

Next, a blanket (unpattemed), low energy BF2 threshold adjust implant is performed, as shown in Fig. 7.45. This implant allows for the "tuning" of both the PMOS and NMOS threshold voltages. The single boron implant is common for single workfunction gates. However, for dual workfunction gates (common in technologies with minimum gate lengths of 250 nm or less), separate p-type and n-type implants are required for the threshold adjustment in the NMOS and PMOS, respectively.

To form the gate stack (i.e., the gate dielectric and polysilicon gate electrode) the next set of processes are required. Of course, the gate stack provides for the capacitive coupling to the channel. Using wet processing, the sacrificial oxide is stripped from the active areas. As shown in Fig. 7.46, a high quality, thin oxide is thermally grown, which serves as the gate dielectric. In modern CMOS, it is common to use nitrided gate oxide by performing the oxidation in 02 and NO or N20. It can be argued that the gate oxidation is the most critical step in the entire process sequence, as the characteristic of the resultant film greatly determines the behavior of the CMOS transistors.

The gate oxidation is immediately followed by an LPCVD polysilicon deposition, as depicted in Fig. 7.47. For single workfunction gates, the polysilicon can be doped with phosphorous during poly deposition or subsequently implanted. For dual workfunction gates, the NMOS and PMOS can be doped during the n+ and p+ source/drain implants, respectively.

Once the gate stack is formed, the transistor gates and local interconnects are patterned using photolithography (mask layer 4) to generate the appropriate patterns in photoresist, as seen in Fig. 7.48. The gate patterning must be precisely controlled as it determines the gate lengths. Deviations in the resultant physical gate lengths can cause severe performance issues with the CMOS. Seen in Fig. 7.48 are the ideal gate profiles following the RIE of polysihcon and subsequent resist strip.

The gate module concludes with the poly reoxidation as shown in Fig. 7.49. Here the thermal oxidation of the polysihcon and active silicon is performed to (1) grow a buffer pad oxide for the subsequent nitride spacer deposition and (2) electrically activate the implanted dopants in the polysihcon. Notice that since the polysihcon oxidizes at a faster rate than the crystalline silicon, the resultant oxide thickness is greater on the polysihcon than the active silicon.

d. Source/Drain Module At the onset of the source/drain module, the source/drain extensions are formed by a series of processes. Photolithography (mask layer 5) is used to pattern resist such that the NMOS devices are exposed, as shown in Fig. 7.50.

Then, a low energy phosphorus implant is performed to form the nchannel, low doped drain (nLDD) extensions. Notice that the presence of the polysilicon gate inherently leads to the self-alignment of the extensions with respect to the gate. The nLDD suppresses hot carrier injection into the gate and reduces short-channel effects in the NMOS. At this point in the process sequence, a deep boron pocket implant is often used to prevent source/drain punchthrough in the NMOS. The photoresist is stripped. The resultant structure is shown in Fig. 7.51.

In a similar manner, the p-channel source/drain extensions are formed. Photolithography (mask layer 6) is used to protect NMOS devices with resist, as shown in Fig. 7.52. Boron is implanted at low energy to form the p-channel low doped drain (pLDD) extensions. Again, the polysilicon serves to self-align the implant with respect to the gate electrodes. As was the case with the NMOS, it is common to use a deep phosphorus pocket implant to suppress PMOS punchthrough.

Once the photoresist is stripped, the cross-section shown in Fig. 7.53 is achieved. To complete the source/drain extensions, the gate sidewall spacers must be formed prior to the actual source/drain implants.

As shown in Fig. 7.54, conformal silicon nitride is deposited using LPCVD. A CVD oxide may be used in lieu of the nitride.

Following the subsequent nitride etch, this nitride will form the LDD sidewall spacers. The spacers function as (1) a mask to the source/drain implants and (2) a barrier to the subsequent salicide formation. The actual spacers are formed by an unpattemed anisotropic RIE of nitride, as illustrated in Fig. 7.55. The spacer etch is end-pointed on the underlying oxide. Notice that since the nitride is thickest along the polysilicon sidewall, a well-formed insulating region remains on both sides of the polysilicon. This structure is called a spacer.

During the source/drain implants, the combination of the polysilicon and spacers block the implantation, thus allowing for self-alignment to not only the gate but also to the LDD extensions. With this stated, the NMOS source/drains are formed, as shown in Fig. 7.56.

Photolithography (mask layer 5, second use) protects the PMOS with resist while exposing the NMOS. A relatively low energy, high dose arsenic implant is performed to form the n+ regions. The resist is stripped yielding the structure in Fig. 7.57. In addition to the source/drain formation, this implant forms the necessary n+ ohmic contacts. The PMOS source/drains and p+ ohmic contacts are formed in a similar manner.

Photolithography (mask layer 6, second use) and a low energy, high dose BF2 implant is used, as illustrated in Fig. 7.58.

The resist is stripped resulting in the structure shown in Fig. 7.59. The source/drain module concludes with a high temperature anneal that electrically activates the implants and re-crystallizes the damaged silicon. In modern CMOS, the primary reason that polysilicon is chosen as the gate electrode material as opposed to metal is that the poly can withstand the high temperatures required to activate the source/drain implants.

2. Backend-of-the-Line Integration(BEOL) BEOL refers to all processes subsequent to source/drain formation. Hence, BEOL processes are used to "wire" the transistors together using multiple layers of dielectrics and metals. The BEOL begins with the salicidation of the polysilicon and source/drain regions. The remaining BEOL processes proceed in repetitive sets of modules to yield lateral and vertical interconnects isolated from one another with dielectrics. It is important to understand that there is a high degree of interrelationship between unit processes within each module and between modules themselves. A seemingly "trivial" change in one unit process in a given module can have dramatic effects on processes in other modules. In other words, there is no trivial process change. a. Self-Aligned Silicide (Salicide) Module

At the boundary of the FEOL and BEOL is the self-aligned silicide, called salicide, formation. Silicide lowers the sheet resistance of the polysilicon and active silicon regions. The self-aligned silicide (salicide) relies on the fact that metal silicide will generally not form over dielectric materials such as silicon nitride. Therefore, a metal such as titanium or cobalt can be deposited over the entire surface of the wafer, then annealed to selectively form silicide over exposed polysilicon and silicon. Because of the presence of the trench fill and sidewall spacers, the silicide become self-aligned without the need for photopatterning. The salicide module begins with the removal of the thin oxide, present from the FEOL, using buffered HF, as shown in Fig. 7.61.

Next, a refractory metal (e.g., titanium or cobalt) is deposited by sputtering, as depicted in Fig. 7.62. To minimize contamination, a thin layer of TiN is deposited as a cap. A relatively low temperature, nitrogen ambient, rapid thermal annealing (RTA) is used to react titanium (or cobalt) with the silicon, forming TiSi2 (C49 phase) or (CoSix). The resultant silicide (i.e., C49) is a high resistivity phase. Also, notice that the underlying nitride and oxide serves to block the formation of the silicide from the sidewalls and trenches, respectively.

To prevent spacer overgrowth of the silicide, the low resistivity phase is achieved by processing with two separate anneals. The first, as described above, forms the high resistivity phase without the risk of silicide formation on the nitride. The second, as described below, occurs following the wet chemical etching of the unreacted titanium (or cobalt) using a higher temperature, which causes a phase change (C49 to C54 for TiSi2) with a much lower resistivity. If one high temperature anneal was originally performed to achieve the low resistivity phase, then significant overgrowth could occur, leading to leakage current from the source and drain to the gate of the transistors.

To continue the salicide module, following the first anneal, the unreacted titanium (or cobalt) is wet chemically etched from the wafer. The second RTA, in argon ambient at a slightly higher temperature, achieves the low resistivity phase, as shown in Fig. 7.63. b. Pre-Metal Dielectric The pre-metal dielectric (PMD) provides electrical isolation between metal 1 and polysilicon/silicon. To aid the subsequent contact etch process, a thin layer of silicon nitride is deposited as an etch stop. This is followed by a high density plasma deposition of the PMD oxide, as shown in Fig. 7.64.

The resultant surface of the PMD must be planarized to allow for improved depth-of-focus for the subsequent high resolution photopatteming of metal 1. With CMP, the PMD is planarized, producing the ross-section shown in Fig. 7.65.

c. Contact Module The contacts provide the electrical coupling between metal 1 and polysilicon/silicon. The first BEOL photolithography (mask layer 7) step patterns contact openings in the resist. The PMD and nitride is then dry etched using the nitride as an etch-stop layer. The resist is stripped from the wafer, resulting in the structure shown in Fig. 7.66. Contact openings to the source and drains are

shown; however, contacts to polysilicon (not shown) over field oxide are simultaneously formed.

Next, a thin layer of titanium is deposited by ionized metal plasma (IMP) sputtering, preceded by an in-situ argon sputter etch to clean the bottom of the high aspect ratio contact openings. The titanium is the first component of the contact liner and functions to chemically reduce oxides at the bottom of the contacts. The second component of the liner is a thin CVD TiN. The primary purpose of this layer is to act as a diffusion barrier to the fluorine (which readily etches silicon) used in the subsequent tungsten deposition. The contact openings are filled (actually overfilled) with tungsten using a WF6 CVD process, as shown in Fig. 7.67

As depicted in Fig. 7.68, the overfilled tungsten is polished back to the top of the planarized PMD using CMP. At this point, the surface of the wafer is ultra-smooth and essentially free of all topography.

To aid the photolithographic alignment of the metal layer to the contacts, a tungsten recess etch is performed to provide adequate alignment reference. The recessed contacts are shown in Fig. 7.69.

d. Metallization 1 To allow for electrical signal transmission from contact-to-contact and from contactto- vial, defined metallization must be formed. Following the recess etch, sputtering is used to deposit a film stack consisting of Ti/TiN/Al/TiN, as seen in Fig. 7.70. The Ti provides adhesion of the TiN and reduction in electromigration problems. The bottom TiN serves primarily as a diffusion barrier to TiAl3 formation. The topmost TiN acts as an anti- reflective coating for the metal photolithography as well as an etch stop for the subsequent via formation.

Using photolithography (mask layer 8), the metal 1 pattern in resist is generated, as depicted in Fig. 7.71. A dry metal etch transfers the pattern into the metal. To prevent metal corrosion, the resist is plasma stripped in an 02/N2/H20 ambient, producing the cross-section shown in Fig. 7.71.

e. Intra-Metal Dielectric 1 Deposition The intra-metal dielectric 1 (IMDl) provides the electrical isolation between metal1 and metal2. It is common to deposit this film using high density plasma CVD, as shown in Fig. 7.72. As can be seen, the conformal deposition results in a surface topography that must be planarized by CMP. The depth-offocus is improved for the subsequent photolithographic steps as it is for the PMD planarization.

f.

Via 1 Module Electrical coupling between metall and metal2 is achieved by the vial module. The planarized IMD is photolithographically defined (mask layer 9), and an RIE opens the vias. The resist is stripped using 02 plasma and wet processing, producing the cross-section shown in Fig. 7.73.

Next, similar to the contact fill, an argon sputter etch is performed followed by the deposition of thin layers of IMP titanium and CVD TiN. Using a WF6 CVD process, the vias are deposited (overfilled), as seen in Fig. 7.74.

The excess tungsten is removed by CMP utilizing the IMDl as a "polish stop," as depicted in Fig. 7.75. Again, as to provide observable alignment features, a tungsten recess etch is often required (also shown in Fig. 7.75).

g. Metallization 2 In a similar manner as the metal 1 process, the metal 2 stack is deposited (Fig. 7.76) and photolithographically (mask layer 10) defined, as shown in Fig. 7.77. Note that we are not discussing metal implementation using copper. Copper wiring is often implemented with dual-Damascene techniques, where both vias and metal layers are simultaneously formed in a series of process steps.

h. Additional Metal/Dielectric Layers At this point, additional tiers of dielectric/metal layers can be formed by replicating the aforementioned processes. In modern CMOS there may be more than eight metal layers. It should be noted that as dielectric/metal layers are added, the cumulative film stresses can cause significant bow/warp in the wafers. Hence, great effort is expended to minimize the stresses in the BEOL films. i. Final Passivation To protect the CMOS from mechanical abrasion during probe and packaging and to provide a barrier to contaminants (e.g., H20, ionic salts), a final passivation layer must be deposited. The passivation type is determined in large part by the type of package in which the CMOS IC will be placed. Common passivation layers are (1) doped glass and (2) silicon nitride on deposited oxide. Figure 7.78 shows the cross-section of our CMOS process flow following the deposition of the passivation.

Finally, the bond pads are opened using photolithography (mask layer n) and by dry etching the passivation. Following photoresist strip, the final CMOS cross-section is shown in Fig. 7.79.

3. Backend Processes Following completion of the final passivation, the wafers are removed from the cleanroom in preparation for a series of backend (i.e., post-fab) processes. These processes include wafer probe, die separation, packaging, and final test/burn-in. a. Wafer Probe Generally, dedicated die with parametric structures and devices are stepped into various positions of the wafer. Alternatively, parametric structures are placed in the dividing regions, called streets or scribe lines, between die. Electrical characterization of these parametric structures and devices is often performed at select points in the fabrication process flow (such as following metal 1 patterning). Parameters such as contact resistance, sheet resistance, transistor threshold voltage, saturated drain current, off-current, sub-threshold slope, etc., are measured. If problems are observed from the in-line parametric tests, troubleshooting can begin sooner than if the testing were only performed following final passivation. Furthermore, wafers that do not meet the parametric standards can be removed (or "killed") from the fabrication sequence (and thus money is saved).

After the completed wafers are removed from the fab, wafer-level probing is performed to check final device parameters and to check CMOS integrated circuit functionality and performance. Wafer probe is accomplished by using sophisticated testers that can probe individual die (or sets of die) and apply test vectors to determine circuit behavior, bievitablity, there are a percentage of die that will not pass all the vector sets and thus are considered failed die. The ratio of good die-to-total die represents the wafer yield given by

In these cases, the die are marked, often with an ink dot, to indicate a nonfunctional circuit. Since the processing costs of a wafer are fixed, higher yield equates to higher profit. b. Die Separation Prior to separating the individual die, the backs of the wafers are often thinned using a lapping process similar to the CMP process discussed in Sec. 7.1. This thinning is often required for specific types of packages. Furthermore, thinning can aid in improving the removal of heat from the CMOS circuits. Next, the die are separated from the wafers using a dicing saw comprised of a diamond-coated blade. The cutting paths are aligned to the streets or scribe lines on the wafer. Great care is given to minimize damage to the die during this mechanical separation. Along with the inked die, die that are observed to be damaged from the dicing are discarded. Obviously, the separation process can reduce the yield. c. Packaging The good die are now attached to a header in the appropriate package type. The die attach can be accomplished by either eutectic or epoxy attachment. Next, the bond pads are wired to the leads of the package. Common wire bonding techniques include thermocompression, thermosonic, and ultrasonic bonding. At this point, the packaging is completed by a wide range of different processes, greatly dependent on the type of package in which the IC resides. For instance, in plastic dual in-line packages (DIPs), a process similar to injection molding is performed to form a relatively inexpensive package. If ceramic packaging is required, then the attached, wire bonded die will reside in a cavity that is sealed by a metal lid. In general, plastic (or epoxy) packages are inexpensive, but do not provide a hermetic seal. On the contrary, ceramic packages are more costly, but do provide a hermetic seal. For information on other packaging schemes, the reader is referred to the list of additional reading at the end of the chapter. Finally, it should be noted that the packaging process can add to the overall yield loss. d. Final Test and Burn-In Once packaged, the CMOS parts are tested for final functionality and performance. When this is completed, it is common for the parts to go through a burn-in step. Here they are operated at extreme temperatures and voltages to weed out infant failures. Additional yield loss can be observed.

III. SUMMARY and CONCLUSION A CMOS (complementary MOSFET) employs a unique combination of a p-channel and n-channel MOSFET with a single set of external leads. It has the advantages of a very high input impedance, fast switching speeds and low operating power levels, all of which make it as a useful logic circuit. An integrated circuit process is usually a structured sequence of operations such as the ability to deposit/modify thin films on the substrate, to apply a patterned mask on the films by photolithographic process, and to etch the films selectively to form actual devices. Semiconductor devices and circuits are formed in thin slices of a material (called a wafer) that servers as the substrate. For proper operation of the device/circuit, the substrate material must have crystalline structure where all the atoms are aligned in a specific pattern. One of the basic building blocks in integrated circuit processing is the ability to deposit thin films of material. A large number of deposited films by wide variety of techniques are used in integrated circuits. These films can either be grown on semiconductor or deposited by various techniques. Most films can be formed by more than one method. Thermal Oxidation of Silicon is taken up first because it is an important step which is often repeated throughout the IC fabrication. This is followed by other principal film deposition techniques such as vacuum evaporation, sputtering and chemical vapor deposition. The properties of the films or substrate can be modified by process like diffusion and ion implantation and they enables to form a variety of devices in integrated circuits. The oxide of silicon, or silicon dioxide (SiO 2), is one of the most important ingredients in integrated circuits. Thermal SiO2 is amorphous. It has a density of 2.2 gm/cm3 and molecular density of 2.3x1022 molecules/cm3 . The crystalline SiO2 known as Quartz has a density of 2.65 gm/cm3. SiO2 has excellent properties which makes them necessary in every part of the integrated circuits. Etching is a process that removes unwanted materials from the surface of a substrate by various dry and wet techniques. These techniques are used to remove silicon dioxide, silicon nitride, polysilicon, aluminum, tungsten, contamination particles, and other layer materials. This process step creates the layer definition that is based on the outcome of a previous photolithography process step. These etch processes transform a single layer of semiconductor material into the patterns, features, lines, and interconnects. Following completion of the final passivation, the wafers are removed from the cleanroom in preparation for a series of backend (i.e., post-fab) processes. These processes include wafer probe, die separation, packaging, and final test/burn-in.

IV. BIBLIOGRAPHY CMOS Circuit Design, Layout and Simulation, R. Jacob Baker http://lsmwww.epfl.ch/Education/former/2002-2003/VLSIDesign/ch02/ch02.html

Republic of the Philippines Polytechnic University of the Philippines COLLEGE OF ENGINEERING ELECTRONICS AND COMMUNICATIONS ENGINEERING DEPARTMENT 3rd floor, CEA Bldg. Anonas St. cor. Pureza St. NDC Compound, Sta. Mesa, Manila

ECEN 3253 MICROPROCESSOR SYSTEM

GROUP ACTIVITY I: CMOS FABRICATION (Research)

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