REPORTLAB3 Ee271

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Extra Lab - Student Shop Group 10 : Nguyn nh Minh Nht-Trng Minh Quc-Ng Nh Tr
REPORT EXTRA LAB EE 271
GROUP 10 Nguyn nh Minh Nht Trng Minh Quc Ng Nh Tr
OUTLINE
I. LAB REQUIREMENTS AND THE SOLUTION II. SYSTEM DESIGN III. CODE AND SIMULATION IV. CONCLUSIONS
I.
LAB REQUIREMENTS AND THE SOLUTION
In this laboratory, we are required to design a system that displays the code of the items in the 7 segments decoders as well as displays on sale? and expensive? states of yes or no of th ese items in both 7 segments decoders and Red LEDs. The input of this systems is controlled by 3 switches, whose on, off states demonstrates the binary UPC code of items. The on sale LEDR*1+ and expensive LEDR*0+ display as same as the on sale and expensive 7 segments decoders, respectively.
The outputs display has to follow the table:
SOLUTION FOR THE LAB REQUIREMENTS

For this problem, we suggest that the item should be solved independently, one after another, that is for each case of input items, we write the code for 7 segments decoders to display the item codes ( for 7 segments decoders no.1 and no.2) and on sale?, expensive? states ( for 7 segments decoders no.3 and no.4). If the input UPC code is not found in the above table, system would display nothing. For example, if the input is 001, that is Spring Shoes, the code is as follow: case (x) 3'b001: begin // 2 first 7 segments decoders display item code LedOut1 = 7'b0001000; // display letter A LedOut2 = 7'b1001111; // display number 1 // 3rd 7 segments decoders display yes no state of on sale? LedOut3 = 7'b1111111; // display nothing meaning no // 4th 7 segments decoders display yes no state of expensive? LedOut4 = 7'b0000000; // display 8 meaning yes // 2 red LED display as the same as 7 segments decoders 3rd and 4th, respectively LEDR[0] = 0; LEDR[1] = 1; end
We have the table ruling the outputs display: x ( input ) LedOut1 (code letter) 1111111 0001000 1111111 0000000 0110001 0001000 0111000 0110001 LedOut2 LedOut3 (code number) (on sale? state) 1111111 1111111 1001111 1111111 1111111 1111111 0000110 1111111 0100100 0000000 0000100 1111111 0010010 0000000 0000000 0000000 LedOut4 (expensive? state 1111111 0000000 1111111 1111111 1111111 0000000 0000000 1111111 LEDR[0] LEDR[1]
000 001 010 011 100 101 110 111
0 1 0 0 0 1 1 0
0 0 0 0 1 0 1 1
II.
SYSTEM DESIGN
LedOut1 (7 bits) LedOut2 (7 bits) x (3 bit) STUDENT SHOP LedOut2 (7 bits) LedOut2 (7 bits) LEDR (2 bits)
III.
CODE AND SIMULATION
VERILOG CODE
module StudentShop(LedOut1, LedOut2, LedOut3, LedOut4, LEDR, x); output reg [0:6] LedOut1; output reg [0:6] LedOut2; output reg [0:6] LedOut3; output reg [0:6] LedOut4; output reg [0:1] LEDR; input [0:2] x; always @(x) case (x) 3'b001: begin LedOut1 LedOut2 LedOut3 LedOut4 LEDR[1] LEDR[0] end 3'b011: begin LedOut1 = 7'b0000000; LedOut2 = 7'b0000110; LedOut3 = 7'b1111111; LedOut4 = 7'b1111111; LEDR[1]= 0; LEDR[0] = 0; end 3'b100: begin LedOut1 LedOut2 LedOut3 LedOut4 LEDR[1] LEDR[0] end 3'b101: begin LedOut1 LedOut2 LedOut3 LedOut4 LEDR[1] LEDR[0] end 3'b110: begin LedOut1 = 7'b0111000; LedOut2 = 7'b0010010; = = = = = = 7'b0001000; 7'b0000100; 7'b1111111; 7'b0000000; 0; 1; = = = = = = 7'b0110001; 7'b0100100; 7'b0000000; 7'b1111111; 1; 0; = = = = = = 7'b0001000; 7'b1001111; 7'b1111111; 7'b0000000; 0; 1;
Extra Lab - Student Shop Group 10 : Nguyn nh Minh Nht-Trng Minh Quc-Ng Nh Tr LedOut3 LedOut4 LEDR[1] LEDR[0] end 3'b111: begin LedOut1 LedOut2 LedOut3 LedOut4 LEDR[1] LEDR[0] end default: begin LedOut1 = LedOut2 = LedOut3 = LedOut4 = LEDR[1] = LEDR[0] = end endcase endmodule 7'b 7'b 7'b 7'b 0; 0; 1111111; 1111111; 1111111; 1111111; //1 //1 //1 //1 = = = = = = 7'b0110001; 7'b0000000; 7'b0000000; 7'b1111111; 1; 0; = = = = 7'b0000000; 7'b0000000; 1; 1;
TEST BENCH CODE

module studentshop_tb; wire [0:6] LedOut1_tb; wire [0:6] LedOut2_tb; wire [0:6] LedOut3_tb; wire [0:6] LedOut4_tb; wire LedR1_tb, LedR2_tb; reg [0:2] x_tb; StudentShop dut (LedOut1_tb, LedOut2_tb, LedOut3_tb, LedOut4_tb, LedR1_tb, LedR2_tb, x_tb); initial begin $dumpvars(1, dut); $dumpfile("studentshop_tb.vcd"); end initial begin x_tb = 3'b000; #25 x_tb = 3'b001; #25 x_tb = 3'b010; #25 x_tb = 3'b011; #25 x_tb = 3'b100; #25 x_tb = 3'b101; #25 x_tb = 3'b110; #25 x_tb = 3'b111; $finish; end endmodule
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WAVEFORM:
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COMMENTS:
The simulation is as we expect. For example, when the input is 011, the LedOut1 is 0000000 ( that is letter B ), the LedOut2 is 0000110 ( that is number 3 ), the LedOut3 is 1111111 ( nothing, means no ), the LedOut3 is 1111111(nothing, means no ), LEDR[0] and LEDR[1] are both 0.
The real result when we run the system in the FPGA KIT is the same as simulation.
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IV.
CONCLUSIONS

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REPORT EXTRA LAB EE 271

GROUP 10 Nguyn nh Minh Nht Trng Minh Quc Ng Nh Tr

LAB REQUIREMENTS AND THE SOLUTION

The outputs display has to follow the table:

SOLUTION FOR THE LAB REQUIREMENTS

000 001 010 011 100 101 110 111

CODE AND SIMULATION

TEST BENCH CODE

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