Triac bt137 600

DL137/D Rev.
7, May-2000
Thyristor Device Data

TRIACs, SCRs, Surge Suppressors, and Triggers
ON Semiconductor
Thyristor Device Data

TRIACs, SCRs, Surge Suppressors, and Triggers
DL137/D Rev. 7, May2000
SCILLC, 2000 Previous Edition 1995 All Rights Reserved
This edition of the Thyristor Data Manual has been revised extensively to reflect our current product portfolio and to incorporate new products and corrections to existing data sheets. An expanded index is intended to help the reader find information about a variety of subject material in the sections on Theory and Applications. Although information in this book has been carefully checked, no responsibility for inaccuracies can be assumed by ON Semiconductor. Please consult your nearest ON Semiconductor sales office for further assistance regarding any aspect of ON Semiconductor Thyristor products.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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ON SEMICONDUCTOR DEVICE CLASSIFICATIONS

In an effort to provide uptodate information to the customer regarding the status of any given device, ON Semiconductor has classified all devices into three categories: Preferred devices, Current products and Not Recommended for New Design products. A Preferred type is a device which is recommended as a first choice for future use. These devices are preferred by virtue of their performance, price, functionality, or combination of attributes which offer the overall best value to the customer. This category contains both advanced and mature devices which will remain available for the foreseeable future. Preferred devices are denoted below the device part numbers on the individual data sheets. Device types identified as current may not be a first choice for new designs, but will continue to be available because of the popularity and/or standardization or volume usage in current production designs. These products can be acceptable for new designs but the preferred types are considered better alternatives for long term usage. Any device that has not been identified as a preferred device is a current device. This data book does not contain any Not Recommended for New Design devices.
ICePAK, POWERTAP, Thermopad, Thermowatt, and Unibloc are trademarks of Semiconductor Components Industries, LLC (SCILLC). Cho-Therm is a registered trademark of Chromerics, Inc. Grafoil is a registered trademark of Union Carbide Rubber-Duc is a trademark of AAVID Engineering Sil Pad and Thermal Clad are trademarks of the Bergquist Company. Sync-Nut is a trademark of ITW Shakeproof Thermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc. Kapton and Teflon are registered trademarks of du Pont de Nemours & Co., Inc.
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
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ABOUT THIS REVISION 7 . . .

What can quickly identify engineers as Thyristor knowledgeable is them knowing the K lead designator on the case outlines and packages identifies the cathode on SCRs. In this revision 7 of the Thyristor data book, a lot has changed. ON Semiconductor ON Semiconductor is one of the worlds largest suppliers of analog, standard logic, and discrete semiconductors for data and power management, with shipments of approximately 19 billion units and net product revenue of over US $1.6 billion (pro forma) in 1999. ON Semiconductors products include integrated circuits for highbandwidth data applications, analog ICs for power management and lowvoltage power transistors. In addition to using micropackaging technology across all product families, ON Semiconductor offers the largest selection of discrete semiconductors in a variety of surface mount and standard packages. These semiconductors turn on and connect digital electronic products to our world. ON Semiconductor is the tradename of SCG Holding Corporation. Altogether we have over 30 years experience in manufacturing Thyristors. Updated Data Book Although some very successful older data sheets have been around in previous revisions of the Thyristor data book, all have been revised if only to make minor corrections and format changes. Over two dozen new data sheets have been added to the revision 7 data book that were not in the previous edition. In particular we are proud of our series of high performance, new generation thyristors. We now have a larger selection of device types with high noise immunity and also a larger number of sensitive gate triacs and SCRs. In addition, there is the new line of MMT surge protection series for telecom systems. Finally, a total of six new application notes were added to this book. To find a complete list of the new material in the revision 7 data book please see the page title Whats Different in the Rev. 7 Data Book near the front of this book. Safety Regulatory Approval For the first time in the Thyristor data book we included the UL safety regulatory registration file number on the data sheets. UL approval registrations include the fullpack package for isolation, along with the UL approvals for both SIDACs and our new line of Thyristor Surge Protective Devices (TSPD), the two MMT series that is now included in the revision 7 Thyristor data book. WEB Site Naturally it is impossible to keep a data book completely current. We encourage customers to visit our ON Semiconductor Thyristor web site at http://onsemi.com for the latest information and data sheet releases. Thank you for your support, Contributors and Editors
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WHATS DIFFERENT IN THE REV. 7 DATA BOOK?
DATA SHEET ADDITIONS (From Rev. 6 Data Book) 2N6394 Series 2N6400 Series MAC4DCM, MAC4DCN MAC4DHM MAC4DLM MAC4DSM, MAC4DSN MAC4M, MAC4N MAC4SM, MAC4SN MAC8SD, MAC8SM, MAC8SN MAC12HCD, MAC12HCM, MAC12HCN MAC12SM, MAC12SN MAC15SD, MAC15SM, MAC15SN MAC16CD, MAC16CM, MAC16CN MAC16HCD, MAC16HCM, MAC16HCN MAC997 Series MCR8DCM, MCR8DCN MCR8DSM, MCR8DSN MCR12DCM, MCR12DCN MCR12DSM, MCR12DSN MCR12LD, MCR12LM, MCR12LN MCR682 MCR692, MCR693 MCR716, MCR718 MMT05B230T3, MMT05B260T3, MMT05B310T3 MMT10B230T3, MMT10B260T3, MMT10B310T3
NEW PRODUCT LITERATURE ADDITIONS (From Rev. 6 Data Book) AND8005 AND8006 AND8007 AND8008 AND8015 AND8017
DATA SHEET DELETIONS (From Rev. 6 Data Book) 2N623741 BRX4449 BRY5530 Series MAC218, A Series MAC228AFP, FP Series MAC229, A Series MAC310, A Series MAC321 Series MCR102103 MCR310 Series MCR506 Series S2800 Series T2323 MBS4991 Series MMT10V275 Series
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THYRISTOR PART NUMBER PREFIX*
DEVICE PREFIX 2N5060 Series 2N6027, 2N6028 2N6071A Series 2N6344, 49 2N6344A, 48A, 49A 2N6394 Series 2N6400 Series 2N6504 Series C106X & C122X MACXXXX MCRXXXX MKPXXXX MMTXXXX TXXXX
DEVICE DESCRIPTION Silicon Controlled Rectifiers (SCR) Programmable Unijunction Transistor (PUT) Triacs
Silicon Controlled Rectifiers (SCR)
Silicon Controlled Rectifiers (SCR) Triacs Silicon Controlled Rectifiers (SCR) Sidacs: High Voltage Bidirectional Triggers Thyristor Surge Protective Devices (TSPD) Triacs
*2N Devices JEDEC Registered Series
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Table of Contents
Chapter 1: Theory and Applications

(Sections 1 thru 9)
Page Section 1: Symbols and Terminology . . . . . . . . . . . . . 11 Section 2: Theory of Thyristor Operation . . . . . . . . . 17 Basic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 20 False Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Theory of SCR Power Control . . . . . . . . . . . . . . . . . . 23 Triac Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Methods of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Zero Point Switching Techniques . . . . . . . . . . . . . . . . 32 Section 3: Thyristor Drivers and Triggering . . . . . . . 36 Pulse Triggering of SCRs . . . . . . . . . . . . . . . . . . . . . . 36 Effect of Temperature, Voltage and Loads . . . . . . . . 40 Using Negative Bias and Shunting . . . . . . . . . . . . . . 42 Snubbing Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Using Sensitive Gate SCRs . . . . . . . . . . . . . . . . . . . . 47 Drivers: Programmable Unijunction Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Section 4: The SIDAC, A New High Voltage Bilateral Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Section 5: SCR Characteristics . . . . . . . . . . . . . . . . . . 67 SCR TurnOff Characteristics . . . . . . . . . . . . . . . . . . 67 SCR TurnOff Mechanism . . . . . . . . . . . . . . . . . . . . . 67 SCR TurnOff Time tq . . . . . . . . . . . . . . . . . . . . . . . . . 67 Parameters Affecting tq . . . . . . . . . . . . . . . . . . . . . . . . 72 Characterizing SCRs for Crowbar Applications . . . . 78 Switches as LineType Modulators . . . . . . . . . . . . . . 86 Parallel Connected SCRs . . . . . . . . . . . . . . . . . . . . . . 92 RFI Suppression in Thyristor Circuits . . . . . . . . . . . . 96 Section 6: Applications . . . . . . . . . . . . . . . . . . . . . . . . 100 Phase Control with Thyristors . . . . . . . . . . . . . . . . . 100 Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Phase Control with Trigger Devices . . . . . . . . . . . . 109 Cycle Control with Optically Isolated Triac Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 AC Power Control with SolidState Relays . . . . . . 117 Triacs and Inductive Loads . . . . . . . . . . . . . . . . . . . . 121 Inverse Parallel SCRs for Power Control . . . . . . . . 124 Interfacing Digital Circuits to Thyristor Controlled AC Loads . . . . . . . . . . . . . . . . . . . . . . . . 125 DC Motor Control with Thyristors . . . . . . . . . . . . . . . 134 Programmable Unijunction Transistor (PUT) Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Triac ZeroPoint Switch Applications . . . . . . . . . . . 143 AN1045 Series Triacs in AC High Voltage Switching Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 AN1048 RC Snubber Networks for Thyristor Power Control and Transient Suppression . . . . . . . 159 AND8005 Automatic AC Line Voltage Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Page Section 6: Applications (continued) AND8006 Electronic Starter for Flourescent Lamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 AND8007 Momentary Solid State Switch for Split Phase Motors . . . . . . . . . . . . . . . . . . . . . . . . 188 AND8008 Solid State Control Solutions for Three Phase 1 HP Motor . . . . . . . . . . . . . . . . . . . 193 AND8015 Long Life Incandescent Lamps using SIDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 AND8017 Solid State Control for BiDirectional Motors . . . . . . . . . . . . . . . . . . . . . . . . . 205 Section 7: Mounting Techniques for Thyristors . . 208 Mounting Surface Considerations . . . . . . . . . . . . . . 209 Thermal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Insulation Considerations . . . . . . . . . . . . . . . . . . . . . 211 Fastening Techniques . . . . . . . . . . . . . . . . . . . . . . . . 216 Insulated Packages . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Surface Mount Devices . . . . . . . . . . . . . . . . . . . . . . . 219 Thermal System Evaluation . . . . . . . . . . . . . . . . . . . 221 Section 8: Reliability and Quality . . . . . . . . . . . . . . . 225 Using Transient Thermal Resistance Data in High Power Pulsed Thyristor Applications . . . . . . 225 Thyristor Construction . . . . . . . . . . . . . . . . . . . . . . . . 237 InProcess Controls and Inspections . . . . . . . . . . . 237 Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Stress Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Environmental Testing . . . . . . . . . . . . . . . . . . . . . . . . 240 Section 9: Appendices . . . . . . . . . . . . . . . . . . . . . . . . . 241
Chapter 2: Selector Guide

SCRs: Silicon Controlled Rectifiers . . . . . . . . . . . . . . . 249 TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Surge Suppressors and Triggers . . . . . . . . . . . . . . . . . 256
Chapter 3: Data Sheets

2N5060 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2N6027, 2N6028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2N6071A/B Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2N6344, 2N6349 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2N6344A, 2N6348A, 2N6349A . . . . . . . . . . . . . . . . . . . . 2N6394 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2N6400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2N6504 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C106 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C122F1, C122B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC08BT1, MAC08MT1 . . . . . . . . . . . . . . . . . . . . . . . . . MAC4DCM, MAC4DCN . . . . . . . . . . . . . . . . . . . . . . . . . . MAC4DHM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 265 272 278 283 288 293 298 303 308 311 320 328
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Table of Contents (continued)
Chapter 3: Data Sheets (continued)

Page MAC4DLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 MAC4DSM, MAC4DSN . . . . . . . . . . . . . . . . . . . . . . . . . . 340 MAC4M, MAC4N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 MAC4SM, MAC4SN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 MAC8D, MAC8M, MAC8N . . . . . . . . . . . . . . . . . . . . . . . . 358 MAC8SD, MAC8SM, MAC8SN . . . . . . . . . . . . . . . . . . . . 363 MAC9D, MAC9M, MAC9N . . . . . . . . . . . . . . . . . . . . . . . . 369 MAC12D, MAC12M, MAC12N . . . . . . . . . . . . . . . . . . . . 374 MAC12HCD, MAC12HCM, MAC12HCN . . . . . . . . . . . . 379 MAC12SM, MAC12SN . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 MAC15 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 MAC15A6FP, MAC15A8FP, MAC15A10FP . . . . . . . . . 394 MAC15M, MAC15N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 MAC15SD, MAC15SM, MAC15SN . . . . . . . . . . . . . . . . 404 MAC16CD, MAC16CM, MAC16CN . . . . . . . . . . . . . . . . 410 MAC16D, MAC16M, MAC16N . . . . . . . . . . . . . . . . . . . . 415 MAC16HCD, MAC16HCM, MAC16HCN . . . . . . . . . . . . 420 MAC97 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 MAC210A8, MAC210A10 . . . . . . . . . . . . . . . . . . . . . . . . . 433 MAC210A8FP, MAC210A10FP . . . . . . . . . . . . . . . . . . . . 438 MAC212A6FP, MAC212A8FP, MAC212A10FP . . . . . . 443 MAC212A8, MAC212A10 . . . . . . . . . . . . . . . . . . . . . . . . . 448 MAC218A6FP, MAC218A10FP . . . . . . . . . . . . . . . . . . . . 453 MAC223A6, MAC223A8, MAC223A10 . . . . . . . . . . . . . 457 MAC223A6FP, MAC223A8FP, MAC223A10FP . . . . . . 461 MAC224A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 MAC228A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 MAC229A8FP, MAC229A10FP . . . . . . . . . . . . . . . . . . . . 474 MAC320A8FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 MAC997 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 MCR08B, MCR08M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 MCR8DCM, MCR8DCN . . . . . . . . . . . . . . . . . . . . . . . . . . 499 MCR8DSM, MCR8DSN . . . . . . . . . . . . . . . . . . . . . . . . . . 504 MCR8M, MCR8N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 MCR8SD, MCR8SM, MCR8SN . . . . . . . . . . . . . . . . . . . 514 MCR12D, MCR12M, MCR12N . . . . . . . . . . . . . . . . . . . . 518 MCR12DCM, MCR12DCN . . . . . . . . . . . . . . . . . . . . . . . . 522 MCR12DSM, MCR12DSN . . . . . . . . . . . . . . . . . . . . . . . . 528 MCR12LD, MCR12LM, MCR12LN . . . . . . . . . . . . . . . . . 534 MCR16N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 MCR226, MCR228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 MCR25D, MCR25M, MCR25N . . . . . . . . . . . . . . . . . . . . 550 Page MCR682 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 MCR692, MCR693 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 MCR723, MCR726, MCR728 . . . . . . . . . . . . . . . . . . 563 MCR100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 MCR1066, MCR1068 . . . . . . . . . . . . . . . . . . . . . . . . . . 572 MCR2182, MCR2184, MCR2186 . . . . . . . . . . . . . . . 575 MCR2186FP, MCR21810FP . . . . . . . . . . . . . . . . . . . . 579 MCR2258FP, MCR22510FP . . . . . . . . . . . . . . . . . . . . 584 MCR2644, MCR2646, MCR2648 . . . . . . . . . . . . . . . 589 MCR2654 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 MCR703A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 MCR716, MCR718 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 MKP1V120 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 MKP3V120, MKP3V240 . . . . . . . . . . . . . . . . . . . . . . . . . . 611 MMT05B230T3, MMT05B260T3, MMT05B310T3 . . . . 615 MMT10B230T3, MMT10B260T3, MMT10B310T3 . . . . 621 T2322B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 T2500D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 T2800D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Chapter 4: Surface Mounting Guide Package Information and Tape and Reel Specifications
Information for Using Surface Mount Thyristors . . . . . Tape and Reel Packaging Specifications . . . . . . . . . . . Surface Mount (DPAK, SMB, SOT223) . . . . . . . . AxialLead (DO41, Surmetic 50) . . . . . . . . . . . . . . TO92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 641 641 644 645
Chapter 5: Outline Dimensions and Leadform Options

Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Leadform Options TO225AA (Case 77) . . . . . . . . . . . . . . . . . . . . . . . . 654 TO220 (Case 221A) . . . . . . . . . . . . . . . . . . . . . . . . . 655
Chapter 6: Index and Cross Reference

Index and Cross Reference . . . . . . . . . . . . . . . . . . . . . . 657
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ABOUT THYRISTORS
Thyristors can take many forms, but they have certain things in common. All of them are solid state switches which act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become lowimpedance current paths and remain in that condition until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. Silicon controlled rectifiers (SCRs) and triacs are both members of the thyristor family. SCRs are unidirectional devices where triacs are bidirectional. An SCR is designed to switch load current in one direction, while a triac is designed to conduct load current in either direction. Structurally, all thyristors consist of several alternating layers of opposite P and N silicon, with the exact structure varying with the particular kind of device. The load is applied across the multiple junctions and the trigger current is injected at one of them. The trigger current allows the load current to flow through the device, setting up a regenerative action which keeps the current flowing even after the trigger is removed. These characteristics make thyristors extremely useful in control applications. Compared to a mechanical switch, a thyristor has a very long service life and very fast turn on and turn off times. Because of their fast reaction times, regenerative action and low resistance once triggered, thyristors are useful as power controllers and transient overvoltage protectors, as well as simply turning devices on and off. Thyristors are used in motor controls,
incandescent lights, home appliances, cameras, office equipment, programmable logic controls, ground fault interrupters, dimmer switches, power tools, telecommunication equipment, power supplies, timers, capacitor discharge ignitors, engine ignition systems, and many other kinds of equipment. Although thyristors of all sorts are generally rugged, there are several points to keep in mind when designing circuits using them. One of the most important is to respect the devices rated limits on rate of change of voltage and current (dv/dt and di/dt). If these are exceeded, the thyristor may be damaged or destroyed. On the other hand, it is important to provide a trigger pulse large enough and fast enough to turn the gate on quickly and completely. Usually the gate trigger current should be at least 50 percent greater than the maximum rated gate trigger current. Thyristors may be driven in many different ways, including directly from transistors or logic families, power control integrated circuits, by optoisolated triac drivers, programmable unijunction transistors (PUTs) and SIDACs. These and other design considerations are covered in this manual. Of interest too, is a new line of Thyristor Surge Suppressors in the surface mount SMB package covering surge currents of 50 and 100 amps, with breakover voltages from 265 to 365 volts. These Thyristor Surge Protection devices prevent overvoltage damage to sensitive circuits by lightening, induction, and power line crossing. They are breakover triggered crowbar protectors with turn off occurring when the surge current falls below the holding current value.
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CHAPTER 1 Theory and Applications

Sections 1 thru 9
Page Section 1: Symbols and Terminology . . . . . . . . . . . . . 11 Section 2: Theory of Thyristor Operation . . . . . . . . . 17 Basic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 20 False Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Theory of SCR Power Control . . . . . . . . . . . . . . . . . . 23 Triac Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Methods of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Zero Point Switching Techniques . . . . . . . . . . . . . . . . 32 Section 3: Thyristor Drivers and Triggering . . . . . . . 36 Pulse Triggering of SCRs . . . . . . . . . . . . . . . . . . . . . . 36 Effect of Temperature, Voltage and Loads . . . . . . . . 40 Using Negative Bias and Shunting . . . . . . . . . . . . . . 42 Snubbing Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Using Sensitive Gate SCRs . . . . . . . . . . . . . . . . . . . . 47 Drivers: Programmable Unijunction Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Section 4: The SIDAC, A New High Voltage Bilateral Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Section 5: SCR Characteristics . . . . . . . . . . . . . . . . . . 67 SCR TurnOff Characteristics . . . . . . . . . . . . . . . . . . 67 SCR TurnOff Mechanism . . . . . . . . . . . . . . . . . . . . . 67 SCR TurnOff Time tq . . . . . . . . . . . . . . . . . . . . . . . . . 67 Parameters Affecting tq . . . . . . . . . . . . . . . . . . . . . . . . 72 Characterizing SCRs for Crowbar Applications . . . . 78 Switches as LineType Modulators . . . . . . . . . . . . . . 86 Parallel Connected SCRs . . . . . . . . . . . . . . . . . . . . . . 92 RFI Suppression in Thyristor Circuits . . . . . . . . . . . . 96 Section 6: Applications . . . . . . . . . . . . . . . . . . . . . . . . 100 Phase Control with Thyristors . . . . . . . . . . . . . . . . . 100 Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Phase Control with Trigger Devices . . . . . . . . . . . . 109 Cycle Control with Optically Isolated Triac Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 AC Power Control with SolidState Relays . . . . . . 117 Triacs and Inductive Loads . . . . . . . . . . . . . . . . . . . . 121 Inverse Parallel SCRs for Power Control . . . . . . . . 124 Page Interfacing Digital Circuits to Thyristor Controlled AC Loads . . . . . . . . . . . . . . . . . . . . . . . . 125 DC Motor Control with Thyristors . . . . . . . . . . . . . . . 134 Programmable Unijunction Transistor (PUT) Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Triac ZeroPoint Switch Applications . . . . . . . . . . . 143 AN1045 Series Triacs in AC High Voltage Switching Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 AN1048 RC Snubber Networks for Thyristor Power Control and Transient Suppression . . . . . . . 159 AND8005 Automatic AC Line Voltage Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 AND8006 Electronic Starter for Flourescent Lamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 AND8007 Momentary Solid State Switch for Split Phase Motors . . . . . . . . . . . . . . . . . . . . . . . . 188 AND8008 Solid State Control Solutions for Three Phase 1 HP Motor . . . . . . . . . . . . . . . . . . . 193 AND8015 Long Life Incandescent Lamps using SIDACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 AND8017 Solid State Control for BiDirectional Motors . . . . . . . . . . . . . . . . . . . . . . . . . 205 Section 7: Mounting Techniques for Thyristors . . 208 Mounting Surface Considerations . . . . . . . . . . . . . . 209 Thermal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Insulation Considerations . . . . . . . . . . . . . . . . . . . . . 211 Fastening Techniques . . . . . . . . . . . . . . . . . . . . . . . . 216 Insulated Packages . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Surface Mount Devices . . . . . . . . . . . . . . . . . . . . . . . 219 Thermal System Evaluation . . . . . . . . . . . . . . . . . . . 221 Section 8: Reliability and Quality . . . . . . . . . . . . . . . 225 Using Transient Thermal Resistance Data in High Power Pulsed Thyristor Applications . . . . . . 225 Thyristor Construction . . . . . . . . . . . . . . . . . . . . . . . . 237 InProcess Controls and Inspections . . . . . . . . . . . 237 Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Stress Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Environmental Testing . . . . . . . . . . . . . . . . . . . . . . . . 240 Section 9: Appendices . . . . . . . . . . . . . . . . . . . . . . . . . 241
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SECTION 1 SYMBOLS AND TERMINOLOGY
SYMBOLS
The following are the most commonly used schematic symbols for Thyristors:
Name of Device
Silicon Controlled Rectifier (SCR)
Symbol
G A K
Triac
MT2 G
MT1
Thyristor Surge Protective Devices & Sidac
MT1
MT2
Programmable Unijunction Transistor (PUT)
G A K
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THYRISTOR TERMINOLOGY (The following terms are used in SCR and TRIAC specifications.)
Symbol di/dt
Terminology CRITICAL RATE OF RISE OF ONSTATE CURRENT
Definition The maximum rate of change of current the device will withstand after switching from an offstate to an onstate when using recommended gate drive. In other words, the maximum value of the rate of rise of onstate current which a Triac or SCR can withstand without damage. Is the ability of a Triac to turn off itself when it is driving an inductive load and a resultant commutating dv/dt condition associated with the nature of the load. Also, commonly called static dv/dt. It is the minimum value of the rate of rise of forward voltage which will cause switching from the offstate to the onstate with gate open. The maximum value of current which will flow at VDRM and specified temperature when the SCR or Triac is in the offstate. Frequently referred to as leakage current in the forward offstate blocking mode. The maximum peak gate current which may be safely applied to the device to cause conduction. The maximum value of gate current required to switch the device from the offstate to the onstate under specified conditions. The designer should consider the maximum gate trigger current as the minimum trigger current value that must be applied to the device in order to assure its proper triggering. The minimum current that must be flowing (MT1 & MT2; cathode and anode) to keep the device in a regenerative onstate condition. Below this holding current value the device will return to a blocking state, off condition. The minimum current that must be applied through the main terminals of a Triac (or cathode and anode of an SCR) in order to turn from the offstate to the onstate while its IGT is being correctly applied. The maximum value of current which will flow at VRRM and specified temperature when the SCR or Triac is in the reverse mode, offstate. Frequently referred to as leakage current in the reverse offstate blocking mode. The maximum average onstate current the device may safely conduct under stated conditions without incurring damage.
(di/dt)c
RATE OF CHANGE OF COMMUTATING CURRENT (Triacs)
dv/dt
CRITICAL RATE OF RISE OF OFFSTATE VOLTAGE
IDRM
PEAK REPETITIVE BLOCKING CURRENT
IGM
FORWARD PEAK GATE CURRENT (SCR) PEAK GATE CURRENT (Triac) GATE TRIGGER CURRENT
IGT
IH
HOLDING CURRENT
IL
LATCHING CURRENT
IRRM
PEAK REPETITIVE REVERSE BLOCKING CURRENT
IT(AV)
AVERAGE ONSTATE CURRENT (SCR)
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Symbol ITM
Terminology PEAK REPETITIVE ONSTATE CURRENT (SCR) (also called PEAK DISCHARGE CURRENT)
Definition Peak discharge current capability of a thyristor useful when connected to discharge peak current usually from a capacitor. This is a rarely specified parameter. (See MCR68 and MCR69 data sheets, for examples where it is specified.) The maximum value of onstate rms current that can be applied to the device through the two main terminals of a Triac (or cathode and anode if an SCR) on a continuous basis. The maximum allowable nonrepetitive surge current the device will withstand at a specified pulse width, usually specified at 60 Hz. The maximum forward nonrepetitive overcurrent capability that the device is able to handle without damage. Usually specified for onehalf cycle of 60 Hz operation. The maximum allowable value of gate power, averaged over a full cycle, that may be dissipated between the gate and cathode terminal (SCR), or main terminal 1 if a Triac. The maximum instantaneous value of gate power dissipation between gate and cathode terminal for an SCR or between gate and a main terminal MT1 for a Triac, for a short pulse duration. The thermal resistance (steadystate) from the device case to the ambient. The thermal resistance (steadystate) from the semiconductor junction(s) to the ambient. The thermal resistance (steadystate) from the semiconductor junction(s) to a stated location on the case. The thermal resistance (steadystate) from the semiconductor junction(s) to a stated location on the mounting surface. The air temperature measured below a device in an environment of substantially uniform temperature, cooled only by natural air currents and not materially affected by radiant and reflective surfaces. The temperature of the device case under specified conditions.
IT(RMS)
ONSTATE RMS CURRENT
ITSM
PEAK NONREPETITIVE SURGE CURRENT
I2t
CIRCUIT FUSING CONSIDERATIONS (Current squared time)
PG(AV)
FORWARD AVERAGE GATE POWER (SCR) AVERAGE GATE POWER (Triac)
PGM
FORWARD PEAK GATE POWER (SCR) PEAK GATE POWER (Triac)
RCA
THERMAL RESISTANCE, CASETOAMBIENT THERMAL RESISTANCE, JUNCTIONTOAMBIENT THERMAL RESISTANCE, JUNCTIONTOCASE THERMAL RESISTANCE, JUNCTIONTOMOUNTING SURFACE
RJA
RJC
RJM
TA
AMBIENT TEMPERATURE
TC
CASE TEMPERATURE
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Symbol tgt
Terminology TURNON TIME (SCR) (Also called Gate Controlled Turnon Time)
Definition The time interval between a specified point at the beginning of the gate pulse and the instant when the device voltage has dropped to a specified low value during the switching of an SCR from the off state to the on state by a gate pulse. The junction temperature of the device at the die level as a result of ambient and load conditions. In other words, the junction temperature must be operated within this range to prevent permanent damage. The time interval between the instant when the SCR current has decreased to zero after external switching of the SCR voltage circuit and the instant when the thyristor is capable of supporting a specified wave form without turning on. The minimum and maximum temperature at which the device may be stored without harm with no electrical connections. The maximum allowed value of repetitive forward voltage which may be applied and not switch the SCR or Triac on or do damage to the thyristor. At the maximum rated operational temperature, and at a specified main terminal offstate voltage applied, this parameter specifies the maximum DC voltage that can be applied to the gate and still not switch the device from offstate to and onstate. The maximum peak value of voltage allowed between the gate and cathode terminals with these terminals forward biased for an SCR. For a Triac, a bias condition between the gate and main terminal MT1. The gate dc voltage required to produce the gate trigger current. The dielectric withstanding voltage capability of a thyristor between the active portion of the device and the heat sink. Relative humidity is a specified condition. The maximum allowable peak reverse voltage applied to the gate on an SCR. Measured at a specified IGR which is the reverse gate current. The maximum allowed value of repetitive reverse voltage which may be applied and not switch the SCR or Triac on or do damage to the thyristor.
TJ
OPERATING JUNCTION TEMPERATURE
tq
TURNOFF TIME (SCR)
Tstg
STORAGE TEMPERATURE
VDRM
PEAK REPETITIVE OFFSTATE FORWARD VOLTAGE
VGD
GATE NONTRIGGER VOLTAGE
VGM
FORWARD PEAK GATE VOLTAGE (SCR) PEAK GATE VOLTAGE (Triac)
VGT
GATE TRIGGER VOLTAGE
V(Iso)
RMS ISOLATION VOLTAGE
VRGM
PEAK REVERSE GATE BLOCKING VOLTAGE (SCR)
VRRM
PEAK REPETITIVE REVERSE OFFSTATE VOLTAGE
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Symbol VTM
Terminology PEAK FORWARD ONSTATE VOLTAGE (SCR) PEAK ONSTATE VOLTAGE (Triac)
Definition The maximum voltage drop across the main terminals at stated conditions when the devices are in the onstate (i.e., when the thyristor is in conduction). To prevent heating of the junction, the VTM is measured at a short pulse width and low duty cycle. The transient thermal impedance from the semiconductor junction(s) to the ambient. The transient thermal impedance from the semiconductor junction(s) to a stated location on the case.
ZJA(t)
TRANSIENT THERMAL IMPEDANCE, JUNCTIONTOAMBIENT TRANSIENT THERMAL IMPEDANCE, JUNCTIONTOCASE
ZJC(t)
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Thyristor Surge Protector Devices (TSPD) and Sidac Terminology*
Symbol IBO
Terminology BREAKOVER CURRENT
Definition The breakover current IBO is the corresponding parameter defining the VBO condition, that is, where breakdown is occurring. The maximum value of current which will flow at specific voltages (VD1 and VD2) when the TSPD is clearly in the offstate. Frequently referred to as leakage current. The maximum pulse surge capability of the TSPD (nonrepetitive) under double exponential decay waveform conditions. Defines the instantaneous peak power dissipation when the TSPD (thyristor surge suppressor devices) are subjected to specified surge current conditions. The effective switching resistance usually under a sinusoidal, 60 Hz condition. It is the peak voltage point where the device switches to an onstate condition. VBR is the voltage where breakdown occurs. Usually given as a typical value for reference to the Design Engineer. The maximum offstate voltage prior to the TSPD going into a characteristic similar to an avalanche mode. When a transient or line signal exceeds the VDM, the device begins to avalanche, then immediately begins to conduct. The maximum voltage drop across the terminals at stated conditions when the TSPD devices are in the onstate (i.e., conduction). To prevent overheating, VT is measured at a short pulse width and a low duty cycle.
ID1, ID2
OFFSTATE CURRENT (TSPD)
Ipps
PULSE SURGE SHORT CIRCUIT CURRENT NONREPETITIVE (TSPD)
Ppk
INSTANTANEOUS PEAK POWER DISSIPATION (TSPD)
Rs
SWITCHING RESISTANCE (Sidac)
VBO
BREAKOVER VOLTAGE
V(BR)
BREAKDOWN VOLTAGE (TSPD)
VDM
OFFSTATE VOLTAGE (TSPD)
VT
ONSTATE VOLTAGE (TSPD)
* All of the definitions on this page are for ones that were not already previously defined under Triac and SCR terminology.
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SECTION 2 THEORY OF THYRISTOR OPERATION
Edited and Updated
To successfully apply thyristors, an understanding of their characteristics, ratings, and limitations is imperative. In this chapter, significant thyristor characteristics, the basis of their ratings, and their relationship to circuit design are discussed. Several different kinds of thyristors are shown in Table 2.1. Silicon Controlled Rectifiers (SCRs) are the most widely used as power control elements; triacs are quite popular in lower current (under 40 A) ac power applications. Diacs, SUSs and SBSs are most commonly used as gate trigger devices for the power control elements.
Table 2.1. Thyristor Types
*JEDEC Titles Reverse Blocking Diode Thyristor Reverse Blocking Triode Thyristor Reverse Conducting Diode Thyristor Reverse Conducting Triode Thyristor Bidirectional Triode Thyristor Popular Names, Types
{ Four Layer Diode, Silicon { Unilateral Switch (SUS) { Silicon Controlled Rectifier { (SCR) { Reverse Conducting Four { Layer Diode { Reverse Conducting SCR { Triac
* JEDEC is an acronym for the Joint Electron Device Engineering Councils, an industry standardization activity cosponsored by the Electronic Industries Association (EIA) and the National Electrical Manufacturers Association (NEMA).
{ Not generally available.
Before considering thyristor characteristics in detail, a brief review of their operation based upon the common twotransistor analogy of an SCR is in order. BASIC BEHAVIOR The bistable action of thyristors is readily explained by analysis of the structure of an SCR. This analysis is essentially the same for any operating quadrant of triac because a triac may be considered as two parallel SCRs oriented in opposite directions. Figure 2.1(a) shows the
schematic symbol for an SCR, and Figure 2.1(b) shows the PNPN structure the symbol represents. In the twotransistor model for the SCR shown in Figure 2.1(c), the interconnections of the two transistors are such that regenerative action occurs. Observe that if current is injected into any leg of the model, the gain of the transistors (if sufficiently high) causes this current to be amplified in another leg. In order for regeneration to occur, it is necessary for the sum of the common base current gains () of the two transistors to exceed unity. Therefore, because the junction leakage currents are relatively small and current gain is designed to be low at the leakage current level, the PNPN device remains off unless external current is applied. When sufficient trigger current is applied (to the gate, for example, in the case of an SCR) to raise the loop gain to unity, regeneration occurs and the onstate principal current is limited primarily by external circuit impedance. If the initiating trigger current is removed, the thyristor remains in the on state, providing the current level is high enough to meet the unity gain criteria. This critical current is called latching current. In order to turn off a thyristor, some change in current must occur to reduce the loop gain below unity. From the model, it appears that shorting the gate to cathode would accomplish this. However in an actual SCR structure, the gate area is only a fraction of the cathode area and very little current is diverted by the short. In practice, the principal current must be reduced below a certain level, called holding current, before gain falls below unity and turnoff may commence. In fabricating practical SCRs and Triacs, a shorted emitter design is generally used in which, schematically, a resistor is added from gate to cathode or gate to MT1. Because current is diverted from the Nbase through the resistor, the gate trigger current, latching current and holding current all increase. One of the principal reasons for the shunt resistance is to improve dynamic performance at high temperatures. Without the shunt, leakage current on most high current thyristors could initiate turnon at high temperatures.
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Sensitive gate thyristors employ a high resistance shunt or none at all; consequently, their characteristics can be altered dramatically by use of an external resistance. An external resistance has a minor effect on most shorted emitter designs.
ANODE ANODE
GATE CATHODE (a) ANODE IC1 IB2 IB1 IC2 P N P N P N P GATE N P N (c) CATHODE (b) CATHODE GATE IK
Figure 2.1. Twotransistor analogy of an SCR: (a) schematic symbol of SCR; (b) PNPN structure represented by schematic symbol; (c) twotransistor model of SCR.
from leakage, or avalanche breakdown of a blocking junction. As a result, the breakover voltage of a thyristor can be varied or controlled by injection of a current at the gate terminal. Figure 2.2 shows the interaction of gate current and voltage for an SCR. When the gate current Ig is zero, the applied voltage must reach the breakover voltage of the SCR before switching occurs. As the value of gate current is increased, however, the ability of a thyristor to support applied voltage is reduced and there is a certain value of gate current at which the behavior of the thyristor closely resembles that of a rectifier. Because thyristor turnon, as a result of exceeding the breakover voltage, can produce high instantaneous power dissipation nonuniformly distributed over the die area during the switching transition, extreme temperatures resulting in die failure may occur unless the magnitude and rate of rise of principal current (di/dt) is restricted to tolerable levels. For normal operation, therefore, SCRs and triacs are operated at applied voltages lower than the breakover voltage, and are made to switch to the on state by gate signals high enough to assure complete turnon independent of the applied voltage. On the other hand, diacs and other thyristor trigger devices are designed to be triggered by anode breakover. Nevertheless they also have di/dt and peak current limits which must be adhered to.
Junction temperature is the primary variable affecting thyristor characteristics. Increased temperatures make the thyristor easier to turn on and keep on. Consequently, circuit conditions which determine turnon must be designed to operate at the lowest anticipated junction temperatures, while circuit conditions which are to turn off the thyristor or prevent false triggering must be designed to operate at the maximum junction temperature. Thyristor specifications are usually written with case temperatures specified and with electrical conditions such that the power dissipation is low enough that the junction temperature essentially equals the case temperature. It is incumbent upon the user to properly account for changes in characteristics caused by the circuit operating conditions different from the test conditions. TRIGGERING CHARACTERISTICS Turnon of a thyristor requires injection of current to raise the loop gain to unity. The current can take the form of current applied to the gate, an anode current resulting
V Ig4 Ig3 Ig2 Ig1 = 0
Figure 2.2. Thyristor Characteristics Illustrating Breakover as a Function of Gate Current
A triac works the same general way for both positive and negative voltage. However since a triac can be switched on by either polarity of the gate signal regardless of the voltage polarity across the main terminals, the situation is somewhat more complex than for an SCR. The various combinations of gate and main terminal polarities are shown in Figure 2.3. The relative sensitivity depends on the physical structure of a particular triac, but as a rule, sensitivity is highest in quadrant I and quadrant IV is generally considerably less sensitive than the others.
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MT2(+) QUADRANT II MT2(+), G() QUADRANT I MT2(+), G(+)
G() QUADRANT III MT2(), G() QUADRANT IV MT2(), G(+)
G(+)
MT2()
Figure 2.3. Quadrant Definitions for a Triac
Gate sensitivity of a triac as a function of temperature is shown in Figure 2.4.

30 IGT, GATE TRIGGER CURRENT (mA) 20 OFFSTATE VOLTAGE = 12 Vdc ALL QUADRANTS
Although the criteria for turnon have been described in terms of current, it is more basic to consider the thyristor as being charge controlled. Accordingly, as the duration of the trigger pulse is reduced, its amplitude must be correspondingly increased. Figure 2.5 shows typical behavior at various pulse widths and temperatures. The gate pulse width required to trigger a thyristor also depends upon the time required for the anode current to reach the latching value. It may be necessary to maintain a gate signal throughout the conduction period in applications where the load is highly inductive or where the anode current may swing below the holding value within the conduction period. When triggering an SCR with a dc current, excess leakage in the reverse direction normally occurs if the trigger signal is maintained during the reverse blocking phase of the anode voltage. This happens because the SCR operates like a remote base transistor having a gain which is generally about 0.5. When high gate drive currents are used, substantial dissipation could occur in the SCR or a significant current could flow in the load; therefore, some means usually must be provided to remove the gate signal during the reverse blocking phase.
300 IGTM , PEAK GATE CURRENT (mA)
10 7 5 1 QUADRANT 2 3 4 40 20 0 20 40 60 80 TJ, JUNCTION TEMPERATURE (C)
OFFSTATE VOLTAGE = 12 V 100 70 50 30 TJ = 55C 25C 100C 0.5 1 2 5 10 20 PULSE WIDTH (s) 50 100 200
3 80 60
100
120
10 7 5 3 0.2
Figure 2.4. Typical Triac Triggering Sensitivity in the Four Trigger Quadrants
Since both the junction leakage currents and the current gain of the transistor elements increase with temperature, the magnitude of the required gate trigger current decreases as temperature increases. The gate which can be regarded as a diode exhibits a decreasing voltage drop as temperature increases. Thus it is important that the gate trigger circuit be designed to deliver sufficient current to the gate at the lowest anticipated temperature. It is also advisable to observe the maximum gate current, as well as peak and average power dissipation ratings. Also in the negative direction, the maximum gate ratings should be observed. Both positive and negative gate limits are often given on the data sheets and they may indicate that protective devices such as voltage clamps and current limiters may be required in some applications. It is generally inadvisable to dissipate power in the reverse direction.
Figure 2.5. Typical Behavior of Gate Trigger Current as Pulse Width and Temperature Are Varied
LATCH AND HOLD CHARACTERISTICS In order for the thyristor to remain in the on state when the trigger signal is removed, it is necessary to have sufficient principal current flowing to raise the loop gain to unity. The principal current level required is the latching current, IL. Although triacs show some dependency on the gate current in quadrant II, the latching current is primarily affected by the temperature on shorted emitter structures. In order to allow turn off, the principal current must be reduced below the level of the latching current. The current level where turn off occurs is called the holding current, IH. Like the latching current, the holding current is affected by temperature and also depends on the gate impedance.
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Reverse voltage on the gate of an SCR markedly increases the latch and hold levels. Forward bias on thyristor gates may significantly lower the values shown in the data sheets since those values are normally given with the gate open. Failure to take this into account can cause latch or hold problems when thyristors are being driven from transistors whose saturation voltages are a few tenths of a volt. Thyristors made with shorted emitter gates are obviously not as sensitive to the gate circuit conditions as devices which have no builtin shunt. SWITCHING CHARACTERISTICS When triacs or SCRs are triggered by a gate signal, the turnon time consists of two stages: a delay time, td, and a rise time, tr, as shown in Figure 2.6. The total gate controlled turnon time, tgt, is usually defined as the time interval between the 50 percent point of the leading edge of the gate trigger voltage and 90 percent point of the principal current. The rise time tr is the time interval required for the principal current to rise from 10 to 90 percent of its maximum value. A resistive load is usually specified.
90% POINT PRINCIPAL VOLTAGE 10% POINT 0 90% POINT 10% POINT td ton GATE CURRENT IGT 0 (WAVESHAPES FOR A SENSITIVE LOAD) tr
PRINCIPAL CURRENT 0
IGT 50%
50% POINT
Figure 2.6. Waveshapes Illustrating Thyristor TurnOn Time For A Resistive Load
Delay time decreases slightly as the peak offstate voltage increases. It is primarily related to the magnitude of the gatetrigger current and shows a relationship which is roughly inversely proportional.
The rise time is influenced primarily by the offstate voltage, as high voltage causes an increase in regenerative gain. Of major importance in the rise time interval is the relationship between principal voltage and current flow through the thyristor di/dt. During this time the dynamic voltage drop is high and the current density due to the possible rapid rate of change can produce localized hot spots in the die. This may permanently degrade the blocking characteristics. Therefore, it is important that power dissipation during turnon be restricted to safe levels. Turnoff time is a property associated only with SCRs and other unidirectional devices. (In triacs of bidirectional devices a reverse voltage cannot be used to provide circuitcommutated turnoff voltage because a reverse voltage applied to one half of the structure would be a forwardbias voltage to the other half.) For turnoff times in SCRs, the recovery period consists of two stages, a reverse recovery time and a gate or forward blocking recovery time, as shown in Figure 2.7. When the forward current of an SCR is reduced to zero at the end of a conduction period, application of reverse voltage between the anode and cathode terminals causes reverse current flow in the SCR. The current persists until the time that the reverse current decreases to the leakage level. Reverse recovery time (trr) is usually measured from the point where the principal current changes polarity to a specified point on the reverse current waveform as indicated in Figure 2.7. During this period the anode and cathode junctions are being swept free of charge so that they may support reverse voltage. A second recovery period, called the gate recovery time, tgr, must elapse for the charge stored in the forwardblocking junction to recombine so that forwardblocking voltage can be reapplied and successfully blocked by the SCR. The gate recovery time of an SCR is usually much longer than the reverse recovery time. The total time from the instant reverse recovery current begins to flow to the start of the forwardblocking voltage is referred to as circuit commutated turnoff time tq. Turnoff time depends upon a number of circuit conditions including onstate current prior to turnoff, rate of change of current during the forwardtoreverse transition, reverseblocking voltage, rate of change of reapplied forward voltage, the gate bias, and junction temperature. Increasing junction temperature and on state current both increase turnoff time and have a more significant effect than any of the other factors. Negative gate bias will decrease the turnoff time.
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REAPPLIED dv/dt
PRINCIPAL VOLTAGE
FORWARD
0 REVERSE
di/dt
PRINCIPAL CURRENT 0
FORWARD
REVERSE trr tq tgr
Figure 2.7. Waveshapes Illustrating Thyristor TurnOff Time
For applications in which an SCR is used to control ac power, during the entire negative half of the sine wave a reverse voltage is applied. Turn off is easily accomplished for most devices at frequencies up to a few kilohertz. For applications in which the SCR is used to control the output of a fullwave rectifier bridge, however, there is no reverse voltage available for turnoff, and complete turnoff can be accomplished only if the bridge output is reduced close to zero such that the principal current is reduced to a value lower than the device holding current for a sufficiently long time. Turnoff problems may occur even at a frequency of 60 Hz particularly if an inductive load is being controlled. In triacs, rapid application of a reverse polarity voltage does not cause turnoff because the main blocking junctions are common to both halves of the device. When the first triac structure (SCR1) is in the conducting state, a quantity of charge accumulates in the Ntype region as a result of the principal current flow. As the principal current crosses the zero reference point, a reverse current is established as a result of the charge remaining in the Ntype region, which is common to both halves of the device. Consequently, the reverse recovery current becomes a forward current to the second half of the triac.
The current resulting from stored charge causes the second half of the triac to go into the conducting state in the absence of a gate signal. Once current conduction has been established by application of a gate signal, therefore, complete loss in power control can occur as a result of interaction within the Ntype base region of the triac unless sufficient time elapses or the rate of application of the reverse polarity voltage is slow enough to allow nearly all the charge to recombine in the common Ntype region. Therefore, triacs are generally limited to lowfrequency 60 Hz applications. Turnoff or commutation of triacs is more severe with inductive loads than with resistive loads because of the phase lag between voltage and current associated with inductive loads. Figure 2.8 shows the waveforms for an inductive load with lagging current power factor. At the time the current reaches zero crossover (Point A), the half of the triac in conduction begins to commutate when the principal current falls below the holding current. At the instant the conducting half of the triac turns off, an applied voltage opposite the current polarity is applied across the triac terminals (Point B). Because this voltage is a forward bias to the second half of the triac, the suddenly reapplied voltage in conjunction with the remaining stored charge in the highvoltage junction reduces the overall device capability to support voltage. The result is a loss of power control to the load, and the device remains in the conducting state in absence of a gate signal. The measure of triac turnoff ability is the rate of rise of the opposite polarity voltage it can handle without remaining on. It is called commutating dv/dt (dv/dt[c]). Circuit conditions and temperature affect dv/dt(c) in a manner similar to the way tq is affected in an SCR. It is imperative that some means be provided to restrict the rate of rise of reapplied voltage to a value which will permit triac turnoff under the conditions of inductive load. A commonly accepted method for keeping the commutating dv/dt within tolerable levels is to use an RC snubber network in parallel with the main terminals of the triac. Because the rate of rise of applied voltage at the triac terminals is a function of the load impedance and the RC snubber network, the circuit can be evaluated under worstcase conditions of operating case temperature and maximum principal current. The values of resistance and capacitance in the snubber area then adjusted so that the rate of rise of commutating dv/dt stress is within the specified minimum limit under any of the conditions mentioned above. The value of snubber resistance should be high enough to limit the snubber capacitance discharge currents during turnon and dampen the LC oscillation during commutation. The combination of snubber values having highest resistance and lowest capacitance that provides satisfactory operation is generally preferred.
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IH V I A dr c dt B
Figure 2.8. Inductive Load Waveforms
FALSE TRIGGERING Circuit conditions can cause thyristors to turn on in the absence of the trigger signal. False triggering may result from: 1) A high rate of rise of anode voltage, (the dv/dt effect). 2) Transient voltages causing anode breakover. 3) Spurious gate signals. Static dv/dt effect: When a source voltage is suddenly applied to a thyristor which is in the off state, it may switch from the off state to the conducting state. If the thyristor is controlling alternating voltage, false turnon resulting from a transient imposed voltage is limited to no more than onehalf cycle of the applied voltage because turnoff occurs during the zero current crossing. However, if the principal voltage is dc voltage, the transient may cause switching to the on state and turnoff could then be achieved only by a circuit interruption. The switching from the off state caused by a rapid rate of rise of anode voltage is the result of the internal capacitance of the thyristor. A voltage wavefront impressed across the terminals of a thyristor causes a capacitancecharging current to flow through the device which is a function of the rate of rise of applied offstate voltage (i = C dv/dt). If the rate of rise of voltage exceeds a critical value, the capacitance charging current exceeds the gate triggering current and causes device turnon. Operation at elevated junction temperatures reduces the thyristor ability to support a steep rising voltage dv/dt because of increased sensitivity. dv/dt ability can be improved quite markedly in sensitive gate devices and to some extent in shorted emitter designs by a resistance from gate to cathode (or MT1) however reverse bias voltage is even more effective in an SCR. More commonly, a snubber network is used to keep the dv/dt within the limits of the thyristor when the gate is open. TRANSIENT VOLTAGES: Voltage transients which occur in electrical systems as a result of disturbance on the ac line caused by various sources such as energizing transformers, load switching, solenoid closure, contractors and the like may generate voltages which are
above the ratings of thyristors. Thyristors, in general, switch from the off state to the on state whenever the breakover voltage of the device is exceeded, and energy is then transferred to the load. However, unless a thyristor is specified for use in a breakover mode, care should be exercised to ensure that breakover does not occur, as some devices may incur surface damage with a resultant degradation of blocking characteristics. It is good practice when thyristors are exposed to a heavy transient environment to provide some form of transient suppression. For applications in which lowenergy, longduration transients may be encountered, it is advisable to use thyristors that have voltage ratings greater than the highest voltage transient expected in the system. The use of voltage clipping cells (MOV or Zener) is also an effective method to hold transient below thyristor ratings. The use of an RC snubber circuit is effective in reducing the effects of the highenergy shortduration transients more frequently encountered. The snubber is commonly required to prevent the static dv/dt limits from being exceeded, and often may be satisfactory in limiting the amplitude of the voltage transients as well. For all applications, the dv/dt limits may not be exceeded. This is the minimum value of the rate of rise offstate voltage applied immediately to the MT1MT2 terminals after the principal current of the opposing polarity has decreased to zero. SPURIOUS GATE SIGNALS: In noisy electrical environments, it is possible for enough energy to cause gate triggering to be coupled into the gate wiring by stray capacitance or electromagnetic induction. It is therefore advisable to keep the gate lead short and have the common return directly to the cathode or MT1. In extreme cases, shielded wire may be required. Another aid commonly used is to connect a capacitance on the order of 0.01 to 0.1 F across the gate and cathode terminals. This has the added advantage of increasing the thyristor dv/dt capability, since it forms a capacitance divider with the anode to gate capacitance. The gate capacitor also reduces the rate of application of gate trigger current which may cause di/dt failures if a high inrush load is present. THYRISTOR RATINGS To insure long life and proper operation, it is important that operating conditions be restrained from exceeding thyristor ratings. The most important and fundamental ratings are temperature and voltage which are interrelated to some extent. The voltage ratings are applicable only up to the maximum temperature ratings of a particular part number. The temperature rating may be chosen by the manufacturer to insure satisfactory voltage ratings, switching speeds, or dv/dt ability.
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OPERATING CURRENT RATINGS Current ratings are not independently established as a rule. The values are chosen such that at a practical case temperature the power dissipation will not cause the junction temperature rating to be exceeded. Various manufacturers may chose different criteria to establish ratings. At ON Semiconductors, use is made of the thermal response of the semiconductor and worst case values of onstate voltage and thermal resistance, to guarantee the junction temperature is at or below its rated value. Values shown on data sheets consequently differ somewhat from those computed from the standard formula:
TC(max) = T (rated) RJC
PD(AV)
where TC (max) = Maximum allowable case temperature T (rated) = Rated junction temperature or maximum rated case temperature with zero principal current and rated ac blocking voltage applied. RJC = Junction to case thermal resistance PD(AV) = Average power dissipation
For a triac, the current waveform used in the rating is a full sine wave. Multicycle surge curves are used to select proper circuit breakers and series line impedances to prevent damage to the thyristor in the event of an equipment fault. The subcycle overload or subcycle surge rating curve is so called because the time duration of the rating is usually from about one to eight milliseconds which is less than the time of one cycle of a 60 Hz power source. Overload peak current is often given in curve form as a function of overload duration. This rating also applies following any rated load condition and neither offstate nor reverse blocking capability is required on the part of the thyristor immediately following the overload current. The subcycle surge current rating may be used to select the proper currentlimiting fuse for protection of the thyristor in the event of an equipment fault. Since this use of the rating is so common, manufacturers simply publish the i2t rating in place of the subcycle current overload curve because fuses are commonly rated in terms of i2t. The i2t rating can be approximated from the single cycle surge rating (ITSM) by using:
i2t = I2TSM
The above formula is generally suitable for estimating case temperature in situations not covered by data sheet information. Worst case values should be used for thermal resistance and power dissipation. OVERLOAD CURRENT RATINGS Overload current ratings may be divided into two types: nonrepetitive and repetitive. Nonrepetitive overloads are those which are not a part of the normal application of the device. Examples of such overloads are faults in the equipment in which the devices are used and accidental shorting of the load. Nonrepetitive overload ratings permit the device to exceed its maximum operating junction temperature for short periods of time because this overload rating applies following any rated load condition. In the case of a reverse blocking thyristor or SCR, the device must block rated voltage in the reverse direction during the current overload. However, no type of thyristor is required to block offstage voltage at any time during or immediately following the overload. Thus, in the case of a triac, the device need not block in either direction during or immediately following the overload. Usually only approximately one hundred such current overloads are permitted over the life of the device. These nonrepetitive overload ratings just described may be divided into two types: multicycle (which include single cycle) and subcycle. For an SCR, the multicycle overload current rating, or surge current rating as it is commonly called, is generally presented as a curve giving the maximum peak values of half sine wave onstate current as a function of overload duration measured in number of cycles for a 60 Hz frequency.
t/2
where the time t is the time base of the overload, i.e., 8.33 ms for a 60 Hz frequency. Repetitive overloads are those which are an intended part of the application such as a motor drive application. Since this type of overload may occur a large number of times during the life of the thyristor, its rated maximum operating junction temperature must not be exceeded during the overload if long thyristor life is required. Since this type of overload may have a complex current waveform and dutycycle, a current rating analysis involving the use of the transient thermal impedance characteristics is often the only practical approach. In this type of analysis, the thyristor junctiontocase transient thermal impedance characteristic is added to the users heat dissipator transient thermal impedance characteristic. Then by the superposition of power waveforms in conjunction with the composite thermal impedance curve, the overload current rating can be obtained. The exact calculation procedure is found in the power semiconductor literature. THEORY OF SCR POWER CONTROL The most common form of SCR power control is phase control. In this mode of operation, the SCR is held in an off condition for a portion of the positive half cycle and then is triggered into an on condition at a time in the half cycle determined by the control circuitry (in which the circuit current is limited only by the load the entire line voltage except for a nominal one volt drop across the SCR is applied to the load).
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One SCR alone can control only one half cycle of the waveform. For full wave ac control, two SCRs are connected in inverse parallel (the anode of each connected to the cathode of the other, see Figure 2.9a). For full wave dc control, two methods are possible. Two SCRs may be used in a bridge rectifier (see Figure 2.9b) or one SCR may be placed in series with a diode bridge (see Figure 2.9c). Figure 2.10 shows the voltage waveform along with some common terms used in describing SCR operation. Delay angle is the time, measured in electrical degrees, during which the SCR is blocking the line voltage. The period during which the SCR is on is called the conduction angle. It is important to note that the SCR is a voltage controlling device. The load and power source determine the circuit current. Now we arrive at a problem. Different loads respond to different characteristics of the ac waveform. Some loads are sensitive to peak voltage, some to average voltage and some to rms voltage. Figures 2.11(b) and 2.12(b) show the various characteristic voltages plotted against the conduction angle for half wave and full wave circuits. These voltages have been normalized to the rms of the applied voltage. To determine the actual peak, average or rms voltage for any conduction angle, we simply multiply the normalized voltage by the rms value of the applied line voltage. (These normalized curves also apply to current in a resistive circuit.) Since the greatest majority of circuits are either 115 or 230 volt power, the curves have been redrawn for these voltages in Figures 2.11(a) and 2.12(a). A relative power curve has been added to Figure 2.12 for constant impedance loads such as heaters. (Incandescent lamps and motors do not follow this curve precisely since their relative impedance changes with applied voltage.) To use the curves, we find the full wave rated power of the load, then multiply by the fraction associated with the phase angle in question. For example, a 180 conduction angle in a half wave circuit provides 0.5 x full wave fullconduction power. An interesting point is illustrated by the power curves. A conduction angle of 30 provides only three per cent of full power in a full wave circuit, and a conduction angle of 150 provides 97 per cent of full power. Thus, the control circuit can provide 94 per cent of full power control with a pulse phase variation of only 120. Thus, it becomes pointless in many cases to try to obtain conduction angles less than 30 or greater than 150.
CONTROL CHARACTERISTICS
The simplest and most common control circuit for phase control is a relaxation oscillator. This circuit is shown diagrammatically as it would be used with an SCR in Figure 2.13. The capacitor is charged through the resistor from a voltage or current source until the breakover voltage of the trigger device is reached. At that time, the trigger device changes to its on state, and the capacitor is discharged through the gate of the SCR. Turnon of the SCR is thus accomplished with a short, high current pulse. Commonly used trigger devices are programmable unijunction transistors, silicon bilateral switches, SIDACs, optically coupled thyristors, and power control integrated circuits. Phase control can be obtained by varying the RC time constant of a charging circuit so that trigger device turnon occurs at varying phase angles within the controlled half cycle. If the relaxation oscillator is to be operated from a pure dc source, the capacitor voltagetime characteristic is shown in Figure 2.14. This shows the capacitor voltage as it rises all the way to the supply voltage through several time constants. Figure 2.14(b) shows the charge characteristic in the first time constant greatly expanded. It is this portion of the capacitor charge characteristic which is most often used in SCR and Triac control circuits. Generally, a design starting point is selection of a capacitance value which will reliably trigger the thyristor when the capacitor is discharged. Gate characteristics and ratings, trigger device properties, and the load impedance play a part in the selection. Since not all of the important parameters for this selection are completely specified, experimental determination is often the best method. Lowcurrent loads and strongly inductive circuits sometimes cause triggering difficulty because the gate current pulse goes away before the principal thyristor current achieves the latching value. A series gate resistor can be used to introduce a RC discharge time constant in the gate circuit and lengthen trigger pulse duration allowing more time for the main terminal current to rise to the latching value. Small thyristors will require a series gate resistance to avoid exceeding the gate ratings. The discharge time constant of a snubber, if used, can also aid latching. The duration of these capacitor discharge duration currents can be estimated by tw10 = 2.3 RC where tw10 = time for current to decay to 10% of the peak.
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LINE CONTROL CIRCUIT LINE LOAD
(a) ac Control
CONTROL CIRCUIT LOAD
(c) One SCR dc Control Figure 2.9. SCR Connections For Various Methods Of Phase Control
FULL WAVE RECTIFIED OPERATION VOLTAGE APPLIED TO LOAD
LINE
CONTROL CIRCUIT
LOAD
DELAY ANGLE CONDUCTION ANGLE
(b) Two SCR dc Control
Figure 2.10. Sine Wave Showing Principles Of Phase Control
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1.8 HALF WAVE 1.6 NORMALIZED SINE WAVE rms VOLTAGE POWER AS FRACTION OF FULL CONDUCTION 1.4 1.2 VOLTAGE 1 rms 0.8 0.6 0.4 0.2 0 0 20 40 AVG POWER PEAK VOLTAGE
APPLIED VOLTAGE 230 V 115 V 360 180 HALF WAVE 320 280 240 200 160 120 80 40 0 160 140 120 100 rms 80 60 40 20 0 0 20 40 AVG PEAK VOLTAGE
(a)
60 80 100 120 140 160 180 CONDUCTION ANGLE
(b)
Figure 2.11. HalfWave Characteristics Of Thyristor Power Control
1.8 FULL WAVE 1.6 NORMALIZED SINE WAVE rms VOLTAGE POWER AS FRACTION OF FULL CONDUCTION 1.4 1.2 VOLTAGE 1 0.8 0.6 AVG 0.4 0.2 0 0 20 40 PEAK VOLTAGE
APPLIED VOLTAGE 230 V 115 V 360 180 FULL WAVE 320 280 240 200 160 120 80 40 0 160 140 120 100 80 60 AVG 40 20 0 0 20 40 PEAK VOLTAGE rms
rms POWER
(a)
(b)
Figure 2.12. FullWave Characteristics Of Thyristor Power Control
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In many of the recently proposed circuits for low cost operation, the timing capacitor of the relaxation oscillator is charged through a rectifier and resistor using the ac power line as a source. Calculations of charging time with this circuit become exceedingly difficult, although they are still necessary for circuit design. The curves of Figure 2.14 simplify the design immensely. These curves show the voltagetime characteristic of the capacitor charged from one half cycle of a sine wave. Voltage is
normalized to the rms value of the sine wave for convenience of use. The parameter of the curves is a new term, the ratio of the RC time constant to the period of one half cycle, and is denoted by the Greek letter . It may most easily be calculated from the equation
= 2RCf. Where: R = resistance in Ohms C = capacitance in Farads f = frequency in Hertz.
1 0.9 0.8 CAPACITOR VOLTAGE AS FRACTION OF SUPPLY VOLTAGE 0.7 CAPACITOR VOLTAGE AS FRACTION OF SUPPLY VOLTAGE 0.6 0.5 0.4 0.3 0.2 0.1 0 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 TIME CONSTANTS 5 6 0 0.2 0.4 0.6 0.8 1 1.2 TIME CONSTANTS
Figure 2.13(a). Capacitor Charging From dc Source
Figure 2.13(b). Expanded Scale
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1.80 APPLIED VOLTAGE, V 1.40 V NORMALIZED VOLTAGE AS A FRACTION OF rms CHARGING SOURCE VOLTAGE 1.20 1 CAPACITOR VOLTAGE, VC 0.3 0.4 0.5 0.80 0.707 0.60 0.7 1 1.5 2 3 5 20 160 40 140 60 120 80 100 100 80 120 60 140 40 160 20 180 0 R C VC = 0.1 0.2
0.40
0.20 0 0 180
30
DELAY ANGLE IN DEG. CONDUCTION ANGLE IN DEG.
Figure 2.14(a). Capacitor Voltage When Charged
0.35 = 0.1 NORMALIZED VOLTAGE AS A FRACTION OF rms CHARGING SOURCE VOLTAGE 0.30 0.25 0.2 0.3 0.5 0.7 1 1.5 2 2.5
0.20
4 5
0.15 7 0.10 10 15 0.05 0 0 180 20 160 40 140 60 120 80 100 100 80 120 60 140 40 20 50 160 20 180 0
Figure 2.14(b). Expansion of Figure 2.15(a).
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NORMALIZED VOLTAGE AS A FRACTION OF rms CHARGING SOURCE VOLTAGE
0.1 0.09 0.08 0.0696 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0
= 0.1 0.2
0.3 0.7 1 0.5
1.5
2 2.5
8.5 10 12.5 15 20 35 50
10 170
20 160
30 150
40 140
50 130
60 120
70 110
80 100
90 90
100 80
110 70
120 60
130 50
140 40
150 30
160 20
170 10
180 0
180
rms CHARGING SOURCE VOLTAGE
Figure 2.14(c). Expansion of Figure 2.14(b)
To use the curves when starting the capacitor charge from zero each half cycle, a line is drawn horizontally across the curves at the relative voltage level of the trigger breakdown compared to the rms sine wave voltage. The is determined for maximum and minimum conduction angles and the limits of R may be found from the equation for . An example will again clarify the picture. Consider the same problem as the previous example, except that the capacitor charging source is the 115 Vac, 60 Hz power line. The ratio of the trigger diode breakover voltage to the RMS charging voltage is then
8/115 = 69.6
can be prevented by selecting a lower value resistor and larger capacitor. The available current can be determined from Figure 2.14(a). The vertical line drawn from the conduction angle of 30 intersects the applied voltage curve at 0.707. The instantaneous current at breakover is then
I = (0.707
1158)/110 k = 733 A.
103.
A line drawn at 0.0696 on the ordinate of Figure 2.14(c) shows that for a conduction angle of 30, = 12, and for a conduction angle of 150, = 0.8. Therefore, since R = /(2CF)
Rmax
+ 2(1.0
12 100 k ohms, 10 6)60
Rmin
+ 2(1
0.8 6667 ohms. 106 )60
When the conduction angle is greater than 90, triggering takes place before the peak of the sine wave. If the current thru the SBS does not exceed the switching current at the moment of breakover, triggering may still take place but not at the predicted time because of the additional delay for the rising line voltage to drive the SBS current up to the switching level. Usually long conduction angles are associated with low value timing resistors making this problem less likely. The SBS current at the moment of breakover can be determined by the same method described for the trailing edge. It is advisable to use a shunt gatecathode resistor across sensitive gate SCRs to provide a path for leakage currents and to insure that firing of the SCR causes turnon of the trigger device and discharge of the gate circuit capacitor. TRIAC THEORY The triac is a threeterminal ac semiconductor switch which is triggered into conduction when a lowenergy signal is applied to its gate. Unlike the silicon controlled rectifier or SCR, the triac will conduct current in either direction when turned on. The triac also differs from the SCR in that either a positive or negative gate signal will trigger the triac into conduction. The triac may be thought of as two complementary SCRs in parallel.
These values would require a potentiometer of 100 k in series with a 6.2 k minimum fixed resistance. The timing resistor must be capable of supplying the highest switching current allowed by the SBS specification at the switching voltage. When the conduction angle is less than 90, triggering takes place along the back of the power line sine wave and maximum firing current thru the SBS is at the start of SBS breakover. If this current does not equal or exceed ls the SBS will fail to trigger and phase control will be lost. This
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The triac offers the circuit designer an economical and versatile means of accurately controlling ac power. It has several advantages over conventional mechanical switches. Since the triac has a positive on and a zero current off characteristic, it does not suffer from the contact bounce or arcing inherent in mechanical switches. The switching action of the triac is very fast compared to conventional relays, giving more accurate control. A triac can be triggered by dc, ac, rectified ac or pulses. Because of the low energy required for triggering a triac, the control circuit can use any of many lowcost solidstate devices such as transistors, bilateral switches, sensitive gate SCRs and triacs, optically coupled drivers and integrated circuits. CHARACTERISTICS OF THE TRIAC Figure 2.15(a) shows the triac symbol and its relationship to a typical package. Since the triac is a bilateral device, the terms anode and cathode used for unilateral devices have no meaning. Therefore, the terminals are simply designated by MT1, MT2, and G, where MT1 and MT2 are the currentcarrying terminals, and G, is the gate terminal used for triggering the triac. To avoid confusion, it has become standard practice to specify all currents and voltages using MT1 as the reference point. The basic structure of a triac is shown in Figure 2.15(b). This drawing shows why the symbol adopted for the triac consists of two complementary SCRs with a common gate. The triac is a fivelayer device with the region between MT1 and MT2 being PNPN switch (SCR) in parallel with a NPNP switch (complementary SCR). Also, the structure gives some insight into the triacs ability to be triggered with either a positive or negative gate signal. The region between MT1 and G consists of two complementary diodes. A positive or negative gate signal will forwardbias one of these diodes causing the same transistor action found in the SCR. This action breaks down the blocking junction regardless of the polarity of MT1. Current flow between MT2 and MT1 then causes the device to provide gate current internally. It will remain on until this current flow is interrupted. The voltagecurrent characteristic of the triac is shown in Figure 2.16 where, as previously stated, MT1 is used as the reference point. The first quadrant, QI, is the region where MT2 is positive with respect to MT1 and quadrant III is the opposite case. Several of the terms used in characterizing the triac are shown on the figure. VDRM is the breakover voltage of the device and is the highest voltage the triac may be allowed to block in either
direction. If this voltage is exceeded, even transiently, the triac may go into conduction without a gate signal. Although the triac is not damaged by this action if the current is limited, this situation should be avoided because control of the triac is lost. A triac for a particular application should have VDRM at least as high as the peak of the ac waveform to be applied so reliable control can be maintained. The holding current (IH) is the minimum value of current necessary to maintain conduction. When the current goes below IH, the triac ceases to conduct and reverse to the blocking state. IDRM is the leakage current of the triac with VDRM applied from MT2 to MT1 and is several orders of magnitude smaller than the current rating of the device. The figure shows the characteristic of the triac without a gate signal applied but it should be noted that the triac can be triggered into the on state at any value of voltage up to VDRM by the application of a gate signal. This important characteristic makes the triac very useful. Since the triac will conduct in either direction and can be triggered with either a positive or negative gate signal there are four possible triggering modes (Figure 2.3): Quadrant I; MT2(+), G(+), positive voltage and positive gate current. Quadrant II; MT2(+), G(), positive voltage and negative gate current. Quadrant III; MT2(), G(), negative voltage and negative gate current. Quadrant IV; MT2(), G(+), negative voltage and positive gate current. Present triacs are most sensitive in quadrants I and III, slightly less so in quadrant II, and much less sensitive in quadrant IV. Therefore it is not recommended to use quadrant IV unless special circumstances dictate it. An important fact to remember is that since a triac can conduct current in both directions, it has only a brief interval during which the sine wave current is passing through zero to recover and revert to its blocking state. For this reason, reliable operation of present triacs is limited to 60 Hz line frequency and lower frequencies. For inductive loads, the phaseshift between the current and voltage means that at the time the current falls below IH and the triac ceases to conduct, there exists a certain voltage which must appear across the triac. If this voltage appears too rapidly, the triac will resume conduction and control is lost. In order to achieve control with certain inductive loads, the rate of rise in voltage (dv/dt) must be limited by a series RC network across the triac. The capacitor will then limit the dv/dt across the triac. The resistor is necessary to limit the surge of current from the capacitor when the triac fires, and to damp the ringing of the capacitance with the load inductance.
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MT2
PHASE CONTROL
GATE MT1
(a)
MT2
P N N P
MT1
(b) Figure 2.15. Triac Structure and Symbol
ONSTATE
IDRM
VDRM
IH
Q1 MT2+ BLOCKING STATE VDRM
V IH BLOCKING STATE QIII MT2ONSTATE IDRM
An effective and widelyused method of controlling the average power to a load through the triac is by phase control. Phase control is a method of utilizing the triac to apply the ac supply to the load for a controlled fraction of each cycle. In this mode of operation, the triac is held in an off or open condition for a portion of each positive and negative cycle, and then is triggered into an on condition at a time in the half cycle determined by the control circuitry. In the on condition, the circuit current is limited only by the load i.e., the entire line voltage (less the forward drop of the triac) is applied to the load. Figure 2.17 shows the voltage waveform along with some common terms used in describing triac operation. Delay angle is the angle, measured in electrical degrees, during which the triac is blocking the line voltage. The period during which the triac is on is called the conduction angle. It is important to note that the triac is either off (blocking voltage) or fully on (conducting). When it is in the on condition, the circuit current is determined only by the load and the power source. As one might expect, in spite of its usefulness, phase control is not without disadvantages. The main disadvantage of using phase control in triac applications is the generation of electromagnetic interference (EMI). Each time the triac is fired the load current rises from zero to the loadlimited current value in a very short time. The resulting di/dt generates a wide spectrum of noise which may interfere with the operation of nearby electronic equipment unless proper filtering is used.
ZERO POINT SWITCHING
Figure 2.16. Triac VoltageCurrent Characteristic
METHODS OF CONTROL
AC SWITCH
A useful application of triac is as a direct replacement for an ac mechanical relay. In this application, the triac furnishes onoff control and the powerregulating ability of the triac is not utilized. The control circuitry for this application is usually very simple, consisting of a source for the gate signal and some type of small current switch, either mechanical or electrical. The gate signal can be obtained from a separate source or directly from the line voltage at terminal MT2 of the triac.
In addition to filtering, EMI can be minimized by zeropoint switching, which is often preferable. Zero point switching is a technique whereby the control element (in this case the triac) is gated on at the instant the sine wave voltage goes through zero. This reduces, or eliminates, turnon transients and the EMI. Power to the load is controlled by providing bursts of complete sine waves to the load as shown in Figure 2.18. Modulation can be on a random basis with an onoff control, or a proportioning basis with the proper type of proportional control. In order for zeropoint switching to be effective, it must indeed be zero point switching. If a triac is turned on with as little as 10 volts across it into a load of a fewhundred watts, sufficient EMI will result to nullify the advantages of adopting zeropoint switching in the first place. BASIC TRIAC AC SWITCHES Figure 2.19 shows methods of using the triac as an onoff switch. These circuits are useful in applications where simplicity and reliability are important. As previously stated, there is no arcing with the triac, which can be very important in some applications. The circuits are for resistive loads as shown and require the addition of a dv/dt network across the triac for inductive loads.
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Figure 2.19(a) shows lowvoltage control of the triac. When switch S1 is closed, gate current is supplied to the triac from the 10 volt battery. In order to reduce surge current failures during turn on (ton), this current should be 5 to 10 times the maximum gate current (IGT) required to trigger the triac. The triac turns on and remains on until S1 is opened. This circuit switches at zero current except for initial turn on. S1 can be a verylowcurrent switch because it carries only the triac gate current. Figure 2.19(b) shows a triac switch with the same characteristics as the circuit in Figure 2.19(a) except the need for a battery has been eliminated. The gate signal is obtained from the voltage at MT2 of the triac prior to turn on. The circuit shown in Figure 2.19(c) is a modification of Figure 2.19(b). When switch S1 is in position one, the triac receives no gate current and is nonconducting. With S1 in position two, circuit operation is the same as that for Figure 2.19(b). In position three, the triac receives gate current only on positive half cycles. Therefore, the triac conducts only on positive half cycles and the power to the load is half wave. Figure 2.19(d) shows ac control of the triac. The pulse can be transformer coupled to isolate power and control circuits. Peak current should be 10 times IGT(max) and the RC time constant should be 5 times ton(max). A high frequency pulse (1 to 5 kHz) is often used to obtain zero point switching.
VOLTAGE APPLIED TO LOAD
applied to the load as shown in Figure 2.20. This type of switching is primarily used to control power to resistive loads such as heaters. It can also be used for controlling the speed of motors if the duty cycle is modulated by having short bursts of power applied to the load and the load characteristic is primarily inertial rather than frictional. Modulation can be on a random basis with an onoff control, or on a proportioning basis with the proper type of proportioning control. In order for zeropoint switching to be effective, it must be true zeropoint switching. If an SCR is turned on with an anode voltage as low as 10 volts and a load of just a few hundred watts, sufficient EMI will result to nullify the advantages of going to zeropoint switching in the first place. The thyristor to be turned on must receive gate drive exactly at the zero crossing of the applied voltage. The most successful method of zeropoint thyristor control is therefore, to have the gate signal applied before the zero crossing. As soon as the zero crossing occurs, anode voltage will be supplied and the thyristor will come on. This is effectively accomplished by using a capacitor to derive a 90 leading gate signal from the power line source. However, only one thyristor can be controlled from this phaseshifted signal, and a slaving circuit is necessary to control the other SCR to get fullwave power control. These basic ideas are illustrated in Figure 2.21. The slaving circuit fires only on the half cycle after the firing of the master SCR. This guarantees that only complete cycles of power will be applied to the load. The gate signal to the master SCR receives all the control; a convenient control method is to replace the switch with a lowpower transistor, which can be controlled by bridge sensing circuits, manually controlled potentiometers, or various other techniques.
DELAY ANGLE CONDUCTION ANGLE HALF POWER TO LOAD
LOAD VOLTAGE
Figure 2.17. Sine Wave Showing Principles of Phase Control
LINE VOLTAGE
ZERO POINT SWITCHING TECHNIQUES Zeropoint switches are highly desirable in many applications because they do not generate electromagnetic interference (EMI). A zeropoint switch controls sinewave power in such a way that either complete cycles or half cycles of the power supply voltage are
FULL POWER TO LOAD
Figure 2.18. Sine Wave Showing Principles of ZeroPoint Switching
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15 LOAD LOAD VOLTAGE 115 VAC 60 Hz + 10 V R1 47
S1
2N6346 LINE VOLTAGE
(a): Low Voltage Controlled Triac Switch
Figure 2.20. Load Voltage and Line Voltage for 25% Duty Cycle
15 LOAD R1 100 115 VAC 60 Hz S1 2N6342
(b): Triac ac Static Contactor

15 LOAD
S1 115 VAC 60 Hz 3 2 1 2N6342
R1 100
(c): 3 Position Static Switch
15 LOAD
R1
2N6346
(d): AC Controlled Triac Switch Figure 2.19. Triac Switches
A basic SCR is very effective and trouble free. However, it can dissipate considerable power. This must be taken into account in designing the circuit and its packaging. In the case of triacs, a slaving circuit is also usually required to furnish the gate signal for the negative half cycle. However, triacs can use slave circuits requiring less power than do SCRs as shown in Figure 2.21. Other considerations being equal, the easier slaving will sometimes make the triac circuit more desirable than the SCR circuit. Besides slaving circuit power dissipation, there is another consideration which should be carefully checked when using highpower zeropoint switching. Since this is onoff switching, it abruptly applies the full load to the power line every time the circuit turns on. This may cause a temporary drop in voltage which can lead to erratic operation of other electrical equipment on the line (light dimming, TV picture shrinkage, etc.). For this reason, loads with high cycling rates should not be powered from the same supply lines as lights and other voltagesensitive devices. On the other hand, if the load cycling rate is slow, say once per half minute, the loading flicker may not be objectionable on lighting circuits. A note of caution is in order here. The fullwave zeropoint switching control illustrated in Figure 2.21 should not be used as a halfwave control by removing the slave SCR. When the slave SCR in Figure 2.21 is removed, the master SCR has positive gate current flowing over approximately 1/4 of a cycle while the SCR itself is in the reverseblocking state. This occurs during the negative half cycle of the line voltage. When this condition exists, Q1 will have a high leakage current with full voltage applied and will therefore be dissipating high power. This will cause excessive heating of the SCR and may lead to its failure. If it is desirable to use such a circuit as a halfwave control, then some means of clamping the gate signal during the negative half cycle must be devised to inhibit gate current while the SCR is reverse blocking. The circuits shown in Figures 2.23 and 2.24 do not have this disadvantage and may be used as halfwave controls.
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OPERATION
AC LINE 150 1W 2 F 200 V LOAD Q1 (MASTER)
Q2 (SLAVE)
Figure 2.21. Slave and Master SCRs for ZeroPoint Switching
1.2 k 7W AC LINE 150 1W ONOFF CONTROL
2 F 200 V MAC210A8
LOAD
Figure 2.22. Triac ZeroPoint Switch
S1 AC LINE D1 1N4004 R1 3.8 k R2 8.2 k 1W D2 1N4004 C1 D4 0.25 F 1N5760 D3 1N4004 R3 1k LOAD Q1 MCR226
Figure 2.23. SensitiveGate Switch
S1 D1 1N4004 C2 10 nF 200 V R1 3.8 k R2 8.2 k 1W
C1 0.25 F 200 V D3 D4 1N4004 1N5760 D2 1N4004 R3 100
LOAD Q1 MCR2184
AC LINE
Figure 2.24. ZeroPoint Switch
The zeropoint switches shown in Figure 2.23 and 2.24 are used to insure that the control SCR turns on at the start of each positive alternation. In Figure 2.23 a pulse is generated before the zero crossing and provides a small amount of gate current when line voltage starts to go positive. This circuit is primarily for sensitivegate SCRs. Lesssensitive SCRs, with their higher gate currents, normally require smaller values for R1 and R2 and the result can be high power dissipation in these resistors. The circuit of Figure 2.24 uses a capacitor, C2, to provide a lowimpedance path around resistors R1 and R2 and can be used with lesssensitive, highercurrent SCRs without increasing the dissipation. This circuit actually oscillates near the zero crossing point and provides a series of pulses to assure zeropoint switching. The basic circuit is that shown in Figure 2.23. Operation begins when switch S1 is closed. If the positive alternation is present, nothing will happen since diode D1 is reverse biased. When the negative alternation begins, capacitor C1 will charge through resistor R2 toward the limit of voltage set by the voltage divider consisting of resistors R1 and R2. As the negative alternation reaches its peak, C1 will have charged to about 40 volts. Line voltage will decrease but C1 cannot discharge because diode D2 will be reverse biased. It can be seen that C1 and threelayer diode D4 are effectively in series with the line. When the line drops to 10 volts, C1 will still be 40 volts positive with respect to the gate of Q1. At this time D4 will see about 30 volts and will trigger. This allows C1 to discharge through D3, D4, the gate of Q1, R2, and R1. This discharge current will continue to flow as the line voltage crosses zero and will insure that Q1 turns on at the start of the positive alternation. Diode D3 prevents reverse gatecurrent flow and resistor R3 prevents false triggering. The circuit in Figure 2.24 operates in a similar manner up to the point where C1 starts to discharge into the gate. The discharge path will now be from C1 through D3, D4, R3, the gate of Q1, and capacitor C2. C2 will quickly charge from this high pulse of current. This reduces the voltage across D4 causing it to turn off and again revert to its blocking state. Now C2 will discharge through R1 and R2 until the voltage on D4 again becomes sufficient to cause it to break back. This repetitive exchange of charge from C1 to C2 causes a series of gatecurrent pulses to flow as the line voltage crosses zero. This means that Q1 will again be turned on at the start of each positive alternation as desired. Resistor R3 has been added to limit the peak gate current.
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AN SCR SLAVING CIRCUIT
An SCR slaving circuit will provide fullwave control of an ac load when the control signal is available to only one of a pair of SCRs. An SCR slaving circuit is commonly used where the master SCR is controlled by zeropoint switching. Zeropoint switching causes the load to receive a full cycle of line voltage whenever the control signal is applied. The duty cycle of the control signal therefore determines the average amount of power supplied to the load. Zeropoint switching is necessary for large loads such as electric heaters because conventional phaseshift techniques would generate an excessive amount of electromagnetic interference (EMI). This particular slaving circuit has two important advantages over standard RC discharge slaving circuits. It derives these advantages with practically no increase in price by using a lowcost transistor in place of the currentlimiting resistor normally used for slaving. The first advantage is that a large pulse of gate current is available at the zerocrossing point. This means that it is not necessary to select sensitivegate SCRs for controlling power. The second advantage is that this current pulse is reduced to zero within one alternation. This has a couple of good effects on the operation of the slaving SCR. It prevents gate drive from appearing while the SCR is reversebiased, which would produce high power dissipation within the device. It also prevents the slaved SCR from being turned on for additional half cycles after the drive is removed from the control SCR.
OPERATION
C1 is being charged, D1 reversebiases the baseemitter junction of Q3, thereby holding it off. The charging time constant, R1, C1, is set long enough that C1 charges for practically the entire half cycle. The charging rate of C1 follows an S shaped curve, charging slowly at first, then faster as the supply voltage peaks, and finally slowly again as the supply voltage decreases. When the supply voltage falls below the voltage across C1, diode D1 becomes reverse biased and the baseemitter of Q3 becomes forward biased. For the values shown, this occurs approximately 6 before the end of the half cycle conduction of Q1. The base current is derived from the energy stored in C1. This turns on Q3, discharging C1 through Q3 and into the gate of Q2. As the voltage across C1 decreases, the base drive of Q3 decreases and somewhat limits the collector current. The current pulse must last until the line voltage reaches a magnitude such that latching current will exist in Q2. The values shown will deliver a current pulse which peaks at 100 mA and has a magnitude greater than 50 mA when the anode cathode voltage of Q2 reaches plus 10 volts. This circuit completely discharges C1 during the half cycle that Q2 is on. This eliminates the possibility of Q2 being slaved for additional half cycles after the drive is removed from Q1. The peak current and the current duration are controlled by the values of R1 and C1. The values chosen provide sufficient drive for shorted emitter SCRs which typically require 10 to 20 mA to fire. The particular SCR used must be capable of handling the maximum current requirements of the load to be driven; the 8 ampere, 200 V SCRs shown will handle a 1000 watt load.
10 k 2W + 5 F C1 50 V CONTROL SCR Q2 2N6397 R1 1N4004 120 VAC 60 Hz
The SCR slaving circuit shown in Figure 2.25 provides a single power pulse to the gate of SCR Q2 each time SCR Q1 turns on, thus turning Q2 on for the half cycle following the one during which Q1 was on. Q2 is therefore turned on only when Q1 is turned on, and the load can be controlled by a signal connected to the gate of Q1 as shown in the schematic. The control signal an be either dc or a power pulse. If the control signal is synchronized with the power line, this circuit will make an excellent zeropoint switch. During the time that Q1 is on, capacitor C1 is charged through R1, D1 and Q1. While
1000 W MAX
Q1 2N6397
Q3 MPS 3638
INPUT SIGNAL
*1000 WATT LOAD. SEE TEXT.
Figure 2.25. SCR Slave Circuit
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SECTION 3 THYRISTOR DRIVERS AND TRIGGERING
Edited and Updated
1.0 W BASE WIDTH L DIFFUSION LENGTH 0.8
Triggering a thyristor requires meeting its gate energy specifications and there are many ways of doing this. In general, the gate should be driven hard and fast to ensure complete gate turn on and thus minimize di/dt effects. Usually this means a gate current of at least three times the gate turn on current with a pulse rise of less than one microsecond and a pulse width greater than 10 microseconds. The gate can also be driven by a dc source as long as the average gate power limits are met. Some of the methods of driving the gate include: 1) Direct drive from logic families of transistors 2) Opto triac drivers 3) Programmable unijunction transistors (PUTs) 4) SIDACs In this chapter we will discuss all of these, as well as some of the important design and application considerations in triggering thyristors in general. In the chapter on applications, we will also discuss some additional considerations relating to drivers and triggers in specific applications. PULSE TRIGGERING OF SCRs
GATE TURNON MECHANISM
a , COMMON BASE CURRENT GAIN
W L
+ 0.1
W L
0.6
+ 0.5
W L
+ 1.0
0.4
0.2
0 103
102
101
1.0
10
102
EMITTER CURRENT DENSITY (mA/mm2)
Figure 3.1. Typical Variation of Transistor with Emitter Current Density
The turnon of PNPN devices has been discussed in many papers where it has been shown that the condition of switching is given by dv = 0 (i.e., 1 + 2 = 1, where 1 di and 2 are the current amplification factors of the two transistors. However, in the case of an SCR connected to a reverse gate bias, the device can have 1 + 2 = 1 and still stay in the blocking state. The condition of turnon is actually 1 + 2 1. The current amplification factor, , increases with emitter current; some typical curves are shown in Figure 3.1. The monotonical increase of with IE of the device in the blocking state makes the regeneration of current (i.e., turnon) possible.
Using the two transistor analysis, the anode current, IA, can be expressed as a function of gate current, IG, as:
I
a2 IG ) ICS1 ) ICS2 + A 1*a *a

1 2
(1)
Definitions and derivations are given in Appendix I. Note that the anode current, IA, will increase to infinity as 1 + 2 = 1. This analysis is based upon the assumption that no majority carrier current flows out of the gate circuit. When no such assumption is made, the condition for turnon is given by:
IK IA
a1 +1* a
2
(2)
which corresponds to 1 + 2
u1 (see Appendix I).
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J1 IA ANODE (A) P1 N1
J2
J3 IK P2 N2 CATHODE (K)
CURRENT PULSE TRIGGERING Current pulse triggering is defined as supplying current through the gate to compensate for the carriers lost by recombination in order to provide enough current to sustain increasing regeneration. If the gate is triggered with a current pulse, shorter pulse widths require higher currents as shown by Figure 3.3(a). Figure 3.3(a) seems to indicate there is a constant amount of charge required to trigger on the device when IG is above a threshold level. When the charge required for turnon plotted versus pulse current or pulse width, there is an optimum range of current levels or pulse widths for which the charge is minimum, as shown in region A of Figure 3.3(b) and (c). Region C shows that for lower current levels (i.e., longer minimum pulse widths) more charge is required to trigger on the device. Region B shows increasing charge required as the current gets higher and the pulse width smaller.
IG GATE (G)
Figure 3.2. Schematic Structure of an SCR, Positive Currents Are Defined as Shown by the Arrows
Current regeneration starts when charge or current is introduced through the gate (Figure 3.2). Electrons are injected from the cathode across J3; they travel across the P2 base region to be swept out by the collector junction, J2, and thrown into the N1 base. The increase of majority carrier electrons in region N1 decreases the potential in region N1, so that holes from P1 are injected across the junction J1, into the N1 base region to be swept across J2, and thrown into the P2 base region. The increase in the potential of region P2 causes more electrons to be injected into P2, thereby repeating the cycle. Since increases with the emitter current, an increase of regeneration takes place until 1 + 2 1. Meanwhile, more carriers are collected than emitted from either of the emitters. The continuity of charge flow is violated and there is an electron buildup on the N1 side of J2, and a hole buildup on the P2 side. When the inert impurity charges are compensated for by injected majority carriers, the junction J2 becomes forward biased. The collector emits holes back to J1 and electrons to J3 until a steady state continuity of charge is established. During the regeneration process, the time it takes for a minority carrier to travel across a base region is the transit time, t, which is given approximately as:
100 VAK = 10 V TA = 25C i G , MINIMUM GATE TRIGGER CURRENT (mA) 80
60
HIGH UNIT
40 LOW UNIT 20 IG THRESHOLD
t1
W2 i 2D i
where Wi
+ base width D i + diffusion length
(3)
0 0.05
0.1
0.2
0.5
1.0
2.0
5.0
10
(The subscript i can be either 1 or 2 to indicate the appropriate base.) The time taken from the start of the gate trigger to the turnon of the device will be equal to some multiple of the transit time.
t, PULSE WIDTH (ms)
Figure 3.3(a). Typical Variation of Minimum Gate Current Required to Trigger
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100 VAK = 10 V TA = 25C
100 VAK = 10 V T = 25C HIGH UNIT
50 Qin, MINIMUM TRIGGER CHARGE (nc) I G THRESHOLD
50 Q in , MINIMUM TRIGGER CHARGE (nc)
20
LOW UNIT
HIGH UNIT
(Q = it) 20 B 10 LOW UNIT A C
10
I G THRESHOLD
5.0
5.0
2.0
2.0
1.0 2.0 5.0 10 20 50 100 iG, GATE CURRENT (mA)
1.0 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 t, MINIMUM PULSE WIDTH (ms)
Figure 3.3(b). Variation of Charge versus Gate Current
Figure 3.3(c). Variation of Charge versus Minimum Pulse Width
The charge characteristic curves can be explained qualitatively by the variation of current amplification (T) with respect to emitter current. A typical variation of 1 and 2 for a thyristor is shown in Figure 3.4(a). From Figure 3.4(a), it can be deduced that the total current amplification factor, T = 1 + 2, has a characteristic curve as shown in Figure 3.4(b). (The data does not correspond to the data of Figure 3.3 they are taken for different types of devices.) The gate current levels in region A of Figure 3.3 correspond to the emitter (or anode) currents for which the slope of the T curve is steepest (Figure 3.4(b)). In region A the rate that T builds up with respect to changes of IE (or IA) is high, little charge is lost by recombination, and therefore, a minimum charge is required for turnon. In region C of Figure 3.3, lower gate current corresponds to small IE (or IA) for which the slope of T, as well as T itself, is small. It takes a large change in IE (or IA) in order to build up T. In this region, a lot of the turnon the device should be large enough to flood the gate to cathode junction nearly instantaneously with a
charge supplied through the gate is lost by recombination. The charge required for turnon increases markedly as the gate current is decreased to the threshold level. Below this threshold, the device will not turn on regardless of how long the pulse width becomes. At this point, the slope of T is equal to zero; all of the charge supplied is lost completely in recombination or drained out through gatecathode shunt resistance. A qualitative analysis of variation of charge with pulse width at region A and C is discussed in Appendix II. In region B, as the gate current level gets higher and the pulse width smaller, there are two effects that contribute to an increasing charge requirement to triggeron the device: (1) the decreasing slope of T and, (2) the transit time effect. As mentioned previously, it takes some multiple of the transit time for turnon. As the gate pulse width decreases to N (tN1 + tP2) or less, (where N is a positive real number, tN1 = transit time of base N1, and tP2 = transit time of base P2) the amount of current required to charge which corresponds to IE (or IA) high enough to give T 1.
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1.0 NPN SECTION a2
1.4
1.2 0.8
a , CURRENT AMPLIFICATION FACTOR
a , CURRENT AMPLIFICATION FACTOR
B 1.0 A 0.8
0.6
0.4
0.6
PNP SECTION a1
0.4
0.2 0.2
0 0.1 1.0 10 100 300 IE, EMITTER CURRENT (mA)
0 0.1 1.0 10 100 300 IE, EMITTER CURRENT (mA)
Figure 3.4(a). The Variation of 1 and 2 with Emitter Current for the Two Sections of Two Typical Silicon Controlled Rectifiers
Figure 3.4(b). Typical Variation of T versus Emitter Current
CAPACITANCE CHARGE TRIGGERING Using a gate trigger circuit as shown in Figure 3.5, the charge required for turnon increases with the value of
capacitance used as shown in Figure 3.7. Two reasons may account for the increasing charge characteristics: 1) An effect due to threshold current. 2) An effect due to variation of gate spreading resistance.
90%
r G1
) RS
DV2
DV1
r G1
) RS
r G2
DV1
(r G 1
e *t ) RS)C1
TO COMMUTATING CIRCUIT SCR C
r G2
10%
) RS

I II tf1 tf2 PULSE WIDTH, t
DV2 *t ) RS e * (rG2 ) RS)C2

Ithr
RS
D V1
0
tfi = 2.2 (rG1 + RS)C1 SHADED AREA I = |(rG1 + RS)(C1)|(Ithr) SHADED AREA II = |(rG2 + RS)(C2)|(Ithr) |(rG1 + RS)(C1)|(Ithr) < |(rG2 + RS)(C2) |(Ithr)
DV1C1 + DV2C2
C1
t C2
Figure 3.5. Gate Circuit of Capacitance Charge Triggering
Figure 3.6. Gate Current Waveform in Capacitance Charge Triggering
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Consider the gate current waveform in Figure 3.6; the triggering pulse width is made large enough such that tfl; the threshold trigger current is shown as Ithr. All of the charge supplied at a transient current level less than Ithr is lost by recombination, as shown in the shaded regions. The gate spreading resistance (rG) of the gate junction varies inversely with peak current; the higher the peak current, the smaller the gate spreading resistance. Variation of gate spreading resistance measured by the method of Time Domain Reflectometry is plotted in Figure 3.8. From the data of Figure 3.7, it is clear that for larger values of capacitance a lower voltage level is required for turnon. The peak current of the spike in Figure 3.6 is
3.0 NORMALIZED GATE SPREADING RESISTANCE 2.0 IA = 1 A TA = 25C VAK = 10 V
uu
HIGH UNIT
1.0 0.7 0.5 Z0 = 50 LOW UNIT
0.3 0.2 0.1
W
50 100 200 500 1000
given by Ipk
Ipk. Smaller Ipk in turn yields large rG, so that rG is dependent on the value of capacitance used in capacitance charge triggering. This reasoning is confirmed by measuring the fall time of the gate trigger voltage and calculating the transient gate spreading resistance, rG, from: R s Figure 3.9. As expected, rG increases with increasing values of capacitance used. Referring back to Figure 3.6, for the same amount of charge (C V), the larger the (Rs + rG)C time constant of the current spike, the more charge under the threshold level is lost in recombination. Increasing the value of C will increase the time constant more rapidly than if rG were invariant. Therefore, increasing the value of C should increase the charge lost as shown in Figure 3.7. Note that a two order of magnitude increase in capacitance increased the charge by less than 3:1.
V + Rs ) rG ; the smaller V, the smaller
20
GATE CURRENT (mA)
Figure 3.8. Variation of Gate Spreading Resistance versus Gate Peak Current
) rG + 2.2tf C .
Results
are
plotted
in
EFFECT OF TEMPERATURE The higher the temperature, the less charge required to turn on the device, as shown in Figure 3.10. At the range of temperatures where the SCR is operated the life time of minority carriers increases with temperature; therefore less charge into the gate is lost in recombination. As analyzed in Appendix II, there are three components of charge involved in gate triggering: (1) Qr, charge lost in recombination, (2) Qdr, charge drained out through the builtin gatecathode shunt resistance, (3) Qtr, net charge for triggering. All of them are temperature dependent. Since the temperature coefficient of voltage across a pn junction is small, Qdr may be considered invariant of temperature. At the temperature range of operation, the temperature is too low to give rise to significant impurity gettering, lifetime increases with temperature causing Qr to decrease with increasing temperature. Also, Qtr decreases with increasing temperature because at a constant current the T of the device in the blocking state increases with temperature;7 in other words, to attain T = 1 at an elevated temperature, less anode current, hence gate current [see equation (3) of Appendix I], is needed; therefore, Qtr decreases. The input charge, being equal to the sum of Qtr, Qr, and Qdr, decreases with increasing temperature. The minimum current trigger charge decreases roughly exponentially with temperature. Actual data taken on an MCR729 deviate somewhat from exponential trend (Figure 3.10). At higher temperatures, the rate of decrease is less; also for different pulse widths the rates of decrease of Qin are different; for large pulse widths the recombination charge becomes more significant than that of small pulse widths. As the result, it is expected and Figure 3.10 shows that Qin decreases more rapidly with temperature at high pulse widths. These effects are analyzed in
15 Q in , MINIMUM TRIGGER CHARGE, Q(nc) 10 VAK = 10 V TA = 15C HIGH UNIT
7.0 5.0 LOW UNIT
3.0
2.0
PULSE WIDTH = 50 ms 1.0 100 200 500 1000 2000 5000 10,000 C, CAPACITANCE (pF)
Figure 3.7. Variation of Trigger Charge versus Capacitance Used
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Appendix II [equation (7), page 242]. The theory and experiment agree reasonably well.
EFFECT OF BLOCKING VOLTAGE An SCR is an avalanche mode device; the turnon of the device is due to multiplication of carriers in the middle collector junction. The multiplication factor is given by the empirical equation
M
40 VAK = 10 V T = 25C r G , GATE SPREADING RESISTANCE ( )
where M
1 ( V )n VB
(6)
30
5 Multiplication factor V 5 Voltage across the middle collector junction

(R S
20
) rG ) 2.2C
tf
5 Breakdown voltage of the middle collector junction n 5 Some positive number

VB
(voltage at which the device is blocking prior to turnon)
10
Note as V is increased, M also increases and in turn increases (the current amplification factor = M where Emitter efficiency, Base transport factor, and Factor of recombination).
0 200 300 500 1000 2000 C, CAPACITANCE (pF)
Figure 3.9. Variation of Transient Base Spreading Resistance versus Capacitance
The larger the V, the larger is T. It would be expected for the minimum gate trigger charge to decrease with increasing V. Experimental results show this effect (see Figure 3.11). For the MCR729, the gate trigger charge is only slightly affected by the voltage at which the device is blocking prior to turnon; this reflects that the exponent, n, in equation (6) is small. EFFECT OF GATE CIRCUIT
20 VAK = 10 V t = GATE CURRENT PULSE WIDTH (Q = it) Q in , MINIMUM TRIGGER CHARGE (nc)
10 9.0 8.0 7.0 t = 300 ns
t=1 s
As mentioned earlier, to turn on the device, the total amplification factor must be greater than unity. This means that if some current is being drained out of the gate which bleeds the regeneration current, turnon will be affected. The higher the gate impedance, the less the gate trigger charge. Since the regenerative current prior to turnon is small, the gate impedance only slightly affects the required minimum trigger charge; but in the case of overdriving the gate to achieve fast switching time, the gate circuit impedance will have noticeable effect. EFFECT OF INDUCTIVE LOAD The presence of an inductive load tends to slow down the change of anode current with time, thereby causing the required charge for triggering to increase with the value of inductance. For dc or long pulse width current triggering, the inductive load has little effect, but its effect increases markedly at short pulse widths, as shown in Figure 3.12. The increase in charge occurs because at short pulse widths, the trigger signal has decreased to a negligible value before the anode current has reached a level sufficient to sustain turnon.
t = 500 ns 6.0 5.0 t = 100 ns
4.0 15 +25 +65 +105 T, TEMPERATURE (C)
Figure 3.10. Variation of Q versus Temperature
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10 9.0 8.0 7.0 6.0 Q in , MINIMUM TRIGGER CHARGE (nc) 5.0 #3 4.0 #2
USING NEGATIVE BIAS AND SHUNTING Almost all SCRs exhibit some degree of turnoff gain. At normal values of anode current, negative gate current will not have sufficient effect upon the internal feedback loop of the device to cause any significant change in anode current. However, it does have a marked effect at low anode current levels; it can be put to advantage by using it to modify certain device parameters. Specifically, turnoff time may be reduced and hold current may be increased. Reduction of turnoff time and increase of hold current are useful in such circuits as inverters or in fullwave phase control circuits in which inductance is present. Negative gate current may, of course, be produced by use of an external bias supply. It may also be produced by taking advantage of the fact that during conduction the gate is positive with respect to the cathode and providing an external conduction path such as a gatetocathode resistor. All ON Semiconductor SCRs, with the exception of sensitive gate devices, are constructed with a built in gatetocathode shunt, which produces the same effect as negative gate current. Further change in characteristics can be produced by use of an external shunt. Shunting does not produce as much of a change in characteristics as does negative bias, since the negative gate current, even with an external short circuit, is limited by the lateral resistance of the base layer. When using external negative bias the current must be limited, and care must be taken to avoid driving the gate into the avalanche region. The effects of negative gate current are not shown on the device specification sheets. The curves in Figure 3.13 represent measurements made on a number of SCRs, and should therefore not be considered as spec limits. They do, however, show definite trends. For example, all of the SCRs showed an improvement in turnoff time of about onethird by using negative bias up to the point where no further significant improvement was obtained. The increase in hold current by use of an external shunt resistor ranged typically between 5 and 75 percent, whereas with negative bias, the range of improvement ran typically between 21/2 and 7 times the open gate value. Note that the holding current curves are normalized and are referred to the open gate value.
#1
3.0
2.0 TA = 25C PW = 500 ns 0.05 mF CAP. DISCHARGE 1.0 10 20 30 50 100 200 500 1000 VAK, ANODE VOLTAGE (V)
Figure 3.11. Variation of Current Trigger Charge versus Blocking Voltage Prior to TurnOn
80
Q in , MINIMUM TRIGGER CHARGE (nc)
60 L = 100 mH
40 L = 10 mH L = 0 mH 20 TA = 25C VAK = 10 V 0 30 50 70 100 200 300 500 700 1000 t, MINIMUM PULSE WIDTH (ns)
Figure 3.12. Effect of Inductance Load on Triggering Charge
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SPREAD OF 5 DEVICES 1.6
REDUCING di/dt EFFECT FAILURES Figure 3.14 shows a typical SCR structural cross section (not to scale). Note that the collector of transistor 1 and the base of transistor 2 are one and the same layer. This is also true for the collector of transistor 2 and the base of transistor 1. Although for optimum performance as an SCR the base thicknesses are great compared to a normal transistor, nevertheless, base thickness is still small compared to the lateral dimensions. When applying positive bias to the gate, the transverse base resistance, spreading resistance or rb will cause a lateral voltage drop which will tend to forward bias those parts of the transistor 1 emitterjunction closest to the base contact (gate) more heavily, or sooner than the portions more remote from the contact area. Regenerative action, consequently will start in an area near the gate contact, and the SCR will turn on first in this area. Once on, conduction will propagate across the entire junction.
LAYER NO. 4 NO. 3 (C) (B) (E) T2 T1 (E) (B) (C) CATHODE GATE
NORMALIZED HOLDING CURRENT
1.4
1.2
1.0 1.0 10 100 1000 5000
GATETOCATHODE RESISTANCE (OHMS)
Figure 3.13(a). Normalized Holding Current versus GatetoCathode Resistance

SPREAD OF 5 DEVICES 6.0 NORMALIZED HOLDING CURRENT
4.0
NO. 2 NO. 1
2.0
0 0 2.0 4.0 6.0 8.0 10 GATETOCATHODE VOLTAGE (VOLTS)
Figure 3.14. Construction of Typical SCR

N P N P ANODE
Figure 3.13(b). Normalized Holding Current versus GatetoCathode Voltage

AVERAGE 10 DEVICES 6.0
TURNOFF TIME ( m s)
IF = 10 A 4.0 IF = 5 A 2.0
0 0 5.0 GATETOCATHODE VOLTAGE (VOLTS) 10
Figure 3.13(c). TurnOff Time versus Bias
The phenomenon of di/dt failure is related to the turnon mechanism. Let us look at some of the external factors involved and see how they contribute. Curve 3.15(a) shows the fall of anodetocathode voltage with time. This fall follows a delay time after the application of the gate bias. The delay time and fall time together are called turnon time, and, depending upon the device, will take anywhere from tens of nanoseconds up to a few microseconds. The propagation of conduction across the entire junction requires a considerably longer time. The time required for propagation or equalization of conduction is represented approximately by the time required for the anodetocathode voltage to fall from the 10 percent point to its steady state value for the particular value of anode current under consideration (neglecting the change due to temperature effects). It is during the interval of time between the start of the fall of anodetocathode voltage and the final equalization of conduction that the SCR is most susceptible to damage from excessive current.
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Let us superimpose a current curve (b) on the anodeto cathode voltage versus time curve to better understand this. If we allow the current to rise rapidly to a high value we find by multiplying current and voltage that the instantaneous dissipation curve (c) reaches a peak which may be hundreds of times the steady state dissipation level for the same value of current. At the same time it is important to remember that the dissipation does not take place in the entire junction, but is confined at this time to a small volume. Since temperature is related to energy per unit volume, and since the energy put into the device at high current levels may be very large while the volume in which it is concentrated is very small, very high spot temperatures may be achieved. Under such conditions, it is not difficult to attain temperatures which are sufficient to cause localized melting of the device. Even if the peak energy levels are not high enough to be destructive on a singleshot basis, it must be realized that since the power dissipation is confined to a small area, the power handling capabilities of the device are lessened. For pulse service where a significant percentage of the power per pulse is dissipated during the falltime interval, it is not acceptable to extrapolate the steady state power dissipation capability on a duty cycle basis to obtain the allowable peak pulse power.
ANODE TO CATHODE VOLTAGE (a) 100 PERCENT OF MAXIMUM (%) INSTANTANEOUS POWER DISSIPATION (c) 50 ANODE CURRENT (b)
tion is not useful, however, for determining the limitations of the device before the entire junction is in conduction, because they are based on measurements made with the entire junction in conduction. At present, there is no known technique for making a reasonably accurate measurement of junction temperature in the time domain of interest. Even if one were to devise a method for switching a sufficiently large current in a short enough time, one would still be faced with the problem of charge storage effects in the device under test masking the thermal effects. Because of these and other problems, it becomes necessary to determine the device limitations during the turnon interval by destructive testing. The resultant information may be published in a form such as a maximum allowable current versus time, or simply as a maximum allowable rate of rise of anode current (di/dt). Understanding the di/dt failure mechanism is part of the problem. To the user, however, a possible cure is infinitely more important. There are three approaches that should be considered. Because of the lateral base resistance the portion of the gate closest to the gate contact is the first to be turned on because it is the first to be forward biased. If the minimum gate bias to cause turnon of the device is used, the spot in which conduction is initiated will be smallest in size. By increasing the magnitude of the gate trigger pulse to several times the minimum required, and applying it with a very fast rise time, one may considerably increase the size of the spot in which conduction starts. Figure 3.16(a) illustrates the effect of gate drive on voltage fall time and Figure 3.16(b) shows the improvement in instantaneous dissipation. We may conclude from this that overdriving the gate will improve the di/dt capabilities of the device, and we may reduce the stress on the device by doing so.
350 ANODE TO CATHODE VOLTAGE (VOLTS) 300 PEAK ANODE CURRENT = 500 A 250 200 IGT = 2 A 150 IGT = 17 mA 100 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t, TIME (ms)
0 0.1 1.0 TIME (ms)
Figure 3.15. Typical Conditions FastRise, High Current Pulse
The final criterion for the limit of operation is junction temperature. For reliable operation the instantaneous junction temperature must always be kept below the maximum junction temperature as stated on the manufacturers data sheet. Some SCR data sheets at present include information on how to determine the thermal response of the junction to current pulses. This informa-
Figure 3.16(a). Effect of Gate Drive on Fall Time
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A very straightforward approach is to simply slow down the rate of rise of anode current to insure that it stays within the device ratings. This may be done simply by adding some series inductance to the circuit.
WHY AND HOW TO SNUB THYRISTORS Inductive loads (motors, solenoids, etc.) present a problem for the power triac because the current is not in phase with the voltage. An important fact to remember is that since a triac can conduct current in both directions, it has only a brief interval during which the sine wave current is passing through zero to recover and revert to its blocking state. For inductive loads, the phase shift between voltage and current means that at the time the current of the power handling triac falls below the holding current and the triac ceases to conduct, there exists a certain voltage which must appear across the triac. If this voltage appears too rapidly, the triac will resume conduction and control is lost. In order to achieve control with certain inductive loads, the rate of rise in voltage (dv/dt) must be limited by a series RC network placed in parallel with the power triac as shown in Figure 3.18. The capacitor CS will limit the dv/dt across the triac. The resistor RS is necessary to limit the surge current from CS when the triac conducts and to damp the ringing of the capacitance with the load inductance LL. Such an RC network is commonly referred to as a snubber. Figure 3.19 shows current and voltage waveforms for the power triac. Commutating dv/dt for a resistive load is typically only 0.13 V/s for a 240 V, 50 Hz line source and 0.063 V/s for a 120 V, 60 Hz line source. For inductive loads the turnoff time and commutating dv/dt stress are more difficult to define and are affected by a number of variables such as back EMF of motors and the ratio of inductance to resistance (power factor). Although it may appear from the inductive load that the rate or rise is extremely fast, closer circuit evaluation reveals that the commutating dv/dt generated is restricted to some finite value which is a function of the load reactance LL and the device capacitance C but still may exceed the triacs critical commutating dv/dt rating which is about 50 V/s. It is generally good practice to use an RC snubber network across the triac to limit the rate of rise (dv/dt) to a value below the maximum allowable rating. This snubber network not only limits the voltage rise during commutation but also suppresses transient voltages that may occur as a result of ac line disturbances. There are no easy methods for selecting the values for RS and CS of a snubber network. The circuit of Figure 3.18 is a damped, tuned circuit comprised of RS, CS, RL and LL, and to a minor extent the junction capacitance of the triac. When the triac ceases to conduct (this occurs every half cycle of the line voltage when the current falls below the holding current), the triac receives a step impulse of line voltage which depends on the power factor of the load. A given load fixes RL and LL; however, the circuit designer can vary RS and CS. Commutating dV/dt can be lowered by increasing CS while RS can be increased to decrease resonant over ringing of the tuned circuit.
INSTANTANEOUS POWER DISSIPATION (kW)
70 60 PEAK ANODE CURRENT = 500 A 50 IGT = 2 A 40 IGT = 17 mA 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t, TIME (ms)
Figure 3.16(b). Effect of Gate Drive On TurnOn Dissipation
If the application should require a rate of current rise beyond the rated di/dt limit of the device, then another approach may be taken. The device may be turned on to a relatively low current level for a sufficient time for a large part of the junction to go into conduction; then the current level may be allowed to rise much more rapidly to very high levels. This might be accomplished by using a delay reactor as shown in Figure 3.17. Such a reactor would be wound on a square loop core so that it would have sharp saturation characteristic and allow a rapid current rise. It is also possible to make use of a separate saturation winding. Under these conditions, if the delay is long enough for the entire junction to go into conduction, the power handling capabilities of the device may be extrapolated on a duty cycle basis.
+ SCR
RL DELAY REACTOR
Figure 3.17. Typical Circuit Use of a Delay Reactor
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BASIC CIRCUIT ANALYSIS

RS AC CS
2 ZERO CROSSING CIRCUIT
4 LL LOAD RL
Figure 3.18. Triac Driving Circuit with Snubber

IF(ON)
Figure 3.20 shows an equivalent circuit used for analysis, in which the triac has been replaced by an ideal switch. When the triac is in the blocking or nonconducting state, represented by the open switch, the circuit is a standard RLC series network driven by an ac voltage source. The following differential equation can be obtained by summing the voltage drops around the circuit;
(R L q c(t) ) RS) i(t) ) L di(t) ) + VMsin(wt ) f) dt CS (2)
IF(OFF)
AC LINE VOLTAGE
AC CURRENT COMMUTATING dv/dt VOLTAGE ACROSS POWER TRIAC
t0 TIME RESISTIVE LOAD
IF(ON)
IF(OFF)
in which i(t) is the instantaneous current after the switch opens, qc(t) is the instantaneous charge on the capacitor, VM is the peak line voltage, and is the phase angle by which the voltage leads the current prior to opening of the switch. After differentiation and rearrangement, the equation becomes a standard secondorder differential equation with constant coefficients. With the imposition of the boundary conditions that i(o) = 0 and qc(o) = 0 and with selected values for RL, L, RS and CS, the equation can be solved, generally by the use of a computer. Having determined the magnitude and time of occurrence of the peak voltage across the thyristor, it is then possible to calculate the values and times of the voltages at 10% and 63% of the peak value. This is necessary in order to compute the dv/dt stress as defined by the following equation:
dv dt
AC LINE VOLTAGE
* V1 + Vt2 2 * t1
0 AC CURRENT THROUGH POWER TRIAC d COMMUTATING dv/dt VOLTAGE ACROSS POWER TRIAC
t0 TIME INDUCTIVE LOAD
Figure 3.19. Current and Voltage Waveforms During Commutation
where V1 and t1 are the voltage and time at the 10% point and V2 and t2 are the voltage and time at the 63% point. Solution of the differential equation for assumed load conditions will give the circuit designer a starting point for selecting RS and CS. Because the design of a snubber is contingent on the load, it is almost impossible to simulate and test every possible combination under actual operating conditions. It is advisable to measure the peak amplitude and rate of rise of voltage across the triac by use of an oscilloscope, then make the final selection of RS and CS experimentally. Additional comments about circuit values for SCRs and Triacs are made in Chapter 6.
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L LOAD AC POWER SOURCE
RL RS CS
Figure 3.20. Equivalent Circuit used for Analysis
USING SENSITIVE GATE SCRs In applications of sensitive gate SCRs such as the ON Semiconductor 2N6237, the gatecathode resistor, RGK (Figure 3.21) is an important factor. Its value affects, in varying degrees, such parameters as IGT, VDRM, dv/dt, IH, leakage current, and noise immunity.
ANODE (A)
Figure 3.22(a) shows the construction of a sensitive gate SCR and the path taken by leakage current flowing out through RGK. Large SCRs (Figure 3.22(b)) keep the path length small by bringing the gate layer up to contact the cathode metal. This allows the current to siphon out allround the cathode area. When the chip dimensions are small there is little penalty in placing the resistor outside the package. This gives the circuit designer considerable freedom in tailoring the electrical properties of the SCR. This is a great advantage when low trigger or holding current is needed. Still, there are tradeoffs in the maximum allowable junction temperature and dV/dt immunity that go with larger resistor values. Verifying that the design is adequate to prevent circuit upset by heat or noise is important. The rated value for RGK is usually 1 K Ohm. Lower values improve blocking and turnoff capability.
K K G DIFFUSED CATHODE G METAL P N P DIFFUSED BASE DIFFUSED K EMITTER SHORTS G
GATE (G)
N + RGK A
N P N P
CATHODE (K)

A A CASE CASE (a). SIMPLE CONSTRUCTION (b). SHORTED EMITTER CONSTRUCTION
Figure 3.21. GateCathode Resistor, RGK
Figure 3.22. Sensitive Gate SCR Construction
SCR CONSTRUCTION The initial step in making an SCR is the creation, by diffusion, of Ptype layers is Ntype silicon base material. Prior to the advent of the alldiffused SCR, the next step was to form the gatecathode PN junction by alloying in a goldantimony foil. This produced a silicon PN junction of the regrown type over most of the junction area. However, a resistive rather than semiconductor junction would form where the molten alloy terminated at the surface. This formed an internal RGK, looking in at the gatecathode terminals, that reduced the sensitivity of the SCR. Modern practice is to produce the gatecathode junction by masking and diffusing, a much more controllable process. It produces a very clean junction over the entire junction area with no unwanted resistive paths. Good dv/dt performance by larger SCRs, however, requires resistive paths distributed over the junction area. These are diffused in as emitter shorts and naturally desensitize the device. Smaller SCRs may rely on an external RGK because the lateral resistance in the gate layer is small enough to prevent leakage and dV/dt induced currents from forward biasing the cathode and triggering the SCR.
The sensitive gate SCR, therefore, is an alldiffused design with no emitter shorts. It has a very high impedance path in parallel with the gatecathode PN diode; the better the process is the higher this impedance, until a very good device cannot block voltage in the forward direction without an external RGK. This is so, because thermally generated leakage currents flowing from the anode into the gate junction are sufficient to turn on the SCR. The value for RGK is usually one kilohm and its presence and value affects many other parameters. FORWARD BLOCKING VOLTAGE AND CURRENT, VDRM AND IDRM The 2N6237 family is specified to have an IDRM, or anodetocathode leakage current, of less than 200 A at maximum operating junction temperature and rated VDRM. This leakage current increases if RGK is omitted and, in fact, the device may well be able to regenerate and turn on. Tests were run on several 2N6239 devices to establish the dependency of the leakage current on RGK and to determine its relationship with junction temperature, TJ, and forward voltage VAK (Figure 3.23a).
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Figure 3.23(a) is a plot of VAK, forward voltage, versus RGK taken at the maximum rated operating junction temperature of 110C. With each device the leakage current, IAK, is set for a VAK of 200 V, then VAK reduced and RGK varied to reestablish the same leakage current. The plot shows that the leakage current is not strongly voltage dependent or, conversely, RGK may not be increased for derate. While the leakage current is not voltage dependent, it is very temperature dependent. The plot in Figure 3.23(b) of TJ, junction temperature, versus RGK taken at VDRM, the maximum forward blocking voltage shows this dependence. For each device (2N6329 again) the leakage current, IAK, was measured at the maximum operating junction temperature of 110C, then the junction temperature was reduced and RGK varied to reestablish that same leakage current. The plot shows that the leakage current is strongly dependent on junction temperature. Conversely RGK may be increased for derated temperature. A conservative rule of thumb is that leakage doubles every 10C. If all the current flows out through RGK, triggering will not occur until the voltage across RGK reaches VGT. This implies an allowed doubling of the resistor for every 10 reduction in maximum junction temperature. However, this rule should be applied with caution. Static dV/dt may require a smaller resistor than expected. Also the leakage current does not always follow the 10 rule below 70C because of surface effects. To summarize, the leakage current in a sensitive gate SCR is much more temperature sensitive than voltage sensitive. Operation at lower junction temperatures allows an increase in the gatecathode resistor which makes the SCRresistor combination more sensitive.
200 2N6239 TJ = 110C IAK CONSTANT
110 2N6239 VAK = VDRM = 200 V IAK CONSTANT
100
TJ ( C)
90
80
70 60 1K 5K 10 K RGK (OHMS) 50 K 100 K
Figure 3.23(b). TJ versus RGK (Typical) for Constant Leakage Current
dv/dt
CAG i RGK
Figure 3.23(c). dv/dt Firing of an SCR
dv/dt, RATE OF RISE OF ANODE VOLTAGE (V/ s)
1,000V/ s
MCR7066 TJ = 110C 400 V PEAK EXPONENTIAL METHOD IGT = 27 A
180 VAK (VOLTS)
100V/ s
160
140
10V/ s
IGT = 5.6 A
120 100 0 1K RGK (OHMS) 2K 3K
1V/ s 10
100
1,000 RGK ( )
10,000
100,000
Figure 3.23(a). VAK versus RGK (Typical) for Constant Leakage Current
Figure 3.23(d). Static dv/dt as a function of GateCathode Resistance on two devices with different sensitivity.
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RATEOFRISE OF ANODE VOLTAGE, dv/dt An SCRs junctions exhibit capacitance due to the separation of charge when the device is in a blocking state. If an SCR is subjected to forward dv/dt, this capacitance can couple sufficient current into the SCRs gate to turn it on, as shown in Figure 3.23(c). RGK acts as a diversionary path for the dv/dt current. (In larger SCRs, where the lateral gate resistance of the device limits the influence of RGK, this path is provided by the resistive emitter shorts mentioned previously.) The gatecathode resistor, then, might be expected to have some effect on the dv/dt performance of the SCR. Figure 3.23(d) confirms this behavior. The static dV/dt for two MCR706 devices varies over several powers of ten with changes in the gatecathode resistance. Selection of the external resistor allows the designer to trade dynamic performance with the amount of drive current provided to the resistorSCR combination. The sensitivegate device with low RGK provides performance approaching that of an equivalent nonsensitive SCR. This strong dependence does not exist with conventional shorted emitter SCRs because of their internal resistor. The conventional SCR cannot be made more sensitive, but the sensitivegate device attributes can be reliably set with the resistor to any desired point along the sensitivity range. Low values of resistance make the dV/dt performance more uniform and predictable. The curves for two devices with different sensitivity diverge at high values of resistance because the device response becomes more dependent on its sensitivity. The resistor is the most important factor determining the static dV/dt capability of the product. Reverse biasing the gate also improves dV/dt. A 2N6241 improved by a factor of 50 with a 1 volt bias. GATE CURRENT, IGT The total gate current that a gating circuit must supply is the sum of the current that the device itself requires to fire and the current flowing to circuit ground through RGK, as shown in Figure 3.24. IGT, the current required by the device so that it may fire, is usually specified by the device manufacturer as a maximum at some temperature (for the 2N6236 series it is 500 A maximum at 40C). The current flowing through RGK is defined by the resistor value and by the gatetocathode voltage that the SCR needs to fire. This is 1 V maximum at 40C for the 2N6237 series, for example.
ITOT VGT RGK IGT IR
GATE CURRENT, IGT(min) SCR manufacturers sometimes get requests for a sensitivegate SCR specified with an IGT(min), that is, the maximum gate current that will not fire the device. This requirement conflicts with the basic function of a sensitive gate SCR, which is to fire at zero or very low gate current, IGT(max). Production of devices with a measurable IGT(min) is at best difficult and deliveries can be sporadic! One reason for an IGT(min) requirement might be some measurable offstate gating circuit leakage current, perhaps the collector leakage of a driving transistor. Such current can readily be bypassed by a suitably chosen RGK. The VGT of the SCR at the temperature in question can be estimated from Figure 3.25, an Ohms Law calculation made, and the resistor installed to define this wont fire current. This is a repeatable design well in the control of the equipment designer.
GATE TRIGGER VOLTAGE, VGT The gatecathode junction is a pn silicon junction. So the gate trigger voltage follows the diode law and has roughly the same temperature coefficient as a silicon diode, 2mV/C. Figure 3.25 is a plot of VGT versus temperature for typical sensitive gate SCRs. They are prone to triggering by noise coupled through the gate circuit because of their low trigger voltage. The smallest noise voltage margin occurs at maximum temperature and with the most sensitive devices.
0.9 V GT , GATE TRIGGER VOLTAGE (VOLTS) 0.8 HIGH UNIT 0.7 0.6 0.5 LOW UNIT 0.4 0.3 0.2 0.1 30 10 10 30 50 70 90 110 130 JUNCTION TEMPERATURE (C) IGT = 20 NA @ 300K IGT = 200 mA @ 300K
Figure 3.25. Typical VGT vs TJ Figure 3.24. SCR and RGK Gate Currents
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HOLDING CURRENT, IH The holding current of an SCR is the minimum anode current required to maintain the device in the on state. It is usually specified as a maximum for a series of devices (for instance, 5 mA maximum at 25C for the 2N6237 series). A particular device will turn off somewhere between this maximum and zero anode current and there is perhaps a 20to1 spread in each lot of devices. Figure 3.26 shows the holding current increasing with decreasing RGK as the resistor siphons off more and more of the regeneratively produced gate current when the device is in the latched condition. Note that the gatecathode resistor determines the holding current when it is less than 100 Ohms. SCR sensitivity is the determining factor when the resistor exceeds 1 meg Ohm. This allows the designer to set the holding current over a wide range of possible values using the resistor. Values typical of those in conventional nonsensitive devices occur when the external resistor is similar to their internal gatecathode shorting resistance. The holding current uniformity also improves when the resistor is small.
10 TJ = 25C I H , HOLDING CURRENT, mA
1.0 IGT = 1.62 A
0.1
IGT = 20 NA 0.01 0.1 1.0 10 100 1,000 RGK, GATECATHODE RESISTANCE, K
1,000 Ohm resistor, between 100 A to 1 mA of noise current is necessary to generate enough voltage to fire the device. Adding a capacitor sized between 0.01 and 0.1 F creates a noise filter and improves dV/dt by shunting dV/dt displacement current out through the gate terminal. These components must be placed as close as possible to the gate and cathode terminals to prevent lead inductance from making them ineffective. The use of the capacitor also requires the gate drive circuit to supply enough current to fire the SCR without excessive time delay. This is particularly important in applications with rapidly rising (di/dt 50 A/s) anode current where a fast rise high amplitude gate pulse helps to prevent di/dt damage to the SCR. Reverse gate voltage can cause unwanted turnoff of the SCR. Then the SCR works like a gate turnoff thyristor. Turnoff by the gate signal is more probable with small SCRs because of the short distance between the cathode and gate regions. Whether turnoff occurs or not depends on many variables. Even if turnoff does not occur, the effect of high reverse gate current is to move the conduction away from the gate, reducing the effective cathode area and surge capability. Suppressing the reverse gate voltage is particularly important when the gate pulse duration is less than 1 microsecond. Then the part triggers by charge instead of current so halving of the gate pulse width requires double the gate current. Capacitance coupled gate drive circuits differentiate the gate pulse (Figure 3.27) leading to a reverse gate spike. The reverse gate voltage rating should not be exceeded to prevent avalanche damage. This discussion has shown that the use of RGK, the gatecathode resistor, has many implications. Clear understanding of its need and its influence on the performance of the sensitive gate SCR will enable the designer to have better control of his circuit designs using this versatile part.
Figure 3.26. 2N5064 Holding Current
NOISE IMMUNITY Changes in electromagnetic and electrostatic fields coupled into wires or printed circuit lines can trigger these sensitive devices, as can logic circuit glitches. The result is more serious than with a transistor since an SCR will latch on. Careful wire harness design (twisted pairs and adequate separation from highpower wiring) and printed circuit layout (gate and return runs adjacent to one another) can minimize potential problems. A gate cathode network consisting of a resistor and parallel capacitor also helps. The resistor provides a static short and is helpful with noise signals of any frequency. For example, with a
OPTIONAL REVERSE GATE SUPPRESSOR DIODE
Figure 3.27. Capacitance Coupled Gate Drive
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DRIVERS: PROGRAMMABLE UNIJUNCTION TRANSISTORS The programmable unijunction transistor (PUT) is a four layer device similar to an SCR. However, gating is with respect to the anode instead of the cathode. An external resistive voltage divider accurately sets the triggering voltage and allows its adjustment. The PUT finds limited application as a phase control element and is most often used in long duration or low battery drain timer circuits where its high sensitivity permits the use of large timing resistors and small capacitors. Like an SCR, the PUT is a conductivity modulated device capable of providing high current output pulses. OPERATION OF THE PUT The PUT has three terminals, an anode (A), gate (G), and cathode (K). The symbol and a transistor equivalent circuit are shown in Figure 3.28. As can be seen from the equivalent circuit, the device is actually an anodegated SCR. This means that if the gate is made negative with respect to the anode, the device will switch from a blocking state to its on state.
A ANODE (A) GATE (G) G
voltages are reversed. Negative resistance terminology describes the device characteristics because of the traditional application circuit. An external reference voltage must be maintained at the gate terminal. A typical relaxation type oscillator circuit is shown in Figure 3.29(a). The voltage divider shown is a typical way of obtaining the gate reference. In this circuit, the characteristic curve looking into the anodecathode terminals would appear as shown in Figure 3.29(b). The peak and valley points are stable operating points at either end of a negative resistance region. The peak point voltage (VP) is essentially the same as the external gate reference, the only difference being the gate diode drop. Since the reference is circuit and not device dependent, it may be varied, and in this way, VP is programmable. In characterizing the PUT, it is convenient to speak of the Thevenin equivalent circuit for the external gate voltage (VS) and the equivalent gate resistance (RG). The parameters are defined in terms of the divider resistors (R1 and R2) and supply voltage as follows:
VS RG
+ R1 V1(R1 ) R2) + R1 R2(R1 ) R2)
Most device parameters are sensitive to changes in VS and RG. For example, decreasing RG will cause peak and valley currents to increase. This is easy to see since RG actually shunts the device and will cause its sensitivity to decrease. CHARACTERISTICS OF THE PUT Table 3.1 is a list of typical characteristics of ON Semiconductors 2N6027/2N6028 of programmable unijunction transistors. The test circuits and test conditions shown are essentially the same as for the data sheet characteristics. The data presented here defines the static curve shown in Figure 3.29(b) for a 10 V gate reference (VS) with various gate resistances (RG). It also indicates the leakage currents of these devices and describes the output pulse. Values given are for 25C unless otherwise noted.
(K) CATHODE
Figure 3.28(a). PUT Symbol
Figure 3.28(b). Transistor Equivalent
The PUT is a complementary SCR when its anode is connected like an SCRs cathode and the circuit bias
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VP VS VAK
PEAK POINT NEGATIVE RESISTANCE REGION VALLEY POINT
RT
R2 + VF V1 VV
OUTPUT CT R0
VS
R1
IGAO
IP IA
IV
IF
Figure 3.29(a). Typical Oscillator Circuit
Figure 3.29(b). Static Characteristics
Table 3.1. Typical PUT Characteristics

Symbol IP IV VAG IGAO IGKS VF VO tr Curve Tracer Used 3.33 3.34 Test Circuit Figure 3.30 3.30 Test Conditions RG = 1 m RG = 10 k RG = 1 M RG = 10 k (See Figure 3.31) VS = 40 V VS = 40 V IF = 50 mA (See Figure 3.32) 5 0.8 11 40 5 0.8 11 40 nA V V ns 2N6027 1.25 4 18 150 2N6028 0.08 0.70 18 150 Unit A A A A
PEAK POINT CURRENT, (IP) The peak point is indicated graphically by the static curve. Reverse anode current flows with anode voltages less than the gate voltage (VS) because of leakage from the bias network to the charging network. With currents less than IP, the device is in a blocking state. With currents above IP, the device goes through a negative resistance region to its on state. The charging current, or the current through a timing resistor, must be greater than IP at VP to insure that a device will switch from a blocking to an on state in an oscillator circuit. For this reason, maximum values of IP are given on the data sheet. These values are dependent on VS temperature, and RG. Typical curves on the data sheet indicate this dependence and must be consulted for most applications. The test circuit in Figure 3.30 is a sawtooth oscillator which uses a 0.01 F timing capacitor, a 20 V supply, an adjustable charging current, and equal biasing resistors (R). The two biasing resistors were chosen to given an equivalent RG of 1 M and 10 k. The peak point
current was measured with the device off just prior to oscillation as detected by the absence of an output voltage pulse. The 2N5270 held effect transistor circuit is used as a current source. A variable gate voltage supply was used to control this current. VALLEY POINT CURRENT, (IV) The valley point is indicated graphically in Figure 3.28. With currents slightly less than IV, the device is in an unstable negative resistance state. A voltage minimum occurs at IV and with higher currents, the device is in a stable on state. When the device is used as an oscillator, the charging current or the current through a timing resistor must be less than IV at the valley point voltage (VV). For this reason, minimum values for IV are given on the data sheet for RG = 10 k. With RG = 1 M, a reasonable low is 2 A for all devices. When the device is used in the latching mode, the anode current must be greater than IV. Maximum values for IV are given with RG = 1 M. All devices have a reasonable high of 400 A IV with RG = 10 k.
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PEAK POINT VOLTAGE, (VP) The unique feature of the PUT is that the peak point voltage can be determined externally. This programmable feature gives this device the ability to function in voltage controlled oscillators or similar applications. The triggering or peak point voltage is approximated by
VP VT
across the PUT. A Tektronix, Type W plugin was used to determine this parameter. FORWARD ANODEGATE VOLTAGE, (VAG) The forward anodetogate voltage drop affects the peak point voltage as was previously discussed. The drop is essentially the same as a small signal silicon diode and is plotted in Figure 3.31. The voltage decreases as current decreases, and the change in voltage with temperature is greater at low currents. At 10 nA the temperature coefficient is about 2.4 V/C and it drops to about 1.6 mV/C at 10 mA. This information is useful in applications where it is desirable to temperature compensate the effect of this diode. GATECATHODE LEAKAGE CURRENT, (IGKS) The gatetocathode leakage current is the current that flows from the gate to the cathode with the anode shorted to the cathode. It is actually the sum of the open circuit gateanode and gatecathode leakage currents. The shorted leakage represents current that is shunted away from the voltage divider.
) V S,
where VS is the unloaded divider voltage and VT is the offset voltage. The actual offset voltage will always be higher than the anodegate voltage VAG, because IP flows out of the gate just prior to triggering. This makes VT = VAG + IP RG. A change in RG will affect both VAG and IP RG but in opposite ways. First, as RG increases, IP decreases and causes VAG to decrease. Second, since IP does not decrease as fast as RG increases, the IP RG product will increase and the actual VT will increase. These second order effects are difficult to predict and measure. Allowing VT to be 0.5 V as a first order approximation gives sufficiently accurate results for most applications. The peak point voltage was tested using the circuit in Figure 3.30 and a scope with 10 M input impedance
IP, IV RS VG + 20 V PUT UNDER TEST R + G
S 2N5270 D
NOTES: 1) VARIOUS SENSE RESISTORS (RS) ARE USED TO KEEP THE SENSE VOLTAGE NEAR 1 Vdc. 2) THE GATE SUPPLY (VG) IS ADJUSTED FROM ABOUT 0.5 V TO +20 V. Vp 0.01 mF OUTPUT PULSE
20
R = 2 RG VS = 10 V
Figure 3.30. Test Circuit for IP, VP and IV
GATEANODE LEAKAGE CURRENT, (IGAO) The gatetoanode leakage current is the current that flows from the gate to the anode with the cathode open. It is important in long duration timers since it adds to the charging current flowing into the timing capacitor. The typical leakage currents measured at 40 V are shown in Figure 3.32. Leakage at 25C is approximately 1 nA and the current appears to double for about every 10C rise in temperature.
FORWARD VOLTAGE, (VF) The forward voltage (VF) is the voltage drop between the anode and cathode when the device is biased on. It is the sum of an offset voltage and the drop across some internal dynamic impedance which both tend to reduce the output pulse. The typical data sheet curve shows this impedance to be less than 1 ohm for up to 2 A of forward current.
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PEAK OUTPUT VOLTAGE, (VO) The peak output voltage is not only a function of VP, VF and dynamic impedance, but is also affected by switching speed. This is particularly true when small capacitors (less than 0.01 F) are used for timing since they lose part of their charge during the turn on interval. The use of a relatively large capacitor (0.2 F) in the test circuit of Figure 3.33 tends to minimize this last effect. The output voltage is measured by placing a scope across the 20 ohm resistor which is in series with the cathode lead. RISE TIME, (tr) Rise time is a useful parameter in pulse circuits that use capacitive coupling. It can be used to predict the amount of current that will flow between these circuits. Rise time is specified using a fast scope and measuring between 0.6 V and 6 V on the leading edge of the output pulse. MINIMUM AND MAXIMUM FREQUENCY In actual tests with devices whose parameters are known, it is possible to establish minimum and maximum values of timing resistors that will guarantee oscillation. The circuit under discussion is a conventional RC relaxation type oscillator. To obtain maximum frequency, it is desirable to use low values of capacitance (1000 pF) and to select devices and bias conditions to obtain high IV. It is possible to use stray capacitance but the results are generally unpredictable. The minimum value of timing resistance is obtained using the following rule of thumb:
R (min)
TEMPERATURE ( C)
0.9
0.7
VAG (VOLTS)
0.5
25C 75C
0.3
0.1 0 0.01
0.1
1.0
10 IAG (mA)
100
1K
10 K
Figure 3.31. Voltage Drop of 2N6027 Series

70
60
50
40
30
20 1.0 10 IGAO, GATE TO ANODE LEAKAGE CURRENT (nA)
+ 2(V1 * VV)IV
Figure 3.32. Typical Leakage Current of the 2N6027, 2N6028 Reverse Voltage Equals 40 V
where the valley voltage (VV) is often negligible. To obtain minimum frequency, it is desirable to use high values of capacitance (10 F) and to select devices and bias conditions to obtain low IP. It is important that the capacitor leakage be quite low. Glass and mylar dielectrics are often used for these applications. The maximum timing resistor is as follows:
R (max)
510 k A 1 mF + 20 V 0.2 mF K 20 27 k V0 G OUTPUT 16 k
+ (VI * VP)2IP
In a circuit with a fixed value of timing capacitance, our most sensitive PUT, the 2N6028, offers the largest dynamic frequency range. Allowing for capacitance and bias changes, the approximate frequency range of a PUT is from 0.003 Hz to 2.5 kHz.
Figure 3.33. PUT Test Circuit for Peak Output Voltage (Vo)
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510 k A + 0.001 mF G 1000 pF K 20 16 k
TO TEKTRONICS TYPE 567 OR EQUIVALENT RG = 10 k
V1 20 V
100 27 k 100
Figure 3.34. tr Test Circuit for PUTs
length of the output pulse as temperature increases is responsible for this result. Since this parameter has not been characterized, it is obvious that temperature compensation is more practical with relatively low frequency oscillators. Various methods of compensation are shown in Figure 3.36. In the low cost dioderesistor combination of 3.36(a), the diode current is kept small to cause its temperature coefficient to increase. In 3.36(b), the bias current through the two diodes must be large enough so that their total coefficient compensates for VAG. The transistor approach in 3.36(c) can be the most accurate since its temperature coefficient can be varied independently of bias current.
100 k < R < 1 M
RT
1k
+ 12 V 0.01 mF K 75
OUTPUT 2k
(a) DIODERESISTOR
Figure 3.35. Uncompensated Oscillator
TEMPERATURE COMPENSATION The PUT with its external bias network exhibits a relatively small frequency change with temperature. The uncompensated RC oscillator shown in Figure 3.35 was tested at various frequencies by changing the timing resistor RT. At discrete frequencies of 100, 200, 1000 and 2000 Hz, the ambient temperature was increased from 25 to 60C. At these low frequencies, the negative temperature coefficient of VAG predominated and caused a consistent 2% increase in frequency. At 10 kHz, the frequency remained within 1% over the same temperature range. The storage time phenomenon which increases the
(b) DUALDIODE
(c) TRANSISTOR
Figure 3.36. Temperature Compensation Techniques
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SECTION 4 THE SIDAC, A NEW HIGH VOLTAGE BILATERAL TRIGGER
Edited and Updated
The SIDAC is a high voltage bilateral trigger device that extends the trigger capabilities to significantly higher voltages and currents than have been previously obtainable, thus permitting new, cost-effective applications. Being a bilateral device, it will switch from a blocking state to a conducting state when the applied voltage of either polarity exceeds the breakover voltage. As in other trigger devices, (SBS, Four Layer Diode), the SIDAC switches through a negative resistance region to the low voltage on-state (Figure 4.1) and will remain on until the main terminal current is interrupted or drops below the holding current. SIDACs are available in the large MKP3V series and economical, easy to insert, small MKP1V series axial lead
packages. Breakdown voltages ranging from 104 to 280 V are available. The MKP3V devices feature bigger chips and provide much greater surge capability along with somewhat higher RMS current ratings. The high-voltage and current ratings of SIDACs make them ideal for high energy applications where other trigger devices are unable to function alone without the aid of additional power boosting components. The basic SIDAC circuit and waveforms, operating off of ac are shown in Figure 4.2. Note that once the input voltage exceeds V(BO), the device will switch on to the forward on-voltage VTM of typically 1.1 V and can conduct as much as the specified repetitive peak on-state current ITRM of 20 A (10 s pulse, 1 kHz repetition frequency).
ITM IH
VTM
SLOPE = RS
IS IDRM VS I(BO) VDRM V(BO)
RS
(V(BO) (IS
* VS) * I(BO))
Figure 4.1(b). Actual MKP1V130 V-I Characteristic. Horizontal: 50 V/Division. Vertical: 20 mA/Division. (0,0) at Center. RL = 14 k Ohm.
Figure 4.1(a). Idealized SIDAC V-I Characteristics
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VIN V(BO) V(BO) V(BO) VT
VIN
RL
RL
t RS
RS
(V(BO) (IS
* I(BO))
* VS)
IH IT
IH
RS = SIDAC SWITCHING RESISTANCE
CONDUCTION ON ANGLE OFF
Figure 4.2. Basic SIDAC Circuit and Waveforms
Operation from an AC line with a resistive load can be analyzed by superimposing a line with slope = 1/RL on the device characteristic. When the power source is AC, the load line can be visualized as making parallel translations in step with the instantaneous line voltage and frequency. This is illustrated in Figure 4.3 where v1 through v5 are the instantaneous open circuit voltages of the AC generator and i1 through i5 are the corresponding short circuit currents that would result if the SIDAC was not in the circuit. When the SIDAC is inserted in the circuit, the current that flows is determined by the intersection of the load line with the SIDAC characteristic. Initially the SIDAC blocks, and only a small leakage
i i5 (VT, IT)
current flows at times 1 through 4. The SIDAC does not turn-on until the load line supplies the breakover current (I(BO)) at the breakover voltage (V(BO)). If the load resistance is less than the SIDAC switching resistance, the voltage across the device will drop quickly as shown in Figure 4.2. A stable operating point (VT, IT) will result if the load resistor and line voltage provide a current greater than the latching value. The SIDAC remains in an on condition until the generator voltage causes the current through the device to drop below the holding value (IH). At that time, the SIDAC switches to the point (Voff, Ioff) and once again only a small leakage current flows through the device.
SLOPE i3 i RL
+ RIL
(VOFF, IOFF)
v1, ..., v5 = INSTANTANEOUS OPEN CIRCUIT VOLTAGES AT TIME 1, ..., 5 i1, ..., i5 = INSTANTANEOUS SHORT CIRCUIT CURRENTS AT TIME 1, ..., 5
RL
tRS
IH i1 (VBO, IBO) v v1 v2 v3 v4 v5 i
+ RvL
Figure 4.3. Load Line for Figure 4.2. (1/2 Cycle Shown.)
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Figure 4.4 illustrates the result of operating a SIDAC with a resistive load greater than the magnitude of its switching resistance. The behavior is similar to that described in Figures 4.2 and 4.3 except that the turn-on and turn-off of the SIDAC is neither fast nor complete. Stable operating points on the SIDAC characteristics between (V(BO), I(BO)) and (VS, IS) result as the generator voltage increases from v2 to v4. The voltage
across the SIDAC falls only partly as the loadline sweeps through this region. Complete turn-on of the SIDAC to (VT, IT) does not occur until the load line passes through the point (VS, IS). The load line illustrated in Figure 4.4 also results in incomplete turn-off. When the current drops below I H, the operating point switches to (Voff, Ioff) as shown on the device characteristic.
RL
(VT, IT) i4 i3 i2 i1 IH (VS, IS) (VOFF, IOFF) (VBO, IBO) v1 v2 v3 v4 v
RL RS RS = SIDAC SWITCHING RESISTANCE
Figure 4.4. High Resistance Load Line with Incomplete Switching
The switching current and voltage can be 2 to 3 orders of magnitude greater than the breakover current and on-state voltage. These parameters are not as tightly specified as VBO and IBO. Consequently operation of the SIDAC in the state between fully on and fully off is undesirable because of increased power dissipation, poor efficiency, slow switching, and tolerances in timing. Figure 4.5 illustrates a technique which allows the use of the SIDAC with high impedance loads. A resistor can be placed around the load to supply the current required to latch the SIDAC. Highly inductive loads slow the current rise and the turn-on of the SIDAC because of their L/R time constant. The use of shunt resistor around the load will improve performance when the SIDAC is used with inductive loads such as small transformers and motors. The SIDAC can be used in oscillator applications. If the load line intersects the device characteristic at a point where the total resistance (RL + RS) is negative, an unstable operating condition with oscillation will result. The resistive load component determines steady-state behavior. The reactive components determine transient behavior. Figure 4.10 shows a SIDAC relaxation oscillator application. The wide span between IBO and IH makes the SIDAC easy to use. Long oscillation periods can be achieved with economical capacitor sizes because of the low device I(BO).
Z1 is typically a low impedance. Consequently the SIDACs switching resistance is not important in this application. The SIDAC will switch from a blocking to full on-state in less than a fraction of a microsecond. The timing resistor must supply sufficient current to fire the SIDAC but not enough current to hold the SIDAC in an on-state. These conditions are guaranteed when the timing resistor is selected to be between Rmax and Rmin. For a given time delay, capacitor size and cost is minimized by selecting the largest allowable timing resistor. Rmax should be determined at the lowest temperature of operation because I(BO) increases then. The load line corresponding to Rmax passes through the point (V(BO), I(BO)) allowing the timing resistor to supply the needed breakover current at the breakover voltage. The load line for a typical circuit design should enclose this point to prevent sticking in the off state. Requirements for higher oscillation frequencies and greater stored energy in the capacitor result in lower values for the timing resistor. Rmin should be determined at the highest operating temperature because IH is lower then. The load line determined by R and Vin should pass below IH on the device characteristic or the SIDAC will stick in the on-state after firing once. I H is typically more than 2 orders of magnitude greater than IBO. This makes the SIDAC well suited for operation over a wide temperature span.
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SIDAC turn-off can be aided when the load is an under-damped oscillatory CRL circuit. In such cases, the SIDAC current is the sum of the currents from the timing resistor and the ringing decay from the load. SIDAC turn-off behavior is similar to that of a TRIAC where turn-off will not occur if the rate of current zero crossing is high. This is a result of the stored charge within the volume of the device. Consequently, a SIDAC cannot be force commuted like an SCR. The SIDAC will pass a ring wave of sufficient amplitude and frequency. Turn-off requires the device current to approach the holding current gradually. This is a complex function of junction temperature, holding current magnitude, and the current wave parameters.
RSL RSL RL HIGH v LOW
conduction angle is 90 because the SIDAC must switch on before the peak of the line voltage. Line regulation and breakover voltage tolerances will require that a conduction angle longer than 90 be used, in order to prevent lamp turn-off under low line voltage conditions. Consequently, practical conduction angles will run between 110 and 130 with corresponding power reductions of 10% to 30%. In Figure 4.2 and Figure 4.7, the SIDAC switching angles are given by:
qON
+ SIN*1 (V(BO)Vpk) + 180 * SIN*1
where Vpk = Maximum Instantaneous Line Voltage

qOFF
(I H R L) V T V pk
tRS
TYPICAL: RSL = 2.7 k OHM 10 WATT RS = 3 k OHM RSL = TURN-ON SPEED UP RESISTOR RS = SIDAC SWITCHING RESISTANCE
Figure 4.5. Inductive Load Phase Control
The simple SIDAC circuit can also supply switchable load current. However, the conduction angle is not readily controllable, being a function of the peak applied voltage and the breakover voltage of the SIDAC. As an example, for peak line voltage of about 170 V, at V(BO) of 115 V and a holding current of 100 mA, the conduction angle would be about 130. With higher peak input voltages (or lower breakdown voltages) the conduction angle would correspondingly increase. For non-critical conduction angle, 1 A rms switching applications, the SIDAC is a very cost-effective device. Figure 4.7 shows an example of a SIDAC used to phase control an incandescent lamp. This is done in order to lower the RMS voltage to the filament and prolong the life of the bulb. This is particularly useful when lamps are used in hard to reach locations such as outdoor lighting in signs where replacement costs are high. Bulb life span can be extended by 1.5 to 5 times depending on the type of lamp, the amount of power reduction to the filament, and the number of times the lamp is switched on from a cold filament condition. The operating cost of the lamp is also reduced because of the lower power to the lamp; however, a higher wattage bulb is required for the same lumen output. The maximum possible energy reduction is 50% if the lamp wattage is not increased. The minimum
where ON, OFF = Switching Angles in degrees VT = 1 V = Main Terminal Voltage at IT = IH Generally the load current is much greater than the SIDAC holding current. The conduction angle then becomes 180 minus (on). Rectifiers have also been used in this application to supply half wave power to the lamp. SIDACs prevent the flicker associated with half-wave operation of the lamp. Also, full wave control prevents the introduction of a DC component into the power line and improves the color temperature of the light because the filament has less time to cool during the off time. The fast turn-on time of the SIDAC will result in the generation of RFI which may be noticeable on AM radios operated in the vicinity of the lamp. This can be prevented by the use of an RFI filter. A possible filter design is shown in Figure 4.5. This filter causes a ring wave of current through the SIDAC at turn-on time. The filter inductor must be selected for resonance at a frequency above the upper frequency limit of human hearing and as low below the start of the AM broadcast band as possible for maximum harmonic attenuation. In addition, it is important that the filter inductor be non-saturating to prevent dI/dT damage to the SIDAC. For additional information on filter design see page 99.
ZL
@
)
VIN
SIDAC
Figure 4.6. SIDAC Circuit
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100 WATT 240 V 100 HY PREM SPE304 RDC = 0.04
220 VAC
0.1 F OPTIONAL RFI FILTER 400 V
(2)MKP1V130RL
Figure 4.7. Long-Life Circuit for Incandescent Lamp
The sizing of the SIDAC must take into account the RMS current of the lamp, thermal properties of the SIDAC, and the cold start surge current of the lamp which is often 10 to 20 times the steady state load current. When lamps burn out, at the end of their operating life, very high surge currents which could damage the SIDAC are possible because of arcing within the bulb. The large MKP3V device is recommended if the SIDAC is not to be replaced along with the bulb. Since the MKP3V series of SIDACs have relatively tight V(BO) tolerances (104 V to 115 V for the 115 device), other possible applications are over-voltage protection (OVP) and detection circuits. An example of this, as illustrated in Figure 4.8, is the SIDAC as a transient protector in the transformer-secondary of the medium voltage power supply, replacing the two more expensive back-to-back zeners or an MOV. The device can also be used across the output of the regulator ( 100 V) as a simple OVP, but for this application, the regulator must have current foldback or a circuit breaker (or fuse) to minimize the dissipation of the SIDAC.
Another example of OVP is the telephony applications as illustrated in Figure 4.9. To protect the Subscriber Loop Interface Circuit (SLIC) and its associated electronics from voltage surges, two SIDACs and two rectifiers are used for secondary protection (primary protection to 1,000 V is provided by the gas discharge tube across the lines). As an example, if a high positive voltage transient appeared on the lines, rectifier D1 (with a P.I.V. of 1,000 V) would block it and SIDAC D4 would conduct the surge to ground. Conversely, rectifier D2 and SIDAC D3 would protect the SLIC for negative transients. The SIDACs will not conduct when normal signals are present. Being a negative resistance device, the SIDAC also can be used in a simple relaxation oscillator where the frequency is determined primarily by the RC time constant (Figure 4.10). Once the capacitor voltage reaches the SIDAC breakover voltage, the device will fire, dumping the charged capacitor. By placing the load in the discharge path, power control can be obtained; a typical load could be a transformer-coupled xeon flasher, as shown in Figure 4.12.
SIDAC AS A TRANSIENT PROTECTOR SIDAC AS AN OVP VIN REG. z
VO
p 100 V
Figure 4.8. Typical Application of SIDACs as a Transient Protector and OVP in a Regulated Power Supply
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MOC3031 90 V RMS @ 48 Vdc RING GENERATOR RE RG1 105 V RG2 TIP RPT RT RR RPR RING PRIMARY PROTECTION GAS DISCHARGE TUBE 1N4007 D2 SECONDARY PROTECTION 1N4007 D1 135 V RING ENABLE 0 TO + 5 V GND
TIP DRIVE TIP SENSE RING SENSE RING DRIVE SLIC MC3419-1L
48 V BATTERY
Figure 4.9. SIDACs Used for OVP in Telephony Applications
V(BO) R VIN
u V(BO)
VC t iL ZL iL
VC C
R MAX
V IN
V (BO) I (BO) t
R MIN
VTM q VIN * IH
^ RC In
*
I
I VBO VIN
Figure 4.10. Relaxation Oscillator Using a SIDAC
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SIDACs provide an economical means for starting high intensity high pressure gas discharge lamps. These lamps are attractive because of their long operating life and high efficiency. They are widely used in outdoor lighting for these reasons. Figure 4.13 illustrates how SIDACs can be used in sodium vapor lamp starters. In these circuits, the SIDAC is used to generate a short duration (1 to 20 s) high-voltage pulse of several KV or more which is timed by means of the RC network across the line to occur near the peak of the AC input line voltage. The high voltage pulse strikes the arc which lights the lamp. In these circuits, an inductive ballast is required to provide a stable operating point for the lamp. The lamp is a negative resistance device whose impedance changes with current, temperature, and time over the first few minutes of operation. Initially, before the lamp begins to conduct, the lamp impedance is high and the full line voltage appears across it. This allows C to charge to the breakover voltage of the SIDAC, which then turns on discharging the capacitor through a step-up transformer generating the high voltage pulse. When the arc strikes, the voltage across the lamp falls reducing the available charging voltage across RC to the point where VC no longer exceeds V(BO) and the SIDAC remains off. The low duty cycle lowers average junction temperature improving SIDAC reliability. Normal operation approximates non-repetitive conditions. However, if the lamp fails or is removed during replacement, operation of the SIDAC will be at the 60 Hz line frequency. The design of the circuit should take into account the resulting steady state power dissipation.
LB R vac C1
(a). Conventional HV Transformer
LB C vac R
(b). H.V. Auto-Transformer
LB
C vac R
VIN
HV
(c). Tapped Ballast Auto Transformer Figure 4.13. Sodium Vapor Lamp Starter Circuits
Figure 4.11. Typical Capacitor Discharge SIDAC Circuit
220 2W 20 F VIN 400 V 300 V
1M 2W 560 k 2W 1 F 200 V + 2 kW XEON TUBE RS-272-1145
125 V
4 kV PULSE TRANSFORMER RS-272-1146
Figure 4.12. Xeon Flasher Using a SIDAC
Figure 4.14 illustrates a solid state fluorescent lamp starter using the SIDAC. In this circuit the ballast is identical to that used with the conventional glow-tube starter shown in Figure 4.15. The glow tube starter consists of a bimetallic switch placed in series with the tube filaments which closes to energize the filaments and then opens to interrupt the current flowing through the ballast inductor thereby generating the high-voltage pulse necessary for starting. The mechanical glow-tube starter is the circuit component most likely to cause unreliable starting.
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LB
D1 D2
115 VAC
PTC
LB
UNIVERSAL MFG CORP CAT200-H2 14-15-20-22 WATT BALLAST 325 mHY 28.9 DCR 1N4005 RECTIFIER (2) MKP1V130RL SIDAC 3 VFD 400 V 68 k OHMS 112 WATT KEYSTONE CARBON COMPANY RL3006-50-40-25-PTO 50 OHMS/25C MICROTRAN QIL 50-F 50 mHY 11 OHMS
D1 D2 C R PTC
Figure 4.14. Fluorescent Starter Using SIDAC
The heating of the filaments causes thermonic emission of electrons from them. These electrons are accelerated along the length of the tube causing ionization of the argon gas within the tube. The heat generated by the starting current flow through the tube vaporizes the mercury droplets within the tube which then become ionized themselves causing the resistance and voltage across the tube to drop significantly. The drop in voltage across the tube is used to turn off the starting circuit and prevent filament current after the lamp is lit. The SIDAC can be used to construct a reliable starter circuit providing fast, positive lamp ignition. The starter shown in Figure 4.14 generates high voltage by means of a series CRL charging circuit. The circuit is roughly analogous to a TRIAC snubber used with an inductive load, except for a lower damping factor and higher Q. The
size of C determines the amount of filament heating current by setting the impedance in the filament circuit before ionization of the tube. The evolution of this circuit can be understood by first considering an impractical circuit (Figure 4.16). If LB and C are adjusted for resonance near 60 Hz, the application of the AC line voltage will result in a charging current that heats the filaments and a voltage across the capacitor and tube that grows with each half-cycle of the AC line until the tube ionizes. Unfortunately, C is a large capacitor which can suddenly discharge through the tube causing high current pulses capable of destroying the tube filament. Also C provides a permanent path for filament current after starting. These factors cause short tube operating life and poor efficiency because of filament power losses. The impractical circuit must be modified to: (1) Switch off the filament current after starting. (2) Limit capacitor discharge current spikes. In Figure 4.14 a parallel connected rectifier and SIDAC have been added in series with the capacitor C. The breakover voltage of the SIDAC is higher than the peak of the line voltage. Diode D1 is therefore necessary to provide a current path for charging C. On the first half-cycle, C resonant charges through diode D1 to a peak voltage of about 210 V, and remains at that value because of the blocking action of the rectifier and SIDAC. During this time, the bleeder resistor R has negligible effect on the voltage across C because the RC time constant is long in comparison to the line period. When the line reverses, the capacitor voltage boosts the voltage across the SIDAC until breakover results. This results in a sudden step of voltage across the inductor L, causing resonant charging of the capacitor to a higher voltage on the 2nd half-cycle.
NEON GAS FLUORESCENT COATING COATED FILAMENT STARTER
SYLVANIA F15T8/CW
(ARGON GAS) MERCURY DROPLETS
BALLAST INDUCTOR
VAC
Figure 4.15. Fluorescent Lamp with Glow Tube Starter
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BALLAST CHOKE fo RB LB
1 + 2a + 60 Hz LC
V VAC
X LB + RTOTAL
VSTART
V max
+ Q VAC 2
VSTART
t VMAX
Figure 4.16. Impractical Starter Circuit
(a). 5 ms/DIVISION
(b). 100 ms/DIVISION
Figure 4.17. Starting Voltage Across Fluorescent Tube 100 V/DIV 0 V AT CENTER VLine = 110 V
Several cycles of operation are necessary to approach steady state operating conditions. Figure 4.17 shows the starting voltage waveform across the tube. The components R, PTC, and L serve the dual role of guarantying SIDAC turn-off and preventing capacitor discharge currents through the tube. SIDACs can also be used with auto-transformer ballasts. The high voltage necessary for starting is generated by the leakage autotransformer. The SIDAC is used to turn-on the filament transformer initially and turn it off after ionization causes the voltage across the tube to drop. Figure 4.18 illustrates this concept. The resistor R can be added to aid turn-off of the SIDAC by providing a
small idle current resulting in a voltage drop across the impedance Z. The impedance Z could be a saturable reactor and or positive temperature coefficient thermistor. These components help to insure stability of the system comprised of the negative resistance SIDAC and negative resistance tube during starting, and promote turn off of the SIDAC. The techniques illustrated in Figure 4.13 are also possible methods for generation of the necessary highvoltage required in fluorescent starting. The circuits must be modified to allow heating of the fluorescent tube cathodes if starting is to simulate the conditions existing when a glow tube is used.
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C Z VBO VBO
t VSTART u VOPERATING
VAC R
Figure 4.18. Fluorescent Starter Using SIDAC and Autotransformer Ballast Table 4.1. Possible Sources for Thermistor Devices Fenwal Electronics, 63 Fountain Street Framingham MA 01701 Keystone Carbon Company, Thermistor Division St. Marys, PA 15857 Thermometrics, 808 U.S. Highway 1 Edison, N.J. 08817 Therm-O-Disc, Inc. Micro Devices Product Group 1320 South Main Street, Mansfield, OH 44907 Midwest Components Inc., P.O Box 787 1981 Port City Boulevard, Muskegon, MI 49443 Nichicon (America) Corp., Dept. G 927 E. State Pkwy, Schaumburg, IL 60195
Thermistors are useful in delaying the turn-on or insuring the turn-off of SIDAC devices. Table 4.1 shows possible sources of thermistor devices. Other high voltage nominal current trigger applications are: Gas or oil igniters Electric fences HV electrostatic air filters Capacitor Discharge ignitions Note that all these applications use similar circuits where a charged capacitor is dumped to generate a high transformer secondary voltage (Figure 4.11). In many cases, the SIDAC current wave can be approximated by an exponential or quasi-exponential current wave (such as that resulting from a critically damped or slightly underdamped CRL discharge circuit). The ques-
tion then becomes; how much real world surge current can the SIDAC sustain? The data sheet defines an ITSM of 20 A, but this is for a 60 Hz, one cycle, peak sine wave whereas the capacitor discharge current waveform has a fast-rise time with an exponential fall time. To generate the surge current curve of peak current versus exponential discharge pulse width, the test circuit of Figure 4.19 was implemented. It simulates the topology of many applications whereby a charged capacitor is dumped by means of a turned-on SIDAC to produce a current pulse. Timing for this circuit is derived from the nonsymmetrical CMOS astable multivibrator (M.V.) gates G1 and G2. With the component values shown, an approximate 20 second positive-going output pulse is fed to the base of the NPN small-signal high voltage transistor Q1, turning it on. The following high voltage PNP transistor is consequently turned on, allowing capacitor C1 to be charged through limiting resistor R1 in about 16 seconds. The astable M.V. then changes state for about 1.5 seconds with the positive going pulse from Gate 1 fed through integrator R2-C2 to Gate 3 and then Gate 4. The net result of about a 100 s time delay from G4 is to ensure non-coincident timing conditions. This positive going output is then differentiated by C3-R3 to produce an approximate 1 ms, leading edge, positive going pulse which turns on NPN transistor Q3 and the following PNP transistor Q4. Thus, an approximate 15 mA, 1 ms pulse is generated for turning on SCR Q5 about 100 s after capacitor charging transistor Q2 is turned off. The SCR now fires, discharging C1 through the current limiting resistor R4 and the SIDAC Device Under Test (D.U.T.). The peak current and its duration is set by the voltage VC across capacitor C1 and current limiting resistor R4. The circuit has about a 240 V capability limited by C1, Q1 and Q2 (250 V, 300 V and 300 V respectively).
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+15 V R2 100 k C2 1 G3 2 0.001 F 3
+15 V 5 G4 6 VCC 4
p 240 V
Q2 MJ4646 R1 4k 5W LED R4 3.3 2W Q5 MCR 6507 SIDAC DUT 2N3906 Q4 1k 1k 1N 4003 Q3 2N3904 10 k
MC14011 +15 V +15 V 14 8 G1 9 22 M 22 M 10 12 13 2.2 M 1N914 0.47 F G2 7 22 k 11 47 k
10 k 39 k 2W Q1 MPS A42 C1 80 F 250 V
+15 V C3 0.1 F R3 10 k 10 k
22 k
1N914
Figure 4.19. SIDAC Surge Tester
I pk, SURGE CURRENT (AMPS)
The SCR is required to fire the SIDAC, rather than the breakover voltage, so that the energy to the D.U.T. can be predictably controlled. By varying VC, C1 and R4, the surge current curve of Figure 4.20 was derived. Extensive life testing and adequate derating ensure that the SIDAC, when properly used, will reliably operate in the various applications.
100
30 Ipk 10% 3 1 0.3 1 3 10 tw, PULSE WIDTH (ms) 30 100 300 tw
10
Figure 4.20. Exponential Surge Current Capability of the MKP3V SIDAC. Pulse Width versus Peak Current
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SECTION 5 SCR CHARACTERISTICS
Edited and Updated
SCR TURNOFF CHARACTERISTICS In addition to their traditional role of power control devices, SCRs are being used in a wide variety of other applications in which the SCRs turnoff characteristics are important. As in example reliable high frequency inverters and converter designs ( 20 kHz) require a known and controlled circuitcommutated turnoff time (tq). Unfortunately, it is usually difficult to find the turnoff time of a particular SCR for a given set of circuit conditions. This section discusses tq in general and describes a circuit capable of measuring tq. Moreover, it provides data and curves that illustrate the effect on tq when other parameters are varied, to optimize circuit performance.
is necessary to apply a negative (reverse) voltage to the device anode, causing the holes and electrons near the two end junctions, J1 and J3, to diffuse to these junctions. This causes a reverse current to flow through the SCR. When the holes and electrons near junctions J1 and J3 have been removed, the reverse current will cease and junctions J1 and J3 will assume a blocking state. However, this does not complete the recovery of the SCR since a high concentration of holes and electrons still exist near the center junction, J2. This concentration decreases by the recombination process and is largely independent of the external circuit. When the hole and electron concentration near junction J2 has reached some low value, junction J2 will assume its blocking condition and a forward voltage can, after this time, be applied without the SCR switching back to the conduction state.
ANODE
SCR TURNOFF MECHANISM The SCR, being a four layer device (PNPN), is represented by the two interconnected transistors, as shown in Figure 5.1. This regenerative configuration allows the device to turn on and remain on when the gate trigger is removed, as long as the loop gain criteria is satisfied; i.e., when the sum of the common base current gains () of both the equivalent NPN transistor and PNP transistor, exceed one. To turn off the SCR, the loop gain must be brought below unity, whereby the onstate principal current (anode current iT) limited by the external circuit impedance, is reduced below the holding current (IH). For ac line applications, this occurs automatically during the negative going portion of the waveform. However, for dc applications (inverters, as an example), the anode current must be interrupted or diverted; (diversion of the anode current is the technique used in the tq test fixture described later in this application note). SCR TURNOFF TIME tq Once the anode current in the SCR ceases, a period of time must elapse before the SCR can again block a forward voltage. This period is the SCRs turnoff time, tq, and is dependent on temperature, forward current, and other parameters. The turnoff time phenomenon can be understood by considering the three junctions that make up the SCR. When the SCR is in the conducting state, each of the three junctions is forward biased and the N and P regions (base regions) on either side of J2 are heavily saturated with holes and electrons (stored charge). In order to turn off the SCR in a minimum amount of time, it
N P GATE N ANODE
P J1 N GATE P GATE CATHODE CATHODE PNPN STRUCTURE N J3 J2
ANODE ANODE ITM Q1 P N IC1 = IB2 P Q2 GATE IB1 = IC2
CATHODE
CATHODE
TWO TRANSISTOR MODEL
Figure 5.1. Two Transistor Analogy of an SCR
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tq MEASUREMENT
When measuring SCR turnoff time, tq, it is first necessary to establish a forward current for a period of time long enough to ensure carrier equilibrium. This must be specified, since ITM has a strong effect on the turnoff time of the device. Then, the SCR current is reversed at a specified di/dt rate, usually by shunting the SCR anode to some negative voltage through an inductor. The SCR will then display a reverse recovery current, which is the charge clearing away from the junctions. A further waiting time must then elapse while charges recombine, before a forward voltage can be applied. This forward voltage is ramped up a specified dv/dt rate. The dv/dt delay time is reduced until a critical point is reached where the SCR can no longer block the forward applied voltage ramp. In effect, the SCR turns on and consequently, the ramp voltage collapses. The elapsed time between this critical point and the point at which the forward SCR current passes through zero and starts to go negative (reverse recovery phase), is the tq of the SCR. This is illustrated by the waveforms shown in Figure 5.2.
tq GENERAL TEST FIXTURE
Synchronized Pulse Generator establishes system timing; a Constant Current Generator (variable in amplitude) powers the Device Under Test (DUT); a di/dt Circuit controls the rate of change of the SCR turnoff current; and the dv/dt Circuit reapplies a controlled forward blocking voltage. Note from the waveforms illustrated that the di/dt circuit, in parallel with the DUT, diverts the constant current from the DUT to produce the described anode current ITM.
tq TEST FIXTURE CHARACTERISTICS
The simplified circuit for generating these waveforms is schematically illustrated in Figure 5.3. This circuit is implemented with as many as eight transformers including variacs, and in addition to being very bulky, has been known to be troublesome to operate. However, the configuration is relevent and, in fact, is the basis for the design, as described in the following paragraphs.
tq TEST FIXTURE BLOCK DIAGRAMS AND WAVEFORMS
The block diagram of the tq Test Fixture, illustrated in Figure 5.4, consists of four basic blocks: A Line
ITM 50% ITM 50% IRM di/dt
The complete schematic of the tq Test Fixture and the important waveforms are shown in Figures 5.5 and 5.6, respectively. A CMOS Gate is used as the Line Synchronized Pulse Generator, configured as a wave shaping Schmitt trigger, clocking two cascaded monostable multivibrators for delay and pulse width settings (Gates 1C to 1F). The result is a pulse generated every half cycle whose width and position (where on the cycle it triggers) are adjustable by means of potentiometers R2 and R3, respectively. The output pulse is normally set to straddle the peak of the ac line, which not only makes the power supplies more efficient, but also allows a more consistent oscilloscope display. This pulse shown in waveform A of Figure 5.6 initiates the tq test, which requires approximately 0.5 ms to assure the device a complete turn on. A fairly low duty cycle results, (approximately 5%) which is important in minimizing temperature effects. The repetitive nature of this test permits easy oscilloscope viewing and allows one to readily walk in the dv/dt ramp. This is accomplished by adjusting the appropriate potentiometer (R7) which, every 8.33 ms (every half cycle) will apply the dv/dt ramp at a controlled time delay.
IDX
IRM trr tq dv/dt VDX
VT
Figure 5.2. SCR Current and Voltage Waveforms During CircuitCommutated TurnOff
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S2 IT S3 L1 R2
D1 S1 IT I1 S4 C1 V1 R1 V3 DUT D3 V2 D2 dv/dt di/dt
Figure 5.3. Simplified tq Test Circuit
To generate the appropriate system timing delays, four RC integrating network/comparators are used, consisting of opamps U2, U5 and U6. Opamp U2A, along with transistor Q2, optocoupler U4 and the following transistors Q6 and Q7, provide the gate drive pulse to the DUT (see waveforms B, C and D of Figure 5.6). The resulting gate current pulse is about 50 s wide and can be selected, by means of switch S2, for an IGT of from about 1 mA to 90 mA. Optocoupler U4, as well as U1 in the Constant Current Circuit, provide electrical isolation between the power circuitry and the low level circuitry. The Constant Current Circuit consists of an NPN Darlington Q3, connected as a constant current source driving a PNP triDarlington (Darlington Q4, Bipolar Q5). By varying the base voltage of Q3 (with Current Control potentiometer R4), the collector current of Q3 and thus the base voltage of Q4 will also vary. The PNP output transistor Q5 (MJ14003) (rated at 70 A), is also configured as a constant current source with four, parallel connected emitter resistors (approximately 0.04 ohms, 200 W), thus providing as much as 60 A test current. Very briefly, the circuit operates as follows: CMOS Gate 1E is clocked high, turning on, in order, a) NPN transistor Q16, b) PNP transistor Q1, c) optocoupler U3, and d) transistors Q3, Q4 and Q5. The board mounted Current Set potentiometer R5, sets the maximum output current and R4, the Current Control, is a front panel, multiturn potentiometer.
CONSTANT CURRENT GENERATOR
D1 IT dv CIRCUIT dt di CIRCUIT dt
DUT LINE SYNC PULSE GENERATOR IGT
CONSTANT CURRENT di/dt
IT 0 V1 dv/dt
di/dt
dv/dt
Figure 5.4. Block Diagram of the tq Test Fixture and Waveforms
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LINE SYNCHRONIZED PULSE GENERATOR + 10 V + 10 V 220 k 22 k 2 1A 1C 100 k + 10 V 3 LM317T U7 + 240 2N3904 Q16 10 k + 50,000 F 25 V STANCOR P6337 CONSTANT CURRENT CIRCUIT 1N 914 510 k 5 100 1/2 W 4 1k MPS A13 D1 100 1W + 10 V 82 90 mA 120 70 160 50 330 30 820 10 1k IT DUT 150 k o 150 V V1 GATE CURRENT SW S2 100 k Q3 * L1 100 1W 12 k + 10 V 4N35 U3 2 Q2 0.1 F 1N4728 3.3 k 3.3 V 2N3904 10 k 430 2W MJ 14003 Q5 (3) MTM15N06E Q10 560 2W + 10 V 2N6042 Q4 47 2W 1.2 k 2W 0.1 F (4) 0.15 , 50 W 1.8 k 50 F 20 V 47 k 1k 1.5 k Q1 2N 3906 2 + 10 V + 20 V (UNLOADED) + 12 V (LOADED) 25 k R3 PULSE WIDTH CONTROL 7 5 6 1 4 + 10 V 16 1B 8 3 220 pF 150 k 100 k 15 0.1 F 11 12 9 1E 1F 1D 14 13 10 0.001 4.7 k F 2 A S.B. POWER ON 0.1 F 200 V 0.1 F, 200 V SW S1 1M 0.01 F 1N914 U1 MC14572 R2 PULSE DELAY + 10 V CONTROL
1k 10 k
TRIAD F93X
1N4001
120 V SWD
2000 F
25 V 1
120 V 60 Hz
V1 18 V TYP 10 V 100 F + 20 V
20,000 F 25 V
1/2 W
1k
5 V 10 V
330 1W
0.1 F
di CIRCUIT dt Q11 560 2W 1K 2W 1N 5932A 0.001 F Q12 .001 560 2W F 1K 2W 0.002 1N F 5932A 0.001 F
1N4733 5.1 V, 1 W + 3 2 U2A 820 pF (1/2) MC1458
1N4740 10 V, 1 W
1N 5370A 1.2 K 56 V 2W 5W V2 o MR856
1 4N35 U4 1k 2 1k 1k Q6 10 k 2N3904 + 10 V 3.3 k VREF 1W 100 1W 4 2N 4919 Q7 20
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CURRENT CONTROL R4 1k CURRENT SET R5 + 10 V 5 5V 8.2 k 1 mA SW.53 OFF + 10 V BIAS 0.1 F U6 MC1741 150 k, 10 T 1 k 0.001 F 7 (1/2) MC1458 tq TIME CONTROL R7 3 10 k 1k 4.7 k 0.1 F 50 k 0.02 F 6 U2B R6 ON TIME CONTROL 5 + 1N4728 7 1.8 k 6 + 2 U6 4 10 k 3.3 V 0.1 F 10 V 39 k 0.002 F 10 V
1N 5932A 20 V 1.5 W I1
L1:
0 H (TYP) *DIODE REQUIRED WITH L1
R1
A
1000 C1 1N 4747 + 10 V 0.1 F MJE 250 Q14 2N3904 Q13 + 10 V dv CIRCUIT dt 0.1 F 5 8 + 7 6 U5 4 (1/2) MC1458 U5 + V1 18 V MTM2N90 Q15 1k 2W
+ V1 o 0.001 F 1k MJE254 Q9
+ 10 V 470 56 2W
D1:
MR506 FOR 3 A, HIGH tq DUTS MR856 FOR 3 A, LOW tq DUTS (DIODE IF SCALED TO DUT IA)
10 k
I1:
50 mA FOR HIGH tq DUTS
o 1N4728 100 470 10 k 1N 914 2N4401 SYNC Q8 OUT
1 A FOR LOW tq
50 V (TYP) R1 1 k
V1
V1
R1
50 V (TYP) 50
C1:
DETERMINED BY SPEC dv/dt
V2:
12 V (TYP),
t 50 V
10 F 15 V
Figure 5.5. tq Test Fixture
Time delay for the di/dt Circuit is derived from cascaded opamps U2B and U5 (waveforms F and G of Figure 5.6). The output gate, in turn, drives NPN transistor Q8, followed by PNP transistor Q9, whose output provides the gate drive for the three parallel connected Nchannel power MOSFET transistors Q10 Q12 (waveforms H of Figure 5.6). These three FETs (MTM15N06), are rated at 15 A continuous drain current and 40 A pulsed current and thus can readily divert the maximum 60 A constant current that the Fixture can generate. The results of this diversion from the DUT is described by waveforms E, H and I of Figure 5.6, with the di/dt of of ITM dictated by the series inductance L1. For all subsequent testing, the inductor was a shorting bar, resulting in very little inductance and consequently, the highest di/dt (limited primarily by wiring inductance). When a physical inductor L1 is used, a clamp diode, scaled to the diverted current, should be placed across L1 to limit inductive kicks.
shown in Figure 5.7 where both a fast recovery rectifier and standard recovery rectifier were used in measuring tq of a standard 2N6508 SCR. Although the di/dts were the same, the reverse recovery current IRM and trr were greater with the standard recovery rectifier, resulting in a somewhat shorter tq (59 s versus 63 s). In fact, tq is affected by the initial conditions (ITM, di/dt, IRM, dv/dt, etc.) and these conditions should be specified to maintain measurement repeatability. This is later described in the published curves and tables. Finally, the resistor R1 and the resultant current I1 in the dv/dt circuit must meet certain criteria: I1 should be greater than the SCR holding current so that when the DUT does indicate tq limitation, it latches up, thus suppressing the dv/dt ramp voltage; and, for fast SCRs (low tq), I1 should be large enough to ensure measurement repeatability. Typical values of I1 for standard and fast SCRs may be 50 mA and 500 mA, respectively. Obviously, for high forward blocking voltage + V1 tests, the power requirements must be met.
EFFECTS OF GATE BIAS ON tq
dv/dt CIRCUIT
The last major portion of the Fixture, the dv/dt Circuit, is variable time delayed by the multiturn, front panel tq Time Control potentiometer R7, operating as part of an integrator on the input of comparator U6. Its output (waveform J of Figure 5.6) is used to turnoff, in order, a) normally on NPN transistor Q13, b) PNP transistor Q14 and c) Nchannel power MOSFET Q15 (waveform L of Figure 5.6). This FET is placed across ramp generating capacitor C1, and when unclamped (turned off), the capacitor is allowed to charge through resistor R1 to the supply voltage + V1. Thus, the voltage appearing on the drain will be an exponentially rising voltage with a dv/dt dictated by R1, C1, whose position in time can be advanced or delayed. This waveform is then applied through a blocking diode to the anode of the DUT for the forward blocking voltage test. Another blocking diode, D1, also plays an important role in tq measurements and must be properly selected. Its purpose is to prevent the dv/dt ramp from feeding back into the Current Source and di/dt Circuit and also to momentarily apply a reverse blocking voltage (a function of V2 of the di/dt circuit) to the DUT. Consequently, D1 must have a reverse recovery time trr greater than the DUT, but less than the tq time. When measuring standard recovery SCRs, its selection fast recovery rectifiers or standard recovery is not that critical, however, for fast recovery, low tq SCRs, the diode must be tailored to the DUT to produce accurate results. Also, the current rating of the diode must be compatible with the DUT test current. These effects are illustrated in the waveforms
Examples of the effects of I1 on tq are listed in Table 5.III whereby standard and fast SCRs were tested with about 50 mA and 1 A, respectively. Note that the low tq SCRs required fast recovery diodes and high I1 current.
TEST FIXTURE POWER SUPPLIES
Most of the power supplies for the system are self contained, including the + 12 V supply for the Constant Current Circuit. This simple, unregulated supply furnishes up to 60 A peak pulsed current, primarily due to the line synchronized operation of the system. Power supplies +V1 and V2, for this exercise, were external supplies, since they are variable, but they can be incorporated in the system. The reverse blocking voltage to the DUT is supplied by V2 and is typically set for about 10 V to 20 V, being limited to the breakdown voltage of the diverting power MOSFETS (VDSS = 60 V). The + 12 V unregulated supply can be as high as + 20 V when unloaded; therefore, V2 (MAX), in theory, would be 40 V but should be limited to less than 36 V due to the 56 V protective Zener across the drainsource of the FETs. Also, V2 must be capable of handling the peak 60 A, diverting current, if so required. The reapplied forward blocking voltage power supply +V1, may be as high as the DUT VDRM which conceivably can be 600 V, 1,000 V or greater and, since this supply is on most of the time, must be able to supply the required I1. Due to the sometimes high power requirements, + V1 test conditions may have to be reduced for extremely fast SCRs.
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PARAMETERS AFFECTING tq
To see how the various circuit parameters can affect tq, one condition at a time is varied while the others are held constant. The parameters to be investigated are a) forward current magnitude (ITM), b) forward current duration, c) rate of change of turnoff current (di/dt), d) reverse current magnitude (IRM), e) reverse voltage (VRM), f) rate of reapplied forward voltage (dv/dt), g) magnitude limit of reapplied voltage, h) gatecathode resistance and i) gate drive magnitude (IGT). Typical data of this kind, taken for a variety of SCRs, including standard SCRs, high speed SCRs, is con-
densed and shown in Table 5.1. The data consists of the different conditions which the particular SCR types were subjected to; ten SCRs of each type were serialized and tested to each condition and the ten tqs were averaged to yield a typical tq. The conditions listed in Column A in Table 5.1, are typical conditions that might be found in circuit operation. Columns B through J in Table 5.1, are in order of increasing tq; the conditions listed in these columns are only the conditions that were modified from those in Column A and if a parameter is not listed, it is the same as in Column A.
Q1 COL. A U2, P1 B U4, P4 C IGT D CONSTANT CURRENT GEN. E Q5 COL. U2, P7 F U5, P7 G Q9 COL. Q10Q12 di/dt CIRCUIT IT DUT U6, P6 dv/dt CIRCUIT Q15 GATE dv/dt Q15 DRAIN dv/dt OUTPUT H I J K
L 0 200 400 t, TIME (s) 600 800
Figure 5.6. tq Test Fixture System Waveforms
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I = 2 A/Div
0A V = 10 V/Div
0V
tq = 63 s
t = 50 s/Div
t = 1 s/Div
D1 = MR856, FAST RECOVERY RECTIFIER
I = 2 A/Div
0A V = 10 V/Div
0V
tq = 59 s
t = 50 s/Div
t = 1 s/Div
D1 = 1N5402, STANDARD RECOVERY RECTIFIER
Figure 5.7. The Effects of Blocking Diode D1 on tq of a 2N6508 SCR
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Table 5.1. Parameters Affecting tq

B C D E F G H I
Device
2N6508 25 A 600 V RGK = 100 dv/dt = 2.4 V/s ITM = 1 A IRM = 1.8 A di/dt = 32 A/s RGK = 100 dv/dt = 2.4 V/s IRM = 50 mA di/dt = 0.45 A/s RGK = 100 dv/dt = 2.4 V/s RGK = 100 typ tq = 65 s typ tq = 60 s typ tq = 64 s typ tq = 64 s RGK = dv/dt = 2.4 V/s RGK = 100 dv/dt = 2.4 V/s ITM = 2 A IRM = 50 mA di/dt = 0.5 s
RGK = 1 k dv/dt = 15 V/s ITM = 25 A IRM = 14 A di/dt = 100 A/s ITM duration = 275 s IGT = 30 mA
1
RGK = 100 dv/dt = 2.4 V/s ITM = 37 A
IGT = 90 mA typ tq = 68 s
typ tq = 68 s
typ tq = 42 s
typ tq = 45 s
typ tq = 49 s
2N6399 12 A RGK = 100 dv/dt = 2.5 V/s ITM = 1 A IRM = 50 mA di/dt = 0.5 A/s RGK = 100 dv/dt = 2.5 V/s IRM = 50 mA di/dt = 32 A/s RGK = 100 typ tq = 45 s typ tq = 32 s typ tq = 33 s typ tq = 35.5 s RGK = dv/dt = 2.5 V/s IRM = 50 mA di/dt = 0.35 A/s RGK = 100 dv/dt = 2.5 V/s ITM = 1 A IRM = 2.7 A di/dt = 56 A/s RGK = 100 dv/dt = 2.5 V/s ITM = 18 A IRM = 50 mA di/dt = 0.3 A/s
RGK = 1 k dv/dt = 90 V/s ITM = 12 A IRM = 11 A di/dt = 100 A/s ITM duration = 275 s IGT = 30 mA typ tq = 30 s typ tq = 31 s
IGT = 90 mA typ tq = 48 s
typ tq = 48 s
Table 5.1. Continued

B C D E F G H I
Device
C106B 4A
IGT = 1 mA RGK = 1 k dv/dt = 5 V/ms ITM = 4A IRM = 4A di/dt = 50 A/ms ITM duration = 275 ms VDX = 50 V ITM = 2 A IRM = 2.5 A di/dt = 30 A/ms VDX = 50 V V2 = 35 V IRM = 0.2 A di/dt = 1.4 A/ms typ tq = 27 ms typ tq = 27 ms typ tq = 27 ms IRM = 0.15 A V2 = 4 V di/dt = 1.4 A/ms dv/dt = 1.4 V/ms IRM = 0.15 A di/dt = 1.4 A/ms typ tq = 25 ms typ tq = 26 ms typ tq = 26 ms typ tq = 26 ms ITM = 6 A IRM = 1 A/ms di/dt = 1 A/ms VDX = 150 V ITM = 6 A IRM = 0.1 A di/dt = 1 A/ms VDX = 50 V dv/dt = 1.4 V/ms ITM = 2 A IRM = 0.2 A di/dt = 1.4 A/ms IGT = 90 mA dv/dt = 1.4 V/ms IRM = 2 A di/dt = 1.4 A/ms typ tq = 27 ms
typ tq = 28 ms
2N6240 4A
RGK = 1 k dv/dt = 40 V/ms ITM = 4 A IRM = 4 A di/dt = 50 A/ms ITM duration = 275 ms IGT = 1 mA VDX = 50 V RGK = 100 dv/dt = 1.3 V/ms ITM = 1 A IRM = 50 mA di/dt = 0.5 A/ms IGT = 90 mA VDX = 150 V RGK = 100 dv/dt = 1.75 V/ms ITM = 1 A IRM = 50 mA di/dt = 0.5 A/ms IGT = 90 mA RGK = 100 dv/dt = 1.75 V/ms IRM = 50 mA di/dt = 0.5 A/ms IGT = 90 mA RGK = 100 IRM = 50 mA di/dt = 0.5 A/ms IGT = 90 mA RGK = 100 IGT = 900 mA typ tq = 32.7 ms typ tq = 30 ms typ tq = 27.7 ms typ tq = 28.6 ms typ tq = 26.2 ms dv/dt = 1.75 V/ms RGK = 100 ITM = 6 A IRM = 50 mA di/dt = 0.5 A/ms IGT = 90 mA typ tq = 26 ms
RGK = dv/dt = 1.75 V/ms ITM = 1 A IRM = 50 mA di/dt = 0.5 A/ms IGT = 90 mA typ tq = 37.2 ms
IGT = 90 mA typ tq = 41.4 ms
typ tq = 44.8 ms
MCR1006 0.8 A dv/dt = 30 V/ms ITM = 0.25 A IRM = 40 mA di/dt = 0.6 A/ms dv/dt = 30 V/ms Ir = 40 mA di/dt = 0.8 A/ms V2 = 9 V IRM = 20 mA di/dt = 0.4 A/ms typ tq = 13.7 ms typ tq = 13.9 ms V2 = 1 V Ir = 40 mA di/dt = 0.8 A/ms typ tq = 13.5 ms typ tq = 12.7 ms dv/dt = 30 V/ms ITM = 1.12 A IRM = 40 mA di/dt = 0.8 A/ms typ tq = 14.4 ms
dv/dt = 5 V/ms ITM = 0.2 A IRM = 50 mA di/dt = 0.6 A/ms dv/dt = 5 V/ms IRM = 50 mA di/dt = 0.8 A/ms typ tq = 30/ms typ tq = 31 ms typ tq = 27/ms dv/dt = 5 V/ms ITM = 1.12 A IRM = 50 mA di/dt = 0.8 A/ms IRM = 40 mA V2 = 9 V di/dt = 0.45 A/ms typ tq = 31.2 ms IRM = 40 mA V2 = 1 V di/dt = 0.8 A/ms typ tq = 31.4 ms dv/dt = 3.5 V/ms ITM = 0.25 A IRM = 40 mA di/dt = 0.7 A/ms dv/dt = 3.5 V/ms IRM = 40 mA di/dt = 0.8 A/ms typ tq = 19/ms typ tq = 19.1 ms dv/dt = 3.5 V/ms ITM = 1.12 A IRM = 40 mA di/dt = 0.8 A/ms VDX = 60 V typ tq = 19.8 ms dv/dt = 3.58/ms ITM = 1.12 A IRM = 40 mA di/dt = 0.7 A/ms typ tq = 20.2 ms V2 = 4 V IRM = 20 mA di/dt = 0.2 A/ms typ tq = 30 ms
RGK = 1 k dv/dt = 160 V/ms ITM = 0.8 A IRM = 0.8 A di/dt = 12 A/ms VDX = 50 V ITM duration = 275 ms
dv/dt = 30 V/ms ITM = 1.12 A IRM = 40 mA di/dt = 0.8 A/ms VDX = 100 V typ tq = 14.4 ms
typ tq = 14.4 ms
2N5064 0.8 A
RGK = 1 k dv/dt = 30 V/ms ITM = 0.8 A IRM = 0.8 A di/dt = 12 A/ms ITM duration = 275 ms VDX = 50 V
VDX = 100 V dv/dt = 5 V/ms ITM = 1.12 A IRM = 50 mA di/dt = 0.8 A typ tq = 31.7 ms
typ tq = 28.9 ms
2N5061 0.8 A
dv/dt = 10 V/ms ITM = 0.8 A IRM = 0.8 A di/dt = 18 A/ms ITM duration = 275 ms RGK = 1 k VDX = 30 V
V2 = 1 V IRM = 40 mA di/dt = 0.8 A/ms typ tq = 30.2 ms
typ tq = 31.7 ms
Table 5.2 is a condensed summary of Table 5.1 and shows what happens to the tq of the different devices when a parameter is varied in one direction or the other. THE EFFECT OF CHANGING PARAMETERS ON tq From Tables 5.1 and 5.2, it is clear that some parameters affect tq more than others. The following discussion describes the effect on tq of the various parameters.
FORWARD CURRENT MAGNITUDE (ITM)
Parameter Changed IGT Increase
Device 2N6508 2N6399 2N6240 C106F 2N6508 2N6399 2N6240 2N6508 2N6399 2N6240 C106F 2N6240 MCR1006 2N5064 2N5061 2N6508 C106F 2N6240 2N6508 2N6399 C106F 2N6240
Columns AI AG AI HI AH AG GI EF DF CH DC BC FG DG DE EH HJ DF EG DE EH DC DE CE CF CD BE
1st (s) 68 48 44.8 27 68 48 41.4 60 32 26.2 26 26.2 14.4 31 20.2 65 29 30 60 32 26 26.2 27.7 26.2 13.5 30.7 19.1
2nd (s) 68 48 41.4 27 65 45 32.7 64 35.5 37.2 26 26 14.4 31.7 19.8 60 27 27.7 64 33 27 27.7 28.6 28.6 14.4 31 20.7
Decrease RGK 1 k to 100 ohms Increase RGK 1 k to
Of the parameters that were investigated, forwardcurrent magnitude and the di/dt rate have the strongest effect on tq. Varying the ITM magnitude over a realistic range of ITM conditions can change the measured tq by about 30%. The change in tq is attributed to varying current densities (stored charge) present in the SCRs junctions as the ITM magnitude is changed. Thus, if a large SCR must have a short tq when a low ITM is present, a large gate trigger pulse (IGT magnitude) would be advantageous. This turns on a large portion of the SCR to minimize the high current densities that exists if only a small portion of the SCR were turned on (by a weak gate pulse) and the low ITM did not fully extend the turned on region. In general, the SCR will exhibit longer tq times with increasing ITM. Increasing temperature also increases the tq time.
di/dt RATE
VDX
Decrease dv/dt Rate
Increase ITM
MCR1006 2N5064 2N5061
Table 5.2. The Effects of Changing Parameters on tq
Varying the turnoff rate of change of anode current di/dt does have some effect on the tq of SCRs. Although the increase in tq versus increasing di/dt was nominal for the SCRs illustrated, the percentage change for the fast SCRs was fairly high (about 30 40%).
REVERSE CURRENT MAGNITUDE (IRM)
By using different series inductors and changing the negative anode turnoff voltage, it is possible to keep the di/dt rate constant while changing IRM. It was found that IRM has little or no effect on tq when it is the only variable changed (see Table 5.1 C106F, Columns F and G, for example).
REVERSE ANODE VOLTAGE (VRM)
The reverse current is actually due to the stored charge clearing out of the SCRs junctions when a negative voltage is applied to the SCR anode. IRM is very closely related to the di/dt rate; an increasing di/dt rate causing an increase of IRM and a decreasing di/dt rate causing a lower IRM.
Reverse anode voltage has a strong effect on the IRM magnitude and the di/dt rate, but when VRM alone is varied, with IRM and di/dt held constant, little or no change in tq time was noticed. VRM must always be within the reverse voltage of the device.
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Gate Bias Device 0V tq1 2N6508 2N6240 2N6399 C106F 40 s 16 s 30 s 13 s 5V tq2 30 s 9 s 25 s 8 s
Conditions V2 = 10 V, IF = 3 A Diode DI Slow MR502 Slow Slow Slow dv/dt (V/s) 2.5 2.5 2.5 2.5
+ V1 50 V Remarks
RI 1 k/50
dv/dt (v/s) 2.5/50
Slow diode faster than fast diode, (lower tq) Slow diode faster. 2.5 V/s faster than 50 V/s Tested slow diode only Tested slow diode only
Table 5.3 The Effects of Gate Bias on tq
25 STANDARD SCR t q, TURN-OFF TIME (s) 20 15 10 5 0 1 2 5 10 20 50 ITM, ANODE CURRENT (AMPS) C106F C106 dv/dt RGK TA di/dt : : : : 5 A/ s 45 V/ s 100 25C
MAGNITUDE LIMIT OF REAPPLIED dv/dt (VDX)
Changing the magnitude limit of the reapplied dv/dt voltage has little or no effect on a given SCRs tq time when the maximum applied voltage is well below the voltage breakdown of the SCR. The tq times will lengthen if the SCR is being used near its voltage breakdown, since the leakage present near breakdown is higher than at lower voltage levels. The leakage will lengthen the time it takes for the charge to be swept out of the SCRs center junction, thus lengthening the time it takes for this junction to return to the blocking state.
GATE CATHODE RESISTANCE (RGK)
Figure 5.8. Standard SCR TurnOff Time tq as a Function of Anode Current ITM
In general, the lower the RGK is, the shorter the tq time will be for a given SCR. This is because low RGK aids in the removal of stored charge in the SCRs junctions. An approximate 15% change in the tq time is seen by changing RGK from 100 ohms to 1000 ohms for the DUTs.
GATE DRIVE MAGNITUDE (IGT)
REAPPLIED dv/dt RATE
Varying the reapplied dv/dt rate across the range of dv/dts commonly encountered can vary the tq of a given SCR by more than 10%. The effect of the dv/dt rate on tq is due to the AnodeGate capacitance. The dv/dt applied at the SCR anode injects current into the gate through this capacitance (iGT = C dv/dt). As the dv/dt rate increased, the gate current also increases and can trigger the SCR on. To complicate matters, this injected current also adds to the current due to leakage or stored charge left in the junctions just after turnoff. The stored charge remaining in the center junction is the main reason for long tq times and, for the most part, the charge is removed by the recombination process. If the reapplied dv/dt rate is high, more charge is injected into this junction and prevents it from returning to the blocking state, as soon as if it were a slow dv/dt rate. The higher the dv/dt rate, the longer the tq times will be.
Changing the gate drive magnitude has little effect on a SCRs tq time unless it is grossly overdriven or underdriven. When it is overdriven, there is an unnecessary large amount of charge in SCRs junction. When underdriven, it is possible that only a small portion of the chip at the gate region turns on. If the anode current is not large enough to spread the small turned on region, there is a high current and charge density in this region that consequently lengthens the tq time.
FORWARD CURRENT DURATION
Forward current duration had no measurable effect on tq time when varied from 100 s to 300 s, which were the limits of the ON Semiconductor tq Tester. Longer ITM durations heat up the SCR which causes temperature effects; very short ITM durations affect the tq time due to the lack of time for the charges in the SCRs junctions to reach equilibrium, but these effects were not seen in the range tested.
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REVERSE GATE BIAS VOLTAGE
As in transistor operation, reverse biasing the gate of the SCR decreases the turnoff time, due to the rapid sweeping out of the stored charge. The reduction in tq for standard SCRs is quite pronounced, approaching perhaps 50% in some cases; for fast SCRs, only nominal improvement might result. Table 5.3 shows this effect on six SCRs where the gate bias was set for 0 V and 5 V, respectively (the 1 k gate resistor of the DUT was either grounded or returned to 5 V). Due to the internal, monolithic resistor of most SCRs, the actual reverse bias voltage between the gatecathode is less than the reverse bias supply. CHARACTERIZING SCRs FOR CROWBAR APPLICATIONS The use of a crowbar to protect sensitive loads from power supply overvoltage is quite common and, at the first glance, the design of these crowbars seems like a straightforward, relatively simple task. The crowbar SCR is selected so as to handle the overvoltage condition and a fuse is chosen at 125 to 250% of the supplys rated fullload line current. However, upon further investigation, other questions and problems are encountered. How much overvoltage and for how long (energy) can the load take this overvoltage? Will the crowbar respond too slowly and thus not protect the load or too fast resulting in false, nuisance triggering? How much energy can the crowbar thyristor (SCR) take and will it survive until the fuse opens or the circuit breaker opens? How fast will the fuse open, and at what energy level? Can the fuse adequately differentiate between normal current levels including surge currents and crowbar short circuit conditions? It is the attempt of this section to answer these questions to characterize the load, crowbar, and fuse and thus to match their characteristics to each other. The type of regulator of most concern is the low voltage, series pass regulator where the filter capacitors to be crowbarred, due to 60 Hz operation, are relatively large and the charge and energy stored correspondingly large. On the other hand, switching regulators operating at about 20 kHz require smaller capacitors and thus have lower crowbar constraints. These regulators are quite often lineoperated using a high voltage, twotransistor inverter, half bridge or full bridge, driving an output stepdown transformer. If a transistor were to fail, the regulatortransformed power would be less and the output voltage would drop, not rise, as is the case for the linear series regulator with a shorted pass transistor. Thus, the need for overvoltage protection of these types of switching regulators is minimized. This premise, however, does not consider the case of the lower power series switching regulator where a
shorted transistor would cause the output voltage to rise. Nor does it take into account overvoltage due to transients on the output bus or accidental power supply hookup. For these types of operations, the crowbar SCR should be considered. HOW MUCH OVERVOLTAGE CAN THE LOAD TAKE? Crowbar protection is most often needed when ICs are used, particularly those requiring a critical supply voltage such as TTL or expensive LSI memories and MPUs. If the load is 5 V TTL, the maximum specified continuous voltage is 7 V. (CMOS, with its wide power supply range of 3 to 18 V, is quite immune to most overvoltage conditions.) But, can the TTL sustain 8 V or 10 V or 15 V and, if so, for how long and for how many power cycles? Safe Operating Area (SOA) of the TTL must be known. Unfortunately, this information is not readily available and has to be generated.
20 V , SUPPLY VOLTAGE (VOLTS) CC TJ 85C, DUTY CYCLE = 10% VCC 5V PULSE WIDTH
18
16
14
12
10
10
30 50 PULSE WIDTH (ms)
100
300 500
Figure 5.9. Pulsed Supply Voltage versus Pulse Width
Using the test circuit illustrated in Appendix III, a quasiSOA curve for a typical TTL gate was generated (Figure 5.9). Knowing the overvoltagetime limit, the crowbar and fuse energy ratings can be determined. The two possible configurations are illustrated in Figure 5.10, the first case shows the crowbar SCR across the input of the regulator and the second, across the output. For both configurations, the overvoltage comparator senses the load voltage at the remote load terminals, particularly when the IR drop of the supply leads can be appreciable. As long as the output voltage is less than that of the comparator reference, the crowbar SCR will be in an off state and draw no supply current. When an overvoltage condition occurs, the comparator will produce a gate trigger to the SCR, firing it, and thus clamping the regulator input, as in the first case to the SCRs onstate drop of about 1 to 1.5 V, thereby protecting the load.
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(a). SCR Across Input of Regulator

F
D1
Vin
SERIES REGULATOR OVERVOLTAGE SENSE Cin Co
vO
(b). SCR Across Output of Regulator
Vin
REGULATOR
* vO
OVERVOLTAGE SENSE
*NEEDED IF SUPPLY NOT CURRENT LIMITED
Figure 5.10. Typical Crowbar Configurations
Placing the crowbar across the input filter capacitors, although effectively clamping the output, has several disadvantages. 1. There is a stress placed on the input rectifiers during the crowbarring short circuit time before the line fuse opens, particularly under repeated operation. 2. Under low line conditions, the minimum short circuit current can be of the same magnitude as the maximum primary line current at high line, high load, making the proper fuse selection a difficult choice. 3. The capacitive energy to be crowbarred (input and output capacitor through rectifier D1) can be high. When the SCR crowbar and the fuse are placed in the dc load circuit, the above problems are minimized. If crowbarring occurs due to an external transient on the line and the regulators current limiting is working properly, the SCR only has to crowbar the generally smaller output filter capacitor and sustain the limited regulator current. If the series pass devices were to fail (short), even with current limiting or foldback disabled, the crowbarred energy would generally be less than of the previous case. This is due to the higher impedance of the shorted regulator (due to emitter sharing and current sensing resistors) relative to that of rectifier D1.
Fuse selection is much easier as a fault will now give a greater percentage increase in dc load current than when measuring transformer primary or secondary rms current. The disadvantage, however, of placing the fuse in the dc load is that there is no protection for the input rectifier, capacitor, and transformer, if one of these components were to fail (short). Secondly, the one fuse must protect not only the load and regulator, but also have adequate clearing time to protect the SCR, a situation which is not always readily accomplished. The input circuitry can be protected with the addition of a primary fuse or a circuit breaker. HOW MUCH ENERGY HAS TO BE CROWBARRED? This is dictated by the power supply filter capacitors, which are a function of output current. A survey of several linear power supply manufacturers showed the output filter capacitor size to be from about 100 to 400 microfarads per ampere with about 200 F/A being typical. A 30 A regulator might therefore have a 6000 F output filter capacitor.
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Additionally, the usually much larger input filter capacitor will have to be dumped if the regulator were to short, although that energy to be dissipated will be dependent on the total resistance in the circuit between that capacitor and the SCR crowbar. The charge to be crowbarred would be
Q
+ CV + IT,
the energy,
E
+ 12 CV2
i pk C +V RT
and the peak surge current
When the SCR crowbars the capacitor, the current waveform will be similar to that of Figure 5.11, with the peak surge current, ipk, being a function of the total impedance in the circuit (Figure 5.12) and will thus be limited by the Equivalent Series Resistance (ESR) and inductance (ESL) of the capacitor plus the dynamic impedance of the SCR, any external current limiting resistance, (and inductance) of the interconnecting wires and circuit board conductors. The ESR of computer grade capacitors, depending on the capacitor size and working voltage, might vary from 10 to 1000 milliohms (m). Those used in this study were in the 25 to 50 m range. The dynamic impedance of the SCR (the slope of the onstate voltage, onstate current curve), at high currents, might be in the 10 to 20 m range. As an example, from the onstate characteristics of the MCR70, 35 A rms SCR, the dynamic impedance is
rd VF (4.5 * 3.4)V 1.1 V +D DIF + (300 * 200)A + 100 A `11 m.
The interconnecting wire might offer an additional 5 m (#20 solid copper wire 20 m/ft) so that the total circuit resistance, without additional current limiting, might be in the 40 to 70 m range. The circuit inductance was considered low enough to ignore so far as ipk is concerned for this exercise, being in hundreds of nanohenry range (ESL 3 nH, L wire 500 nH/ft). However, di/dt will be affected by the inductance.
HOW MUCH ENERGY CAN THE CROWBAR SCR SUSTAIN? There are several factors which contribute to possible SCR failures or degradation the peak surge current, di/dt, and a measure of the devices energy capability, I2t.
If the peak current and/or duration of the surge is large, destruction of the device due to excessive dissipation can occur. Obviously, the ipk can be reduced by inserting additional impedance in the crowbar path, at an increase in dump time. However, this time, which is a measure of how long the overvoltage is present, should be within the SOA of the load. The energy stored in the capacitor being a constant for a particular voltage would suggest that the I2t integral for any limiting resistance is also a constant. In reality, this is not the case as the thermal response of the device must be taken into consideration. It has been shown that the dissipation capability of a device varies as to the t for the first tens of milliseconds of the thermal response and, in effect, the measure of a devices energy capability would be closer to i2 t. This effect is subsequently illustrated in the empirically derived ipk versus time derating curves being a nonlinear function. However, for comparison with fuses, which are rated in I2t, the linear time base, t, will be used. The di/dt of the current surge pulse is also a critical parameter and should not exceed the devices ratings (typically about 200 A/s for 50 A or less SCRs). The magnitude of di/dt that the SCR can sustain is controlled by the device construction and, to some extent, the gate drive conditions. When the SCR gate region is driven on, conduction across the junction starts in a small region and progressively propagates across the total junction. Anode current will initially be concentrated in this small conducting area, causing high current densities which can degrade and ultimately destroy the device. To minimize this di/dt effect, the gate should be turned on hard and fast such that the area turned on is initially maximized. This can be accomplished with a gate current pulse approaching five times the maximum specified continuous gate current, Igt, and with a fast rise time (< 1 s). The gate current pulse width should be greater than the propagation time; a figure of 10 s minimum should satisfy most SCRs with average current ratings under 50 A or so. The wiring inductance alone is generally large enough to limit the di/dt. Since most SCRs are good for over 100 A/s, this effect is not too large a problem. However, if the di/dt is found excessive, it can be reduced by placing an inductance in the loop; but, again, this increases the circuits response time to an overvoltage and the tradeoff should be considered.
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ipk
0 t = 0.5 ms/Div 50% di/dt
10% 2.3 tW 10% tW 0 5 t
t = 10 s/Div I = 200 A/Div MCR69 C = 22,000 F RS = 0 VC = 30 V IGT = 200 mA
CROWBAR CURRENT TERMS
Figure 5.11. Typical SCR Crowbar Waveform
RW
LW
ESR
RS
ESL
LS
RW, LW: INTERCONNECTING WIRE IMPEDANCE RS, LS: CURRENT LIMITING IMPEDANCE
Figure 5.12. Circuit Elements Affecting SCR Surge Current
Since many SCR applications are for 60 Hz line operation, the specified peak nonrepetitive surge current ITSM and circuit fusing I2t are based on 1/2 cycle (8.3 ms) conditions. For some SCRs, a derating curve based on up to 60 or 100 cycles of operation is also published. This rating, however, does not relate to crowbar applications. To fully evaluate a crowbar system, the SCR must be characterized with the capacitor dump exponential surge current pulse. A simple test circuit for deriving this pulse is shown in Figure 5.13, whereby a capacitor is charged through a limiting resistor to the supply voltage, V, and then the charge is dumped by the SCR device under test (DUT). The SCR gate pulse can be varied in magnitude, pulse width, and rise time to produce the various IGT conditions. An estimate of the crowbar energy capability of the DUT is determined by first dumping the capacitor charged to low voltage and then progressively increasing the voltage until the DUT fails. This is repeated for several devices to establish an average and minimum value of the failure points cluster.
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100 DUT V 22,000 F 50 H.P. 214A PULSE GENERATOR
EXTERNAL TRIGGER
Figure 5.13
This procedure was used to test several different SCRs of which the following Table 5.4 describes several of the pertinent energy specifications and also the measured crowbar surge current at the point of device failure. This oneshot destruct test was run with a gate current of five IGT(MAX) and a 22,000 F capacitor whose ESR produced the exponentially decaying current pulse about 1.5 ms wide at its 10% point. Based on an appropriate derating, ten devices of each line where then successfully tested under the following conditions.
Device 2N6397 2N6507 VC 12 V 30 V ipk 250 A 800 A t 1.5 ms 1.5 ms
To determine the effect of gate drive on the SCRs, three devices from each line were characterized at nondestruct levels using three different capacitors (200, 6,000, and 22,000 F), three different capacitor voltages (10, 20, and 30 V), and three different gate drives (IGT(MAX), 5 IGT(MAX), and a ramp IGT(MAX) with a di/dt of
about 1 mA/s). Due to its energy limitations, the MCR68 was tested with only 10 V across the larger capacitors. The slow ramp, IGT, was used to simulate overvoltage sense applications where the gate trigger rise time can be slow such as with a coupling zener diode. No difference in SCR current characteristics were noted with the different gate current drive conditions; the peak currents were a function of capacitor voltage and circuit impedance, the fall times related to RTC, and the rise times, tr, and di/dt, were more circuit dependent (wiring inductance) and less device dependent (SCR turnon time, ton). Since the wiring inductance limits, tr, the effect of various IGTs was masked, resulting in virtually identical waveforms. The derated surge current, derived from a single (or low number) pulse test, does not truly reflect what a power supply crowbar SCR might have to see over the life of the supply. Life testing over many cycles have to be performed; thus, the circuit described in Appendix IV was developed. This life test fixture can simultaneously test ten SCRs under various crowbar energy and gate drive conditions.
Table 5.4. Specified and Measured Current Characteristics of Three SCRs

Maximum Specified Values Device Case IT(rms) (A) 2N6397 2N6507 TO220 TO220 12 25 IT(AV) (A) 8 16 ITSM* (A) 100 300 I2t (A2s) 40 375 IGT(Max) (mA) 30 40 Min (A) 380 1050 Measured Crowbar Surge Current Ipk Max (A) 750 1250 Ave (A) 480 1100
* ITSM = Peak NonRepetitive Surge Current, 1/2 cycle sine wave, 8.3 ms.
Each of the illustrated SCRs of Figure 5.14(a) were tested with as many as four limiting resistors (0, 50, 100, and 240 m) and run for 1000 cycles at a nominal energy level. If no failures occurred, the peak current was progressively increased until a failure(s) resulted. Then the current was reduced by 10% and ten new devices were tested for 2000 cycles (about six hours at 350 cycles/hour). If this test
proved successful, the data was further derated by 20% and plotted as shown on loglog paper with a slope of 1/4. This theoretical slope, due to the I2 t onedimensional heatflow relationship (see Appendix VI), closely follows the empirical results. Of particular interest is that although the peak current increases with decreasing time, as expected, the I2t actually decreases.
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3000 1000
NORMALIZED PEAK SURGE CURRENT
Ipk , PEAK CURRENT (AMPS)
C = 8400 F ESR 25 m VC 60 V
Ipk TA = 25C N = 2000 PULSES f = 3 PULSES/MIN. tW 5 TC
1 N = 2000 PULSES 0.8
2N6507 300 100 30 2N6397
0.6
0.4
0.2 0.1 0.5 5 10 tW, BASE PULSE WIDTH (ms) 1 50 100 0 25 50 75 100 125 TC, AMBIENT TEMPERATURE (C)
Figure 5.14(a). Peak Surge Current versus Pulse Width
(b). Peak Surge Current versus Ambient Temperature
Figure 5.14(b) shows the effect of elevated ambient temperature on the peak current capability of the illustrated SCRs. FUSE CHARACTERISTICS SCRs, like rectifiers, are generally rated in terms of average forward current, IT(AV), due to their halfwave operation. Additionally, an rms forward current, IT(rms), a peak forward surge current, ITSM, and a circuitfusing energy limit, I2t, may be shown. However, these specifications, which are based onehalf cycle 60 Hz operation, are not related to the crowbar current pulse and some means must be established to define their relationship. Also, fuses which must ultimately match the SCR and the load, are rated in rms currents. The crowbar energy curves are based on an exponentially decaying surge current waveform. This can be converted* to Irms by the equation.
I rms
+ 0.316 ipk
which now allows relating the SCR to the fuse. *See Appendix V The logic load has its own overvoltage SOA as a function of time (Figure 5.9). The crowbar SCR must clamp the overvoltage within a specified time, and still be within its own energy rating; thus, the serieslimiting resistance, RS, in the crowbar path must satisfy both the load and SCR energy limitations. The overvoltage response time is set by the total limitations. The overvoltage response time is set by the total limiting resistance and dumped capacitor(s) time constant. Since the SOA of the TTL used in this exercise was derived by a rectangular overvoltage pulse (in effect, overenergy), the energy equivalent of the realworld exponentially falling voltage waveform must be made. An approximation can be made by using an equivalent rectangular pulse of 0.7 times the peak power and 0.7 times the base time.
Once an overvoltage is detected and the crowbar is enabled, in addition to sustaining the peak current, the SCR must handle the regulator shortcircuit current for the time it takes to open the fuse. Thus, all three elements are tied together the load can take just so much overvoltage (overenergy) and the crowbar SCR must repeatedly sustain for the life of the equipment an rms equivalent current pulse that lasts for the fuse response time. It would seem that the matching of the fuse to the SCR would be straightforward simply ensure that the fuse rms current rating never exceed the SCR rms current rating (Figure 5.15), but still be sufficient to handle steadystate and normal overload currents. The more exact relationship would involve the energy dissipated in the system I2Rdt, which on a comparative basis, can be reduced to I2t. Thus, the letthrough I2t of the fuse should not exceed I2t capability of the SCR under all operating conditions. These conditions are many, consisting of available fault current, power factor of the load, supply voltage, supply frequency, ambient temperature, and various fuse factors affecting the I2t. There has been much detailed information published on fuse characteristics and, rather than repeat the text which would take many pages, the reader is referred to those sources. Instead, the fuse basics will be defined and an example of matching the fuse to the SCR will be shown. In addition to interrupting high current, the fuse should limit the current, thermal energy, and overvoltage due to the high current. Figure 5.16 illustrates the condition of the fuse at the moment the overcurrent starts. The peak letthrough current can be assumed triangular in shape for a firstorder approximation, lasting for the clearing time of the fuse. This time consists of the melting or prearcing time and the arcing time. The melting time is an inverse function of overcurrent and, at the time that the fuse element is opened, an arc will be formed causing the peak arc voltage. This arc voltage is both fuse and circuit dependent and under certain conditions can exceed the
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peak line voltage, a condition the user should ensure does not overstress the electronics. The available shortcircuit current is the maximum current the circuit is capable of delivering and is generally limited by the input transformer copper loss and reactance when the crowbar SCR is placed at the input to the regulator or the regulator current limiting when placed at the output. For a fuse to safely protect the circuit, it should limit the peak letthrough current and clear the fault in a short time, usually less than 10 ms.
Two other useful curves, the total clearing I2t characteristic and the peak letthrough current IPLT characteristic, are illustrated in Figures 5.17 and 5.18 respectively. Some vendors also show total clearing time curves (overlayed on Figure 5.17 as dotted lines) which then allows direct comparison with the SCR energy limits. When this clearing time information is not shown, then the designer should determine the IPLT and I2t from the respective curves and then solve for the clearing time from the approximate equation relating these two parameters. Assuming a triangular waveform for IPLT, the total clearing time, tc, would then approximately be
2 tc 3 I t I PLT2
CURRENT I rms (LOG)
SCR CHARACTERISTICS
FUSE CHARACTERISTIC Irms (max) LIMITED BY FUSE 10 ms TIME t (LOG) 4 HRS
Figure 5.15. TimeCurrent Characteristic Curves of a Crowbar SCR and a Fuse
FUSE VOLTAGE SUPPLY VOLTAGE INSTANT OF SHORT
PEAK ARC VOLTAGE
Once tc of the fuse is known, the comparison with the SCR can readily be made. As long as the I2t of the fuse is less than the I2t of the SCR, the SCR is protected. It should be pointed out that these calculations are predicated on a known value of available fault current. By inspection of Figure 5.18, it can be seen that IPLT can vary greatly with available fault current, which could have a marked effect on the degree of protection. Also, the illustrated curves are for particular operating conditions; the curves will vary somewhat with applied voltage and frequency, initial loading, load power factor, and ambient temperature. Therefore, the reader is referred to the manufacturers data sheet in those cases where extrapolation will be required for other operating conditions. The final proof is obtained by testing the fuse in the actual circuit under worstcase conditions. CROWBAR EXAMPLE
FUSE CURRENT PEAK FUSE CURRENT IPLT
MELTING TIME ARCING TIME CLEARING TIME PEAK ASYMMETRICAL FAULT CURRENT
Figure 5.16. Typical Fuse Timing Waveforms During Short Circuit
Fuse manufacturers publish several curves for characterizing their products. The currenttime plot, which describes current versus melting time (minimum time being 10 ms), is used in general industrial applications, but is not adequate for protecting semiconductors where the clearing time must be in the subcycle range. Where protection is required for normal multicycle overloads, this curve is useful.
To illustrate the proper matching of the crowbar SCR to the load and the fuse, consider the following example. A 50 A TTL load, powered by a 60 A current limited series regulator, has to be protected from transients on the supply bus by crowbarring the regulator output. The output filter capacitor of 10,000 F (200 F/A) contributes most of the energy to be crowbarred (the input capacitor is current limited by the regulator). The transients can reach 18 V for periods 100 ms. Referring to Figure 5.9, it is seen that this transient exceeds the empirically derived SOA. To ensure safe operation, the overvoltage transient must be crowbarred within 5 ms. Since the TTL SOA is based on a rectangular power pulse even though plotted in terms of voltage, the equivalent crowbarred energy pulse should also be derived. Thus, the exponentially decaying voltage waveform should be multiplied by the exponentially decaying current to result in an energy waveform proportional to e2x. The rectangular equivalent will have to be determined and then compared with the TTL SOA. However, for simplicity, by using the crowbarred exponential waveform, a conservative rating will result.
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102 LET-THROUGH I2t (A2S)
SF 13X SERIES 130 Vrms, 60 Hz TA = 25C POWER FACTOR
p 15%
15 A
20 A
4 10 A 10
4 5 ms 1 10 4 2 ms 1.5 ms TOTAL CLEARING TIME 4 105
102 4 103 4 104 AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS)
Figure 5.17. Maximum Clearing I2t Characteristics for 10 to 20 A Fuses
To protect the SCR, a fuse must be chosen that will open before the SCRs I2t is exceeded, the current being the regulator limiting current which will also be the available fault current to the fuse. The fuse could be eliminated by using a 60 A SCR, but the cost versus convenience tradeoff of not replacing the fuse is not warranted for this example. A second fuse or circuit breaker will protect the rectifiers and regulator for internal faults (shorts), but its selection, which is based on the respective energy limits of those components, is not part of this exercise.
INSTANTANEOUS PEAK LET-THROUGH CURRENT (AMPS
If a crowbar discharge time of 3 ms were chosen, it would not only be within the rectangular pulsed SOA, but also be well within the derived equivalent rectangular model of the exponential waveform. It would also require about 1.3 time constants for the overvoltage to decay from 18 V to 5 V; thus, the RC time constant would be 3 ms/1.3 or 2.3 ms. The limiting resistance, RS would simply be
RS 2.3 ms + 0.23 W ` 0.2 W + 10, 000 mF
103 MAX PEAK AVAILABLE CURRENT (2.35 x SYMMETRICAL rms AMPERES)
20 A
15 A 10 A 102
4 SF 13X SERIES 130 Vrms, 60 Hz POWER FACTOR 10 10 4 102 4 103 4 104 AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS)
p 15%
4 105
Figure 5.18. Peak LetThrough Current versus Fault Current for 10 to 20 A Fuses
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Since the capacitor quickly charges up to the overvoltages VCC1 of 18 V, the peak capacitor discharge current would be
I pk CC1 18 V + 90 A + VR + 0.2 W S
I2t rating is not specified, but can be calculated from the equation
I 2t ) (300 A)2 + (ITSM t+ (8.3 ms) + 375 A 2s 2 2 2
The rms current equivalent for this exponentially decaying pulse would be
I rms
+ 0.316 Ipk + 0.316(90) + 28.4 A rms
Now referring to the SCR peak current energy curves (Figure 5.14), it is seen that the MCR68 can sustain 210 A peak for a base time of 3 ms. This 12 A SCR must also sustain the 60 A regulator limited current for the time required to open the fuse. The MCR68 has a specified peak forward surge current rating of 100 A (1/2 cycle, sine wave, 60 Hz, nonrepetitive) and a circuit fusing rating of 40 A2s. The nonrepetitive rating implies that the device can sustain 100 occurrences of this 1/2 cycle surge over the life of the device; the SCR crowbar surge current curves were based on 2000 cycles. For the 3 ms time frame, the I12t1 for the exponential waveform is
I1 t1 2
Extrapolating to 6 ms results in about 318 A2s, an I2t rating much greater than the circuit 24 A2s value. The circuit designer can then make the cost/performance tradeoffs. All of these ratings are predicated on the fuse operating within 6 ms. With an available fault current of 60 A, Figure 5.17 shows that a 10 A (SF13X series) fuse will have a letthrough I2t of about 10 A2s and a total clearing time of about 6 ms, satisfying the SCR requirements, that is,
I 2t fuse tc
t I2t SCR p 6 ms
Figure 5.18 illustrates that for the same conditions, instantaneous peak letthrough current of about 70 A would result. For fuse manufacturers that dont show the clearing time information, the approximate time can be calculated from the triangular model, as follows
tc 3(10) + I3 I2t2 + (70) + 6.1 ms 2 PLT
(28.4 A)2(3 ms)
2.4 A 2s
Assuming that the fuse will open within 6 ms, the approximate energy that the SCR must sustain would be 60 A for an additional 3 ms. By superposition, this would amount to
2 I2 t2
The fuse is now matched to the SCR which is matched to the logic load. Other types of loads can be similarly matched, if the load energy characteristics are known. CHARACTERIZING SWITCHES AS LINETYPE MODULATORS In the past, hydrogen thyratrons have been used extensively as discharge switches for line type modulators. In general, such devices have been highly satisfactory from an electrical performance standpoint, but they have some major drawbacks including relatively large size and weight, low efficiency (due to filament power requirements), and short life expectancy compared with semiconductor devices, now can be eliminated through the use of silicon controlled rectifiers. A line type modulator is a modulator whose output pulse characteristics are determined by a lumped constant transmission line (pulse forming network) and by the proper match of the line impedance (PFN) to the load impedance. A switch for this type modulator should only initiate conduction and should have no effect on pulse characteristics. This is in contrast to a hard switch modulator where output pulse characteristics are determined by the hard relationship of grid (base) control of conduction through a vacuum tube (transistor) switch. Referring to the schematic (Figure 5.25), when the power supply is first turned on, no charge exists in the PFN, and energy is transferred from the power supply to the PFN via the resonant circuit comprising the charging choke and PFN capacitors. At the time that the voltage
+ (60 A)2(6 ms) + 21.6 A2s
which , when added to the exponential energy, would result in 24 A2. The MCR68 has a 40 A2s rating based on a 1/2 cycle of 8.3 ms. Due to the onedimensional heat flow in the device, the energy capability is not linearly related to time, but varies as to the t. Therefore, with a 6 ms 1/2cycle sine wave, the 40 A2t rating would now decrease to approximately (see Appendix VI for derivation).
I2 t2
t2 I1 t1 t1 2
+ 40 A2s + 34 A2s
1 2

6 ms 8.3 ms
1 2
Although the 1/2 cycle extrapolated rating is greater than the actual crowbar energy, it is only characterized for 100 cycles of operation. To ensure 2000 cycles of operation, at a somewhat higher cost, the 25 A MCR69 could be chosen. Its exponential peak current capability, at 3 ms, is about 560 A and has a specified ITSM of 300 A for 8.3 ms. The
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across the PFN capacitors reaches twice the power supply voltage, current through the charging choke tries to reverse and the power supply is disconnected due to the back biased impedance of the holdoff diode. If we assume this diode to be perfect, the energy remains stored in the PFN until the discharge switch is triggered to its on state. When this occurs, assuming that the pulse transformer has been designed to match the load impedance to the PFN impedance, all energy stored in the PFN reactance will be transferred to the load if we neglect switch losses. Upon completion of the transfer of energy the switch must return to its off condition before allowing transfer of energy once again from the power supply to the PFN storage element. OPTIMUM SWITCH CHARACTERISTICS
FORWARD BREAKOVER VOLTAGE
of 5 to 10 ohms or less. Operating the SCR at higher current to switch the same equivalent pulse power as a thyratron requires the SCR on impedance to be much lower so that the I2R loss is a reasonable value, in order to maintain circuit efficiency. Low switch loss, moreover, is mandatory because internal power dissipation can be directly translated into junctiontemperaturerise and associated leakage current increase which, if excessive, could result in thermal runaway.
TURNON TIME
Device manufacturers normally apply the variable amplitude output of a halfwave rectifier across the SCR. Thus, forward voltage is applied to the device for only a half cycle and the rated voltage is applied only as an ac peak. While this produces a satisfactory rating for ac applications, it does not hold for dc. An estimated 90% of devices tested for minimum breakover voltage (VBO) in a dc circuit will not meet the data sheet performance specifications. A switch designed for the pulse modulator application should therefore specify a minimum continuous forward breakover voltage at rated maximum leakage current for maximum device temperatures.
THE OFF SWITCH
In radar circuits the pulsepower handling capability of an SCR, rather than the normally specified average power capability, is of primary importance. For short pulses at high PRFs the major portion of semiconductor dissipation occurs during the initial turnon during the time that the anode rises from its forward leakage value to its maximum value. It is necessary, therefore, that turnon time be as short as possible to prevent excessive power dissipation. The function of radar is to provide distance information measured as a function of time. It is important, therefore, that any delay introduced by a component be fixed in relation to some variable parameter such as signal strength or temperature. For radar pulse modulator applications, a minimal delay variation versus temperature is required and any such variation must be repetitive from SCR to SCR, in production lots, so that adequate circuit compensation may be provided.
PULSE GATE CURRENT TO FIRE
The maximum forward leakage current of the SCR must be limited to a low value at maximum device temperature. During the period of device nonconduction it is desired that the switch offer an off impedance in the range of megohms to hundreds of megohms. This is required for two reasons: (1) to prevent diminishing the efficiency of recharge by an effective shunt path across the PFN, and (2) to prevent the bleeding off of PFN charge during the interpulse period. This second factor is especially important in the design of radar tansponders wherein the period between interrogations is variable. Change of the PFN voltage during the interpulse period could result in frequency shift, pulse instabilities, and loss of power from the transmitter being modulated.
THE ON SWITCH
The time of delay, the time of rise, and the delay variation versus temperature associated with SCR turnon are functions of the gate triggering current available and the trigger pulse duration. In order to predict pulse circuit operation of the SCR, the pulse gate current required to turn the device on when switching the lowimpedance modulator should be specified and the limits of turnon time variation for the specified pulse trigger current and collector load should be given at the high and low operating temperature extremes.
RECOVERY TIME
At present, SCR design is more limited in the achievable maximum forward sustaining voltage than in the current that the device will conduct. For this reason modulators utilizing SCRs can be operated at lower impedance levels than comparable thyratron circuits of yesterday. It is not uncommon for the characteristic impedance of the pulse forming network to be in the order
After the cessation of forward conducting current in the on device, a time of SCR circuit isolation must be provided to allow the semiconductor to return to its off state. Recovery time cannot be given as an independent parameter of device operation, but must include factors as determined by the external circuit, such as: (1) pulse current and rate of decay; (2) availability of an inverse voltage immediately following pulsecurrent conduction; (3) level of base bias following pulse current conduction; (4) rate of rise of reapplied positive voltage and its amplitude in relation to SCR breakover voltage; and (5) maximum circuit ambient temperature.
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In the reverse direction the controlled rectifier behaves like a conventional silicon diode. Under worst circuit conditions, if an inverse voltage is generated through the existence of a load short circuit, the current available will be limited only by the impedance of the pulse forming network and SCR inverse characteristics. The reverse current is able to sweep out some of the carriers from the SCR junctions. Intentional design of the load impedance to something less than the network impedance allows development of an inverse voltage across the SCR immediately after pulse conduction, enhancing switch turnoff time. Careful use of a fast clamp diode in series with a fast zener diode, the two in shunt across the SCR, allows application of a safe value of circuitinversevoltage without preventing the initial useful reverse current. Availability of a negative basebias following pulse current conduction provides a similar enhancement of switch turnoff time. If removal of carriers from the SCR junction enables a faster switch recovery time, then, conversely, operation of the SCR at high temperatures with large forward currents and with slow rate of current decay all increase device recovery time.
HOLDING CURRENT
Where Ebb = power supply voltage Vn(0) = 0 volts if the PFN employs a clamp diode or is matched to the load Tr = time of resonant recharge and is usually equal to Lc Cn
1 PRF
= value of charging inductance = value of total PFN capacity
For a given radar pulse modulator design, the values of power supply voltage, time of resonant recharge, charging choke inductance, and PFN capacitance are established. If the time (t) represents the recovery time of the SCR being used as the discharge switch, ic then represents the minimum value of holding current required by the SCR to prevent power supply lockon. Conversely, if the modulator design is about an existing SCR where holding current, recovery time, and forward breakover voltage are known, the charge parameters can be derived by rewriting the above formula as follows:
* Vn(0) iH + LcCn
V BO
One of the anomalies that exist in the design of a pulse SCR is the requirement for a high holding current. This need can be determined by examining the isolation component that disconnects the power supply from the discharge circuit during the time that PFN energy is being transferred to the transmitter and during the recovery time of the discharge switch. An inductance resonating with the PFN capacitance at twice the time of recharge is normally used for power supply isolation. Resonant charging restricts the initial flow of current from the power supply, thereby maximizing the time at which power supply current flow will exceed the holding current of the SCR. If the PFN recharge current from the power supply exceeds the holding current of the SCR before it has recovered, the SCR will again conduct without the application of a trigger pulse. As a result continuous conduction occurs from the power supply through the low impedance path of the charging choke and on switch. This lockon condition can completely disable the equipment employing the SCR switch. The charging current passed by the inductance is given as (the PFN inductance is considered negligible):
cos
T r 2(recovery time) 2 Lc Cn Tr
sin 2L c C n
The designer may find that for the chosen SCR the desired characteristics of modulator pulse width and pulse repetition frequency are not obtainable. One means of increasing the effective holding current of an SCR is for the semiconductor to exhibit some turnoff gain characteristic for the residual current flow at the end of the modulator pulse. The circuit designer then can provide turnoff base current, making the SCR more effective as a pulse circuit element.
THE SCR AS A UNIDIRECTIONAL SWITCH
* Vn(0) ic(t) + LcCn

E bb
cos
2L c C n Tr sin 2L c C n T r 2t
When triggered to its on state, the SCR, like the hydrogen thyratron, is capable of conducting current in one direction. A load short circuit could result in an inverse voltage across the SCR due to the reflection of voltage from the pulse forming network. The circuit designer may wish to provide an intentional loadtoPFN mismatch such that some inverse voltage is generated across the SCR to enhance its turnoff characteristics. Nevertheless, since the normal circuit application is unidirectional, the semiconductor device designer could take advantage of this fact in restricting the inversevoltage rating that the SCR must withstand. The circuit designer, in turn, can accommodate this lack of peak inversevoltage rating by use of a suitable diode clamp across the PFN or across the SCR.
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SCRs TESTS FOR PULSE CIRCUIT APPLICATION The suitability for pulse circuit applications of SCRs not specifically characterized for such purposes can be determined from measurements carried out with relatively simple test circuits under controlled conditions. Applicable test circuits and procedures are outlined in the following section.
FORWARD BLOCKING VOLTAGE AND LEAKAGE CURRENT
Mount the SCRs to a heat sink and connect the units to be tested as shown in Figure 5.21. Place the assembly in an oven and stabilize at maximum SCR rated temperature. Turn on the power supply and raise the voltage to rated VBO. Allow units to remain with the voltage applied for minimum of four hours. At the end of the temperature soak, determine if any units exhibit thermal runaway by checking for blown fuses (without removing the power). Reject any units which have blown circuit fuses. The forward leakage current, ILF, of the remaining units may be calculated after measuring the voltage VL, across resistor R2. Any units with a leakage current greater than manufacturers rating should be rejected.
To measure turnon time using a Tektronix 545 oscilloscope (or equivalent) with a dual trace type CA plugin, connect probes of Channels A and B to Test Points A and B. Place the Mode selector switch in the Added Algebraically position and the Channel B Polarity switch in the Inverted position. Adjust the HR212A pulse generator to give a positive pulse 1 s wide (100 pps) as viewed at Test Point A. Adjust the amplitude of the added voltage across the 100ohm base resistor for the specified pulse gate current (200 mA in this example). Switch the Mode selector knob to the alternate position. Connect Channel A to Test Point D. Leave the oscilloscope probe, Channel B, at Test Point B, thereby displaying the input trigger waveform. Measure the time between the 50 percent voltage amplitudes of the two waveforms. This is the TurnOn Time (tD + tR). To measure turnon time versus temperature, place the device to be tested on a suitable heat sink and place the assembly in a temperature chamber. Stabilize the chamber at minimum rated (cold) temperature. Repeat the above measurements. Raise the chamber temperature to maximum rated (hot) temperature and stabilize. Repeat the measurements above.
+ REGULATED POWER SUPPLY VL R2
1/16 A ADDITIONAL UNITS MAY BE CONNECTED IN PARALLEL
ANODE GATE CATHODE R1
Figure 5.20. Vertical Set to 4 cm, Horizontal 0.2 s/cm. Detected RF Magnetron Pulse
TURNON TIME, VARIATION AND ON IMPEDANCE This circuit assumes that the pulse gate current required to switch a given modulator load current is specified by the manufacturer or that the designer is able to specify the operating conditions. Typical operating values might be: Time of trigger pulse t = 1 s Pulse gate current IG = 200 mA Forward blocking voltage VBO = 400 V Load current ILoad = 30 A
Figure 5.21. Test Setup for SCR Forward Blocking Voltage and Leakage Current Measurements
RESISTOR R1 IS USED ONLY IF MANUFACTURER CALLS FOR BIAS RESISTOR BETWEEN GATE AND CATHODE. RESISTOR R2 CAN HAVE ANY SMALL VALUE WHICH, WHEN MULTIPLIED BY MAXIMUM ALLOWABLE LEAKAGE CURRENT, WILL PROVIDE A CONVENIENT READING OF VOLTAGE VL.
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To measure the turnon impedance for the specified current load, the on impedance can be measured as an SCR forward voltage drop. The point in time of measurement shall be half the output pulse width. For a 1 s output pulse, the measurement procedure would be: Connect the oscilloscope probe, Channel B, to Point D shown in Figure 5.22. Use the oscilloscope controls Time/CM and Multiplier to a setting of 0.5 s per centimeter or faster. With the Amplitude Control set to view 100 volts per centimeter (to prevent amplifier overloading) measure the amplitude of the voltage drop, VF, across the SCR 0.5 s after the PFN voltage waveform has dropped to half amplitude. It may be necessary to check ground reference several times during this test to provide the needed accuracy of measurement.
E = VBO VBO V BO 2 0V
To measure holding current, connect the SCRs under test as illustrated in Figure 5.23. Place SCRs in oven and stabilize at maximum expected operating temperature. View the waveform across R1 by connecting the oscilloscope probe (Tektronix 2465) Channel A to Point A, and Channel B to Point B. Place the Mode Selector switch in the Added Algebraically position. Place the Polarity swich of Channel B in the Inverted position. Adjust both Volts/CM switches to the same scale factor, making sure that each Variable knob is in its Calibrated position. Adjust pulse generator for a positive pulse, 1 s wide, and 1,000 pps pulse repetition frequency. Adjust power supply voltage to rated VBO. Adjust input pulse amplitude until unit fully triggers. Measure amplitude of voltage drop across R1, V(A B), and calculate holding current in mA from the equation
mA
1 2
Von
* B) ) VBO + V(AR1 100 k W

V BO V
t = AS SPECIFIED
IC = AS SPECIFIED
A B
100 k t = AS SPECIFIED D zO = R
R
Any unit which turns on but does not turn off has a holding current of less than
100 k
HP 212A
1:1 51
100
+ 2:1
V BO LOAD
WHERE ILOAD = AS SPECIFIED
Figure 5.22. Suggested Test Circuit for SCR On Measurements
HOLDING CURRENT
The SCR holding current can be measured with or without a gate turnoff current, according to the position of switch S2. The ON Semiconductor Trigger Pulse Generator is a transistor circuit capable of generating a 1.5 s turnon pulse followed by a variableduration turnoff pulse. Measurements should be made at the maximum expected temperature of operation. Resistor R1 should be chosen to allow an initial magnitude of current flow at the device pulse current rating.
The approximate voltage setting to view the amplitude of the holding current will be 10 or 20 volts per centimeter. The approximate sweep speed will be 2 to 5 s per centimeter. These settings will, of course, vary, depending upon the holding current of the unit under test. SCR recovery time is greatly dependent upon the circuit in which the device is used. However, any test of SCR recovery time should suffice to compare devices of various manufacturers, as long as the test procedure is standardized. Further evaluation of the selected devices could be made in an actual modulator circuit tester wherein techniques conducive to SCR turnoff are used. The circuit setup shown in Figures 5.24 and 5.25 can be employed for such tests. A slight load to PFN mismatch is called for to generate an inverse voltage across the SCR at the termination of the output pulse. An SCR gate turnoff pulse is used. The recharge component is a charging choke, providing optimized conditions of reapplied voltage to the PFN (and across the SCR). Adequate heat sinking of the SCR should be provided.
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HARRISON 800 A P.S. + 12 12
B R1
2W 100k
R3
TIME AT WHICH TO MEASURE IN
S1A
ON SEMI CONDUCTOR TRIGGER S2 PULSE GEN R2 R4 51
ANODE S1B
HP212 PULSE GEN.
GATE
CATHODE
C1 7500 fd.
REGULATED POWER SUPPLY IH VOLTAGE LEVEL FROM WHICH TO CALCULATE HOLDING CURRENT
NOTE: ADDITIONAL UNITS MAY BE TESTED BY SWITCHING THE ANODE AND GATE CONNECTIONS TO SIMILARLY MOUNTED SCRs. SHORT LEAD LENGTHS ARE DESIRABLE.
Figure 5.23. Test Setup for Measuring Holding Current
REGULATED POWER SUPPLY
CHARGING CHOKE
HARRISON 800 A + 12 12 A
B HOLD OFF DIODE PFN zO
q RLOAD
C
HP212A PULSE GEN
ON SEMI CONDUCTOR TRIGGER PULSE GEN
ANODE
GATE
CATHODE
RLOAD
Figure 5.24. Modulator Circuit for SCR Tests
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CHARGE IMPEDANCE
LOAD
POWER SUPPLY
ENERGY STORE
DISC SWITCH
BLOCK DIAGRAM; CHARGING CHOKE HOLD OFF DIODE PULSE TRANSFORMER
PFN Es
LOAD
TRIGGER IN
SCR
SIMPLIFIED SCHEMATIC
Figure 5.25. Radar Modulator, Resonant Line Type
PARALLEL CONNECTED SCRs When an application requires current capability in excess of a single economical SCR, it can be worthwhile to consider paralleling two or more devices. To help determine if two or more SCRs in parallel are more cost effective than one high current SCR, some of the advantages and disadvantages are listed for parallel devices.
Advantages
1. Less expensive to purchase 2. Less expensive to mount 3. Less expensive to replace, in case of failure 4. Ease of mounting 5. Ease of isolation from sink
Disadvantages
1. Increased SCR count 2. Selected or matched devices 3. Increased component count 4. Greater R & D effort There are several factors to keep in mind in paralleling and many are pertinent for single SCR operations as well. GATE DRIVE The required gate current (IGT) amplitude can vary greatly and can depend upon SCR type and load being switched. As a general rule for parallel SCRs, IGT should
be at least two or three times the IGT(MAX) specification on the data sheet and ideally close to, but never exceeding, the maximum specified gate power dissipation or peak current. Adequate gate current is necessary for rapid turnon of all the parallel SCRs and to ensure simultaneous turnon without excessive current crowding across any of the individual die. The rise time of the gate drive pulse should be fast, ideally 100 ns. Each gate should be driven from a good current source and through its own resistor, even if transformer drive is used. Gate pulse width requirements vary but should be of sufficient width to ensure simultaneous turnon and last well beyond the turnon delay of the slowest device, as well as beyond the time required for latching of all devices. Ideally, gate current would flow for the entire conduction period to ensure latching under all operating conditions. With low voltage switching, which includes conduction angles near 180 and near zero degrees, the gate drive requirements can be more critical and special emphasis may be required of gate pulse amplitude and width.
PARAMETER MATCHING For reliable current sharing with parallel SCRs, there are certain device parameters that should be matched or held within close tolerances. The degree of matching required varies and can be affected by type of load (resistive, inductive, incandescent lamp or phase controlled loads) being switched.
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The most common device parameters that can effect current sharing are: 1. 2. 3. td turnon delay time tr turnon rise time of anode current VA(MIN) minimum anode voltage at which device will turn on 4. Static onstate voltage and current 5. IL Latching current The four parameters shown in Table 5.6 were measured with a curve tracer and are: IL, latching current; VTM, onstate voltage; IGT and VGT, minimum gate current and voltage for turn on. Of the four parameters, IL and VTM can greatly affect current sharing. The latching current of each SCR is important at turnon to ensure each device turns on and will stay on for the entire conduction period. Onstate voltage determines how well the SCRs share current when cathode ballasting is not used. Table 5.5 gives turnon delay time (td) and turnon rise time (tr) of the anodecathode voltage and the minimum forward anode voltage for turnon. These parameters were measured in the circuits shown in Figures 5.28 and 5.29. One SCR at a time was used in the circuit shown in Figure 5.28. Turnon delay on twentyfive SCRs was measured (only ten are shown in Table 5.5) and they could be from one or more production lots. The variation in td was slight and ranged from 35 to 44 ns but could vary considerably on other production lots and this possible variation in td would have to be considered in a parallel application. Waveforms for minimum forward anode voltage for turnon are shown in Figure 5.26. The trailing edge of the gate current pulse is phase delayed (R3) so that the SCR is not turned on. The width of the gate current pulse is now increased (R5) until the SCR turns on and the forward anode voltage switches to the onstate at about 0.73 V. This is the minimum voltage at which this SCR will turn on with the circuit conditions shown in Figure 5.28. For dynamic turnon current sharing, td, tr and VA(MIN) are very important. As an example, with a high wattage incandescent lamp load, it is very important that the inrush current of the cold filament be equally shared by the parallel SCRs. The minimum anode voltage at which a device turns on is also very important. If one of the parallel devices turns on before the other devices and its onstate voltage is lower than the required minimum anode voltage for turnon of the unfired devices, they therefore cannot turn on. This would overload the device which
turned on, probably causing failure from overcurrent and excessive junction temperature.
Table 5.5. MCR12D TurnOn Delay, Rise Time and Minimum Forward Anode Voltage For TurnOn
Minimum Anode TurnOn Delay and Rise Time Voltage For OffState Voltage = 8 V Peak TurnOn OffState RL = 10 Ohms, IA 6.5 A Peak Voltage = 4 V Peak IG = 100 mA (PW = 100 s) Device RL = 0.5 Ohm IA = 5A Conduction Angle 90 Degrees IG = 100 mA
td(ns) 1 2 3 4 5 6 7 8 9 10 35 38 45 44 44 43 38 38 38 37
tr(s) 0.80 0.95 1 1 0.90 0.85 1.30 1.25 1 0.82
(Volts) 0.70 0.81 0.75 0.75 0.75 0.75 0.75 0.70 0.75 0.70
OFFSTATE ANODECATHODE VOLTAGE 0.2 V/Div ONSTATE IG = 50 1 mA/Div 0 100 s/Div 0
Figure 5.26. Minimum Anode Voltage For TurnOn OffState Voltage = 4 V Peak, RL = 0.5 Ohm, IA 5 A, IG = 75 mA
Turnoff time tq is important in higher frequency applications which require the SCR to recover from the forward conduction period and be able to block the next cycle of forward voltage. Thus, tq matching for high frequency operation can be as important as td, tr and VA(MIN) matching for equal turnon current sharing. Due to the variable in tq measurement, no further attempt will be made here to discuss this parameter and the reader is referred to Application Note AN914. The need for onstate matching of current and voltage is important, especially in unforced current sharing circuits.
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UNFORCED CURRENT SHARING When operating parallel SCRs without forced current sharing, such as without cathode ballasting using resistors or inductors, it is very important that the device parameters be closely matched. This includes td, tr, minimum forward anode voltage for turnon and onstate voltage matching. The degree of matching determines the success of the circuit. In circuits without ballasting, it is especially important that physical layout, mounting of devices and resistance paths be identical for good current sharing, even with onstate matched devices. Figure 5.27 shows how anode current can vary on devices closely matched for onstate voltage (1, 3 and 4) and a mismatched device (2). Without resistance ballasting, the matched devices share peak current within one ampere and device 2 is passing only nine amps, seven amps lower than device 1. Table 5.6 shows the degree of match or mismatch of VTM of the four SCRs. With unforced current sharing (RK = 0), there was a greater tendency for one device (1) to turnon, preventing the others from turning on when low anode switching voltage ( 10 V rms) was tried. Table 5.5 shows that the minimum anode voltage for turnon is from 7 to 14% lower for device 1 than on 2, 3 and 4. Also, device 1 turnon delay is 35 ns versus 38, 45 and 44 ns for devices 2, 3 and 4. The tendency for device 1 to turn on, preventing the other three from turning on, is most probably due to its lower minimum anode voltage requirement and shorter turn on delay. The remedy would be closer matching of the minimum anode voltage for turnon and driving the gates hard (but less than the gate power specifications) and increasing the width of the gate current pulse.
its share of current (Figure 5.29) with RK equal zero. As RK increases, device 2 takes a greater share of the total current and with RK around 0.25 ohm, the four SCRs are sharing peak current quite well. The value of RK depends on how close the onstate voltage is matched on the SCRs and the degree of current sharing desired, as well as the permissible power dissipation in RK.
17 IA(pk) , PEAK ANODE CURRENT (AMPS) #3 SCR #1
15
13
#4
11
#2
IG = 400 mA PW = 400 s OFFSTATE VOLTAGE = 26 V (rms) INDUCTIVE LOAD CONDUCTION ANGLE = 120 50 100 150 200 RK, CATHODE RESISTORS (MILLIOHMS) 250
Figure 5.27. Effects Of Cathode Resistor On Anode Current Sharing
Table 5.6. MCR12D Parameters Measured On Curve Tracer, TC = 25C

IL, Latching Current VD = 12 Vdc IG = 100 mA 13 mA 27 28 23 23 23 18 19 19 16 Minimum Gate VTM, OnState Current & Voltage for TurnOn Voltage VD = 12 Vdc, IA = 15 A RL = 140 PW = 300 s IGT VGT 1.25 V 1.41 1.26 1.26 1.28 1.26 1.25 1.25 1.25 1.25 5.6 mA 8.8 12 9.6 9.4 9.6 7.1 7 8.4 6.9 0.615 V 0.679 0.658 0.649 0.659 0.645 0.690 0.687 0.694 0.679
Device #
FORCED CURRENT SHARING Cathode ballast elements can be used to help ensure good static onstate current sharing. Either inductors or resistors can be used and each has advantages and disadvantages. This section discuses resistive ballasting, but it should be kept in mind that the inductor method is usually better suited for the higher current levels. Although they are more expensive and difficult to design, there is less power loss with inductor ballasting as well as other benefits. The degree of peak current sharing is shown in Figure 5.27 for four parallel MCR12D SCRs using cathode resistor ballasting with an inductive anode load. With devices 1, 3 and 4, onstate voltage is matched within 10 mV at an anode current of 15 A (See Table 5.6) and are within 1A of each other in Figure 5.27, with cathode resistance (RK) equal to zero. As RK increases, the current sharing becomes even closer. The unmatched device 2, with a VTM of 1.41 V (Table 5.6), is not carrying
1 2 3 4 5 6 7 8 9 10
LINE SYNCHRONIZED DRIVE CIRCUIT Gate drive for phase control of the four parallel SCRs is accomplished with one complementary MOS hex gate, MC14572, and two bipolar transistors (Figure 5.28). This adjustable linesynchronized driver permits SCR conduction from near zero to 180 degrees. A Schmitt trigger clocks a delay monostable multivibrator that is followed by a pulsewidth monostable multivibrator.
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Line synchronization is achieved through the half wave section of the secondary winding of the fullwave, centertapped transformer (A). This winding also supplies power to the circuit through rectifiers D1 and D2. The fullwave signal is clipped by diode D5, referenced to a + 15 volt supply, so that the input limit of the CMOS chip is not exceeded. The waveform is then shaped by the Schmitt trigger, which is composed of inverters U1 a and U1 b. A fast switching output signal B results. The positivegoing edge of this pulse is differentiated by the capacitiveresistive network of C1 and R2 and
D1 D2 100 , 250 1 W F D5 1N914 TRIAD F90X A D3 1N914 1 k FULL WAVE S1 D4 0 k HALF WAVE 22 k 2 U1 a 1 4 25 V
triggers the delay multivibrator that is composed of U1 c and U1 d. As a result, the normally high output is switched low. The trailing edge of this pulse (C) then triggers the following multivibrator, which is composed of NAND gate U1 e and inverter U1 f. The positive going output pulse (waveform D) of this multivibrator, whose width is set by potentiometer R6, turns on transistors Q1 and Q2, which drives the gates of the four SCRs. Transistor Q2 supplies about 400 mA drive current to each gate through 100 ohm resistors and has a rise time of 100 ns.
+ 15 V 1N5352 5 V, 5 W R1 220 k U1 b B 3
+ 15 V R3 1 m C1 0.01 F R2 100 k 0.01 F + 15 V
6 7
U1
t5
150 k
R4 9
120 V 60 Hz
SCHMITT TRIGGER
0.01 F
10 U1 d
5.30(a)
1N914 U1 e 13 D
R5 100 k 0.01 F 4.7 k R6 25 k 16 12 U 1f 8
0.7 ms 1 6 rms DELAY MULTIVIBRATOR
t t
15 A 15 V 0 15 V B 0 15 V C 0 15 V D 0 14
11
30 s 2 200 s PULSEWIDTH MULTIVIBRATOR
+ 40 V 10 k Q2 MJE253
0.001 10 k 1
TIP122 0.005
5.30(b)
10 k
1k
TO GATES RESISTORS
Figure 5.28. LineSynchronized Gate Driver
PARALLEL SCR CIRCUIT The four SCRs are MCR12Ds, housed in the TO220 package, rated at 12 A rms, 50 V and are shown schematically in Figure 5.29. Due to line power limitations, it was decided to use a voltage step down transformer and not try working directly from the 120 V line. Also, line isolation was desirable in an experiment of this type. The step down transformer ratings were 120 V rms primary, 26 V rms secondary, rated at 100 A, and was used with a variable transformer for anode voltage adjustment.
The inductive load consisted of four filter chokes in parallel (Stancor #C2688 with each rated at 10 mH, 12.5 Adc and 0.11 ohm). For good current sharing with parallel SCRs, symmetry in layout and mounting is of primary importance. The four SCRs were mounted on a natural finish aluminum heat sink and torqued to specification which is 8 inch pounds. Cathode leads and wiring were identical, and when used, the cathode resistors RK were matched within 1%. An RC snubber network (R7 and C2) was connected across the anodescathodes to slow down the rateofrise of the offstate voltage, preventing unwanted turnon.
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LOAD: FOUR STANCOR FILTER CHOKES (#C2688) IN PARALLEL EACH RATED AT: 10 mH @ 12.5 Adc AND 0.11 OHMS ALL ANODES COMMON TO HEAT SINK Q3 100 1k Q4 100 1k Q5 100 1k 0.25 C2 Q6 R7 100 SNUBBER
26 V rms 100 120 V rms 60 Hz 1k
RK
RK
RK
RK
Q3 Q6, MCR12D
Figure 5.29. Parallel Thyristors
CHARACTERIZING RFI SUPPRESSION IN THYRISTOR CIRCUITS In order to understand the measures for suppression of EMI, characteristics of the interference must be explored first. To have interference at all, we must have a transmitter, or creator of interference, and a receiver, a device affected by the interference. Neither the transmitter nor the receiver need be related in any way to those circuits commonly referred to as radiofrequency circuits. Common transmitters are opening and closing of a switch or relay contacts, electric motors with commutators, all forms of electric arcs, and electronic circuits with rapidly changing voltages and currents. Receivers are generally electronic circuits, both low and high impedance which are sensitive to pulse or high frequency energy. Often the very circuits creating the interference are sensitive to similar interference from other circuits nearby or on the same power line. EMI can generally be separated into two categories radiated and conducted. Radiated interference travels by way of electromagnetic waves just as desirable RF energy does. Conducted interference travels on power, communications, or control wires. Although this separation and nomenclature might seem to indicate two neat little packages, independently controllable, such is not the case. The two are very often interdependent such that in some cases control of one form may completely eliminate the other. In any case, both interference forms must be considered when interference elimination steps are taken. Phase control circuits using thyristors (SCRs, triacs, etc.) for controlling motor speed or resistive lighting and heating loads are particularly offensive in creating interference. They can completely obliterate most stations on any AM radio nearby and will play havoc with another control on the same power line. These controls are generally connected in one of the two ways shown in the block diagrams of Figure 5.30.
A common example of the connection of 5.30(a) is the wall mounted light dimmer controlling a ceiling mounted lamp. A motorized appliance with a builtin control such as a food mixer is an example of the connection shown in 5.30(b). Figure 5.30(a) may be redrawn as shown in Figure 5.31, illustrating the complete circuit for RF energy. The switch in the control box represents the thyristor, shown in its blocking state. In phase control operation, this switch is open at the beginning of each half cycle of the power line alternations. After a delay determined by the remainder of the control circuitry, the switch is closed and remains that way until the instantaneous current drops to zero. This switch is the source from which the RF energy flows down the power lines and through the various capacitors to ground.
CONTROL
LINE
LOAD
(a). Separately Mounted Control
CONTROL LINE LOAD
(b). Control and Load in the Same Enclosure Figure 5.30. Block Diagram of Control Connections
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If the load is passive, such as a lamp or a motor which does not generate interference, it may be considered as an impedance bypassed with the wiretowire capacitance of its leads. If it is another RF energy source, however, such as a motor with a commutator, it must be treated separately to reduce interference from that source. The power supply may be considered as dc since the interference pulse is extremely short (10 s) compared to the period of the power line frequency (16 ms for 60 Hz). The inductance associated with the power source comes from two separate phenomena. First is the leakage impedance of the supply transformer, and second is the selfinductance of the wires between the power line transformer and the load. One of the most difficult parameters to pin down in the system is the effect of grounding. Most industrial and commercial wiring and many homes use a grounded conduit system which provides excellent shielding of radiated energy emanating from the wiring. However, a large number of homes are being wired with two to three wire insulated cable without conduit. In threewire systems, one wire is grounded independently of the power system even though one of the power lines is already grounded. The capacitances to ground shown in Figure 5.31 will be greatly affected by the type of grounding used. Of course, in any home appliance, filtering must be provided suitable for all three different systems. Before the switch in the control is closed, the system is in a steadystate condition with the upper line of the power line at the system voltage and the bottom line and the load at ground potential. When the switch is closed, the upper line potential instantaneously falls due to the line and source inductance, then it rises back to its original value as the line inductance is charged. While the upper line is rising, the line from the control to the load also rises in potential. The effect of both of these lines increasing in potential together causes an electro static field change which radiates energy. In addition, any other loads connected across the power lines at point A, for example, would be affected by a temporary loss of voltage created by the closing of the switch and by the line and source inductance. This is a form of conducted interference. A second form of radiated interference is inductive coupling in which the power line and ground form a oneturn primary of an air core transformer. In this mode, an unbalanced transient current flows down the power lines with the difference current flowing to ground through the various capacitive paths available. The secondary is the radio antenna or the circuit being affected. This type of interference is a problem only when
the receiver is within about one wavelength of the transmitter at the offending frequency. Radiated interference from the control circuit proper is of little consequence due to several factors. The lead lengths in general are so short compared to the wavelengths in question that they make extremely poor antenna. In addition, most of these control circuits are mounted in metal enclosures which provide shielding for radiated energy generated within the control circuitry. A steel box will absorb radiated energy at 150 kHz such that any signal inside the box is reduced 12.9 dB per mil of thickness of the box. In other words, a 1/16 inch thick steel box will attenuate radiated interference by over 800 dB! A similar aluminum box will attenuate 1 dB per mil or 62.5 dB total. Thus, even in an aluminum box, the control circuitry will radiate very little energy. Both forms of radiated interference which are a problem are a result of conducted interference on the power lines which is in turn caused by a rapid rise in current. Thus, if this current rise is slowed, all forms of interference will be reduced. RFI SOLUTIONS Since the switch in Figure 5.31, when it closes, provides a very low impedance path, a capacitor in parallel with it will show little benefit in slowing down the rise of current. The capacitor will be charged to a voltage determined by the circuit constants and the phase angle of the line voltage just before the switch closes. When the switch closes, the capacitor will discharge quickly, its current limited only by its own resistance and the resistance of the switch. However, a series inductor will slow down the current rise in the load and thus reduce the voltage transient on all lines. A capacitor connected as shown in Figure 5.32 will also help slow down the current rise since the inductor will now limit the current out of the capacitor. Thus, the capacitor voltage will drop slowly and correspondingly the load voltage will increase slowly. Although this circuit will be effective in many cases, the filter is unbalanced, providing an RF current path through the capacitances to ground. It has, therefore, been found advantageous to divide the inductor into two parts and to put half in each line to the control. Figure 5.33 illustrates this circuit showing the polarity marks of two coils which are wound on the same core. A capacitor at point A will help reduce interference further. This circuit is particularly effective when used with the connection of Figure 5.30(b) where the load is not always on the grounded side of the power line. In this case, the two halves of the inductor would be located in the power line leads, between the controlled circuit and the power source.
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LOAD
CONTROL
Figure 5.31. RF Circuit for Figure 5.30(a)
0.1 F
100 H CONTROL 10 A TRIAC
8A LOAD
to line transients. The value of tr may be calculated by dividing the peak current anticipated by the allowable rate of current rise. Ferrite core inductors have proved to be the most practical physical configuration. Most ferrites are effective; those with highest permeability and saturation flux density are preferred. Those specifically designed as high frequency types are not necessarily desirable. Laminated iron cores may also be used; however, they require a capacitor at point A in Figure 5.33 to be at all effective. At these switching speeds, the iron requires considerable current in the windings before any flux change can take place. We have found currents rising to half their peak value in less than one s before the inductance begins to slow down the rise. The capacitor supplies this current for the short period without dropping in voltage, thus eliminating the pulse on the power line. Once a core material has been selected, wire size is the next decision in the design problems. Due to the small number of turns involved (generally a single layer) smaller sizes than normally used in transformers may be chosen safely. Generally, 500 to 800 circular mills per ampere is acceptable, depending on the enclosure of the filter and the maximum ambient temperature expected. An idea of the size of the core needed may be determined from the equation:
(1) A cA w E rms t r + 26 Awire B MAX
Figure 5.32. One Possible EMI Reduction Circuit
Where the control circuit is sensitive to fast rising line transients, a capacitor at point B will do much to eliminate this problem. The capacitor must charge through the impedance of the inductor, thus limiting the rate of voltage change (dv/dt) applied to the thyristor while it is in the blocking state. DESIGN CRITERIA Design equations for the split inductor have been developed based on parameters which should be known before attempting a design. The most difficult to determine is tr, the minimum allowable current rise time which will not cause objectionable interference. The value of this parameter must be determined empirically in each situation if complete interference reduction is needed. ON Semiconductor has conducted extensive tests using an AM radio as a receiver and a 600 Watt thyristor lamp dimmer as a transmitter. A rate of about 0.35 Amp per s seems to be effective in eliminating objectionable interference as well as materially reducing false triggering of the thyristor due
where: Ac = the effective crosssectional area of the core in in2 Aw = available core window area in in2 Awire = wire cross section in circular mils BMAX = core saturation flux density in gauss tr = allowable current rise time in seconds Erms = line voltage (A factor of 3 has been included in this equation to allow for winding space factor.) Once a tentative core selection has been made, the number of turns required may be found from the equation:
(2) N rms t r 10 + 11 EB MAXA c 6
where: N = the total number of turns on the core The next step is to check how well the required number of turns will fit onto the core. If the fit is satisfactory, the core design is complete; if not, some tradeoffs will have to be made.
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240 H 120 Vac 5A LOAD A 240 H B CONTROL 10 A TRIAC
As was previously mentioned, a current rise rate of about 0.35 ampere per s has been found to be acceptable for interference problems with acdc radios in most wiring situations. With 5 amperes rms, 7 amperes peak,
tr 7 + 20 ms + 0.35
Figure 5.33. Split Inductor Circuit
Then the equation (1):

A cA w
In most cases, the inductor as designed at this point will have far too much inductance. It will support the entire peak line voltage for the time selected as tr and will then saturate quickly, giving much too fast a current rise. The required inductance should be calculated from the allowable rise time and load resistance, making the rise time equal to two time constants. Thus:
(3) 2L R
+ 26
2580 120 20 3800 gauss
10
*6 + 0.044
Core part number 1F30 of the same company in a U1 configuration has an AcAw product of 0.0386, which should be close enough.
N
+ tr
or
+ R2tr
10
+ 10.93
Paper or other insulating material should be inserted between the core halves to obtain the required inductance by the equation:
(4) Ig
120 20 10 6 3800 0.137
10 6
+ 42 turns
+ 3.19 N
2 Ac L
*8
* Imc
where: Ig = total length of air gap in inches = effective ac permeability of the core material at the power line frequency Ic = effective magnetic path length of the core in inches Ac = effective cross sectional area of the core in square inches L = inductance in henries DESIGN EXAMPLE Consider a 600 watt, 120 Volt lamp dimmer using an ON Semiconductor 2N6348A triac. Line current is 600 =
120
Two coils of 21 turns each should be wound on either one or two legs and be connected as shown in Figure 5.33. The required inductance of the coil is found from equation (3).
rated + R2tr + E I rated L + 240 mH tr 2
+120 5
20 2
10 6
+ 240
6 10
To obtain this inductance, the air gap should be

2 +3.19 42 240 I g + 0.03035 Ig 0.137 10 8 3.33 1900 10 6
+ 0.03210.00175
5 amperes. #16 wire will provide about 516 circular mils per ampere. For core material, type 3C5 of Ferroxcube Corporation of America, Saugerties, New York, has a high Bmax and . The company specifies BMAX = 3800 gauss and = 1900 for material.
Thus, 15 mils of insulating material in each leg will provide the necessary inductance. If a problem still exists with false triggering of the thyristor due to conducted interference, a capacitor at point B in Figure 5.33 will probably remedy the situation.
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SECTION 6 APPLICATIONS
Edited and Updated
Because they are reliable solid state switches, thyristors have many applications, especially as controls. One of the most common uses for thyristors is to control ac loads such as electric motors. This can be done either by controlling the part of each ac cycle when the circuit conducts current (phase control) or by controlling the number of cycles per time period when current is conducted (cycle control). In addition, thyristors can serve as the basis of relaxation oscillators for timers and other applications. Most of the devices covered in this book have control applications. PHASE CONTROL WITH THYRISTORS The most common method of electronic ac power control is called phase control. Figure 6.1 illustrates this concept. During the first portion of each half-cycle of the ac sine wave, an electronic switch is opened to prevent the current flow. At some specific phase angle, , this switch is closed to allow the full line voltage to be applied to the load for the remainder of that half-cycle. Varying will control the portion of the total sine wave that is applied to the load (shaded area), and thereby regulate the power flow to the load. The simplest circuit for accomplishing phase control is shown in Figure 6.2. The electronic switch in this case is a triac (Q) which can be turned on by a small current pulse to its gate. The TRIAC turns off automatically when the current through it passes through zero. In the circuit shown, capacitor CT is charged during each half-cycle by the current flowing through resistor RT and the load. The fact that the load is in series with RT during this portion of the cycle is of little consequence since the resistance of RT is many times greater than that of the load. When the voltage across CT reaches the breakdown voltage of the DIAC bilateral trigger (D), the energy stored in capacitor CT is released. This energy produces a current pulse in the DIAC, which flows through the gate of the TRIAC and turns it on. Since both the DIAC and the TRIAC are bidirectional devices, the values of RT and CT will determine the phase angle at which the TRIAC will be triggered in both the positive and negative half-cycles of the ac sine wave.
PORTION OF WAVEFORM APPLIED TO LOAD
Figure 6.1. Phase Control of AC Waveform
LOAD RT AC LINE VOLTAGE D CT Q
Figure 6.2. Simplest Circuit for Phase Control
= 150 = 90
= 90 = 150 APPLIED SINE WAVE
Figure 6.3. Waveforms of Capacitor Voltage at Two Phase Angles
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The waveform of the voltage across the capacitor for two typical control conditions ( = 90 and 150) is shown in Figure 6.3. If a silicon controlled rectifier is used in this circuit in place of the TRIAC, only one half-cycle of the waveform will be controlled. The other half-cycle will be blocked, resulting in a pulsing dc output whose average value can be varied by adjusting RT.
VR
3/4 VR TYPICAL FAN LOAD VR = FULL RATED VOLTAGE
SPEED
1/2 VR CONSTANT TORQUE LOAD 1/4 VR
CONTROL OF INDUCTION MOTORS Shaded-pole motors driving low-starting-torque loads such as fans and blowers may readily be controlled using any of the previously described full-wave circuits. One needs only to substitute the winding of the shaded-pole motor for the load resistor shown in the circuit diagrams. Constant-torque loads or high-starting-torque loads are difficult, if not impossible, to control using the voltage controls described here. Figure 6.4 shows the effect of varying voltage on the speed-torque curve of a typical shaded-pole motor. A typical fan-load curve and a constant-torque-load curve have been superimposed upon this graph. It is not difficult to see that the torque developed by the motor is equal to the load torque at two different points on the constant-torque-load curve, giving two points of equilibrium and thus an ambiguity to the speed control. The equilibrium point at the lower speed is a condition of high motor current because of low counter EMF and would result in burnout of the motor winding if the motor were left in this condition for any length of time. By contrast, the fan speed-torque curve crosses each of the motor speedtorque curve crosses each of the motor speed-torque curves at only one point, therefore causing no ambiguities. In addition, the low-speed point is one of low voltage well within the motor windings current-carrying capabilities. Permanent-split-capacitor motors can also be controlled by any of these circuits, but more effective control is achieved if the motor is connected as shown in Figure 6.5. Here only the main winding is controlled and the capacitor winding is continuously connected to the entire ac line voltage. This connection maintains the phase shift between the windings, which is lost if the capacitor phase is also controlled. Figure 6.6(a) shows the effect of voltage on the speed-torque characteristics of this motor and a superimposed fan-load curve.
TORQUE
Figure 6.4. Characteristics of Shaded-Pole Motors at Several Voltages
MOT AC LINE VOLTAGE CONTROL CIRCUIT
Figure 6.5. Connection Diagram for Permanent-Split-Capacitor Motors
Not all induction motors of either the shaded-pole or the permanent-split-capacitor types can be controlled effectively using these techniques, even with the proper loads. Motors designed for the highest efficiencies and, therefore, low slip also have a very low starting torque and may, under certain conditions, have a speed-torque characteristic that could be crossed twice by a specific fan-load speed-torque characteristic. Figure 6.6(b) shows motor torque-speed characteristic curves upon which has been superimposed the curve of a fan with high starting torque. It is therefore desirable to use a motor whose squirrel-cage rotor is designed for medium-to-high impedance levels and, therefore, has a high starting torque. The slight loss in efficiency of such a motor at full rated speed and load is a small price to pay for the advantage of speed control prevents the TRIAC from turning on due to line transients and inductive switching transients.
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TYPICAL FAN LOAD VR SPEED VR 3/4 VR 1/2 VR 1/4 VR VR = FULL RATED VOLTAGE TORQUE TORQUE 3/4 VR 1/2 VR 1/4 VR
HIGH-STARTINGTORQUE FAN LOAD
SPEED
(a). High-Starting-Torque Motor
(b). High-Efficiency Motor
Figure 6.6. SpeedTorque Curves for a PermanentSplitCapacitor Motors at Various Applied Voltages
A unique circuit for use with capacitor-start motors in explosive or highly corrosive atmospheres, in which the arcing or the corrosion of switch contacts is severe and undesirable, is shown in Figure 6.7. Resistor R1 is connected in series with the main running winding and is of such a resistance that the voltage drop under normal full-load conditions is approximately 0.2 V peak. Since starting currents on these motors are quite high, this peak voltage drop will exceed 1 V during starting conditions, triggering the TRIAC, which will cause current to flow in the capacitor winding. When full speed is reached, the current through the main winding will decrease to about 0.2 V, which is insufficient to trigger the TRIAC thus the capacitor winding will no longer be energized. Resistor R2 and capacitor C2 form a dv/dt suppression network; this prevents the TRIAC from turning on due to line transients and inductive switching transients. CONTROL OF UNIVERSAL MOTORS Any of the half-wave or full-wave controls described previously can be used to control universal motors. Nonfeedback, manual controls, such as those shown in Figure 6.2, are simple and inexpensive, but they provide very little torque at low speeds. A comparison of typical speed-torque curves using a control of this type with those of feedback control is shown in Figure 6.8. These motors have some unique characteristics which allow their speed to be controlled very easily and efficiently with a feedback circuit such as that shown in Figure 6.9. This circuit provides phase-controlled halfwave power to the motor; that is, on the negative half-cycle, the SCR blocks current flow in the negative direction causing the motor to be driven by a pulsating direct current whose amplitude is dependent on the phase control of the SCR.
MOT AC LINE VOLTAGE
C1
C2 R2
R1
Figure 6.7. Circuit Diagram for Capacitor-Start Motor
VR = FULL RATED VOLTAGE VR VR SPEED SPEED 3/4 VR 1/2 VR 3/4 VR 1/2 VR 1/4 VR
TORQUE (A) NON-FEEDBACK CONTROL
TORQUE (B) FEEDBACK CONTROL
Figure 6.8. Comparison of Feedback Control with Non-Feedback Control
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The theory of operation of this control circuit is not at all difficult to understand. Assuming that the motor has been running, the voltage at point A in the circuit diagram must be larger than the forward drop of Diode D1, the gate-to-cathode drop of the SCR, and the EMF generated by the residual MMF in the motor, to get sufficient current flow to trigger the SCR. The waveform at point A (VA) for one positive half-cycle is shown in 6.9(b), along with the voltage levels of the SCR gate (VSCR), the diode drop (VD), and the motor-generated EMF (VM). The phase angle () at which the SCR would trigger is shown by the vertical dotted line. Should the motor for any reason speed up so that the generated motor voltage would increase, the trigger point would move upward and to the right along the curve so that the SCR would trigger later in the half-cycle and thus provide less power to the motor, causing it to slow down again. Similarly, if the motor speed decreased, the trigger point would move to the left and down the curve, causing the TRIAC to trigger earlier in the half-cycle providing more power to the motor, thereby speeding it up. Resistors R1, R2, and R3, along with diode D2 and capacitor C1 form the ramp-generator section of the circuit. Capacitor C1 is changed by the voltage divider R1, R2, and R3 during the positive half-cycle. Diode D2 prevents negative current flow during the negative half-cycle, therefore C1 discharges through only R2 and R3 during that half-cycle. Adjustment of R3 controls the amount by which C1 discharges during the negative half-cycle. Because the resistance of R1 is very much larger than the ac impedance of capacitor C1, the voltage waveform on C1 approaches that of a perfect cosine wave with a dc component. As potentiometer R2 is varied, both the dc and the ac voltages are divided, giving a family of curves as shown in 6.9(c).
R1
A C1 AC LINE VOLTAGE R2
D1 C2
R3 MOT D2
Figure 6.9. (a). Speed-Control Scheme for Universal Motors
The gain of the system, that is, the ratio of the change of effective SCR output voltage to the change in generator EMF, is considerably greater at low speed settings than it is at high speed settings. This high gain coupled with a motor with a very low residual EMF will cause a condition sometimes known as cycle skipping. In this mode of operation, the motor speed is controlled by skipping entire cycles or groups of cycles, then triggering one or two cycles early in the period to compensate for the loss in speed. Loading the motor would eliminate this condition; however, the undesirable sound and vibration of the motor necessitate that this condition be eliminated. This can be done in two ways. The first method is used if the motor design is fixed and cannot be changed. In this case, the impedance level of the voltage divider R1, R2 and R3 can be lowered so that C1 will charge more rapidly, thus increasing the slope of the ramp and lowering the system gain. The second method, which will provide an overall benefit in improved circuit performance, involves a redesign of the motor so that the residual EMF becomes greater. In general, this means using a lower grade of magnetic steel for the laminations. As a matter of fact, some people have found that ordinary cold-rolled steel used as rotor laminations makes a motor ideally suited for this type of electronic control. Another common problem encountered with this circuit is that of thermal runaway. With the speed control set at low or medium speed, at high ambient temperatures the speed may increase uncontrollably to its maximum value. This phenomenon is caused by an excessive impedance in the voltage-divider string for the SCR being triggered. If the voltage-divider current is too low, current will flow into the gate of the SCR without turning it on, causing the waveform at point A to be as shown in 6.9(d). The flat portion of the waveform in the early part of the half-cycle is caused by the SCR gate current loading the voltage divider before the SCR is triggered. After the SCR is triggered, diode D1 is back-biased and a load is no longer on the voltage divider so that it jumps up to its unloaded voltage. As the ambient temperature increases, the SCR becomes more sensitive, thereby requiring less gate current to trigger, and is triggered earlier in the half-cycle.This early triggering causes increased current in the SCR, thereby heating the junction still further and increasing still further the sensitivity of the SCR until maximum speed has been reached. The solutions to this problem are the use of the most sensitive SCR practical and a voltage divider network of sufficiently low impedance. As a rough rule of thumb, the average current through the voltage divider during the positive half-cycle should be approximately three times the current necessary to trigger the lowest-sensitivity (highest gate current) SCR being used.
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VA VA VD VSCR VM PHASE ANGLE
(b). Waveform for One Positive Half-Cycle of Circuit
be short-circuited without causing danger. Many designers have found it advantageous, therefore, to use 115 V motors with this system and provide a switch to apply full-wave voltage to the motor for high-speed operation. Figure 6.10 shows the proper connection for this switch. If one were to simply short-circuit the SCR for full-speed operation, a problem could arise. If the motor were operating at full speed with the switch closed, and the switch were then opened during the negative half-cycle, the current flowing in the inductive field of the motor could then break down the SCR in the negative direction and destroy the control. With the circuit as shown, the energy stored in the field of the motor is dissipated in the arc of the switch before the SCR is connected into the circuit.
VA (R2) R2 VM AC LINE VOLTAGE (R2)
PHASE ANGLE
(c). Voltage Waveform at Point A for Three Settings of Potentiometer R2
CONTROL CIRCUIT
TRIGGER POINT
MOT
Figure 6.10. Switching Scheme for Full-Wave Operation

UNLOADED WAVEFORM
CONTROL OF PERMANENT-MAGNET MOTORS

ACTUAL WAVEFORM
(d). Point A Voltage with Excessive Resistance R1
In addition to the type of steel used in the motor laminations, consideration should also be given to the design of motors used in this half-wave speed control. Since the maximum rms voltage available to the motor under half-wave conditions is 85 V, the motor should be designed for use at that voltage to obtain maximum speed. However, U.L. requirements state that semiconductor devices used in appliance control systems must be able to
As a result of recent developments in ceramic permanent-magnet materials that can be easily molded into complex shapes at low cost, the permanent-magnet motor has become increasingly attractive as an appliance component. Electronic control of this type of motor can be easily achieved using techniques similar to those just described for the universal motor. Figure 6.11 is a circuit diagram of a control system that we have developed and tested successfully to control permanent-magnet motors presently being used in blenders. Potentiometer R3 and diode D1 form a dc charging path for capacitor C1; variable resistor R1 and resistor R2 form an ac charging path which creates the ramp voltage on the capacitor. Resistor R4 and diode D2 serve to isolate the motor control circuit from the ramp generator during the positive and negative half-cycles, respectively.
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D1 AC LINE VOLTAGE R1 R3
R2
R4
D2
C1
MOT
Figure 6.11. Circuit Diagram for Controlling Permanent-Magnet Motors
A small amount of cycle skipping can be experienced at low speeds using this control, but not enough to necessitate further development work. Since the voltage generated during off time is very high, the thermal runaway problem does not appear at all. Typical speed-torque curves for motors of this type are shown in Figure 6.12.
VR VR = FULL RATED VOLTAGE
3/4 VR SPEED
1/2 VR
1/4 VR
TORQUE
Figure 6.12. Speed-Torque Characteristic of Permanent-Magnet Motors at Various Applied Voltages
MOTOR SPEED CONTROL WITH FEEDBACK While many motor speed control circuits have used SCRs, the TRIAC has not been very popular in this application. At first glance, it would appear that the TRIAC would be perfect for speed control because of its bilateral characteristics. There are a couple of reasons why this is not true. The major difficulty is the TRIACs dv/dt characteristic. Another reason is the difficulty of obtaining a feedback signal because of the TRIACs bilatera nature. While the TRIAC has its disadvantages, it does offer some advantages. In a SCR speed control either two SCRs
must be used, or the line voltage must be full-wave rectified using relatively high current rectifiers, or the control must be limited to half-wave. The TRIAC eliminates all these difficulties. By using a TRIAC the part count, package size, and cost can be reduced. Figure 6.13 shows a TRIAC motor speed control circuit that derives its feedback from the load current and does not require separate connections to the motor field and armature windings. Therefore, this circuit can be conveniently built into an appliance or used as a separate control. The circuit operates as follows: When the TRIAC conducts, the normal line voltage, less the drop across the TRIAC and resistor R5, is applied to the motor. By delaying the firing of the TRIAC until a later portion of the cycle, the rms voltage applied to the motor is reduced and its speed is reduced proportionally. The use of feedback maintains torque at reduced speeds. Diodes D1 through D4 form a bridge which applies full-wave rectified voltage to the phase-control circuit. Phase control of the TRIAC is obtained by the charging of capacitor C1 through resistors R2 and R3 from the voltage level established by zener diode D5. When C1 charges to the firing voltage of PUT Q1, the TRIAC triggers by transformer T1. C1 discharges through the emitter of Q1. While the TRIAC is conducting, the voltage drop between points A and B falls below the breakdown voltage of D5. Therefore, during the conduction period, the voltage on C1 is determined by the voltage drop from A to B and by resistors R1, R2, and R3. Since the voltage between A and B is a function of motor current due to resistor R5, C1 is charged during the conduction period to a value which is proportional to the motor current. The value of R5 is chosen so that C1 cannot charge to a high enough voltage to fire Q1 during the conduction period. However, the amount of charging required to fire Q1 has been decreased by an amount proportional to the motor current. Therefore, the firing angle at which Q1 will fire has been advanced in proportion to the motor current. As the motor is loaded and draws more current, the firing angle of Q1 is advanced even more, causing a proportionate increase in the rms voltage applied to the motor, and a consequent increase in its available torque. Since the firing voltage of Q1 depends on the voltage from base one to base two, it is necessary to support the base two voltage during the conduction portion of the cycle to prevent the feedback voltage from firing Q1. D6 and C2 perform this function. Because the motor is an inductive load, it is necessary to limit the commutation dv/dt for reliable circuit operation. R6 and C3 perform this function.
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R1 18 k 2W R2 27 k R3 50 k D5 ZENER 9.1 V D6 1N4001 R4 16 k Q2 MAC9D C2 10 F 10 V R7 27 k
D1 115 VAC 60 Hz D3 IN4006(4)
D2
Q1 2N6027
R6 100 C3 0.1 F
D4
C1 0.1 F
T1 DALE PT-50 ORIGIN B MOTOR Motor Rating (Amperes) 2 3 6.5 NOMINAL R5 VALUES R5 OHMS 1 0.67 0.32 Watts 5 10 15 R5
R5 SEE TABLE
+ I2 M
IM = Max. Rated Motor Current (RMS)
Figure 6.13. Motor Speed Control with Feedback
Nominal values for R5 can be obtained from the table or they can be calculated from the equation given. Exact values for R5 depend somewhat on the motor characteristics. Therefore, it is suggested that R5 be an adjustable wirewound resistor which can be calibrated in terms of motor current, and the speed control can be adapted to many different motors. If the value of R5 is too high, feedback will be excessive and surging or loss of control will result. If the value is too low, a loss of torque will result. The maximum motor current flows through R5, and its wattage must be determined accordingly. This circuit has been operated successfully with 2 and 3 ampere 1/4-inch drills and has satisfactorily controlled motor speeds down to 1/3 or less of maximum speed with good torque characteristics. to the motor, and a consequent increase in its available torque. AN INTEGRATED CIRCUIT FEEDBACK CONTROL The TDA1185A TRIAC phase angle controller (Figure 6.14) generates controlled triac triggering pulses and applies positive current feedback to stabilize the speed of universal motors. A ramp voltage synchronized to the ac
line half cycle and compared to an external set voltage determines the firing angle. Negative gate pulses drive the triac in quadrants two and three. Because the speed of a universal motor decreases as torque increases, the TDA1185A lengthens the triac conduction angle in proportion to the motor current, sensed through resistor R9. The TDA1185A is the best solution for low cost applications tolerating 5% motor speed variation. Open loop systems do not have a tachometer or negative feedback and consequently cannot provide perfect speed compensation.
CONSTANT SPEED MOTOR CONTROL USING TACHOMETER FEEDBACK
Tachometer feedback sensing rotor speed provides excellent performance with electric motors. The principal advantages to be gained from tachometer feedback are the ability to apply feedback control to shaded-pole motors, and better brush life in universal motors used in feedback circuits. This latter advantage results from the use of full-wave rather than half-wave control, reducing the peak currents for similar power levels.
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+ 100 F C8 8 120 k
14
100
R9 0.05
1.0 F R12
POSITIVE FEEDBACK FULL-WAVE + FULL-WAVE TRIGGER PULSE GENERATOR MONITORING
2 820 k CURRENT SYNCHRO M
12 SET +
MAC8D
C13 RCOMPENSATION SOFT START
13 +
10 R10
4 C4
VCC 1 SAWTOOTH GENERATOR
820 k VOLTAGE SYNCHRO
PROGRAMMING PIN MAIN LINE VOLTAGE COMPENSATION
2.0 W 18 k 1N4005
Figure 6.14. TDA 1185-A Universal Motor Speed Control Internal Block Diagram/Pin Assignment THE TACHOMETER
The heart of this system is, of course, the speed-sensing tachometer itself. Economy being one of the principal goals of the design, it was decided to use a simple magnetic tachometer incorporating the existing motor fan as an integral part of the magnetic circuit. The generator consists of a coil wound on a permanent magnet which is placed so that the moving fan blades provide a magnetic path of varying reluctance as they move past the poles of the magnet. Several possible configurations of the magnetic system are shown in Figure 6.15. Flux in a magnetic circuit can be found from the magnetic Ohms law:
position of the motor armature, the magnetic path will be of relatively low reluctance; then as the motor turns the reluctance will increase until one fan blade is precisely centered between the poles of the magnet. As rotation continues, the reluctance will then alternately increase and decrease as the fan blades pass the poles of the magnet. If a bar- or L-shaped magnet is used so that one pole is close to the shaft or the frame of the motor and the other is near the fan blades, the magnetic path reluctance will vary as each blade passes the magnet pole near the fan. In either case the varying reluctance causes variations in the circuit flux and a voltage is generated in the coil wound around the magnet. The voltage is given by the equation:
e x 10 8, + N d dt
+ MMF , R
where
= the flux, MMF = the magnetomotive force (strength of the magnet), and R = the reluctance of the magnetic path.
Assuming the MMF of the permanent magnet to be constant, it is readily apparent that variations in reluctance will directly affect the flux. The steel fan blades provide a low-reluctance path for the flux once it crosses the air gap between them and the poles of the magnet. If the magnet used has a horseshoe or U shape, and is placed so that adjacent fan blades are directly opposite each pole in one
e = the coil voltage in volts, N = the number of turns in the coil, and d = the rate of change of flux in lines per dt second. In a practical case, a typical small horseshoe magnet wound with 1000 turns of wire generated a voltage of about 0.5 volts/1000 rpm when mounted in a blender. Since both generated voltage and frequency are directly proportional to the motor speed, either parameter can be used as the feedback signal. However, circuits using voltage sensing are less complex and therefore less expensive. Only that system will be discussed here.
where
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COIL WIRES
MAGNET FAN MOTOR ARMATURE MOTOR FAN SIDE VIEW MOTOR ARMATURE
MOTOR FAN COIL WIRES MOTOR ARMATURE MAGNET TOP VIEW FERROUS MOTOR HOUSING POSSIBLE MAGNET SHAPES AND LOCATIONS
Figure 6.15. (a). Locations for Magnetic Sensing Tachometer Generator Using a Horseshoe Magnet
(b). Locations for Magnetic Sensing Tachometer Generator Using an L or Bar Magnet
THE ELECTRONICS
In one basic circuit, which is shown in Figure 6.16, the generator output is rectified by rectifier D1, then filtered and applied between the positive supply voltage and the base of the detector transistor Q1. This provides a negative voltage which reduces the base-voltage on Q1 when the speed increases. The emitter of the detector transistor is connected to a voltage divider which is adjusted to the desired tachometer output voltage. In normal operation, if the tachometer voltage is less than desired, the detector transistor, Q1, is turned on by current through R1 into its base. Q1 then turns on Q2 which causes the timing capacitor for programmable unijunction transistor Q3 to charge quickly. As the tachometer output approaches the voltage desired, the base-emitter voltage of Q1 is reduced to the point at which Q1 is almost cut off. Thereby, the collector current of Q2, which charges the PUT timing capacitor, reduces, causing it to charge slowly and trigger the thyristor later in the half cycle. In this manner, the average power to the motor is reduced until just enough power to maintain the desired motor speed is allowed to flow. Input circuit variations are used when the tachometer output voltage is too low to give a usable signal with a silicon rectifier. In the variation shown in Figure 6.16(b), the tachometer is connected between a voltage divider and the base of the amplifier transistor. The voltage divider is
set so that with no tachometer output the transistor is just barely in conduction. As the tachometer output increases, QT is cut off on negative half cycles and conducts on positive half cycles. Resistors R9 and R10 provide a fixed gain for this amplifier stage, providing the hFE of QT is much greater than the ratio of R9 to R10. Thus the output of the amplifier is a fixed multiple of the positive values of the tachometer waveform. The rectifier diode D1 prevents C1 from discharging through R9 on negative half cycles of the tachometer. The remainder of the filter and control circuitry is the same as the basic circuit. In the second variation, shown in 6.16(c), R8 has been replaced by a semiconductor diode, D2. Since the voltage and temperature characteristics more closely match those of the transistor base-to-emitter junction, this circuit is easier to design and needs no initial adjustments as does the circuit in 6.16(b). The remainder of this circuit is identical to that of Figure 6.15. In the second basic circuit, which is shown in Figure 6.17, the rectified and filtered tachometer voltage is added to the output voltage of the voltage divider formed by R1 and R2. If the sum of the two voltages is less than V1 VBE Q1 (where VBE Q1 is the base-emitter voltage of Q1), Q1 will conduct a current proportional to V1 VBE Q1, charging capacitor C. If the sum of the two voltages is greater than V1 VBE Q1, Q1 will be cut off and no current will flow into the capacitor. The operation of the remainder of the circuit is the same as the previously described circuits.
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C1
R1
+V 1 R2
(PURE dc) R3 R5 + V2 LOAD 120 V AC C2 (PULSING dc)
control circuit, the thyristor switches on for the remainder of the half cycle. By controlling the phase angle at which the thyristor is switched on, the relative power in the load may be controlled.
PHASE CONTROL WITH PROGRAMMABLE UNIJUNCTION TRANSISTORS
Q2 D1 TACHOMETER GENERATOR R4 INPUT CIRCUIT DETECTOR AND POWER CONTROL CIRCUIT Q1 R6
PUTs provide a simple, convenient means for obtaining the thyristor trigger pulse synchronized to the ac line at a controlled phase angle.
+ V1 (PURE dc) R1 TACH Q1 + V2 PULSATING dc LOAD 120 VAC
Figure 6.16. (a). Basic Tachometer Control Circuit
R7 TACH
R9
C1
R1
QT R8 R10
D1
R2
Figure 6.17. Another Basic Tachometer Circuit (b). Variation Used when the Tachometer Output is Too Low for Adequate Control
R9 R7 TACH QT D1 D2 R10
C1
R1
(c). Variation Providing Better Temperature Tracking and Easier Initial Adjustment
PHASE CONTROL WITH TRIGGER DEVICES Phase control using thyristors is one of the most common means of controlling the flow of power to electric motors, lamps, and heaters. With an ac voltage applied to the circuit, the gated thyristor (SCR, TRIAC, etc.) remains in its off-state for the first portion of each half cycle of the power line, then, at a time (phase angle) determined by the
These circuits are all based on the simple relaxation oscillator circuit of Figure 6.18. RT and CT in the figure form the timing network which determines the time between the application of voltage to the circuit (represented by the closing of S1) and the initiation of the pulse. In the case of the circuit shown, with Vs pure dc, the oscillator is free running, RT and CT determine the frequency of oscillation. The peak of the output pulse voltage is clipped by the forward conduction voltage of the gate to cathode diode in the thyristor. The principal waveforms associated with the circuit are shown in Figure 6.18(b). Operation of the circuit may best be described by referring to the capacitor voltage waveform. Following power application, CT charges at the rate determined by its own capacitance and the value of RT until its voltage reaches the peak point voltage of the PUT. Then the PUT switches into conduction, discharging CT through RGK and the gate of the thyristor. With Vs pure dc, the cycle then repeats immediately; however, in many cases Vs is derived from the anode voltage of the thyristor so that the timing cycle cannot start again until the thyristor is blocking forward voltage and once again provides Vs.
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RB1 G VS RB2 K
RT A CT RGK
LOAD
(a)
In this circuit, RD is selected to limit the current through D1 so that the diode dissipation capability is not exceeded. Dividing the allowable diode dissipation by one-half the zener voltage will give the allowable positive current in the diode since it is conducting in the voltage regulating mode only during positive half cycles. Once the positive halfcycle current is found, the resistor value may be calculated by subtracting 0.7 times the zener voltage from the rms line voltage and dividing the result by the positive current:
RD
* 0.7 Vz + Erms I positive
Von V CT CAPACITOR VOLTAGE
The power rating of RD must be calculated on the basis of full wave conduction as D1 is conducting on the negative half cycle acting as a shunt rectifier as well as providing Vs on the positive half cycle.
Voff RD RT V V RB1 OUTPUT VOLTAGE D1 VS CT R3 LINE R1
VCG IBBRB1 0
R2
(a)
VS RECTIFIED SINE WAVE
(b) Figure 6.18. Basic Relaxation Oscillator Circuit (a) and Waveforms (b)
It is often necessary to synchronize the timing of the output pulses to the power line voltage zero-crossing points. One simple method of accomplishing synchronization is shown in Figure 6.19. Zener diode D1 clips the rectified supply voltage resulting in a Vs as shown in 6.19(b). Since VS, and therefore the peak point voltage of the PUT drops to zero each time the line voltage crosses zero, CT discharges at the end of every half cycle and begins each half cycle in the discharged state. Thus, even if the PUT has not triggered during one half cycle, the capacitor begins the next half cycle discharged. Consequently, the values of RT and CT directly control the phase angle at which the pulse occurs on each half cycle. The zener diode also provides voltage stabilization for the timing circuit giving the same pulse phase angle regardless of normal line voltage fluctuations.
APPLICATIONS
(b) Figure 6.19. Control Circuit (a) with Zener Clipped, Rectified Voltage (b)
LOAD 600 W RD 6.8 k 2W RT D1 1N5250 A R1 100 k 2N6027 R2 R3 100 k 5.1 k MCR8D 10 k
AC LINE
CT 0.1 F
The most elementary application of the PUT trigger circuit, shown in Figure 6.20, is a half-wave control circuit.
Figure 6.20. Half Wave Control Circuit with Typical Values for a 600 Watt Resistive Load
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The thyristor is acting both as a power control device and a rectifier, providing variable power to the load during the positive half cycle and no power to the load during the negative half cycle. The circuit is designed to be a two terminal control which can be inserted in place of a switch. If full wave power is desired as the upper extreme of this control, a switch can be added which will short circuit the SCR when RT is turned to its maximum power position. The switch may be placed in parallel with the SCR if the load is resistive; however, if the load is inductive, the load must be transferred from the SCR to the direct line as shown in Figure 6.21.
CONTROL CIRCUIT
Full wave control may be realized by the addition of a bridge rectifier, a pulse transformer, and by changing the thyristor from an SCR to a TRIAC, shown in Figure 6.22. Occasionally a circuit is required which will provide constant output voltage regardless of line voltage changes. Adding potentiometer P1, as shown in Figure 6.23, to the circuits of Figures 6.20 and 6.22, will provide an approximate solution to this problem. The potentiometer is adjusted to provide reasonably constant output over the desired range of line voltage. As the line voltage increases, so does the voltage on the wiper of P1 increasing VS and thus the peak point voltage of the PUT. The increased peak point voltage results in CT charging to a higher voltage and thus taking more time to trigger. The additional delay reduces the thyristor conduction angle and maintains the average voltage at a reasonably constant value.
FEEDBACK CIRCUITS
(a). Resistive Load
CONTROL CIRCUIT
The circuits described so far have been manual control circuits; i.e., the power output is controlled by a potentiometer turned by hand. Simple feedback circuits may be constructed by replacing RT with heat or light-dependent sensing resistors; however, these circuits have no means of adjusting the operating levels. The addition of a transistor to the circuits of Figures 6.20 and 6.22 allows complete control.
RD P1 500 RT D1 1N5250A CT 0.1 F RG1 100 k 2N6027 RG2 100 5.1 k
(b). Inductive Load Figure 6.21. Half Wave Controls with Switching for Full Wave Operation
6.8 k RECTIFIED LINE (FULL OR HALF WAVE)
10 k
RGK TO THYRISTOR GATE-CATHODE
LOAD 900 W RD 6.8 k 2W 1N5250 A RT R1 100 k 2N6027 R2 CT 0.1 F DALE PT50 (OR EQUIVALENT) R3 100 k 5.1 k 10 k D1 MAC12D
Figure 6.23. Circuit for Line Voltage Compensation

6.8 k RD RECTIFIED LINE (FULL OR HALF WAVE) Rs* 1N5250A D1 Rc 100 k Q1 RT(MIN) 10 k MPS6512 2N6027 10 k 100 TO THYRISTOR GATE-CATHODE 5.1 k
LINE
MDA920A4
CT 0.1 F
*Rs SHOULD BE SELECTED TO BE ABOUT 3 k TO 5 k OHMS AT THE DESIRED OUTPUT LEVEL
Figure 6.22. A Simple Full Wave Trigger Circuit with Typical Values for a 900 Watt Resistive Load
Figure 6.24. Feedback Control Circuit
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Figure 6.24 shows a feedback control using a sensing resistor for feedback. The sensing resistor may respond to any one of many stimuli such as heat, light, moisture, pressure, or magnetic field. Rs is the sensing resistor and Rc is the control resistor that establishes the desired operating point. Transistor Q1 is connected as an emitter follower such that an increase in the resistance of Rs decreases the voltage on the base of Q1, causing more current to flow. Current through Q1 charges CT, triggering the PUT at a delayed phase angle. As Rs becomes larger, more charging current flows, causing the capacitor voltage to increase more rapidly. This triggers the PUT with less phase delay, boosting power to the load. When Rs decreases, less power is applied to the load. Thus, this circuit is for a sensing resistor which decreases in response to too much power in the load. If the sensing resistor increases with load power, then Rs and Rc should be interchanged. If the quantity to be sensed can be fed back to the circuit in the form of an isolated, varying dc voltage such as the output of a tachometer, it may be inserted between the voltage divider and the base of Q1 with the proper polarity. In this case, the voltage divider would be a potentiometer to adjust the operating point. Such a circuit is shown in Figure 6.25.
6.8 k RECTIFIED LINE 1N5250A 10 k Rc 100 k es RT(MIN) 2N6027 MPS6512 R1 0.1 F CT 10 k 100 5.1 k TO THYRISTOR GATECATHODE
gain. To solve this problem a dc amplifier could be inserted between the voltage divider and the control transistor gate to provide as close a control as desired. Other modifications to add multiple inputs, switched gains, ramp and pedestal control, etc., are all simple additions to add sophistication.
MCR218-4 RD AC LINE 6.8 k RC 1k T DALE PT50 (OR EQUIVALENT) Q1 MPS6512
2k
R1 100 k DC LOAD 600 W R2 30 k
3.9 k
1N5250A
2N6028 CT 0.1 F
C1 10 F
Figure 6.26. Half Wave, Average Voltage Feedback
RG 10
10 MCR218-4 (2)
T RG
MPS6512 2k 6.8 k RD 2 W 2N6028 D1 1N5250A Q1
R1 100 k
R2 30 k DC 10 LOAD F
3.9 k
1N4003 (2) 1N4721 (2) AC LINE
CT 0.1 F
C1
DALE PT50 (OR EQUIVALENT)
Figure 6.25. Voltage Feedback Circuit
In some cases, average load voltage is the desired feedback variable. In a half wave circuit this type of feedback usually requires the addition of a pulse transformer, shown in Figure 6.26. The RC network, R1, R2, C1, averages load voltage so that it may be compared with the set point on Rs by Q1. Full wave operation of this type of circuit requires dc in the load as well as the control circuit. Figure 6.27 is one method of obtaining this full wave control. Each SCR conducts on alternate half-cycles and supplies pulsating dc to the load. The resistors (Rg) insure sharing of the gate current between the simultaneously driven SCRs. Each SCR is gated while blocking the line voltage every other half cycle. This momentarily increases reverse blocking leakage and power dissipation. However, the leakage power loss is negligible due to the low line voltage and duty cycle of the gate pulse. There are, of course, many more sophisticated circuits which can be derived from the basic circuits discussed here. If, for example, very close temperature control is desired, the circuit of Figure 6.24 might not have sufficient
Figure 6.27. Full Wave, Average Voltage Feedback Control
CLOSED LOOP UNIVERSAL MOTOR SPEED CONTROL Figure 6.28 illustrates a typical tachometer stabilized closed feedback loop control using the TDA1285A integrated circuit. This circuit operates off the ac line and generates a phase angle varied trigger pulse to control the triac. It uses inductive or hall effect speed sensors, controls motor starting acceleration and current, and provides a 1 to 2% speed variation for temperature and load variations. CYCLE CONTROL WITH OPTICALLY ISOLATED TRIAC DRIVERS In addition to the phase control circuits, TRIAC drivers can also be used for ac power control by on-off or burst control, of a number of ac cycles. This form of power control allows logic circuits and microprocessors to easily control ac power with TRIAC drivers of both the zerocrossing and non zero-crossing varieties.
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VCC C14 47 nF 10 330 nF 16 220 k 1.5 F 1.0 M R4 220 nF 10 NF C4 100 nF C5 4 5 14 9
47 F + 10 k R1
1N4005 820 k 2 820 k 1 M Inductive TACHO
220 V
TDA1285A 8 C11 C7 1.0 F 220 nF 11 7 13 6 12 3 22 k 0.1 F 2.2 k R3 0.1 F
Figure 6.28. (a). Motor Control Circuit

NOTES: Frequency to Voltage converter Max. motor speed 30,000 rpm TDA1285A 6 12 HALLEFFECT SENSOR
30, 000 x 4 Tachogenerator 4 pairs of poles: max. frequency = 60
+ 2 kHz
47 k
C11 = 680 pF. R4 adjusted to obtain VPin 4 = 12 V at max. speed: 68 k Power Supply with Vmains = 120 Vac, R1 = 4.7 k. Perfect operation will occur down to 80 Vac.
(b). Circuit Modifications to Connect a Hall-Effect Sensor
USING NON-ZERO CROSSING OPTICALLY ISOLATED TRIAC DRIVERS

USING THE MOC3011 ON 240 VAC LINES
The rated voltage of a MOC3011 is not sufficiently high for it to be used directly on 240 V line; however, the designer may stack two of them in series. When used this way, two resistors are required to equalize the voltage dropped across them as shown in Figure 6.29.
REMOTE CONTROL OF AC VOLTAGE
Local building codes frequently require all 115 V light

+5V 150
switch wiring to be enclosed in conduit. By using a MOC3011, a TRIAC, and a low voltage source, it is possible to control a large lighting load from a long distance through low voltage signal wiring which is completely isolated from the ac line. Such wiring usually is not required to be put in conduit, so the cost savings in installing a lighting system in commercial or residential buildings can be considerable. An example is shown in Figure 6.29. Naturally, the load could also be a motor, fan, pool pump, etc.
180 LOAD
MOC3011
1M
240 Vac MOC3011 l 1M
1k
Figure 6.29. Two MOC3011 TRIAC Drivers in Series to Drive 240 V TRIAC
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NON-CONDUIT #22 WIRE
180
115 V 360 MOC3011 2N6342A
5V
Figure 6.30. Remote Control of AC Loads Through Low Voltage Non-Conduit Cable
SOLID STATE RELAY
Figure 6.30 shows a complete general purpose, solid state relay snubbed for inductive loads with input protection. When the designer has more control of the input and output conditions, he can eliminate those components which are not needed for his particular application to make the circuit more cost effective.
INTERFACING MICROPROCESSORS TO 115 VAC PERIPHERALS
the second input of a 2 input gate is tied to a simple timing circuit, it will also provide energization of the TRIAC only at the zero crossing of the ac line voltage as shown in Figure 6.32. This technique extends the life of incandescent lamps, reduces the surge current strains on the TRIAC, and reduces EMI generated by load switching. Of course, zero crossing can be generated within the microcomputer itself, but this requires considerable software overhead and usually just as much hardware to generate the zero-crossing timing signals. APPLICATIONS USING THE ZERO CROSSING TRIAC DRIVER For applications where EMI induced, non-zero crossingload switching is a problem, the zero crossing TRIAC driver is the answer. This TRIAC driver can greatly simplify the suppression of EMI for only a nominal increased cost. Examples of several applications using the MOC3031, 41 follows.
180 2.4 k
The output of a typical microcomputer input-output (I/O) port is a TTL-compatible terminal capable of driving one or two TTL loads. This is not quite enough to drive the MOC3011, nor can it be connected directly to an SCR or TRIAC, because computer common is not normally referenced to one side of the ac supply. Standard 7400 series gates can provide an input compatible with the output of an MC6821, MC6846 or similar peripheral interface adaptor and can directly drive the MOC3011. If
150
2W 1N4002 2N3904 47
MOC3011
0.1 F 2N6071B 115 V
10 k
Figure 6.31. Solid-State Relay
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+5 V +5 V ADDRESS MC6800 OR MC6802 MPU DATA MC6820 OR MC6821 OR MC6846 I/O 7400 300 MOC3011 180
200 W
2N6071 300 MOC3011 180 2.4 k 0.1 F 2N6071B 1k 5V OPTO TRIAC DRIVERS MOTOR
115 V (RESISTIVE LOAD)
115 V (INDUCTIVE LOAD)
115 V
6.3 V 3k 100 k 2N3904
OPTIONAL ZERO-CROSSING CIRCUITRY
Figure 6.32. Interfacing an M6800 Microcomputer System to 115 Vac Loads MATRIX SWITCHING
Matrix, or point-to-point switching, represents a method of controlling many loads using a minimum number of components. On the 115 V line, the MOC3031 is ideal for this application; refer to Figure 6.33. The large static dv/dt rating of the MOC3031 prevents unwanted loads from being triggered on. This might occur, in the case of non-zero crossing TRIAC drivers, when a TRIAC driver on a vertical line was subjected to a large voltage ramp due
to a TRIAC on a horizontal line being switched on. Since non-zero crossing TRIAC drivers have lower static dv/dt ratings, this ramp would be sufficiently large to trigger the device on. R is determined as before:
R (min)
+ Iin(pk) TSM 170 V + 150 ohms + 1.2 A

V
150
LOAD
LOAD
LOAD MOC 3031
150 LOAD LOAD LOAD MOC 3031
150 LOAD LOAD LOAD MOC 3031 MOC 3031 150 MOC 3031 150 MOC 3031 150 115 V
CONTROL BUS
Figure 6.33. Matrix Switching http://onsemi.com

115
300 CONTROL MOC 3041
LOAD
LOAD
LOAD
Figure 6.34. Power Relay Control
POWER RELAYS
The use of high-power relays to control the application of ac power to various loads is a very widespread practice. Their low contact resistance causes very little power loss and many options in power control are possible due to their multipole-multithrow capability. The MOC3041 is well suited to the use of power relays on the 230 Vac line; refer to Figure 6.34. The large static dv/dt of this device makes a snubber network unnecessary, thus reducing component count and the amount of printed circuit board space required. A non-zero crossing TRAIC driver (MOC3021) could be used in this application, but its lower static dv/dt rating would necessitate a snubber network.
the I/O port and in turn, drive the MOC3031 and/or MOC3041; refer to Figure 6.35. The zero-crossing feature of these devices extends the life of incandescent lamps, reduces inrush currents and minimizes EMI generated by load switching.
AC MOTORS
The large static dv/dt rating of the zero-crossing TRIAC drivers make them ideal when controlling ac motors. Figure 6.36 shows a circuit for reversing a two phase motor using the MOC3041. The higher voltage MOC3041 is required, even on the 115 Vac line, due to the mutual and self-inductance of each of the motor windings, which may cause a voltage much higher than 115 Vac to appear across the winding which is not conducting current.
DETERMINING LIMITING RESISTOR R FOR A HIGH-WATTAGE INCANDESCENT LAMP
MICROCOMPUTER INTERFACE
The output of most microcomputer input/output (I/O) ports is a TTL signal capable of driving several TTL gates. This is insufficient to drive a zero-crossing TRIAC driver. In addition, it cannot be used to drive an SCR or TRIAC directly, because computer common is not usually referenced to one side of the ac supply. However, standard 7400 NAND gates can be used as buffers to accept the output of
+5 V +5 V 7400 ADDRESS MC68000 MPU DATA MC6820 OR MC6821 OR MC6846 I/O
Many high-wattage incandescent lamps suffer shortened lifetimes when switched on at ac line voltages other than zero. This is due to a large inrush current destroying the filament. A simple solution to this problem is the use of the MOC3041 as shown in Figure 6.37. The MOC3041 may be controlled from a switch or some form of digital logic.
200 W 300 MOC 3031 300 MOC 3041 150 2N6071 MOTOR 230 V (INDUCTIVE LOAD) 115 V (RESISTIVE LOAD)
300
LOAD
POWER RELAY (230 VAC COIL)
230 VAC
2N6073
1 k +5 V
Figure 6.35. M68000 Microcomputer Interface
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MOTOR OPTIONAL CURRENT LIMITING RESISTOR 115 V R 300 MOC 3041 C 300 MOC 3041
Figure 6.36. Reversing Motor Circuit
The minimum value of R is determined by the maximum surge current rating of the MOC3041 (ITSM):
R (min)
+ +
V in(pk) I TSM V in(pk) 1.2 A (10)
e. Zero Voltage Switching Output (Will Only Turn On Close to Zero Volts) f. AC Output (50 or 60 Hz) Figure 6.38 shows the general format and waveforms of the SSR. The input on/off signal is conditioned (perhaps only by a resistor) and fed to the Light-Emitting-Diode (LED) of an optoelectronic-coupler. This is ANDed with a go signal that is generated close to the zero-crossing of the line, typically 10 Volts. Thus, the output is not gated on via the amplifier except at the zero-crossing of the line voltage. The SSR output is then re-gated on at the beginning of every half-cycle until the input on signal is removed. When this happens, the thyristor output stays on until the load current reaches zero, and then turns off.
On a 230 Vac Line:

R (min)
V + 283 ohms + 340 1.2 A
(11)
In reality, this would be a 300 ohm resistor. AC POWER CONTROL WITH SOLID-STATE RELAYS The Solid-State Relay (SSR) as described below, is a relay function with: a. Four Terminals (Two Input, Two Output) b. DC or AC Input c. Optical Isolation Between Input and Output d. Thyristor (SCR or TRIAC) Output
ADVANTAGES AND DISADVANTAGES OF SSRs The SSR has several advantages that make it an attractive choice over its progenitor, the Electromechanical Relay (EMR) although the SSR generally costs more than its electromechanical counterpart. These advantages are:
LAMP R SWITCH OR DIGITAL LOGIC MOC 3041 300 230 V
Figure 6.37. High-Wattage Lamp Control
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ZERO CROSS DETECTOR GO/NO GO INPUT ON/OFF LED AND AMPL
LOAD
POWER SWITCH
LINE LINE 0 GO NO GO ON OFF OUTPUT
Figure 6.38. SSR Block Diagram
1. No Moving Parts the SSR is all solid-state. There are no bearing surfaces to wear, springs to fatigue, assemblies to pick up dust and rust. This leads to several other advantages. 2. No Contact Bounce this in turn means no contact wear, arcing, or Electromagnetic Interference (EMI) associated with contact bounce. 3. Fast Operation usually less than 10 s. Fast turn-on time allows the SSR to be easily synchronized with line zero-crossing. This also minimizes EMI and can greatly increase the lifetime of tungsten lamps, of considerable value in applications such as traffic signals. 4. Shock and Vibration Resistance the solid-state contact cannot be shaken open as easily as the EMR contact. 5. Absence of Audible Noise this devolves from the lack of moving mechanical parts. 6. Output Contact Latching the thyristor is a latching device, and turns off only at the load current zerocrossing, minimizing EMI. 7. High Sensitivity the SSR can readily be designed to interface directly with TTL and CMOS logic, simplifying circuit design. 8. Very Low Coupling Capacitance Between Input and Output. This is a characteristic inherent in the optoelectronic-coupler used in the SSR, and can be useful in areas such as medical electronics where the reduction of stray leakage paths is important.
This list of advantages is impressive, but of course, the designer has to consider the following disadvantages: 1. Voltage Transient Resistance the ac line is not the clean sine wave obtainable from a signal generator. Superimposed on the line are voltage spikes from motors, solenoids, EMRs (ironical), lightning, etc. The solid-state components in the SSR have a finite voltage rating and must be protected from such spikes, either with RC networks (snubbing), zener diodes, MOVs or selenium voltage clippers. If not done, the thyristors will turn on for part of a half cycle, and at worst, they will be permanently damaged, and fail to block voltage. For critical applications a safety margin on voltage of 2 to 1 or better should be sought. The voltage transient has at least two facets the first is the sheer amplitude, already discussed. The second is its frequency, or rate-of-rise of voltage (dv/dt). All thyristors are sensitive to dv/dt to some extent, and the transient must be snubbed, or soaked up, to below this level with an RC network.(1) Typically this rating (critical or static dv/dt) is 50 to 100 V/s at maximum temperature. Again the failure mode is to let through, to a halfcycle of the line, though a high energy transient can cause permanent damage. Table 6.1 gives some starting points for snubbing circuit values. The component values required depend on the characteristics of the transient, which are usually difficult to quantify. Snubbing across the line as well as across the SSR will also help.
Table 6.1. Typical Snubbing Values
Load Current A rms 5 10 25 40 Resistance 47 33 10 22 Capacitance F 0.047 0.1 0.22 0.47
1. For a more thorough discussion of snubbers, see page 45.
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+ INPUT R1 C1 R2 R4 R6
+ R11 LOAD
SCR1 R13 OC1 Q1 Q2 D2 D1 R3 INPUT AND CONTROL CIRCUIT TRIAC POWER CIRCUIT LINE R7 C2 R5 C11 R12 BR 11 TR11
Figure 6.39 (a). TRIAC SSR Circuit
2. Voltage Drop The SSR output contact has some offset voltage approximately 1 V, depending on current, causing dissipation. As the thyristor has an operating temperature limit of +125C, this heat must be removed, usually by conduction to air via a heat sink or the chassis. 3. Leakage Current When an EMR is open, no current can flow. When an SSR is open however, it does not have as definite an off condition. There is always some current leakage through the output power switching thyristor, the control circuitry, and the snubbing network. The total of this leakage is usually 1 to 10 mA rms three or four orders of magnitude less than the on-state current rating. 4. Multiple Poles are costly to obtain in SSRs, and three phase applications may be difficult to implement. 5. Nuclear Radiation SSRs will be damaged by nuclear radiation.
CONTROL CIRCUIT OPERATION
The operation of the control circuit is straightforward. The AND function of Figure 6.38 is performed by the wired-NOR collector configuration of the small-signal transistors Q1 and Q2. Q1 clamps the gate of SCR1 if optoelectronic-coupler OC1 is off. Q2 clamps the gate if there is sufficient voltage at the junction of the potential divider R4,R5 to overcome the VBE of Q2. By judicious selection of R4 and R5, Q2 will clamp SCR1s gate if more than approximately 5 Volts appear at the anode of SCR1; i.e., Q2 is the zero-crossing detector.
Table 6.2. Control Circuit Parts List
Line Voltage Part C1 C2 D1 D2 OC1 Q1 Q2 R1 R2 R3 R4 R5 R6 R7 SCR1 120 V rms 220 pF, F, 20%, 200 Vdc 0.022 F, 20%, 50 Vdc 1N4001 1N4001 MOC1005 MPS5172 MPS5172 1 k, 10%, 1 W 47 k, 5%, , 1/2 W 1 M, 10%, 1/4 W 110 k, 5%, 1/2 W 15 k, 5% 5%, 1/4 W 33 k, 10%, 10% 1/2 W 10 k, 10% 10%, 1/4 W 2N5064 240 V rms 100 pF, F, 20%, 400 Vdc 0.022 F, 20%, 50 Vdc 1N4001 1N4001 MOC1005 MPS5172 MPS5172 1 k, 10%, 1 W 100 k, 5%, ,1W 1 M, 10%, 1/4 W 220 k, 5%, 1/2 W 15 k, 5% 5%, 1/4 W 68 k, 10% 10%, 1 W 10% 1/4 W 10 k, 10%, 2N6240
TRIAC SSR CIRCUIT Many SSR circuits use a TRIAC as the output switching device. Figure 6.39(a) shows a typical TRIAC SSR circuit. The control circuit is used in the SCR relay as well, and is defined separately. The input circuit is TTL compatible. Output snubbing for inductive loads will be described later. A sensitive-gate SCR (SCR1) is used to gate the power TRIAC, and a transistor amplifier is used as an interface between the optoelectronic-coupler and SCR1. (A sensitive-gate SCR and a diode bridge are used in preference to a sensitive gate TRIAC because of the higher sensitivity of the SCR.)
If OC1 is on, Q1 is clamped off, and SCR1 can be turned on by current flowing down R6, only if Q2 is also off which it is only at zero crossing.
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(b)
ZERO VOLTAGE FIRING LEVEL
CROSSING
LINE ZERO
VSCR1
(c)
FIRING WINDOW WITHOUT C1 AND C2
FIRING WINDOW
(d)
FIRING WINDOW WITH C1 AND C2
FIRING WINDOW
Figure 6.39. Firing Windows
The capacitors are added to eliminate circuit race conditions and spurious firing, time ambiguities in operation. Figure 6.39(b) shows the full-wave rectified line that appears across the control circuit. The zero voltage firing level is shown in 6.39(b) and 6.39(c), expanded in time and voltage. A race condition exists on the up-slope of the second half-cycle in that SCR1 may be triggered via R6 before Q1 has enough base current via R2 to clamp SCR1s gate. C1 provides current by virtue of the rate of change of the supply voltage, and Q1 is turned on firmly as the supply voltage starts to rise, eliminating any possibility of unwanted firing of the SSR; thus eliminating the race condition.
This leaves the possibility of unwanted firing of the SSR on the down-slope of the first half cycle shown. C2 provides a phase shift to the zero voltage potential divider, and Q2 is held on through the real zero-crossing. The resultant window is shown in 6.39(d).
CONTROL CIRCUIT COMPONENTS
The parts list for the control circuit at two line voltages is shown in Table 6.2. R1 limits the current in the input LED of OC1. The input circuit will function over the range of 3 to 33 Vdc. D1 provides reverse voltage protection for the input of OC1.
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D2 allows the gate of SCR1 to be reverse biased, providing better noise immunity and dv/dt performance. R7 eliminates pickup on SCR1s gate through the zero-crossing interval. SCR1 is a sensitive gate SCR; the 2N5064 is a TO-92 device, the 2N6240 is a Case 77 device. Alternatives to the simple series resistor (R1) input circuit will be described later.
POWER CIRCUIT COMPONENTS
The parts list for the TRIAC power circuit in Figure 6.39(a) is shown in Table 6.3 for several rms current ratings, and two line voltages. The metal TRIACs
are in the half-inch pressfit package in the isolated stud configuration; the plastic TRIACs are in the TO-220 Thermowatt package. R12 is chosen by calculating the peak control circuit off-state leakage current and ensuring that the voltage drop across R12 is less than the VGT(MIN) of the TRIAC. C11 must be an ac rated capacitor, and with R13 provides some snubbing for the TRIAC. The values shown for this network are intended more for inductive load commutating dv/dt snubbing than for voltage transient suppression. Consult the individual data sheets for the dissipation, temperature, and surge current limits of the TRIACs.
Table 6.3. TRIAC Power Circuit Parts List

Voltage rms Current Amperes BR11 C11, F (10%, line voltage ac rated) R11 (10%, 1 W) R12 (10%, 1/2 W) R13 (10%, 1/2 W) TR11 Plastic 8 IN4004(4) 0.047 12 IN4004(4) 0.047 120 V rms 25 IN4004(4) 0.1 40 IN4004(4) 0.1 8 IN4004(4) 0.047 12 IN4004(4) 0.047 240 V rms 25 IN4004(4) 0.1 40 IN4004(4) 0.1
39 18 620 2N6344
39 18 620 2N6344A
39 18 330
39 18 330
39 18 620 2N6344
39 18 620 2N6344A
39 18 330
39 18 330
TRIACs AND INDUCTIVE LOADS The TRIAC is a single device which to some extent is the equivalent of two SCRs inverse parallel connected; certainly this is so for resistive loads. Inductive loads however, can cause problems for TRIACs, especially at turn-off. A TRIAC turns off every line half-cycle when the line current goes through zero. With a resistive load, this coincides with the line voltage also going through zero. The TRIAC must regain blocking-state before there are more than 1 or 2 Volts of the reverse polarity across it at 120 V rms, 60 Hz line this is approximately 30 s. The TRIAC has not completely regained its off-state characteristics, but does so as the line voltage increases at the 60 Hz rate. Figure 6.40 indicates what happens with an inductive or lagging load. The on signal is removed asynchronously and the TRIAC, a latching device, stays on until the next current zero. As the current is lagging the applied voltage, the line voltage at that instant appears across the TRIAC. It is this rate-of-rise of voltage, the commutating dv/dt, that must be limited in TRIAC circuits, usually to a few volts per microsecond. This is normally done by use of a snubber network RS and CS as shown in Figure 6.41.
SCRs have less trouble as each device has a full half-cycle to turn off and, once off, can resist dv/dt to the critical value of 50 to 100 V/s.
CHOOSING THE SNUBBING COMPONENTS(1)
There are no easy methods for selecting the values of RS and CS in Figure 6.41 required to limit commutating dv/dt. The circuit is a damped tuned circuit comprised by RS, CS, RL and LL, and to a minor extent the junction capacitance of the TRIAC. At turn-off this circuit receives a step impulse of line voltage which depends on the power factor of the load. Assuming the load is fixed, which is normally the case, the designer can vary RS and CS. CS can be increased to decrease the commutating dv/dt; RS can be increased to decrease the resonant over-ring of the tuned circuit to increase damping. This can be done empirically, beginning with the values for C11 and R13 given in Table 6.3, and aiming at close to critical damping and the data sheet value for commutating dv/dt. Reduced temperatures, voltages, and off-going di/dt (rate-of-change of current at turn-off) will give some safety margin.
1. For a more thorough discussion of snubbers, see page 45.
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ON/OFF SIGNAL
ON OFF
LOAD CURRENT 0 (LAGGING LOAD) LINE VOLTAGE dv/dt
LINE AND TRIAC VOLTAGE TRIAC VOLTAGE
Figure 6.40. Commutating dv/dt
Table 6.4. SCR Power Circuit Parts List

Voltage rms Current Amperes C21 (10%, line voltage ac rated) D21-24 R21 (10%, 1 W) R22, 23 (10%, 1/2 W) R24 SCR21 22 SCR21, Plastic 2N6240 2N6397 2N6402 1N4003 39 18 1N4003 39 18 1N4003 39 18 5 120 V rms 11 22 49 5 240 V rms 11 22 49
SEE TEXT 1N4003 39 18 1N4004 39 18 1N4004 39 18 1N4004 39 18 1N4004 39 18
SEE TEXT 2N6240 2N6397 2N6403
LL
LOAD
RL
RS CS
Figure 6.41. TRIAC with Snubber Network
SCR SSR CIRCUIT The inverse parallel connected Silicon Controlled Rectifier (SCR) pair (shown in Figure 6.42) is less sensitive to
commutating dv/dt. Other advantages are the improved thermal and surge characteristics of having two devices; the disadvantage is increased cost. The SCR power circuit can use the same control circuit as the TRIAC Circuit shown in Figure 6.39(a). In Figure 6.42, for positive load terminal and when the control circuit is gated on, current flows through the load, D21, R21, SCR1, D22, the gate of SCR21 and back to the line, thus turning on SCR21. Operation is similar for the other line polarity. R22 and R23 provide a path for the off-state leakage of the control circuit and are chosen so that the voltage dropped across them is less than the VGT(MIN) of the particular SCR. R24 and C21 provide snubbing and line transient suppression, and may be chosen from Table 6.4 or from the C11, R13 rows of Table 6.3. The latter values will provide less transient protection but also less off-state current, with the capacitor being smaller. Other circuit values are shown in Table 6.46.
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LOAD D21 R23
D24 R21 + INPUT + R24 D22 SCR21 C21 SCR22 CONTROL CIRCUIT (SEE FIGURE 6.39(a) AND TABLE 6.II)
R22 D23 LINE
Figure 6.42. SCR SSR Circuit
Consult the individual data sheets for packages and dissipation, temperature, and surge current limits. While the SCRs have much higher dv/dt commutation ability, with inductive loads, attention should be paid to maintaining the dv/dt below data sheet levels. ALTERNATE INPUT CIRCUITS
CMOS COMPATIBLE
adequately over 3 to 33 Vdc and 40 to +100C. Note that though the SSR is protected against damage from improperly connected inputs, the external circuit is not, as D31 acts as a bypass for a wrongly connected input driver.
+ OC1
The 1 k resistor, R1, shown in Figure 6.39(a) and Table 6.2, provide an input that is compatible with the current that a TTL gate output can sink. The resistor R1 must be changed for CMOS compatibility, aiming at 2 mA in the LED for adequate performance to 100C. At 2 mA do not use the CMOS output for any other function, as a LOGIC 0 or 1 may not be guaranteed. Assume a forward voltage drop of 1.1 V for the LED, and then make the Ohms Law calculation for the system dc supply voltage, thus defining a new value for R1.
TTL/CMOS COMPATIBLE
R31 330 k
INPUT Q32 D31 1N4001 2N6427 Q31 MPS5172 TH31 WESTERN THERMISTOR CORP., CURVE 2, 650 10% @ 25C P/N2C6500 OR EQUIVALENT R33 180
To be TTL compatible at 5 Volts and CMOS compatible over 3 to 15 Volts, a constant current circuit is required, such as the one in Figure 6.43. The current is set by the VBE of Q31 and the resistance of the R32, R33, and thermistor TH31 network, and is between 1 and 2 mA, higher at high temperatures to compensate for the reduced transmission efficiency of optoelectronic-couplers at higher temperature. The circuit of Figure 6.43 gives an equivalent impedance of approximately 50 k. The circuit performs
R32 330
TH31
Figure 6.43. TTL/CMOS Compatible Input
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AC LINE COMPATIBLE
To use SSRs as logic switching elements is inefficient, considering the availability and versatility of logic families such as CMOS. When it is convenient to trigger from ac, a circuit such as shown in Figure 6.44 may be used. The capacitor C41 is required to provide current to the LED of OC1 through the zero-crossing time. An in-phase input voltage gives the worst case condition. The circuit gives 2 mA minimum LED current at 75% of nominal line voltage. INVERSE PARALLEL SCRs FOR POWER CONTROL TRIACs are very useful devices. They end up in solid
state relays, lamp drivers, motor controls, sensing and detection circuits; just about any industrial full-wave application. But in high-frequency applications or those requiring high voltage or current, their role is limited by their present physical characteristics, and they become very expensive at current levels above 40 amperes rms. SCRs can be used in an inverse-parallel connection to bypass the limitations of a TRIAC. A simple scheme for doing this is shown in Figure 6.45. The control device can take any of many forms, shown is the reed relay (Figure 6.45). TRIACs and Opto couplers can be inserted at point AA to replace the reed relay.
R42 R41 C41 BR41 INPUT AC 2 F 10% 50 V
2 k, 10% 1/2 W R41 OC1 120 V 240 V 22 k, 10%, 1 W 47 k, 10%, 2 W
Figure 6.44. AC Compatible Input
Compared to a TRIAC, an inverse-parallel configuration has distinct advantages. Voltage and current capabilities are dependent solely on SCR characteristics with ratings today of over a thousand volts and several hundred amps. Because each SCR operates only on a half-wave basis, the systems rms current rating is 2 times the SCRs rms
FLOATING LOAD RL ILa SCR1 OR
current rating (see Suggested SCR chart). The system has the same surge current rating as the SCRs do. Operation at 400 Hz is also no problem. While turn-off time and dv/dt limits control TRIAC operating speed, the recovery characteristics of an SCR need only be better than the appropriate half-wave period.
V q I2 * (RL ) RC) GP WHERE IGP IS PEAK GATE CURRENT RATING OF SCR a b 2V
IG1 IG
1 A
2 A R SCR2
GROUNDED LOAD RL
RC CONTROL DEVICE (CLOSED RESISTANCE) IG2
ILb
Figure 6.45. Use of Inverse Parallel SCRs
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With inductive loads you no longer need to worry about commutating dv/dt, either. SCRs only need to withstand static dv/dt, for which they are typically rated an order of magnitude greater than TRIACs are for commutating dv/dt. Better reliability can be achieved by replacing the reed relay with a low current TRIAC to drive the SCRs, although some of its limitations come with it. In the preferred circuit of Figure 6.46(b), the main requirements of the TRIAC are that it be able to block the peak system voltage and that it have a surge current rating compatible with the gate current require-ments of the SCRs. This is normally so small that a TO-92 cased device is adequate to drive the largest SCRs. In circuits like Figure 6.45, the control devices
A
alternately pass the gate currents IG1 and IG2 during the a and b half cycles, respectively. ILa and ILb are the load currents during the corresponding half cycles. Each SCR then gets the other half cycle for recovery time. Heat sinking can also be done more efficiently, since power is being dissipated in two packages, rather than all in one. The load can either be floated or grounded. the SCRs are not of the shunted-gate variety, a gate-cathode resistance should be added to shunt the leakage current at higher temperatures. The diodes act as steering diodes so the gate-cathode junctions are not avalanched. The blocking capability of the diodes need only be as high as the VGT of the SCRs. A snubber can also be used if conditions dictate.
A A A
GATE CONTROL GATE CONTROL
GATE CONTROL (FLOATING)
(a). Reed Relay
(b). Low-Current TRIAC
(c). Optically Coupled TRIAC Driver
Figure 6.46. Control Devices
This circuit offers several benefits. One is a considerable increase in gain. This permits driving the TRIAC with almost any other semiconductors such as linear ICs, photosensitive devices and logic, including MOS. If necessary, it can use an optically coupled TRIAC driver to isolate (up to 7500 V isolation) delicate logic circuits from
the power circuit (see Figure 6.46(c)). Table 6.6. lists suggested components. Another benefit is being able to gate the TRIAC with a supply of either polarity. Probably the most important benefit of the TRIAC/SCR combination is its ability to handle variable-phase applications nearly impossible for non solid-state control devices.
Table 6.6. Driver TRIACs

Line Voltage 120 220 Gate Negative Or In Phase With Line Voltage MAC97A4 MAC97A6 Gate Positive MAC97A4 MAC97A6 Optically Coupled MOC3030*, 3011 MOC3020, MOC3021
*Includes inhibit circuit for zero crossover firing.
INTERFACING DIGITAL CIRCUITS TO THYRISTOR CONTROLLED AC LOADS Because they are bidirectional devices, TRIACs are the most common thyristor for controlling ac loads. A TRIAC can be triggered by either a positive or negative gate signal on either the positive or negative half-cycle of applied MT2 voltage, producing four quadrants of operation. However, the TRIACs trigger sensitivity varies with the quadrant,
with quadrants II and III (gate signal negative and MT2 either positive or negative) being the most sensitive and quadrant IV (gate positive, MT2 negative) the least sensitive. For driving a TRIAC with IC logic, quadrants II and III are particularly desirable, not only because less gate trigger current is required, but also because IC power dissipation is reduced since the TRIAC can be triggered by an active low output from the IC.
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There are other advantages to operating in quadrants II and III. Since the rate of rise of on-state current of a TRIAC (di/dt) is a function of how hard the TRIACs gate is turned on, a given IC output in quadrants II and III will produce a greater di/dt capability than in the less sensitive quadrant IV. Moreover, harder gate turn-on could reduce di/dt failure. One additional advantage of quadrant II and III operation is that devices specified in all four quadrants are generally more expensive than devices specified in quadrants I, II and III, due to the additional testing involved and the resulting lower yields.
USING TRIACs
TTL-TO-THYRISTOR INTERFACE The subject of interfacing requires a knowledge of the output characteristics of the driving stages as well as the input requirements of the load. This section describes the driving capabilities of some of the more popular TTL circuits and matches these to the input demands of thyristors under various practical operating conditions.
Two important thyristor parameters are gate trigger current (IGT) and gate trigger voltage (VGT). IGT (Gate Trigger Current) is the amount of gate trigger current required to turn the device on. IGT has a negative temperature coefficient that is, the trigger current required to turn the device on increases with decreasing temperature. If the TRIAC must operate over a wide temperature range, its IGT requirement could double at the low temperature extreme from that of its 25C rating. It is good practice, if possible, to trigger the thyristor with three to ten times the IGT rating for the device. This increases its di/dt capability and ensures adequate gate trigger current at low temperatures. VGT (Gate Trigger Voltage) is the voltage the thyristor gate needs to ensure triggering the device on. This voltage is needed to overcome the input threshold voltage of the device. To prevent thyristor triggering, gate voltage should be kept to approximately 0.4 V or less. Like IGT, VGT increases with decreasing temperature.
INDUCTIVE LOAD SWITCHING
LOAD MT2 MT1 B TRIAC CURRENT 60 Hz LINE
GATE VOLTAGE APPLIED TO TERMINALS A AND B
A t1 IGT TRIAC VOLTAGE WITH SNUBBER NETWORK t2
Switching of inductive loads, using TRIACs, may require special consideration in order to avoid false triggering. This false-trigger mechanism is illustrated in Figure 6.47 which shows an inductive circuit together with the accompanying waveforms. As shown, the TRIAC is triggered on, at t1, by the positive gate current (IGT). At that point, TRIAC current flows and the voltage across the TRIAC is quite low since the TRIAC resistance, during conduction, is very low. From point t1 to t2 the applied IGT keeps the TRIAC in a conductive condition, resulting in a continuous sinusoidal current flow that leads the applied voltage by 90 for this pure inductive load. At t2, IGT is turned off, but TRIAC current continues to flow until it reaches a value that is less than the sustaining current (IH), at point A. At that point, TRIAC current is cut off and TRIAC voltage is at a maximum. Some of that voltage is fed back to the gate via the internal capacitance (from MT2 to gate) of the TRIAC.
CHANGE IN TRIAC VOLTAGE DURING TURN-OFF (dv)
toff(dt) TRIAC VOLTAGE WITH SNUBBER NETWORK
UNDESIRED TRIGGERING DUE TO FEEDBACK
Figure 6.47. Inductive Load TRIAC Circuit and Equivalent Waveforms
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TTL CIRCUITS WITH TOTEM-POLE OUTPUTS (e.g. 5400 SERIES)
VCC SOURCE CURRENT R2 SINK 100 CURRENT Q2
VCC LOAD CONNECTION FOR CURRENT SINK CONDITION Vout Q3
The configuration of a typical totem-pole connected TTL output stage is illustrated in Figure 6.48(a). This stage is capable of sourcing current to a load, when the load is connected from Vout to ground, and of sinking current from the load when the latter is connected from Vout to VCC. If the load happens to be the input circuit of a TRIAC (gate to MT1), the TRIAC will be operating in quadrants I and IV (gate goes positive) when connected from Vout to ground, and of sinking II and III (gate goes negative) when connected from Vout to VCC.
QUADRANT I-IV OPERATION
R1 1.4 k Vin TTL GATE Q1
1k
LOAD CONNECTION FOR CURRENT SOURCE CONDITION
Considering first the gate-positive condition, Figure 6.48(b), the operation of the circuit is as follows: When Vin to the TTL output stage is low (logical zero), transistors Q1 and Q3 of that stage are cut off, and Q2 is conducting. Therefore, Q2 sources current to the thyristor, and the thyristor would be triggered on during the Vin = 0 condition. When Vin goes high (logical one), transistors Q1 and Q3 are on and Q2 is off. In this condition depicted by the equivalent circuit transistor Q3 is turned on and its collector voltage is, essentially, VCE(sat). As a result, the TRIAC is clamped off by the low internal resistance of Q3.
QUADRANT II-III OPERATION
Vin Vout SOURCE CURRENT SINK CURRENT
(a)
VCC
When the TRIAC is to be operated in the more sensitive quadrants II and III (negative-gate turn-on), the circuit in Figure 6.49(a) may be employed. With Q3 in saturation, as shown in the equivalent circuit of 6.49(b), its saturation voltage is quite small, leaving virtually the entire VEE voltage available for thyristor turn-on. This could result in a TRIAC gate current that exceeds the current limit of Q3, requiring a current-limiting series resistor, (R(Iim)). When the Vout level goes high, Q3 is turned off and Q2 becomes conductive. Under those conditions, the TRIAC gate voltage is below VGT and the TRIAC is turned off.
DIRECT-DRIVE LIMITATIONS
R1
R2
TRIAC LOAD 60 Hz
Q2
Vout GATE MT1
(b)
With sensitive-gate TRIACs, the direct connection of a TRIAC to a TTL circuit may sometimes be practical. However, the limitations of such circuits must be recognized. For example: For TTL circuits, the high logic level is specified as 2.4 volts. In the circuit of Figure 6.48(a), transistor Q2 is capable of supplying a short-circuit output current (ISC) of 20 to 55 mA (depending on the tolerances of R1 and R2, and on the hFE of Q2). Although this is adequate to turn a sensitive-gate TRIAC on, the specified 2.4 volt (high) logic level can only be maintained if the sourcing current is held to a maximum of 0.4 mA far less than the current required to turn on any thyristor. Thus, the direct connection is useful only if the driver need not activate other logic circuits in addition to a TRIAC.
R1
TRIAC LOAD Vout Q3 60 Hz
Q1
1k
(c) Figure 6.48. Totem-Pole Output Circuit TTL Logic, Together with Voltage and Current Waveforms, (b) Equivalent Circuit for Triggering TRIAC with a Positive Voltage TRIAC-On Condition, (c) TRIAC-Off Condition
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A similar limiting condition exists in the Logic 0 condition of the output, when the thyristor is to be clamped off. In this condition, Q3 is conducting and Vout equals the saturation voltage (VCE(sat)) of Q3. TTL specifications indicate that the low logic level (logic 0) may not exceed 0.4 volts, and that the sink current must be limited to 16 mA in order not to exceed this value. A higher value of sink current would cause (VCE(sat)) to rise, and could trigger the thyristor on.
CIRCUIT DESIGN CONSIDERATIONS
In practice, a 270 , 1/4 W resistor may be used.
R(lim) LOGIC CIRCUIT
MT1
MT2 LOAD
60 Hz LINE
Where a 5400-type TTL circuit is used solely for controlling a TRIAC, with positive-gate turn-on (quadrants I-IV), a sensitive gate TRIAC may be directly coupled to the logic output, as in Figure 6.48. If the correct logic levels must be maintained, however, a couple of resistors must be added to the circuit, as in Figure 6.50(a). In this diagram, R1 is a pull-up which allows the circuit to source more current during a high logical output. Its value must be large enough, however, to limit the sinking current below the 16 mA maximum when Vout goes low so that the logical zero level of 0.4 volts is not exceeded. Resistor R2, a voltage divider in conjunction with R1, insures VOH (the high output voltage) to be 2.4 V or greater. For a supply voltage of 5 V and a maximum sinking current of 16 mA
R1
(a)
5V
R1
Isink Vout R(lim) MT1
Q1 Q3 1k VEE(sat) 0.4 V MAX LOAD MT2
60 Hz LINE
q VCC16 mA q 50.016 q 312 W
5V
(b)
Thus, 330 , 1/4 W resistor may be used. Assuming R1 to be 330 and a thyristor gate on voltage (VGT) of 1 V, the equivalent circuit of Figure 6.49(b) exists during the logical 1 output level. Since the logical 1 level must be maintaned at 2.4 volts, the voltage drop across R2 must be 1.4 V. Therefore,
R2
Figure 6.49. TTL Circuit for Quadrant II and III TRIAC Operation Requiring Negative VGT, (b) Schematic Illustrates TRIAC Turn-On Condition, Vout = Logical 0
+ 1.4IR + 1.4VR R + 1.4(2.63.30) ` 175 W

1 2
VCC
VCC
A 180 resistor may be used for R2. If the VGT is less than 1 volt, R2 may need to be larger. The MAC97A and 2N6071A TRIACs are compatible devices for this circuit arrangement, since they are guaranteed to be triggered on by 5 mA, whereas the current through the circuit of Figure 6.50(b) is approximately 8 mA, (V R R 1). When the TRIAC is to be turned on by a negative gate voltage, as in Figure 6.49(b), the purpose of the limiting resistor R(Iim) is to hold the current through transistor Q3 to 16 mA. With a 5 V supply, a TRIAC VGT of 1 V and a maximum sink current of 16 mA
R (lim)
LOAD 60 Hz LINE
R1
R1 Vout R2
MT2
Vout = 2.4 V
R2 LOGIC CIRCUIT MT1 G=1V
(a)
(b)
+ (VCCVGT)Isink + (51)(0.016q250 W
Figure 6.50. Practical Direct-Coupled TTL TRIAC Circuit, (b) Equivalent Circuit Used for Calculation of Resistor Values
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OPEN COLLECTOR TTL CIRCUIT
The output section of an open-collector TTL gate is shown in Figure 6.51(a). A typical logic gate of this kind is the 5401 type Q2-input NAND gate circuit. This logic gate also has a maximum sink current of 16 mA (VOL = 0.4 V max.) because of the Q1 (sat) limitations. If this logic gate is to source any current, a pull-up-collector resistor, R1 (6.51b) is needed. When this TTL gate is used to trigger a thyristor, R1 should be chosen to supply the maximum trigger current available from the TTL circuit ( 16 mA, in this case). The value of R1 is calculated in the same way and for the same reasons as in Figure 6.50. If a logical 1 level must be maintained at the TTL output (2.4 V min.), the entire circuit of Figure 6.50 should be used. For direct drive (logical 0) quadrants II and III triggering, the open collector, negative supplied ( 5 V) TTL circuit of Figure 6.52 can be used. Resistor R1 can have a value of 270 , as in Figure 6.49. Resistor R2 ensures that the TRIAC gate is referenced to MT1 when the TTL gate goes high (off), thus preventing unwanted turn-on. An R2 value of about 1 k should be adequate for sensitive gate TRIACs and still draw minimal current.
Circuits utilizing Schottky TTL are generally designed in the same way as TTL circuits, although the current source/sink capabilities may be slightly different.
MT1
R2 MT2 R1 LOGIC CIRCUIT 5V LOAD 60 Hz LINE
Figure 6.52. Negative-Supplied ( 5 V) TTL Gate Permits TRIAC Operation in Quadrants II and III
TRIGGERING THYRISTORS FROM LOGIC GATES USING INTERFACE TRANSISTORS
VCC
1.4 k TTL GATE Q1 1k
Vout
(a)
5V LOAD
For applications requiring thyristors that demand more gate current than a direct-coupled logic circuit can supply, an interface device is needed. This device can be a small-signal transistor or an opto coupler. The transistor circuits can take several different configurations, depending on whether a series or shunt switch design is chosen, and whether gate-current sourcing (quadrants I and IV) or sinking (quadrants II and III) is selected. An example of a series switch, high output (logic 1) activation, is shown in Figure 6.53. Any logic family can be used as long as the output characteristics are known. The NPN interface transistor, Q1, is configured in the common-emitter mode the simplest approach with the emitter connected directly to the gate of the thyristor.
VCC
MT2 R1 Vout LOGIC CIRCUIT G
60 Hz LINE R1 R2 R4
LOAD
MT2 Q1
60 Hz LINE
MT1 LOGIC GATE
G R3 R5
MT1
(b) Figure 6.51. Output Section of Open-Collector TTL, (b) For Current Sourcing, A Pull-up Resistor, R1, Must Be Added
Figure 6.53. Series Switch, High Output (Logic 1)
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Depending on the logic family used, resistor R1 (pull-up resistor) and R3 (base-emitter leakage resistor) may or may not be required. If, for example, the logic is a typical TTL totem-pole output gate that must supply 5 mA to the base of the NPN transistor and still maintain a high (2.4 V) logic output, then R1 and R2 are required. If the high logic level is not required, then the TTL circuit can directly source the base current, limited by resistor R2. To illustrate this circuit, consider the case where the selected TRIAC requires a positive-gate current of 100 mA. The interface transistor, a popular 2N4401, has a specified minimum hFE (at a collector current of 150 mA) of 100. To ensure that this transistor is driven hard into saturation, under worse case (low temperature) conditions, a forced hFE of 20 is chosen thus, 5 mA of base current. For this example, the collector supply is chosen to be the same as the logic supply (+5 V); but for the circuit configuration, it could be a different supply, if required. The collector-resistor, R4, is simply
R4
When thyristor operation in quadrants II and III is desired, the circuits of Figures 6.55 and 6.56 can be used; Figure 6.55 is for high logic output activation and Figure 6.56 is for low. Both circuits are similar to those on Figures 6.53 and 6.54, but with the transistor polarity and power supplies reversed.
+5V
LOAD R2 MT2 R1 Q1 LOGIC GATE R4 R3 G MT1 60 Hz LINE
+ (VCC * VCE(sat) * VGT(typ))IGT + (5 * 1 * 0.9)100 mA + 40 W
Figure 6.54. Low-Logic Activation with Interface Transistor
A 39 ohm, 1 W resistor is then chosen, since its actual dissipation is about 0.4 W. If the logic 1 output level is not important, then the base limiting resistor R2 is required, and the pull-up resistor R1 is not. Since the collector resistor of the TTL upper totem-pole transistor, Q2, is about 100 , this resistor plus R2 should limit the base current to 5 mA. Thus R2 calculates to
R2
R1 R2 LOGIC GATE
R5 R4 Q1
MT1
MT2 R3 LOAD
60 Hz LINE
+ [(VCC * VBE * VGT)5 mA] * 100 W + [(5 * 0.7 * 0.9)0.005] 100 W [ 560 W (specified)
VEE
When the TTL output is low, the lower transistor of the totem-pole, Q3, is a clamp, through the 560 resistor, across the 2N4401; and, since the 560 resistor is relatively low, no leakage-current shunting resistor, R3, is required. In a similar manner, if the TTL output must remain at logic 1 level, the resistor R1 can be calculated as described earlier (R3 may or may not be required). For low-logic activation (logic 0), the circuit of Figure 6.54 can be used. In this example, the PNP-interface transistor 2N4403, when turned on, will supply positivegate current to the thyristor. To ensure that the high logic level will keep the thyristor off, the logic gate and the transistor emitter must be supplied with the same power supply. The base resistors, as in the previous example, are dictated by the output characteristics of the logic family used. Thus if a TTL gate circuit is used, it must be able to sink the base current of the PNP transistor (IOL(MAX) = 16 mA).
Figure 6.55. High-Logic Output Activation
Figure 6.55 sinks current from the thyristor gate through a switched NPN transistor whose emitter is referenced to a negative supply. The logic circuit must also be referenced to this negative supply to ensure that transistor Q1 is turned off when required; thus, for TTL gates, VEE would be 5 V. In Figure 6.56, the logic-high bus, which is now ground, is the common ground for both the logic, and the thyristor and the load. As in the first example (Figure 6.53), the negative supply for the logic circuit (VEE) and the collector supply for the PNP transistor need not be the same supply. If, for power-supply current limitations, the collector supply is chosen to be another supply (VCC), it must be within the VCEO ratings of the PNP transistor. Also, the power dissipation of collector resistor, R3, is a function of VCC the lower VCC, the lower the power rating.
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R2 R1 LOGIC GATE
R4 G
MT1
MT2 R3 LOAD
60 Hz LINE
The four examples shown use gate-series switching to activate the thyristor and load (when the interface transistor is off, the load is off). Shunt-switching can also be used if the converse is required, as shown in Figures 6.57 and 6.58. In Figure 6.57, when the logic output is high, NPN transistor, Q1, is turned on, thus clamping the gate of the thyristor off. To activate the load, the logic output goes low, turning off Q1 and allowing positive gate current, as set by resistor R3, to turn on the thyristor. In a similar manner, quadrants II and III operation is derived from the shunt interface circuit of Figure 6.58. OPTICAL ISOLATORS/COUPLERS An Optoelectronic isolator combines a light-emitting device and a photo detector in the same opaque package that provides ambient light protection. Since there is no electrical connection between input and output, and the emitter and detector cannot reverse their roles, a signal can pass through the coupler in one direction only. Since the opto-coupler provides input circuitry protection and isolation from output-circuit conditions, groundloop prevention, dc level shifting, and logic control of high voltage power circuitry are typical areas where optocouplers are useful. Figure 6.59 shows a photo-TRIAC used as a driver for a higher-power TRIAC. The photo-TRIAC is light sensitive and is turned on by a certain specified light density (H), which is a function of the LED current. With dark conditions (LED current = 0) the photo-TRIAC is not turned on, so that the only output current from the coupler is leakage current, called peak-blocking current (IDRM). The coupler is bilateral and designed to switch ac signals. The photo-TRIAC output current capability is, typically, 100 mA, continuous, or 1 A peak.
I H R MT2
VEE
Figure 6.56. Low-Logic Output Activation
+5V
R3
LOAD
R1 Q1 LOGIC GATE R2 G
MT2
60 Hz LINE
MT1
Figure 6.57. Shunt-Interface Circuit (High-Logic Output
R2 R1 LOGIC GATE R3
MT1
MT2
60 Hz LINE
LED PHOTO TRIAC OPTO COUPLER LOAD G MT1 60 Hz LINE
LOAD
VEE
Figure 6.58. Shunt-Interface Circuit (Quadrants I and III Operation)
Figure 6.59. Optically-Coupled TRIAC Driver is Used to Drive a Higher-Power TRIAC
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Any Opto TRIAC can be used in the circuit of Figure 6.59 by using Table 6.8. The value of R is based on the photo-TRIACs current-handling capability. For example, when the MOC3011 operates with a 120 V line voltage (approximately 175 V peak), a peak IGT current of 175 V/180 ohm (approximately 1 A) flows when the line voltage is at its maximum. If less than 1 A of IGT is needed, R can be increased. Circuit operation is as follows:
+ 300 mA (VOH + 2.4 V) + 1.8 mA (VOL + 0.4 V) V CC + 5 V

I OH I OL
Since this is not adequate for driving the optocoupler directly (10 mA for the MOC3011), an interface transistor is necessary. The circuit of Figure 6.60 may be used for thyristor triggering from the 3870 logical 1.
+5V R3
Table 6.8. Specifications for Typical Optically Coupled TRIAC Drivers

Device Type MOC3011 MOC3011 MOC3021 MOC3031 Maximum Required LED Trigger Current (mA) 15 10 15 15 Peak Blocking Voltage 250 250 400 250 R(Ohms) 180 180 360 51
R R1 MT2 60 Hz LINE G R2 MT1
When an op-amp, logic gate, transistor or any other appropriate device turns on the LED, the emitted light triggers the photo-TRIAC. Since, at this time, the main TRIAC is not on, MT2-to-gate is an open circuit. The 60 Hz line can now cause a current flow via R, the photo-TRIAC, Gate-MT1 junction and load. This Gate-MT1 current triggers the main TRIAC, which then shorts and turns off the photo-TRIAC. The process repeats itself every half cycle until the LED is turned off. Triggering the main TRIAC is thus accomplished by turning on the LED with the required LED-trigger current indicated in Table 6.7. MICROPROCESSORS Microprocessor systems are also capable of controlling ac power loads when interfaced with thyristors. Commonly, the output of the MPU drives a PIA (peripheral interface adaptor) which then drives the next stage. The PIA Output Port generally has a TTL compatible output with significantly less current source and sink capability than standard TTL. (MPUs and PIAs are sometimes constructed together on the same chip and called microcontrollers.) When switching ac loads from microcomputers, it is good practice to optically isolate them from unexpected load or ac line phenomena to protect the computer system from possible damage. In addition, optical isolation will make UL recognition possible. A typical TTL-compatible microcontroller, such as the MC3870P offers the following specifications:
Q1 MC3870
LOAD
Figure 6.60. Logical 1 Activation from MC3870P Microcomputer
The interface transistor, again, can be the 2N4401. With 10 mA of collector current (for the MOC3011) and a base current of 0.75 mA, the VCE(sat) will be approximately 0.1 V. R1 can be calculated as in a previous example. Specifically:
1.8 mA (maximum I OL for the 3870) 5 V R 1; R 1 2.77 k
u R 1 can be 3 k, 14 W
R2
With a base current of 0.75 mA, R1 will drop (0.75 mA) (3 k) or 2.25 V. This causes a VOH of 2.75 V, which is within the logical 1 range.
+ [2.75 VVBE(on)]IB + (2.750.75)0.75 + 2.66 R 2 can be a 2.7 k, 14 W resistor. .

R 3 must limit I C to 10 mA : R3
+ [5 VVCE(sat) VF(diode)10 mA] + (50.11.2)10 mA + 370 W
Since R3 is relatively small, no base-emitter leakage resistor is required.
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Figure 6.61 shows logical 0 activation. Resistor values are calculated in a similar way.
+5V
R1 R2 Q1 MC3870P R3 R MT2 60 Hz LINE MT1
LOAD
Figure 6.61. Logical 0 Activation
VDD S
VDD
VDD
P-CHANNEL Vin D D Vout N-CHANNEL
P-CHANNEL rDS(on) Vout Vout
RL
RL S
N-CHANNEL rDS(on)
(a)
(b)
(c)
As shown in Figure 6.62(a), the output stage of a typical CMOS Gate consists of a P-channel MOS device connected in series with an N-channel device (drain-to-drain), with the gates tied together and driven from a common input signal. When the input signal goes high, logical 1, the P-channel device is essentially off and conducts only leakage current (IDSS), on the order of pico-amps. The N-channel unit is forward-biased and, although it has a relatively high on resistance (rDS(on)), the drain-to-source voltage of the N-channel device (VDS) is very low (essentially zero) because of the very low drain current (VDSS) flowing through the device. Conversely, when the input goes low (zero), the P-channel device is turned fully on, the N-channel device is off and the output voltage will be very near VDD. When interfacing with transistors or thyristors, the CMOS Gate is current-limited mainly by its relatively high on resistance, the dc resistance between drain and source, when the device is turned on. The equivalent circuits for sourcing and sinking current into an external load is shown in Figures 6.62(b) and 6.62(c). Normally, when interfacing CMOS to CMOS, the logic outputs will be very near their absolute maximum states (VDD or 0 V) because of the extremely small load currents. With other types of loads (e.g. TRIACs), the current, and the resulting output voltage, is dictated by the simple voltage divider of rDS(on) and the load resistor RL, where rDS(on) is the total series and/or parallel resistance of the devices comprising the NOR and NAND function. Interfacing CMOS gates with thyristors requires a knowledge of the on resistance of the gate in the source and sink conditions. The on-resistance of CMOS devices is not normally specified on data sheets. It can easily be calculated, however, from the output drive currents, which are specified. The drive (source/sink) currents of typical CMOS gates at various supply voltages are shown in Table 6.9. From this information, the on resistance for worst case design is calculated as follows: For the source condition
r DS(on)(MAX)
Figure 6.62. Output Section of a Typical CMOS Gate, (b) Equivalent Current-Sourcing Circuit is Activated when Vin goes Low, Turning the P-Channel Device Fully On, (c) Equivalent Current Sinking Circuit is Activated when the Input Goes High and Turns the N-Channel Device On
+ (VDD * VOH)IOH(MIN) + VOLIOL(MIN)
Similarly, for the sink current condition

r DS(on)(MAX)
THE CMOS INTERFACE Another popular logic family, CMOS, can also be used to drive thyristors.
Values of rDS(on) for the various condition shown in Table 6.9 are tabulated in Table 6.10. Specified source/sink currents to maintain logical 1 and logical 0 levels for various power-supply (VDD) voltages. The IOH and IOL values are used to calculate the on resistance of the CMOS output.
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Table 6.9. CMOS Characteristics

CMOS AL Series mA, dc Min I(source) IOH VDD = 5 V; VOH = 2.5 V VDD = 10 V; VOH = 9.5 V VDD = 15 V; VOH = 13.5 V I(sink) IOL VDD = 5 V; VOL= 0.4 V VDD = 10 V; VOL = 0.5 V VDD = 15 V; VOL = 1.5 V 0.5 0.5 Typ 1.7 0.9 3.5 7.8 2 7.8 CMOSCL/CP Series mA, dc Min 0.2 0.2 Typ 1.7 0.9 3.5 7.8 2 7.8
DC MOTOR CONTROL WITH THYRISTORS In order to control the speed of a dc series field motor at different required torque levels, it is necessary to adjust the voltage applied to the motor. For any particular applied voltage the motor speed is determined solely by the torque requirements and top speed is reached under minimum torque conditions. When a series motor is used as a traction drive for vehicles, it is desirable to control the voltage to the motor to fit the various torque requirements of grades, speed and load. The common method of varying the speed of the motor is by inserting resistance in series with the motor to reduce the supplied voltage. This type of motor speed control is very inefficient due to the I2R loss, especially under high current and torque conditions. A much more efficient method of controlling the voltage applied to the motor is the pulse width modulation method shown in Figure 6.63. In this method, a variable width pulse of voltage is applied to the motor at the same rate to proportionally vary the average voltage applied to the motor. A diode is placed in parallel with the inductive motor path to provide a circuit for the inductive motor current and prevent abrupt motor current change. Abrupt current changes would cause high induced voltage across the switching device.
APPLIED BATTERY VOLTAGE
Output Drive Current
0.4 0.9
0.2 0.5
Table 6.10. Calculated CMOS On Resistance Values For Current Sourcing and Sinking at Various VDD Options
OutputResistance,rDS(on) Ohms Typical Source Condition VDD = 5V 10 V 15 V 5V 10 V 15 V 1.7 k 500 430 500 420 190 12.5 k 2.5 k 2k 1k Maximum
p g Conditions Operating
Sink Condition VDD =
AVERAGE
VM
+ BATTERY
LM
BATTERY CURRENT
AVERAGE
It is apparent from this table that the on resistance decreases with increasing supply voltage. Although the minimum currents are now shown on the data sheet for the 15 V case, the maximum on resistance can be no greater than the 10 V example and, therefore, can be assumed for worst case approximation to be 1 and 2.5 kohms for sink-and-source current cases, respectively. The sourcing on resistance is greater than the sinking case because the difference in carrier mobilities of the two channel types. Since rDS(on) for both source and sink conditions varies with supply voltage (VDD), there are certain drive limitations. The relative high rDS(on) of the P-channel transistor could possibly limit the direct thyristor drive capability; and, in a like manner, the N-channel r DS(on) might limit its clamping capability. With a 10 or 15 V supply, the device may be capable of supplying more than 10 mA, but should be limited to that current, with an external limiting resistor, to avoid exceeding the reliable limits of the unit metalization.
RM
DIODE CURRENT
AVERAGE
VM = BACK EMF OF MOTOR LM = MOTOR INDUCTANCE RM = MOTOR RESISTANCE
MOTOR CURRENT
AVERAGE
Figure 6.63. Basic Pulse Width Modulated Motor Speed Control
The circulating current through the diode decreases only in response to motor and diode loss. With reference to Figure 6.63, it can be seen that the circulating diode current causes more average current to flow through the motor than is taken from the battery. However, the power taken from the battery is approximately equal to the power delivered to the motor, indicating that energy is stored in the motor inductance at the battery voltage level and is delivered to the motor at the approximate current level when the battery is disconnected.
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To provide smooth and quiet motor operation, the current variations through the motor should be kept to a minimum during the switching cycle. There are limitations on the amount of energy that can be stored in the motor inductance, which, in turn, limits the power delivered to the motor during the off time; thus the off time must be short. To operate the motor at low speeds, the on time must be approximately 10 percent of the off time and therefore, a rapid switching rate is required that is generally beyond the capabilities of mechanical switches. Practical solutions can be found by the use of semiconductor devices for fast, reliable and efficient switching operations. SCR DC MOTOR CONTROL SCRs offer several advantages over power transistors as semiconductor switches. They require less driver power, are less susceptible to damage by overload currents and can handle more voltage and current. Their disadvantages are that they have a higher power dissipation due to higher voltage drops and the difficulty in commutating to the off condition. The SCR must be turned off by either interrupting the current through the anode-cathode circuit or by forcing current through the SCR in the reverse direction so that the net flow of forward current is below the holding current long enough for the SCR to recover blocking ability. Commutation of the SCR in high current motor control circuits is generally accomplished by discharging a capacitor through the SCR in the reverse direction. The value of this capacitor is determined approximately from the following equation:
Cc q IA + TV c
mately 55 F. In this circuit, SCR3 is gated on at the same time as SCR1 and allows the resonant charging of Cc through Lc to twice the supply voltage. SCR3 is then turned off by the reversal of voltage in the resonant circuit before SCR2 is gated on. It is apparent that there is very little power loss in the charge circuit depending upon the voltage drop across SCR3 and the resistance in Lc.
R1
Cc SCR1 SCR2
TRIGGER CIRCUIT
Figure 6.64. Speed Control with Resistive Charging
Lc SCR3 Cc SCR1 TRIGGER CIRCUIT SCR2
Figure 6.65. Speed Control with Inductive Charging
Where: Cc = Tq = IA = Vc =
value of necessary commutating capacitance turn-off time of the SCR value of anode current before commutation voltage of Cc before commutation
D2
This relationship shows that to reduce the size of Cc, the capacitor should be charged to as high a voltage as possible and the SCR should be selected with as low a turn-off time as possible. If a 20 microsecond turn-off time SCR is commutated by a capacitor charged to 36 volts, it would take over 110 F to turn off 200 amperes in the RC commutating circuit of Figure 6.64. If a 50 cycle switching frequency is desired, the value of R1 would be approximately 5 ohms to allow charging time with an on duty cycle of 10 percent. The value of this resistor would give approximately 260 watts dissipation in the charging circuit with 90 percent off duty cycle. If the resonant charging commutating circuitry of Figure 6.65 is used, the capacitor is reduced to approxi-
D1
TRIGGER CIRCUIT
SCR1
SCR2
Figure 6.66. SCR Motor Control with Transformer Charging
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If the commutating capacitor is to be reduced further, it is necessary to use a transformer to charge the capacitor to more than twice the supply voltage. This type of circuit is illustrated by the transformer charge circuit shown in Figure 6.66. In this circuit the capacitor can be charged to several times the supply voltage by transformer action through diode D1 before commutating SCR1. The disadvantage of this circuit is in the high motor current that flows through the transformer primary winding. HEAVY DUTY MOTOR CONTROL WITH SCRs Another advantage of SCRs is their high surge current capabilities, demonstrated in the motor drive portion of the golf cart controller shown in Figure 6.67. Germanium power transistors were used because of the low saturation voltages and resulting low static power loss. However, since switching speeds are slow and leakage currents are high, additional circuit techniques are required to ensure reliable operation: 1. The faster turn-on time of the SCR (Q9) over that of the germanium transistors shapes the turn-on load line. 2. The parallelled output transistors (Q3-Q8) require a 6 V reverse bias. 3. The driver transistor Q2 obtains reverse bias by means of diode D4.
To obtain the 6 V bias, the 36 V string of 6 V batteries are tapped, as shown in the schematic. Thus, the motor is powered from 30 V and the collector supply for Q2 is 24 V, minimizing the dissipation in colllector load resistor R1. Total switching loss in switchmode applications is the result of the static (on-state) loss, dynamic (switching) loss and leakage current (off-state) loss. The low saturation voltage of germanium transistors produces low static loss. However, switching speeds of the germanium transistors are low and leakage currents are high. Loss due to leakage current can be reduced with off bias, and load line shaping can minimize switching loss. The turn-off switching loss was reduced with a standard snubber network (D5, C1, R2) see Figure 6.67. Turn-on loss was uniquely and substantially reduced by using a parallel connected SCR (across the germanium transistors) the MCR265-4 (55 A rms, 550 A surge). This faster switching device diverts the initial turn-on motor load current from the germanium output transistors, reducing both system turn-on loss and transistor SOA stress. The main point of interest is the power switching portion of the PWM motor controller. Most of the readily available PWM ICs can be used (MC3420, MC34060, TL494, SG1525A, UA78S40, etc.), as they can source at least a 10 mA, +15 V pulse for driving the following power MOSFET.
+ 36 V
OFF BIAS 6 25 W Q3 1N1183 D4 Q2 1 F 0.6 200 W (6) MATCHED Q8 Q9 MCR 265-4 700 F C1 1 R2 + 24 V 1N914 D2 330 (2) D3 1N914 PWM 1k 10 k Q1 MTP12N10E SENSE CURRENT TO PWM 0.001 UTC H51 dc MOTOR 2 HP 1N4744 FORWARD REVERSE D1 + 18 V 1N1183 470 + 15 V 20 50 W R1
+ 30 V
27 + 15 V + 10 F 25 V 0.01 F
D5
Figure 6.67. PWM DC Motor Controller Using SCR Turn-On Feature
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Due to the extremely high input impedance of the power MOSFET, the PWM output can be directly connected to the FET gate, requiring no active interface circuitry. The positive going output of the PWM is power gained and inverted by the TMOS FET Q1 to supply the negative going base drive to PNP transistor Q2. Diode D1 provides off-bias to this paraphase amplifier, the negative going pulse from the emitter furnishing base drive to the six parallel connected output transistors and the positive going collector output pulse supplying the SCR gate trigger coupled through transformer T1. Since the faster turn-on SCR is triggered on first, it will carry the high, initial turn-on motor current. Then the slower turn-on germanium transistors will conduct clamping off the SCR, and carry the full motor current. For the illustrated 2HP motor and semiconductors, a peak exponentially rising and falling SCR current pulse of 120 A lasting for about 60 s was measured. This current is well within the rating of the SCR. Thus, the high turn-on stresses are removed from the transistors providing a much more reliable and efficient motor controller while using only a few additional components. DIRECTION AND SPEED CONTROL FOR MOTORS For a shunt motor, a constant voltage should be applied to the shunt field to maintain constant field flux so that the armature reaction has negligible effect. When constant voltage is applied to the shunt field, the speed is a direct function of the armature voltage and the armature current. If the field is weak, then the armature reaction may counterbalance the voltage drop due to the brushes, windings and armature resistances, with the net result of a rising speed-load characteristic. The speed of a shunt-wound motor can be controlled with a variable resistance in series with the field or the armature. Varying the field current for small motor provides a wide range of speeds with good speed regulation. However, if the field becomes extremely weak, a rising speed-load characteristic results. This method cannot provide control below the design motor speed. Varying the resistance in series with the armature results in speeds less than the designed motor speed; however, this method yields poor speed regulation, especially at low speed settings. This method of control also increases power dissipation and reduces efficiency and the torque since the maximum armature current is reduced. Neither type of resistive speed control is very satisfactory. Thyristor drive controls, on the other hand, provide continuous control through the range of speed desired, do not have the power losses inherent in resistive circuits, and do not compromise the torque characteristics of motors.
Although a series-wound motor can be used with either dc or ac excitation, dc operation provides superior performance. A universal motor is a small series-wound motor designed to operate from either a dc or an ac supply of the same voltage. In the small motors used as universal motors, the winding inductance is not large enough to produce sufficient current through transformer action to create excessive commutation problems. Also, high-resistance brushes are used to aid commutation. The characteristics of a universal motor operated from alternating current closely approximate those obtained for a dc power source up to full load; however, above full load the ac and dc characteristics differ. For a series motor that was not designed as a universal motor, the speed-torque characteristic with ac rather than dc is not as good as that for the universal motor. At eight loads, the speed for ac operation may be greater than for dc since the effective ac field strength is smaller than that obtained on direct current. At any rate, a series motor should not be operated in a no-load condition unless precaution is are taken to limit the maximum speed.
SERIES-WOUND MOTORS
The circuit shown in Figure 6.68 can be used to control the speed and direction of rotation of a series-wound dc motor. Silicon controlled rectifiers Q1- Q4, which are connected in a bridge arrangement, are triggered in diagonal pairs. Which pair is turned on is controlled by switch S1 since it connects either coupling transformer T1 or coupling transformer T2 to a pulsing circuit. The current in the field can be reversed by selecting either SCRs Q2 and Q3 for conduction, or SCRs Q1 and Q4 for conduction. Since the armature current is always in the same direction, the field current reverses in relation to the armature current, thus reversing the direction of rotation of the motor. A pulse circuit is used to drive the SCRs through either transformer T1 or T2. The pulse required to fire the SCR is obtained from the energy stored in capacitor C1. This capacitor charges to the breakdown voltage of zener diode D5 through potentiometer R1 and resistor R2. As the capacitor voltage exceeds the zener voltage, the zener conducts, delivering current to the gate of SCR Q5. This turns Q5 on, which discharges C1 through either T1 or T2 depending on the position of S1. This creates the desired triggering pulse. Once Q5 is on, it remains on for the duration of the half cycle. This clamps the voltage across C1 to the forward voltage drop of Q5. When the supply voltage drops to zero, Q5 turns off, permitting C1 to begin charging when the supply voltage begins to increase.
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D1 AC LINE D3
D2
(4) 1N4722 OR MDA2503
MCR12D Q1
T1
MCR12D Q2
T2
D4 R1 20 k 5W R2, 4.7 k 5W
MCR12D Q3
FIELD
MCR12D Q4
T2 5 F 75 V + D5 1N5262 R3 1k C1 S1 T1 (2) SPRAGUE 11Z13 T2
T1
ARMATURE
Q5 2N5062
Figure 6.68. Direction and Speed Control for Series-Wound or Universal Motor
ac LINE
D1 D3
D2 D4
(4) 1N4722 Q3 Q1
R1 20 k 5W R2, 4.7 k 5W + Q5 2N5062 R3 1k D5 C1 1N5262 T1 T2 T1 Q4 Q2 5 F 75 V FIELD T2 ARMATURE T1
T2
T1 AND T2 ARE SPRAGUE 11Z13 Q1 THRU Q4 MCR12D
Figure 6.69. Direction and Speed Control for Shunt-Wound Motor
The speed of the motor can be controlled by potentiometer R1. The larger the resistance in the circuit, the longer required to charge C1 to the breakdown voltage of zener D5. This determines the conduction angle of either Q1 and Q4, or Q2 and Q3, thus setting the average motor voltage and thereby the speed.
SHUNT-WOUND MOTORS
If a shunt-wound motor is to be used, then the circuit in
Figure 6.69 is required. This circuit operates like the one shown in Figure 6.68. The only differences are that the field is placed across the rectified supply and the armature is placed in the SCR bridge. Thus the field current is unidirectional but armature current is reversible; consequently the motors direction of rotation is reversible. Potentiometer R1 controls the speed as explained previously.
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RESULTS
Excellent results were obtained when these circuits were used to control 1/15 hp, 115 V, 5,000 r/min motors. This circuit will control larger, fractional-horsepower motors provided the motor current requirements are within the semiconductor ratings. Higher current devices will permit control of even larger motors, but the operation of the motor under worst case must not cause anode currents to exceed the ratings of the semiconductor. PUT APPLICATIONS PUTs are negative resistance devices and are often used in relaxation oscillator applications and as triggers for controlling thyristors. Due to their low leakage current, they are useful for high-impedance circuits such as long-duration timers and comparators.
TYPICAL CIRCUITS
With the supply voltage applied to the circuit, the timing capacitor C1 charges to the firing point of the PUT, 2 volts plus a diode drop. The output of the PUT is coupled through two 0.01 F capacitors to the gate of Q2 and Q3. To clarify operation, assume that Q3 is on and capacitor C4 is charged plus to minus as shown in the figure. The next pulse from the PUT oscillator turns Q2 on. This places the voltage on C4 across Q3 which momentarily reverse biases Q3. This reverse voltage turns Q3 off. After discharging, C4 then charges with its polarity reversed to that shown. The next pulse from Q1 turns Q3 on and Q2 off. Note that C4 is a non-polarized capacitor. For the component values shown, the lamp is on for about 1/2 second and off the same amount of time.
R1 10 k + 40 V R2 20 k C1 R3 510 k Q1 MPS6516 RAMP OUT R5 2N6027 100 k R4 100
The following circuits show a few of the many ways in which the PUT can be used. The circuits are not optimized even though performance data is shown. In several of the circuit examples, the versatility of the PUT has been hidden in the design. By this it is meant that in designing the circuit, the circuit designer was able to select a particular intrinsic standoff ratio or he could select a particular RG (gate resistance) that would provide a maximum or minimum valley and peak current. This makes the PUT very versatile and very easy to design with.
LOW VOLTAGE LAMP FLASHER
+ 5 to 20 V
Figure 6.71. (a). Voltage Controlled Ramp Generator (VCRG)

20 19 18 17 16 15 Vin (VOLTS) 14 13 12 11 10 9 8 7 C = 0.0047 F C = 0.01 F
The PUT operates very well at low supply voltages because of its low on-state voltage drop. A circuit using the PUT in a low voltage application is shown in Figure 6.70 where a supply voltage of 3 volts is used. The circuit is a low voltage lamp flasher composed of a relaxation oscillator formed by Q1 and an SCR flip flop formed by Q2 and Q3.
+3V C4 4 F + (SEE TEXT) 0.01 F C3 R7 1k Q3 2N5060 GE NO. 14
R1 100 k Q1 2N6027
R3 1k
R6 51 k
R4 2k C1 10 F R2 910
C2 0.01 F
Q2 2N5060
R5 1k
6 5 1 2 3 4 5 6 7 8 DURATION TIME (ms)
Figure 6.70. Low Voltage Lamp Flasher
(b). Voltage versus Ramp Duration Time of VCRG
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VOLTAGE CONTROLLED RAMP GENERATOR
The PUT provides a simple approach to a voltage controlled ramp generator, VCRG, as shown in Figure 6.71(a). The current source formed by Q1 in conjuction with capacitor C1 set the duration time of the ramp. As the positive dc voltage at the gate is changed, the peak point firing voltage of the PUT is changed which changes the duration time, i.e., increasing the supply voltage increases the peak point firing voltage causing the duration time to increase. Figure 6.71(b) shows a plot of voltage-versus-ramp duration time for a 0.0047 F and a 0.01 F timing capacitor. The figure indicates that it is possible to have a change in frequency of 3 ms and 5.4 ms for the 0.0047 F and the 0.01 F capacitor respectively as the control voltage is varied from 5 to 20 volts.
LOW FREQUENCY DIVIDER
discharged but C2 remains charged to 10 volts. As Q1 turns off this time, C1 and C2 again charge. This time C2 charges to the peak point firing voltage of the PUT causing it to fire. This discharges capacitor C2 and allows capacitor C1 to charge to the line voltage. As soon as C2 discharges and C1 charges, the PUT turns off. The next cycle begins with another positive pulse on the base of Q1 which again discharges C1. The input and output frequency can be approximated by the equation
f in
) C2) fout [ (C1 C1
The circuit shown in Figure 6.72 is a frequency divider with the ratio of capacitors C1 and C2 determining division. With a positive pulse applied to the base of Q1, assume that C1 = C2 and that C1 and C2 are discharged. When Q1 turns off, both C1 and C2 charge to 10 volts each through R3. On the next pulse to the base of Q1, C1 is again
+ 20 Vdc
For a 10 kHz input frequency with an amplitude of 3 volts, Table 6.11 shows the values for C1 and C2 needed to divide by 2 to 11. This division range can be changed by utilizing the programmable aspect of the PUT and changing the voltage on the gate by changing the ratio R6/(R6 + R5). Decreasing the ratio with a given C1 and C2 decreases the division range and increasing the ratio increases the division range. The circuit works very well and is fairly insensitive to the amplitude, pulse width, rise and fall times of the incoming pulses.
Table 6.11
R3 1k
C1
1N4001 D2
Q2 2N6027
R5 5.1 k
8V
C1 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F 0.01 F
C2 0.01 F 0.02 F 0.03 F 0.04 F 0.05 F 0.06 F 0.07 F 0.08 F 0.09 F 0.1 F
Division 2 3 4 5 6 7 8 9 10 11
3V
R1 3.9 k
Q1 MPS6512
D1 1N4001
C2 R4 100 R6 5.1 k
OUT
R2 2.2 k
Figure 6.72. Low Frequency Divider
PUT LONG DURATION TIMER
A long duration timer circuit that can provide a time delay of up to 20 minutes is shown in Figure 6.73. The circuit is a standard relaxation oscillator with a FET current source in which resistor R1 is used to provide reverse bias on the gate-to-source of the JFET. This turns the JFET off and increases the charging time of C1. C1 should be a low leakage capacitor such as a mylar type. The source resistor of the current source can be computed using the following equation:
+ VP (1 * IOIDSS ) N R1 + VIGS O
V GS
where
IO is the current out of the current source. VP is the pinch off voltage, VGS is the voltage gate-to-source and, IDSS is the current, drain-to-source, with the gate shorted to the source.
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The time needed to charge C1 to the peak point firing voltage of Q2 can be approximated by the following equation:
t V, + CD I
For example, the 2N6028 has IP guaranteed to be less than 0.15 A at RG = 1 M Ohm as shown in Figure 6.73.
+ 20 Vdc Q1 2N5457 R1 22 M R3 2M
where
t is time in seconds C is capacitance in F, V is the change in voltage across capacitor C1, and I is the constant current used to charge C1.
C1 10 F MYLAR
Q2 2N6028
Maximum time delay of the circuit is limited by the peak point firing current, lP, needed to fire Q2. For charging currents below IP, there is not enough current available from the current source to fire Q2, causing the circuit to lock up. Thus PUTs are attractive for long duration timing circuits because of their low peak point current. This current becomes very small when RG (the equivalent parallel resistance of R3 and R4) is made large.
PHASE CONTROL
R2 100
OUTPUT
R4 2M
Figure 6.73. 20-Minute, Long Duration Timer
Figure 6.74 shows a circuit using a PUT for phase control of an SCR. The relaxation oscillator formed by Q2 provides conduction control of Q1 from 1 to 7.8 milliseconds or 21.6 to 168.5. This constitutes control of over
97% of the power available to the load. Only one SCR is needed to provide phase control of both the positive and negative portion of the sine wave byputting the SCR across the bridge composed of diodes D1 through D4.
R1
D3 D1 LOAD 100 115 V rms 60 Hz D2 Q1 2N6402 D4
15 k 2 WATT
D5 1N4114 20 V C1 0.1 F
R2 250 k
R3 1k
Q2 2N6027
R4 1k
Figure 6.74. SCR Phase Control
BATTERY CHARGER USING A PUT
A short circuit proof battery charger is shown in Figure 6.75 which will provide an average charging current of about 8 amperes to a 12 volt lead acid storage battery. The charger circuit has an additional advantage in that it will not function nor will it be damaged by improperly connecting the battery to the circuit. With 115 volts at the input, the circuit commences to function when the battery is properly attached. The battery provides the current to charge the timing capacitor C1 used in the PUT relaxation oscillator. When C1 charges to the
peak point voltage of the PUT, the PUT fires turning the SCR on, which in turn applies charging current to the battery. As the battery charges, the battery voltage increases slightly which increases the peak point voltage of the PUT. This means that C1 has to charge to a slightly higher voltage to fire the PUT. The voltage on C1 increases until the zener voltage of D1 is reached which clamps the voltage on C1 and thus prevents the PUT oscillator from oscillating and charging ceases. The maximum battery voltage is set by potentiometer R2 which sets the peak point firing voltage of the PUT.
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In the circuit shown, the charging voltage can be set from 10 V to 14 V, the lower limit being set by D1 and the upper limit by T1. Lower charging voltages can be obtained by reducing the reference voltage (reducing the value of zener diode D1) and limiting the charging current (using either a lower voltage transformer, T1, or adding resistance in
T1 115 V rms 14 V rms
series with the SCR). Resistor R4 is used to prevent the PUT from being destroyed if R2 were turned all the way up. Figure 6.75(b) shows a plot of the charging characteristics of the battery charger.
SCR A R1 10 k 2N6027 PUT D1 1N5240 10 V C1 0.1 F T2 11Z12 1:1 DALE PT50 R3 47 k B R4 1k R2 50 k + 12 V
Figure 6.75. (a). 12-Volt Battery Charger

8 SPECIFIC GRAVITY OF ELECTROLYTE versus TIME 1250 SPECIFIC GRAVITY 7 6 1200 5 4 1150 CHARGING CURRENT versus TIME 3 2 0 1 2 3 4 5 TIME (HR) 6 7 8 9 CURRENT (AMPS)
Figure 6.75 (b) Charging Characteristics of Battery Charger
90 V rms VOLTAGE REGULATOR USING A PUT
The circuit of Figure 6.76 is an open loop rms voltage regulator that will provide 500 watts of power at 90 V rms with good regulation for an input voltage range of 110 130 V rms. With the input voltage applied, capacitor C1 charges until the firing point of Q3 is reached causing it to fire. This turns Q5 on which allows current to flow through the load. As the input voltage increases, the voltage across R10
increases which increases the firing point of Q3. This delays the firing of Q3 because C1 now has to charge to a higher voltage before the peak-point voltage is reached. Thus the output voltage is held fairly constant by delaying the firing of Q5 as the input voltage increases. For a decrease in the input voltage, the reverse occurs. Another means of providing compensation for increased input voltage is achieved by Q2 and the resistive divider formed by R6 and R7. As input voltage increases, the voltage at the base of Q2 increases causing Q2 to turn on harder which decreases the charging rate of C1 and further delays the firing of Q5. To prevent the circuit from latching up at the beginning of each charging cycle, a delay network consisting of Q1 and its associated circuitry is used to prevent the current source from turning on until the trigger voltage has reached a sufficiently high level. This is achieved in the following way: Prior to the conduction of D2, the voltage on the base of Q1 is set by the voltage divider (R4 + R5)/(R1 + R3 + R4 + R5). This causes the base of Q1 to be more positive than the emitter and thus prevents Q1 from conducting until the voltage across R3 is sufficient to forward bias the base-emitter junction of Q1. This occurs when the line voltage has increased to about 15 volts. The circuit can be operated over a different voltage range by changing resistors R6 and/or R4 which change the charging rate of C1.
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Figure 6.76(b) provides a plot of output voltage and conduction angle versus input voltage for the regulator. As
LOAD 500 W 90 V 2 R1 10 k
the figure indicates, good regulation can be obtained between the input voltage range of 110 to 130 volts.
R6 300 k R9 100 k
R2 1k
110-130 V rms
R3 D1 1k R4 10 k
Q1 2N3906 Q2 2N3903
Q3 2N6027 Q5 MCR16M C1 0.1 F 100 V
D2 1N4747 20 V
R5 6.8 k
R7 4.7 k
R8 10 k
R10 6.8 k
Figure 6.76. (a). rms Voltage Regulator
100 OUTPUT VOLTAGE (V rms) 90 80 70 60 50 80 90 CONDUCTION TIME OUTPUT VOLTAGE 100 110 120 130 140 150 INPUT VOLTAGE (V rms) 160
7 6 5 4 3 2 170 CONDUCTION ANGLE (ms)
(b). Output Voltage and Conduction Angle versus Input Voltage
TRIAC ZERO-POINT SWITCH APPLICATIONS

BASIC TRIAC ZERO-POINT SWITCH
Figure 6.77 shows a manually controlled zero-point switch useful in power control for resistive loads. Operation of the circuit is as follows. On the initial part of the positive half cycle, the voltage is changing rapidly from zero causing a large current flow into capacitor C2. The current through C2 flows through R4, D3, and D4 into the gate of the TRIAC Q2 causing it to turn on very close to zero voltage. Once Q2 turns on, capacitor C3 charges to the peak of the line voltage through D5. When the line voltage passes through the peak, D5 becomes reverse-biased and C3 begins to discharge through D4 and the gate of Q2. At
this time the voltage on C3 lags the line voltage. When the line voltage goes through zero there is still some charge on C3 so that when the line voltage starts negative C3 is still discharging into the gate of Q2. Thus Q2 is also turned on near zero on the negative half cycle. This operation continues for each cycle until switch S1 is closed, at which time SCR Q1 is turned on. Q1 shunts the gate current away from Q2 during each positive half cycle keeping Q2 from turning on. Q2 cannot turn on during the negative cycle because C3 cannot charge unless Q2 is on during the positive half cycle. If S1 is initially closed during a positive half cycle, SCR Q1 turns on but circuit operation continues for the rest of the complete cycle and then turns off. If S1 is closed during a negative half cycle, Q1 does not turn on because it is reverse biased. Q1 then turns on at the beginning of the positive half cycle and Q2 turns off. Zero-point switching when S1 is opened is ensured by the characteristic of SCR Q1. If S1 is opened during the positive half cycle, Q1 continues to conduct for the entire half cycle and TRIAC Q2 cannot turn on in the middle of the positive half cycle. Q2 does not turn on during the negative half cycle because C3 was unable to charge during the positive half cycle. Q2 starts to conduct at the first complete positive half cycle. If S1 is opened during the negative half cycle, Q2 again cannot turn on until the beginning of the positive half cycle because C3 is uncharged. A 3-volt gate signal for SCR Q1 is obtained from D1, R1, C1, and D6.
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R3 1.2 k 7W D1 1N4003 R4 150 1W R1 12 k 2W R2 10 k C1 10 F 5V + D6 1N4372 S1
C2 2 F 200 V
+ Q2 2N6346 D4 1N4001 D5 1N4003 + C3 1 F 200 V
D3 1N4003
115 VAC 60 Hz
D2 1N4003 Q1 MCR1906-4 R5 1k 2W
LOAD
Figure 6.77. Zero-Point Switch
AN INTEGRATED CIRCUIT ZERO VOLTAGE SWITCH
A single CA3059/79 integrated circuit operating directly off the ac line provides the same function as the discrete circuit shown in Figure 6.77. Figure 6.78 shows its block diagram. The circuit operates a power triac in quadrants one and four, providing gate pulses synchronized to the
zero voltage point of the ac cycle. This eliminates the RFI resulting from the control of resistive loads like heaters and flashing lamps. Table 6.12 specifies the value of the input series resistor for the operating line voltage. Figure 6.79 shows the pin connection for a typical application.
2 VCC
RS
5 LIMITER AC INPUT 12 DC MODE or 400 Hz INPUT ZERO CROSSING DETECTOR
POWER SUPPLY
VCC CURRENT BOOST RL 3 MT2
AC INPUT 15 V VOLTAGE
100 F +
RP
14
PROTECTION CIRCUIT + ON/OFF SENSING AMP VCC
TRIAC DRIVE
4 GATE
MT1
13 9 * RX
10 11
8 *NTC SENSOR GND 7
1 INHIBIT
6 EXTERNAL TRIGGER
Figure 6.78. Functional Block Diagram
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Table 6.12.
9 10 11 3
RL
AC Input Voltage (50/60 Hz) vac 24 120 208/230 277
Input Series Resistor (RS) k 20 2.0 10 20 25
Dissipation Rating for RS W 05 0.5 20 2.0 40 4.0 5.0
RS 10 k
5
T2800D CA3059
4
120 Vrms 60 Hz
7
8 13 14 2
R2 5k
TEMPERATURE CONTROL WITH ZERO-POINT SWITCHING ZERO VOLTAGE SWITCH PROPORTIONAL BAND TEMPERATURE CONTROLLER
ON OFF
R1 5k + 100 f 15 V
Figure 6.79. Zero Voltage Switch Using CA3059 Integrated Circuit
Figure 6.80 shows the block diagram for the UAA1016B integrated circuit temperature controller. Figure 6.81 shows a typical application circuit. This device drives triacs with a zero voltage full wave technique allowing RFI free power regulation of resistive loads and adjustable burst frequency to comply with standards. It operates directly off the ac line triggers the triac in Q2 and Q3, is sensor fail-safe, and provides proportional temperature control over an adjustable band. Consult the device data sheet (DS9641) for detailed information.
220 VAC
TEMP. SET
R1
R2 3 4 R4 1.0 M
FAIL-SAFE
PULSE AMPLIFIER SAMPLING FULL WAVE LOGIC 6 MAC224-8 7
+ COMPARATOR UAA1016B SAWTOOTH GENERATOR
VREF
1 SYNCHRONIZATION POWER SUPPLY
(NTC) TEMP. SENSOR
LOAD
2 R3 RL 180 k CPin 2 RSYNC
VCC
Design Notes: 1. Let R4
q 5RL + )
220 VAC
2. Select R2 Ratio for a symmetrical reference deviation centered about Pin 1 output swing, R2 will be slightly greater than R3. R3 DVPin 1 3. Select R2 and R3 values for the desired reference deviation where DV REF R4 1 R2 | | R3
Figure 6.80. UA1016B Block Diagram and Pin Assignment
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50 k 6.8 k 22 k 3 4 UAA1016B R4 1 6.8 k RL 47 F 8.0 V RT : NTC R @ 25C = 22 k B = 3700 + 2 8 100 k 5 + 100 F HEATER 2.0 kW 7 MOV MAC224-8 100 220 VAC 6 0.1 F
RT
10%
18 k 2.0 W 1N4005
MOV: 250 VAC VARISTOR
Figure 6.81. Application Circuit Electric Radiator with Proportional Band Thermostat, Proportional Band 1C at 25C
TRIAC RELAY-CONTACT PROTECTION
A common problem in contact switching high current is arcing which causes erosion of the contacts. A solution to this problem is illustrated in Figure 6.82. This circuit can be used to prevent relay contact arcing for loads up to 50 amperes. There is some delay between the time a relay coil is energized and the time the contacts close. There is also a delay between the time the coil is de-energized and the time the contacts open. For the relay used in this circuit both times are about 15 ms. The TRIAC across the relay contacts will turn on as soon as sufficient gate current is present to fire it. This occurs after switch S1 is closed but before the relay contacts close. When the contacts close, the load current passes through them, rather than through the TRIAC, even though the TRIAC is receiving gate current. If S1 should be closed during the negative half cycle of the ac line, the TRIAC will not turn on immediately but will wait until the voltage begins to go positive, at which time diode D1 conducts providing gate current through R1. The maximum time that could elapse before the TRIAC turns on is 8-1/3 ms for the 60 Hz supply. This is adequate to ensure that the TRIAC will be on before the relay contact closes. During the positive half cycle, capacitor C1 is charged through D1 and R2. This stores energy in the capacitor so that it can be used to keep
the TRIAC on after switch S1 has been opened. The time constant of R1 plus R2 and C1 is set so that sufficient gate current is present at the time of relay drop-out after the opening of S1, to assure that the TRIAC will still be on. For the relay used, this time is 15 ms. The TRIAC therefore limits the maximum voltage, across the relay contacts upon dropout to the TRIACs voltage drop of about 1 volt. The TRIAC will conduct until its gate current falls below the threshold level, after which it will turn off when the anode current goes to zero. The TRIAC will conduct for several cycles after the relay contacts open. This circuit not only reduces contact bounce and arcing but also reduces the physical size of the relay. Since the relay is not required to interrupt the load current, its rating can be based on two factors: the first is the rms rating of the current-carrying metal, and the second is the contact area. This means that many well-designed 5 ampere relays can be used in a 50 ampere load circuit. Because the size of the relay has been reduced, so will the noise on closing. Another advantage of this circuit is that the life of the relay will be increased since it will not be subjected to contact burning, welding, etc. The RC circuit shown across the contact and TRIAC (R3 and C2) is to reduce dv/dt if any other switching element is used in the line.
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R3 47 50 AMP LOAD S1 R1 1.5 k 10 W R2 10 10 W C1 20 F 250 V C2 0.1 F MAC210A8
AN AUTOMATIC AC LINE VOLTAGE SELECTOR USING THE MC34161 AND A TRIAC
115 VAC 60 Hz
115 V RELAY WITH PICKUP AND DROP-OUT TIMES OF 10-20 ms D1 1N4004
Line operated switching regulators run off of 120 or 240 VAC by configuring the main reservoir input capacitor filter as a full-wave doubler or full-wave bridge. This integrated circuit provides the control signals and triggering for a TRIAC to automatically provide this function. Channel 1 senses the negative half cycles of the AC line voltage. If the line voltage is less than 150 V, the circuit will switch from bridge mode to voltage doubling mode after a preset time delay. The delay is controlled by the 100 k resistor and the 10 F capacitor. If the line voltage is greater than 150 V, the circuit will immediately return to fullwave bridge mode.
Figure 6.82. TRIAC Prevents Relay Contact Arcing
B+ MAC + 228A6FP T INPUT 92 TO 276 VAC MR506 8 3.0 A 1 10 k 7 2 + 100 k 1.6 M 3 + 1N 4742 10 k 3W + 47 4 10 + + 1.27 V + + 1.27 V + 2.54 V REFERENCE + 2.8 V 6 10 k + 220 250 V 75 k RTN 220 250 V 75 k
1.2 k
+ 0.6 V 5
Figure 6.83. Automatic AC Line Voltage Selector
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Series Triacs In AC High Voltage Switching Circuits

By George Templeton Thyristor Applications Engineer http://onsemi.com
APPLICATION NOTE
INTRODUCTION
Edited and Updated
This paper describes the series connection of triacs to create a high voltage switch suitable for operation at voltages up to 2000 Volts. They can replace electromechanical contactors or extend their current rating and lifetime. Motor starters and controllers operating at line voltages of 240 Volts or more require high-voltage switches. Transformer action and resonant snubber charging result in voltages much greater than the peak of the line. Triacs can be subjected to both commutating and static dV/dt when multiple switching devices are present in the circuit. Snubber designs to prevent static dV/dt turn-on result in higher voltages at turn-off. Variable load impedances also raise voltage requirements. The benefits of series operation include: higher blocking voltage, reduced leakage, better thermal stability, higher dV/dt capability, reduced snubber costs, possible snubberless operation, and greater latitude in snubber design. The advantages of triacs as replacements for relays include: Small size and light weight Safety freedom from arcing and spark initiated explosions Long lifespan contact bounce and burning eliminated Fast operation turn-on in microseconds and turn-off in milliseconds Quiet operation Triacs can be used to replace the centrifugal switch in capacitor start motors. The blocking voltage required of the triac can be much greater than the line voltage would suggest. It must block the vector sum of the line, auxiliary
winding, and start capacitor voltage. This voltage increases when triac turn-off occurs at higher rpm. TRIGGERING Figure 1 illustrates a series thyristor switching circuit. In this circuit, the top triac triggers in Quadrant 1 when the bottom triac triggers in Quadrant 3. When the optocoupler turns on, gate current flows until the triacs latch. At that time, the voltage between the gate terminals drops to about 0.6 Volts stopping the gate current. This process repeats each half cycle. The power rating of the gate resistor can be small because of the short duration of the gate current. Optocoupler surge or triac gate ratings determine the minimum resistance value. For example, when the maximum optocoupler ITSM rating is 1 A:
Rg Rg
u+ VpeakImax + 750 V1 A + 750 Ohm
(1.0)
The triacs retrigger every half cycle as soon as the line voltage rises to the value necessary to force the trigger current. The instantaneous line voltage V is
V
+ IGT Rg ) 2 VGT ) 2 VTM
(1.1)
where VGT, IGT are data book specifications for the triac and VTM is the on-voltage specification for the optocoupler. The phase delay angle is
qd
+ SIN*1 2

V V LINE
(1.2)
Semiconductor Components Industries, LLC, 1999
148
August, 1999 Rev. 2
Publication Order Number: AN1045/D
AN1045/D
IG RG IL G MT1 MT2 I 6 3 MT2 MT1 PROCESS WIDTH 3 MEAN DESIGN CAPABILITY 6
Figure 6.1. Series Switch
Figure 6.2. Designing for Probable Leakage
STATIC VOLTAGE SHARING Maximum blocking voltage capability results when the triacs share voltage equally. The blocking voltage can be dc or ac. A combination of both results when the triac switches the start winding in capacitor start motors. In the simple series connection, both triacs operate with an identical leakage current which is less than that of either part operated alone at the same voltage. The voltages across the devices are the same only when their leakage resistances are identical. Dividing the voltage by the leakage current gives the leakage resistance. It can range from 200 kohm to 2000 megohm depending on device characteristics, temperature, and applied voltage. Drawing a line corresponding to the measured series leakage on each devices characteristic curve locates its operating point. Figure 3a shows the highest and lowest leakage units from a sample of 100 units. At room temperature, a leakage of 350 nA results at 920 Volts. The lowest leakage unit blocks at the maximum specified value of 600 Volts, while the highest blocks 320 Volts. A 50 percent boost results. Figure 3b shows the same two triacs at rated TJmax. The magnitude of their leakage increased by a factor of about 1000. Matching between the devices improved, allowing operation to 1100 Volts without exceeding the 600 Volt rating of either device. Identical case temperatures are necessary to achieve good matching. Mounting the devices closely together on a common heatsink helps. A stable blocking condition for operation of a single triac with no other components on the heatsink results when
dI MT dT J
turn leads to greater leakage. If the rate of heat release at the junction exceeds the rate of removal as temperature increases, this process repeats until the leakage current is sufficient to trigger the thyristor on. DC blocking simplifies analysis. A design providing stable dc operation guarantees ac performance. AC operation allows smaller heatsinks. The last term in the stability equation is the applied voltage when the load resistance is low and the leakage causes negligible voltage drop across it. The second term is the thermal resistance from junction to ambient. The first term describes the behavior of leakage at the operating conditions. For example, if leakage doubles every 10C, a triac operating with 2 mA of leakage at 800 Vdc with a 6C/W thermal resistance is stable because
2 mA 10C
@ @
6C W
800 V
+ 0.96
@ @
dT J dP J
dP J dI MT
t1
(2.0)
Thermal run-away is a regenerative process which occurs whenever the loop gain in the thermal feedback circuit reaches unity. An increase in junction temperature causes increased leakage current and higher power dissipation. Higher power causes higher junction temperature which in
Operating two triacs in series improves thermal stability. When two devices have matched leakages, each device sees half the voltage and current or 1/4 of the power in a single triac. The total leakage dissipation will approach half that of a single device operated at the same voltage. The additional voltage margin resulting from the higher total blocking voltage reduces the chance that either device will operate near its breakdown voltage where the leakage current increases rapidly with small increments in voltage. Higher voltage devices have lower leakage currents when operated near breakdown. Consequently, the highest breakover voltage unit in the pair will carry the greatest proportion of the burden. If the leakage current is large enough to cause significant changes in junction temperature, (TJ = JC PD), the effect will tend to balance the voltage division between the two by lowering the leakage resistance of the hotter unit. If the leakage mismatch between the two is large, nearly all the voltage will drop across one device. As a result there will be little benefit connecting two in series. Series blocking voltage depends on leakage matching. Blocking stability depends on predictable changes in leakage with temperature. Leakage has three components.
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HIGH
LOW IL
LOW HIGH 25C 100 A/ 125C
(a)
100 V/
100 nA/
(b)
100 V/
Figure 6.3. Leakage Matching versus Temperature
Surface Leakage
Passivation technique, junction design, and cleanliness determine the size of this component. It tends to be small and not very dependent on temperature.
Diffusion Leakage
Measurements with 1 volt reverse bias show that this component is less than 10 percent of the total leakage for allowed junction temperatures. It follows an equation of the form:
I
from 70 to 150C. Actual values measured 0.064 at 125 and 0.057 at 150. Deviations from this behavior will result at voltages and temperatures where leakage magnitude, current gain, and avalanche multiplication aid unwanted turn-on. Sensitive gate triacs are not recommended for this reason. DERATING AND LEAKAGE MATCHING Operation near breakdown increases leakage mismatch because of the effects of avalanche multiplication. For series operation, devices should be operated at least 100 Volts below their rating.
20 18 PERCENT (SAMPLE SIZE = 100) 16 14 12 10 8 6 4 2 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 650 V 550 V TJ = 25C
and doubles about every 10C. Its value can be estimated by extrapolating backward from high temperature data points.
Depletion Layer Charge Generation
T e*(qvkT)
(2.1)
This component is a result of carriers liberated from within the blocking junction depletion layer. It grows with the square root of the applied voltage. The slope of the leakage versus applied voltage is the mechanism allowing for series operation with less than perfect leakage matching. Predictable diffusion processes determine this leakage. At temperatures between 70 and 150C it is given by:
i E T e * kT (2.2)
where E = 1.1 eV, k = 8.62E 5 eV/k, T = degrees Kelvin, and k = 8.62 x 10 5 eV/k. It is useful to calculate the percentage change in leakage current with temperature:
A
Figure 6.4. Normalized Leakage (Mean = 1.0)
1 di i dT J
E + 0.08 + 8% + kT 2 C
The coefficient A was evaluated on 3 different die size triacs by curve fitting to leakage measurements every 10
Figure 4 shows the leakage histogram for a triac sample operated at two different voltages. The skewedness in the high-voltage distribution is a consequence of some of the sample operating near breakdown.
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HEATSINK SELECTION Solving equations (2.0) and (2.3) for the thermal resistance required to prevent runaway gives:
JA
t A 1V i
where JA is thermal resistance, junction to ambient, in C/W, A = 0.08 at TJ = 125C, V = rated VDRM, and i = rated IDRM. JA must be low enough to remove the heat resulting from conduction losses and insure blocking stability. The latter can be the limiting factor when circuit voltages are high. For example, consider a triac operated at 8 amps (rms) and 8 Watts. The allowed case temperature rise at 25 ambient is 85C giving a required CA (thermal resistance, case to ambient) of 10.6C/W. Allowing 1C/W for CHS (thermal resistance, case to heatsink) leaves 9.6C/W for SA (thermal resistance, heatsink to ambient). However, thermal stability at 600 V and 2 mA IDRM requires JA = 10.4C/W. A heatsink with SA less than 7.4C/W is needed, given a junction to case thermal resistance of 2C/W. The operation of devices in series does not change the coefficient A. When matching and thermal tracking is perfect, both devices block half the voltage. The leakage current and power divide by half and the allowed JA for blocking stability increases by 4.
@@
(3.0)
Low duty cycles allow the reduction of the heatsink size. The thermal capacitance of the heatsink keeps the junction temperature within specification. The package time constant (Cpkg RJA) is long in comparison with the thermal response time of the die, causing the instantaneous TJ to rise above the case as it would were the semiconductor mounted on an infinite heatsink. Heatsink design requires estimation of the peak case temperature and the use of the thermal derating curves on the data sheet. The simplest model applies to a very small heatsink which could be the semicondutor package itself. When SA is large in comparison with CHS, it is sufficient to lump both the package and heatsink capacitances together and treat them as a single quantity. The models provide good results when the heatsink is small and the thermal paths are short. Model C, Figure 5 is a useful simplification for low duty cycle applications. Increasing heatsink mass adds thermal capacitance and reduces peak junction temperature. Heatsink thermal resistance is proportional to surface area and determines the average temperature.
qSA
+ 32.6 A(*0.47)
(3.1)
where A = total surface area in square inches, SA = thermal resistance sink to ambient in C/W. Analysis of heatsink thermal response to a train of periodic pulses can be treated using the methods in ON Semiconductor application note AN569 and Figure 6. For example:
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CA
Pd ton
CPKG
CA TC
Pd CA
CPKG TC
TA
TA
(a.) Standard Thermal Analogue For a Thyristor in Free Air

In Circuit (B): The steady state case temperature is given by (5.0) T CSS P d q CA T A in C where Pd = Applied average power, watts CA = Case to ambient thermal resistance, C/W TA = ambient temperature, C The package rises toward the steady state temperature exponentially with time constant (5.1)
(b.) Equivalent Circuit For (a)

In terms of measurable temperatures: DTCpk (5.3) r(t on) DTCSS
In model (b.) this is (5.4) r(t on)
+ (1 * e*tont)
t on + (CA In*(1 * r(ton))
Solving 5-4 for the package capacitance gives (5.5) C PKG
t + qCA
C PKG, seconds
where Cpkg = HM, Joules/C H = Specific heat, calories/(gm S C) M = Mass in grams and 1 Calorie = 4.184 Joule 1 Joule = 1 Watt S Sec The case temperature rise above ambient at the end of power pulse is: (5.2) where
Use simplified model C when t on DTC
tt t tt DTCSS pk
* TA pk DTCSS + TCSS * TA
TC
DTC pk +
DTCpk + DTCSS(1 * e*tont)
Pd
CPKG
TC
To account for thermal capacity, a time dependent factor r(t) is applied to the steady state case-to-ambient thermal resistance. The package thermal resistance, at a given on-time, is called transient thermal resistance and is given by: R qCA (t on)
TA
+ r(ton) qCA
(c.) Simplified Model

(5.6) T C d t on +P ) TA C PKG
where r(ton) = Unitless transient thermal impedance coefficient.
Figure 6.5. Transient Thermal Response For a Single Power Pulse
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AN1045/D
Assume the case temperature changes by 40C for a single power pulse of 66.67 W and 3 s duration. Then from equation (5.6):
C pkg (3 seconds) + (66.7 Watts) + 5 Joules 40C C
+ (1 * e*180150) + .6988 R (t on ) Tp) + (1 * 1 *183150) + .7047

R (T p)
The heatsink thermal resistance can be determined by applying dc power, measuring the final case temperature, and using equation (5.0).
TC PD
Then from Figure 6: delta TC = (1.111 + 46.225 + 1.333 46.61) 30 = 61.8C If the ambient temperature is 25C, TC = 87C. COMPENSATING FOR MAXIMUM SPECIFIED LEAKAGE Identical value parallel resistors around each triac will prevent breakdown resulting from mismatched leakages. Figure 7 derives the method for selecting the maximum allowed resistor size. A worst case design assumes that the series pair will operate at maximum TJ and that one of the triacs leaks at the full specified value while the other has no leakage at all. A conservative design results when the tolerances in the shunt resistors place the highest possible resistor across the low leakage unit and the lowest possible resistor around the high leakage unit. This method does not necessarily provide equal voltage balancing. It prevents triac breakover. Perfect voltage sharing requires expensive high-wattage resistors to provide large bleeder currents.
* TA + 175-25 + 30CW
5
The application requires a 3 s on-time and 180 s period at 66.7 W. Then

P avg
+ (66.7 W) (3180) + 1.111 W

N+1 PULSE Pd ton
Nth PULSE
tp PAVG
DTC
* Pd r (tp)]qCA
(N
) 1) + [PAVG ) (Pd * PAVG) r (ton ) tp) ) Pd r (ton)

VS
IDRM (T2)
T2 IL
I2 R2
Where TC (N + 1) = maximum rise above ambient Pd = applied average power within a pulse PAV G = average power within a period r(ton + tp) = time dependent factor for sum of ton and tp r(ton) = time dependent factor for ton r(tp) = time dependent factor for tp V1
IDRM (T1) R1 T1
I1 V1
DILR1R2 SR 1 + RV ) ) R 1 2 R1 ) R2
Figure 6.6. Steady State Peak Case Temperature Rise
Let R1 = R (1 + p) and R2 = R (1 p) where R = Nominal resistor value p = 0.05 for 5% tolerance, etc. R
Using equation (5.3), the theoretical steady state case temperature rise is:
T CSS
* TA + (66.7 W) (30CW) + 2000C
L Worst case becomes: and
* VS (1 ) p) x 2 VDRM DI (1 * p2)
and
R(t on)
+ R (3 s) + (40C measured rise)2000 + 0.02
IDRM (T1) = 0; IDRM (T2) = Spec. max. value IL = Spec. Max. Value
From equation (5.4) and (5.1):
Figure 6.7. Maximum Allowed Resistor for Static Voltage Sharing
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COMPENSATION FOR PROBABLE LEAKAGE Real triacs have a leakage current greater than zero and less than the specified value. Knowledge of the leakage distribution can be used to reduce resistor power requirements. The first step is to statistically characterize the product at maximum temperature. Careful control of the temperature is critical because leakage depends strongly on it. The process width is the leakage span at plus or minus 3 standard deviations (sigma) from the mean. To minimize the probability of out of spec parts, use a design capability index (Cp) of 2.0.
Cp
Theoretically there would be no more than 3.4 triacs per million exceeding the design tolerance even if the mean value of the leakage shifted by plus or minus 1.5 sigma. SELECTING RESISTORS Small resistors have low voltage ratings which can impose a lower constraint on maximum voltage than the triac. A common voltage rating for carbon resistors is: Rated Power (W) 1/4 Watt 1/2 1 2 Maximum Voltage (V) 250 Volts 350 500 750
+ (design DI)(process width) Cp + (12 sigma)(6 sigma)
(4.0)
Figure 2 and Figure 7 describe this. Substituting delta IL at 6 sigma in Figure 7 gives the resistor value. The required power drops by about 4.
Series resistors are used for higher voltage.
I Rmin E Rmax IDRM
ACTUAL TRIAC Let V DRM MODEL TRIAC E
R max + E Rmax ) Rmin 1 min ) IImax R min
+ VDRM
R max VMT2 1 VDRM
+ VIDRM min
+ VIDRM max
(8.0)
(a) Equivalent Circuit
(b) Model
Figure 6.8. Maximum Voltage Sharing Without Shunt Resistor
OPERATION WITHOUT RESISTORS Figure 8 derives the method for calculating maximum operating voltage. The voltage boost depends on the values of Imin and Imax. For example :
Table 1. Normalized leakage and voltage boost factor. (Mean = 1.0)

Voltage (V) TJ (C) Rshunt 550 25 100 1.31 5 0.72 9 0.116 1.55 1.18 650 25 100 1.59 1 0.68 1 0.17 2 1.43 1.00 550 100 16 1.18 7 0.84 0 0.10 6 1.71 1.22 550 125 16 1.22 8 0.83 5 0.113 1.68 1.19 550 125 1.5M 16 1.12 3 0.92 0 0.05 5 1.82 1.50 550 150 1.5M 16 1.34 6 0.82 0 0.13 2 1.61 1.12 550 150 510K 16 1.18 6 0.87 7 0.08 4 1.74 1.33
) +
1 131 mA 683 mA
1.19
Sample Size Maximum Minimum Sigma Sample Boost 6 Sigma Boost
A 19 percent voltage boost is possible with the 6 sigma design. Testing to the measured maximum and minimum of the sample allows the boost to approach the values given in Table 1.
(1
) 0.8351.228) + 1.68
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COMPENSATING FOR SURFACE LEAKAGE A small low power shunt resistance will provide nearly perfect low temperature voltage sharing and will improve high temperature performance. It defines the minimum leakage current of the parallel triac-resistor combination. The design method in Figure 8 can be used by adding the resistor current to the measured maximum and minimum leakage currents of the triac sample. This is described in Table 1. SERIES dV dt s The series connection will provide twice the Triacs can tolerate very high rates of voltage rise when the peak voltage magnitude is below the threshold needed to trigger the device on. This behavior is a consequence of the voltage divider action between the device collector and gate-cathode junction capacitances. If the rise-time is made short in comparison with minority carrier lifetime, voltage and displaced charge determine whether the device triggers on or not. Series operation will extend the range of voltage and load conditions where a static dV snubber is not
dt
capability of the lowest device in the pair (Figure 9). Dynamic matching without a snubber network depends on equality of the thyristor self capacitance. There is little variation in junction capacitance. Device gain variations introduce most of the spread in triac performance. The blocking junction capacitance of a thyristor is a declining function of dc bias voltage. Mismatch in static blocking voltage will contribute to unequal capacitances. However, this effect is small at voltages beyond a few volts. The attachment of a heatsink at the high-impedance node formed by connection of the triac main-terminals can also contribute to imbalance by introducing stray capacitance to ground. This can be made insignificant by adding small capacitors in parallel with the triacs. Snubbers will serve the same purpose.
dV dt s
needed. Figure 10 graphs the results of measurements on two series connected triacs operated without snubbers. The series connection doubled the allowed step voltage. However, this voltage remained far below the combined 1200 V breakover voltage of the pair.
800 MAXIMUM STEP VOLTAGE (V) 700 600 500 400 V 300 200 100 0 0 20 40 60 dV 10 kV ms dt f = 10 Hz pw = 100 s 80 TJ (C) 100 120 140 160
10,000 9 8 7 6 5 4 EXPONENTIAL STATIC dv/dtS (V/ s) 3 2 2 1000 9 8 7 6 5 4 3 2 R 1 R = 270 k C = 1000 pF Vpk = 1000 V C 1 R C
Figure 6.10. Step Blocking Voltage VS TJ (Unsnubbed Series Triacs)
Exponential dV
than 2 kV/s showed that turn-on of the series pair can occur because of breakdown or dV . The former was the limiting factor at junction temperatures below 100C. Performance improved with temperature because device gain aided voltage sharing. The triac with the highest current gain in the pair is most likely to turn-on. However, this device has the largest effective capacitance. Consequently it is exposed to less voltage and dV . At higher temperadt dt
dt s
tests performed at 1000 V and less
tures, rate effects dominated over voltage magnitudes, and the capability of the series pair fell. dV performance of the
dt
series devices was always better than that of a single triac alone.
0 15 30 45 60 75 90 105 120 135 150
100
TURNOFF Process tolerances cause small variations in triac turn-off time. Series operation will allow most of the reapplied blocking voltage to appear across the faster triac when a dynamic voltage sharing network is not used.
JUNCTION TEMPERATURE (TJ) C
Figure 6.9. Exponential Static dV/dt, Series MAC15-8 Triacs
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Figure 11 describes the circuit used to investigate this behavior. It is a capacitor discharge circuit with the load series resonant at 60 Hz. This method of testing is desirable because of the reduced burn and shock hazard resulting from the limited energy storage in the load capacitor. The triacs were mounted on a temperature controlled hotplate. The single pulse non-repetitive test aids junction temperature control and allows the use of lower power rated components in the snubber and load circuit.
15K 13K S1 11 2W S1 G2 15K 2W 2W 510
CL MT1, T2 910 G2
PEARSON 301X 1 PROBE MT1 MT2 T2 270K 2W
CL
Rs Cs
LL S2 Hg RELAY
S4A + 100 V 910 1/2W G1 PUSH TO TEST S4B
MOC3081
G2 2.2 Meg
MT2 1N4001 MOC3081 2.2 Meg G1 510 G1 MT1 T1 270K 2W
Cs S3 Rs CL
20 F 200 V
(a) Triac Gate Circuit
MT1, T1 S1 = GORDES MR988 REED WOUND WITH 1 LAYER AWG #18 LL = 320 MHY CL = 24 FD, NON-POLAR REVERSE S4 AND VCC TO CHECK OPPOSITE POLARITY.
(c) Load Circuit
(b) Optocoupler Gate Circuit Figure 6.11. dV cTest Circuit
dt
Snubberless turn-off at 1200 V and 320 milli-henry resulted in 800 V peak and 100 V/s. Although this test exceeded the ratings of the triacs, they turned off successfully. Snubberless operation is allowable when: 1. The total transient voltage across both triacs does not exceed the rating for a single device. This voltage depends on the load phase angle, self capacitance of the load and triac, damping constant, and natural resonance of the circuit. 2. The total dV across the series combination does
dt c
suggest that the reverse recovery charge is less than 2 micro-coulombs. Recovery currents cannot be much greater than IH or IGT, or the triac would never turn-off. Recovery can be forward, reverse, or near zero current depending on conditions. Snubber design for the series switch has the following objectives: Controlling the voltage peak. Resonant charging will magnify the turn-off voltage. Controlling the voltage rate. Peak voltage trades with voltage rate. Equalizing the voltage across the series devices by providing for imbalance in turn-off charge. Designs that satisfy the first two objectives will usually provide capacitor values above the minimum size. Select the snubber for a satisfactory compromise between voltage and dV . Then check the capacitor to insure that it is suffidt
not exceed the capability of a single device. Maximum turn-off voltage capability and tolerance for variable loads requires the use of a snubber network to provide equal dynamic voltage sharing. Figure 12 and Figure 13 derives the minimum size snubber capacitor allowed. It is determined by the recovery charge of the triac. Measurements in fast current crossing applications
ciently large.
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TRIAD C30X 50H, 3500 VCC 1.5 kV
AN1045/D
VMT2-1 AND IMT2 V2 Q2 VDRM Q IRRM VMT2-1
C2 T2 VS T1 Q+ Q Q Q
+ 0;
dl CAPABILITY dt The hazard of thyristor damage by dl overstress is

dt
dI dt c t (dv/dt)c
greater when circuit operating voltages are high because dl
dt
C1 Q 1
Worst case: C2
+ C(1 ) p);
C1
+ C(1 * p);
Q1
Q2
+ DQ
is proportional to voltage. Damage by short duration transients is possible even though the pulse is undetectable when observed with non-storage oscilloscopes. This type of damage can be consequence of snubber design, transients, or parasitic capacitances. A thyristor can be triggered on by gate current, exceeding its breakdown voltage, or by exceeding its dV
where C = Nominal value of capacitor and p = 0.1 for 10% tolerance, etc. Q = Reverse recovery charge Note that T1 has no charge while T2 carries full recovery charge. 1 Q2 1 1 * DQ +Q ) + C(1Q* )Q C1 C2 p) C(1 ) p) DQ Cy 2 V DRM * V S(1 ) p) VS For the model shown above,
ty. In the latter case, a trigger current is generated by charging of the internal depletion layer capacitance in the device. This effect aids turn-on current spreading, although damage can still occur if the rate of follow on dl is high. Repetidt
dt s
capabili-
Figure 6.12. Minimum Capacitor Size for Dynamic Voltage Sharing
tive operation off the ac line at voltages above breakdown is a worst case condition. Quadrant 3 has a slightly slower gated turn-on time, increasing the chance of damage in this direction. Higher operating voltages raise power density and local heating, increasing the possibility of die damage due to hot-spots and thermal run-away.
Snubber designs for static, commutating, and combined dV

dt
stress are shown in Table 2. Circuits switching the line or a charged capacitor across a blocking triac require the addition of a series snubber inductor. The snubber must be designed for maximum dV with the minimum circuit inductance. This
dt
RE1 5K 200W 06 kV 1/2A 60 Hz
R NON-INDUCTIVE
T106-6 L MT1 *S1 G 1K 2W CARBON
contraint increases the required triac blocking voltage.

Table 2. Snubber Designs
Type L (mh) RL Ohm Rs Ohm Cs (f) Damping Ratio Vstep (V) Vpk (V) tpk (s) dV dt c 320 8 1820 0.5 1.14 1200 1332 768 4.6
MT2 MT2
QTY = 6 TO 16 MKP1V130
0.4 0 48 0.5 0.85 1200 1400 29.8 103
C G Both 320 8 48 0.5 .035 750 1423 1230 1.3 Vci V 1000 1900* 1500 C FD 4.06 1.05 0.002 L HY 3.4 7.9 0.3 R 5.7 5.7 10 dl/dt A/s 100 179 3000 Rejects Tested 0/100 0/195 3/10 MT1 PEARSON 411 I PROBE
dV dt s
dV (V/s) dt
* Open S1 to test breakover dl/dt
Note: Divide Rs and dV by 2, multiply Cs by 2 for each triac. dt
Figure 6.13. dl/dt Test Circuit
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AN1045/D
Ideally, turn-on speed mismatch should not be allowed to force the slower thyristor into breakdown. An RC snubber across each thyristor prevents this. In the worst case, one device turns on instantly while the other switches at the slowest possible turn-on time. The rate of voltage rise at the slower device is roughly dV
IR s , where VI is the maxi+ V2L dt
turn-on. Alternatively, a large triac capable of surviving the surge can be used.
T2 Q
IH1 IH2
lpk Q
mum voltage across L. This rate should not allow the voltage to exceed VDRM in less than Tgt to prevent breakover. But what if the thyristors are operated without a snubber, or if avalanche occurs because of a transient overvoltage condition? The circuit in Figure 13 was constructed to investigate this behavior. The capacitor, resistor, and inductor create a pulse forming network to shape the current wave. The initial voltage on the capacitor was set by a series string of sidac bidirectional breakover devices. Test results showed that operation of the triac switch was safe as long as the rate of current rise was below 200 A/s. This was true even when the devices turned on because of breakover. However, a 0.002 f capacitor with no series limiting impedance was sufficient to cause damage in the Q3 firing polarity. Circuit malfunctions because of breakover will be temporary if the triac is not damaged. Test results suggest that there will be no damage when the series inductance is sufficient to hold dl/dt to acceptable values. Highly energetic transients such as those resulting from lightning strikes can cause damage to the thyristor by I2t surge overstress. Device survival requires the use of voltage limiting devices in the circuit and dV limiting snubbers to prevent unwanted
dt
T1
t = 0
t1
t2
DQ
for turn-off at I
t2
DQ +
I H1
+ Ipk Sinwt1 I H1 thus t 1 + 1 Sin *1 w I pk Worst case : I H2 + 0; f 2 + wt 2 + p

DQ + w DQ + w
I pk
t1
I pk SINwt dt
+ pk w (cos wt1 * cos wt2)

I
I pk
)
1
(1
) cos[SIN*1 IIH1 ]) pk
I

*
I H1 I pk 2
Figure 6.14. Forward Recovery Charge for Turn-Off at lH
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RC Snubber Networks For Thyristor Power Control and Transient Suppression

By George Templeton Thyristor Applications Engineer http://onsemi.com
APPLICATION NOTE
INTRODUCTION
Edited and Updated
RC networks are used to control voltage transients that could falsely turn-on a thyristor. These networks are called snubbers. The simple snubber consists of a series resistor and capacitor placed around the thyristor. These components along with the load inductance form a series CRL circuit. Snubber theory follows from the solution of the circuits differential equation. Many RC combinations are capable of providing acceptable performance. However, improperly used snubbers can cause unreliable circuit operation and damage to the semiconductor device. Both turn-on and turn-off protection may be necessary for reliability. Sometimes the thyristor must function with a range of load values. The type of thyristors used, circuit configuration, and load characteristics are influential. Snubber design involves compromises. They include cost, voltage rate, peak voltage, and turn-on stress. Practical solutions depend on device and circuit physics. STATIC dV dt
WHAT IS STATIC dV ? dt dV Static is a measure of the ability of a thyristor to dt
dV DEVICE PHYSICS dt s
Static dV turn-on is a consequence of the Miller effect

dt
and regeneration (Figure 1). A change in voltage across the junction capacitance induces a current through it. This current is proportional to the rate of voltage change dV . It
dt
triggers the device on when it becomes large enough to raise the sum of the NPN and PNP transistor alphas to unity.
A A IB P I1 IC N NPN CJ P CJ N IJ IB N IK K TWO TRANSISTOR MODEL OF SCR IA IA PNP IC IJ P I2 G dV dt (aN CJ V PE NB dv dt CJ G t NE PB C
+1*
CJ
) ap)
CEFF
+ 1*(aN)ap)
K INTEGRATED STRUCTURE
retain a blocking state under the influence of a voltage transient.
Figure 6.1.
dV Model dt s
159
August, 1999 Rev. 2
Publication Order Number: AN1048/D
AN1048/D
CONDITIONS INFLUENCING dV dt s
170 150 130 STATIC dV (V/ s) dt 110 90 70 50 30 10 25 40 55 70 85 100 115 130 145 MAC 228A10 VPK = 800 V
Transients occurring at line crossing or when there is no initial voltage across the thyristor are worst case. The collector junction capacitance is greatest then because the depletion layer widens at higher voltage. Small transients are incapable of charging the selfcapacitance of the gate layer to its forward biased threshold voltage (Figure 2). Capacitance voltage divider action between the collector and gate-cathode junctions and builtin resistors that shunt current away from the cathode emitter are responsible for this effect.
180 160 140 STATIC dV (V/ s) dt 120 100 80 60 40 20 0 200 300 400 500 600 100 PEAK MAIN TERMINAL VOLTAGE (VOLTS) 700 800 MAC 228A10 TRIAC TJ = 110C
TJ, JUNCTION TEMPERATURE (C)
dV Figure 6.3. Exponential versus Temperature dt s
dV FAILURE MODE
dt s
Occasional unwanted turn-on by a transient may be acceptable in a heater circuit but isnt in a fire prevention sprinkler system or for the control of a large motor. Turn-on is destructive when the follow-on current amplitude or rate is excessive. If the thyristor shorts the power line or a charged capacitor, it will be damaged. Static dV turn-on is non-destructive when series impeddt
ance limits the surge. The thyristor turns off after a halfcycle of conduction. High dV aids current spreading in the
dt
dV Figure 6.2. Exponential versus Peak Voltage dt s
thyristor, improving its ability to withstand dI. Breakdown

dt
Static dV does not depend strongly on voltage for operadt
turn-on does not have this benefit and should be prevented.

140 120 100 MAC 228A10 800 V 110C
tion below the maximum voltage and temperature rating. Avalanche multiplication will increase leakage current and reduce dV capability if a transient is within roughly 50 volts
dt
A higher rated voltage device guarantees increased dV at

dt
lower voltage. This is a consequence of the exponential rating method where a 400 V device rated at 50 V/s has a higher dV to 200 V than a 200 V device with an identical
dt
STATIC dV (V/ s) dt
of the actual device breakover voltage.
80 60 40 RINTERNAL = 600
rating. However, the same diffusion recipe usually applies for all voltages. So actual capabilities of the product are not much different. Heat increases current gain and leakage, lowering
dV , the gate trigger voltage and noise immunity
dt s
20 0 10 100 1000 GATE-MT1 RESISTANCE (OHMS) 10,000
(Figure 3).
dV Figure 6.4. Exponential dt s versus Gate to MT1 Resistance
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GATE-CATHODE RESISTANCE (OHMS)
IMPROVING dV dt s dV Static can be improved by adding an external resistor dt
AN1048/D
10 MEG MCR22-006 TA = 65C 10 V K A G
from the gate to MT1 (Figure 4). The resistor provides a path for leakage and dV induced currents that originate in
dt
1 MEG
the drive circuit or the thyristor itself. Non-sensitive devices (Figure 5) have internal shorting resistors dispersed throughout the chips cathode area. This design feature improves noise immunity and high temperature blocking stability at the expense of increased trigger and holding current. External resistors are optional for nonsensitive SCRs and TRIACs. They should be comparable in size to the internal shorting resistance of the device (20 to 100 ohms) to provide maximum improvement. The internal resistance of the thyristor should be measured with an ohmmeter that does not forward bias a diode junction.
100 K
10K 0.001
0.01
0.1 1 STATIC dV (V ms) dt
dV Figure 6.6. Exponential dt versus s Gate-Cathode Resistance
10
100
2200 2000 1800 STATIC dV (V/ s) dt 1600 1400 1200 1000 800 MAC 15-8 VPK = 600 V
A gate-cathode capacitor (Figure 7) provides a shunt path for transient currents in the same manner as the resistor. It also filters noise currents from the drive circuit and enhances the built-in gate-cathode capacitance voltage divider effect. The gate drive circuit needs to be able to charge the capacitor without excessive delay, but it does not need to supply continuous current as it would for a resistor that increases dV the same amount. However, the
dt
capacitor does not enhance static thermal stability.

130 120
600
50
60
dV Figure 6.5. Exponential dt s versus Junction Temperature
STATIC dV (V/ s) dt
100 110 70 80 90 TJ, JUNCTION TEMPERATURE (C)
120
130
110
MAC 228A10 800 V 110C
100 90 80 70
Sensitive gate TRIACs run 100 to 1000 ohms. With an external resistor, their dV capability remains inferior to dt non-sensitive devices because lateral resistance within the gate layer reduces its benefit. Sensitive gate SCRs (IGT 200 A) have no built-in resistor. They should be used with an external resistor. The recommended value of the resistor is 1000 ohms. Higher
60 0.001
0.01 0.1 GATE TO MT1 CAPACITANCE (F)
values reduce maximum operating temperature and dV
(Figure 6). The capability of these parts varies by more than 100 to 1 depending on gate-cathode termination.
dV Figure 6.7. Exponential dt versus Gate s to MT1 Capacitance The maximum dV improvement occurs with a short. dt s
dt s
Actual improvement stops before this because of spreading resistance in the thyristor. An external capacitor of about 0.1 F allows the maximum enhancement at a higher value of RGK.
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One should keep the thyristor cool for the highest dV
Also devices should be tested in the application circuit at the highest possible temperature using thyristors with the lowest measured trigger current. TRIAC COMMUTATING dV dt
WHAT IS COMMUTATING dV ? dt dV The commutating rating applies when a TRIAC has dt
AN1048/D
. for sinusoidal currents is given by the slope of the secant line between the 50% and 0% levels as:
dt s
+
dI dt c dt
6 f I TM A ms 1000
where f = line frequency and ITM = maximum on-state current in the TRIAC. Turn-off depends on both the Miller effect displacement current generated by dV across the collector capacitance and the currents resulting from internal charge storage within the volume of the device (Figure 10). If the reverse recovery current resulting from both these components is high, the lateral IR drop within the TRIAC base layer will forward bias the emitter and turn the TRIAC on. Commutating dV capability is lower when turning off from the posdt
been conducting and attempts to turn-off with an inductive load. The current and voltage are out of phase (Figure 8). The TRIAC attempts to turn-off as the current drops below the holding value. Now the line voltage is high and in the opposite polarity to the direction of conduction. Successful turn-off requires the voltage across the TRIAC to rise to the instantaneous line voltage at a rate slow enough to prevent retriggering of the device.
VOLTAGE/CURRENT R VLINE L i G 1 VMT2-1
2 VMT2-1
itive direction of current conduction because of device geometry. The gate is on the top of the die and obstructs current flow. Recombination takes place throughout the conduction period and along the back side of the current wave as it declines to zero. Turn-off capability depends on its shape. If the current amplitude is small and its zero crossing dI
PHASE ANGLE
low, there is little volume charge storage and turn-off becomes limited by dV . At moderate current amplitudes,
dt s
dI dt c
TIME VLINE
TIME
the volume charge begins to influence turn-off, requiring a larger snubber. When the current is large or has rapid zero crossing, dV
dt
dt c
is
dV dt c
Figure 6.8. TRIAC Inductive Load Turn-Off
dV dt c
delay time to voltage reapplication determine whether turnoff will be successful or not (Figures 11, 12).
G MT1 TOP N N N
Previously Conducting Side
dt c
has little influence. Commutating dI and
dV DEVICE PHYSICS dt c
P
A TRIAC functions like two SCRs connected in inverseparallel. So, a transient of either polarity turns it on. There is charge within the crystals volume because of prior conduction (Figure 9). The charge at the boundaries of the collector junction depletion layer responsible for
dV is also present. TRIACs have lower dt s dV because of this additional charge. dt s
N + N N N
dV than dt c
The volume charge storage within the TRIAC depends on the peak current before turn-off and its rate of zero crossing dI . In the classic circuit, the load impedance
dt c
REVERSE RECOVERY CURRENT PATH
MT2 LATERAL VOLTAGE DROP
and line frequency determine dI . The rate of crossing

dt c
STORED CHARGE FROM POSITIVE CONDUCTION
Figure 6.9. TRIAC Structure and Current Flow at Commutation
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VOLTAGE/CURRENT
VMT2-1 VOLUME STORAGE CHARGE
di dt c
IRRM
CONDITIONS INFLUENCING dV dt c dV Commutating depends on charge storage and recovdt
dV dt c TIME
ery dynamics in addition to the variables influencing static

dV. High temperatures increase minority carrier life-time dt
0 CHARGE DUE TO dV/dt
and the size of recovery currents, making turn-off more difficult. Loads that slow the rate of current zero-crossing aid turn-off. Those with harmonic content hinder turn-off.
Circuit Examples
Figure 6.10. TRIAC Current and Voltage at Commutation
Figure 13 shows a TRIAC controlling an inductive load in a bridge. The inductive load has a time constant longer than the line period. This causes the load current to remain constant and the TRIAC current to switch rapidly as the line voltage reverses. This application is notorious for causing TRIAC turn-off difficulty because of high dI .
dt c
RS C i
E V MAIN TERMINAL VOLTAGE (V) LS
dI dt c
DC MOTOR R L +
60 Hz E
u
L R 8.3 ms
Figure 6.13. Phase Controlling a Motor in a Bridge

VT 0 td TIME
Figure 6.11. Snubber Delay Time
0.5 NORMALIZED DELAY TIME (t d* = W0 td) 0.2 0.2 0.1 0.1 0.05 0.02 RL = 0 M=1 IRRM = 0 0.01 V
High currents lead to high junction temperatures and rates of current crossing. Motors can have 5 to 6 times the normal current amplitude at start-up. This increases both junction temperature and the rate of current crossing, leading to turn-off problems. The line frequency causes high rates of current crossing in 400 Hz applications. Resonant transformer circuits are doubly periodic and have current harmonics at both the primary and secondary resonance. Non-sinusoidal currents can lead to turn-off difficulty even if the current amplitude is low before zero-crossing.
0.05 0.03 0.02 0.001 0.002
T 0.005 E 0.1 0.2 0.3 0.5 0.005 0.01 0.02 0.05 DAMPING FACTOR
Figure 6.12. Delay Time To Normalized Voltage
turn-on or total turn-off failure is possible. This can be destructive if the TRIAC conducts asymmetrically causing a dc current component and magnetic saturation. The winding resistance limits the current. Failure results because of excessive surge current and junction temperature.
dV FAILURE MODE dt c dV failure causes a loss of phase control. Temporary dt c
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IMPROVING dV dt c
AN1048/D
The same steps that improve dV
when stored charge dominates turn-off. Steps that reduce the stored charge or soften the commutation are necessary then. Larger TRIACs have better turn-off capability than smaller ones with a given load. The current density is lower in the larger device allowing recombination to claim a greater proportion of the internal charge. Also junction temperatures are lower. TRIACs with high gate trigger currents have greater turn-off ability because of lower spreading resistance in the gate layer, reduced Miller effect, or shorter lifetime. The rate of current crossing can be adjusted by adding a commutation softening inductor in series with the load. Small high permeability square loop inductors saturate causing no significant disturbance to the load current. The inductor resets as the current crosses zero introducing a large inductance into the snubber circuit at that time. This slows the current crossing and delays the reapplication of blocking voltage aiding turn-off. The commutation inductor is a circuit element that introduces time delay, as opposed to inductance, into the circuit. It will have little influence on observed dV at the
dt

dt s
Is
Hs ML + 0.4 p N
where :
aid dV
dt c
except
Hs = MMF to saturate = 0.5 Oersted ML = mean magnetic path length = 4.99 cm.
Is (4.99) + (.5) + 60 mA. .4 p 33
SNUBBER PHYSICS
UNDAMPED NATURAL RESONANCE I Radianssecond + LC dt
w0
Resonance determines dV and boosts the peak capacitor voltage when the snubber resistor is small. C and L are related to one another by 02. dV scales linearly with 0
dt
when the damping factor is held constant. A ten to one reduction in dV requires a 100 to 1 increase in either
dt
component.
DAMPING FACTOR
+R 2
C L
The damping factor is proportional to the ratio of the circuit loss and its surge impedance. It determines the trade off between dV and peak voltage. Damping factors between
dt
device. The following example illustrates the improvement resulting from the addition of an inductor constructed by winding 33 turns of number 18 wire on a tape wound core (52000-1A). This core is very small having an outside diameter of 3/4 inch and a thickness of 1/8 inch. The delay time can be calculated from:
ts
0.01 and 1.0 are recommended.

The Snubber Resistor Damping and dV dt
+ (N A BE10*8)
When
where:
t 0.5, the snubber resistor is small, and dV dt
depends mostly on resonance. There is little improvement in dV for damping factors less than 0.3, but peak voltage
dt
ts = time delay to saturation in seconds. B = saturating flux density in Gauss A = effective core cross sectional area in cm2 N = number of turns. For the described inductor:
ts
and snubber discharge current increase. The voltage wave has a 1-COS () shape with overshoot and ringing. Maximum dV occurs at a time later than t = 0. There is a time
dt
+ (33 turns) (0.076 cm2 ) (28000 Gauss) (1 10 8 ) (175 V) + 4.0 ms.
delay before the voltage rise, and the peak voltage almost doubles. When 0.5, the voltage wave is nearly exponential in shape. The maximum instantaneous dV occurs at t = 0.
dt
There is little time delay and moderate voltage overshoot. When
u 1.0, the snubber resistor is large and dV dt
The saturation current of the inductor does not need to be much larger than the TRIAC trigger current. Turn-off failure will result before recovery currents become greater than this value. This criterion allows sizing the inductor with the following equation:
depends mostly on its value. There is some overshoot even through the circuit is overdamped. High load inductance requires large snubber resistors and small snubber capacitors. Low inductances imply small resistors and large capacitors.
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Damping and Transient Voltages
Figure 14 shows a series inductor and filter capacitor connected across the ac main line. The peak to peak voltage of a transient disturbance increases by nearly four times. Also the duration of the disturbance spreads because of ringing, increasing the chance of malfunction or damage to the voltage sensitive circuit. Closing a switch causes this behavior. The problem can be reduced by adding a damping resistor in series with the capacitor.
Table 1 shows suggested minimum resistor values estimated (Appendix A) by testing a 20 piece sample from the four different TRIAC die sizes.
Table 1. Minimum Non-inductive Snubber Resistor for Four Quadrant Triggering.
Peak VC Volts 200 300 400 600 800 Rs Ohms 3.3 6.8 11 39 51 dI dt A/s 170 250 308 400 400
TRIAC Type Non-Sensitive Gate (IGT 10 mA) 8 to 40 A(RMS)
100 H 340 V 0 10 s
0.05 0.1 F V VOLTAGE SENSITIVE CIRCUIT
+ 700 V (VOLTS)
Reducing dI dt
TRIAC dI can be improved by avoiding quadrant 4

dt
0
700 0 10 TIME (s) 20
triggering. Most optocoupler circuits operate the TRIAC in quadrants 1 and 3. Integrated circuit drivers use quadrants 2 and 3. Zero crossing trigger devices are helpful because they prohibit triggering when the voltage is high. Driving the gate with a high amplitude fast rise pulse increases dI capability. The gate ratings section defines the
dt
Figure 6.14. Undamped LC Filter Magnifies and Lengthens a Transient dI dt Non-Inductive Resistor
maximum allowed current. Inductance in series with the snubber capacitor reduces
dI. It should not be more than five percent of the load dt inductance to prevent degradation of the snubbers dV dt
The snubber resistor limits the capacitor discharge current and reduces dI stress. High dI destroys the thyristor
dt dt
even though the pulse duration is very short. The rate of current rise is directly proportional to circuit voltage and inversely proportional to series inductance. The snubber is often the major offender because of its low inductance and close proximity to the thyristor. With no transient suppressor, breakdown of the thyristor sets the maximum voltage on the capacitor. It is possible to exceed the highest rated voltage in the device series because high voltage devices are often used to supply low voltage specifications. The minimum value of the snubber resistor depends on the type of thyristor, triggering quadrants, gate current amplitude, voltage, repetitive or non-repetitive operation, and required life expectancy. There is no simple way to predict the rate of current rise because it depends on turn-on speed of the thyristor, circuit layout, type and size of snubber capacitor, and inductance in the snubber resistor. The equations in Appendix D describe the circuit. However, the values required for the model are not easily obtained except by testing. Therefore, reliability should be verified in the actual application circuit.
suppression capability. Wirewound snubber resistors sometimes serve this purpose. Alternatively, a separate inductor can be added in series with the snubber capacitor. It can be small because it does not need to carry the load current. For example, 18 turns of AWG No. 20 wire on a T50-3 (1/2 inch) powdered iron core creates a non-saturating 6.0 H inductor. A 10 ohm, 0.33 F snubber charged to 650 volts resulted in a 1000 A/s dI. Replacement of the non-inductive snubdt
ber resistor with a 20 watt wirewound unit lowered the rate of rise to a non-destructive 170 A/s at 800 V. The inductor gave an 80 A/s rise at 800 V with the noninductive resistor.
The Snubber Capacitor
A damping factor of 0.3 minimizes the size of the snubber capacitor for a given value of dV. This reduces the cost
dt
and physical dimensions of the capacitor. However, it raises voltage causing a counter balancing cost increase. Snubber operation relies on the charging of the snubber capacitor. Turn-off snubbers need a minimum conduction angle long enough to discharge the capacitor. It should be at least several time constants (RS CS).
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STORED ENERGY Inductive Switching Transients E
snubber inductor and limits the rate of inrush current if the device does turn on. Resistance in the load lowers dV and
dt
+1 2
I0 =
L I 0 2 Watt-seconds or Joules
VPK (Figure 16).

1.4 E 2.2 dV dt 2.1 2 1.9 M = 0.75 NORMALIZED PEAK VOLTAGE VPK /E 1.8 1.7 1.6 M = 0.5 0.6 M = 0.25 1.5 1.4 1.3 1.2 M=0 0.2 1.1 1 M = RS / (RL + RS) 0 0 0.2 S + RESISTIVE DIVISION RATIO + RL R ) RS I +0 RRM 0.4 0.6 DAMPING FACTOR 0.8 1 0.9
(dV dt )/ (E W0 )
current in Amperes flowing in the inductor at t = 0. Resonant charging cannot boost the supply voltage at turn-off by more than 2. If there is an initial current flowing in the load inductance at turn-off, much higher voltages are possible. Energy storage is negligible when a TRIAC turns off because of its low holding or recovery current. The presence of an additional switch such as a relay, thermostat or breaker allows the interruption of load current and the generation of high spike voltages at switch opening. The energy in the inductance transfers into the circuit capacitance and determines the peak voltage (Figure 15).
L I R VPK C OPTIONAL FAST
1.2
VPK
1 M=1 NORMALIZED dV dt 0.8
0.4
dV dt
I V C PK
+I
SLOW
L C
(b.) Unprotected Circuit
(a.) Protected Circuit
Figure 6.16. 0 To 63% dV dt
Figure 6.15. Interrupting Inductive Load Current Capacitor Discharge
CHARACTERISTIC VOLTAGE WAVES Damping factor and reverse recovery current determine the shape of the voltage wave. It is not exponential when the snubber damping factor is less than 0.5 (Figure 17) or when significant recovery currents are present.
=0 = 0.1
thyristor every time it turns on. The power loss is proportional to frequency (PAV = 120 Ec @ 60 Hz).
CURRENT DIVERSION
T h e e n e rg y s t o r e d i n t h e s n u b b e r c a p a c i t o r
Ec
+1 C V2 2
transfers to the snubber resistor and
The current flowing in the load inductor cannot change instantly. This current diverts through the snubber resistor causing a spike of theoretically infinite dV with magnitude dt equal to (IRRM R) or (IH R).
LOAD PHASE ANGLE dV at turn-off. However, they help to protect the dt c thyristor from transients and dV . The load serves as the dt s
V MT (VOLTS) 2-1
500 400 300 200 100 0 0
0.3
0.1 = 0.3 0 =1
Highly inductive loads cause increased voltage and
0.7
1.4
2.1
2.8 3.5 4.2 TIME (s)
4.9
5.6
0 63% dV dt s R L
+ 100 Vms, E + 250 V, + 0, IRRM + 0
6.3
Figure 6.17. Voltage Waves For Different Damping Factors
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AN1048/D
2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1063 dV % dt VPK 1063%
COMPLEX LOADS
NORMALIZED PEAK VOLTAGE AND
dV MAX dt
063% dV dt
dV dt o
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 DAMPING FACTOR () (R 0, M 1, I 0)
NORMALIZED dV dt
+ + dt + dV E w0
RRM
NORMALIZED V PK
PK + VE
Many real-world inductances are non-linear. Their core materials are not gapped causing inductance to vary with current amplitude. Small signal measurements poorly characterize them. For modeling purposes, it is best to measure them in the actual application. Complex load circuits should be checked for transient voltages and currents at turn-on and off. With a capacitive load, turn-on at peak input voltage causes the maximum surge current. Motor starting current runs 4 to 6 times the steady state value. Generator action can boost voltages above the line value. Incandescent lamps have cold start currents 10 to 20 times the steady state value. Transformers generate voltage spikes when they are energized. Power factor correction circuits and switching devices create complex loads. In most cases, the simple CRL model allows an approximate snubber design. However, there is no substitute for testing and measuring the worst case load conditions.
SURGE CURRENTS IN INDUCTIVE CIRCUITS
Figure 6.18. Trade-Off Between VPK and dV dt
dV dt
A variety of wave parameters (Figure 18) describe dV dt Some are easy to solve for and assist understanding. These include the initial dV, the maximum instantaneous dV, and the average dV to the peak reapplied voltage. The 0 to 63%
dt dV and 10 to 63% dt s dV definitions on device data dt c dt dt
Inductive loads with long L/R time constants cause asymmetric multi-cycle surges at start up (Figure 20). Triggering at zero voltage crossing is the worst case condition. The surge can be eliminated by triggering at the zero current crossing angle.
20 MHY i
sheets are easy to measure but difficult to compute. NON-IDEAL BEHAVIORS

CORE LOSSES
240 VAC
0.1
The magnetic core materials in typical 60 Hz loads introduce losses at the snubber natural frequency. They appear as a resistance in series with the load inductance and winding dc resistance (Figure 19). This causes actual dV to dt be less than the theoretical value.
L R
i (AMPERES)
90
0 ZERO VOLTAGE TRIGGERING, IRMS = 30 A 40 80 120 TIME (MILLISECONDS) 160 200
Figure 6.20. Start-Up Surge For Inductive Circuit

C L DEPENDS ON CURRENT AMPLITUDE, CORE SATURATION R INCLUDES CORE LOSS, WINDING R. INCREASES WITH FREQUENCY C WINDING CAPACITANCE. DEPENDS ON INSULATION, WIRE SIZE, GEOMETRY
Figure 6.19. Inductor Model
Core remanence and saturation cause surge currents. They depend on trigger angle, line impedance, core characteristics, and direction of the residual magnetization. For example, a 2.8 kVA 120 V 1:1 transformer with a 1.0 ampere load produced 160 ampere currents at start-up. Soft starting the circuit at a small conduction angle reduces this current. Transformer cores are usually not gapped and saturate easily. A small asymmetry in the conduction angle causes magnetic saturation and multi-cycle current surges.
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Steps to achieve reliable operation include: 1. Supply sufficient trigger current amplitude. TRIACs have different trigger currents depending on their quadrant of operation. Marginal gate current or optocoupler LED current causes halfwave operation. 2. Supply sufficient gate current duration to achieve latching. Inductive loads slow down the main terminal current rise. The gate current must remain above the specified IGT until the main terminal current exceeds the latching value. Both a resistive bleeder around the load and the snubber discharge current help latching. 3. Use a snubber to prevent TRIAC dV resistor. The non-inductive snubber circuit is useful when the load resistance is much larger than the snubber resistor.
RL E e RS CS e E V step t=0 e (t S +E R R ) RL S = (RL + RS) CS
4. Minimize designed-in trigger asymmetry. Triggering must be correct every half-cycle including the first. Use a storage scope to investigate circuit behavior during the first few cycles of turn-on. Alternatively, get the gate circuit up and running before energizing the load. 5. Derive the trigger synchronization from the line instead of the TRIAC main terminal voltage. This avoids regenerative interaction between the core hysteresis and the triggering angle preventing trigger runaway, halfwave operation, and core saturation. 6. Avoid high surge currents at start-up. Use a current probe to determine surge amplitude. Use a soft start circuit to reduce inrush current.
DISTRIBUTED WINDING CAPACITANCE
dt c
failure.
+ o)) + E

RS RS RESISTOR COMPONENT
TIME
) RL e*tt ) (1 * e*tt)
CAPACITOR COMPONENT
Figure 6.21. Non-Inductive Snubber Circuit Opto-TRIAC Examples Single Snubber, Time Constant Design
There are small capacitances between the turns and layers of a coil. Lumped together, they model as a single shunt capacitance. The load inductor behaves like a capacitor at frequencies above its self-resonance. It becomes ineffective in controlling dV and VPK when a fast transient such as that
dt
Figure 22 illustrates the use of the RC time constant design method. The optocoupler sees only the voltage across the snubber capacitor. The resistor R1 supplies the trigger current of the power TRIAC. A worst case design procedure assumes that the voltage across the power TRIAC changes instantly. The capacitor voltage rises to 63% of the maximum in one time constant. Then:
R1 CS E where + t + 0.63 dV dt s
dV is the rated static dV dt s dt
resulting from the closing of a switch occurs. This problem can be solved by adding a small snubber across the line.
SELF-CAPACITANCE
for the optocoupler.

1 A, 60 Hz
A thyristor has self-capacitance which limits dV when the

dt
load inductance is large. Large load inductances, high power factors, and low voltages may allow snubberless operation. SNUBBER EXAMPLES
WITHOUT INDUCTANCE Power TRIAC Example
VCC
Rin 1 2
10 V/s MOC 3021 CNTL
L = 318 MHY 6 4 180 0.1 F 2.4 k C1 2N6073A 1 V/s 170 V
0.63 (170) 240 s
DESIGN dV dt TIME
(0.63) (170) + (2400) + 0.45 Vms (0.1 mF)
Figure 21 shows a transient voltage applied to a TRIAC controlling a resistive load. Theoretically there will be an instantaneous step of voltage across the TRIAC. The only elements slowing this rate are the inductance of the wiring and the self-capacitance of the thyristor. There is an exponential capacitor charging component added along with a decaying component because of the IR drop in the snubber
dV (V ms) dt Power TRIAC 0.99 Optocoupler 0.35
Figure 6.22. Single Snubber For Sensitive Gate TRIAC and Phase Controllable Optocoupler ( = 0.67)
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The optocoupler conducts current only long enough to trigger the power device. When it turns on, the voltage between MT2 and the gate drops below the forward threshold voltage of the opto-TRIAC causing turn-off. The optocoupler sees dV However a power TRIAC along with the optocoupler should be used for higher load currents.
80 70 LOAD CURRENT (mA RMS) 60 50 40 30 20 NO SNUBBER 10 0 20 30 40 50 60 70 80 TA, AMBIENT TEMPERATURE (C) 90 100 CS = 0.001 CS = 0.01
in the conduction cycle at zero current crossing. Therefore, it is not necessary to design for the lower optocoupler
dt s
when the power TRIAC turns off later
for the optocoupler protects both devices.

1 MHY VCC MOC3031 1 2 3 4 5 6 51 MCR2654 100 1N4001 (50 V/s SNUBBER, = 1.0) 0.022 F 100 1N4001 MCR2654 430 120 V 400 Hz
dV rating. In this example, a single snubber designed dt c
(RS = 100 , VRMS = 220 V, POWER FACTOR = 0.5)
Figure 6.24. MOC3062 Inductive Load Current versus TA
Figure 6.23. Anti-Parallel SCR Driver
A phase controllable optocoupler is recommended with a power device. When the load current is small, a MAC97A TRIAC is suitable. Unusual circuit conditions sometimes lead to unwanted operation of an optocoupler in dV
Optocouplers with SCRs
Anti-parallel SCR circuits result in the same dV across

dt
the optocoupler and SCR (Figure 23). Phase controllable opto-couplers require the SCRs to be snubbed to their lower
dV rating. Anti-parallel SCR circuits are free from the dt
charge storage behaviors that reduce the turn-off capability of TRIACs. Each SCR conducts for a half-cycle and has the next half cycle of the ac line in which to recover. The turnoff dV of the conducting SCR becomes a static forward blocking dV for the other device. Use the SCR data sheet
dt dV rating in the snubber design. dt s
rents in the power device cause increased voltages between MT2 and the gate that hold the optocoupler on. Use of a larger TRIAC or other measures that limit inrush current solve this problem. Very short conduction times leave residual charge in the optocoupler. A minimum conduction angle allows recovery before voltage reapplication.
THE SNUBBER WITH INDUCTANCE
dt c
mode. Very large cur-
A SCR used inside a rectifier bridge to control an ac load will not have a half cycle in which to recover. The available time decreases with increasing line voltage. This makes the circuit less attractive. Inductive transients can be suppressed by a snubber at the input to the bridge or across the SCR. However, the time limitation still applies.
OPTO dV dt c
dt
Consider an overdamped snubber using a large capacitor whose voltage changes insignificantly during the time under consideration. The circuit reduces to an equivalent L/R series charging circuit. The current through the snubber resistor is:
i V +R
t
* *
1 e
t
and the voltage across the TRIAC is:

e
+ i R S.
The voltage wave across the TRIAC has an exponential rise with maximum rate at t = 0. Taking its derivative gives its value as:
Zero-crossing optocouplers can be used to switch inductive loads at currents less than 100 mA (Figure 24).
+
dV dt 0
V RS . L
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Highly overdamped snubber circuits are not practical designs. The example illustrates several properties: 1. The initial voltage appears completely across the circuit inductance. Thus, it determines the rate of change of current through the snubber resistor and the initial dV.
dt Z
= measured phase angle between line V and load I RL = measured dc resistance of the load. Then
RMS +V I RMS
RL
) XL2
XL
Z2
* RL2
and
This result does not change when there is resistance in the load and holds true for all damping factors. 2. The snubber works because the inductor controls the rate of current change through the resistor and the rate of capacitor charging. Snubber design cannot ignore the inductance. This approach suggests that the snubber capacitance is not important but that is only true for this hypothetical condition. The snubber resistor shunts the thyristor causing unacceptable leakage when the capacitor is not present. If the power loss is tolerable,
dV can be controlled without the capacitor. An dt
+ 2 pXfL
Line
If only the load current is known, assume a pure inductance. This gives a conservative design. Then:
L
+ 2 p fVRMS I + 2
120
where E
Line RMS
+ 2
V RMS.
For example:
E
+ 170 V; L + (8 A) 120 + 39.8 mH. (377 rps)

dt (
example is the soft-start circuit used to limit inrush current in switching power supplies (Figure 25).
Read from the graph at = 0.6, VPK = (1.25) 170 = 213 V. Use 400 V TRIAC. Read dV 2. Apply the resonance criterion:
Snubber With No C
w0 +
RS

spec dV dt 5 10 6 V S (1) (170 V)
+0.6) + 1.0.
dV E . dt (P) 10 3 r p s.
E AC LINE SNUBBER L RECTIFIER BRIDGE dV dt
+
f
RS G
G ER S L
C1
w0 +
C
+ 29.4
+w 1 + 0.029 m F 2 L
0
3. Apply the damping criterion:

C1
E AC LINE SNUBBER L
RECTIFIER BRIDGE
RS
+ 2
Figure 6.25. Surge Current Limiting For a Switching Power Supply
TRIAC DESIGN PROCEDURE dV dt c 1. Refer to Figure 18 and select a particular damping factor () giving a suitable trade-off between VPK and dV. dt Determine the normalized dV corresponding to the chosen dt damping factor. The voltage E depends on the load phase angle:
E
XL RL
dV SAFE AREA CURVE dt c Figure 26 shows a MAC15 TRIAC turn-off safe operating area curve. Turn-off occurs without problem
dt dI and delay time at high currents. Reduction values of dt c
+
L C
2 (0.6)
39.8 0.029
10 3 10 6
* + 1400 ohms. *
under the curve. The region is bounded by static dV at low
+ 2
VRMS Sin (f) where
f + tan *1
of the peak current permits operation at higher line frequency. This TRIAC operated at f = 400 Hz, TJ = 125C, and ITM = 6.0 amperes using a 30 ohm and 0.068 F snubber. Low damping factors extend operation to higher
where
saturable commutation inductor extends the allowed current rate by introducing recovery delay time.
dI , but capacitor sizes increase. The addition of a small, dt c
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One hundred H is a suggested value for starting the design. Plug the assumed inductance into the equation for C. Larger values of inductance result in higher snubber resistance and reduced dI. For example:
6 f ITM 10 *3 Ams
ITM = 15 A 100
+
dI dt c
Given E = 240 2 Pick = 0.3.
+ 340 V.
dt
(V/ s) ( dV dt )c
10
WITH COMMUTATION L
Then from Figure 18, VPK = 1.42 (340) = 483 V. Thus, it will be necessary to use a 600 V device. Using the previously stated formulas for 0, C and R we find:
10 VS w0 + 50 + 201450 (0.73) (340 V) 6 C 1 + (201450)2 (100 rps
0.1 10 14 18
22 26 30 34 38 dI AMPERES MILLISECOND dt c
42
46
50
MAC 16-8, COMMUTATIONAL L 33 TURNS # 18, 52000-1A TAPE WOUND CORE 3 4 INCH OD
Figure 6.26.
+ 2 (0.3)
10
100 0.2464
*6) + 0.2464 m F 10 *6 + 12 ohms 10 *6
VARIABLE LOADS The snubber should be designed for the smallest load inductance because dV will then be highest because of its dependence on 0. This requires a higher voltage device for operation with the largest inductance because of the corresponding low damping factor. Figure 28 describes dV for an 8.0 ampere load at various
dt dt
dV dI versus T = 125C dt c dt c J
STATIC dV DESIGN dt There is usually some inductance in the ac main and power wiring. The inductance may be more than 100 H if there is a transformer in the circuit or nearly zero when a shunt power factor correction capacitor is present. Usually the line inductance is roughly several H. The minimum inductance must be known or defined by adding a series inductor to insure reliable operation (Figure 27).
power factors. The minimum inductance is a component added to prevent static dV firing with a resistive load.
dt
8 A LOAD R MAC 218A6FP 68 0.033 F L 120 V 60 Hz
10 100 H 20 A LS1 340 V
0.33 F
t 50 V/s
+
dV dt s 12 HEATER
0.75 0.03 0.04 0.06 R 15 0 10.6 13.5
100 V ms
+
dV dt c
VPK V 191 325 225 136 V 170 170 120 74
5 V ms
L MHY 0.1 39.8 28.1 17.3
Vstep
dv dt V/s 86 4.0 3.3 2.6
Figure 6.27. Snubbing For a Resistive Load
Figure 6.28. Snubber For a Variable Load
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EXAMPLES OF SNUBBER DESIGNS Table 2 describes snubber RC values for V/s dV
Figures 31 and 32 show possible R and C values for a 5.0

dt c
dV . dt s
80 A RMS
assuming a pure inductive load.

0.1
40 A 20 A CS ( F) 10 A 5A 0.01 2.5 A
dV Designs dt (E = 340 V, Vpeak = 500 V, = 0.3) Table 2. Static

5.0 V/s L H 47 100 220 500 1000 C F R Ohm 50 V/s C F 0.33 0.15 0.068 0.033 R Ohm 10 22 51 100 100 V/s C F 0.15 0.1 0.033 0.015 R Ohm 10 20 47 110
0.6 A 0.001 0
3.0
11
TRANSIENT AND NOISE SUPPRESSION Transients arise internally from normal circuit operation or externally from the environment. The latter is particularly frustrating because the transient characteristics are undefined. A statistical description applies. Greater or smaller stresses are possible. Long duration high voltage transients are much less probable than those of lower amplitude and higher frequency. Environments with infrequent lightning and load switching see transient voltages below 3.0 kV.
10K
Figure 6.30. Snubber Capacitor For dV = 5.0 V/s dt c
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
DAMPING FACTOR
PURE INDUCTIVE LOAD, V I RRM 0
+ 120 VRMS,
0.9
0.6 A RMS
2.5 A 5A
1000 R S (OHMS)
10 A 20 A 40 A 80 A
100
10 0
Figure 6.29. Snubber Resistor For dV = 5.0 V/s dt c
0.1
0.2
0.3
0.4
0.5
0.6
DAMPING FACTOR
PURE INDUCTIVE LOAD, V I RRM 0
+ 120 VRMS,

0.7 0.8
0.9
The natural frequencies and impedances of indoor ac wiring result in damped oscillatory surges with typical frequencies ranging from 30 kHz to 1.5 MHz. Surge amplitude depends on both the wiring and the source of surge energy. Disturbances tend to die out at locations far away from the source. Spark-over (6.0 kV in indoor ac wiring) sets the maximum voltage when transient suppressors are not present. Transients closer to the service entrance or in heavy wiring have higher amplitudes, longer durations, and more damping because of the lower inductance at those locations. The simple CRL snubber is a low pass filter attenuating frequencies above its natural resonance. A steady state sinusoidal input voltage results in a sine wave output at the same frequency. With no snubber resistor, the rate of roll off approaches 12 dB per octave. The corner frequency is at the snubbers natural resonance. If the damping factor is low, the response peaks at this frequency. The snubber resistor degrades filter characteristics introducing an up-turn at = 1 / (RC). The roll-off approaches 6.0 dB/octave at frequencies above this. Inductance in the snubber resistor further reduces the roll-off rate. Figure 32 describes the frequency response of the circuit in Figure 27. Figure 31 gives the theoretical response to a 3.0 kV 100 kHz ring-wave. The snubber reduces the peak voltage across the thyristor. However, the fast rise input causes a high dV step when series inductance is added to the
dt
snubber resistor. Limiting the input voltage with a transient suppressor reduces the step.
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400 VMT (VOLTS) 2-1 WITHOUT 5 HY WITH 5 HY AND 450 V MOV AT AC INPUT
0 WITH 5 HY
In Figure 32, there is a separate suppressor across each thyristor. The load impedance limits the surge energy delivered from the line. This allows the use of a smaller device but omits load protection. This arrangement protects each thyristor when its load is a possible transient source.
400 0 1 2 3 TIME (s) 4 5 6
Figure 6.31. Theoretical Response of Figure 33 Circuit to 3.0 kV IEEE 587 Ring Wave (RSC = 27.5 )
VMAX
+ 10
Figure 6.33. Limiting Line Voltage

0 VOLTAGE GAIN (dB) 10 100 H 20 Vin 30 40 10K 12 5 H 10 Vout 0.33 F WITH 5 HY
WITHOUT 5HY 1M
100K FREQUENCY (Hz)
Figure 6.32. Snubber Frequency Response
Vout
in Figure 6.34. Limiting Thyristor Voltage
dt dI when coupling is by stray capacitance, and when the dt
The noise induced into a circuit is proportional to dV
coupling is by mutual inductance. Best suppression requires the use of a voltage limiting device along with a rate limiting CRL snubber. The thyristor is best protected by preventing turn-on from dV or breakover. The circuit should be designed for dt what can happen instead of what normally occurs. In Figure 30, a MOV connected across the line protects many parallel circuit branches and their loads. The MOV defines the maximum input voltage and dI through the load.
dt dV and peak voltage With the snubber, it sets the maximum dt
It is desirable to place the suppression device directly across the source of transient energy to prevent the induction of energy into other circuits. However, there is no protection for energy injected between the load and its controlling thyristor. Placing the suppressor directly across each thyristor positively limits maximum voltage and snubber discharge dI .
dt
EXAMPLES OF SNUBBER APPLICATIONS In Figure 35, TRIACs switch a 3 phase motor on and off and reverse its rotation. Each TRIAC pair functions as a SPDT switch. The turn-on of one TRIAC applies the differential voltage between line phases across the blocking device without the benefit of the motor impedance to constrain the rate of voltage rise. The inductors are added to prevent static dV firing and a line-to-line short.
dt
across the thyristor. The MOV must be large because there is little surge limiting impedance to prevent its burn-out.
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SNUBBER 1 100 H 300 4 MOC 3081 FWD SNUBBER 2 300 4 MOC 3081 REV SNUBBER 2 100 H 300 4 MOC 3081 FWD SNUBBER 2 300 6 3 N MOC 3081 REV 4 1 G 91 43 6 2 1 6 G 91 MOC 3081 4 6 1 G 91 SNUBBER ALL MOVS ARE 275 VRMS ALL TRIACS ARE MAC218A10FP 1/3 HP 208 V 3 PHASE 6 2 1 G 91 0.15 F 22 2W WIREWOUND
91 G 1 2 SNUBBER
Figure 6.35. 3 Phase Reversing Motor
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Figure 36 shows a split phase capacitor-run motor with reversing accomplished by switching the capacitor in series with one or the other winding. The forward and reverse TRIACs function as a SPDT switch. Reversing the motor applies the voltage on the capacitor abruptly across the blocking thyristor. Again, the inductor L is added to prevent
dV firing of the blocking TRIAC. If turn-on occurs, the
dt s
less dV capability than similar non-sensitive devices. A

dt
non-sensitive thyristor should be used for high dV .

dt
TRIAC commutating dV ratings are 5 to 20 times less

dt
than static dV ratings.

dt
forward and reverse TRIACs short the capacitors (Cs) resulting in damage to them. It is wise to add the resistor RS to limit the discharge current.
SNUBBER INDUCTOR D1 C1 D3 D4 RL 240 V 0 G C2 CS + +
D2 120 VAC OR 240 VAC 46 V/s MAX 3.75 LS 330 V 500 H 5.6 MOTOR 1/70 HP 0.26 A
REV 91 0.1
91 RS 115 2N6073
FWD 0.1 CS
120 V RS
Figure 6.37. Tap Changer For Dual Voltage Switching Power Supply
Phase controllable optocouplers have lower dV ratings

Figure 6.36. Split Phase Reversing Motor dt
Figure 37 shows a tap changer. This circuit allows the operation of switching power supplies from a 120 or 240 vac line. When the TRIAC is on, the circuit functions as a conventional voltage doubler with diodes D1 and D2 conducting on alternate half-cycles. In this mode of operation, inrush current and dI are hazards to TRIAC reliability.
dt
than zero crossing optocouplers and power TRIACs. These should be used when a dc voltage component is present, or to prevent turn-on delay. Zero crossing optocouplers have more dV capability than
dt
power thyristors; and they should be used in place of phase controllable devices in static switching applications. APPENDIX A MEASURING dV
dt s dt
Series impedance is necessary to prevent damage to the TRIAC. The TRIAC is off when the circuit is not doubling. In this state, the TRIAC sees the difference between the line voltage and the voltage at the intersection of C1 and C2. Transients on the line cause dV firing of the TRIAC. High
dt s dI inrush current, , and overvoltage damage to the filter dt
Figure 38 shows a test circuit for measuring the static dV of power thyristors. A 1000 volt FET switch insures that the voltage across the device under test (D.U.T.) rises rapidly from zero. A differential preamp allows the use of a N-channel device while keeping the storage scope chassis at ground for safety purposes. The rate of voltage rise is adjusted by a variable RC time constant. The charging resistance is low to avoid waveform distortion because of the thyristors self-capacitance but is large enough to prevent damage to the D.U.T. from turn-on dI. Mounting the
dt
capacitor are possibilities. Prevention requires the addition of a RC snubber across the TRIAC and an inductor in series with the line. THYRISTOR TYPES Sensitive gate thyristors are easy to turn-on because of their low trigger current requirements. However, they have
miniature range switches, capacitors, and G-K network close to the device under test reduces stray inductance and allows testing at more than 10 kV/s.
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27 VDRM/VRRM SELECT X100 PROBE DIFFERENTIAL PREAMP X100 PROBE G RGK MOUNT DUT ON TEMPERATURE CONTROLLED C PLATE dV dt VERNIER 1 470 pF 0.001 0.005 82 2W 0.01 2W POWER 0.047 1N914 20 V 56 2W 1000 1/4 W MTP1N100 0.47 1N967A 18 V 01000 V 10 mA 0.1 TEST 2 DUT 20 k 2W 2W 1000 10 WATT WIREWOUND 0.33 1000 V
0.047 1000 V
100 2W
1 MEG
2 W EACH 1.2 MEG
f = 10 Hz PW = 100 s 50 PULSE GENERATOR
ALL COMPONENTS ARE NON-INDUCTIVE UNLESS OTHERWISE SHOWN
Figure 6.38. Circuit For Static dV Measurement of Power Thyristors dt
APPENDIX B MEASURING dV dt c A test fixture to measure commutating dV is shown in

dt
Figure 39. It is a capacitor discharge circuit with the load series resonant. The single pulse test aids temperature control and allows the use of lower power components. The limited energy in the load capacitor reduces burn and shock hazards. The conventional load and snubber circuit provides recovery and damping behaviors like those in the application. The voltage across the load capacitor triggers the D.U.T. It terminates the gate current when the load capacitor voltage crosses zero and the TRIAC current is at its peak. Each VDRM, ITM combination requires different components. Calculate their values using the equations given in Figure 39.
Commercial chokes simplify the construction of the necessary inductors. Their inductance should be adjusted by increasing the air gap in the core. Removal of the magnetic pole piece reduces inductance by 4 to 6 but extends the current without saturation. The load capacitor consists of a parallel bank of 1500 Vdc non-polar units, with individual bleeders mounted at each capacitor for safety purposes. An optional adjustable voltage clamp prevents TRIAC breakdown. To measure dV , synchronize the storage scope on the
dt c
current waveform and verify the proper current amplitude and period. Increase the initial voltage on the capacitor to compensate for losses within the coil if necessary. Adjust the snubber until the device fails to turn off after the first half-cycle. Inspect the rate of voltage rise at the fastest passing condition.
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HG = W AT LOW NON-INDUCTIVE RESISTOR DECADE 010 k, 1 STEP + CLAMP 2.2 M, 2W 51 k 2W 2.2 M, 2W CLAMP
LD10-1000-1000 LL RL TRIAD C30X 50 H, 3500 910 k Q3 C L (NON-POLAR) Q1 MR760 MR760 2.2 M
MR760 2.2 M
2W
CAPACITOR DECADE 110 F, 0.011 F, 100 pF 0.01 F
51 k RS 2N3904
2W 2N390 6 0.01 1/2 W 120
2.2 M
0-1 kV 20 mA
0.01
120 1/2 W
2N390 6 5 PEARSON 301 X 360 1k
150 k
6.2 MEG 2N3904 +5
2 W Q3
2N3906 0.1 2N3904
2N3904 0.1 2N3906 2 51 2W 51 1 2W 5 G TRIAC UNDER TEST CASE CONTROLLED HEATSINK 56 2 WATT 0.22
Q1
1/2 W
360
1/2 W 1k
2N3904 Q3 270 k + Q1 270 k 2N3906 0.22
CS
+5
dV dt SYNC
2.2 k 1/2
1N5343 7.5 V
CL
I PK + W0 + 2 pp VCi V Ci I T
LL
2 + W0 Ci + 4 pT2 I PK C V
W0 L
I + L
+
dI dt c
6f I PK
10 6 A ms
Figure 6.39.
dV Test Circuit For Power TRIACs dt c
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62 F 1 kV
910 k 2W
6.2 MEG 2 W
+ 1.5 kV 70 mA
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APPENDIX C dV DERIVATIONS dt
DEFINITIONS 1.0 RT M CONSTANTS (depending on the damping factor): 2.1
+ RL ) RS + Total Resistance
T
2.2
1.1
S +R + Snubber Divider Ratio R
2.3
1.2
w0 +
w + Damped
1.3
1 L CS
+ Undamped Natural Frequency

Natural Frequency 2.4
+ 0) + w0 RT + a + + 0 Underdamped (0 t t 1) w + w0 2 * a2 + w0 1 * 2 Critical Damped ( + 1) a + w0, w + 0, R + 2 L , C + 2 aR C

w
No Damping (
RT + Wave Decrement Factor +2 L LI 2 Initial Energy In Inductor + 1122 CV + Final 2 Energy In Capacitor L C Initial Current Factor
w + a
Overdamped ( 2
u 1) * w0 + w0 2 * 1
2
Laplace transforms for the current and voltage in Figure 40 are:

3.0 i (S)
1.4
1.5
1.6 1.7
+ + +
I +E RT 2 C L
E L SI ; e RT 1 2 S S L LC
+E * S
L
S V0L S2
*c
1 ) RLT S) LC
a w0
+ Damping Factor
across the load
RL t=0 I
V0
+ E * RS I + Initial Voltage drop at t + 0 L

+
RS e CS
1.8
+ CI E LRL S dV + Initial instantaneous dV dt 0 dt

c
at t
+ 0,
INITIAL CONDITIONS I I RRM VC 0 S
ignoring
Figure 6.40. Equivalent Circuit for Load and Snubber
1.9
+
dV dt 0
any initial instantaneous voltage step at t 0 because of I RRM
The inverse laplace transform for each of the conditions gives:

UNDERDAMPED (Typical Snubber Design) 4.0
V OL
RT L
2.0
E RS + + 0, dV L dt 0 dV + Maximum instantaneous dV dt max dt t max + Time of maximum instantaneous dV dt t peak + Time of maximum instantaneous peak
V PK
When I
) c.
For all damping conditions
a + E * V0L Cos (wt) * w c *at w sin (wt) e

e
sin (wt) e
*a )
t
4.1
de dt
+ V0L
Cos (wt) a sin (wt) e at
2a Cos (wt)
a 2) ) (w2w sin (wt)
voltage across thyristor
Average dV dt
+ Maximum instantaneous voltage across the

thyristor.
+ VPK tPK + Slope of the secant line from t + 0 through V PK
4.2
t PK
1 w tan
*1 *
RS
When M
+ 0,
eat
)c * * ca V0 w w L 0, I + 0 : w t PK + p
2a V0 L w2 a2
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4.3
+ E ) wa0 * a tPK w02 V0L2) 2ac V0L) c When I + 0, R L + 0, M + 1:

V PK
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6.3 V PK
+ E V0L (1a tPK)c tPK ea tPK
6.4
4.4
+ (1 ) e * a tPK) V PK Average dV + t PK dt
V PK E t max
PK +V t PK When I + 0, R S + 0, M + 0 Average dV dt e(t) rises asymptotically to E. t PK and average dV dt do not exist. 3aV0 ) 2c L +a 2V ) ac 0L When I + 0, t max + 0 RS y34, For RT then dV + dV dt max dt 0 t max
4.5
4.6
+
dV dt max e de dt
1 ATN +w
* V0L (w2 * 3a2)) V0 (a 3 * 3aw2) ) c(a 2 * w 2) L

w (2ac
2
6.5
V0
w0 2 2ac V0 L
) c2
ea t max
NO DAMPING 5.0 5.1 5.2
+ E (1 * Cos (w0t)) ) C Iw0 + E w0 sin (w0t) )

I C
sin (w0t) 6.6
+
dV dt 0
I Cos (w t) 0 C
+ 0 when I + 0
+ a V0L (2a tmax) ) c (1a tmax) ea tmax
dV dt max
5.3
t PK
* tan*1 CEI w0
5.4
V PK
5.5
+E)
tan
w0
E2
) w I22C2
w0 EC
I 1 p when I w0 2
APPENDIX D SNUBBER DISCHARGE dI DERIVATIONS dt

OVERDAMPED 1.0 i VC S a at sinh (wt) +w L S
dV dt AVG
+ tPK
I +C
5.6
t max
+ w10
* +
1
V PK
5.7
dV dt max
+0
1.1
i PK
+ VC S
E 2w0 2 C 2 I 2
) + w0E when I+ 0
1.2
t PK
1 tanh 1 w +w a
CS LS
e a t
PK
CRITICAL DAMPING 6.0 6.1
e + E * V0 (1 * at)e *at ) cte *at L de dt
CRITICAL DAMPED 2.0 i
+ a VOL (2 * at) ) c(1 * at) e*at

2
+ VLCS
S
te at
6.2
c )2V 0L t PK + c a) V0
L
2.1
i PK t PK
+ 0.736 VRCS
S 1 +a
2.2
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UNDERDAMPED VC S at 3.0 i w LS e sin (wt)
3.1
i PK t PK
+ VC S
3.2
1 tan 1 w +w a
NO DAMPING 4.0 i VC S +w L sin (wt) CS LS
CS LS
e a t
PK
4.1
i PK t PK
+ VC S + 2pw
4.2
RS t=0 VCS CS i
LS
+ 0, VCS + INITIAL VOLTAGE

INITIAL CONDITIONS :
Figure 6.41. Equivalent Circuit for Snubber Discharge
BIBLIOGRAPHY Bird, B. M. and K. G. King. An Introduction To Power Electronics. John Wiley & Sons, 1983, pp. 250281. Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976. Gempe, Horst. Applications of Zero Voltage Crossing Optically Isolated TRIAC Drivers, AN982, Motorola Inc., 1987. Guide for Surge Withstand Capability (SWC) Tests, ANSI 337.90A-1974, IEEE Std 4721974. IEEE Guide for Surge Voltages in Low-Voltage AC Power Circuits, ANSI/IEEE C62.41-1980, IEEE Std 5871980. Ikeda, Shigeru and Tsuneo Araki. The dI Capability of
dt
Kervin, Doug. The MOC3011 and MOC3021, EB-101, Motorola Inc., 1982. McMurray, William. Optimum Snubbers For Power Semiconductors, IEEE Transactions On Industry Applications, Vol. IA-8, September/October 1972. Rice, L. R. Why R-C Networks And Which One For Your Converter, Westinghouse Tech Tips 5-2. Saturable Reactor For Increasing Turn-On Switching Capability, SCR Manual Sixth Edition, General Electric, 1979. Zell, H. P. Design Chart For Capacitor-Discharge Pulse Circuits, EDN Magazine, June 10, 1968.
Thyristors, Proceedings of the IEEE, Vol. 53, No. 8, August 1967.
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Automatic AC Line Voltage Selector
Prepared by: Alfredo Ochoa, Alex Lara & Gabriel Gonzalez Thyristors Applications Engineers
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APPLICATION NOTE
well known, there is no arcing with the triac, which can also be very important in some applications. The main disadvantages of the mechanical switches or selectors appear when they are driving high current levels that can cause arcing and sparks on their contacts each time they are activated or deactivated. Because of these kind of effects the contacts of the switches get very significantly damaged causing problems in the functionality of the equipment or appliances. DEFINITIONS Control Transformers. This transformer consists of two or more windings coupled by a common or mutual magnetic field. One of these windings, the primary, is connected to an alternating voltage source. An alternating flux will be produced whose amplitude will depend on the primary voltage and number of turns. The mutual flux will link the other winding, the secondary, in which it will induce a voltage whose value will depend on the number of secondary turns. When the numbers of primary and secondary turns are properly proportioned, almost any desired voltage ratio or ratio of transformation can be obtained. This transformer is also widely used in low power electronic and control circuits. There it performs such functions as matching the source impedance and its load for maximum power transfer, isolating one circuit from another, or isolating direct current while maintaining AC continuity between two circuits.
INTRODUCTION In some cases, appliances and equipment are able to operate when supplied by two different levels of AC line voltage to their main terminals (120V or 240V). This is why, it is very common that appliances and equipment have mechanical selectors or switches as an option for selecting the level of voltage needed. Nevertheless, it is also very common that these types of equipment can suffer extensive damage caused for not putting the selector in the right position. To prevent these kind of problems, thyristors can be used as a solution for making automatic voltage selectors in order to avoid possibilities of equipment damage due to over or low voltages AC line supplied to them. Thyristors can take many forms, but they have certain things in common. All of them are solid state switches, which act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. A useful application of triacs is a direct replacement for mechanical selectors, relays or switches. In this application, the triac furnishes onoff control and the power regulating ability of the triac is not utilized. The control circuitry for these applications is usually very simple and these circuits are useful in applications where simplicity and reliability are important. In addition, as is
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The following schematic diagram shows an automatic voltage selector for AC voltage supply of 110V/220V and
Control Transformer 220 V/24 V 250 mA 110 V or 220 V? 1N4007
load of 10 Amp rms max. Loads can be equipment or any kind of appliances:
330
330
W
1N4735
LM339
10 k
330 F
1N5349
2.4 k
W
+ LM339 10 k
820
Main Transformer 110 V 220 V TO LOAD EQUIPMENT
2.4 k
MOC3022
470
W
1k
51
W
MAC15A8 470
2N2222 1k
10 nF
1.6 k
51
W
MAC15A8
10 nF
MOC3022
2N2222
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When the main terminals of the equipment are connected to the AC line voltage, one of the comparators (LM339) keeps its output at low level and the other one at high level because of the voltage references connected to their inverter and noninverter input pins. Therefore, one of the transistors (2N2222) is activated allowing current through the LED of the optocoupler, and which triggers one of the triacs (MAC15A8) that then provides the right level of AC line voltage to the main transformer of the equipment by connecting one of the primary windings through the triac triggered. The operational range, in the previous circuit, in the low AC line voltage condition (110V) is from 100 Vrms to 150 Vrms. This means, the triac that is driving the winding of the main transformer for 110V would keep itself triggered whenever the input voltage in the control transformer is within 100 and 150 Vrms. The operation range in high AC line voltage condition (220V) is from 180 Vrms to 250 Vrms, therefore, the triac that is driving the winding of the main transformer for 220V would keep itself triggered whenever the voltage in the control transformer is within 180 and 250 Vrms. Another very important item to take into consideration is the operational range of environmental temperature which is from 0C to 65C. If the circuit is working outside of these temperature limits, it very probably will experience unreliable functionality. In conclusion, this automatic voltage selector provides a very important protection for any kind of voltage sensitive equipment or appliances against the wrong levels of AC line input voltages. It eliminates the possibility of any damage in the circuitry of the equipment caused by connecting low or high voltage to the main terminals. In addition, the total price of the electronic circuitry is inexpensive when compared to the cost of the equipment if it suffers any damage.
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Electronic Starter for Flourescent Lamps
http://onsemi.com Prepared by: Alfredo Ochoa, Alex Lara & Gabriel Gonzalez Thyristors Applications Engineers
APPLICATION NOTE
voltage protectors, as well as simply turning devices on and off. Thyristors are used to control motors, incandescent and fluorescent lamps, and many other kinds of equipment. Although thyristors of all sorts are generally rugged, there are several points to keep in mind when designing circuits using them. One of the most important parameters to respect is the devices rated limits on rate of change of voltage and current (dV/dt and di/dt). If these are exceeded, the thyristor may be damaged or destroyed. DEFINITIONS Ambient Sound Levels. Background noise generated by ballast and other equipment operating in a building. Arc. Intense luminous discharge formed by the passage of electric current across a space between electrodes. Ballast. An electrical device used in fluorescent and high intensity discharge (HID) fixtures. It furnishes the necessary starting and operating current to the lamp for proper performance. Electrode. Metal filament that emits electrons in a fluorescent lamp. Fluorescent lamp. Gas filled lamp in which light is produced by the interaction of an arc with phosphorus lining the lamps glass tube. Fluorescent light circuit. Path over which electric current flows to operate fluorescent lamps. Three major types of fluorescent lighting circuits are in use today, preheat, instant start (slimline) and rapid start. Instant start (slimline). A class of fluorescent. Ballast provides a high starting voltage surge to quickly light the lamp. All instant start lamps have a single pin base and can be used only with instant ballast. Rapid Start Lamps. Fluorescent lamps that glow immediately when turned on and reach full brightness in about 2 seconds. Preheat Lamp. A fluorescent lamp in which the filament must be heated before the arc is created. This application note is designed for Preheat Start Lamp circuit. The description of the functionality of this Lamp is described below:
INTRODUCTION In lighting applications for fluorescent lamps the choice of the starter switch to be used is always very important for the designers: the cost, reliability, ruggedness, and ease to be driven must always be kept in mind. This is especially important in lighting circuits where the designer has to optimize the operating life of the fluorescent lamps by using the right starter switch. In the large family of electronic switches, the thyristor must be considered as a low cost and powerful device for lighting applications. Thyristors can take many forms, but they have certain features in common. All of them are solid state switches that act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. Silicon controlled rectifiers (SCRs) and triacs are both members of the thyristor family. SCRs are unidirectional devices while triacs are bidirectional. A SCR is designed to switch load current in one direction, while a triac is designed to conduct load currents in either direction. Structurally, all thyristors consist of several alternating layers of opposite P and N silicon, with the exact structure varying with the particular kind of device. The load is applied across the multiple junctions and the trigger current is injected at one of them. The trigger current allows the load current to flow through the device setting up a regenerative action which keeps the current flowing even after the trigger is removed. These characteristics make thyristors extremely useful in control applications. Compared to a mechanical switch, a thyristor has a very long service life and very fast turn on and turn off times. Because of their fast reaction times, regenerative action, and low resistance, once triggered, thyristors are useful as power controllers and transient over
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HOW THE LAMP WORKS (Using the conventional glowtube starter)
Neon Gas Fluorescent Coating Starter
Coated Filament
(Argon Gas) Mercury Droplets
Ballast Inductor
VAC
The above Figure illustrates a fluorescent lamp with the conventional glowtube starter. The glowtube starter consists of a bimetallic switch placed in series with the tube filament which closes to energize the filaments and then opens to interrupt the current flowing through the ballast inductor, thereby, generating the high voltage pulse necessary for starting. The mechanical glowtube starter is the circuit component most likely to cause unreliable starting. The principle disadvantage of the conventional glowtube starter is that it has to open several times in the filament circuit to interrupt the current flowing through the
ballast inductor in order to generate the high voltage necessary for turningon the fluorescent lamp. However, those interactions decrease the life of the lamp considerably. Besides, the lamp turnson in around 3 seconds when it is using the conventional glowtube starter and it also causes degradation to the lamp. On the other hand, the following schematic diagrams show the electronic circuitry which substitutes the conventional glowtube starter for fluorescent lamps applications of 20 Watts and 40 Watts using a diode, SCR, and a TVS or zener clipper(s):
Fluorescent Lamp of 20 Watts

Switch A K Fluorescent Lamp 20 W Ballast Inductor
Clipper SA90A MCR1008 Gate Diode 1N4003
Line (120 V; 60 Hz)
Coated Filaments
Electronic Starter
Fluorescent Lamp of 40 Watts

White Switch Phase Line (120 V; 60 Hz) Neutral Fluorescent Lamp 40 W Coated Filaments 0.1 F Ballast Inductor Black Blue 30 Clipper SA170A Clipper SA30A MCR1008 Gate Diode 1N4003
W
A K
Electronic Starter
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The main reason why the previous circuits are different is due to the high voltage must be generated for each kind of lamp. This means, the inductor ballast for fluorescent lamps of 40 Watts provides higher voltage than the inductor ballast for lamps of 20 Watts, that is why, the electronic circuits have to be different. As an observation, even the conventional glowtube starters have to be selected Fluorescent Lamp of 20 Watts: according the power of the lamp, it means, there is not a general glowtube starter who can operate for all kinds of fluorescent lamps. The following plots show the voltage and current waveform in the electronic starter circuitry when the fluorescent lamps is turnedon:
Vp=160V Vp=78V Ch1 Voltage Time before the Lamp turnson
Ch2 Current
Ip=1.2Amp
When the switch is turnedon, the voltage across the Clipper (SA90A) is the same as the voltage of the AC Line (Vpeak=160V), and since the Clipper allows currentflow through itself only once its VBR is reached (100V peak), the SCR (MCR1008) turnson and closes the circuit to energize the filaments of the fluorescent lamp. At this time, the current across the circuit is around 1.2A peak, and once the lamp has got enough heat, it decreases its dynamic resistance and permits currentflow through itself which causes the voltage across the Clipper to decrease to around
78 Vpeak. This effect makes the clipper turn off, since the voltage is less than the VBR of the device (SA90A), and because the clipper turns off, the SCR also turnsoff, and opens the circuit to interrupt the current flowing through the ballast inductor, thereby, generating the high voltage pulse necessary for starting the lamp. The time that the fluorescent lamp will take before to turnon is around 400 msecs by using the electronic starter. It is a faster starter then when the lamp is using the conventional glowtube starter.
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Fluorescent Lamp of 40 Watts:
Vp=230V Vp=140V Ch1 Voltage Time before the Lamp turnson
Ch2 Current
Ip=2.1Amp
The operation of the electronic starter circuit of 40 watts is similar than for 20 watts, the only difference between them is that the Inductor Ballast of 40 watts generates higher voltage than the inductor ballast of 20 watts. That is why the schematic circuit for lamps of 40 watts has two clippers and one snubber inside its control circuit. Besides, the current flowing through this circuit is around 2.1A peak and it appears around 550 msecs (which is the time that the lamp takes before it turn itself on), longer than in the electronic starter circuit of 20 watts. In conclusion the electronic starter circuits (for 20 and 40 watts) are more reliable than the conventional glowtube
starters since the lamps turnon faster and more efficiently increasing their lifetime considerably. Besides, the total price of the electronic devices is comparable with the current starters (glowtube). In summary, it is also important to mention that the range of the AC voltage supply to the electronic starter circuits must be from 115Vrms to 130Vrms for operating correctly. If it is not within this voltage range the circuits may not be able to operate in the correct way causing unreliable starting of the lamp. Also, extreme environmental temperatures could effect the right functionality of the electronic starters but it is a fact that they can operate between 15C to 40C.
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Momentary Solid State Switch for Split Phase Motors

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APPLICATION NOTE
INTRODUCTION In control applications for motors the choice of the solid state switch to be used is always very important for the designers: the cost, reliability, ruggedness, and ease to be driven must always be kept in mind. This is especially important in motor control circuits where the designer has to optimize the circuitry for controlling the motors in the correct and efficient way. In the large family of electronic switches, the thyristor must be considered as a low cost and powerful device for motor applications. Thyristors can take many forms, but they have certain features in common. All of them are solid state switches which act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. Because Thyristors are reliable solid state switches, they have many applications, especially as controls. A useful application of triac is as a direct replacement for an AC mechanical relay. In this application, the triac furnishes onoff control and the power regulating ability of the triac is utilized. The control circuitry for this application is usually very simple, consisting of a source for the gate signal and some type of small current switch, either mechanical or electrical. The gate signal can be obtained from a separate source or directly from the line voltage at terminal MT2 of the triac. One of the most common uses for thyristors is to control AC loads such as electric motors. This can be done either by controlling the part of each AC cycle when the circuit conducts current (Phase control) or by controlling the
number or cycles per time period when current is conducted (cycle control). In addition, thyristors can serve as the basis of relaxation oscillators for timers and other applications. DEFINITIONS SplitPhase Motor. SplitPhase motors have two stator windings, a main winding and an auxiliary winding, with their axes displaced 90 electrical degrees in space. The auxiliary winding has a higher resistancetoreactance ratio than the main winding, so that the two currents are out of phase. The stator field thus first reaches a maximum about the axis of one winding and then somewhat later in time (about 80 to 85 electrical degrees) reaches a maximum about the axis of the winding 90 electrical degrees away in space. The result is a rotating stator field which causes the motor to start. At about 75 percent of synchronous speed, the auxiliary winding is cut out by a centrifugal switch. The below figure shows an schematic representation of a splitphase motor:
Line
Main Winding
Centrifugal Switch
Auxiliary Winding
When the line voltage is applied, the current flows through both windings and the result is a rotating stator field which causes the motor to start. At about 75 percent of synchronous speed, the auxiliary winding is cut out by a centrifugal switch.
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The following figure shows a conventional schematic diagram using a relay for controlling a splitphase fractional horsepower motor (the compressor of a refrigerator for example):
Bimetal Switch Line Thermostat Switch
Start Winding IS IO
Main Winding
In the previous figure the thermostatswitch is controlling the workingcycle of the compressor and it is dependent on the set point of environment temperature which has to be selected according to the temperature needed. The bimetal switch protects the compressor against overload and the relay controls the momentary switch which cuts out the starter winding once the motor has reached about 75 percent of the synchronous speed (after around 300 msecs). The below plot shows the current flowing through the compressor (1 Phase, 115Vac, 60Hz, 4.1Arms) when it starts to operate under normal conditions:
Momentary Switch
Neutral
This plot shows the total current flowing through the compressor when it starts to operate and the time in which the current reaches the maximum value (Is) due to the start of the motor. After this time (210 msecs) the start winding
is cut out by the momentary switch and then the current decreases to reach the nominal current of the compressor (Io=4.1 Arms).
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The following schematic diagrams show the way triacs can substitute for the relay and how they can be triggered by using different control options:
Bimetal Switch Line Thermostat Switch
Start Winding
Normal Op. Winding
Momentary Solid State Switch
MT2 Gate MT1 MAC8D, M Main Winding Solid Connected to Neutral
Neutral 0 lg Negative Triggering for Quadrants 2 and 3 Nonsensitive Gate TRIAC VCC
Logic Signal Gate
MT2
MT1
Neutral
Bimetal Switch Line
Direct Negative Logic Driven by Microcontroller
MT2 RS Gate MT1 MAC8SD, M CS
mC
HC
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In the first diagram, the triac (MAC8D,M) is making the function of the conventional relays momentary switch, and it can be triggered by using a transistor as shown in the above schematic or through the signals of a microcontroller. Since this triac (MAC8D,M) is a snubberless device, it does not need a snubber network for protecting itself against dV/dt phenomena. In the second diagram the triac (MAC8SD,M) is also performing the function of the relays momentary switch,
120 V/14 V
but since this device is a sensitive gate triac, it only needs a very low Igt current for triggering itself, therefore, this option is especially useful in applications where the level of the current signals are small. On the other hand, the following figure shows a practical solid state solution for controlling the compressor with the operating characteristics mentioned previously (1 Phase, 115Vac, 60Hz, 4.1 Arms) :
1000 mF Neutral
280
W W
10 k
+ +
1N4003 LM741C
10 k
1.3 k 1000 mF
10 F
100
W
510
2N6520
10 k Bimetal Switch Line Thermostat Switch
Start Winding
Normal Op. Winding
Neutral
MT2 MAC8D, M MT1 Main Winding Solid Connected to Neutral
Neutral
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When the thermostat switch is activated, the triac (MAC8D,M) turnson and allows current flow through the starter winding. This current is around 20 Arms because at the start of the motor (see current plot shown previously), after around 210msec, the triac turnsoff and blocks the current flowing through the starter winding. In that moment, the total current flowing through the motor decreases until it reaches the nominal current (4.1 Arms) and the motor continues operating until the thermostat switch is switched off. Since the triac operates for very short times (around 210 msec), it does not need a heat sink, therefore, it can be placed on the control board without any kind of problems. In the previous schematic diagram the triac of 8 Arms (MAC8D,M), was selected based on the nominal and start current conditions of the compressor previously described (1 Phase, 115Vac, 60Hz, 4.1Arms). Therefore, it is important to mention that in these kind of applications, the triacs must be selected taking into consideration the characteristics of each kind of motor to control (nominal and start currents, frequency, Vac, power, etc). Also, it is important to remember that it is not possible to have a general reference for selecting the right triacs for each motor control application. In conclusion, the solid state solution described previously, provides a more reliable control than the conventional momentary switch controlled by a relay since the thyristors do not cause any kind of sparks when they start to operate. In addition, the total price of the electronic components do not exceed the price of the conventional relay approach. In summary, it is also important to mention that extreme environmental temperatures could affect the functionality of this momentary solid state switch, but it is a fact that the triac solution is able to operate between 0C to 65C. Another important consideration is to include in the power circuit of the motor the right overload switch in order to protect the motor and the triacs against overload phenomena.
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AND8008/D
Solid State Control Solutions for Three Phase 1 HP Motor

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APPLICATION NOTE
INTRODUCTION In all kinds of manufacturing, it is very common to have equipment that has three phase motors for doing different work functions on the production lines. These motor functions can be extruders, fans, transport belts, mixers, pumps, air compressors, etc. Therefore, it is necessary to have equipment for controlling the start and stop of the motors and in some cases for reversing them. Actually, one of the most common solutions for performing this control functions is by using three phase magnetic starters. It consists of a block with three main mechanical contacts which provide the power to the three main terminals of the motor once its coil is energized. However, the magnetic starter has a lot of disadvantages and the most common appear when they are driving high current levels that can cause arcing and sparks on their contacts each time they are activated or deactivated. Because of these kind of effects the contacts of the magnetic starters get very significantly damaged causing problems in their functionality. With time it can cause bad and inefficient operation of the motors. This is why, thyristor should be considered as a low cost alternative and indeed a powerful device for motor control applications. Thyristors can take many forms but they have certain features in common. All of them are solid state switches that act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device.
DEFINITIONS Three phase induction motor. A three phase induction motor consists of a stator winding and a rotor of one of the two following types: one type is a squirrelcage rotor with a winding consisting of conducting bars embedded in slots in the rotor iron and short circuited at each end by conducting end rings. The other type is a wound rotor with a winding similar to and having the same number of poles as the stator winding, with the terminals of the winding being connected to the slip rings or collector rings on the left end of the shaft. Carbon brushes bearing on these rings make the rotor terminals available at points external to the motor so that additional resistance can be inserted in the rotor circuit if desired. Three phase voltages of stator frequency are induced in the rotor, and the accompanying currents are determined by the voltage magnitude and rotor impedance. Because they are induced by the rotating stator field, these rotor currents inherently produce a rotor field with the same number of poles as the stator and rotating at the same speed with respect to the stationary rotor. Rotor and stator fields are thus stationary with respect to each other in space, and a starting torque is produced. If this torque is sufficient to overcome the opposition to rotation created by the shaft load the motor will come up to its operating speed. The operating speed can never equal the synchronous speed of the stator field. The following figure shows a three phase 1HP motor controlled through a conventional magnetic starter which has an overload relay for protecting the motor against overload phenomena.
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Power Schematic
220 Vrms 60 Hz L1 Start A Stop L2 L3
NC
OL
OL
OL
3 Phase Motor 1 H.P.
When the start button is pushed on, the coil of the magnetic starter (A) is energized, thereby, the mechanical switch contacts close allowing currentflow through the motor which starts it to operate. If the stop button is pushed, the coil (A) will be deenergized causing the motor to stop because of the mechanical switch contacts opened. In addition, if an overload phenomena exists in the circuit of the motor, the switch contact (NC) of the overload relay will open deenergizing the coil and protecting the motor against any kind of damage.
Magnetic starters have a lot of disadvantages like arcing, corrosion of the switch contacts, sparks, noisy operation, short life span, etc. Therefore, in some motor applications, it is not useful to control the motors by using magnetic starters since the results can be undesirable. On the other hand, the following schematic diagrams show how thyristors can perform the same control function for starting and stopping a three phase 1HP motor. In addition, the diagrams below show an over load circuit for protecting the motor against overload phenomena.
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Line Voltage 220 Vrms 60 Hz L2 510
Diagram 1
L3 510
L1 510
W
MAC8N
W
MAC8N
W
MAC8N
MOC3062 To Over Load Protection Circuit for Line 1
MOC3062
MOC3062 To Over Load Protection Circuit for Line 3
Current Transformer
Current Transformer
Diagram 1 shows how three triacs (MAC8M) substitute the mechanical contacts of the conventional magnetic starter (shown previously) for supplying the power to the three phase 1HP motor once the triacs are triggered. It is important to mention that the optocoupler devices (MOC3061) will supply the signal currents to the triacs and hence the motor keeping the same phase shifting (120 electrical degrees) between lines. This is because these optocuplers (MOC3061) have zero crossing circuits within them. Another important thing must be considered as a protection for the triacs (MAC8M) against fast voltage transients, is a RC network called snubber which consists of a series resistor and capacitor placed around the triacs. These components along with the load inductance from a series CRL circuit. Many RC combinations are capable of providing acceptable performance. However, improperly used snubbers can cause unreliable circuit operation and damage
to the semiconductor device. Snubber design involves compromises. They include cost, voltage rate, peak voltage, and turnon stress. Practical solutions depend on the device and circuit physics. Diagram 2 shows an electronic overload circuit which provides very reliable protection to the motor against over load conditions. The control signals for the two electronic overload circuits are received from the shunt resistors connected in parallel to the two current transformers placed in two of the three main lines (L1, L3) for sensing the current flowing through the motor when it is operating. The level of the voltage signals appearing in the shunt resistors is dependent on the current flowing through each main line of the motor. Therefore, if it occurs, that an over load condition in the power circuit of the motor, that voltage level will increase its value causing the activation of the electronic overload circuits which will stop the motor by protecting it against the overload condition experienced.
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Over Load Protection Circuit for Line 1
10 k Wire Conductor Line 1 1k 0.1 Shunt 1k 10 k
Diagram 2
2k
W m
220 F
W W
+12 Vdc +12 Vdc +12 Vdc + LM324 10 k 12 Vdc 12 Vdc 25 k MUR160 1k
LM324 + +12 Vdc LM324 MUR160
12 Vdc
22 k
W
+12 Vdc 2k
+12 Vdc Output Signal Connected to OR Gates Input One 1k
+ LM324
MUR160
220 F
1k 12 Vdc
4.3 k
W
Over Load Protection Circuit for Line 3
10 k
2k
W m
Wire Conductor Line 3 1k 0.1 Shunt 1k 10 k
220 F
W W
+12 Vdc +12 Vdc +12 Vdc + LM324 10 k 12 Vdc 12 Vdc 25 k MUR160 1k
LM324 + +12 Vdc LM324 MUR160
12 Vdc
22 k
W
+12 Vdc 2k
+12 Vdc Output Signal Connected to OR Gates Input Two 1k
+ LM324
MUR160
220 F
1k 12 Vdc
4.3 k
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Start/Stop Control Circuit
Output Signal from Over Load Protection Line 1 Output Signal from Over Load Protection Line 3 MC14075
Diagram 3
Stop +12 Vdc Button
+12 Vdc 510
1k
CD MC14013 1.5 k Q
W
MOC3062
W
2N2222
+12 Vdc
Start Button
SD
MOC3062
1k
MOC3062
Diagram 3 shows the main electronic control circuit for controlling the start and stop of the motor each time it is needed. If the start button is pushed on, the Flip Flop (MC14013) is activated triggering the transistor (2N2222) which turns on the optocouplers LEDs which in turn the three triacs (MAC8M) get triggered and finally starts the motor. The motor will stop to operate, whenever the stop
button is pushed or any overload condition occurs in the power circuit of the motor. The following plot shows the motors start current waveform on one of the three phases when the motor starts to operate under normal operation conditions and without driving any kind of mechanical load:
Ipk = 28.8 Amp start current
Ipk = 2.8 Amp Normal operation
128 msec
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This other plot shows the motors start current waveform of the three phases when the motor start to operate under normal operation conditions and without mechanical load.
Phase R start current Waveform
Phase S start current Waveform
Phase T start current Waveform
The previous plots show the maximum start current IPK of the motor when it starts to operate and how long it takes before the current reaches its nominal value. Here, It is important to mention that the triacs (MAC8N) were selected by taking into consideration the motors start current value as well as the ITSM capability of these devices. Therefore, if it is needed to control motors with higher power (more than 1HP), first, it would be necessary to characterize them in order to know their current characteristics. Next be able to select the right triacs for controling the motor without any kind of problems. Another important item must be considered if it is needed
to control motors with higher power. These are the electronic overload circuits, which have to be adjusted taking into consideration the level of overload current that is needed to protect, and is dependent on the kind of motor that is being controlled. Based in the previous diagrams and plots, it has been proven that triacs can substitute the function of the magnetic starters for starting and stopping a three phase 1HP motor as well as for protecting it against overload conditions. The following schematics show a solid state solution for controlling and reversing a three phase 1HP motor:
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Reverse Control Schematic
+12 Vdc Right S MC14013 1k +12 Vdc Stop From Over Load Protection Circuit R MC14075 MC14075 +12 Vdc Left S 1k Q
Schematic 1
MC14013 R 510
1k
W
MC14075
10 k
W
+12 Vdc 2k
+12 Vdc
+12 Vdc +12 Vdc 10 k
220 F
LM339
W W
1.5 k
Right 2N2222 4.3 k
W
+12 Vdc
MOC3062 3 MOC3062 2
10 k
W
+12 Vdc
+12 Vdc
+12 Vdc 510 10 k
220 F 2k
LM339
W W
W
Left
MUR160 MOC3062 1 MOC3062 4 MOC3062 5
1.5 k
2N2222
4.3 k
MUR160
Schematic 1 shows the control diagram for controlling and reversing the motor depending on which direction it is needed to operate. If the rightbutton is pushedon, the triacs number 1, 2, and 3 (shown in the schematic 2) will be activated, thereby, the motor will operate in the right direction. If the left button is pushedon, the triacs numbered 1, 4, and 5 will be activated causing the left operation of the motor. Because of the design of the control circuit, it is possible to reverse the motor without stopping it once it is operating in right direction. This means, it is not necessary to stop the motor in order to reverse itself.
Nevertheless, it is important to mention that the control circuit takes a delaytime (of around 3 seconds) before it activates the other triacs (1,4,5) for reversing the motor. This delay is to assure that the triacs operating (1,2,3) will be completely in the off state before it turnson those other triacs. This delaytime is very important because if the triacs for reversing the motor are activated before the other triacs triggered have reached their completely turnedoff state, it may cause a big short circuit between phases. If this happens the triacs will be damaged.
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Power Schematic
220 Vrms 60 Hz L1 L2 L3
Schematic 2
510
W
MAC8N
51
510
W
MAC8N
51
510
W
MAC8N
51
510
W
MAC8N
51
510
W
MAC8N
51
MOC3062 1
MOC3062 2 10 nF
MOC3062 3 10 nF
MOC3062 4 10 nF
MOC3062 5 10 nF 10 nF
To Over Load Circuit 1
To Over Load Circuit 2
Schematic 2 shows the power diagram for reversing a three phase 1HP motor. The way it makes this reverse function control is by changing the phasesorder supplied to the motor through the triacs (number 4 and 5) and it is based in the motors principle for reversing itself. This diagram also shows two current transformer placed in two of the three main lines of the motor for sending the control signals to the electronic overload circuit described previously. So this means, that the same overload concept is applicable to these schematics as well as the motors start current waveforms and characteristics shown and explained previously. In conclusion, it is proven that thyristors can substitute to the magnetic starters for making three phase motor control function in more efficient ways. Because thyristors are very reliable power switches, they can offer many advantages in motor applications. Some of the advantages of triacs as replacements for relays include: High Commutating di/dt and High Immunity to dv/dt @ 125C
Small size and light weight. Safety freedom form arcing and spark initiated Long life span contact bounce and burning
eliminated. Fast operation turnon in microseconds and turnoff in milliseconds. Quiet operation. The above mentioned points are only some of the big advantages that can be had if thyristors are used for making motor control function. Besides, the total cost of the previous control and power circuits does not exceed to the cost of the conventional magnetic starters. One more consideration is that extreme environmental temperatures could effect the functionality of the electronic control circuits described herein. Therefore, if the operation is needed under extreme ambient temperatures, the designer must evaluate the parameter variation of all the electronic devices in order to assure the right operation in the application circuit. explosions.
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AND8015/D
Long Life Incandescent Lamps using SIDACs

Prepared by: Alfredo Ochoa, Alex Lara & Gabriel Gonzalez Thyristor Application Engineers
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APPLICATION NOTE
Abstract
Since the invention of the incandescent lamp bulb by the genius Thomas A. Edison in 1878, there has been little changes in the concept. Nowadays we are currently use them in our houses, and they are part of our comfort but, since we are more environmentally conscious and more demanding on energy cost saving products, along with their durability, we present here an application concept involved this simple incandescent lamp bulb in conjunction with the Bilateral Trigger semiconductor device called SIDAC, offering an alternative way to save money in energy consumption and also giving a longer life time to the lamp bulbs.
Theory of the SIDAC
The SIDAC is a high voltage bilateral trigger device that extends the trigger capabilities to significantly higher voltages and currents than have been previously obtainable, thus permitting new, cost effective applications. Being a bilateral device, it will switch from a blocking state to a
conducting state when the applied voltage of either polarity exceeds the breakover voltage. As in other trigger devices, the SIDAC switches through a negative resistance region to the low voltage onstate and will remain on until the main terminal current is interrupted or drops below the holding current. SIDACs are available in the large MKP3V series and the economical, easy to insert, small MKP1V series axial lead packages. Breakdown voltages ranging from 110 to 250V are available. The MKP3V devices feature bigger chips and provide much greater surge capability along with somewhat higher RMS current ratings. The high voltage and current ratings of SIDACs make them ideal for high energy applications where other trigger devices are unable to function alone without the aid of additional power boosting components. The following figure shows the idealized SIDAC characteristics:
ITM IH
VTM Slope = Rs IS IDRM VS I(BO) V(BO) VDRM
Rs = (V(BO) VS) (IS I(BO))
Once the input voltage exceeds V(BO), the device will switch on to the forward onvoltage VTM of typically 1.1 V and can conduct as much as the specified repetitive peak on state current ITSM of 20A (10s pulse, 1KHz repetition frequency).
SIDACs can be used in many applications as transient protectors, Over Voltage Protectors, Xeon flasher, relaxation oscillators, sodium vapor lamp starters, etc.
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This paper explains one of the most typical applications for SIDACs which is a long life circuit for incandescent lamps. The below schematic diagrams show the configurations Option 1: ac line voltage 110V, 60Hz or 50Hz of a SIDAC used in series with an incandescent lamp bulb through a fixed phase for the most typical levels of ac line voltages:
SIDAC MKP1V120RL
AC Line 110V, 60 Hz
100 WATTS 110V
Option 2: ac line voltage 220V, 60Hz or 50 Hz
SIDAC MKP1V120RL
AC Line 220V, 60 Hz
100 WATTS 220V
This is done in order to lower the RMS voltage to the filament, and prolong the life of the bulb. This is particularly useful when lamps are used in hard to reach locations such as outdoor lighting in signs where replacement costs are high. Bulb life span can be extended by 1.5 to 5 times depending on the type of lamp, the amount of power reduction to the filament, and the number of times the lamp is switched on from a cold filament condition. The operating cost of the lamp is also reduced because of the lower power to the lamp; however, a higher wattage bulb is required for the same lumen output. The maximum
possible energy reduction is 50% if the lamp wattage is not increased. The minimum conduction angle is 90 because the SIDAC must switch on before the peak of the line voltage. Line regulation and breakover voltage tolerances will require that a conduction angle longer than 90 be used, in order to prevent lamp turnoff under low line voltage conditions. Consequently, practical conduction angles will run between 110 and 130 with corresponding power reductions of 10% to 30%. The following plots show the basic voltage and current waveforms in the SIDAC and load:
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Incandescent Lamp of 100W, 110V, 60Hz
Ch1 Voltage Vpk = 123V V(BO) Ch2 Current Ipk = 0.96A
V(BO)
Conduction Angle
Incandescent Lamp of 50W, 220V, 60Hz
Ch1 Voltage Vpk = 121V V(BO) Ch2 Current Ipk = 0.33A
V(BO)
Conduction Angle
In both previous cases, once the ac line voltage reaches the V(BO) of the SIDAC (MKP1V120RL), it allows current flow to the incandescent lamp causing the turnon of this at some specific phaseangle which is determined by the SIDAC because of its V(BO). The fast turnon time of the SIDAC will result in the generation of RFI which may be noticeable on AM radios operated in the vicinity of the lamp. This can be prevented by the use of an RFI filter. A possible filter can be the following: connect an inductor (100H) in series with the SIDAC and a capacitor (0.1F) in parallel with the SIDAC and inductor. This filter causes a ring wave of current through the SIDAC at turn on time. The filter inductor must be selected for resonance at a frequency above the upper frequency limit of human hearing and as low below the start of the AM broadcast band as possible for maximum harmonic
attenuation. In addition, it is important that the filter inductor be nonsaturating to prevent di/dt damage to the SIDAC. The sizing of the SIDAC must take into account the RMS current of the lamp, thermal properties of the SIDAC, and the cold start surge current of the lamp which is often 10 to 20 times the steady state load current. When lamps burn out, at the end of their operating life, very high surge currents which could damage the SIDAC are possible because of arcing within the bulb. The large MKP3V device is recommended if the SIDAC is not to be replaced along with the bulb. In order to establish what will be the average power that an incandescent lamp is going to offer if a SIDAC (MKP1V120RL) is connected in series within the circuit, some ideal calculations could be made for these purposes
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Example: Incandescent lamp of 100W (120V, 60Hz).
200 v(t): i(t) x 100: VL(t): v(t): Voltage waveform in the SIDAC l(t): Portion of current waveform applied to the load (Multiplied by a factor of 100 to make it more graphically visible) VL(t): Voltage waveform in the Load
Voltage / Current
100
100
200
0.002
0.004 time in seconds
0.006
0.008
In this case, the conduction angle is around 130 (6 msecs) in each half cycle of the sinusoidal current waveform, therefore, the average power of the lamp can be obtained by calculating the following operations:
eff
eff
Pav = ieffVLeff Pav = 91.357

8.33
10
*3
i(t) dt
2
2 T
8.33
10
*3
v(t) dt
2
2 T
Based on this, it is possible to observe that the average power output is a little bit lower than the original power of the lamp (100W), even though the conduction angle is being reduced because of the SIDAC. In conclusion, when a SIDAC is used to phase control an incandescent lamp, the operation life of the bulb is going to be extended by 1.5 to 5 times which represents a big economical advantage when compared to the total cost of the lamp if it is changed. In addition, the original power of the lamp is not going to be reduced considerably which assures the proper level of illumination for the area in which the incandescent lamp is being used for. Finally, since the SIDACs are provided in a very small axial lead package, they can be mounted within the same place that the incandescent lamp is placed.
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AND8017/D Solid State Control for Bi-Directional Motors

Prepared by: Alfredo Ochoa, Alex Lara & Gabriel Gonzalez Thyristor Application Engineers http://onsemi.com
APPLICATION NOTE
INTRODUCTION
Some split phase motors are able to operate in forward and reverse directions since they have two windings for these purposes. Depending on which winding is energized, the motor operates in that direction. These motors are especially used in applications for washing machines, transport belts, and all kinds of equipment in which the operation in both directions is needed. One of the most traditional way to control these kind of motors is through mechanical relays. Nevertheless, they have a lot of disadvantages which make them ineffective. This paper is going to show how triacs can substitute the function of the mechanical relays for controlling bidirectional motors offering a higher level of quality and reliability for control purposes. The triac is a three terminal ac semiconductor switch that is triggered into conduction when a low energy signal is applied to its gate. Unlike the silicon controlled rectifier or SCR, the triac will conduct current in either direction when turned on. The triac also differs from the SCR in that either a positive or negative gate signal will trigger the triac into conduction. The triac may be thought of as two complementary SCRs in parallel. The triac offers the circuit designer an economical and versatile means of accurately controlling ac power. It has several advantages over conventional mechanical switches.
Since the triac has a positive on and a zero current off characteristics, it does not suffer from the contact bounce or arcing inherent in mechanical switches. The switching action of the triac is very fast compared to conventional relays, giving more accurate control. A triac can be triggered by dc, ac, rectified ac or pulses. Because of the low energy required for triggering a triac, the control circuit can use any of many low cost solid state devices such as transistors, sensitive gate SCRs and triacs, optically coupled drivers, and integrated circuits.
DEFINITIONS
The twophase induction motor consists of a stator with two windings displaced 90 electrical degrees from each other in space and squirrel cage rotor or the equivalent. The ac voltages applied to the two windings are generally phase displaced from each other 90 in time. When the voltages magnitudes are equal, the equivalent of balanced two phase voltages is applied to the stator. The resultant stator flux is then similar to a threephase induction motor. The motor torque speed curves are also similar to those of a threephase motor. The twophase control motor is usually built with a high resistance rotor to give a high starting torque and a dropping torque speed characteristic. The following schematic diagram shows an ac split phase motor:
Switch 1
Switch 2
Line
Winding A
Winding B
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If switch 1 is activated, rotation in one direction is obtained; if switch 2 is activated, rotation in the other direction results. Since the torque is a function of the voltage supply, changing the magnitude of this changes the developed torque of the motor. The stalled torque is assumed to be linearly proportional to the rms control winding voltage. It is very common to add a resonant LC circuit connected between the motor windings in order to damp the energy stored by each motor winding inductance, avoiding
Split Phase Motor 1/4 Hp, 230 V RPM 1400
damage to the switches when the transition from one direction to the other occurs. In addition, this resonant LC circuit helps to have good performance in the motors torque each time it changes its rotation. The following schematic diagram shows how two triacs can control the rotation of a split phase motor depending in which winding is energized. In this case the motor selected for analysis purposes has the following technical characteristics: 230Vrms, 1.9 Arms, 1/4 Hp, 60Hz, 1400 RPM.
Winding 1 220 VAC 60 Hz
50 H
Winding 2 15 F
MAC210A10FP 2k G
MT2 MT1 51
MAC210A10FP
W
MOV
MT2 MT1 51
2k G
W
MOV
10 k
10 nF
10 k
10 nF
MOC3042
MOC3042
Direct Negative Logic Driven by Microcontroller
C HC
The micro is controlling the trigger of the triacs through optocouplers (MOC3042). The optocoupler protects the control circuitry (Microcontroller, Logic Gates, etc.) if a short circuit condition occurs within the power circuitry since these optocouplers insolate the control part of the general circuit. The MOVs protects the triacs against to the high voltage transients caused because of the motor rotation changes, so it is very important to add them in the power circuit, otherwise the triacs could be damaged easily. The snubber arrangement provides protection against dV/dt conditions occurring within the application circuit and the resonant LC circuit connected between the motors wind-
ings helps to have good performance in the torque of the motor when it changes its rotation. In the case that the motor is locked due to some mechanical problem within the application field, the maximum current peak flowing through the triacs would be 7.2 Amps (5.02 Amps rms), therefore, the triacs (MAC210A10FP) would not be damaged since they are able to handle up to 12 A rms. Nevertheless, it is recommended to add an overload protector in the power circuit of the motor in order to protect it against any kind of overload conditions which
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could damage the motor in a short period of time since the current flowing would be higher than its nominal value. In conclusion, it has been shown how triacs (MAC210A10FP) substitute the mechanical relays functions to control bidirectional motors offering many important advantages like reliable control, quiet operation, long life span, small size, light weight, fast operation, among others. These are only some of the big advantages that can be obtained if thyristors are used to control bidirectional motors. Besides, the total cost of the electronic circuitry does not exceed to the cost of the conventional mechanical relays. A very important consideration is that extreme environment temperatures could affect the functionality of the electronic devices, therefore, if operation under extreme ambient temperatures is needed, the designer must take into consideration the parameter variation of the electronic devices in order to establish if any kind of adjustment is needed within the electronic circuitry. Another important item to be considered by the designer is that the triacs have to be mounted on a proper heatsink in order to assure that the case temperature of the device does not exceed the specifications shown in the datasheet.
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SECTION 7 MOUNTING TECHNIQUES FOR THYRISTORS
Edited and Updated
INTRODUCTION Current and power ratings of semiconductors are inseparably linked to their thermal environment. Except for lead-mounted parts used at low currents, a heat exchanger is required to prevent the junction temperature from exceeding its rated limit, thereby running the risk of a high failure rate. Furthermore, the semiconductor industrys field history indicated that the failure rate of most silicon semiconductors decreases approximately by one half for a decrease in junction temperature from 160C to 135C.(1) Guidelines for designers of military power supplies impose a 110C limit upon junction temperature.(2) Proper mounting minimizes the temperature gradient between the semiconductor case and the heat exchanger. Most early life field failures of power semiconductors can be traced to faulty mounting procedures. With metal packaged devices, faulty mounting generally causes unnecessarily high junction temperature, resulting in reduced component lifetime, although mechanical damage has occurred on occasion from improperly mounting to a warped surface. With the widespread use of various plastic-packaged semiconductors, the prospect of mechanical damage is very significant. Mechanical damage can impair the case moisture resistance or crack the semiconductor die.
Figure 7.1 shows an example of doing nearly everything wrong. A tab mount TO-220 package is shown being used as a replacement for a TO-213AA (TO-66) part which was socket mounted. To use the socket, the leads are bent an operation which, if not properly done, can crack the package, break the internal bonding wires, or crack the die. The package is fastened with a sheet-metal screw through a 1/4 hole containing a fiber-insulating sleeve. The force used to tighten the screw tends to pull the package into the hole, causing enough distortion to crack the die. In addition the contact area is small because of the area consumed by the large hole and the bowing of the package; the result is a much higher junction temperature than expected. If a rough heatsink surface and/or burrs around the hole were displayed in the illustration, most but not all poor mounting practices would be covered.
PLASTIC BODY LEADS PACKAGE HEATSINK MICA WASHER
EQUIPMENT HEATSINK (1) MIL-HANDBOOK 2178, SECTION 2.2. (2) Navy Power Supply Reliability Design and Manufacturing Guidelines NAVMAT P4855-1, Dec. 1982 NAVPUBFORCEN, 5801 Tabor Ave., Philadelphia, PA 19120.
SOCKET FOR TO-213AA PACKAGE
SPEED NUT (PART OF SOCKET) SHEET METAL SCREW
Figure 7.1. Extreme Case of Improperly Mounting A Semiconductor (Distortion Exaggerated)
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In many situations the case of the semiconductor must be electrically isolated from its mounting surface. The isolation material is, to some extent, a thermal isolator as well, which raises junction operating temperatures. In addition, the possibility of arc-over problems is introduced if high voltages are present. Various regulating agencies also impose creepage distance specifications which further complicates design. Electrical isolation thus places additional demands upon the mounting procedure. Proper mounting procedures usually necessitate orderly attention to the following: 1. Preparing the mounting surface 2. Applying a thermal grease (if required) 3. Installing the insulator (if electrical isolation is desired) 4. Fastening the assembly 5. Connecting the terminals to the circuit In this note, mounting procedures are discussed in general terms for several generic classes of packages. As newer packages are developed, it is probable that they will fit into the generic classes discussed in this note. Unique requirements are given on data sheets pertaining to the particular package. The following classes are defined: Stud Mount Flange Mount Pressfit Plastic Body Mount Tab Mount Surface Mount Appendix A contains a brief review of thermal resistance concepts. Appendix B discusses measurement difficulties with interface thermal resistance tests.
TIR = TOTAL INDICATOR READING SAMPLE PIECE TIR h
REFERENCE PIECE
DEVICE MOUNTING AREA
Figure 7.2. Surface Flatness Measurement Surface Finish
Surface finish is the average of the deviations both above and below the mean value of surface height. For minimum interface resistance, a finish in the range of 50 to 60 microinches is satisfactory; a finer finish is costly to achieve and does not significantly lower contact resistance. Tests conducted by Thermalloy using a copper TO-204 (TO-3) package with a typical 32-microinch finish, showed that heatsink finishes between 16 and 64 -in caused less than 2.5% difference in interface thermal resistance when the voids and scratches were filled with a thermal joint compound.(3) Most commercially available cast or extruded heatsinks will require spotfacing when used in high-power applications. In general, milled or machined surfaces are satisfactory if prepared with tools in good working condition.
Mounting Holes
MOUNTING SURFACE PREPARATION In general, the heatsink mounting surface should have a flatness and finish comparable to that of the semiconductor package. In lower power applications, the heatsink surface is satisfactory if it appears flat against a straight edge and is free from deep scratches. In high-power applications, a more detailed examination of the surface is required. Mounting holes and surface treatment must also be considered.
Surface Flatness
Surface flatness is determined by comparing the variance in height (h) of the test specimen to that of a reference standard as indicated in Figure 7.2. Flatness is normally specified as a fraction of the Total Indicator Reading (TIR). The mounting surface flatness, i.e., h/TIR, if less than 4 mils per inch, normal for extruded aluminum, is satisfactory in most cases.
Mounting holes generally should only be large enough to allow clearance of the fastener. The large thick flange type packages having mounting holes removed from the semiconductor die location, such as the TO-3, may successfully be used with larger holes to accommodate an insulating bushing, but many plastic encapsulated packages are intolerant of this condition. For these packages, a smaller screw size must be used such that the hole for the bushing does not exceed the hole in the package. Punched mounting holes have been a source of trouble because if not properly done, the area around a punched hole is depressed in the process. This crater in the heatsink around the mounting hole can cause two problems. The device can be damaged by distortion of the package as the mounting pressure attempts to conform it to the shape of the heatsink indentation, or the device may only bridge the crater and leave a significant percentage of its heat-dissipating surface out of contact with the heatsink. The first effect may often be detected immediately by visual cracks in the package (if plastic), but usually an unnatural stress is imposed, which results in an early-life failure. The second effect results in hotter operation and is not manifested until much later.
(3) Catalog #87-HS-9 (1987), page 8, Thermalloy, Inc., P.O. Box 810839, Dallas, Texas 75381-0839.
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Although punched holes are seldom acceptable in the relatively thick material used for extruded aluminum heatsinks, several manufacturers are capable of properly utilizing the capabilities inherent in both fine-edge blanking or sheared-through holes when applied to sheet metal as commonly used for stamped heatsinks. The holes are pierced using Class A progressive dies mounted on four-post die sets equipped with proper pressure pads and holding fixtures. When mounting holes are drilled, a general practice with extruded aluminum, surface cleanup is important. Chamfers must be avoided because they reduce heat transfer surface and increase mounting stress. However, the edges must be broken to remove burrs which cause poor contact between device and heatsink and may puncture isolation material.
Surface Treatment
a resistivity of approximately 60C/W/in whereas air has 1200C/W/in. Since surfaces are highly pock-marked with minute voids, use of a compound makes a significant reduction in the interface thermal resistance of the joint. However, the grease causes a number of problems, as discussed in the following section. To avoid using grease, manufacturers have developed dry conductive and insulating pads to replace the more traditional materials. These pads are conformal and therefore partially fill voids when under pressure.
Thermal Compounds (Grease)
Many aluminium heatsinks are black-anodized to improve radiation ability and prevent corrosion. Anodizing results in significant electrical but negligible thermal insulation. It need only be removed from the mounting area when electrical contact is required. Heatsinks are also available which have a nickel plated copper insert under the semiconductor mounting area. No treatment of this surface is necessary. Another treated aluminum finish is iridite, or chromateacid dip, which offers low resistance because of its thin surface, yet has good electrical properties because it resists oxidation. It need only be cleaned of the oils and films that collect in the manufacture and storage of the sinks, a practice which should be applied to all heatsinks. For economy, paint is sometimes used for sinks; removal of the paint where the semiconductor is attached is usually required because of paints high thermal resistance. However, when it is necessary to insulate the semiconductor package from the heatsink, hard anodized or painted surfaces allow an easy installation for low voltage applications. Some manufacturers will provide anodized or painted surfaces meeting specific insulation voltage requirements, usually up to 400 volts. It is also necessary that the surface be free from all foreign material, film, and oxide (freshly bared aluminum forms an oxide layer in a few seconds). Immediately prior to assembly, it is a good practice to polish the mounting area with No. 000 steel wool, followed by an acetone or alcohol rinse. INTERFACE DECISIONS When any significant amount of power is being dissipated, something must be done to fill the air voids between mating surfaces in the thermal path. Otherwise the interface thermal resistance will be unnecessarily high and quite dependent upon the surface finishes. For several years, thermal joint compounds, often called grease, have been used in the interface. They have
Joint compounds are a formulation of fine zinc or other conductive particles in the silicone oil or other synthetic base fluid which maintains a grease-like consistency with time and temperature. Since some of these compounds do not spread well, they should be evenly applied in a very thin layer using a spatula or lintless brush, and wiped lightly to remove excess material. Some cyclic rotation of the package will help the compound spread evenly over the entire contact area. Some experimentation is necessary to determine the correct quantity; too little will not fill all the voids, while too much may permit some compound to remain between well mated metal surfaces where it will substantially increase the thermal resistance of the joint. To determine the correct amount, several semiconductor samples and heatsinks should be assembled with different amounts of grease applied evenly to one side of each mating surface. When the amount is correct a very small amount of grease should appear around the perimeter of each mating surface as the assembly is slowly torqued to the recommended value. Examination of a dismantled assembly should reveal even wetting across each mating surface. In production, assemblers should be trained to slowly apply the specified torque even though an excessive amount of grease appears at the edges of mating surfaces. Insufficient torque causes a significant increase in the thermal resistance of the interface. To prevent accumulation of airborne particulate matter, excess compound should be wiped away using a cloth moistened with acetone or alcohol. These solvents should not contact plastic-encapsulated devices, as they may enter the package and cause a leakage path or carry in substances which might attack the semiconductor chip. The silicone oil used in most greases has been found to evaporate from hot surfaces with time and become deposited on other cooler surfaces. Consequently, manufacturers must determine whether a microscopically thin coating of silicone oil on the entire assembly will pose any problems. It may be necessary to enclose components using grease. The newer synthetic base greases show far less tendency to migrate or creep than those made with a silicone oil base. However, their currently observed working temperature range are less,
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they are slightly poorer on thermal conductivity and dielectric strength and their cost is higher. Data showing the effect of compounds on several package types under different mounting conditions is shown in Table 7.1. The rougher the surface, the more valuable the grease becomes in lowering contact resistance; therefore, when mica insulating washers are used, use of grease is generally mandatory. The joint compound also improves the breakdown rating of the insulator.
Conductive Pads
Because of the difficulty of assembly using grease and the evaporation problem, some equipment manufacturers will not, or cannot, use grease. To minimize the need for grease, several vendors offer dry conductive pads which approximate performance obtained with grease. Data for a
greased bare joint and a joint using Grafoil, a dry graphite compound, is shown in the data of Figure 7.3. Grafoil is claimed to be a replacement for grease when no electrical isolation is required; the data indicates it does indeed perform as well as grease. Another conductive pad available from Aavid is called KON-DUX. It is made with a unique, grain oriented, flake-like structure (patent pending). Highly compressible, it becomes formed to the surface roughness of both of the heatsink and semiconductor. Manufacturers data shows it to provide an interface thermal resistance better than a metal interface with filled silicone grease. Similar dry conductive pads are available from other manufacturers. They are a fairly recent development; long term problems, if they exist, have not yet become evident.
Table 7.1 Approximate Values for Interface Thermal Resistance Data from Measurements Performed in ON Semiconductor Applications Engineering Laboratory
Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless otherwise noted the case temperature is monitored by a thermocouple located directly under the die reached through a hole in the heatsink. (See Appendix B for a discussion of Interface Thermal Resistance Measurements.)
Package Type and Data JEDEC Outlines DO-203AA, TO-210AA TO-208AB DO-203AB, TO-210AC TO-208 DO-208AA TO-204AA (TO-3) TO-213AA (TO-66) TO-126 TO-220AB Test Torque Torq e In-Lb 15 25 6 6 6 8
Interface Thermal Resistance (C/W) Metal-to-Metal Dry 0.3 0.2 0.15 0.5 1.5 2.0 1.2 Lubed 0.2 0.1 0.1 0.1 0.5 1.3 1.0 Dry 1.6 0.8 1.3 2.3 4.3 3.4 With Insulator Lubed 0.8 0.6 0.36 0.9 3.3 1.6 Type 3 mil Mica 5 mil Mica 3 mil Mica 2 mil Mica 2 mil Mica 2 mil Mica 1, 2 1 See Note
Description 10-32 Stud 7/16 Hex 1/4-28 Stud 11/16 Hex Pressfit, 1/2 Diamond Flange Diamond Flange Thermopad 1/4 x 3/8 Thermowatt
NOTES: 1. See Figures 3 and 4 for additional data on TO-3 and TO-220 packages. 2. Screw not insulated. See Figure 7.
INSULATION CONSIDERATIONS Since most power semiconductors use are vertical device construction it is common to manufacture power semiconductors with the output electrode (anode, collector or drain) electrically common to the case; the problem of isolating this terminal from ground is a common one. For lowest overall thermal resistance, which is quite important when high power must be dissipated, it is best to isolate the entire heatsink/semiconductor structure from ground, rather than to use an insulator between the
semiconductor and the heatsink. Heatsink isolation is not always possible, however, because of EMI requirements, safety reasons, instances where a chassis serves as a heatsink or where a heatsink is common to several non-isolated packages. In these situations insulators are used to isolate the individual components from the heatsink. Newer packages, such as the ON Semiconductor Isolated TO-220 Full Pack, was introduced to save the equipment manufacturer the burden of addressing the isolation problem.
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Insulator Thermal Resistance
When an insulator is used, thermal grease is of greater importance than with a metal-to-metal contact, because two interfaces exist instead of one and some materials, such as mica, have a hard, markedly uneven surface. With many isolation materials reduction of interface thermal resistance of between 2 to 1 and 3 to 1 are typical when grease is used. Data obtained by Thermalloy, showing interface resistance for different insulators and torques applied to TO-204 (TO-3) and TO-220 packages, are shown in Figure 7.3, for bare and greased surfaces. Similar materials to those shown are available from several
manufacturers. It is obvious that with some arrangements, the interface thermal resistance exceeds that of the semiconductor (junction to case). Referring to Figure 7.3, one may conclude that when high power is handled, beryllium oxide is unquestionably the best. However, it is an expensive choice. (It should not be cut or abraided, as the dust is highly toxic.) Thermafilm is filled polyimide material which is used for isolation (variation of Kapton). It is a popular material for low power applications because of its low cost ability to withstand high temperatures, and ease of handling in contrast to mica which chips and flakes easily.
2 THERMAL RESISTANCE FROM TRANSISTOR CASE TO MOUNTING SURFACE, R CS ( C/WATT) THERMAL RESISTANCE FROM TRANSISTOR CASE TO MOUNTING SURFACE, R CS ( C/WATT)
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 MOUNTING SCREW TORQUE (IN-LBS) 72 145 217 290 362 INTERFACE PRESSURE (psi) 435 (1) (2) (3) (5) (4) (6) (7)
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 (8) 0 1 2 3 4 5 6 MOUNTING SCREW TORQUE (IN-LBS) 72 145 217 290 362 INTERFACE PRESSURE (psi) 435 (6) (7) (1) (2) (3) (4) (5) (1) Thermalfilm, .002 (.05) thick. (2) Mica, .003 (.08) thick. (3) Mica, .002 (.05) thick. (4) Hard anodized, .020 (.51) thick. (5) Aluminum oxide, .062 (1.57) thick. (6) Beryllium oxide, .062 (1.57) thick. (7) Bare joint no finish. (8) Grafoil, .005 (.13) thick.* *Grafoil is not an insulating material.
(a). TO-204AA (TO-3) Without Thermal Grease

THERMAL RESISTANCE FROM TRANSISTOR CASE TO MOUNTING SURFACE, R CS ( C/WATT) (1) 4 (2) (3) 3 (4) (1) Thermalfilm, .022 (.05) thick. (2) Mica, .003 (.08) thick. (3) Mica, .002 (.05) thick. (4) Hard anodized, .020 (.51) thick. (5) Thermalsil II, .009 (.23) thick. (6) Thermalsil III, .006 (.15) thick. (7) Bare joint no finish. (8) Grafoil, .005 (.13) thick* *Grafoil is not an insulating material. THERMAL RESISTANCE FROM TRANSISTOR CASE TO MOUNTING SURFACE, R CS ( C/WATT) 5 5
(b). TO-204AA (TO-3) With Thermal Grease
3 (1) 2 (2) (3) (4) (7)
2 (5) (6) (7) (8)
0 0 1 2 (IN-LBS) 4 5 MOUNTING SCREW TORQUE (IN-LBS) 6
2 3 4 5 1 MOUNTING SCREW TORQUE (IN-LBS)
(c). TO-220 Without Thermal Grease
(d). TO-220 With Thermal Grease
Figure 7.3. Interface Thermal Resistance for TO-204, TO-3 and TO-220 Packages using Different Insulating Materials as a Function of Mounting Screw Torque (Data Courtesy Thermalloy)
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A number of other insulating materials are also shown. They cover a wide range of insulation resistance, thermal resistance and ease of handling. Mica has been widely used in the past because it offers high breakdown voltage and fairly low thermal resistance at a low cost but it certainly should be used with grease. Silicone rubber insulators have gained favor because they are somewhat conformal under pressure. Their ability to fill in most of the metal voids at the interface reduces the need for thermal grease. When first introduced, they suffered from cut-through after a few years in service. The ones presently available have solved this problem by having imbedded pads of Kapton of fiberglass. By comparing Figures 7.3(c) and 7.3(d), it can be noted that Thermasil, a filled silicone rubber, without grease has about the same interface thermal resistance as greased mica for the TO-220 package. A number of manufacturers offer silicone rubber insulators. Table 7.2 shows measured performance of a number of these insulators under carefully controlled, nearly identical conditions. The interface thermal resistance extremes are over 2:1 for the various materials. It is also clear that some of the insulators are much more tolerant than others of out-of-flat surfaces. Since the tests were performed, newer products have been introduced. The Bergquist K-10 pad, for example, is described as having about 2/3 the interface resistance of the Sil Pad 1000 which would place its performance close to the Chomerics 1671 pad. AAVID also offers an isolated pad called Rubber-Duc, however it is only available vulcanized to a heatsink and therefore was not included in the comparison. Published data from AAVID shows RCS below 0.3C/W for pressures above 500 psi. However, surface flatness and other details are not specified so a comparison cannot be made with other data in this note.
The thermal resistance of some silicone rubber insulators is sensitive to surface flatness when used under a fairly rigid base package. Data for a TO-204AA (TO-3) package insulated with Thermasil is shown on Figure 7.4. Observe that the worst case encountered (7.5 mils) yields results having about twice the thermal resistance of the typical case (3 mils), for the more conductive insulator. In order for Thermasil III to exceed the performance of greased mica, total surface flatness must be under 2 mils, a situation that requires spot finishing.
1.2 INTERFACE THERMAL RESISTANCE ( C/W) 1 (1)
(2)
0.8
0.6
0.4
(1) Thermalsil II, .009 inches (.23 mm) thick. (2) Thermalsil III, .006 inches (.15 mm) thick.
0.2 0 0
0.002
0.004
0.006
0.008
0.01
TOTAL JOINT DEVIATION FROM FLAT OVER TO-3 HEADER SURFACE AREA (INCHES) Data courtesy of Thermalloy
Figure 7.4. Effect of Total Surface Flatness on Interface Resistance Using Silicon Rubber Insulators
Table 7.2 Thermal Resistance of Silicone Rubber Pads

Manufacturer Wakefield Bergquist Stockwell Rubber Bergquist Thermalloy Shin-Etsu Bergquist Chomerics Wakefield Bergquist Ablestik Thermalloy Chomerics Product Delta Pad 173-7 Sil Pad K-4 1867 Sil Pad 400-9 Thermalsil II TC-30AG Sil Pad 400-7 1674 Delta Pad 174-9 Sil Pad 1000 Thermal Wafers Thermalsil III 1671 RCS @ 3 Mils* .790 .752 .742 .735 .680 .664 .633 .592 .574 .529 .500 .440 .367 RCS @ 7.5 Mils* 1.175 1.470 1.015 1.205 1.045 1.260 1.060 1.190 .755 .935 .990 1.035 .655
* Test Fixture Deviation from flat from Thermalloy EIR86-1010.
Silicon rubber insulators have a number of unusual characteristics. Besides being affected by surface flatness and initial contact pressure, time is a factor. For example, in a study of the Cho-Therm 1688 pad thermal interface impedance dropped from 0.90C/W to 0.70C/W at the end of 1000 hours. Most of the change occurred during the first 200 hours where RCS measured 0.74C/W. The torque on the conventional mounting hardware had decreased to 3 in-lb from an initial 6 in-lb. With non-conformal materials, a reduction in torque would have increased the interface thermal resistance. Because of the difficulties in controlling all variables affecting tests of interface thermal resistance, data from different manufacturers is not in good agreement. Table 7.3 shows data obtained from two sources. The relative performance is the same, except for mica which varies widely in thickness. Appendix B discusses the variables which need to be controlled. At the time of this writing ASTM Committee D9 is developing a standard for interface measurements.
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Table 7.3 Performance of Silicon Rubber Insulators Tested per MIL-I-49456

Measured Thermal Resistance (C/W) Material Bare Joint, greased BeO, greased Cho Therm, 1617 Cho-Therm, Q Pad ( (non-insulated) ) Sil-Pad, K-10 Thermasil III Mica, greased Sil-Pad 1000 Ch th Cho-therm 1674 Th il II Thermasil Sil-Pad Sil Pad 400 Sil Pad K-4 K4 Sil-Pad Thermalloy Data(1) 0.033 0.082 0.233 0.263 0.267 0.329 0.400 0 433 0.433 0 500 0.500 0.533 0 533 0 583 0.583 Berquist Data(2) 0.008 0.009 0.200 0.400 0.300 0.440 0 440 0 440 0.440
1. From Thermalloy EIR 87-1030 2. From Berquist Data Sheet
consist of multiple chips and integrated circuits as well as the more conventional single chip devices. The newer insulated packages can be grouped into two categories. The first has insulation between the semiconductor chips and the mounting base; an exposed area of the mounting base is used to secure the part. Case 806 (ICePAK) and Case 388 (TO-258AA) (see Figure 7.6) are examples of parts in this category. The second category contains parts which have a plastic overmold covering the metal mounting base. The Fully Isolated, Case 221C, illustrated in Figure 7.8, is an example of parts in the second category. Parts in the first category those with an exposed metal flange or tab are mounted the same as their non-insulated counterparts. However, as with any mounting system where pressure is bearing on plastic, the overmolded type should be used with a conical compression washer, described later in this note. FASTENER AND HARDWARE CHARACTERISTICS Characteristics of fasteners, associated hardware, and the tools to secure them determine their suitability for use in mounting the various packages. Since many problems have arisen because of improper choices, the basic characteristics of several types of hardware are discussed next.
Compression Hardware
The conclusions to be drawn from all this data is that some types of silicon rubber pads, mounted dry, will out perform the commonly used mica with grease. Cost may be a determining factor in making a selection.
Insulation Resistance
When using insulators, care must be taken to keep the mating surfaces clean. Small particles of foreign matter can puncture the insulation, rendering it useless or seriously lowering its dielectric strength. In addition, particularly when voltages higher than 300 V are encountered, problems with creepage may occur. Dust and other foreign material can shorten creepage distances significantly; so having a clean assembly area is important. Surface roughness and humidity also lower insulation resistance. Use of thermal grease usually raises the withstand voltage of the insulating system but excess must be removed to avoid collecting dust. Because of these factors, which are not amenable to analysis, hi-pot testing should be done on prototypes and a large margin of safety employed.
Insulated Electrode Packages
Because of the nuisance of handling and installing the accessories needed for an insulated semiconductor mounting, equipment manufacturers have longed for cost-effective insulated packages since the 1950s. The first to appear were stud mount types which usually have a layer of beryllium oxide between the stud hex and the can. Although effective, the assembly is costly and requires manual mounting and lead wire soldering to terminals on top of the case. In the late eighties, a number of electrically isolated parts became available from various semiconductor manufacturers. These offerings presently
Normal split ring lock washers are not the best choice for mounting power semiconductors. A typical #6 washer flattens at about 50 pounds, whereas 150 to 300 pounds is needed for good heat transfer at the interface. A very useful piece of hardware is the conical, sometimes called a Belleville washer, compression washer. As shown in Figure 7.5, it has the ability to maintain a fairly constant pressure over a wide range of its physical deflection generally 20% to 80%. When installing, the assembler applies torque until the washer depresses to half its original height. (Tests should be run prior to setting up the assembly line to determine the proper torque for the fastener used to achieve 50% deflection.) The washer will absorb any cyclic expansion of the package, insulating washer or other materials caused by temperature changes. Conical washers are the key to successful mounting of devices requiring strict control of the mounting force or when plastic hardware is used in the mounting scheme. They are used with the large face contacting the packages. A new variation of the conical washer includes it as part of a nut assembly. Called a Sync Nut, the patented device can be soldered to a PC board and the semiconductor mounted with 6-32 machine screw.(4)
(4) ITW Shakeproof, St. Charles Road, Elgin, IL 60120.
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280 PRESSURE ON PACKAGE (LB-F) 240 200 160 120 80 40 0 0 20 40 60 80 100
must be used in a clearance hole to engage a speednut. If a self tapping process is desired, the screw type must be used which roll-forms machine screw threads.
Rivets
DEFLECTION OF WASHER DURING MOUNTING (%)
Figure 7.5. Characteristics of the Conical Compression Washers Designed for Use with Plastic Body Mounted Semiconductors Clips
Rivets are not a recommended fastener for any of the plastic packages. When a rugged metal flange-mount package is being mounted directly to a heatsink, rivets can be used provided press-riveting is used. Crimping force must be applied slowly and evenly. Pop-riveting should never be used because the high crimping force could cause deformation of most semiconductor packages. Aluminum rivets are much preferred over steel because less pressure is required to set the rivet and thermal conductivity is improved. The hollow rivet, or eyelet, is preferred over solid rivets. An adjustable, regulated pressure press is used such that a gradually increasing pressure is used to pan the eyelet. Use of sharp blows could damage the semiconductor die.
Solder
Fast assembly is accomplished with clips. When only a few watts are being dissipated, the small board mounted or free-standing heat dissipators with an integral clip, offered by several manufacturers, result in a low cost assembly. When higher power is being handled, a separate clip may be used with larger heatsinks. In order to provide proper pressure, the clip must be specially designed for a particular heatsink thickness and semiconductor package. Clips are especially popular with plastic packages such as the TO-220 and TO-126. In addition to fast assembly, the clip provides lower interface thermal resistance than other assembly methods when it is designed for proper pressure to bear on the top of the plastic over the die. The TO-220 package usually is lifted up under the die location when mounted with a single fastener through the hole in the tab because of the high pressure at one end.
Machine Screws
Until the advent of the surface mount assembly technique, solder was not considered a suitable fastener for power semiconductors. However, user demand has led to the development of new packages for this application. Acceptable soldering methods include conventional beltfurnace, irons, vapor-phase reflow, and infrared reflow. It is important that the semiconductor temperature not exceed the specified maximum (usually 260C) or the die bond to the case could be damaged. A degraded die bond has excessive thermal resistance which often leads to a failure under power cycling.
Adhesives
Machine screws, conical washers, and nuts (or syncnuts) can form a trouble-free fastener system for all types of packages which have mounting holes. However, proper torque is necessary. Torque ratings apply when dry; therefore, care must be exercised when using thermal grease to prevent it from getting on the threads as inconsistent torque readings result. Machine screw heads should not directly contact the surface of plastic packages types as the screw heads are not sufficiently flat to provide properly distributed force. Without a washer, cracking of the plastic case may occur.
Self-Tapping Screws
Adhesives are available which have coefficients of expansion compatible with copper and aluminum.(5) Highly conductive types are available; a 10 mil layer has approximately 0.3C/W interface thermal resistance. Different types are offered: high strength types for non-field-serviceable systems or low strength types for field-serviceable systems. Adhesive bonding is attractive when case mounted parts are used in wave soldering assembly because thermal greases are not compatible with the conformal coatings used and the greases foul the solder process.
Plastic Hardware
Under carefully controlled conditions, sheet-metal screws are acceptable. However, during the tapping process with a standard screw, a volcano-like protrusion will develop in the metal being threaded; an unacceptable surface that could increase the thermal resistance may result. When standard sheet metal screws are used, they
Most plastic materials will flow, but differ widely in this characteristic. When plastic materials form parts of the fastening system, compression washers are highly valuable to assure that the assembly will not loosen with time and temperature cycling. As previously discussed, loss of contact pressure will increase interface thermal resistance.
(5) Robert Batson, Elliot Fraunglass and James P. Moran, Heat Dissipation Through Thermalloy Conductive Adhesives, EMTAS 83. Conference, February 13, Phoenix, AZ; Society of Manufacturing Engineers, One SME Drive, P.O. Box 930, Dearborn, MI 48128.
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FASTENING TECHNIQUES Each of the various classes of packages in use requires different fastening techniques. Details pertaining to each type are discussed in following sections. Some general considerations follow. To prevent galvanic action from occurring when devices are used on aluminum heatsinks in a corrosive atmosphere, many devices are nickel- or gold-plated. Consequently, precautions must be taken not to mar the finish. Another factor to be considered is that when a copper based part is rigidly mounted to an aluminium heatsink, a bimetallic system results which will bend with temperature changes. Not only is the thermal coefficient of expansion different for copper and aluminium, but the temperature gradient through each metal also causes each component to bend. If bending is excessive and the package is mounted by two or more screws the semiconductor chip could be damaged. Bending can be minimized by: 1. Mounting the component parallel to the heatsink fins to provide increased stiffness. 2. Allowing the heatsink holes to be a bit oversized so that some slip between surfaces can occur as temperature changes. 3. Using a highly conductive thermal grease or mounting pad between the heatsink and semicondutor to minimize the temperature gradient and allow for movement.
Tab Mount
need a spacer or combination spacer and isolation bushing to raise the screw head above the top surface of the plastic. The popular TO-220 Package and others of similar construction lift off the mounting surface as pressure is applied to one end. (See Appendix B, Figure B1.) To counter this tendency, at least one hardware manufacturer offers a hard plastic cantilever beam which applies more even pressure on the tab.(6) In addition, it separates the mounting screw from the metal tab. Tab mount parts may also be effectively mounted with clips as shown in Figure 7.10(c). To obtain high pressure without cracking the case, a pressure spreader bar should be used under the clip. Interface thermal resistance with the cantilever beam or clips can be lower than with screw mounting.
(6) Catalog, Edition 18, Richco Plastic Company, 5825 N. Tripp Ave., Chicago, IL 60546.
The tab mount class is composed of a wide array of packages as illustrated in Figure 7.6. Mounting considerations for all varieties are similar to that for the popular TO-220 package, whose suggested mounting arrangements and hardware are shown in Figure 7.7. The rectangular washer shown in Figure 7.7(a) is used to minimize distortion of the mounting flange; excessive distortion could cause damage to the semiconductor chip. Use of the washer is only important when the size of the mounting hole exceeds 0.140 inch (632 clearance). Larger holes are needed to accommodate the lower insulating bushing when the screw is electrically connected to the case; however, the holes should not be larger than necessary to provide hardware clearance and should never exceed a diameter of 0.250 inch. Flange distortion is also possible if excessive torque is used during mounting. A maximum torque of 8 inch-pounds is suggested when using a 632 screw. Care should be exercised to assure that the tool used to drive the mounting screw never comes in contact with the plastic body during the driving operation. Such contact can result in damage to the plastic body and internal device connections. To minimize this problem, ON Semiconductor TO-220 packages have a chamfer on one end. TO-220 packages of other manufacturers may
CASE 221A-07 (TO-220AB)
CASE 221B-04 (TO-220AC)
CASE 314B (5 PIN TO-220)
CASE 314D
CASE 339
CASE 340-02 (TO-218)
CASE 387-01 (TO-254AA) CASE 388-01 (TO-258AA)
CASE 806-05 (ICePAK)
Figure 7.6. Several Types of Tab-Mount Parts
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(a). Preferred Arrangement for Isolated or Non-Isolated Mounting. Screw is at Semiconductor Case Potential. 6-32 Hardware is Used. Use Parts Listed Below
(b). Alternate Arrangement for Isolated Mounting when Screw must be at Heat Sink Potential. 4-40 Hardware is used. Use Parts Listed below.
4-40 PAN OR HEX HEAD SCREW 6-32 HEX HEAD SCREW FLAT WASHER
INSULATING BUSHING
(1) RECTANGULAR STEEL WASHER
SEMICONDUCTOR (CASE 221, 221A)
SEMICONDUCTOR (CASE 221,221A) (2) RECTANGULAR INSULATOR HEATSINK RECTANGULAR INSULATOR
(2) BUSHING
HEATSINK
(3) FLAT WASHER COMPRESSION WASHER (4) CONICAL WASHER
6-32 HEX NUT
4-40 HEX NUT
(1) Used with thin chassis and/or large hole. (2) Used when isolation is required. (3) Required when nylon bushing is used.
Figure 7.7. Mounting Arrangements for Tab Mount TO-220
The copper sheet has a hole for mounting; plastic is molded enveloping the chip but leaving the mounting hole open. The low thermal resistance of this construction is obtained at the expense of a requirement that strict attention be paid to the mounting procedure. The fully isolated power package (Case 221C-02) is similar to a TO-220 except that the tab is encased in plastic. Because the mounting force is applied to plastic, the mounting procedure differs from a standard TO-220 and is similar to that of the Thermopad. Several types of fasteners may be used to secure these packages; machine screws, eyelets, or clips are preferred. With screws or eyelets, a conical washer should be used which applies the proper force to the package over a fairly wide range of deflection and distributes the force over a fairly large surface area. Screws should not be tightened with any type of air-driven torque gun or equipment which may cause high impact. Characteristics of a suitable conical washer is shown in Figure 7.5. Figure 7.9 shows details of mounting Case 77 devices. Clip mounting is fast and requires minimum hardware, however, the clip must be properly chosen to insure that the proper mounting force is applied. When electrical isolation is required with screw mounting, a bushing inside the mounting hole will insure that the screw threads do not contact the metal base. The fully isolated power package, (Case 221C, 221D and 340B) permits the mounting procedure to be greatly simplified over that of a standard TO-220. As shown in Figure 7.10(c), one properly chosen clip, inserted into two slotted holes in the heatsink, is all the hardware needed. Even though clip pressure is much lower than obtained with a screw, the thermal resistance is about the same for either method. This occurs because the clip bears directly on top of the die and holds the package flat while the screw causes the package to lift up somewhat under the die. (See Figure B1 of Appendix B.) The interface should consist of a layer of thermal grease or a highly conductive thermal pad. Of course, screw mounting shown in Figure 7.10(b) may also be used but a conical compression washer should be included. Both methods afford a major reduction in hardware as compared to the conventional mounting method with a TO-220 package which is shown in Figure 7.10(a).
In situations where a tab mount package is making direct contact with the heatsink, an eyelet may be used, provided sharp blows or impact shock is avoided.
Plastic Body Mount
The Thermopad and fully isolated plastic power packages shown in Figure 7.8 are typical of packages in this group. They have been designed to feature minimum size with no compromise in thermal resistance. For the Thermopad (Case 77) parts this is accomplished by die-bounding the silicon chip on one side of a thin copper sheet; the opposite side is exposed as a mounting surface.
CASE 77 CASE 221C-02 (TO-225AA/ (Fully Isolated) TO-126) (THERMOPAD)
CASE 221D-02 (Fully Isolated)
CASE 340B-03 (Fully Isolated)
Figure 7.8. Plastic Body-Mount Packages
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4-40 SCREW MACHINE SCREW OR SHEET METAL SCREW PLAIN WASHER INSULATING BUSHING HEAT SINK SURFACE COMPRESSION WASHER THERMOPAD PACKAGE
INSULATING WASHER (OPTIONAL) MACHINE OR SPEED NUT
INSULATOR HEATSINK COMPRESSION WASHER NUT
(a). Machine Screw Mounting
(a). Screw-Mounted TO-220

EYELET 6-32 SCREW PLAIN WASHER
COMPRESSION WASHER
INSULATING WASHER (OPTIONAL)
HEATSINK
COMPRESSION WASHER NUT
(b). Eyelet Mounting
(b). Screw-Mounted Fully Isolated

CLIP
(c). Clips
HEATSINK
(c). Clip-Mounted Fully Isolated Figure 7.9. Recommended Mounting Arrangements for TO-225AA (TO-126) Thermopad Packages Figure 7.10. Mounting Arrangements for the Fully Isolated Power Package as Compared to a Conventional TO-220
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Surface Mount
100 R JA, THERMAL RESISTANCE ( C/W) 80 PCB, 1/16 IN THICK G10/FR4, 2 OUNCE EPOXY GLASS BOARD, DOUBLE SIDED
Although many of the tab mount parts have been surface mounted, special small footprint packages for mounting power semiconductors using surface mount assembly techniques have been developed. The DPAK, shown in Figure 11, for example, will accommodate a die up to 112 mils x 112 mils, and has a typical thermal resistance around 2C/W junction to case. The thermal resistance values of the solder interface is well under 1C/W. The printed circuit board also serves as the heatsink. Standard Glass-Epoxy 2-ounce boards do not make very good heatsinks because the thin foil has a high thermal resistance. As Figure 7.12 shows, thermal resistance assymtotes to about 20C/W at 10 square inches of board area, although a point of diminishing returns occurs at about 3 square inches. Boards are offered that have thick aluminium or copper substrates. A dielectric coating designed for low thermal resistance is overlayed with one or two ounce copper foil for the preparation of printed conductor traces. Tests run on such a product indicate that case to substrate thermal resistance is in the vicinity of 1C/W, exact values depending upon board type.(7) The substrate may be an effective heatsink itself, or it can be attached to a conventional finned heatsink for improved performance. Since DPAK and other surface mount packages are designed to be compatible with surface mount assembly techniques, no special precautions are needed other than to insure that maximum temperature/time profiles are not exceeded.
(7) Herb Fick, Thermal Management of Surface Mount Power Devices, Power conversion and Intelligent Motion, August 1987.
60
40
20 0 2 4 6
10
PCB PAD AREA (IN2)
Figure 7.12. Effect of Footprint Area on Thermal Resistance of DPAK Mounted on a Glass-Epoxy Board
FREE AIR AND SOCKET MOUNTING In applications where average power dissipation is on the order of a watt or so, most power semiconductors may be mounted with little or no heatsinking. The leads of the various metal power packages are not designed to support the packages; their cases must be firmly supported to avoid the possibility of cracked seals around the leads. Many plastic packages may be supported by their leads in applications where high shock and vibration stresses are not encountered and where no heatsink is used. The leads should be as short as possible to increase vibration resistance and reduce thermal resistance. As a general practice however, it is better to support the package. A plastic support for the TO-220 Package and other similar types is offered by heatsink accessory vendors. In many situations, because its leads are fairly heavy, the CASE 77 (TO-225AA)(TO-127) package has supported a small heatsink; however, no definitive data is available. When using a small heatsink, it is good practice to have the sink rigidly mounted such that the sink or the board is providing total support for the semiconductor. Two possible arrangements are shown in Figure 7.13. The arrangement of part (a) could be used with any plastic package, but the scheme of part (b) is more practical with Case 77 Thermopad devices. With the other package types, mounting the transistor on top of the heatsink is more practical.
CASE 369-07
CASE 369A-13
Figure 7.11. Surface Mount D-PAK Parts
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CONNECTING AND HANDLING TERMINALS

HEATSINK
TO-225AA CASE 77 HEATSINK SURFACE
Pins, leads, and tabs must be handled and connected properly to avoid undue mechanical stress which could cause semiconductor failure. Change in mechanical dimensions as a result of thermal cycling over operating temperature extremes must be considered. Standard metal, plastic, and RF stripline packages each have some special considerations.
Plastic Packages
TWIST LOCKS OR SOLDERABLE LEGS
CIRCUIT BOARD
(a). Simple Plate, Vertically Mounted

HEATSINK
TO-225AA CASE 77 HEATSINK SURFACE CIRCUIT BOARD
(b). Commercial Sink, Horizontally Mounted
Figure 7.13. Methods of Using Small Heatsinks With Plastic Semiconductor Packages
In certain situations, in particular where semiconductor testing is required or prototypes are being developed, sockets are desirable. Manufacturers have provided sockets for many of the packages available from ON Semiconductor. The user is urged to consult manufacturers catalogs for specific details. Sockets with Kelvin connections are necessary to obtain accurate voltage readings across semiconductor terminals.
The leads of the plastic packages are somewhat flexible and can be reshaped although this is not a recommended procedure. In many cases, a heatsink can be chosen which makes lead-bending unnecessary. Numerous-lead and tabforming options are available from ON Semiconductor on large quantity orders. Preformed leads remove the users risk of device damage caused by bending. If, however, lead-bending is done by the user, several basic considerations should be observed. When bending the lead, support must be placed between the point of bending and the package. For forming small quantities of units, a pair of pliers may be used to clamp the leads at the case, while bending with the fingers or another pair of pliers. For production quantities, a suitable fixture should be made. The following rules should be observed to avoid damage to the package. 1. A leadbend radius greater than 1/16 inch is advisable for TO-225AA (CASE 77) and 1/32 inch for TO-220. 2. No twisting of leads should be done at the case. 3. No axial motion of the lead should be allowed with respect to the case. The leads of plastic packages are not designed to withstand excessive axial pull. Force in this direction greater than 4 pounds may result in permanent damage to the device. If the mounting arrangement imposes axial stress on the leads, a condition which may be caused by thermal cycling, some method of strain relief should be devised. When wires are used for connections, care should be exercised to assure that movement of the wire does not cause movement of the lead at the lead-to-plastic junctions. Highly flexible or braided wires are good for providing strain relief. Wire-wrapping of the leads is permissible, provided that the lead is restrained between the plastic case and the point of the wrapping. The leads may be soldered; the maximum soldering temperature, however, must not exceed 260C and must be applied for not more than 10 seconds at a distance greater than 1/8 inch from the plastic case.
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CLEANING CIRCUIT BOARDS It is important that any solvents or cleaning chemicals used in the process of degreasing or flux removal do not affect the reliability of the devices. Alcohol and unchlorinated Freon solvents are generally satisfactory for use with plastic devices, since they do not damage the package. Hydrocarbons such as gasoline and chlorinated Freon may cause the encapsulant to swell, possibly damaging the transistor die. When using an ultrasonic cleaner for cleaning circuit boards, care should be taken with regard to ultrasonic energy and time of application. This is particularly true if any packages are free-standing without support. THERMAL SYSTEM EVALUATION Assuming that a suitable method of mounting the semiconductor without incurring damage has been achieved, it is important to ascertain whether the junction temperature is within bounds. In applications where the power dissipated in the semiconductor consists of pulses at a low duty cycle, the instantaneous or peak junction temperature, not average temperature, may be the limiting condition. In this case, use must be made of transient thermal resistance data. For a full explanation of its use, see ON Semiconductor Application Note, AN569. Other applications, notably RF power amplifiers or switches driving highly reactive loads, may create severe current crowding conditions which render the traditional concepts of thermal resistance or transient thermal impedance invalid. In this case, transistor safe operating area, thyristor di/dt limits, or equivalent ratings as applicable, must be observed. Fortunately, in many applications, a calculation of the average junction temperature is sufficient. It is based on the concept of thermal resistance between the junction and a temperature reference point on the case. (See Appendix A.) A fine wire thermocouple should be used, such as #36 AWG, to determine case temperature. Average operating junction temperature can be computed from the following equation:
TJ
where
TJ = junction temperature (C) TC = case temperature (C) RJC = thermal resistance junctionto-case as specified on the data sheet (C/W) PD = power dissipated in the device (W)
The difficulty in applying the equation often lies in determining the power dissipation. Two commonly used empirical methods are graphical integration and substitution.
Graphical Integration
Graphical integration may be performed by taking oscilloscope pictures of a complete cycle of the voltage and current waveforms, using a limit device. The pictures should be taken with the temperature stabilized. Corresponding points are then read from each photo at a suitable number of time increments. Each pair of voltage and current values are multiplied together to give instantaneous values of power. The results are plotted on linear graph paper, the number of squares within the curve counted, and the total divided by the number of squares along the time axis. The quotient is the average power dissipation. Oscilloscopes are available to perform these measurements and make the necessary calculations.
Substitution
+ TC ) RqJC
PD
This method is based upon substituting an easily measurable, smooth dc source for a complex waveform. A switching arrangement is provided which allows operating the load with the device under test, until it stabilizes in temperature. Case temperature is monitored. By throwing the switch to the test position, the device under test is connected to a dc power supply, while another pole of the switch supplies the normal power to the load to keep it operating at full power level. The dc supply is adjusted so that the semiconductor case temperature remains approximately constant when the switch is thrown to each position for about 10 seconds. The dc voltage and current values are multiplied together to obtain average power. It is generally necessary that a Kelvin connection be used for the device voltage measurement.
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APPENDIX A THERMAL RESISTANCE CONCEPTS The basic equation for heat transfer under steady-state conditions is generally written as:
q
where
+ hADT
(1)
q = rate of heat transfer or power dissipation (PD) h = heat transfer coefficient, A = area involved in heat transfer, T = temperature difference between regions of heat transfer. However, electrical engineers generally find it easier to work in terms of thermal resistance, defined as the ratio of temperature to power. From Equation 1, thermal resistance, R, is
Rq
where
TJ = junction temperature, PD = power dissipation RJC = semiconductor thermal resistance (junction to case), RCS = interface thermal resistance (case to heatsink), RSA = heatsink thermal resistance (heatsink to ambient), TA = ambient temperature.
+ DTq + 1hA
(2)
The coefficient (h) depends upon the heat transfer mechanism used and various factors involved in that particular mechanism. An analogy between Equation (2) and Ohms Law is often made to form models of heat flow. Note that T could be thought of as a voltage thermal resistance corresponds to electrical resistance (R); and, power (q) is analogous to current (I). This gives rise to a basic thermal resistance model for a semiconductor as indicated by Figure A1. The equivalent electrical circuit may be analyzed by using Kirchoffs Law and the following equation results:
TJ
+ PD(RqJC ) RqCS ) RqSA) ) TA
(3)
The thermal resistance junction to ambient is the sum of the individual components. Each component must be minimized if the lowest junction temperature is to result. The value for the interface thermal resistance, RCS, may be significant compared to the other thermal-resistance terms. A proper mounting procedure can minimize RCS. The thermal resistance of the heatsink is not absolutely constant; its thermal efficiency increases as ambient temperature increases and it is also affected by orientation of the sink. The thermal resistance of the semiconductor is also variable; it is a function of biasing and temperature. Semiconductor thermal resistance specifications are normally at conditions where current density is fairly uniform. In some applications such as in RF power amplifiers and short-pulse applications, current density is not uniform and localized heating in the semiconductor chip will be the controlling factor in determining power handling ability.
TJ, JUNCTION TEMPERATURE RJC TC, CASE TEMPERATURE RCS HEATSINK TS, HEATSINK TEMPERATURE RSA FLAT WASHER SOLDER TERMINAL NUT REFERENCE TEMPERATURE TA, AMBIENT TEMPERATURE
DIE INSULATORS
PD
Figure A1. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor
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APPENDIX B MEASUREMENT OF INTERFACE THERMAL RESISTANCE Measuring the interface thermal resistance RCS appears deceptively simple. All thats apparently needed is a thermocouple on the semiconductor case, a thermocouple on the heatsink, and a means of applying and measuring DC power. However, RCS is proportional to the amount of contact area between the surfaces and consequently is affected by surface flatness and finish and the amount of pressure on the surfaces. The fastening method may also be a factor. In addition, placement of the thermocouples can have a significant influence upon the results. Consequently, values for interface thermal resistance presented by different manufacturers are not in good agreement. Fastening methods and thermocouple locations are considered in this Appendix. When fastening the test package in place with screws, thermal conduction may take place through the screws, for example, from the flange ear on a TO-3 package directly to the heatsink. This shunt path yields values which are artificially low for the insulation material and dependent upon screw head contact area and screw material. MIL-I-49456 allows screws to be used in tests for interface thermal resistance probably because it can be argued that this is application oriented. Thermalloy takes pains to insulate all possible shunt conduction paths in order to more accurately evaluate insulation materials. The ON Semiconductor fixture uses an insulated clamp arrangement to secure the package which also does not provide a conduction path. As described previously, some packages, such as a TO-220, may be mounted with either a screw through the tab or a clip bearing on the plastic body. These two methods often yield different values for interface thermal resistance. Another discrepancy can occur if the top of the package is exposed to the ambient air where radiation and convection can take place. To avoid this, the package should be covered with insulating foam. It has been estimated that a 15 to 20% error in RCS can be incurred from this source. Another significant cause for measurement discrepancies is the placement of the thermocouple to measure the semiconductor case temperature. Consider the TO-220 package shown in Figure B1. The mounting pressure at one end causes the other end where the die is located to lift off the mounting surface slightly. To improve contact, ON Semiconductor TO-220 Packages are slightly concave. Use of a spreader bar under the screw lessens the lifting, but some is inevitable with a package of this structure. Three thermocouple locations are shown: a. The ON Semiconductor location is directly under the die reached through a hole in the heatsink. The thermocouple is held in place by a spring which forces the thermocouple into intimate contact with the bottom of the semis case. b. The JEDEC location is close to the die on the top surface of the package base reached through a blind hole drilled through the molded body. The thermocouple is swaged in place. c. The Thermalloy location is on the top portion of the tab between the molded body and the mounting screw. The thermocouple is soldered into position.
E.I.A. DIE THERMALLOY
ON SEMICONDUCTOR
Figure B1. JEDEC TO-220 Package Mounted to Heatsink Showing Various Thermocouple Locations and Lifting Caused by Pressure at One End
Temperatures at the three locations are generally not the same. Consider the situation depicted in the figure. Because the only area of direct contact is around the mounting screw, nearly all the heat travels horizontally along the tab from the die to the contact area. Consequently, the temperature at the JEDEC location is hotter than at the Thermalloy location and the ON Semiconductor location is even hotter. Since junction-to-sink thermal resistance must be constant for a given test setup, the calculated junction-to-case thermal resistance values decrease and case-to-sink values increase as the case temperature thermocouple readings become warmer. Thus the choice of reference point for the case temperature is quite important. There are examples where the relationship between the thermocouple temperatures are different from the previous situation. If a mica washer with grease is installed between the semiconductor package and the heatsink, tightening the screw will not bow the package; instead, the mica will be deformed. The primary heat conduction path is from the die through the mica to the heatsink. In this case, a small temperature drop will exist across the vertical dimension of the package mounting base so that the thermocouple at the EIA location will be the hottest. The thermocouple temperature at the Thermalloy location will be lower but close to the temperature at the EIA location as the lateral heat flow is generally small. The ON Semiconductor location will be coolest.
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The EIA location is chosen to obtain the highest temperature on the case. It is of significance because power ratings are supposed to be based on this reference point. Unfortunately, the placement of the thermocouple is tedious and leaves the semiconductor in a condition unfit for sale. The ON Semiconductor location is chosen to obtain the highest temperature of the case at a point where, hopefully, the case is making contact to the heatsink. Once the special heatsink to accommodate the thermocouple has been fabricated, this method lends itself to production testing and does not mark the device. However, this location is not easily accessible to the user. The Thermalloy location is convenient and is often chosen by equipment manufacturers. However, it also blemishes the case and may yield results differing up to 1C/W for a TO-220 package mounted to a heatsink without thermal grease and no insulator. This error is small when compared to the thermal resistance of heat dissipaters often used with this package, since power dissipation is usually a few watts. When compared to the
specified junction-to-case values of some of the higher power semiconductors becoming available, however, the difference becomes significant and it is important that the semiconductor manufacturer and equipment manufacturer use the same reference point. Another EIA method of establishing reference temperatures utilizes a soft copper washer (thermal grease is used) between the semiconductor package and the heatsink. The washer is flat to within 1 mil/inch, has a finish better than 63 -inch, and has an imbedded thermocouple near its center. This reference includes the interface resistance under nearly ideal conditions and is therefore applicationoriented. It is also easy to use but has not become widely accepted. A good way to improve confidence in the choice of case reference point is to also test for junction-to-case thermal resistance while testing for interface thermal resistance. If the junction-to-case values remain relatively constant as insulators are changed, torque varied, etc., then the case reference point is satisfactory.
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SECTION 8 RELIABILITY AND QUALITY
Edited and Updated
USING TRANSIENT THERMAL RESISTANCE DATA IN HIGH POWER PULSED THYRISTOR APPLICATIONS
INTRODUCTION
For a certain amount of dc power dissipated in a semiconductor, the junction temperature reaches a value which is determined by the thermal conductivity from the junction (where the power is dissipated) to the air or heat sink. When the amount of heat generated in the junction equals the heat conducted away, a steadystate condition is reached and the junction temperature can be calculated by the simple equation:
where TJ = PD RJR + TR (1a) TJ = junction temperature TR = temperature at reference point PD = power dissipated in the junction RJR = steadystate thermal resistance from RJR = junction to the temperature reference RJR = point.
stable. However, for pulses in the microsecond and millisecond region, the use of steadystate values will not yield true power capability because the thermal response of the system has not been taken into account. Note, however, that semiconductors also have pulse power limitations which may be considerably lower or even greater than the allowable power as deduced from thermal response information. For transistors, the second breakdown portion of the pulsed safe operating area defines power limits while surge current or power ratings are given for diodes and thyristors. These additional ratings must be used in conjunction with the thermal response to determine power handling capability. To account for thermal capacity, a time dependent factor r(t) is applied to the steadystate thermal resistance. Thermal resistance, at a given time, is called transient thermal resistance and is given by:
RJR(t) = r(t)
RJR
(2)
Power ratings of semiconductors are based upon steady state conditions, and are determined from equation (1a) under worst case conditions, i.e.:
PD(max) TR + TJ(max) RqJR(max) (1b)
TJ(max) is normally based upon results of an operating life test or serious degradation with temperature of an important device characteristic. TR is usually taken as 25C, and RJR can be measured using various techniques. The reference point may be the semiconductor case, a lead, or the ambient air, whichever is most appropriate. Should the reference temperature in a given application exceed the reference temperature of the specification, PD must be correspondingly reduced. Thermal resistance allows the designer to determine power dissipation under steady state conditions. Steady state conditions between junction and case are generally achieved in one to ten seconds while minutes may be required for junction to ambient temperature to become
The mathematical expression for the transient thermal resistance has been determined to be extremely complex. The response is, therefore, plotted from empirical data. Curves, typical of the results obtained, are shown in Figure 8.1. These curves show the relative thermal response of the junction, referenced to the case, resulting from a step function change in power. Observe that the total percentage difference is about 10:1 in the short pulse ( t) region. However, the values of thermal resistance vary over 20:1. Many ON Semiconductor data sheets have a graph similar to that of Figure 8.2. It shows not only the thermal response to a step change in power (the D = 0, or single pulse curve) but also has other curves which may be used to obtain an effective r(t) value for a train of repetitive pulses with different duty cycles. The mechanics of using the curves to find TJ at the end of the first pulse in the train, or to find TJ(pk) once steady state conditions have been achieved, are quite simple and require no background in the subject. However, problems where the applied power pulses are either not identical in amplitude or width, or the duty cycle is not constant, require a more thorough understanding of the principles illustrated in the body of this report.
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USE OF TRANSIENT THERMAL RESISTANCE DATA
Part of the problem in applying thermal response data stems from the fact that power pulses are seldom rectangular, therefore to use the r(t) curves, an equivalent rectangular model of the actual power pulse must be determined. Methods of doing this are described near the end of this note. Before considering the subject matter in detail, an example will be given to show the use of the thermal response data sheet curves. Figure 8.2 is a representative graph which applies to a 2N5886 transistor.
The temperature is desired, a) at the end of the first pulse b) at the end of a pulse under steady state conditions. For part (a) use:
TJ = r(5 ms) RJCPD + TC
The term r(5 ms) is read directly from the graph of Figure 8.2 using the D = 0 curve,
TJ = 0.49
1.17 50 + 75 = 28.5 + 75 = 103.5
The peak junction temperature rise under steady conditions is found by:
TJ = r(t, D) RJC PD + TC
Pulse power PD = 50 Watts Duration t = 5 milliseconds Period p = 20 milliseconds Case temperature, TC = 75C Junction to case thermal resistance, RJC = 1.17C/W
D = t/p = 5/20 0.25. A curve for D= 0.25 is not on the graph; however, values for this duty cycle can be interpolated between the D = 0.2 and D = 0.5 curves. At 5 ms, read r(t) 0.59.
TJ = 0.59
1.17 50 + 75 = 34.5 + 75 = 109.5C
r (t) , Transient Thermal Resistance (Normalized)
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 1 2
1 2 CASE Case 77 Case 77
DIE SIZE (Sq. Mils) 3,600 8,000
0.2
0.5
1.0
2.0
5.0
10
20 50 t, Time (ms)
100
200
500
1000
2000
5000
10,000
Figure 8.1. Thermal Response, Junction to Case, of Case 77 Types For a Step of Input Power
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.01
D = 0.5 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 t, Time (ms) 10 20 50 100 200 500 1000
Figure 8.2. Thermal Response Showing the Duty Cycle Family of Curves
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The average junction temperature increase above ambient is:

TJ(average) TC = RJC PD D = (1.17) (50) (0.25) = 14.62C (3)
(a) Input Power
Pin P1
P2 P4 P3 t0 t1 P2 P1 P3 P3 P1 P2 P4 Time t2 t3 t4 t5 t6 t7 Time
Note that TJ at the end of any power pulse does not equal the sum of the average temperature rise (14.62C in the example) and that due to one pulse (28.5C in example), because cooling occurs between the power pulses. While junction temperature can be easily calculated for a steady pulse train where all pulses are of the same amplitude and pulse duration as shown in the previous example, a simple equation for arbitrary pulse trains with random variations is impossible to derive. However, since the heating and cooling response of a semiconductor is essentially the same, the superposition principle may be used to solve problems which otherwise defy solution. Using the principle of superposition each power interval is considered positive in value, and each cooling interval negative, lasting from time of application to infinity. By multiplying the thermal resistance at a particular time by the magnitude of the power pulse applied, the magnitude of the junction temperature change at a particular time can be obtained. The net junction temperature is the algebraic sum of the terms. The application of the superposition principle is most easily seen by studying Figure 8.3. Figure 8.3(a) illustrates the applied power pulses. Figure 8.3(b) shows these pulses transformed into pulses lasting from time of application and extending to infinity; at to, P1 starts and extends to infinity; at t1, a pulse ( P1) is considered to be present and thereby cancels P1 from time t1, and so forth with the other pulses. The junction temperature changes due to these imagined positive and negative pulses are shown in Figure 8.3(c). The actual junction temperature is the algebraic sum as shown in Figure 8.3(d). Problems may be solved by applying the superposition principle exactly as described; the technique is referred to as Method 1, the pulsebypulse method. It yields satisfactory results when the total time of interest is much less than the time required to achieve steady state conditions, and must be used when an uncertainty exists in a random pulse train as to which pulse will cause the highest temperature. Examples using this method are given in Appendix A under Method 1. For uniform trains of repetitive pulses, better answers result and less work is required by averaging the power pulses to achieve an average power pulse; the temperature is calculated at the end of one or two pulses following the average power pulse. The essence of this method is shown in Figure 8.6. The duty cycle family of curves shown in Figure 8.2 and used to solve the example problem is based on this method; however, the curves may only be used for a uniform train after steady state conditions are achieved. Method 2 in Appendix A shows equations for calculating the temperature at the end of the nth or n + 1 pulse in a uniform train. Where a duty cycle family of curves is available, of course, there is no need to use this method.
Pin (b) Power Pulses Separated Into Components
P4
(c) TJ Change Caused by Components
Time
(d) Composite TJ
TJ
Time
Figure 8.3. Application of Superposition Principle
P PK1 Peak Power (Watts)
50 40 30 20 10 0
P1 P2
P3
t0 t1 t2 0
1.0
t3
2.0 t, Time (ms)
3.0
t4 t5
4.0
Figure 8.4. NonRepetitive Pulse Train (Values Shown Apply to Example in Appendix)
t Po t0 t1
t
T5
t2 t3 2t
t4 t5
t6 t7
t8 t9
(Conditions for numerical examples
Po = 5 Watts t = 5 ms t = 20 ms
Figure 8.5. A Train of Equal Repetitive Pulses
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nth pulse Po Pavg t

t
n+1 pulse
A point to remember is that a high amplitude pulse of a given amount of energy will produce a higher rise in junction temperature than will a lower amplitude pulse of longer duration having the same energy.
Figure 8.6. Model For a Repetitive Equal Pulse Train
(a)
Temperature rise at the end of a pulse in a uniform train before steady state conditions are achieved is handled by Method 3 (a or b) in the Appendix. The method is basically the same as for Method 2, except the average power is modified by the transient thermal resistance factor at the time when the average power pulse ends. A random pulse train is handled by averaging the pulses applied prior to situations suspected of causing high peak temperatures and then calculating junction temperature at the end of the nth or n + 1 pulse. Part c of Method 3 shows an example of solving for temperature at the end of the 3rd pulse in a three pulse burst.
HANDLING NONRECTANGULAR PULSES

P1 A P1T1 = A T1 PP 0.7 PP PP 0.7 PP 0.71 t t t 0.91 t
(b)
The thermal response curves, Figure 8.1, are based on a step change of power; the response will not be the same for other waveforms. Thus far in this treatment we have assumed a rectangular shaped pulse. It would be desirable to be able to obtain the response for any arbitrary waveform, but the mathematical solution is extremely unwieldy. The simplest approach is to make a suitable equivalent rectangular model of the actual power pulse and use the given thermal response curves; the primary rule to observe is that the energy of the actual power pulse and the model are equal. Experience with various modeling techniques has lead to the following guidelines: For a pulse that is nearly rectangular, a pulse model having an amplitude equal to the peak of the actual pulse, with the width adjusted so the energies are equal, is a conservative model. (See Figure 8.7(a)). Sine wave and triangular power pulses model well with the amplitude set at 70% of the peak and the width adjusted to 91% and 71%, respectively, of the baseline width (as shown on Figure 8.7(b)). A power pulse having a sin2 shape models as a triangular waveform. Power pulses having more complex waveforms could be modeled by using two or more pulses as shown in Figure 8.7(c).
(c)

P1 P1 (t1 t0) + P2 (t2 t1) = A P2 A t0 t1 t2
Figure 8.7. Modeling of Power Pulses
As an example, the case of a transistor used in a dc to ac power converter will be analyzed. The idealized waveforms of collector current, IC, collector to emitter voltage, VCE, and power dissipation PD, are shown in Figure 8.8. A model of the power dissipation is shown in Figure 8.8(d). This switching transient of the model is made, as was suggested, for a triangular pulse. For example, TJ at the end of the rise, on, and fall times, T1, T2 and T3 respectively, will be found.
Conditions: TO3 package, RJC = 0.5C/W, IC = 60A, VCE(off) = 60 V TA = 50C tf = 80 s, tr = 20 s VCE(sat) = 0.3 V @ 60 A Frequency = 2 kHz = 500 s Pon = (60) (0.3) = 18 W Pf = 30 30 = 900 W = Pr
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CollectorEmitter Voltage
Assume that the response curve in Figure 8.1 for a die area of 58,000 square mils applies. Also, that the device is mounted on an MS15 heat sink using Dow Corning DC340 silicone compound with an air flow of 1.0 lb/min flowing across the heatsink. (From MS15 Data Sheet, RCS = 0.1C/W and RSA = 0.55C/W).
Procedure: Average each pulse over the period using equation 13 (Appendix A, Method 2), i.e., Pavg
tf
toff
tr
ton
(a)
VCE
Time
+ 0.7 Pr 0.71 tr ) Pon ton ) 0.7 Pf 0.71 tf + (0.7) (900) (0.71) (20) ) (18) (150) 500 500
t t t
(b)
Collector Current
IC
Power Dissipation
80 ) (0.7) (900) (0.71) 500 + 17.9 ) 5.4 ) 71.5 + 94.8 W
Time PD Pf Pr Pon t(Time)
(c)
From equation 14, Method 2A: T1 = [Pavg + (0.7 Pr Pavg)
r(t1 to)] RJC

(d)
PD
0.7 Pf
T1 T2T3 0.7 Pr 0.7 Pf Pon
At this point it is observed that the thermal response curves of Figure 8.1 do not extend below 100 s. Heat transfer theory for one dimensional heat flow indicates that the response curve should follow the t law at small times. Using this as a basis for extending the curve, the response at 14.2 s is found to be 0.023.
0.7 tr t0 t1
ton
0.7 tf t2 t3
t(Time)
Figure 8.8. Idealized Waveforms of IC, VCE and PD in a DC to AC Inverter For the final point T3 we have:
We then have: T1 = [94.8 + (630 94.8).023] (0.5) T1 = (107.11)(0.5) = 53.55C For T2 we have, by using superposition: T2 = [Pavg Pavg r(t2 to) + 0.7 Pr T2 = r(t2 to) 0.7 Pr T2 = r(t2 t1)] RJC T2 = (Pon 0.7 Pr) T2 =
r(t2 t1) + Pon
T2 = [Pavg + (0.7 Pr Pavg) T2 = [94.8 + (630 94.8) r(150 s)] (0.5)
r(t2 t1)] RJC
@ @
T3 = [Pavg Pavg r(t3 to) + 0.7 Pr T3 = r(t3 to) 0.7 Pr r(t3 t1) + Pon T3 = r(t3 t1) Pon
r(t2 to) +
T3 = + 0.7 Pf T3 = [Pavg + (0.7 Pr Pavg) r(t3 to) + T3 = (Pon 0.7 Pr) r(t3 t1) + (0.7 Pf Pon) T3 = r(t3 t2)] RJC T3 = [94.8 + (535.2) r(221 s) + (612) T3 = + (612)
r(t3 t2) r(t3 t2)] RJC
@ @ @ @ @
@ @ @
@ r(164 s) + (18 630)
r(206.8 s
r(56.8s)] (0.5)
T2 = [94.8 + (535.2)(.079) (612)(.075)] (0.5) T2 = [94.8 + 42.3 45.9] (0.5) T2 = (91.2)(0.5) = 45.6C
T3 = [94.8 + (535.2)(0.09) (612) (0.086) + T3 = (612)(0.045)] (0.5) T3 = [94.8 + 481.7 52.63 + 27.54] (0.5) T3 = (117.88)(0.5) = 58.94C
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The junction temperature at the end of the rise, on, and fall times, TJ1, TJ2, and TJ3, is as follows:
TJ1 = T1 + TA + RCA Pavg RCA = RCS = RSA = 0.1 + 0.55 Pavg TJ2 = 45.6 + 50 + (0.65)(94.8) TJ2 = 157.22C TJ3 = T3 + TA + RCA TJ3 = 170.56C TJ(avg) = Pavg (RJC + RCS + RSA) + TA TJ(avg) = (94.8)(0.5 + 0.1 + 0.55) + 50 TJ(avg) = (94.8)(1.15) + 50 = 159.02C Pavg TJ3 = 58.94 + 50 + (0.65)(94.8)
Table 8.1. Several Possible Methods of Solutions 1. Junction Temperature Rise Using PulseByPulse Method A. Temperature rise at the end of the nth pulse for pulses with unequal amplitude, spacing, and duration. B. Temperature rise at the end of the nth pulse for pulses with equal amplitude, spacing, and duration. 2. Temperature Rise Using Average Power Concept Under Steady State Conditions For Pulses Of Equal Amplitude, Spacing, And Duration A. At the end of the nth pulse. B. At the end of the (n + 1) pulse. 3. Temperature Rise Using Average Power Concept Under Transient Conditions. A. At the end of the nth pulse for pulses of equal amplitude, spacing and duration. B. At the end of the n + 1 pulse for pulses of equal amplitude, spacing and duration. C. At the end of the nth pulse for pulses of unequal amplitude, spacing and duration. D. At the end of the n + 1 pulse for pulses of unequal amplitude, spacing and duration.
METHOD 1A FINDING TJ AT THE END OF THE Nth PULSE IN A TRAIN OF UNEQUAL AMPLITUDE, SPACING, AND DURATION General Equation: n Tn Pi [r(t2n1 t2i2) i 1 r(tn1 t2i1)]RJC
@ @ @
TJ1 = 53.55 + 50 + (0.65)(94.8) = 165.17C TJ2 = T2 + TA + RCA
Inspection of the results of the calculations T1, T2, and T3 reveal that the term of significance in the equations is the average power. Even with the poor switching times there was a peak junction temperature of 11.5C above the average value. This is a 7% increase which for most applications could be ignored, especially when switching times are considerably less. Thus the product of average power and steady state thermal resistance is the determining factor for junction temperature rise in this application.
SUMMARY
This report has explained the concept of transient thermal resistance and its use. Methods using various degrees of approximations have been presented to determine the junction temperature rise of a device. Since the thermal response data shown is a step function response, modeling of different wave shapes to an equivalent rectangular pulse of pulses has been discussed. The concept of a duty cycle family of curves has also been covered; a concept that can be used to simplify calculation of the junction temperature rise under a repetitive pulse train.
APPENDIX A METHODS OF SOLUTION
(11)
where n is the number of pulses and Pi is the peak value of the ith pulse. To find temperature at the end of the first three pulses, Equation 11 becomes: T1 = P1 r(t1) RJC T2 = [P1 r(t3) P1 r(t3 t1) T2 = + P2 r(t3 t2)] RJC T3 = [P1 r(t5) P1 r(t5 t1) + P2 r(t5 t2) T3 = P2 r(t5 t3) + P3 r(t5 t4)] RJC Example: Conditions are shown on Figure 4 as: t3 = 1.3 ms t0 = 0 P1 = 40 W t4 = 3.3 ms t1 = 0.1 ms P2 = 20 W t5 = 3.5 ms t2 = 0.3 ms P3 = 30 W Therefore, t1 t0 = 0.1 ms t2 t1 = 0.2 ms t3 t2 = 1 ms t4 t3 = 2 ms t5 t4 = 0.2 ms t3 t1 = 1.2 ms t5 t1 = 3.4 ms t5 t2 = 3.2 ms t5 t3 = 2.2 ms (11C) (11A) (11B)
In the examples, a type 2N3647 transistor will be used; its steady state thermal resistance, RJC, is 35C/W and its value for r(t) is shown in Figure A1.
Definitions: P1, P2, P3 ... Pn = power pulses (Watts) T T1, T2, T3 ... Tn = junction to case temperature at end of P1, P2, P3 ... Pn t0, t1, t2, ... tn = times at which a power pulse begins or ends r(tn tk) = transient thermal resistance factor at end of time interval (tn tk).
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Procedure: Find r(tn tk) for preceding time intervals from Figure 8.2, then substitute into Equations 11A, B, and C. T1 = P1 r(t1) RJC = 40
For 5 pulses, equation 12A is written: T5 = PD RJC [r(4 + t) r(4) + r(3 + t)] T5 = r(3) + r(2 + t) r(2) + r( + t) T5 = r() + r(t)] Example: Conditions are shown on Figure 8.5 substituting values into the preceding expression: T5 = (5) (35) [r(4.20 + 5) r(4.20) + r(3.20 + 5) T5 = + r(3.20) + r(2.20 + 5) r(2.20) + r(20 + 5) T5 = r(20) + r(5)] T5 = (5) (35) [0.6 0.76 + 0.73 0.72 + 0.68 T5 = 0.66 + 0.59 0.55 + 0.33] (5)(35)(0.40) T5 = 70.0C
T2 = [P1 r(t3) P1 r(t3 t1) + P2 r(t3 t2)] RJC T2 = [40 (0.175) 40 (0.170) + 20 (0.155)] 35 T2 = [40 (0.175 0.170) + 20 (0.155)] 35 T2 = [0.2 + 3.1] 35 = 115.5C T3 = [P1 r(t5) P1 r(t5 t1) + P2 r(t5 t2) T3 = P2 r(t5 t3) + P3 r(t5 t4)] JC T3 = [40 (0.28) 40 (0.277) + 20 (0.275) 20 (0.227) T3 = + 30 (0.07)] 35 T3 = [40 (0.28 0.277) + 20 (0.275 0.227) T3 = + 30 (0.07)] 35 T3 = [0.12 + 0.96 + 2.1]{ 35 = 3.18
@ @
0.05
35 = 70C
35 = 111.3C
Note, by inspecting the last bracketed term in the equations above that very little residual temperature is left from the first pulse at the end of the second and third pulse. Also note that the second pulse gave the highest value of junction temperature, a fact not so obvious from inspection of the figure. However, considerable residual temperature from the second pulse was present at the end of the third pulse.
METHOD 1B FINDING TJ AT THE END OF THE Nth PULSE IN A TRAIN OF EQUAL AMPLITUDE, SPACING, AND DURATION
Note that the solution involves the difference between terms nearly identical in value. Greater accuracy will be obtained with long or repetitive pulse trains using the technique of an average power pulse as used in Methods 2 and 3.
METHOD 2 AVERAGE POWER METHOD, STEADY STATE CONDITION
The general equation for a train of equal repetitive pulses can be derived from Equation 11. Pi = PD, ti = t, and the spacing between leading edges or trailing edges of adjacent pulses is .
General Equation: Tn = PDRJC
The essence of this method is shown in Figure 8.6. Pulses previous to the nth pulse are averaged. Temperature due to the nth or n + 1 pulse is then calculated and combined properly with the average temperature. Assuming the pulse train has been applied for a period of time (long enough for steady state conditions to be established), we can average the power applied as:
Pavg
+ PD t
(13)
i r[(n i) ] Expanding:
+
n
r[(n i) + 1 t]
(12)
METHOD 2A FINDING TEMPERATURE AT THE END OF THE Nth PULSE Applicable Equation: Tn = [Pavg + (PD Pavg) r(t)] RJC or, by substituting Equation 13 into 14, (14)
Tn = PD RJC r[(n 1) + t] r[(n 1) ] Tn = + r[(n 2) + t) r[(n 2) ] + r[(n 3) Tn = + t] r[(n 3) ] + . . . + r[(n i) + t] Tn = r[(n i) ] . . . . . + r(t)]
(12A)
Tn
+ t)
t
t r(t) P R 1 t D qJC
(15)
{Relative amounts of temperature residual from P
1, P2, and P3 respectively are indicated by the terms in brackets.
The result of this equation will be conservative as it adds a temperature increase due to the pulse (PD Pavg) to the average temperature. The cooling between pulses has not been accurately accounted for; i.e., TJ must actually be less than TJ(avg) when the nth pulse is applied.
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Example: Find Tn for conditions of Figure 8.5. Procedure: Find Pavg from equation (13) and substitute values in equation (14) or (15). Tn = [(1.25) + (5.0 1.25)(0.33)] (35) Tn = 43.7 + 43.2 = 86.9C METHOD 2B FINDING TEMPERATURE AT THE END OF THE N + 1 PULSE Applicable Equation: Tn + 1 = [Pavg + (PD Pavg) r(t + ) Tn + 1 + PD r(t) PD r()] RJC or, by substituting equation 13 into 16, Tn + 1 =
t
METHOD 3 AVERAGE POWER METHOD, TRANSIENT CONDITIONS
The idea of using average power can also be used in the transient condition for a train of repetitive pulses. The previously developed equations are used but Pavg must be modified by the thermal response factor at time t(2n 1).
METHOD 3A FINDING TEMPERATURE AT THE END OF THE Nth PULSE FOR PULSES OF EQUAL AMPLITUDE, SPACING AND DURATION Applicable Equation: Tn (16)
tr t (2n1)
t r(t) P R 1 t D JC
(18)
) r(t) * r( )
t
t r(t 1 t
))
t
Conditions: (See Figure 8.5) Procedure: At the end of the 5th pulse (See Figure 8.7) . . . (17) T5 = [5/20 r(85) + (1 5/20)r(5)] (5)(35) T5 = [(0.25)(0765) + (0.75)(0.33)] (175) T5 = 77C
PDRJC
Example: Find Tn for conditions of Figure 8.5. Procedure: Find Pavg from equation (13) and substitute into equation (16) or (17). Tn + 1 = [(1.25) + (5 1.25)(0.59) + (5)(0.33) Tn + 1 (5)(0.56)] (35) = 80.9C
This value is a little higher than the one calculated by summing the results of all pulses; indeed it should be, because no cooling time was allowed between Pavg and the nth pulse. The method whereby temperature was calculated at the n + 1 pulse could be used for greater accuracy.
METHOD 3B FINDING TEMPERATURE AT THE END OF THE N + 1 PULSE FOR PULSES OF EQUAL AMPLITUDE, SPACING AND DURATION Applicable Equation: Tn + 1 =
t
Equation (16) gives a lower and more accurate value for temperature than equation (14). However, it too gives a higher value than the true TJ at the end of the n + 1th pulse. The error occurs because the implied value for TJ at the end of the nth pulse, as was pointed out, is somewhat high. Adding additional pulses will improve the accuracy of the calculation up to the point where terms of nearly equal value are being subtracted, as shown in the examples using the pulse by pulse method. In practice, however, use of this method has been found to yield reasonable design values and is the method used to determine the duty cycle of family of curves e.g., Figure 8.2. Note that the calculated temperature of 80.9C is 10.9C higher than the result of example 1B, where the temperature was found at the end of the 5th pulse. Since the thermal response curve indicates thermal equilibrium in 1 second, 50 pulses occurring 20 milliseconds apart will be required to achieve stable average and peak temperatures; therefore, steady state conditions were not achieved at the end of the 5th pulse.
) 1t r(t ) ) ) r(t) * r( ) PD RJC

t r(t 2n1)
t t t
(19)
Example: Conditions as shown on Figure 8.5. Find temperature at the end of the 5th pulse. For n + 1 = 5, n = 4, t2n1 = t7 = 65 ms, T5 = 5 r(65 ms) 20
) r(5 ms) * r(20 ms)
1 5 r(25 ms) 20 (5)(35)
T5 = [(0.25)(0.73) + (0.75)(0.59) + 0.33 0.55](5)(35) T5 = 70.8C
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The answer agrees quite well with the answer of Method 1B where the pulsebypulse method was used for a repetitive train.
METHOD 3C FINDING TJ AT THE END OF THE Nth PULSE IN A RANDOM TRAIN
The technique of using average power does not limit itself to a train of repetitive pulses. It can be used also where the pulses are of unequal magnitude and duration. Since the method yields a conservative value of junction temperature rise it is a relatively simple way to achieve a first approximation. For random pulses, equations 14 through 17 can be modified. It is necessary to multiply Pavg by the thermal response factor at time t(2n 1). Pavg is determined by averaging the power pulses from time of application to the time when the last pulse starts.
Applicable Equations: General: Pavg =
This result is high because in the actual case considerable cooling time occurred between P2 and P3 which allowed TJ to become very close to TC. Better accuracy is obtained when several pulses are present by using equation 110 in order to calculate TJ tC at the end of the nth + 1 pulse. This technique provides a conservative quick answer if it is easy to determine which pulse in the train will cause maximum junction temperature.
METHOD 3D FINDING TEMPERATURE AT THE END OF THE N + 1 PULSE IN A RANDOM TRAIN
The method is similar to 3C and the procedure is identical. Pavg is calculated from Equation 110 modified by r(t2n 1) and substituted into equation 16, i.e.,
Tn + 1 = [Pavg r(t2n1) + (PD Pave) r(t2n1 Tn + 1 = t2n2) + PD r(t2n+1 t2n) PD r(t2n+1 Tn + 1 = t2n1)] RJC
i For 3 Pulses:
+1
t(2i1)t(2i2) Pi t(2n)t(2i2)
(110)
t1 t0 t3 t2 Pavg = P1 + P2 t4 t0 t4 t2 Example:
(111)
The previous example cannot be worked out for the n + 1 pulse because only 3 pulses are present.
Conditions are shown on Figure 8.4 (refer to Method 1A). Procedure: Find Pavg from equation 13 and the junction temperature rise from equation 14. Conditions: Figure 8.4 0.1 20 1 1.21 6.67 3.3 3 = 7.88 Watts T3 = [Pavg r(t5) + (P3 Pavg) r(t5 t4)] RJC = [7.88 (0.28) + (30 7.88) 0.07] 35 = [2.21 + 1.56] 35 = 132C
Table 8.2. Summary Of Numerical Solution For The Repetitive Pulse Train Of Figure 5
Temperature Obtained, C Temperature Desired At End of 5th Pulse Steady State Peak Pulse by Pulse 70.0 (1B) Average Power Average Power Nth Pulse N + 1 Pulse 77 (3A) 86.9 (2A) 70.8 (3B) 80.9 (2B)
Pavg = 40
Note: Number in parenthesis is method used.
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 t, Time (ms) 10 20 50 100 200 500 1000
Figure 8.9. 2N3467 Transient Thermal Response
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1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1
1 2
Case 221 Case 77

1 2
DIE SIZE (Sq. Mils) 8,100 16,900
DEVICE TYPE MCR1066 2N6344
0.2
0.5
1.0
2.0
5.0
10
20 t, Time (ms)
50
100
200
500
1000
2000
5000
10,000
Figure 8.10. Case 77 and TO220 Thermal Response
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 0.2 0.5 1.0 2.0 5.0 10 20 t, Time (ms) 50 100 200 500 1000 2000 5000 10,000
Figure 8.11. TO92 Thermal Response, Applies to All Commonly Used Die
As the price of semiconductor devices decreases, reliability and quality have become increasingly important in selecting a vendor. In many cases these considerations even outweigh price, delivery and service. The reason is that the cost of device fallout and warranty repairs can easily equal or exceed the original cost of the devices. Consider the example shown in Figure 8.12. Although the case is simplistic, the prices and costs are realistic by todays standards. In this case, the cost of failures raised the device cost from 15 cents to 21 cents, an increase of 40%. Clearly, then, investing in quality and reliability can pay big dividends. With nearly three decades of experience as a major semiconductor supplier, ON Semiconductor is one of the largest manufacturers of discrete semiconductors in the world today. Since semiconductor prices are strongly influenced by manufacturing volume, this leadership has permitted ON Semiconductor to be strongly competitive in the marketplace while making massive investments in equipment, processes and procedures to guarantee that the companys afterpurchase costs will be among the lowest in the industry.
Given: Purchase = 100,000 components @ 15 each Assumptions: Line Fallout = 0.1% Assumptions: Warranty Failures = 0.01% Components Cost =100,000 15 = $15,000 Line Fallout Cost = 100 $40 = 4,000 @ $40 per repair Warranty Cost = 10 $200 = 2,000 @ $200 per repair $21,000 Adjusted Cost Per Component = $21,000 100,000 = 21

Definitions: Line Fall out = Module or subassembly failure requiring troubleshooting, parts replacement and retesting Warranty Failure = System field failure requiring in warranty repair Figure 8.12. Component Costs to the User (Including Line Fallout and Warranty Costs)
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Quality and reliability are two essential elements in order for a semiconductor company to be successful in the marketplace today. Quality and reliability are interrelated because reliability is quality extended over the expected life of the product. Quality is the assurance that a product will fulfill customers expectations. Reliability is the probability that a product will perform its intended function satisfactorily for a prescribed life under certain stated conditions. The quality and reliability of ON Semiconductor thyristors are achieved with a four step program: 1. Thoroughly tested designs and materials 2. Stringent inprocess controls and inspections 3. Process average testing along with 100% quality assurance redundant testing 4. Reliability verifications through audits and reliability studies
RELIABILITY MECHANICS
Since reliability evaluations usually involve only samples of an entire population of devices, the concept of the central limit theorem applies and a failure rate is calculated using the 2 distribution through the equation:
2) 2 nt 2 = chi squared distribution where cl r n t = = = = =
l2 (a, 2r
cl + 100 100
Failure rate Confidence limit in percent Number of rejects Number of devices Duration of tests
ESSENTIALS OF RELIABILITY
Paramount in the mind of every semiconductor user is the question of device performance versus time. After the applicability of a particular device has been established, its effectiveness depends on the length of trouble free service it can offer. The reliability of a device is exactly that an expression of how well it will serve the customer. Reliability can be redefined as the probability of failure free performance, under a given manufacturers specifications, for a given period of time. The failure rate of semiconductors in general, when plotted versus a long period of time, exhibit what has been called the bath tub curve (Figure 8.13).
The confidence limit is the degree of conservatism desired in the calculation. The central limit theorem states that the values of any sample of units out of a large population will produce a normal distribution. A 50% confidence limit is termed the best estimate, and is the mean of this distribution. A 90% confidence limit is a very conservative value and results in a higher which represents the point at which 90% of the area of the distribution is to the left of that value (Figure 8.14).
50% CL X 90% CL
FREQUENCY
l, FAILURE RATE
Figure 8.14. Confidence Limits and the Distribution of Sample Failure Rates
INFANT MORTALITY FAILURE RATE RANDOM FAILURE MECHANISM WEAROUT PHENOMENON
Figure 8.13. Failure Rate of Semiconductor
The term (2r + 2) is called the degrees of freedom and is an expression of the number of rejects in a form suitable to 2 tables. The number of rejects is a critical factor since the definition of rejects often differs between manufacturers. Due to the increasing chance of a test not being representative of the entire population as sample size and test time are decreased, the 2 calculation produces surprisingly high values of for short test durations even though the true long term failure rate may be quite low. For this reason relatively large amounts of data must be gathered to demonstrate the real long term failure rate. Since this would require years of testing on thousands of devices, methods of accelerated testing have been developed.
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Years of semiconductor device testing have shown that temperature will accelerate failures and that this behavior fits the form of the Arrhenius equation:
R(t) = Ro(t)e o/KT Where R(t) = reaction rate as a function of time and temperature Ro = A constant t = Time T = Absolute temperature, Kelvin (C + 273) o = Activation energy in electron volts (ev) K = Boltzmans constant = 8.62 105 ev/K
parameters again after marking the device to further reduce any mixing problems associated with the first test. Prior to shipping, the parts are again sampled, tested to a tight sampling plan by our Quality Assurance department, and finally our outgoing final inspection checks for correct paperwork, mixed product, visual and mechanical inspections prior to packaging to the customers.
AVERAGE OUTGOING QUALITY (AOQ) AOQ = Process Average Probability of Acceptance 106 (PPM) Process Average No. of Reject Devices + No. of Devices Tested of Lots Rejected + (1 No. ) No. of Lots Tested
This equation can also be put in the form: AF = Acceleration factor T2 = User temperature T1 = Actual test temperature
Probability of Acceptance
106 = To Convert to Parts Per Million AOQ No. of Reject Devices + No. of Devices Tested 106(PPM)
The Arrhenius equation states that reaction rate increases exponentially with the temperature. This produces a straight line when plotted on loglinear paper with a slope expressed by o. o may be physically interpreted as the energy threshold of a particular reaction or failure mechanism. The overall activation energy exhibited by ON Semiconductor thyristors is 1 ev.
RELIABILITY QUALIFICATIONS/EVALUATIONS OUTLINE:
(1
No. of Lots Rejected ) No. of Lots Tested
THYRISTOR RELIABILITY
Some of the functions of ON Semiconductor Reliability and Quality Assurance Engineering are to evaluate new products for introduction, process changes (whether minor or major), and product line updates to verify the integrity and reliability of conformance, thereby ensuring satisfactory performance in the field. The reliability evaluations may be subjected to a series of extensive reliability testing, such as in the tests performed section, or special tests, depending on the nature of the qualification requirement.
AVERAGE OUTGOING QUALITY (AOQ)
With the industry trend to average outgoing qualities (AOQ) of less than 100 PPM, the role of device final test, and final outgoing quality assurance have become a key ingredient to success. At ON Semiconductor, all parts are 100% tested to process average limits then the yields are monitored closely by product engineers, and abnormal areas of fallout are held for engineering investigation. ON Semiconductor also 100% redundant tests all dc
The reliability data described herein applies to ON Semiconductors extensive offering of thyristor products for low and medium current applications. The line includes not only the pervasive Silicon Controlled Rectifiers (SCRs) and TRIACs, but also a variety of Programmable Unijunction Transistors (PUTs), SIDACs and other associated devices used for SCR and TRIAC triggering purposes. Moreover, these devices are available in different package styles with overlapping current ranges to provide an integral chipandpackage structure that yields lowest cost, consistent with the overriding consideration of high reliability. Some of the various packages and the range of electrical specifications associated with the resultant products are shown in Figure 8.15. To evaluate the reliability of these structures, production line samples from each type of package are being subjected to a battery of accelerated reliability tests deliberately designed to induce longterm failure. Though the tests are being conducted on a continuing basis, the results so far are both meaningful and impressive. They are detailed on the following pages in the hope that they will provide for the readers a greater awareness of the potential for thyristors in their individual application.
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TO92 Case 029/TO226AA

Devices Available: SCRs, TRIACs, PUTs Current Range: to 0.8 A Voltage Range: 30 to 600 V
These improvements are directed towards longterm reliability in the most strenuous applications and the most adverse environments.
DIE GLASSIVATION
TO225AA Case 077/TO126

Devices Available: SCRs, TRIACs Current Range: to 4 A Voltage Range: 200 to 600 V
All ON Semiconductor thyristor die are glasssealed with an ON Semiconductor patented passivation process making the sensitive junctions impervious to moisture and impurity penetration. This imparts to lowcost plastic devices the same freedom from external contamination formerly associated only with hermetically sealed metal packages. Thus, metal encapsulation is required primarily for higher current devices that would normally exceed the powerdissipation capabilities of plastic packages or for applications that specify the hermetic package.
VOIDFREE PLASTIC ENCAPSULATION
Case 267/Axial Lead (Surmetic 50)

Devices Available: SIDAC Voltage Range: 120 to 240 V
A fifth generation plastic package material, combined with improved copper piecepart designs, maximize package integrity during thermal stresses. The voidfree encapsulation process imparts to the plastic package a mechanical reliability (ability to withstand shock and vibration) even beyond that of metal packaged devices. INPROCESS CONTROLS AND INSPECTIONS
INCOMING INSPECTIONS
TO220AB Case 221A

Devices Available: SCRs, TRIACs Current Range: to 55 A Voltage Range: 50 to 800 V
Figure 8.15. Examples of ON Semiconductors Thyristor Packages
Apparently routine procedures, inspection of incoming parts and materials, are actually among the most critical segments of the quality and reliability assurance program. Thats because small deviations from materials specifications can traverse the entire production cycle before being detected by outgoing Quality Control, and, if undetected, could affect longterm reliability. At ON Semiconductor, piecepart control involves the services of three separate laboratories . . . Radiology, Electron Optics and Product Analysis. All three are utilized to insure product integrity: Raw Wafer Quality, in terms of defects, orientation, flatness and resistivity; Physical Dimensions, to tightly specified tolerances; Metal Hardness, to highly controlled limits; Gaseous Purity and Doping Level; Mold Compounds, for voidfree plastic encapsulation.
INPROCESS INSPECTIONS
THYRISTOR CONSTRUCTION THROUGH A TIME TESTED DESIGN AND ADVANCED PROCESSING METHODS A pioneer in discrete semiconductor components and one of the worlds largest suppliers thereof, ON Semiconductor has pyramided continual process and material improvements into thyristor products whose inherent reliability meets the most critical requirements of the market.
As illustrated in Figure 8.16, every major manufacturing step is followed by an appropriate inprocess QA inspection. Quality control in wafer processing, assembly and final test impart to ON Semiconductor standard thyristors a reliability level that easily exceeds most industrial, consumer and military requirements . . . builtin quality assurance aimed at insuring failurefree shipments of ON Semiconductor products.
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RELIABILITY AUDITS
Reliability audits are performed following assembly. Reliability audits are used to detect process shifts which can have an adverse effect on longterm reliability. Extreme stress testing on a realtime basis, for each product run, uncovers process abnormalities that may have escaped the stringent inprocess controls. Typical tests include HTRB/FB (hightemperature reverse bias and forward bias) storage life and temperature cycling. When abnormalities are detected, steps are taken to correct the process.
OUTGOING QC
The most stringent inprocess controls do not guarantee strict adherence to tight electrical specifications.
ON Semiconductors 100% electrical parametric test does by eliminating all devices that do not conform to the specified characteristics. Additional parametric tests, on a sampling basis, provide data for continued improvement of product quality. And to help insure safe arrival after shipment, antistatic handling and packaging methods are employed to assure that the product quality that has been built in stays that way. From rigid incoming inspection of piece parts and materials to stringent outgoing quality verification, assembly and process controls encompass an elaborate system of test and inspection stations that ensure stepbystep adherence to a prescribed procedure designed to yield a high standard of quality.
IN COMING INSP. WAFER & CHEMICALS
DIFFUSION, MOAT ETCH, PHOTOGLASS
RESIS TIVITY INSPECTION
METALLIZATION, 100% DIE ELECT, TESTS SCRIBE & BREAK
ELEC. & VISUAL INSPECTION
INC. INSP. FORM & CLEAN PC. PARTS QA INSPECTION
DIE BOND
QA INSPECTION
LEAD ATTACHMENT
QA INSPECTION
INJECTION MOLD & DEFLASH PLASTIC, CLEAN & SOLDER DIP LEADS, CURE PLASTIC
RELIA BILITY AUDITS
100% ELECT. SELECTION, 100% BIN SPECIFICATION TEST, 100% QA INSPECTION LASER MARKING
OUTGOING QC SAMPLING
100% ANTISTATIC HANDLING/PACKAGING
FINAL VISUAL & MECHANICAL
SHIPPING
Figure 8.16. InProcess Quality Assurance Inspection Points for Thyristors
RELIABILITY TESTS Only actual use of millions of devices, under a thousand different operating conditions, can conclusively establish the reliability of devices under the extremes of time, temperature, humidity, shock, vibration and the myriads of other adverse variables likely to be encountered in practice.
But thorough testing, in conjunction with rigorous statistical analysis, is the nextbest thing. The series of torture tests described in this document instills a high confidence level regarding thyristor reliability. The tests are conducted at maximum device ratings and are designed to deliberately stress the devices in their most susceptible failure models. The severity of the tests compresses into a relatively short
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test cycle the equivalent of the stresses encountered during years of operation under more normal conditions. The results not only indicate the degree of reliability in terms of anticipated failures; they trigger subsequent investigations into failure modes and failure mechanisms that serve as the basis of continual improvements. And they represent a clearcut endorsement that, for ON Semiconductor thyristors, lowcost and high quality are compatible attributes.
Table 8.4. LeakageCurrent Drift after 1000 Hours HTRB

VDRM = 400 V
TA = 100C
BLOCKING LIFE TEST
This test is used as an indicator of longterm operating reliability and overall junction stability (quality). All semiconductor junctions exhibit some leakage current under reversebias conditions. Thyristors, in addition, exhibit leakage current under forwardbias conditions in the off state. As a normal property of semiconductors, this junction leakage current increases proportionally with temperature in a very predictable fashion. Leakage current can also change as a function of time particularly under hightemperature operation. Moreover, this undesirable drift can produce catastrophic failures when devices are operated at, or in excess of, rated temperature limits for prolonged periods. The blocking life test operates representative numbers of devices at rated (high) temperature and reversebias voltage limits to define device quality (as measured by leakage drifts) and reliability (as indicated by the number of catastrophic failures*). The results of these tests are shown in Table 8.3. Table 8.4 shows leakagecurrent drift after 1000 hours HTRB.
40 A
20 A
+20 A
+40 A
Leakage Shift from Initial Value

The favorable blockinglifetest drift results shown here are attributed to ON Semiconductors unique glassivated junction process which imparts a high degree of stability to the devices.
HIGH TEMPERATURE STORAGE LIFE TEST
Table 8.3. Blocking Life Test High Temperature Reverse Bias (HTRB) and High Temperature Forward Bias (HTFB)
Test Conditions TA @ Rated Voltage 100C 110C 100C 125C Sample Duration Size (Hours) Total Device Hours Catastrophic Failures*
This test consists of placing devices in a hightemperature chamber. Devices are tested electrically prior to exposure to the high temperature, at various time intervals during the test, and at the completion of testing. Electrical readout results indicate the stability of the devices, their potential to withstand high temperatures, and the internal manufacturing integrity of the package. Readouts at the various intervals offer information as to the time period in which failures occur. Although devices are not exposed to such extreme high temperatures in the field, the purpose of this test is to accelerate any failure mechanisms that could occur during long periods at actual storage temperatures. Results of this test are shown in Table 8.5.
Table 8.5. High Temperature Storage Life
Case Test Conditions TA = 150C ** Sample Duration Size (Hours) 10002000 10002000 1000 1000 400 Total Device Hours 1,500,000 Catastrophic Failures* 0
Case
Case 029/TO226AA (TO92) Case 077/TO225AA (TO126) Case 221A/TO220AB Case 267/Axial Lead (Surmetic 50)
1000
1000
1,000,000
Case 029/TO226AA (TO92) Case 077/TO225AA (TO126) Case 221A/TO220
350
550,000
1000
1000
1,000,000
300 100
300,000 100,000
0 0
1000 150
1000 1000
1,000,000 150,000
0 0
Case 267/Axial Lead (Surmetic 50)
* Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions.
* Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions. ** Same for all.
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STRESS TESTING POWER CYCLING AND THERMAL SHOCK

POWER CYCLING TEST
THERMAL SHOCK CONDITIONS BEYOND THE NORM Excesses in temperature not only cause variations in electrical characteristics, they can raise havoc with the mechanical system. Under temperature extremes, contraction and expansion of the chip and package can cause physical dislocations of mechanical interfaces and induce catastrophic failure. To evaluate the integrity of ON Semiconductor thyristors under the most adverse temperature conditions, they are subjected to thermal shock testing.
AIRTOAIR (TEMPERATURE CYCLING)
How do the devices hold up when they are repeatedly cycled from the off state to the on state and back to the off state under conditions that force them to maximum rated junction temperature during each cycle? The Power Cycling Test was devised to provide the answers. In this test, devices are subjected to intermittent operating file (IOL), onstate power until the junction temperature (TJ) has increased to 100C. The devices are then turned off and TJ decreases to near ambient, at which time the cycle is repeated. This test is important to determine the integrity of the chip and lead frame assembly since it repeatedly stresses the devices. It is unlikely that these worstcase conditions would be continuously encountered in actual use. Any reduction in TJ results in an exponential increase in operating longevity. Table 8.6 shows the results of IOL testing.
This thermal shock test is conducted to determine the ability of the devices to withstand exposure to extreme high and low temperature environments and to the shock of alternate exposures to the temperature extremes. Results of this test are shown in Table 8.6.
Table 8.6. AirtoAir

Case Case 029/TO226AA (TO92) Case 077/TO225AA (TO126) Case 221A/TO220 Case 267/Axial Lead (Surmetic 50) Test Conditions 40C or 65C to +150C D ll 15 minutes Dwell15 i t at t each h extreme t Immediate Transfer Sample Size 900 500 400 100 Number of cycles 400 400 400 400 Total Device Cycles 360,000 200,000 160,000 40,000 Catastrophic Failures* 0 0 0 0
ENVIRONMENTAL TESTING
MOISTURE TESTS
the use of a unique junction glassivation process and selection of package materials. The resistance to moisture related failures is indicated by the tests described here.
BIASED HUMIDITY TEST
Humidity has been a traditional enemy of semiconductors, particularly plastic packaged devices. Most moisture related degradations result, directly or indirectly, from penetration of moisture vapor through passivating materials, and from surface corrosion. At ON Semiconductor, this erstwhile problem has been effectively controlled through
This test was devised to determine the resistance of component parts and constituent materials to the combined deteriorative effects of prolonged operation in a hightemperature/highhumidity environment. H3TRB test results are shown in Table 8.7.
Table 8.7. Biased Humidity Test High Humidity, High Temperature, Reverse Bias (H3TRB)
Case Case 029/TO226AA (TO92) Case 077/TO225AA Case 221A/TO220 Case 267/Axial Lead (Surmetic 50) Test Conditions Relative Humidity 85% TA = 85C Reverse VoltageRated or 200 V Maximum Sample Size 400 200 100 30 Duration Hours 5001000 5001000 5001000 1000 Total Device Cycles 300,000 150,000 75,000 30,000 Catastrophic Failures* 0 0 0 0
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SECTION 9 APPENDICES
APPENDIX I USING THE TWO TRANSISTOR ANALYSIS
DEFINITIONS: IC IB ICS
5 Collector current 5 Base current 5 Collector leakage current (saturation component) IA 5 Anode current IK 5 Cathode current 5 Current amplification factor IG 5 Gate current
The subscript i indicates the appropriate transistor.
Equation (3) relates IA to IG, and note that as 1 + 2 = 1, IA goes to infinity. IA can be put in terms of IK and s as follows:
IB1 = IC2 Combining equations (1) and (2): IA
+ +
ICS1 1
I a1 ( K) a2 I A
) ICS2
IA if denominator approaches zero, i.e., if 1 a1 IK a2 IA
FOR TRANSISTOR #1: IC1 = 1 IA + ICSI and IB1 = IA IC1 Combining these equations, IB1 = (1 1) IA ICS1 (1)
Note that just prior to turnon there is a majority carrier buildup in the P2 base. If the gate bias is small there will actually be hole current flowing out from P2 into the gate circuit so that IG is negative, IK = IA + IG is less than IA so: (see Figure 3.2 for the directions of current components)
IK < 1 which corresponds to 1 + 2 > 1 IA
A IA P1 DEVICE #1 N1 P2 IC1 IG IB2 IB1 IC2 N1 N2 P2 DEVICE #2
LIKEWISE, FOR TRANSISTOR #2 IC2 = 2IK + ICS2 IB1 = IC2 and by combining Equations (1) and (2) and substituting IK = IA + IG, it is found that a2IG ICS1 ICS2 IA 1 a1 a2
(2)
IK K
(3)
Figure 9.1. Schematic Diagram of the Two Transistor Model of a Thyristor
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APPENDIX II CHARGE AND PULSE WIDTH In the region of large pulse widths using current triggering, where transit time effects are not a factor, we can consider the input gate charge for triggering, Qin, as consisting of three components: 1. Triggering charge Qtr, assumed to be constant. 2. Charge lost in recombination, Qr, during current regeneration prior to turnon. 3. Charge drained, Qdr, which is bypassed through the builtin gate cathode shunt resistance (the presence of this shunting resistance is required to increase the dv/dt capability of the device). Mathematically, we have
Qin = Qtr + Qdr + Qr = IG (1)
Assume life time at the temperature range of operation increases as some power of temperature
1 = KTm (5)
where K and m are positive real numbers. Combining Equations (4) and (5), we can get the slope of Qin with respect to temperature to be
slope in GC ) + dQ + m(Qtr ) VR dT s
t t t1 t exp. t1 T
(6)
In reality, Qtr is not independent of temperature, in which case the Equation (6) must be modified by adding an additional term to become:
slope GC ) + m(Qtr ) VR s
t t t1 t exp. t1 T
Qr is assumed to be proportional to Qin; to be exact,

Qr = Qin (1 exp/1) (2) where IG = gate current, = pulse width of gate current, 1 = effective life time of minority carriers in the bases
)dQtr dT
expt t1 (7)
Physically, not only does Qtr decrease with temperature so that dQtr/dT is a negative number, but also |dQtr/dTI decreased with temperature as does |d/dTI in the temperature range of interest. Equation (6) [or (7)] indicates two things: 1. The rate of change of input trigger charge decreases as temperature (life time) increases. 2. The larger the pulse width of gate trigger current, the faster the rate of change of Qin with respect to change in temperature. Figure 3.11 shows these trends.
The voltage across the gate to cathode PN junction during forward bias is given by VGK (usually 0.6 V for silicon).* The gate shunt resistance is Rs (for the MCR729, typically 100 ohms), so the drained charge can be expressed by
Qdr GC + VR s
t
(3)
Combining equations (1), (2), and (3), we get

Qin GC + IG + (Qtr ) VR s
t t)
exp.
t t1
(4)
Note that at region A and C of Figure 3.3(c) Qin has an increasing trend with pulse width as qualitatively described by Equation (4).
*VGC is not independent of IG. For example, for the MCR729 the saturation VGC is typically 1 V, but at lower IGs the VGC is also smaller, e.g. for IG = 5 mA, VGC is typically 0.3 V.
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APPENDIX III TTL SOA TEST CIRCUIT Using the illustrated test circuit, the two TTL packages (quad, 2input NAND gates) to be tested were powered by the simple, series regulator that is periodically shorted by the clamp transistor, Q2, at 10% duty cycle rate. By varying the input to the regulator V1 and the clamp pulse width, various power levels can be supplied to the TTL load. Thus, as an example, VCC could be at 5 V for 90 ms and 10 V for 10 ms, simulating a transient on the bus or a possibly shorted power supply pass transistor for that duration. These energy levels are progressively increased until the gate (or gates) fail, as detected by the status of the output LEDs, the voltage and current waveforms and the device case temperature.
VCC V1 MJE220 Q1 220 5.6 V 2W 1W VCC V1 1k 100 F 1N4739 Q2 MJE230 10 V 1N5240 10 M MC14011 V2 = 10 V G4 0.1 F 10 k 1k 2N3904 Q4 1A VCC 300 1D SQUARE WAVE GENERATOR f 1 Hz V2 T1 T2 2D (2) MC7400 DUT 300 LED 220 2A VCC LED 3.9 M 10 k 220
G3
1k 470 10 k V2 G1 10 k
2N3904 Q3
G2 100 k
10 k 0.47 F
5 ms < T2 < 250 ms 50 ms < T2 < 1.9 s 500 k 1N914 5M 1N914 2.2 M
10% DUTY CYCLE GENERATOR
Figure 9.2. TTL SOA Test Circuit
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APPENDIX IV SCR CROWBAR LIFE TESTING This crowbar life test fixture can simultaneously test ten SCRs under various crowbar energy and gate drive conditions and works as follows. The CMOS Astable M.V. (Gates 1 and 2) generate an asymmetric Gate 2 output of about ten seconds high, one second low. This pulse is amplified by Darlington Q22 to turn on the capacitor charging transistors Q1Q10 for the ten seconds. The capacitors for crowbarring are thus charged in about four seconds to whatever power supply voltage to which VCC1 is set. The charging transistors are then turned off for one second and the SCRs are fired by an approximately 100 s delayed trigger derived from Gates 3 and 4. The RC network on Gate 3 input integrates the complementary pulse from Gate 1, resulting in the delay, thus insuring noncoincident firing of the test circuit. The shaped pulse out of Gate 4 is differentiated and the positivegoing pulse is amplified by Q21 and the following ten SCR gate drivers (Q11Q20) to form the approximate 2 ms wide, 1 s rise time, SCR gate triggers, IGT. IGT is set by the collector resistors of the respective gate drivers and the supply voltage, VCC2; thus, for IGT 100 mA, VCC2 30 V, etc. The LEDs across the storage capacitors show the state of the voltage on the capacitors and help determine whether the circuit is functioning properly. The timing sequence would be an off LED for the onesecond capacitor dump period followed by an increasingly brighter LED during the capacitor charge time. Monitoring the current of VCC1 will also indicate proper operation. The fixtures maximum energy limits are set by the working voltage of the capacitors and breakdown voltage of the transistors. For this illustration, the 60 V, 8400 F capacitors (ESR 20 m) produced a peak current of about 2500 A lasting for about 0.5 ms when VCC1 equals 60 V. Other energy values (lower ipk, greater tw) can be obtained by placing a current limiting resistor between the positive side of the capacitor and the crowbar SCR anode.
VDD
+ 15 V 0.1 F
10 k 1N914
100 k 0.001 F
4 VSS
Q21 MJE803
MC14011B 470 +15 V 1 +15 V 2 10 k Q22 2.2 k VCC1 2W 470 MJE803 1N914 0.47 F 2.2 k 2W Q10 MJE250 2.7 k 1W (10) LED 100 5W 8400 F C10 2.2 k 2W
VCC1 VCC2 MJE250 Q1 MJE250 470 R1 2.7 k 1W 100 5W 8400 F C1 Q11 2.2 k
22 M
22 M
2.2 M
270 DUT #1
VCC2 470 MJE250 Q20 270 DUT #10 2.2 k
Figure 9.3. Schematic for SCR Crowbar Life Test
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APPENDIX V DERIVATION OF THE RMS CURRENT OF AN EXPONENTIALLY DECAYING CURRENT WAVEFORM

i = Ipket/
APPENDIX VI DERIVATION OF I2t FOR VARIOUS TIMES
Thermal Equation where and

T=5
Ipk
t = Z()PD Z() = r(t)RJC r(t) = K t
Irms
+ + + + +
Ipk2 T
Therefore, for the same t,
Dt + K
t1
T 1 i2(t)dt T 0 T
RqJCPD 1 2
PD 12
1 (I et t)2dt T 0 pk Ipk2 e2t t T T (2 t) 0
PD
+ K t2 RqJC PD 2, + II12R , R
2 2 t2 t1
t2 t1
t 2
1 2
2 I1 I22
Multiplying both sides by (t1/t2),
(e2T
1 2
t
e0)
2 I1 t1 I22t2
+
t2 1 2 t1 t1 t2
I12t1
+ I22t2
where T = 5, Ipk2 (e10 1) 10
t1 1 2 , t2
t1 t2
1 2
Irms
Ipk + + 0.316 Ipk 10
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APPENDIX VII THERMAL RESISTANCE CONCEPTS The basic equation for heat transfer under steadystate conditions is generally written as:
q = hAT (1)
where q = rate of heat transfer or power dissipation (PD), h = heat transfer coefficient, A = area involved in heat transfer, T = temperature difference between regions of heat transfer.
However, electrical engineers generally find it easier to work in terms of thermal resistance, defined as the ratio of temperature to power. From Equation (1), thermal resistance, R, is
R = T/q = 1/hA (2)
The thermal resistance junction to ambient is the sum of the individual components. Each component must be minimized if the lowest junction temperature is to result. The value for the interface thermal resistance, RCS, is affected by the mounting procedure and may be significant compared to the other thermalresistance terms. The thermal resistance of the heat sink is not constant; it decreases as ambient temperature increases and is affected by orientation of the sink. The thermal resistance of the semiconductor is also variable; it is a function of biasing and temperature. In some applications such as in RF power amplifiers and shortpulse applications, the concept may be invalid because of localized heating in the semiconductor chip.
The coefficient (h) depends upon the heat transfer mechanism used and various factors involved in that particular mechanism. An analogy between Equation (2) and Ohms Law is often made to form models of heat flow. Note that T could be thought of as a voltage; thermal resistance corresponds to electrical resistance (R); and, power (q) is analogous to current (l). This gives rise to a basic thermal resistance model for a semiconductor (indicated by Figure 9.4). The equivalent electrical circuit may be analyzed by using Kirchoffs Law and the following equation results:
TJ = PD(RJC + RCS + RSA) + TA where TJ = junction temperature, PD = power dissipation, RJC = semiconductor thermal resistance (junction to case), RCS = interface thermal resistance (case to heat sink), RSA = heat sink thermal resistance (heat sink to ambient), TA = ambient temperature. (3)
TJ, JUNCTION TEMPERATURE RJC TC, CASE TEMPERATURE TS, HEAT SINK TEMPERATURE TA, AMBIENT TEMPERATURE RCS RSA PD
REFERENCE TEMPERATURE
Figure 9.4. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor
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APPENDIX VIII DERIVATION OF RFI DESIGN EQUATIONS

df dt where: N is total turns Erms is line voltage tr is allowable current rise time in seconds BMAX is maximum usable flux density of core material Ac is usable core area in square inches Window area necessary is: Aw = N Awire 3
The relationship of flux to voltage and time is E = N
or E = NAc dB since = BAc and Ac is a constant. dt Rearranging this equation and integrating we get:
E dt = NAc (B2 B1) = NAc B (1)
(4)
which says that the voltsecond integral required determines the size of the core. In an LR circuit such as we have with a thyristor control circuit, the voltsecond characteristic is the area under an exponential decay. A conservative estimate of the area under the curve may be obtained by considering a triangle whose height is the peak line voltage and the base is the allowable switching time. The area is then 1/2 bh or . 2 Substituting in Equation (1):
Eptr 2 Eptr
The factor of 3 is an approximation which allows for insulation and winding space not occupied by wire. Substituting equation (3) in (4):
Aw rms tr + 10.93BE MAX Ac 106 Awire 3
(The factor 10.93 may be rounded to 11 since two significant digits are all that are necessary.) The factor AcAw can easily be found for most cores and is an easy method for selecting a core.
Ac Aw rAwire + 33 ErmsBtMAX 106
+ N Ac D
(2)
where: Ep is the peak line voltage tr is the allowable current rise time N is the number of turns on the coil Ac is the usable core area in cm2 B is the maximum usable flux density of the core material in W/m2
In this equation, the core area is in in2. To work with circular mils, multiply by 0.78 106 so that:
Ac Aw
trAwire + 26 Erms BMAX
Rewriting Equation (2) to change B from W/m2 to gauss, substituting 2 Erms for Ep and solving for N, we get:
N Erms tr + 22 A c D B
where Awire is the wire area in circular mils. Inductance of an iron core inductor is
L
108
rms tr + 0.707BE MAX Ac
108
Ac in this equation is in cm2. To change to in2, multiply Ac by 6.452. Then:

N Erms tr 106 + 10.93 BMAX Ac (3)
+ 3.19 N2 A1cc 108 Ig ) m

2 8 1 c m
Rearranging terms,
Ig
+ 3.19 N LAc 10
APPENDIX IX BIBLIOGRAPHY ON RFI Electronic Transformers and Circuits, Reuben Lee, John Wiley and Sons, Inc., New York, 1955. Electrical Interference, Rocco F. Ficchi, Hayden Book Company, Inc., New York, 1964. ElectromagneticInterference Control, Norbert J. Sladek, Electro Technology, November, 1966, p. 85. TransmitterReceiver Pairs in EMI Analysis, J. H. Vogelman, Electro Technology, November, 1964, p. 54. Radio Frequency Interference, Onan Division of Studebaker Corporation, Minneapolis, Minnesota. Interference Control Techniques, Sprague Electric Company, North Adams, Massachusetts, Technical Paper 621, 1962. Applying Ferrite Cores to the Design of Power Magnetics, Ferroxcube Corporation of America, Saugerties, New York, 1966.
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CHAPTER 2 Selector Guide
In Brief . . .
ON Semiconductors broad line of Thyristors includes . . . A full line of Silicon Controlled Rectifiers (SCRs) covering a forward current range of 0.8 to 55 amps and blocking voltages from 30 volts to 800 volts. Available in a choice of seven different plastic packages in both through hole and surface mount, for space saving requirements. An extensive line of Triacs (bidirectional devices) from 0.6 to 40 amps with blocking voltages from 200 to 800 volts. Like the SCRs, the Triacs are available in a choice of seven different plastic packages, including the UL registered isolated TO220 package. A new line of Thyristor Surge Suppressors in the surface mount SMB package covering surge currents of 50 and 100 amps, with break over voltages from 265 to 365 volts. Trigger devices, including Sidacs and PUTs (Programmable Unijunction Transistors). Trigger devices are available in both the axial lead and TO92 packages. Finally, ON Semiconductor, formerly a division of Motorola, continues its 30 plus years of leadership in Thyristor products which has made it a leader in new product innovations.
Page SCRs: Silicon Controlled Rectifiers . . . . . . . . . . . . . . . 249 TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Surge Suppressors and Triggers . . . . . . . . . . . . . . . . . 256
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SCRs
Silicon Controlled Rectifiers
Style 4 A K A G K A A G A A
Style 5 G G A K G K
OnState RMS Current IT(RMS) (Amps) 0.8
Blocking Voltage VDRM, VRRM (Volts) 30 60 100 200
TO92(1) (TO226AA) Case 029 Style 10 2N5060 2N5061 2N5062 2N5064 MCR1003 MCR1004 MCR1006 MCR1008
SOT223 Case 318E Style 10
TO225AA (TO126) Case 077 Style 2
DPAK Case 369A Style 4 & 5
Surge Current ITSM (Amps) 60 Hz 10
Max IGT (mA) 0.2
Max VGT (Volts) 0.8
Data Sheet Page Number in Book 258
0.8
100 200 400 600
10
0.2
0.8
566
0.8 1.5 4.0
200 600 400 600 200 400 400 600 600 MCR226 MCR228
MCR08BT1 MCR08MT1
8.0 15 C106B C106D C106D1 C106M C106M1 MCR1066 MCR1068 MCR703AT4(2) MCR704AT4(2) MCR706AT4(2) MCR708AT4(2) MCR716T4(3) MCR718T4(3) 25 25 25 20
0.2 0.2 0.2
0.8 0.8 0.8
491 543 303
4.0 4.0
400 600 100 200 400 600
0.2 0.1
1.0 0.8
572 597
4.0
400 600
0.1
0.8
602
(1) See TO92 data sheets for complete device suffix packaging ordering options. RLRA, RLRE, RL, & RL1 suffixes: Radial Tape and Reel RLRM & ZL1 suffixes: Radial Tape and Ammo Pack (2) Denotes pkg style 4 (3) Denotes pkg style 5 Shaded devices denote sensitive gate SCRs
Lead Identification A = Anode K = Cathode G = Gate
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SCRs (continued)
A A K A A
G K A G K A G K A G
)
Surge Current ITSM (Amps) 60 Hz 80 Data Sheet Page Number in Book 499 514
OnState RMS Current IT(RMS) (Amps) 8.0 8.0
Blocking Voltage VDRM, VRRM (Volts) 600 800 400 600 800
DPAK Case 369A Style 4 MCR8DCMT4 MCR8DCNT4
TO220AB Case 221A09 Style 3
Isolated TO220 Case 221C Style 2
Max IGT (mA) 15 0.2
Max VGT (Volts) 1.0 1.0
MCR8SD MCR8SM MCR8SN MCR8M MCR8N C122F1 C122B1 MCR8DSMT4 MCR8DSNT4 MCR723 MCR726 MCR728 MCR2182 MCR2184 MCR2186 MCR2186FP MCR21810FP MCR12LD MCR12LM MCR12LN MCR12DSMT4 MCR12DSNT4 MCR12DCMT4 MCR12DCNT4 MCR12D MCR12M MCR12N MCR682
80
8.0 8.0 8.0 8.0
600 800 50 200 600 800 100 400 600
80 90 90 100
15 25 0.2 0.2
1.0 1.5 1.0 1.5
510 308 504 563
8.0
50 200 400
100
25
1.5
575
8.0 10
400 800 400 600 800
100 100
25 8.0
1.5 0.8
579 534
12 12 12
600 800 600 800 400 600 800
100 100 100
0.2 20 20
1.0 1.0 1.0
528 522 518
12
50
100
30
1.5
555
UL logo indicates UL Recognized File #E69369 Shaded devices denote sensitive gate SCRs
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SCRs (continued)
A A
K A G
K A G
K A
)
Surge Current ITSM (Amps) 60 Hz 100 Data Sheet Page Number in Book 288
OnState RMS Current IT(RMS) (Amps) 12
Blocking Voltage VDRM, VRRM (Volts) 50 100 400 800
TO220AB Case 221A07 Style 3 2N6394 2N6395 2N6397 2N6399
Max IGT (mA) 30
Max VGT (Volts) 1.5
16 16
800 50 100 200 400 600 800
MCR16N 2N6400 2N6401 2N6402 2N6403 2N6404 2N6405 MCR25D MCR25M MCR25N 2N6504 2N6505 2N6507 2N6508 2N6509 MCR692 MCR693 MCR2258FP MCR22510FP MCR2644 MCR2646 MCR2648 MCR2654 MCR2656 MCR2658 MCR26510
160 160
20 30
1.0 1.5
538 293
25
400 600 800
300
30
1.0
550
25
50 100 400 600 800
300
30
1.5
298
25 25 40
50 100 600 800 200 400 600
300 300 400
30 40 50
1.5 1.5 1.5
559 584 589
55
200 400 600 800
550
50
1.5
593
UL logo indicates UL Recognized File #E69369
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TRIACs (Bidirectional Devices)

MT2 MT2 MT1 MT2 G G MT2 MT1 MT1 MT2 G MT2 MT1 MT2 G
MT2 G MT1
Max IGT (mA) OnState RMS Current IT(RMS) (Amps) 0.6 Blocking Voltage VDRM, VRRM (Volts) 600 200 400 600 0.8 400 600 0.8 2.5 4.0 200 600 200 200 400 600 4.0 4.0 4.0 600 600 600 800 4.0 600 800 TO92(1) (TO226AA) Case 029 Style 12 MAC978 MAC97A4 MAC97A6 MAC97A8 MAC997A6 MAC997B6 MAC997A8 MAC997B8 MAC08BT1 MAC08MT1 T2322B 2N6071A 2N6071B 2N6073A 2N6073B 2N6075A 2N6075B MAC4DLMT4(2) MAC4DLM1(3) MAC4DHMT4(2) MAC4DHM1(3) MAC4DSMT4(2) MAC4DSMT1(3) MAC4DSNT4(2) MAC4DSN1(3) MAC4DCMT4(2) MAC4DCM1(3) MAC4DCNT4(2) MAC4DCN1(3) Lead Identification MT1 = Main Terminal 1 MT2 = Main Terminal 2 G = Gate 40 35 35 35 320 40 40 40 25 30 10 5.0 3.0 5.0 3.0 5.0 3.0 3.0 5.0 10 10 5.0 3.0 5.0 3.0 5.0 3.0 3.0 5.0 10 10 5.0 3.0 5.0 3.0 5.0 3.0 3.0 5.0 10 10 10 5.0 10 5.0 10 5.0 5.0 10 334 328 340 627 272 8.0 8.0 TO225AA (TO126) Case 077 Style 5 Surge Current ITSM (Amps) 60 Hz 8.0 Data Sheet Page Number in Book 425
SOT223 Case 318E Style 11
DPAK Case 369A Style 6
Q1 10 5.0 5.0 5.0 5.0 3.0 5.0 3.0 10
Q2 10 5.0 5.0 5.0 5.0 3.0 5.0 3.0 10
Q3 10 5.0 5.0 5.0 5.0 3.0 5.0 3.0 10
Q4 10 7.0 7.0 7.0 7.0 5.0 7.0 5.0 10
483
311
(1) See TO92 data sheets for complete device suffix packaging ordering options. RLRA, RLRE, RL, & RL1 suffixes: Radial Tape and Reel RLRM & ZL1 suffixes: Radial Tape and Ammo Pack (2) Denotes SMT package (3) Denotes straight lead package Shaded devices denote sensitive gate Triacs
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TRIACs (Bidirectional Devices) (continued)

MT2 MT2
MT1 MT2
MT1 MT2 G
MT1 MT2
)
Max IGT (mA)
OnState RMS Current IT(RMS) (Amps) 4.0 4.0 6.0 8.0
Blocking Voltage VDRM, VRRM (Volts) 600 800 600 800 400 400 600 800
TO220AB Case 221A09 Style 4 MAC4SM MAC4SN MAC4M MAC4N
Surge Current ITSM (Amps) 60 Hz 40 40
Q1 10 35 25 5.0
Q2 10 35 60 5.0
Q3 10 35 25 5.0
Q4 60
Data Sheet Page Number in Book 353 348 630 363
T2500D MAC8SD MAC8SM MAC8SN MAC8D MAC8M MAC8N MAC9D MAC9M MAC9N MAC228A4 MAC228A6 MAC228A8 MAC228A10 MAC229A8FP MAC229A10FP 2N6344 2N6349 T2800D MAC218A6FP MAC218A10FP
60 70
8.0
400 600 800
80
35
35
35
358
8.0
400 600 800
80
50
50
50
369
8.0
200 400 600 800
80
5.0
5.0
5.0
10
470
8.0 8.0 8.0 8.0
600 800 600 800 400 400 800
80 100 100 100
10 50 25 50
10 75 60 50
10 50 25 50
20 75 60 75
474 278 633 453
UL logo indicates UL Recognized File #E69369 Shaded devices denote sensitive gate Triacs
Lead Identification MT1 = Main Terminal 1 MT2 = Main Terminal 2 G = Gate
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MT2 MT2
MT1 MT2
MT1 MT2 G
MT1 MT2
)
Max IGT (mA)
OnState RMS Current IT(RMS) (Amps) 10 10 12 12
Blocking Voltage VDRM, VRRM (Volts) 600 800 600 800 600 800 400 600 800
TO220AB Case 221A07 Style 4 MAC210A8 MAC210A10
Q1 50 50 5.0 50
Q2 50 50 5.0 50
Q3 50 50 5.0 50
Q4 75 75
Data Sheet Page Number in Book 433 438 384 379
MAC210A8FP MAC210A10FP MAC12SM MAC12SN MAC12HCD MAC12HCM MAC12HCN MAC12D MAC12M MAC12N MAC212A8 MAC212A10 MAC212A6FP MAC212A8FP MAC212A10FP 2N6344A 2N6348A 2N6349A MAC15SD MAC15SM MAC15SN MAC15M MAC15N
100 90 100
12
400 600 800
100
35
35
35
374
12 12
600 800 400 600 800
100 100
50 50
50 50
50 50
75 75
448 443
12
600 600 800
100
50
75
50
75
283
15
400 600 800
120
5.0
5.0
5.0
404
15
600 800
150
35
35
35
399
UL logo indicates UL Recognized File #E69369 Shaded devices denote sensitive gate Triacs
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254

MT2 MT2
MT1 MT2
MT1 MT2 G
MT1 MT2
)
Max IGT (mA)
OnState RMS Current IT(RMS) (Amps) 15
Blocking Voltage VDRM, VRRM (Volts) 600 800 400 600 800
TO220AB Case 221A07 Style 4 MAC158 MAC1510 MAC15A6 MAC15A8 MAC15A10
Q1 50 50 50 50 50
Q2 50 50 50 50 50 50
Q3 50 50 50 50 50 50
Q4 75 75 75 75
Data Sheet Page Number in Book 389
15
400 600 800
MAC15A6FP MAC15A8FP MAC15A10FP MAC16D MAC16M MAC16N MAC16CD MAC16CM MAC16CN MAC16HCD MAC16HCM MAC16HCN MAC320A8FP MAC223A6 MAC223A8 MAC223A10 MAC223A6FP MAC223A8FP MAC223A10FP MAC224A4 MAC224A6 MAC224A8 MAC224A10
150
50
394
16
400 600 800
150
50
50
50
415
16
400 600 800
150
35
35
35
410
16
400 600 800
150
50
50
50
420
20 25
600 400 600 800
150 250
50 50
50 50
50 50
75 75
478 457
25
400 600 800
250
50
50
50
75
461
40
200 400 600 800
350
50
50
50
75
465
UL logo indicates UL Recognized File #E69369
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255
Surge Suppressors and Triggers

Thyristor Surge Suppressors (Bidirectional Devices)
MT1
(
MT2

SMB Case 403C General Description 50 170 200 270 170 200 270 MMT05B230T3 MMT05B260T3 MMT05B310T3 MMT10B230T3 MMT10B260T3 MMT10B310T3 265 320 365 265 320 365 175 175 175 175 175 175 100 These Thyristor Surge Protection d i devices prevent t overvoltage lt damage d to sensitive circuits by lightening, induction, and power line crossing. They are breakover triggered crowbar rotectors with turn off occurring protectors when the surge g current falls below the holding current value. 615 621
Surge Current IPPS1 10 x 1000 sec (Amps)
Maximum OffState Voltage (Volts)
Maximum Breakover Voltage VBO (Volts)
Minimum Holding Current IH (mA)
Data Sheet Page Number in Book
High Voltage Bidirectional Triggers: Sidacs
MT2
MT2
MT1
MT1
)
Breakover Voltage Range VBO (Volts) 110130 Surge Current ITSM (Amps) 60 Hz 4.0 Data Sheet Page Number in Book 607

DO41 Case 059A General Description 0.9 MKP1V120RL MKP1V130RL 120140 150170 220250 110130 220250 MKP1V160, RL MKP1V240, RL High voltage trigger devices similar in operation to triacs. Upon reaching the breakover voltage in either direction direction, the devices switch to a low voltage on state. 1.0 MKP3V120, RL MKP3V240, RL 20 611
OnState RMS Current IT(RMS) (Amps)
Surmetic 50 Case 267 Style 2
Thyristor Triggers: Programmable Unijunction Transistors (PUTs)
K G A
IP RG = 10K ohm ( Amps max.) 5.0 1.0 RG = 1M ohm ( Amps max.) 2.0 TO92(1) (TO226AA) Case 029 Style 16 2N6027 2N6028 RG = 10K ohm ( Amps min.) 70 25
IV RG = 1M ohm ( Amps max.) 50 25 Data Sheet Page Number in Book 265

General Description 0.15 Similar to unijunction transistors, except that IP, IV and intrinsic voltage are programmable IV, rogrammable (adjustable) by means of external voltage divider. UL logo indicates UL Recognized File #E116110 (1) See TO92 data sheets for complete device suffix packaging ordering options. RLRA, RLRE, RL, & RL1 suffixes: Radial Tape and Reel RLRM & ZL1 suffixes: Radial Tape and Ammo Pack Lead Identification: Suppressor/Sidac MT1 = Main Terminal 1 MT2 = Main Terminal 2 Lead Identification: PUT A = Anode K = Cathode G = Gate
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256
CHAPTER 3 Data Sheets
Page 2N5060 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 2N6027, 2N6028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 2N6071A/B Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 2N6344, 2N6349 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 2N6344A, 2N6348A, 2N6349A . . . . . . . . . . . . . . . . . . . . 283 2N6394 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 2N6400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 2N6504 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 C106 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 C122F1, C122B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 MAC08BT1, MAC08MT1 . . . . . . . . . . . . . . . . . . . . . . . . . 311 MAC4DCM, MAC4DCN . . . . . . . . . . . . . . . . . . . . . . . . . . 320 MAC4DHM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 MAC4DLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 MAC4DSM, MAC4DSN . . . . . . . . . . . . . . . . . . . . . . . . . . 340 MAC4M, MAC4N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 MAC4SM, MAC4SN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 MAC8D, MAC8M, MAC8N . . . . . . . . . . . . . . . . . . . . . . . . 358 MAC8SD, MAC8SM, MAC8SN . . . . . . . . . . . . . . . . . . . . 363 MAC9D, MAC9M, MAC9N . . . . . . . . . . . . . . . . . . . . . . . . 369 MAC12D, MAC12M, MAC12N . . . . . . . . . . . . . . . . . . . . 374 MAC12HCD, MAC12HCM, MAC12HCN . . . . . . . . . . . . 379 MAC12SM, MAC12SN . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 MAC15 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 MAC15A6FP, MAC15A8FP, MAC15A10FP . . . . . . . . . 394 MAC15M, MAC15N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 MAC15SD, MAC15SM, MAC15SN . . . . . . . . . . . . . . . . 404 MAC16CD, MAC16CM, MAC16CN . . . . . . . . . . . . . . . . 410 MAC16D, MAC16M, MAC16N . . . . . . . . . . . . . . . . . . . . 415 MAC16HCD, MAC16HCM, MAC16HCN . . . . . . . . . . . . 420 MAC97 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 MAC210A8, MAC210A10 . . . . . . . . . . . . . . . . . . . . . . . . . 433 MAC210A8FP, MAC210A10FP . . . . . . . . . . . . . . . . . . . . 438 MAC212A6FP, MAC212A8FP, MAC212A10FP . . . . . . 443 MAC212A8, MAC212A10 . . . . . . . . . . . . . . . . . . . . . . . . . 448 MAC218A6FP, MAC218A10FP . . . . . . . . . . . . . . . . . . . . 453 MAC223A6, MAC223A8, MAC223A10 . . . . . . . . . . . . . 457
Page MAC223A6FP, MAC223A8FP, MAC223A10FP . . . . . . 461 MAC224A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 MAC228A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 MAC229A8FP, MAC229A10FP . . . . . . . . . . . . . . . . . . . . 474 MAC320A8FP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 MAC997 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 MCR08B, MCR08M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 MCR8DCM, MCR8DCN . . . . . . . . . . . . . . . . . . . . . . . . . . 499 MCR8DSM, MCR8DSN . . . . . . . . . . . . . . . . . . . . . . . . . . 504 MCR8M, MCR8N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 MCR8SD, MCR8SM, MCR8SN . . . . . . . . . . . . . . . . . . . 514 MCR12D, MCR12M, MCR12N . . . . . . . . . . . . . . . . . . . . 518 MCR12DCM, MCR12DCN . . . . . . . . . . . . . . . . . . . . . . . . 522 MCR12DSM, MCR12DSN . . . . . . . . . . . . . . . . . . . . . . . . 528 MCR12LD, MCR12LM, MCR12LN . . . . . . . . . . . . . . . . . 534 MCR16N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 MCR226, MCR228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 MCR25D, MCR25M, MCR25N . . . . . . . . . . . . . . . . . . . . 550 MCR682 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 MCR692, MCR693 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 MCR723, MCR726, MCR728 . . . . . . . . . . . . . . . . . . 563 MCR100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 MCR1066, MCR1068 . . . . . . . . . . . . . . . . . . . . . . . . . . 572 MCR2182, MCR2184, MCR2186 . . . . . . . . . . . . . . . 575 MCR2186FP, MCR21810FP . . . . . . . . . . . . . . . . . . . . 579 MCR2258FP, MCR22510FP . . . . . . . . . . . . . . . . . . . . 584 MCR2644, MCR2646, MCR2648 . . . . . . . . . . . . . . . 589 MCR2654 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 MCR703A Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 MCR716, MCR718 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 MKP1V120 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 MKP3V120, MKP3V240 . . . . . . . . . . . . . . . . . . . . . . . . . . 611 MMT05B230T3, MMT05B260T3, MMT05B310T3 . . . . 615 MMT10B230T3, MMT10B260T3, MMT10B310T3 . . . . 621 T2322B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 T2500D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 T2800D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
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257
2N5060 Series Sensitive Gate Silicon Controlled Rectifiers

Reverse Blocking Thyristors
Annular PNPN devices designed for high volume consumer applications such as relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and sensing and detection circuits. Supplied in an inexpensive plastic TO-226AA (TO-92) package which is readily adaptable for use in automatic insertion equipment. Sensitive Gate Trigger Current 200 A Maximum Low Reverse and Forward Blocking Current 50 A Maximum, TC = 110C Low Holding Current 5 mA Maximum Passivated Surface for Reliability and Uniformity Device Marking: Device Type, e.g., 2N5060, Date Code
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) 2N5060 2N5061 2N5062 2N5064 Symbol VDRM, VRRM 30 60 100 200 IT(RMS) IT(AV) 0.51 0.255 ITSM 10 Amps 0.8 Amp Amp TO92 (TO226AA) CASE 029 STYLE 10 3 2 Value Unit Volts
Preferred Device
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SCRs 0.8 AMPERES RMS 30 thru 200 VOLTS
G A K
On-State Current RMS (180 Conduction Angles; TC = 80C) *Average On-State Current (180 Conduction Angles) (TC = 67C) (TC = 102C) *Peak Non-repetitive Surge Current, TA = 25C (1/2 cycle, Sine Wave, 60 Hz) Circuit Fusing Considerations (t = 8.3 ms) *Forward Peak Gate Power (Pulse Width 1.0 sec; TA = 25C)
PIN ASSIGNMENT
1 I2t PGM PG(AV) IGM VRGM TJ Tstg 0.4 0.1 0.01 1.0 5.0 40 to +110 40 to +150 A2s Watt Watt 2 3 Cathode Gate Anode
v v v
*Forward Average Gate Power (TA = 25C, t = 8.3 ms) *Forward Peak Gate Current (Pulse Width 1.0 sec; TA = 25C) *Reverse Peak Gate Voltage (Pulse Width 1.0 sec; TA = 25C) *Operating Junction Temperature Range *Storage Temperature Range *Indicates JEDEC Registered Data.
ORDERING INFORMATION
Amp Volts
Preferred devices are recommended choices for future use and best overall value. See detailed ordering and shipping information in the package dimensions section on page 264 of this data sheet.
C C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.
258
May, 2000 Rev. 3
Publication Order Number: 2N5060/D
2N5060 Series
THERMAL CHARACTERISTICS
Characteristic *Thermal Resistance, Junction to Case(1) Thermal Resistance, Junction to Ambient *Lead Solder Temperature (Lead Length 1/16 from case, 10 s Max) Symbol RJC RJA Max 75 200 +230* Unit C/W C/W C
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
*Peak Repetitive Forward or Reverse Blocking Current(2) (VAK = Rated VDRM or VRRM) TC = 25C TC = 110C IDRM, IRRM 10 50 A A
ON CHARACTERISTICS
*Peak Forward OnState Voltage(3) (ITM = 1.2 A peak @ TA = 25C) Gate Trigger Current (Continuous dc)(4) *(VAK = 7 Vdc, RL = 100 Ohms) Gate Trigger Voltage (Continuous dc)(4) *(VAK = 7 Vdc, RL = 100 Ohms) *Gate NonTrigger Voltage (VAK = Rated VDRM, RL = 100 Ohms) Holding Current (4) *(VAK = 7 Vdc, initiating current = 20 mA) Turn-On Time Delay Time Rise Time (IGT = 1 mA, VD = Rated VDRM, Forward Current = 1 A, di/dt = 6 A/s Turn-Off Time (Forward Current = 1 A pulse, Pulse Width = 50 s, 0.1% Duty Cycle, di/dt = 6 A/s, dv/dt = 20 V/s, IGT = 1 mA) TC = 25C TC = 40C TC = 25C TC = 40C TC = 110C TC = 25C TC = 40C VTM IGT VGT VGD 0.1 IH 3.0 0.2 5.0 10 mA s td tr 200 350 0.8 1.2 Volts Volts 1.7 Volts A
tq
2N5060, 2N5061 2N5062, 2N5064
10 30
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of OffState Voltage (Rated VDRM, Exponential) *Indicates JEDEC Registered Data. (1) This measurement is made with the case mounted flat side down on a heat sink and held in position by means of a metal clamp over the curved surface. (2) RGK = 1000 is included in measurement. (3) Forward current applied for 1 ms maximum duration, duty cycle 1%. (4) RGK current is not included in measurement. dv/dt 30 V/s
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259
2N5060 Series
Voltage Current Characteristic of SCR
+ Current Anode + VTM on state IRRM at VRRM IH
Symbol
VDRM IDRM VRRM IRRM VTM IH
Parameter
Peak Repetitive Off State Forward Voltage Peak Forward Blocking Current Peak Repetitive Off State Reverse Voltage Peak Reverse Blocking Current Peak on State Voltage Holding Current Reverse Blocking Region (off state) Reverse Avalanche Region Anode
+ Voltage IDRM at VDRM Forward Blocking Region (off state)
CURRENT DERATING
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (C)
130 120 110 100 dc 90 80 70 60 50 0 0.1 0.2 0.3 0.4 = 30 60 120 = CONDUCTION ANGLE
a TA , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( C)
130 = CONDUCTION ANGLE 110 TYPICAL PRINTED CIRCUIT BOARD MOUNTING
CASE MEASUREMENT POINT CENTER OF FLAT PORTION
90
90
180
70
dc
50 = 30 30 0 0.1 60 0.2 90 120 0.3 180 0.4
0.5
IT(AV), AVERAGE ON-STATE CURRENT (AMP)
Figure 1. Maximum Case Temperature
Figure 2. Maximum Ambient Temperature
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260
2N5060 Series
CURRENT DERATING
5.0 ITSM , PEAK SURGE CURRENT (AMP)
10 7.0 5.0
3.0 2.0 TJ = 110C 25C 1.0 0.7 0.5
3.0 2.0
i T , INSTANTANEOUS ON-STATE CURRENT (AMP)
1.0 1.0 0.3 0.2
2.0
3.0
5.0 7.0
10
20
30
50 70
100
NUMBER OF CYCLES
Figure 4. Maximum NonRepetitive Surge Current
0.8 P(AV), MAXIMUM AVERAGE POWER DISSIPATION (WATTS) 0.1 0.07 0.05 120 0.6 a = CONDUCTION ANGLE = 30 60 90
180
0.03 0.02
0.4 dc 0.2
0.01 0 0.5 1.0 1.5 2.0 2.5 vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
0 0 0.1 0.2 0.3 0.4 0.5 IT(AV), AVERAGE ON-STATE CURRENT (AMP)
Figure 3. Typical Forward Voltage

r(t), TRANSIENT THERMAL RESISTANCE NORMALIZED
Figure 5. Power Dissipation
1.0 0.5
0.2 0.1 0.05
0.02 0.01 0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1.0
2.0
5.0
10
20
t, TIME (SECONDS)
Figure 6. Thermal Response
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261
2N5060 Series
TYPICAL CHARACTERISTICS
0.8 VG , GATE TRIGGER VOLTAGE (VOLTS) VAK = 7.0 V RL = 100 RGK = 1.0 k
I GT , GATE TRIGGER CURRENT (NORMALIZED)
200 100 50 2N5062-64 20 10 5.0 2N5060-61 2.0 1.0 0.5 0.2 75 50 25 0 25 50 75 100 110 TJ, JUNCTION TEMPERATURE (C) VAK = 7.0 V RL = 100
0.7
0.6
0.5
0.4 0.3 75
50
25
25
50
75
100 110
Figure 7. Typical Gate Trigger Voltage
Figure 8. Typical Gate Trigger Current
4.0 I H , HOLDING CURRENT (NORMALIZED) 3.0 2.0 VAK = 7.0 V RL = 100 RGK = 1.0 k
1.0 0.8
2N5060,61 2N5062-64
0.6 0.4 75
50
25
25
50
75
100 110
Figure 9. Typical Holding Current
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262
2N5060 Series TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A H2B H2B
H W2 H4 H5 L1 L F1 F2 P2 P1 P P2 D H1 W1 W T T2 T1
Figure 10. Device Positioning on Tape

Specification Inches Symbol
D D2 F1, F2 H H1 H2A H2B H4 H5 L L1 P P1 P2 T T1 T2 W W1 W2
Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Item Tape Feedhole Diameter Component Lead Thickness Dimension Component Lead Pitch Bottom of Component to Seating Plane Feedhole Location Deflection Left or Right Deflection Front or Rear Feedhole to Bottom of Component Feedhole to Seating Plane Defective Unit Clipped Dimension Lead Wire Enclosure Feedhole Pitch Feedhole Center to Center Lead First Lead Spacing Dimension Adhesive Tape Thickness Overall Taped Package Thickness Carrier Strip Thickness Carrier Strip Width Adhesive Tape Width Adhesive Tape Position
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
NOTES: 1. Maximum alignment deviation between leads not to be greater than 0.2 mm. 2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm. 3. Component lead to tape adhesion must meet the pull test requirements. 4. Maximum noncumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches. 5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive. 6. No more than 1 consecutive missing component is permitted. 7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component. 8. Splices will not interfere with the sprocket feed holes.
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263
2N5060 Series
ORDERING & SHIPPING INFORMATION: 2N5060 Series packaging options, Device Suffix
U.S. 2N5060,61,62,64 2N5060,61,62,64RLRA 2N5060,64RLRM Europe Equivalent Shipping Bulk in Box (5K/Box) Radial Tape and Reel (2K/Reel) Radial Tape and Fan Fold Box (2K/Box) Description of TO92 Tape Orientation N/A, Bulk Round side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible
2N5060RL1
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264
2N6027, 2N6028
Preferred Device
Programmable Unijunction Transistor
Programmable Unijunction Transistor Triggers

Designed to enable the engineer to program unijunction characteristics such as RBB, , IV, and IP by merely selecting two resistor values. Application includes thyristortrigger, oscillator, pulse and timing circuits. These devices may also be used in special thyristor applications due to the availability of an anode gate. Supplied in an inexpensive TO92 plastic package for highvolume requirements, this package is readily adaptable for use in automatic insertion equipment. Programmable RBB, , IV and IP Low OnState Voltage 1.5 Volts Maximum @ IF = 50 mA Low Gate to Anode Leakage Current 10 nA Maximum High Peak Output Voltage 11 Volts Typical Low Offset Voltage 0.35 Volt Typical (RG = 10 k ohms) Device Marking: Logo, Device Type, e.g., 2N6027, Date Code
Rating *Power Dissipation Derate Above 25C *DC Forward Anode Current Derate Above 25C *DC Gate Current Repetitive Peak Forward Current 100 s Pulse Width, 1% Duty Cycle *20 s Pulse Width, 1% Duty Cycle NonRepetitive Peak Forward Current 10 s Pulse Width *Gate to Cathode Forward Voltage *Gate to Cathode Reverse Voltage *Gate to Anode Reverse Voltage *Anode to Cathode Voltage(1) Operating Junction Temperature Range *Storage Temperature Range *Indicates JEDEC Registered Data (1) Anode positive, RGA = 1000 ohms Anode negative, RGA = open Symbol PF 1/JA IT IG ITRM 1.0 2.0 ITSM VGKF VGKR VGAR VAK TJ Tstg 5.0 40 Amps Volts Volts Volts Volts C C Value 300 4.0 150 2.67 Unit mW mW/C mA mA/C mA Amps 1 2 3 3 2
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PUTs 40 VOLTS 300 mW
G A K
"50
TO92 (TO226AA) CASE 029 STYLE 16
PIN ASSIGNMENT
Anode Gate Cathode
*5.0 "40
50 to +100 55 to +150 40
See detailed ordering and shipping information in the package dimensions section on page 271 of this data sheet. Preferred devices are recommended choices for future use and best overall value.
265
March, 2000 Rev. 1
2N6027, 2N6028
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes ( 1/16 from case, 10 secs max) Symbol RJC RJA TL Max 75 200 260 Unit C/W C/W C
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted.)

Characteristic *Peak Current (VS = 10 Vdc, RG = 1 M) (VS = 10 Vdc, RG = 10 k ohms) *Offset Voltage (VS = 10 Vdc, RG = 1 M) (VS = 10 Vdc, RG = 10 k ohms) *Valley Current (VS = 10 Vdc, RG = 1 M) (VS = 10 Vdc, RG = 10 k ohms) (VS = 10 Vdc, RG = 200 ohms) *Gate to Anode Leakage Current (VS = 40 Vdc, TA = 25C, Cathode Open) (VS = 40 Vdc, TA = 75C, Cathode Open) Gate to Cathode Leakage Current (VS = 40 Vdc, Anode to Cathode Shorted) *Forward Voltage (IF = 50 mA Peak)(1) *Peak Output Voltage (VG = 20 Vdc, CC = 0.2 F) Pulse Voltage Rise Time (VB = 20 Vdc, CC = 0.2 F) *Indicates JEDEC Registered Data (1) Pulse Test: Pulse Width 300 sec, Duty Cycle 2%. 2N6027 2N6028 2N6027 2N6028 1 2N6027 2N6028 (Both Types) 1,4,5 2N6027 2N6028 2N6027 2N6028 2N6027 2N6028 IGAO 1,6 3,7 3 IGKS VF Vo tr 6.0 1.0 3.0 5.0 0.8 11 40 10 50 1.5 80 nAdc Volts Volt ns IV 70 25 1.5 1.0 18 18 150 150 50 25 VT 0.2 0.2 0.2 0.70 0.50 0.35 1.6 0.6 0.6 A Fig. No. 2,9,11 Symbol IP 1.25 0.08 4.0 0.70 2.0 0.15 5.0 1.0 Volts Min Typ Max Unit A
mA nAdc
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266
2N6027, 2N6028
IA +VB A G VAK K R2 VS = R1 R1 V R1 + R2 B IA + VAK RG = R1 R2 R1 + R2 RG VS VF VV 1A Programmable Unijunction with Program Resistors R1 and R2 1B Equivalent Test Circuit for Figure 1A used for electrical characteristics testing (also see Figure 2) IGAO IP IV IF VA VS VP VT = VP VS
IA
IC Electrical Characteristics
Figure 1. Electrical Characterization
Adjust for Turnon Threshold VB
100k 1.0%
IP (SENSE) 100 V = 1.0 nA + 2N5270 0.01 F R RG = R/2 VS = VB/2 (See Figure 1) R CC
+VB +V 510k 16k Vo 6V
vo 20
27k 0.6 V tf t
Scope 20 Put Under Test
Figure 2. Peak Current (IP) Test Circuit
Figure 3. Vo and tr Test Circuit
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267
2N6027, 2N6028
TYPICAL VALLEY CURRENT BEHAVIOR
1000 IV, VALLEY CURRENT ( A) IV, VALLEY CURRENT ( A) 500
RG = 10 k
100
RG = 10 k
100
100 k 1 M
100 k 10 1 M
10
10
15
20
5 50
25
+25
+50
+75
+100
VS, SUPPLY VOLTAGE (VOLTS)
TA, AMBIENT TEMPERATURE (C)
Figure 4. Effect of Supply Voltage
Figure 5. Effect of Temperature
10 V F, PEAK FORWARD VOLTAGE (VOLTS) Vo, PEAK OUTPUT VOLTAGE (VOLTS) 5.0 2.0 1.0 0.5 0.2 0.1 0.05 0.02 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 TA = 25C
25 TA = 25C (SEE FIGURE 3) 20
CC = 0.2 F
15
10 1000 pF 5.0
0 0
5.0
10
15
20
25
30
35
40
IF, PEAK FORWARD CURRENT (AMP)
Figure 6. Forward Voltage
Figure 7. Peak Output Voltage
A G
A P N P N K G
B2 R2 RBB = R1 + R2 R1 = R1 + R2 R1 RT A G R1 K B1 R2
CC
K Circuit Symbol
Equivalent Circuit with External Program Resistors R1 and R2
Typical Application
Figure 8. Programmable Unijunction
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268
2N6027, 2N6028
TYPICAL PEAK CURRENT BEHAVIOR 2N6027
10 IP, PEAK CURRENT ( A) 5.0 3.0 2.0 1.0 0.5 0.3 0.2 0.1 5.0 RG = 10 k 100 k 1.0 M TA = 25C (SEE FIGURE 2) 100 50 IP, PEAK CURRENT ( A) 20 10 5.0 2.0 1.0 0.5 0.2 10 15 20 0.1 50 25 RG = 10 k 100 k 1.0 M 0 +25 +50 +75 +100 VS = 10 VOLTS (SEE FIGURE 2)
Figure 9. Effect of Supply Voltage and RG
Figure 10. Effect of Temperature and RG
2N6028
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 5.0 10 5.0 IP, PEAK CURRENT ( A) RG = 10 k 100 k 2.0 1.0 0.5 0.2 0.1 0.05 0.02 10 15 20 0.01 50 25 100 k 1.0 M 0 +25 +50 +75 +100 RG = 10 k VS = 10 VOLTS (SEE FIGURE 2)
IP, PEAK CURRENT ( A)
1.0 M TA = 25C (SEE FIGURE 2)
Figure 11. Effect of Supply Voltage and RG
Figure 12. Effect of Temperature and RG
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269
2N6027, 2N6028 TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A H2B H2B

Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
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270
2N6027, 2N6028
ORDERING & SHIPPING INFORMATION: 2N6027 and 2N6028 packaging options, Device Suffix
U.S. 2N6027, 2N6028 2N6027, 2N6028RLRA 2N6027RL1 2N6028RLRM 2N6028RLRP Europe Equivalent Shipping Bulk in Box (5K/Box) Radial Tape and Reel (2K/Reel) Radial Tape and Reel (2K/Reel) Radial Tape and Fan Fold Box (2K/Box) Radial Tape and Fan Fold Box (2K/Box) Description of TO92 Tape Orientation N/A, Bulk Round side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible Round side of TO92 and adhesive tape visible
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271
2N6071A/B Series
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied anode voltage with positive or negative gate triggering. Sensitive Gate Triggering Uniquely Compatible for Direct Coupling to TTL, HTL, CMOS and Operational Amplifier Integrated Circuit Logic Functions Gate Triggering 4 Mode 2N6071A,B, 2N6073A,B, 2N6075A,B Blocking Voltages to 600 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat Dissipation and Durability Device Marking: Device Type, e.g., 2N6071A, Date Code
Rating *Peak Repetitive Off-State Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) 2N6071A,B 2N6073A,B 2N6075A,B Symbol VDRM, VRRM 200 400 600 IT(RMS) ITSM I2t PGM PG(AV) VGM TJ Tstg 4.0 30 3.7 10 0.5 5.0 40 to +110 40 to +150 8.0 Amps Amps A2s Watts Watt Volts 1 2 3 Value Unit Volts
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TRIACS 4 AMPERES RMS 200 thru 600 VOLTS
MT2 G
MT1
*On-State RMS Current (TC = 85C) Full Cycle Sine Wave 50 to 60 Hz *Peak Nonrepetitive Surge Current (One Full cycle, 60 Hz, TJ = +110C) Circuit Fusing Considerations (t = 8.3 ms) *Peak Gate Power (Pulse Width 1.0 s, TC = 85C) *Average Gate Power (t = 8.3 ms, TC = 85C) *Peak Gate Voltage (Pulse Width 1.0 s, TC = 85C) *Operating Junction Temperature Range *Storage Temperature Range Mounting Torque (6-32 Screw)(2) *Indicates JEDEC Registered Data.
2 1
TO225AA (formerly TO126) CASE 077 STYLE 5
PIN ASSIGNMENT
Main Terminal 1 Main Terminal 2 Gate
C C in. lb. Device 2N6071A 2N6071B 2N6073A 2N6073B 2N6075A 2N6075B Package TO225AA TO225AA TO225AA TO225AA TO225AA TO225AA Shipping 500/Box 500/Box 500/Box 500/Box 500/Box 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) Torque rating applies with use of a compression washer. Mounting torque in excess of 6 in. lb. does not appreciably lower case-to-sink thermal resistance. Main terminal 2 and heatsink contact pad are common.
Preferred devices are recommended choices for future use and best overall value.
272
May, 2000 Rev. 3
2N6071A/B Series
Characteristic *Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Max 3.5 75 260 Unit C/W C/W C
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted; Electricals apply in both directions)
OFF CHARACTERISTICS
*Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 110C IDRM, IRRM 10 2 A mA
ON CHARACTERISTICS
*Peak On-State Voltage(1) (ITM = 6 A Peak)
"
VTM VGT
Volts Volts
*Gate Trigger Voltage (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms, TJ = 40C) All Quadrants Gate NonTrigger Voltage (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms, TJ = 110C) All Quadrants *Holding Current (Main Terminal Voltage = 12 Vdc, Gate Open, Initiating Current = 1 Adc)
VGD 0.2 IH
1.4
2.5 Volts
mA
"
(TJ = 40C) (TJ = 25C) tgt
1.5
30 15 s
Turn-On Time (ITM = 14 Adc, IGT = 100 mAdc)
QUADRANT (Maximum Value) Type Gate Trigger Current (Continuous dc) (Main Terminal Voltage = 12 Vdc Vdc, RL = 100 ohms) 2N6071A 2N6073A 2N6075A 2N6071B 2N6073B 2N6075B IGT @ TJ +25C 40C +25C 40C I mA 5 20 3 15 II mA 5 20 3 15 III mA 5 20 3 15 IV mA 10 30 5 20
Critical Rate of Rise of Commutation Voltage @ VDRM, TJ = 85C, Gate Open, ITM = 5.7 A, Exponential Waveform, Commutating di/dt = 2.0 A/ms *Indicates JEDEC Registered Data. (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt(c) 5 V/s
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273
2N6071A/B Series
SAMPLE APPLICATION: TTL-SENSITIVE GATE 4 AMPERE TRIAC TRIGGERS IN MODES II AND III
14 MC7400 4 7 VEE = 5.0 V + 2N6071A LOAD 115 VAC 60 Hz
0V
VEE
510
Trigger devices are recommended for gating on Triacs. They provide: 1. Consistent predictable turn-on points. 2. Simplified circuitry. 3. Fast turn-on time for cooler, more efficient and reliable operation.
Voltage Current Characteristic of Triacs (Bidirectional Device)

+ Current Quadrant 1 MainTerminal 2 +
Symbol
Parameter
Peak Repetitive Forward Off State Voltage Peak Forward Blocking Current Peak Repetitive Reverse Off State Voltage Peak Reverse Blocking Current Maximum On State Voltage Holding Current IH Quadrant 3 VTM MainTerminal 2 IRRM at VRRM on state
VTM IH
off state
+ Voltage IDRM at VDRM
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274
2N6071A/B Series
Quadrant Definitions for a Triac
MT2 POSITIVE (Positive Half Cycle) +
(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
(+) IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
MT2 NEGATIVE (Negative Half Cycle) All polarities are referenced to MT1. With inphase signals (using standard AC lines) quadrants I and III are used.
SENSITIVE GATE LOGIC REFERENCE

IC Logic g Functions TTL Firing Quadrant I II 2N6071A Series 2N6071A Series 2N6071B Series 2N6071B Series 2N6071A Series 2N6071A Series 2N6071A Series 2N6071B Series 2N6071A Series III 2N6071A Series 2N6071A Series 2N6071B Series IV
HTL
CMOS (NAND)
CMOS (Buffer)
Operational Amplifier Zero Voltage Switch
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275
2N6071A/B Series
110 110 = 30
60 90
TC , CASE TEMPERATURE ( C)
100 = 30 90 60
100
90
120
90
120 180
180
dc
80 70
80 a 70
dc
= CONDUCTION ANGLE 0 1.0 2.0 3.0 IT(AV), AVERAGE ON-STATE CURRENT (AMP) 4.0
= CONDUCTION ANGLE 0 1.0 2.0 3.0 IT(RMS), RMS ON-STATE CURRENT (AMP) 4.0
Figure 1. Average Current Derating

8.0 a P(AV) , AVERAGE POWER (WATTS) 6.0 a = CONDUCTION ANGLE 60 4.0 = 30 90 180 120 dc P(AV) , AVERAGE POWER (WATTS) 6.0 a 8.0
Figure 2. RMS Current Derating
dc = 180 120
= CONDUCTION ANGLE 4.0
2.0
2.0 90 0
60
30
0 0 2.0 3.0 IT(AV), AVERAGE ON-STATE CURRENT (AMP) 1.0 4.0
1.0 2.0 3.0 IT(RMS), RMS ON-STATE CURRENT (AMP)
4.0

V GT , GATE TRIGGER VOLTAGE (NORMALIZED) I GT , GATE TRIGGER CURRENT (NORMALIZED) 3.0 2.0 OFF-STATE VOLTAGE = 12 Vdc ALL MODES 3.0 2.0
OFF-STATE VOLTAGE = 12 Vdc ALL MODES
1.0 0.7 0.5
1.0 0.7 0.5
0.3 60
40
20
0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C)
120
140
0.3 60
40
20
120
140
Figure 5. Typical GateTrigger Voltage
Figure 6. Typical GateTrigger Current
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276
2N6071A/B Series
40 30 20 IH, HOLDING CURRENT (NORMALIZED) 3.0 2.0 GATE OPEN APPLIES TO EITHER DIRECTION
1.0 0.7 0.5
10 7.0 ITM , ON-STATE CURRENT (AMP) 5.0 TJ = 110C
0.3 60
40
20
20
40
60
80
100
120
140
3.0 2.0

TJ = 25C
1.0 PEAK SINE WAVE CURRENT (AMP) 0.7 0.5
34 32 30 28 26 24 22 20 18 16 14 1.0 TJ = 40 to +110C f = 60 Hz
0.3 0.2
0.1 0 1.0 2.0 3.0 4.0 5.0 VTM, ON-STATE VOLTAGE (VOLTS)
2.0
3.0
4.0
5.0
7.0
10
NUMBER OF FULL CYCLES
Figure 7. Maximum OnState Characteristics

Z JC(t), TRANSIENT THERMAL IMPEDANCE (C/W) 10 5.0 3.0 2.0
Figure 9. Maximum Allowable Surge Current
MAXIMUM
TYPICAL 1.0 0.5 0.3 0.2 0.1 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 t, TIME (ms) 100 200 500 1.0 k 2.0 k 5.0 k 10 k
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277
2N6344, 2N6349
Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever fullwave silicon gate controlled solidstate devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied main terminal voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in all Four Quadrants For 400 Hz Operation, Consult Factory Device Marking: Logo, Device Type, e.g., 2N6344, Date Code
Rating * Peak Repetitive OffState Voltage(1) (TJ = 40 to +110C, Sine Wave 50 to 60 Hz, Gate Open) 2N6344 2N6349 *OnState RMS Current (TC = +80C) Full Cycle Sine Wave 50 to 60 Hz (TC = +90C) *Peak NonRepetitive Surge Current (One Full Cycle, Sine Wave 60 Hz, TC = +25C) Preceded and followed by rated current Circuit Fusing Consideration (t = 8.3 ms) *Peak Gate Power (TC = +80C, Pulse Width = 2 s) *Average Gate Power (TC = +80C, t = 8.3 ms) *Peak Gate Current (TC = +80C, Pulse Width = 2.0 s) *Peak Gate Voltage (TC = +80C, Pulse Width = 2.0 s) *Operating Junction Temperature Range *Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 8.0 4.0 ITSM 100 Amps Amps Value Unit Volts 1
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MT2 G MT1
TO220AB CASE 221A STYLE 4
PIN ASSIGNMENT
1 I2t PGM PG(AV) IGM VGM TJ Tstg 40 20 0.5 2.0 10 40 to +125 40 to +150 A2s Watts Watt 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Amps Volts C C
Device 2N6344 2N6349
Package TO220AB TO220AB
Shipping 500/Box 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.
278
March, 2000 Rev. 1
2N6344, 2N6349
Characteristic *Thermal Resistance, Junction to Case Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC TL Max 2.2 260 Unit C/W C
OFF CHARACTERISTICS
* Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 100C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
* Peak OnState Voltage (ITM = 11 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle
"
p2%)
VTM IGT
1.3
1.55
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) *MT2(+), G(+); MT2(), G() TC = 40C *MT2(+), G(); MT2(), G(+) TC = 40C Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) *MT2(+), G(+); MT2(), G() TC = 40C *MT2(+), G(); MT2(), G(+) TC = 40C Gate NonTrigger Voltage (Continuous dc) (VD = Rated VDRM, RL = 10 k Ohms, TJ = 100C) *MT2(+), G(+); MT2(), G(); MT2(+), G(); MT2(), G() * Holding Current (VD = 12 Vdc, Gate Open) (Initiating Current = 200 mA)
VGT VGD 0.2 TC = 25C *TC = 40C IH tgt
12 12 20 35
50 75 50 75 100 125 Volts
0.9 0.9 1.1 1.4
2.0 2.5 2.0 2.5 2.5 3.0 Volts
6.0 1.5
mA 40 75 2.0 s
"
* Turn-On Time (VD = Rated VDRM, ITM = 11 A, IGT = 120 mA, Rise Time = 0.1 s, Pulse Width = 2 s)
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 11 A, Commutating di/dt = 4.0 A/ms, Gate Unenergized, TC = 80C) *Indicates JEDEC Registered Data. dv/dt(c) 5.0 V/s
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279
2N6344, 2N6349
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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280
2N6344, 2N6349
100 60 90 92 84 80 = CONDUCTION ANGLE dc 120 180 88 PAV , AVERAGE POWER (WATTS) = 30 TC , CASE TEMPERATURE ( C) 96 10 8.0 = CONDUCTION ANGLE 60 TJ 100C 30 90 dc = 180 120
6.0
4.0
2.0
0 0 1.0 3.0 4.0 5.0 6.0 IT(RMS), RMS ON-STATE CURRENT, (AMP) 2.0 7.0 8.0
1.0
5.0 2.0 3.0 4.0 6.0 IT(RMS), RMS ON-STATE CURRENT (AMP)
7.0
8.0
Figure 2. OnState Power Dissipation
1.8 Vgt , GATE TRIGGER VOLTAGE (VOLTS) 1.6 1.4 QUADRANT 4 1.2 1.0 0.8 0.6 0.4 60 40 20 1 QUADRANTS 2 3 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140 I GT , GATE TRIGGER CURRENT (mA) OFF-STATE VOLTAGE = 12 V
50 OFF-STATE VOLTAGE = 12 V 30 20
10 7.0
QUADRANT
1 2 3 4
5.0 60
40
20
120 140
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281
2N6344, 2N6349
100 I H , HOLDING CURRENT (mA) 70 50 30 20 i TM , INSTANTANEOUS ON-STATE CURRENT (AMP) TJ = 100C 10 7.0 5.0 3.0 2.0 100 1.0 0.7 0.5 0.3 0.2 I TSM , PEAK SURGE CURRENT (AMP) 80 25C 20 GATE OPEN MAIN TERMINAL #1 POSITIVE
10 7.0 5.0 MAIN TERMINAL #2 POSITIVE 3.0 2.0 60
40
20
120
140
60 CYCLE TJ = 100C f = 60 Hz Surge is preceded and followed by rated current 1.0 2.0 3.0 5.0 NUMBER OF CYCLES 7.0 10
40
20 0
0.1 0.4
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
4.4
Figure 5. OnState Characteristics
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
1.0 0.5
0.2 0.1 0.05
ZJC(t) = r(t) RJC
0.02 0.01 0.1
0.2
0.5
1.0
2.0
5.0
20 50 t,TIME (ms)
100
200
500
1.0 k
2.0 k
5.0 k
10 k
Figure 8. Typical Thermal Response
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282
2N6344A, 2N6348A, 2N6349A

Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied anode voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in all Four Quadrants For 400 Hz Operation, Consult Factory 8 Ampere Devices Available as 2N6344 thru 2N6349 Device Marking: Logo, Device Type, e.g., 2N6344A, Date Code
Rating *Peak Repetitive OffState Voltage(1) (Gate Open, TJ = 40 to +110C, Sine Wave 50 to 60 Hz, Gate Open) 2N6344A, 2N6348A 2N6349A *OnState RMS Current (Full Cycle Sine Wave 50 to 60 Hz) (TC = +80C) (TC = +95C) *Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +80C) Preceded and followed by rated current Circuit Fusing Consideration (t = 8.3 ms) *Peak Gate Power (TC = +80C, Pulse Width = 2.0 s) *Average Gate Power (TC = +80C, t = 8.3 ms) *Peak Gate Current (Pulse Width = 2.0 s; TC = +80C) *Peak Gate Voltage (Pulse Width = 2.0 s; TC = +80C) *Operating Junction Temperature Range *Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 12 6.0 ITSM 100 A 1 I2t PGM PG(AV) IGM VGM TJ Tstg 59 20 0.5 2.0 A2s Watts Watt A Volts C C 2 3 4 A Value Unit Volts 1
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MT2 G MT1
PIN ASSIGNMENT
Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Device 2N6344A 2N6348A 2N6349A Package TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box
"10
40 to +125 40 to +150
*Indicates JEDEC Registered Data. (1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.
283
February, 2000 Rev. 1
Publication Order Number: 2N6344A/D
2N6344A, 2N6348A, 2N6349A

Characteristic *Thermal Resistance, Junction to Case Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC TL Max 2.0 260 Unit C/W C
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted; Electricals apply in either direction)
OFF CHARACTERISTICS
*Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 110C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
*Peak On-State Voltage (ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle
"
p 2%)
VTM IGT
1.3
1.75
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) *MT2(+), G(+); MT2(), G() TC = 40C *MT2(+), G(); MT2(), G(+) TC = 40C Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) *MT2(+), G(+); MT2(), G() TC = 40C *MT2(+), G(); MT2(), G(+) TC = 40C Gate NonTrigger Voltage (VD = Rated VDRM, RL = 10 k ohms, TJ = 110C) *MT2(+), G(+); MT2(), G(); MT2(+), G(); MT2(), G(+) Holding Current (VD = 12 Vdc, Gate Open) Initiating Current = 200 mA
VGT VGD 0.2 TC = 25C *TC = 40C IH tgt
6.0 6.0 10 25
50 75 50 75 100 125 Volts
0.9 0.9 1.1 1.4
2.0 2.5 2.0 2.5 2.5 3.0 Volts
6.0 1.5
mA 40 75 2.0 s
"
*Turn-On Time (VD = Rated VDRM, ITM = 17 A, IGT = 120 mA, Rise Time = 0.1 s, Pulse Width = 2 s)
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms, Gate Unenergized, TC = 80C) *Indicates JEDEC Registered Data. dv/dt(c) 5.0 V/s
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284
2N6344A, 2N6348A, 2N6349A

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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285
2N6344A, 2N6348A, 2N6349A

110 TC , CASE TEMPERATURE ( C) 30 60 100 90 120 90 80 = CONDUCTION ANGLE 70 0 2.0 dc 0 4.0 6.0 8.0 10 12 IT(RMS), RMS ON-STATE CURRENT, (AMP) 14 0 2.0 4.0 6.0 8.0 10 12 IT(RMS), RMS ON-STATE CURRENT (AMP) 14 180 PAV , AVERAGE POWER (WATTS) 20 12 = CONDUCTION ANGLE TJ = 110C 90 180 120 60 = 30 dc
16
8.0
4.0
1.8 Vgt , GATE TRIGGER VOLTAGE (VOLTS) 1.6 1.4 QUADRANT 4 1.2 1.0 0.8 0.6 0.4 60 40 20 1 QUADRANTS 2 3 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140 I GT , GATE TRIGGER CURRENT (mA) VD = 12 V
50 VD = 12 V 30 20
10 7.0
QUADRANT
1 2 3 4
5.0 60
40
20
120 140
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286
2N6344A, 2N6348A, 2N6349A

100 70 50 30 20 i TM , INSTANTANEOUS ON-STATE CURRENT (AMP) TJ = 100C 10 7.0 5.0 3.0 2.0 100 1.0 0.7 0.5 0.3 0.2 I TSM , PEAK SURGE CURRENT (AMP) 80 25C I H , HOLDING CURRENT (mA) 10 7.0 5.0 MAIN TERMINAL #2 POSITIVE 3.0 2.0 60 20 GATE OPEN MAIN TERMINAL #1 POSITIVE
40
20
120
140
60 CYCLE TJ = 100C f = 60 Hz Surge is preceded and followed by rated current 1.0 2.0 3.0 5.0 NUMBER OF CYCLES 7.0 10
40
20 0
0.1 0.4
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 vTM, MAXIMUM INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
1.0 0.5
0.2 0.1 0.05
ZJC(t) = r(t) RJC
0.02 0.01 0.1
0.2
0.5
1.0
2.0
5.0
20 50 t,TIME (ms)
100
200
500
1.0 k
2.0 k
5.0 k
10 k
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287
2N6394 Series Silicon Controlled Rectifiers

Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supplies. Glass Passivated Junctions with Center Gate Geometry for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 800 Volts Device Marking: Logo, Device Type, e.g., 2N6394, Date Code
*MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) 2N6394 2N6395 2N6397 2N6399 On-State RMS Current (180 Conduction Angles; TC = 90C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 90C) Forward Average Gate Power (t = 8.3 ms, TC = 90C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 90C) Operating Junction Temperature Range Storage Temperature Range *Indicates JEDEC Registered Data (1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. Symbol VDRM, VRRM 50 100 400 800 IT(RMS) ITSM 12 100 A A 1 Value Unit Volts
Preferred Device
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SCRs 12 AMPERES RMS 50 thru 800 VOLTS

G A K
I2t PGM PG(AV) IGM TJ Tstg
40 20 0.5 2.0 40 to +125 40 to +150
A2s Watts Watts 1 A C C 2 3 4
PIN ASSIGNMENT
Cathode Anode Gate Anode
Device 2N6394 2N6395 2N6397 2N6399 Package TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box
288
2N6394 Series
Characteristic Thermal Resistance, Junction to Case Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC TL Max 2.0 260 Unit C/W C

OFF CHARACTERISTICS
* Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
* Peak Forward OnState Voltage(1) (ITM = 24 A Peak) * Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) * Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) Gate NonTrigger Voltage (VD = 12 Vdc, RL = 100 Ohms, TJ = 125C) * Holding Current (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (ITM = 12 A, IGT = 40 mAdc, VD = Rated VDRM) Turn-Off Time (VD = Rated VDRM) (ITM = 12 A, IR = 12 A) (ITM = 12 A, IR = 12 A, TJ = 125C) VTM IGT VGT VGD IH tgt tq 15 35 0.2 1.7 5.0 0.7 6.0 1.0 2.2 30 1.5 50 2.0 Volts mA Volts Volts mA s s
Critical RateofRise of Off-State Voltage Exponential (VD = Rated VDRM, TJ = 125C) *Indicates JEDEC Registered Data (1) Pulse Test: Pulse Width 300 sec, Duty Cycle 2%. dv/dt 50 V/s
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289
2N6394 Series
Symbol
Parameter
Peak Repetitive Off State Forward Voltage Peak Forward Blocking Current Peak Repetitive Off State Reverse Voltage Peak Reverse Blocking Current Peak On State Voltage Holding Current Reverse Blocking Region (off state) Reverse Avalanche Region Anode
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
130 P(AV) , AVERAGE POWER (WATTS) 125 120 115 110 105 dc 100 95 90 0 = 30 60 90 180 8.0 = CONDUCTION ANGLE
20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 7.0 4.0 5.0 6.0 IT(AV), AVERAGE ON-STATE CURRENT (AMPS) 8.0 TJ 125C = CONDUCTION ANGLE = 30 60 180 90 dc
7.0 6.0 1.0 2.0 3.0 4.0 5.0 IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)
Figure 1. Current Derating
Figure 2. Maximum OnState Power Dissipation
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290
2N6394 Series
100 70 50 30 20 i TM , INSTANTANEOUS ONSTATE CURRENT (AMPS) TJ = 25C 125C
10 7.0 5.0 3.0 2.0 100 I TSM , PEAK SURGE CURRENT (AMP) 95 90 85 80 75 70 65 60 55 50 1.0 SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 2.0 3.0 4.0 6.0 8.0 10 TJ = 125C f = 60 Hz 1 CYCLE
1.0 0.7 0.5 0.3 0.2
0.1 0.4 1.2 2.0 2.8 3.6 4.4 5.2 vTH, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) 6.0
NUMBER OF CYCLES
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 50 20 30 t, TIME (ms) 100 200 300 500 1.0 k 2.0 k 3.0 k 5.0 k 10 k ZJC(t) = RJC r(t)
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291
2N6394 Series
I GT, GATE TRIGGER CURRENT (NORMALIZED) 300 200 IGTM , PEAK GATE CURRENT (mA) 100 70 50 30 20 10 7.0 5.0 3.0 0.2 0.5 1.0 2.0 5.0 10 20 PULSE WIDTH (ms) 50 100 200 TJ = 40C 25C 100C 3.0 OFF-STATE VOLTAGE = 12 V 2.0
OFF-STATE VOLTAGE = 12 V
1.0 0.7 0.5
0.3 40 20
140
160
Figure 6. Typical Gate Trigger Current versus Pulse Width
Figure 7. Typical Gate Trigger Current versus Temperature
1.1 VGT, GATE TRIGGER VOLTAGE (VOLTS) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 60 40 OFF-STATE VOLTAGE = 12 V IH , HOLDING CURRENT (mA)
30 OFF-STATE VOLTAGE = 12 V 20
10 7.0 5.0
3.0 20 0 20 40 60 80 100 120 140 60 40 20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
Figure 8. Typical Gate Trigger Voltage versus Temperature
Figure 9. Typical Holding Current versus Temperature
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292

Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supplies; or wherever halfwave silicon gatecontrolled, solidstate devices are needed. Glass Passivated Junctions with Center Gate Geometry for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 800 Volts Device Marking: Logo, Device Type, e.g., 2N6400, Date Code
*MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave 50 to 60 Hz; Gate Open) 2N6400 2N6401 2N6402 2N6403 2N6404 2N6405 Symbol VDRM, VRRM 50 100 200 400 600 800 IT(RMS) IT(AV) ITSM 16 10 160 A A A 1 2 3 Value Unit Volts 4
Preferred Device
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G A K
On-State RMS Current (180 Conduction Angles; TC = 100C) Average On-State Current (180 Conduction Angles; TC = 100C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 100C) Forward Average Gate Power (t = 8.3 ms, TC = 100C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 100C) Operating Junction Temperature Range Storage Temperature Range *Indicates JEDEC Registered Data.
PIN ASSIGNMENT
1 Cathode Anode Gate Anode 145 20 0.5 2.0 40 to +125 40 to +150 A2s Watts Watts A C C 2 3 4
Device 2N6400 2N6401 2N6402 Package TO220AB TO220AB TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box 500/Box 500/Box
2N6403 2N6404 2N6405
293
2N6400 Series

OFF CHARACTERISTICS
ON CHARACTERISTICS
* Peak Forward OnState Voltage (ITM = 32 A Peak, Pulse Width 1 ms, Duty Cycle 2%) * Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) * Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) Gate NonTrigger Voltage (VD = 12 Vdc, RL = 100 Ohms) * Holding Current (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (ITM = 16 A, IGT = 40 mAdc, VD = Rated VDRM) Turn-Off Time (ITM = 16 A, IR = 16 A, VD = Rated VDRM) TC = 25C TJ = +125C TC = 25C TC = 40C TC = 25C TC = 40C TC = +125C TC = 25C *TC = 40C tgt tq 15 35 VTM IGT VGT VGD 0.2 IH 18 1.0 40 60 s s mA 0.7 1.5 2.5 Volts 9.0 1.7 30 60 Volts mA Volts
Critical RateofRise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform) *Indicates JEDEC Registered Data. dv/dt TJ = +125C 50 V/s
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294
2N6400 Series
Symbol
Parameter
128 TC, MAXIMUM CASE TEMPERATURE ( C) P(AV) , AVERAGE POWER (WATTS) 124 120 116 112 dc 108 104 100 0 7.0 5.0 6.0 1.0 2.0 3.0 4.0 8.0 9.0 IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS) 10 = 30 60 90 120 180 = CONDUCTION ANGLE
16 14 12 10 8.0 6.0 4.0 2.0 0 0 = 30 TJ 125C 60 90 120
180 dc
= CONDUCTION ANGLE 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS) 10
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295
2N6400 Series
200
100 70 i TM , INSTANTANEOUS ONSTATE FORWARD CURRENT (AMPS) 50 30 20 TJ = 25C 10 7.0 5.0 3.0 2.0 160 I TSM , PEAK SURGE CURRENT (AMP) 1 CYCLE 125C
150
1.0 0.7 0.5 0.3 0.2 0.4 1.6 2.0 2.4 2.8 4.0 0.8 1.2 3.2 3.6 vTM, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) 4.4
140
130
TJ = 125C f = 60 Hz SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 1.0 2.0 3.0 4.0 6.0 8.0 10
120 110
NUMBER OF CYCLES
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296
2N6400 Series
100 70 50 30 20 10 7.0 5.0 3.0 2.0 1.0 0.2 0.5 1.0 2.0 5.0 10 20 PULSE WIDTH (ms) 50 100 200 100 I GT, GATE TRIGGER CURRENT (mA) OFF-STATE VOLTAGE = 12 V RL = 50
i GT, PEAK GATE CURRENT (mA)
TJ = 40C
10
25C
125C
1 40 25
10
95
110 125
Figure 6. Typical Gate Trigger Current versus Pulse Width
Figure 7. Typical Gate Trigger Current versus Junction Temperature
1.0 VGT, GATE TRIGGER VOLTAGE (VOLTS) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110 125
100
IH , HOLDING CURRENT (mA)
10
1 40 25 10
20
35
50
65
80
95
110 125
Figure 8. Typical Gate Trigger Voltage versus Junction Temperature
Figure 9. Typical Holding Current versus Junction Temperature
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297

Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supply crowbar circuits. Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 800 Volts 300 A Surge Current Capability Device Marking: Logo, Device Type, e.g., 2N6504, Date Code
Rating *Peak Repetitive OffState Voltage(1) (Gate Open, Sine Wave 50 to 60 Hz, TJ = 25 to 125C) 2N6504 2N6505 2N6507 2N6508 2N6509 On-State RMS Current (180 Conduction Angles; TC = 85C) Average On-State Current (180 Conduction Angles; TC = 85C) Peak Non-repetitive Surge Current 8.3 ms (1/2 Cycle, Sine Wave 60 Hz, TJ = 85C) 1.5 ms Forward Peak Gate Power (Pulse Width 1.0 s, TC = 85C) Forward Average Gate Power (t = 8.3 ms, TC = 85C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 85C) Operating Junction Temperature Range Storage Temperature Range *Indicates JEDEC Registered Data (1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. Symbol VDRM, VRRM 50 100 400 600 800 IT(RMS) IT(AV) ITSM 300 350 PGM PG(AV) IGM TJ Tstg 20 0.5 2.0 40 to +125 40 to +150 Watts Watts A C C 2N6504 2N6505 2N6507 2N6508 2N6509 25 16 A A A 1 2 Value Unit Volts 4
Preferred Device
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G A K
PIN ASSIGNMENT
1 2 3 4 Cathode Anode Gate Anode
Device Package TO220AB TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box 500/Box
298
2N6504 Series
*THERMAL CHARACTERISTICS

OFF CHARACTERISTICS
ON CHARACTERISTICS
* Forward OnState Voltage(1) (ITM = 50 A) * Gate Trigger Current (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) * Gate Trigger Voltage (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms, TC = 40C) Gate Non-Trigger Voltage (VAK = 12 Vdc, RL = 100 Ohms, TJ = 125C) * Holding Current (VAK = 12 Vdc, Initiating Current = 200 mA, Gate Open) * Turn-On Time (ITM = 25 A, IGT = 50 mAdc) Turn-Off Time (VDRM = rated voltage) (ITM = 25 A, IR = 25 A) (ITM = 25 A, IR = 25 A, TJ = 125C) TC = 25C TC = 40C tgt tq 15 35 TC = 25C TC = 40C VTM IGT VGT VGD IH 0.2 9.0 1.0 18 1.5 1.8 30 75 1.5 40 80 2.0 s s Volts mA Volts Volts mA
Critical Rate of Rise of Off-State Voltage (Gate Open, Rated VDRM, Exponential Waveform) *Indicates JEDEC Registered Data. (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. dv/dt 50 V/s
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299
2N6504 Series
Symbol
Parameter
TC, MAXIMUM CASE TEMPERATURE ( C)
P(AV) , AVERAGE POWER (WATTS)
13 0 12 0 110 = CONDUCTION ANGLE
32 = CONDUCTION ANGLE 60 = 30 180 90 dc
24
16 TJ = 125C 8.0
10 0 90 80 0 8.0 12 16 IT(AV), ON-STATE FORWARD CURRENT (AMPS) 4.0 20 = 30 60 90 180 dc
0 0 4.0 8.0 12 16 IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS) 20
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300
2N6504 Series
100 70 50 30 125C 20 iF , INSTANTANEOUS FORWARD CURRENT (AMPS) 25C
10 7.0 5.0 3.0 2.0
300 1.0 0.7 0.5 0.3 0.2 I TSM , PEAK SURGE CURRENT (AMP) 1 CYCLE 275
250
225 TC = 85C f = 60 Hz 200 175 1.0 SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 2.0 3.0 4.0 6.0 8.0 10
0.1 0 0.4 0.8 1.2 1.6 2.0 vF, INSTANTANEOUS VOLTAGE (VOLTS) 2.4 2.8
NUMBER OF CYCLES
Figure 3. Typical OnState Characteristics
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301
2N6504 Series
TYPICAL TRIGGER CHARACTERISTICS
100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C) 95 110 125 I GT, GATE TRIGGER CURRENT (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110 125
10
1 40 25
100
10
1 40 25 10
20
35
50
65
80
95
110 125
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302
C106 Series Sensitive Gate Silicon Controlled Rectifiers

Glassivated PNPN devices designed for high volume consumer applications such as temperature, light, and speed control; process and remote control, and warning systems where reliability of operation is important. Glassivated Surface for Reliability and Uniformity Power Rated at Economical Prices Practical Level Triggering and Holding Characteristics Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat Dissipation and Durability Sensitive Gate Triggering Device Marking: Device Type, e.g., C106B, Date Code
Rating Peak Repetitive OffState Voltage(1) (Sine Wave, 5060 Hz, RGK = 1 k, TC = 40 to 110C) C106B C106D, C106D1 C106M, C106M1 On-State RMS Current (180 Conduction Angles, TC = 80C) Average OnState Current (180 Conduction Angles, TC = 80C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = +110C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 sec, TC = 80C) Symbol VDRM, VRRM 200 400 600 IT(RMS) IT(AV) ITSM 4.0 2.55 20 Amps Amps Amps 1 I2t PGM PG(AV) IGM TJ Tstg 1.65 0.5 0.1 0.2 40 to +110 40 to +150 6.0 A2s Watt Watt Amp C106B C C in. lb. C106D C106D1 C106M C106M1 TO225AA TO225AA TO225AA TO225AA TO225AA 500/Box 500/Box 500/Box 500/Box 500/Box 2 3 Value Unit Volts
Preferred Device
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G A K
2 1
PIN ASSIGNMENT
Cathode Anode Gate
v v v
Forward Average Gate Power (Pulse Width 1.0 sec, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 sec, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Mounting Torque(2)
Device Package Shipping
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) Torque rating applies with use of compression washer (B52200F006). Mounting torque in excess of 6 in. lb. does not appreciably lower case-to-sink thermal resistance. Anode lead and heatsink contact pad are common.
303
May, 2000 Rev. 3
Publication Order Number: C106/D
C106 Series
THERMAL CHARACTERISTICS (TC = 25C unless otherwise noted.)
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Max 3.0 75 260 Unit C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, RGK = 1000 Ohms) TJ = 25C TJ = 110C IDRM, IRRM 10 100 A A
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (IFM = 1 A Peak for C106B, D, & M) (IFM = 4 A Peak for C106D1, & M1) Gate Trigger Current (Continuous dc)(2) (VAK = 6 Vdc, RL = 100 Ohms) Peak Reverse Gate Voltage (IGR = 10 A) Gate Trigger Voltage (Continuous dc)(2) (VAK = 6 Vdc, RL = 100 Ohms) Gate NonTrigger Voltage (Continuous dc)(2) (VAK = 12 V, RL = 100 Ohms, TJ = 110C) Latching Current (VAK = 12 V, IG = 20 mA) Holding Current (VD = 12 Vdc) (Initiating Current = 20 mA, Gate Open) TJ = 25C TJ = 40C TJ = 25C TJ = 40C TJ = +110C TJ = 25C TJ = 40C VTM 2.2 Volts
TJ = 25C TJ = 40C
IGT VGRM VGT 0.4 0.5 VGD IL IH .19 .33 .07 3.0 6.0 2.0 .20 .35 5.0 7.0 0.2 .60 .75 0.8 1.0 15 35 200 500 6.0
Volts Volts
Volts mA
mA
Critical RateofRise of OffState Voltage (VAK = Rated VDRM, Exponential Waveform, RGK = 1000 Ohms, TJ = 110C) (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (2) RGK is not included in measurement. dv/dt 8.0 V/s
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304
C106 Series
Symbol
Parameter
100 TC, CASE TEMPERATURE ( C) 90 80 70 60 50 40 30 20 10 0 .4 .8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 IT(AV) AVERAGE ON-STATE CURRENT (AMPERES) HALF SINE WAVE RESISTIVE OR INDUCTIVE LOAD. 50 to 400 Hz DC
P(AV), AVERAGE ON-STATE POWER DISSIPATION (WATTS)
110
10
JUNCTION TEMPERATURE 110C
8 HALF SINE WAVE RESISTIVE OR INDUCTIVE LOAD 50 TO 400Hz. DC
2 0 0 .4 .8 1.2 1.6 2.0 2.4 2.6 3.2 3.6 4.0 IT(AV) AVERAGE ON-STATE CURRENT (AMPERES)
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305
C106 Series
100 IGT, GATE TRIGGER CURRENT ( mA) 1000 IH, HOLDING CURRENT ( m A) 10 5 20 35 50 65 80 95 110
10
100
1 40 25
10 40 25
10
20
35
50
65
80
95
110

1.0 VGT , GATE TRIGGER VOLTAGE (V) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 45 25 10 5 20 35 50 65 80 95 110 1000 I L , LATCHING CURRENT (m A)
100
10 40 25
10
20
35
50
65
80
95
110
Figure 6. Typical Latching Current versus Junction Temperature
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306
C106 Series
Package Interchangeability
The dimensional diagrams below compare the critical dimensions of the ON Semiconductor C-106 package with competitive devices. It has been demonstrated that the smaller dimensions of the ON Semiconductor package make it compatible in most lead-mount and chassis-mount applications. The user is advised to compare all critical dimensions for mounting compatibility.
.295 ____ .305 .145 ____ .155 .148 ____ .158
.115 ____ .130
.400 ____ .360 .095 ____ .105 .135 ____ .115 .127 ____ DIA .123 .026 ____ .019
.425 ____ .435 1 2 3
5_ TYP
.520 ____ .480 .385 ____ .365
.050 ____ .095
.315 ____ .285 .420 ____ .400 .105 ____ .095 .054 ____ .046 .105 ____ .095
.575 ____ .655
.040 .094 BSC .025 ____ .035
.015 ____ .025 .045 ____ .055
.190 ____ .170
.020 ____ .026
ON Semiconductor C-106 Package
Competitive C-106 Package
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307
C122F1, C122B1 Silicon Controlled Rectifiers

Designed primarily for full-wave ac control applications, such as motor controls, heating controls and power supplies; or wherever halfwave silicon gatecontrolled, solidstate devices are needed. Glass Passivated Junctions and Center Gate Fire for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 200 Volts Device Marking: Logo, Device Type, e.g., C122F1, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 25 to 100C, Sine Wave, 50 to 60 Hz; Gate Open) C122F1 C122B1 On-State RMS Current (180 Conduction Angles; TC = 75C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TC = 75C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Power (Pulse Width = 10 s, TC = 70C) Forward Average Gate Power (t = 8.3 ms, TC = 70C) Forward Peak Gate Current (Pulse Width = 10 s, TC = 70C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 50 200 IT(RMS) ITSM 8.0 90 Amps Amps 1 A2s Watts Watt 1 2.0 40 to +125 40 to +150 Amps C C 2 3 TJ Tstg 4 2 3 Value Unit Volts 4
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G A K
I2t PGM PG(AV) IGM
34 5.0 0.5
PIN ASSIGNMENT
Device C122F1 C122B1 Package TO220AB TO220AB Shipping 500/Box 500/Box
308
Publication Order Number: C122F1/D
C122F1, C122B1
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Max 1.8 62.5 260 Unit C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TC = 25C TC = 125C IDRM, IRRM 10 0.5 A mA
ON CHARACTERISTICS
Peak OnState Voltage(1) (ITM = 16 A Peak, TC = 25C) Gate Trigger Current (Continuous dc) (VAK = 12 V, RL = 100 Ohms) Gate Trigger Voltage (Continuous dc) (VAK = 12 V, RL = 100 Ohms) Gate NonTrigger Voltage (Continuous dc) (VAK = 12 V, RL = 100 Ohms, TC = 125C) Holding Current (VAK = 12 Vdc, Initiating Current = 200 mA, Gate Open) TC = 25C TC = 40C Turn-Off Time (VD = Rated VDRM) (ITM = 8 A, IR = 8 A) TC = 25C TC = 40C TC = 25C TC = 40C VTM IGT VGT VGD IH tq 50 30 60 s 0.2 1.5 2.0 Volts mA 25 40 Volts 1.83 Volts mA
Critical RateofRise of OffState Voltage (VAK = Rated VDRM, Exponential Waveform, Gate Open, TC = 100C) (1) Pulse Test: Pulse Width 1 ms, Duty Cycle 2%. dv/dt 50 V/s
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309
C122F1, C122B1
Symbol
Parameter
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
100
100 95 90 85 80 75 70 65 60 0 1 2 3 4 5 CONDUCTION ANGLE = 60 RESISTIVE OR INDUCTIVE LOAD. 50 TO 400 Hz 120 180

0
CONDUCTION CONDUCTION ANGLE ANGLE
90
360 ONE CYCLE OF SUPPLY FREQUENCY
80
DC CONDUCTION ANGLE = 30 60 90 120 180

0 CONDUCTION ANGLE 360
240
360
70
60 0 1 2 3 4 5 6 7 8 IT(AV), AVERAGE ONSTATE FORWARD CURRENT (AMPERES)
IT(AV), AVERAGE ONSTATE CURRENT (AMPERES)
Figure 1. Current Derating (HalfWave)

P(AV), AVERAGE ONSTATE POWER DISSIPATION (WATTS) TC , AVERAGE ONSTATE POWER DISSIPATION (WATTS)
Figure 2. Current Derating (FullWave)
14 RESISTIVE OR INDUCTIVE LOAD, 50 TO 400 Hz 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 IT(AV), AVERAGE ONSTATE CURRENT (AMPERES) CONDUCTION ANGLE 30 60 180 90 120 DC
10 180 120 CONDUCTION ANGLE = 60
240
360
4
0
CONDUCTION CONDUCTION ANGLE ANGLE
360 ONE CYCLE OF SUPPLY FREQUENCY
0 0 1
RESISTIVE OR INDUCTIVE LOAD, 50 TO 400 Hz 2 3 4 5 6 7 8
IT(AV), AVERAGE ONSTATE CURRENT (AMPERES)
Figure 3. Maximum Power Dissipation (HalfWave)
Figure 4. Maximum Power Dissipation (FullWave)
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310
MAC08BT1, MAC08MT1
Preferred Device

Designed for use in solid state relays, MPU interface, TTL logic and other light industrial or consumer applications. Supplied in surface mount package for use in automated manufacturing. Sensitive Gate Trigger Current in Four Trigger Modes Blocking Voltage to 600 Volts Glass Passivated Surface for Reliability and Uniformity Surface Mount Package Device Marking: MAC08BT1: AC08B; MAC08MT1: A08M, and Date Code
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TRIAC 0.8 AMPERE RMS 200 thru 600 VOLTS

Rating Peak Repetitive OffState Voltage(1) (Sine Wave, 50 to 60 Hz, Gate Open, TJ = 25 to 110C) MAC08BT1 MAC08MT1 OnState Current RMS (TC = 80C) (Full Sine Wave 50 to 60 Hz) Peak Nonrepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TC = 25C) Circuit Fusing Considerations (Pulse Width = 8.3 ms) Peak Gate Power (TC = 80C, Pulse Width Average Gate Power (TC = 80C, t = 8.3 ms) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 200 600 IT(RMS) ITSM 0.8 8.0 Amps Amps Value Unit Volts
MT2 G
MT1
4 1 2 3
SOT223 CASE 318E STYLE 11
I2t PGM PG(AV) TJ Tstg
0.4 5.0 0.1 40 to +110 40 to +150
A2s 1 Watts Watt C 2 3 4
PIN ASSIGNMENT
v 1.0 s)
C Device MAC08BT1 Package SOT223 Shipping 16mm Tape and Reel (1K/Reel) 16mm Tape and Reel (1K/Reel)
MAC08MT1
SOT223
311
May, 2000 Rev. 3
Publication Order Number: MAC08BT1/D
MAC08BT1, MAC08MT1
Characteristic Thermal Resistance, Junction to Ambient PCB Mounted per Figure 1 Thermal Resistance, Junction to Tab Measured on MT2 Tab Adjacent to Epoxy Maximum Device Temperature for Soldering Purposes (for 10 Seconds Maximum) Symbol RJA RJT TL Max 156 25 260 Unit C/W C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 110C IDRM, IRRM 10 200 A A
ON CHARACTERISTICS
Peak OnState Voltage(1) (IT = 1.1 A Peak)
"
VTM IGT IH VGT
1.9 10 5.0 2.0
Volts mA mA Volts
Gate Trigger Current (Continuous dc) All Quadrants (VD = 12 Vdc, RL = 100 ) Holding Current (Continuous dc) (VD = 12 Vdc, Gate Open, Initiating Current =
"20 mA)
Gate Trigger Voltage (Continuous dc) All Quadrants (VD = 12 Vdc, RL = 100 )
Critical Rate of Rise of Commutation Voltage (f = 250 Hz, ITM = 1.0 A, Commutating di/dt = 1.5 A/mS OnState Current Duration = 2.0 mS, VDRM = 200 V, Gate Unenergized, TC = 110C, Gate Source Resistance = 150 , See Figure 10) Critical RateofRise of Off State Voltage (Vpk = Rated VDRM, TC= 110C, Gate Open, Exponential Method) (1) Pulse Test: Pulse Width 300 sec, Duty Cycle 2%. (dv/dt)c 1.5 V/s
dv/dt
10
V/s
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312
MAC08BT1, MAC08MT1
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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313
MAC08BT1, MAC08MT1
0.15 3.8 0.079 2.0 0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 inches mm 0.091 2.3 0.244 6.2
0.984 25.0
BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR. BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL. MATERIAL: G10 FIBERGLASS BASE EPOXY
0.096 2.44 0.059 1.5
0.096 2.44 0.059 1.5
0.096 2.44
0.472 12.0
Figure 1. PCB for Thermal Impedance and Power Testing of SOT-223
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314
MAC08BT1, MAC08MT1
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) 10 R JA , JUNCTION TO AMBIENT THERMAL RESISTANCE, C/W 160 150 140 130 120 110 100 90 80 70 60 50 40 30 TYPICAL MAXIMUM DEVICE MOUNTED ON FIGURE 1 AREA = L2 PCB WITH TAB AREA AS SHOWN L
1.0
L 4 1 2 3
0.1 TYPICAL AT TJ = 110C MAX AT TJ = 110C MAX AT TJ = 25C 0 1.0 2.0 3.0 4.0 vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 5.0
MINIMUM FOOTPRINT = 0.076 cm2 0 2.0 4.0 6.0 FOIL AREA (cm2) 8.0 10
0.01
Figure 2. On-State Characteristics

T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (C)
Figure 3. Junction to Ambient Thermal Resistance versus Copper Tab Area

110
110 T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (C) 30 60 90 dc = 180 120 MINIMUM FOOTPRINT 50 OR 60 Hz
= CONDUCTION
ANGLE
100 90 80 70 60 50 40 30 20 0
100 90 80 70 60 50 40 30 1.0 cm2 FOIL AREA 50 OR 60 Hz dc = 180 120
30
60 90
= CONDUCTION
ANGLE
0.4 0.1 0.2 0.3 IT(RMS), RMS ON-STATE CURRENT (AMPS)
0.5
20
0.1
0.3 0.4 0.5 0.6 IT(RMS), RMS ON-STATE CURRENT (AMPS)
0.2
0.7
T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (C)
Figure 4. Current Derating, Minimum Pad Size Reference: Ambient Temperature

110
Figure 5. Current Derating, 1.0 cm Square Pad Reference: Ambient Temperature

110 30 dc 100 = 180 95 120 90 85 80 REFERENCE: FIGURE 1
= CONDUCTION
60 90 80 70 4.0 cm2 FOIL AREA 60 50 dc = 180 120 90
= CONDUCTION
ANGLE
T(tab) , MAXIMUM ALLOWABLE TAB TEMPERATURE ( C)
100
30
105
60
90
ANGLE
0.1
0.6 0.3 0.4 0.5 IT(RMS), RMS ON-STATE CURRENT (AMPS) 0.2
0.7
0.8
0.1
0.3 0.4 0.5 0.6 IT(RMS), ON-STATE CURRENT (AMPS)
0.2
0.7
0.8
Figure 7. Current Derating Reference: MT2 Tab
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315
MAC08BT1, MAC08MT1
1.0 0.9 P(AV) , MAXIMUM AVERAGE POWER DISSIPATION (WATTS) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.3 0.4 0.5 0.6 IT(RMS), RMS ON-STATE CURRENT (AMPS) 0.2 0.7 0.8 0.01 0.0001 0.001 1.0 0.01 0.1 t, TIME (SECONDS) 10 100 = 180 dc 90
= CONDUCTION
ANGLE
1.0

120 30 60
0.1
Figure 9. Thermal Response, Device Mounted on Figure 1 Printed Circuit Board
LL 200 VRMS ADJUST FOR ITM, 60 Hz VAC TRIGGER CHARGE CONTROL TRIGGER CONTROL MEASURE I RS
1N4007
CS 1N914 51 MT2 MT1 G ADJUST FOR + dv/dt(c)
CHARGE
200 V
NON-POLAR CL
Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
Figure 10. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage (dv/dt)c
10 80 60
10
60 Hz 180 Hz 400 Hz
COMMUTATING dv/dt dv/dt c , (V/ S)
COMMUTATING dv/dt dv/dt c , (V/ S)
300 Hz
ITM
110 100 tw f= 1 2 tw
VDRM = 200 V
1.0 1.0
VDRM
(di dt) c
6f I
TM 1000 10
1.0 60
70
di/dtc, RATE OF CHANGE OF COMMUTATING CURRENT (A/mS)
80 90 100 TJ, JUNCTION TEMPERATURE (C)
110
Figure 11. Typical Commutating dv/dt versus Current Crossing Rate and Junction Temperature
Figure 12. Typical Commutating dv/dt versus Junction Temperature at 0.8 Amps RMS
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316
MAC08BT1, MAC08MT1
60 I GT , GATE TRIGGER CURRENT (mA) 600 Vpk TJ = 110C 50 STATIC dv/dt (V/ s) MAIN TERMINAL #2 POSITIVE 10 IGT3 IGT2 IGT4 IGT1 1.0
40
30 MAIN TERMINAL #1 POSITIVE 20 10 100 1000 RG, GATE MAIN TERMINAL 1 RESISTANCE (OHMS) 10,000
0.1 40
20
100
Figure 13. Exponential Static dv/dt versus Gate Main Terminal 1 Resistance
Figure 14. Typical Gate Trigger Current Variation
6.0 5.0 4.0 3.0 2.0 1.0 0 40 MAIN TERMINAL #1 POSITIVE
1.1 VGT , GATE TRIGGER VOLTAGE (VOLTS)
MAIN TERMINAL #2 POSITIVE
VGT3 VGT2 VGT1
VGT4
20
20
40
60
80
100
0.3 40
20
20
40
60
80
100
Figure 15. Typical Holding Current Variation
Figure 16. Gate Trigger Voltage Variation
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317
MAC08BT1, MAC08MT1 INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
0.15 3.8 0.079 2.0
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5
0.091 2.3
0.248 6.3
0.059 1.5
inches mm
SOT-223
SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the MT2 pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 550 milliwatts.
PD = 110C 25C = 550 milliwatts 156C/W
The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 550 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the MT2 pad. By increasing the area of the MT2 pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus MT2 pad area is shown in Figure 3. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.
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318
MAC08BT1, MAC08MT1
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating profile for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 RAMP 200C
STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
STEP 5 STEP 6 STEP 7 STEP 4 HEATING VENT COOLING HEATING ZONES 3 & 6 ZONES 4 & 7 205 TO SPIKE SOAK 219C 170C PEAK AT SOLDER 160C JOINT SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 50C 140C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 17. Typical Solder Heating Profile
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319
MAC4DCM, MAC4DCN
Preferred Device
Triacs

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Surface Mount DPAK Package Passivated Die for Reliability and Uniformity Blocking Voltage to 800 V OnState Current Rating of 4.0 Amperes RMS at 108C High Immunity to dv/dt 500 V/ms at 125C High Immunity to di/dt 6.0 A/ms at 125C Device Marking: Device Type with M truncated, e.g., MAC4DCM: AC4DCM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC4DCM MAC4DCN OnState RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 108C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 msec) Peak Gate Power (Pulse Width 10 msec, TC = 108C) Average Gate Power (t = 8.3 msec, TC = 108C) Peak Gate Current (Pulse Width 10 msec, TC = 108C) Peak Gate Voltage (Pulse Width 10 msec, TC = 108C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 4.0 Amps Value Unit Volts 4 4 1 2 1 2
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TRIACS 4.0 AMPERES RMS 600 thru 800 VOLTS
MT2 G
MT1
DPAK CASE 369 STYLE 6 40 Amps
ITSM
DPAK CASE 369A STYLE 6
PIN ASSIGNMENT
I2t PGM PG(AV) IGM VGM TJ Tstg 6.6 0.5 0.1 0.5 5.0 40 to 125 40 to 150 A2sec Watt Watt 1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Amp Device Volts C C MAC4DCM1 MAC4DCNT4 DPAK 369 DPAK 369A MAC4DCMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 75 Units/Rail 16mm Tape and Reel (2.5K/Reel) 75 Units/Rail
(1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded.
MAC4DCN1
DPAK 369
320
May, 2000 Rev. 3
Publication Order Number: MAC4DCM/D
MAC4DCM, MAC4DCN
Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance Junction to Ambient(1) Maximum Lead Temperature for Soldering Purposes(2) Symbol RqJC RqJA RqJA TL Max 3.5 88 80 260 Unit C/W
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted; Electricals apply in both directions)
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 2.0
ON CHARACTERISTICS
Peak OnState Voltage(3) (ITM = 6.0 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() VTM 1.3 1.6 Volts mA 8.0 8.0 8.0 VGT 0.5 0.5 0.5 0.8 0.8 0.8 0.4 22 1.3 1.3 1.3 35 Volts mA mA 30 50 20 60 80 60 12 18 22 35 35 35 Volts
W) W) W
IGT
Gate NonTrigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(), G() TJ = 125C Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current (VD = 12 V, IG = 35 mA) MT2(+), G(+) MT2(+), G() MT2(), G()
VGD IH IL
0.2 6.0
Characteristic Rate of Change of Commutating Current (VD = 400 V, ITM = 4.0 A, Commutating dv/dt = 18 V/ sec, Gate Open, TJ = 125C, f = 250 Hz, CL = 5.0 F, LL = 20 mH, No Snubber) See Figure 16 Symbol Min 6.0 Typ 8.4 Max Unit A/ms
di/dt(c)
Critical Rate of Rise of OffState Voltage (VD = 0.67 X Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. (3) Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%.
dv/dt
500
1700
V/ s
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321
MAC4DCM, MAC4DCN
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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322
MAC4DCM, MAC4DCN
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) P(AV) , AVERAGE POWER DISSIPATION (WATTS) 125 6.0 180 5.0

dc
120
a = 30
120 90
60 90
4.0 3.0 2.0
a = CONDUCTION ANGLE
115

110
120 180 dc 3.5 4.0
a = 30
1.0 0 0 1.0 2.0 3.0
60
105 0 0.5 1.0 1.5 2.0 2.5 3.0 IT(RMS), RMS ONSTATE CURRENT (AMPS)
4.0
IT(RMS), RMS ONSTATE CURRENT (AMPS)
I T, INSTANTANEOUS ONSTATE CURRENT (AMPS)
TYPICAL @ TJ = 25C 10 MAXIMUM @ TJ = 125C
r(t) , TRANSIENT RESISTANCE (NORMALIZED)
100
1.0
0.1 ZqJC(t) = RqJC(t)Sr(t)
1.0
MAXIMUM @ TJ = 25C
0.1 0 1.0 2.0 3.0 4.0 5.0 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
0.01 0.1 1.0 10 100 1000 10 k t, TIME (ms)
Figure 4. Transient Thermal Response
60 VGT, GATE TRIGGER VOLTAGE(VOLTS) I GT, GATE TRIGGER CURRENT (mA) 50 40 30 Q2 20 Q1 10 0 50
1.2 1.0 0.8 0.6 0.4 0.2 0 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Q2 Q3 Q1
Q3
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323
MAC4DCM, MAC4DCN
60 50 40 30 20 MT2 NEGATIVE 10 0 50 MT2 POSITIVE 120 100 Q2 80 60 Q1 40 20 0 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Q3
IL, LATCHING CURRENT (mA)
10 K TJ = 125C 8.0 K STATIC dv/dt (V/ ms) STATIC dv/dt (V/ ms)
15 K TJ = 125C VPK = 400 V 10 K 600 V 800 V 5.0 K
6.0 K 600 V 4.0 K 800 V
VPK = 400 V
2.0 K 0 100 1000 RGMT1, GATEMT1 RESISTANCE (OHMS) 10 K 0 100 1000 RGMT1, GATEMT1 RESISTANCE (OHMS) 10 K
Figure 9. Exponential Static dv/dt versus GateMT1 Resistance, MT2(+)
Figure 10. Exponential Static dv/dt versus GateMT1 Resistance, MT2()
10 K TJ = 100C
14 K 12 K GATE OPEN STATIC dv/dt (V/ ms) 10 K 8.0 K 6.0 K 4.0 K 2.0 K 0 400 500 600 700 800 400 500 600 700 800 VPK, PEAK VOLTAGE (VOLTS) VPK, PEAK VOLTAGE (VOLTS) 125C 110C TJ = 100C GATE OPEN
8.0 K STATIC dv/dt (V/ ms)
6.0 K
110C
4.0 K 125C
2.0 K 0
Figure 11. Exponential Static dv/dt versus Peak Voltage, MT2(+)
Figure 12. Exponential Static dv/dt versus Peak Voltage, MT2()
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324
MAC4DCM, MAC4DCN
10 K 14 K 12 K 8.0 K STATIC dv/dt (V/ ms) VPK = 400 V 6.0 K 600 V 4.0 K 800 V 2.0 K 2.0 K 0 100 105 110 115 120 125 TJ, JUNCTION TEMPERATURE (C) 0 100 105 110 115 120 125 TJ, JUNCTION TEMPERATURE (C) GATE OPEN STATIC dv/dt (V/ ms) 10 K 8.0 K 6.0 K 800 V 4.0 K 600 V VPK = 400 V GATE OPEN
Figure 13. Typical Exponential Static dv/dt versus Junction Temperature, MT2(+)
Figure 14. Typical Exponential Static dv/dt versus Junction Temperature, MT2()
100 VPK = 400 V dv/dt(c), CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ ms)
TJ = 125C 10
100C
75C
tw VDRM
f=
1 2 tw
6f I (di/dt)c = TM 1000
1.0 0 5.0 10 15 20 25 30 35 di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 15. Critical Rate of Rise of Commutating Voltage
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325
MAC4DCM, MAC4DCN
LL 200 VRMS ADJUST FOR ITM, 60 Hz VAC TRIGGER CHARGE CONTROL TRIGGER CONTROL MEASURE I
1N4007
+ 1N914 51 MT2 MT1 G
CHARGE
200 V
NON-POLAR CL
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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326
MAC4DCM, MAC4DCN
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
http://onsemi.com
327
MAC4DHM Sensitive Gate Triacs

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Surface Mount DPAK Package Passivated Die for Reliability and Uniformity FourQuadrant Triggering Blocking Voltage to 600 V OnState Current Rating of 4.0 Amperes RMS at 93C Low Level Triggering and Holding Characteristics Device Marking: Device Type with M truncated, e.g., MAC4DHM: AC4DHM, Date Code
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Preferred Device
TRIACS 4.0 AMPERES RMS 600 VOLTS
MT2 G
MT1

Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MAC4DHM OnState RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 93C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 msec) Peak Gate Power (Pulse Width 10 msec, TC = 93C) Average Gate Power (t = 8.3 msec, TC = 93C) Peak Gate Current (Pulse Width 10 msec, TC = 93C) Peak Gate Voltage (Pulse Width 10 msec, TC = 93C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 IT(RMS) 4.0 Amps Value Unit Volts 4 1 2 1 2 4
ITSM I2t PGM PG(AV) IGM VGM TJ Tstg
40 6.6 0.5 0.1 0.2 5.0 40 to 110 40 to 150
Amps A2sec Watts Watts Amps Volts C C
DPAK CASE 369 STYLE 6
PIN ASSIGNMENT
1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Device MAC4DHMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 75 Units/Rail
MAC4DHM1
DPAK 369
328
May, 2000 Rev. 3
Publication Order Number: MAC4DHM/D
MAC4DHM
Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance Junction to Ambient(1) Maximum Lead Temperature for Soldering Purposes(2) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. Symbol RqJC RqJA RqJA TL Max 3.5 88 80 260 Unit C/W
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak OnState Voltage(1) (ITM = 6.0 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Continuous dc) (VD = 12 V, RL = 100 , TJ = 110C) All Four Quadrants VTM 1.3 1.8 2.1 2.4 4.2 0.62 0.57 0.65 0.74 0.4 1.6 mA VGT 0.5 0.5 0.5 0.5 VGD 0.1 1.3 1.3 1.3 1.3 Volts 5.0 5.0 5.0 10 Volts Volts
W)
IGT
W)
Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) (VD = 12 V, IG = 5.0 mA) (VD = 12 V, IG = 5.0 mA) (VD = 12 V, IG = 5.0 mA) (VD = 12 V, IG = 10 mA)
IH IL 1.75 5.2 2.1 2.2 10 10 10 10 1.5 15
mA mA
Characteristic Rate of Change of Commutating Current (VD = 200 V, ITM = 1.8 A, Commutating dv/dt = 1.0 V/ sec, TJ = 110C, f = 250 Hz, CL = 5.0 fd, LL = 80 mH, RS = 56 , CS = 0.03 fd) With snubber see Figure 11 Symbol Min Typ 3.0 Max Unit A/ms
di/dt(c)
Critical Rate of Rise of OffState Voltage (VD = 0.67 X Rated VDRM, Exponential Waveform, Gate Open, TJ = 110C) (1) Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%.
dv/dt 20
V/ s
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329
MAC4DHM
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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330
MAC4DHM
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) P(AV) , AVERAGE POWER DISSIPATION (WATTS) 110 6.0 5.0 4.0 3.0 2.0 60 90 180 120 dc
105
a = 30
60 90
100 95 120 180 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IT(RMS), RMS ONSTATE CURRENT (AMPS)
dc 4.0
a = 30
1.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
4.0
100
1.0
1.0
MAXIMUM @ TJ = 25C 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
8.0 VGT, GATE TRIGGER VOLTAGE (VOLTS) I GT, GATE TRIGGER CURRENT (mA) 7.0 6.0 5.0 4.0 Q2 3.0 Q1 2.0 1.0 0 40 25 10 5.0 20 35 50 65 80 95 110 Q3 Q4
1.0 Q4 Q1 0.8 Q2 0.6 Q3
0.4
0.2 40 25 10 5.0 20 35 50 65 80 95 110 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
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331
MAC4DHM
5.0 12 10 8.0 6.0 4.0
4.0
3.0 MT2 NEGATIVE 2.0 MT2 POSITIVE 1.0 0 40 25
Q2
Q4 Q3
2.0 Q1 0
10
5.0
20
35
50
65
80
95
110
40 25
10
5.0
20
35
50
65
80
95
110
40 35 STATIC dv/dt (V/ ms) 30 25 20 15 10 5 100 1000 GATEMT1 RESISTANCE (OHMS) 10 K MAC4DHM dv/dt(c), CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ ms) VD = 400 V TJ = 110C
10 VPK = 400 V
TJ = 110C
100C
90C
1.0
tw VDRM
f=
1 2 tw
6f I (di/dt)c = TM 1000
0.1 0 1.0 2.0 3.0 4.0 5.0 6.0 di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 9. Minimum Exponential Static dv/dt versus GateMT1 Resistance
Figure 10. Typical Critical Rate of Rise of Commutating Voltage
1N4007
CS 1N914 51 MT2 MT1 G ADJUST FOR + di/dt(c)
CHARGE
200 V
NON-POLAR CL
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332
MAC4DHM
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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333
MAC4DLM Sensitive Gate Triacs

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Surface Mount DPAK Package Passivated Die for Reliability and Uniformity FourQuadrant Triggering Blocking Voltage to 600 V OnState Current Rating of 4.0 Amperes RMS at 93C Low Level Triggering and Holding Characteristics Device Marking: Device Type with M truncated, e.g., MAC4DLM: AC4DLM, Date Code
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Preferred Device
MT2 G
MT1

Rating Peak Repetitive OffState Voltage (1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MAC4DLM OnState RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 93C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 msec) Peak Gate Power (Pulse Width 10 msec, TC = 93C) Average Gate Power (t = 8.3 msec, TC = 93C) Peak Gate Current (Pulse Width 10 msec, TC = 93C) Peak Gate Voltage (Pulse Width 10 msec, TC = 93C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 IT(RMS) 4.0 Amps Value Unit Volts 4 1 2 1 2 4
ITSM I2t PGM PG(AV) IGM VGM TJ Tstg
40 6.6 0.5 0.1 0.2 5.0 40 to 110 40 to 150
Amps A2sec Watts Watts Amps Volts C C
DPAK CASE 369 STYLE 6
PIN ASSIGNMENT
1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Device MAC4DLMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 75 Units/Rail
MAC4DLM1
DPAK 369
334
May, 2000 Rev. 1
Publication Order Number: MAC4DLM/D
MAC4DLM
Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance Junction to Ambient (1) Maximum Lead Temperature for Soldering Purposes (2) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. Symbol RqJC RqJA RqJA TL Max 3.5 88 80 260 Unit C/W
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak OnState Voltage (1) (ITM = 6.0 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (VD = 12 V, RL = 100 , TJ = 110C) MT2(+), G(+); MT2(+), G(); MT2(), G(); MT2(), G(+) VTM 1.3 1.8 2.1 2.4 4.2 0.62 0.57 0.65 0.74 1.6 mA VGT 0.5 0.5 0.5 0.5 VGD 0.1 IH IL (VD = 12 V, IG = 5.0 mA) (VD = 12 V, IG = 5.0 mA) (VD = 12 V, IG = 5.0 mA) (VD = 12 V, IG = 10 mA) 1.75 5.2 2.1 2.2 10 10 10 10 1.5 15 mA 0.4 mA 1.3 1.3 1.3 1.3 Volts 3.0 3.0 3.0 5.0 Volts Volts
W)
IGT
W)
Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+)
Characteristic Rate of Change of Commutating Current (VD = 200 V, ITM = 1.8 A, Commutating dv/dt = 1.0 V/ sec, TJ = 110C, f = 250 Hz, CL = 5.0 fd, LL = 80 mH, RS = 56 , CS = 0.03 fd) With snubber see Figure 11 Symbol Min Typ 3.0 Max Unit A/ms
di/dt(c)
Critical Rate of Rise of OffState Voltage (VD = 0.67 X Rated VDRM, Exponential Waveform, Gate Open, TJ = 110C) (1) Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%.
dv/dt 10
V/ s
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335
MAC4DLM
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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336
MAC4DLM
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) P(AV) , AVERAGE POWER DISSIPATION (WATTS) 110 6.0 5.0 4.0 3.0 2.0 60 90 180 120 dc
105
a = 30
60 90
100 95 120 180 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IT(RMS), RMS ONSTATE CURRENT (AMPS)
dc 4.0
a = 30
1.0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
4.0
100
1.0
1.0
MAXIMUM @ TJ = 25C 0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
8.0 VGT, GATE TRIGGER VOLTAGE (VOLTS) I GT, GATE TRIGGER CURRENT (mA) 7.0 6.0 5.0 4.0 Q2 3.0 Q1 2.0 1.0 0 40 25 10 5.0 20 35 50 65 80 95 110 Q3 Q4
1.0 Q4 Q1 0.8 Q2 0.6 Q3
0.4
0.2 40 25 10 5.0 20 35 50 65 80 95 110 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
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337
MAC4DLM
5.0 12 10 8.0 6.0 4.0
4.0
3.0 MT2 NEGATIVE 2.0 MT2 POSITIVE 1.0 0 40 25
Q2
Q4 Q3
2.0 Q1 0
10
5.0
20
35
50
65
80
95
110
40 25
10
5.0
20
35
50
65
80
95
110
40 35 STATIC dv/dt (V/ ms) 30 25 20 15 10 5.0 100 1000 RGK, GATEMT1 RESISTANCE (OHMS) 10 K MAC4DLM dv/dt(c), CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ ms) VD = 400 V TJ = 110C
10 VPK = 400 V
TJ = 110C
100C
90C
1.0
tw VDRM
f=
1 2 tw
6f I (di/dt)c = TM 1000
0.1 0 1.0 2.0 3.0 4.0 5.0 6.0 di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 9. Minimum Exponential Static dv/dt versus GateMT1 Resistance
1N4007
CHARGE
200 V
NON-POLAR CL
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338
MAC4DLM
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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339
MAC4DSM, MAC4DSN
Preferred Device
Triacs

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Surface Mount DPAK Package Passivated Die for Reliability and Uniformity Blocking Voltage to 800 V OnState Current Rating of 4.0 Amperes RMS at 108C Low IGT 10 mA Maximum in 3 Quadrants High Immunity to dv/dt 50 V/ms at 125C Device Marking: Device Type with M truncated, e.g., MAC4DSM: AC4DSM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC4DSM MAC4DSN OnState RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 108C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 msec) Peak Gate Power (Pulse Width 10 msec, TC = 108C) Average Gate Power (t = 8.3 msec, TC = 108C) Peak Gate Current (Pulse Width 10 msec, TC = 108C) Peak Gate Voltage (Pulse Width 10 msec, TC = 108C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 4.0 Amps Value Unit Volts 4 4 1 2 1 2
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TRIACS 4.0 AMPERES RMS 600 thru 800 VOLTS
MT2 G
MT1
DPAK CASE 369 STYLE 6 40 Amps
ITSM
PIN ASSIGNMENT
I2t PGM PG(AV) IGM VGM TJ Tstg 6.6 0.5 0.1 0.2 5.0 40 to 125 40 to 150 A2sec Watt Watt 1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Amp Device Volts C C MAC4DSM1 MAC4DSNT4 DPAK 369 DPAK 369A MAC4DSMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 75 Units/Rail 16mm Tape and Reel (2.5K/Reel) 75 Units/Rail
MAC4DSN1
DPAK 369
340
May, 2000 Rev. 3
Publication Order Number: MAC4DSM/D
MAC4DSM, MAC4DSN
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak OnState Voltage(3) (ITM = 6.0 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 MT2(+), G(+) MT2(+), G() MT2(), G() VTM 1.3 1.6 Volts mA 2.9 2.9 2.9 VGT 0.5 0.5 0.5 0.7 0.65 0.7 0.4 5.5 1.3 1.3 1.3 15 Volts mA mA 6.0 10 6.0 30 30 30 4.0 5.0 7.0 10 10 10 Volts
W) W) W
IGT
Gate NonTrigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(), G() TJ = 125C Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current (VD = 12 V, IG = 10 mA) MT2(+), G(+) MT2(+), G() MT2(), G()
VGD IH IL
0.2 2.0
Characteristic Rate of Change of Commutating Current (VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V/ sec, Gate Open, TJ = 125C, f = 500 Hz, CL = 5.0 F, LL = 20 mH, No Snubber) See Figure 16 Symbol Min 3.0 Typ 4.0 Max Unit A/ms
di/dt(c)
Critical Rate of Rise of OffState Voltage (VD = 0.67 X Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. (3) Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%.
dv/dt
50
175
V/ s
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341
MAC4DSM, MAC4DSN
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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342
MAC4DSM, MAC4DSN
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) P(AV) , AVERAGE POWER DISSIPATION (WATTS) 125 6.0 180 5.0

dc
120
a = 30
120 90
60 90
4.0 3.0 2.0
115

110
120 180 dc 3.5 4.0
a = 30
1.0 0 0 1.0 2.0 3.0
60
105 0 0.5 1.0 1.5 2.0 2.5 3.0 IT(RMS), RMS ONSTATE CURRENT (AMPS)
4.0
IT, INSTANTANEOUS ONSTATE CURRENT (AMPS)
100
1.0
1.0
MAXIMUM @ TJ = 25C
0.01 0.1 1.0 10 100 1000 10 k t, TIME (ms)
18 VGT, GATE TRIGGER VOLTAGE(VOLTS) Q3 I GT, GATE TRIGGER CURRENT (mA) 16 14 12 10 8.0 6.0 4.0 2.0 0 50 25 0 25 50 75 100 125 Q1 Q2
1.0 Q3 0.8 Q2 Q1
0.6
0.4
0.2 50 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
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343
MAC4DSM, MAC4DSN
14 12 IH , HOLDING CURRENT (mA) 10 MT2 NEGATIVE 8.0 6.0 4.0 2.0 0 50 MT2 POSITIVE IL, LATCHING CURRENT (mA) 20 Q1 15 Q3 10 25 Q2
5.0 0
25
25
50
75
100
125
50
25
25
50
75
100
125
1000 TJ = 125C 800 STATIC dv/dt (V/ ms) STATIC dv/dt (V/ ms)
1200 TJ = 125C 1000 800 600 400 200 0 100 1000 RGMT1, GATEMT1 RESISTANCE (OHMS) 10 k 100 1000 RGMT1, GATEMT1 RESISTANCE (OHMS) 10 k 600 V VPK = 400 V
600
400 600 V 200 0 800 V
VPK = 400 V
800 V
Figure 9. Exponential Static dv/dt versus GateMT1 Resistance, MT2(+)
Figure 10. Exponential Static dv/dt versus GateMT1 Resistance, MT2()
800 GATE OPEN 600 STATIC dv/dt (V/ ms) STATIC dv/dt (V/ ms) TJ = 100C 400 110C 125C 200
2000
1600 TJ = 100C 1200 110C 800 125C
GATE OPEN
400 0 400 500 600 700 800 400 500 600 700 800 VPK, PEAK VOLTAGE (VOLTS) VPK, PEAK VOLTAGE (VOLTS)
Figure 11. Exponential Static dv/dt versus Peak Voltage, MT2(+)
Figure 12. Exponential Static dv/dt versus Peak Voltage, MT2()
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344
MAC4DSM, MAC4DSN
800 GATE OPEN 600 STATIC dv/dt (V/ ms) VPK = 400 V STATIC dv/dt (V/ ms) 1600 1400 1200 1000 800 600 400 800 V 0 100 105 110 115 120 125 TJ, JUNCTION TEMPERATURE (C) 200 0 100 105 110 115 120 125 TJ, JUNCTION TEMPERATURE (C) 800 V 600 V VPK = 400 V GATE OPEN
400
600 V
200
Figure 13. Typical Exponential Static dv/dt versus Junction Temperature, MT2(+)
Figure 14. Typical Exponential Static dv/dt versus Junction Temperature, MT2()
100 VPK = 400 V dv/dt(c), CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ ms)
TJ = 125C 10
100C
75C
tw VDRM
f=
1 2 tw
6f I (di/dt)c = TM 1000
1.0 0 5.0 10 15 20 di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
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345
MAC4DSM, MAC4DSN
1N4007
+ 1N914 51 MT2 MT1 G
CHARGE
200 V
NON-POLAR CL
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346
MAC4DSM, MAC4DSN
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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347
MAC4M, MAC4N
Preferred Device
Triacs

Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. Blocking Voltage to 800 Volts On-State Current Rating of 4.0 Amperes RMS at 100C Uniform Gate Trigger Currents in Three Modes High Immunity to dv/dt 500 V/s minimum at 125C Minimizes Snubber Networks for Protection High Surge Current Capability 40 Amperes Industry Standard TO-220AB Package High Commutating di/dt 6.0 A/ms minimum at 125C Operational in Three Quadrants: Q1, Q2, and Q3 Device Marking: Logo, Device Type, e.g., MAC4M, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC4M MAC4N On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 100C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.33 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 100C) Average Gate Power (t = 8.3 ms, TC = 100C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 4.0 Amps 1 2 Value Unit Volts 4
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MT2 G
MT1
ITSM
40
Amps
6.6 0.5 0.1 40 to +125 40 to +150
A2sec Watt Watt C C 1 2 3 4
PIN ASSIGNMENT
Device MAC4M MAC4N Package TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail
348
Publication Order Number: MAC4M/D
MAC4M, MAC4N
Characteristic Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Value 2.2 62.5 260 Unit C/W C
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 6.0 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current (VD = 12 V, IG = 35 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() VTM IGT 8.0 8.0 8.0 IH IL VGT 0.5 0.5 0.5 0.8 0.8 0.8 1.3 1.3 1.3 25 40 20 60 80 60 V 6.0 12 16 21 20 35 35 35 35 mA mA 1.3 1.6 V mA
Rate of Change of Commutating Current (VD = 400 V, ITM = 4.0 A, Commutating dv/dt = 18 V/s, Gate Open, TJ = 125C, f = 250 Hz, CL = 5.0 F, LL = 20 mH, No Snubber) Critical Rate of Rise of Off-State Voltage (VD = 0.67 x Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 200 mA/sec; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 6.0 8.4 A/ms
dv/dt
500
1500
V/s
di/dt
10
A/s
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349
MAC4M, MAC4N
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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350
MAC4M, MAC4N
IGT, GATE TRIGGER CURRENT (mA) 100 VGT, GATE TRIGGER VOLTAGE (VOLTS) Q2 Q3 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) Q2 Q1 Q3
10
Q1
1 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C)

100 IL , LATCHING CURRENT (mA) Q2 Q1 Q3 100 IH, HOLDING CURRENT (mA)
MT2 Positive
MT2 Negative 10
10

P(AV), AVERAGE POWER DISSIPATION (WATTS) 125 TC , CASE TEMPERATURE (C) 6
DC 5 4 3 2 1 0 60 180 120 90
120
115 60 110 90 120 180 105
30
30
DC 0 0.5 1 1.5 2 2.5 3 3.5 IT(RMS), RMS ON-STATE CURRENT (AMPS) 4
1 2 3 0.5 1.5 2.5 3.5 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
Figure 5. Typical RMS Current Derating
Figure 6. On-State Power Dissipation
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351
MAC4M, MAC4N
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) Maximum @ TJ = 25C Typical @ TJ = 25C Maximum @ TJ = 125C r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 100 1
10
0.1
0.01 0.1
10 100 t, TIME (ms)
1000
10000

0.1 0 1 2 3 4 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
Figure 7. Typical On-State Characteristics
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352
MAC4SM, MAC4SN
Preferred Device

Designed for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications. Sensitive Gate Allows Triggering by Microcontrollers and other Logic Circuits High Immunity to dv/dt 50 V/ms Minimum at 125_C Commutating di/dt 3.0 A/ms Minimum at 125_C Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design On-State Current Rating of 4 Amperes RMS at 100_C High Surge Current Capability 40 Amperes Blocking Voltage to 800 Volts Rugged, Economical TO220AB Package Operational in Three Quadrants: Q1, Q2, and Q3 Device Marking: Logo, Device Type, e.g., MAC4SM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC4SM MAC4SN On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 100C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.33 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 100C) Average Gate Power (t = 8.3 ms, TC = 100C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 4.0 Amps Value Unit Volts 1
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MT2 G
MT1
ITSM I2t PGM PG(AV) TJ Tstg
40 6.6 0.5 0.1 40 to +125 40 to +150
Amps A2sec Watt Watt C C MAC4SM MAC4SN 1 2 3 4
PIN ASSIGNMENT
Device Package TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail
353
Publication Order Number: MAC4SM/D
MAC4SM, MAC4SN
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 6.0 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current (VD = 12 V, IG = 10 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() VTM IGT 2.9 2.9 2.9 IH IL VGT 0.5 0.5 0.5 0.7 .65 0.7 1.3 1.3 1.3 6.0 15 6.0 30 30 30 V 2.0 4.0 4.7 6.0 5.0 10 10 10 15 mA mA 1.3 1.6 V mA
Rate of Change of Commutating Current (VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V/s, Gate Open, TJ = 125C, f = 500 Hz, CL = 5.0 F, LL = 20 mH, No Snubber) Critical Rate of Rise of Off-State Voltage (VD = 0.67 x Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 200 mA/sec; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 3.0 4.0 A/ms
dv/dt
50
150
V/s
di/dt
10
A/s
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354
MAC4SM, MAC4SN
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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355
MAC4SM, MAC4SN
IGT, GATE TRIGGER CURRENT (mA) 100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 1.0 0.9 0.8 0.7 0.6 Q2 0.5 Q1 0.4 0.3 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) Q3
10
Q3
Q2
Q1

100 IL , LATCHING CURRENT (mA) 100 IH, HOLDING CURRENT (mA)
Q2 Q1 10 Q3
10
MT2 Positive MT2 Negative

DC 5 4 3 2 1 0 60 180 120 90
120
115 60 110 90 120 180 105
30
30
DC 0 0.5 1 1.5 2 2.5 3 3.5 IT(RMS), RMS ON-STATE CURRENT (AMP) 4
1 2 3 IT(RMS), RMS ON-STATE CURRENT (AMP)
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356
MAC4SM, MAC4SN
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 100 1
Typical @ TJ = 125C Maximum @ TJ = 125C 10
0.1
0.01 0.1
10 100 t, TIME (ms)
1000
10000

0 0.5 1 1.5 2 2.5 3 3.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
0.1
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357
MAC8D, MAC8M, MAC8N

Preferred Device
Triacs

Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. Blocking Voltage to 800 Volts On-State Current Rating of 8.0 Amperes RMS at 100C Uniform Gate Trigger Currents in Three Quadrants High Immunity to dv/dt 250 V/s minimum at 125C Minimizes Snubber Networks for Protection Industry Standard TO-220AB Package High Commutating di/dt 6.5 A/ms minimum at 125C Device Marking: Logo, Device Type, e.g., MAC8D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC8D MAC8M MAC8N On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 100C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) 8.0 Amps 1 ITSM 80 Amps Value Unit Volts 4
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MT2 G
MT1
26 16 0.35 40 to +125 40 to +150
A2sec Watts 1 Watt C C 2 3 4
PIN ASSIGNMENT
Device MAC8D MAC8M MAC8N Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
358
Publication Order Number: MAC8D/D
MAC8D, MAC8M, MAC8N

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage* (ITM = 11 A Peak) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 150 mA) Latching Current (VD = 24 V, IG = 35 mA) MT2(+), G(+); MT2(), G() MT2(+), G() Gate Trigger Voltage (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Gate NonTrigger Voltage (VD = 12 V, RL = 100 , TJ = 125C) MT2(+), G(+); MT2(+), G(); MT2(), G() VTM IGT 5.0 5.0 5.0 IH IL VGT 0.5 0.5 0.5 VGD 0.2 0.69 0.77 0.72 1.5 1.5 1.5 Volts 20 30 50 80 Volts 13 16 18 20 35 35 35 40 mA mA 1.2 1.6 Volts mA
Rate of Change of Commutating Current See Figure 10. (VD = 400 V, ITM = 4.4 A, Commutating dv/dt = 18 V/s, Gate Open, TJ = 125C, f = 250 Hz, No Snubber) CL = 10 F LL = 40 mH Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) *Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 6.5 A/ms
dv/dt
250
V/s
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359
MAC8D, MAC8M, MAC8N

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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360
MAC8D, MAC8M, MAC8N

125 PAV, AVERAGE POWER (WATTS) TC, CASE TEMPERATURE (C) 120 = 120, 90, 60, 30 115 = 180 110 DC 105 12 DC 10 180 8 6 4 2 0 = 30 60 90 120
100
3 4 5 6 IT(RMS), RMS ON-STATE CURRENT (AMP)
2 3 4 5 6 IT(RMS), ON-STATE CURRENT (AMP)
100
TYPICAL AT TJ = 25C MAXIMUM @ TJ = 125C
0.1
I T, INSTANTANEOUS ON-STATE CURRENT (AMP)
10
0.01
0.1
10
100 t, TIME (ms)
1000
1 104
MAXIMUM @ TJ = 25C 1
40 35 I H, HOLD CURRENT (mA) 30 MT2 POSITIVE 25 20 15 MT2 NEGATIVE 10
0.1
0.5
1 1.5 2 2.5 3 3.5 4 4.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
5 50
30
10
110
130
Figure 3. On-State Characteristics http://onsemi.com

361
Figure 5. Hold Current Variation
MAC8D, MAC8M, MAC8N

100 Q2 Q3 Q1 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) 1 0.95 0.9 0.85 0.8 075 0.7 0.65 0.6 0.55 0.5 0.45 0.4 50 Q2 Q3
10
Q1
1 50
30
10
110
130
30
10
110
130
Figure 6. Gate Trigger Current Variation

dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE (V/ s)
5000 4.5K 4K 3.5K 3K 2.5K 2K 1.5K 1K 500 0 1 MT2 POSITIVE 10 100 RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) 1000 MT2 NEGATIVE
100 (dv/dt) c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s)
TJ = 125C 10
100C
75C
tw VDRM
f=
1 2 tw
6f I (di/dt)c = TM 1000
1 10
15 20 25 30 35 40 45 50 55 60 (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 8. Critical Rate of Rise of Off-State Voltage (Exponential)
1N4007
+ 1N914 51 MT2 MT1 G
CHARGE
200 V
NON-POLAR CL
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362
MAC8SD, MAC8SM, MAC8SN

Preferred Device

Designed for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications. Sensitive Gate Allows Triggering by Microcontrollers and other Logic Circuits Uniform Gate Trigger Currents in Three Quadrants; Q1, Q2, and Q3 High Immunity to dv/dt 25 V/ms Minimum at 110_C High Commutating di/dt 8.0 A/ms Minimum at 110_C Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design On-State Current Rating of 8 Amperes RMS at 70_C High Surge Current Capability 70 Amperes Blocking Voltage to 800 Volts Rugged, Economical TO220AB Package Device Marking: Logo, Device Type, e.g., MAC8SM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MAC8SD MAC8SM MAC8SN On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 70C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 70C) Average Gate Power (t = 8.3 ms, TC = 70C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) 8.0 Amps Value Unit Volts 1
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MT2 G
MT1
ITSM
70
Amps 1 2
PIN ASSIGNMENT
20 16 0.35 40 to +110 40 to +150
A2sec Watts Watt C C
3 4
Device MAC8SD MAC8SM MAC8SN Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
363
Publication Order Number: MAC8S/D

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage* (ITM =
11A)
VTM IGT
.8 .8 .8
2.0 3.0 3.0 3.0 5.0 10 5.0 0.62 0.60 0.65
1.85 5.0 5.0 5.0 10 15 20 15
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12V, Gate Open, Initiating Current = Latching Current (VD = 24V, IG = 5mA) MT2(+), G(+) MT2(), G() MT2(+), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100) MT2(+), G(+) MT2(+), G() MT2(), G()
150mA)
IH IL
1.0 2.0 2.0 2.0
mA mA
VGT 0.45 0.45 0.45 1.5 1.5 1.5
Volts
Rate of Change of Commutating Current VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V m/sec, Gate Open, TJ = 110_C, f = 500 Hz, Snubber: CS = 0.01 mF, RS =15 , See Figure 16.) di/dt(c) 8.0 10 A/ms
Critical Rate of Rise of Off-State Voltage (VD = Rate VDRM, Exponential Waveform, RGK = 510
W, TJ = 110_C)
dv/dt
25
75
V/ s
*Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.
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364

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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365

T C , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) 110 P(AV), AVERAGE POWER DISSIPATION (WATTS) 25

100
20
180 120 90 60
DC
a = 30 and 60
90

15
80
10
70
90 180 DC
a = 30
5
60
2 4 6 8 10 IT(RMS), RMS ONSTATE CURRENT (AMPS)
12
4 6 8 10 IT(RMS), RMS ONSTATE CURRENT (AMPS)
12
R(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED)
I T, INSTANTANOUS ON-STATE CURRENT (AMPS)
100
Typical @ TJ = 25C Maximum @ TJ = 110C
10
ZqJC(t) = RqJC(t) r(t) 0.1
1 Maximum @ TJ = 25C
0.1
0.5
1.5 2 2.5 3 3.5 4 4.5 5 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
5.5
0.01 0.1
10 100 t, TIME (ms)
1000
1@ 10 4
10 I L , LATCHING CURRENT (mA)
25
I H , HOLDING CURRENT (mA)
20
6 MT2 NEGATIVE 4 MT2 POSITIVE 2
15
10
Q3
5 Q1
40 25
10
95
110
40 25
10
80
95
110
Figure 5. Typical Holding Current Versus Junction Temperature
Figure 6. Typical Latching Current Versus Junction Temperature
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366

14 V GT, GATE TRIGGER VOLTAGE (VOLTS) IGT, GATE TRIGGER CURRENT (mA) 12 10 8 6 4 2 Q1 0 40 25 10 5 20 35 50 65 TJ, JUNCTION TEMPERATURE (C) 80 95 110 Q3 Q2 1 0.9 Q3 0.8 0.7 0.6 0.5 Q2 0.4 0.3 40 25 10 5 20 35 50 65 TJ, JUNCTION TEMPERATURE (C) 80 Q1 95 110 Q3 Q1
Figure 7. Typical Gate Trigger Current Versus Junction Temperature
Figure 8. Typical Gate Trigger Voltage Versus Junction Temperature
200 180 STATIC dv/dt (V/ mS) 160 140 800 V 120 100 VPK = 400 V TJ = 110C
130 RG MT1 = 510 120 STATIC dv/dt (V/ mS) TJ = 100C
110 110C
600 V
100
90 80 60 100 80 200 300 400 500 600 700 800 RGK, GATEMT1 RESISTANCE (OHMS) 900 1000 400 450 500 550 600 650 VPK, Peak Voltage (Volts)
120C
700
750
800
Figure 9. Typical Exponential Static dv/dt Versus GateMT1 Resistance, MT2(+)
Figure 10. Typical Exponential Static dv/dt Versus Peak Voltage, MT2(+)
130 120 VPK = 400 V STATIC dv/dt (V/ mS) STATIC dv/dt (V/ mS) 110 100 90 RG MT1 = 510 80 70 100 105 TJ, Junction Temperature (C) 110 600 V 800 V
350
300 TJ = 100C 250 110C 200
150
RG MT1 = 510
W
550 600 650 VPK, Peak Voltage (Volts) 700 750 800
100
400
450
500
Figure 11. Typical Exponential Static dv/dt Versus Junction Temperature, MT2(+)
Figure 12. Typical Exponential Static dv/dt Versus Peak Voltage, MT2()
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367

350 300 STATIC dv/dt (V/ mS) 250 200 150 RG MT1 = 510 100 50 100 105 TJ, Junction Temperature (C) 110 100 VPK = 400 V 250 600 V 800 V STATIC dv/dt (V/ S) 300 VPK = 400 V
600 V 200 800 V 150 TJ = 110C 100 200 300 400 500 600 700 800 RGK, GATEMT1 RESISTANCE (OHMS) 900 1000
Figure 13. Typical Exponential Static dv/dt Versus Junction Temperature, MT2()
(dv/dt)c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s)
Figure 14. Typical Exponential Static dv/dt Versus GateMT1 Resistance, MT2()
m
100 VPK = 400 V 90C 10
1 2 tw 6f ITM 1000
100C
f= tw (di/dt)c = VDRM
110C
1 5 10 15 20 25 30 (di/dt)c, CRITICAL RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
1N4007
CHARGE
200 V
NON-POLAR CL
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368
MAC9D, MAC9M, MAC9N

Preferred Device
Triacs

Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. Blocking Voltage to 800 Volts On-State Current Rating of 8.0 Amperes RMS at 100C Uniform Gate Trigger Currents in Three Quadrants High Immunity to dv/dt 500 V/s minimum at 125C Minimizes Snubber Networks for Protection Industry Standard TO-220AB Package High Commutating di/dt 6.5 A/ms minimum at 125C Device Marking: Logo, Device Type, e.g., MAC9D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC9D MAC9M MAC9N On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 100C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) 8.0 Amps 1 ITSM 80 Amps Value Unit Volts 4
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MT2 G
MT1
26 16 0.35 40 to +125 40 to +150
PIN ASSIGNMENT
369
Publication Order Number: MAC9/D
MAC9D, MAC9M, MAC9N

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage* (ITM = 11 A Peak) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 150 mA) Latching Current (VD = 24 V, IG = 50 mA) MT2(+), G(+); MT2(), G() MT2(+), G() Gate Trigger Voltage (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Gate NonTrigger Voltage (VD = 12 V, RL = 100 , TJ = 125C) MT2(+), G(+); MT2(+), G(); MT2(), G() VTM IGT 10 10 10 IH IL VGT 0.5 0.5 0.5 VGD 0.2 0.69 0.77 0.72 1.5 1.5 1.5 Volts 20 30 50 80 Volts 16 18 22 30 50 50 50 50 mA mA 1.2 1.6 Volts mA
Rate of Change of Commutating Current; See Figure 10. (VD = 400 V, ITM = 4.4 A, Commutating dv/dt = 18 V/s, Gate Open, TJ = 125C, f = 250 Hz, No Snubber) CL = 10 F LL = 40 mH Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) *Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 6.5 A/ms
dv/dt
500
V/s
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370
MAC9D, MAC9M, MAC9N

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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371
MAC9D, MAC9M, MAC9N

125 PAV, AVERAGE POWER (WATTS) TC, CASE TEMPERATURE (C) 120 = 120, 90, 60, 30 115 = 180 110 DC 105 12 DC 10 180 8 6 4 2 0 = 30 60 90 120
100
3 4 5 6 IT(RMS), RMS ON-STATE CURRENT (AMP)
2 3 4 5 6 IT(RMS), ON-STATE CURRENT (AMP)
100
TYPICAL AT TJ = 25C MAXIMUM @ TJ = 125C
0.1
10
0.01
0.1
10
100 t, TIME (ms)
1000
1 104
40 35 I H, HOLDING CURRENT (mA) 30 25 20 15 MT2 NEGATIVE 10 MT2 POSITIVE
0.1
0.5
3.5 4.5 1 1.5 2 2.5 3 4 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
5 50
30
10
110
130

372
Figure 5. Holding Current Variation
MAC9D, MAC9M, MAC9N

100 Q2 Q3 Q1 10 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 50
Q3 Q1 Q2
1 50
30
10
110
130
30
10
110
130
5000 (dv/dt) c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s) 4.5K 4K 3.5K 3K 2.5K 2K 1.5K 1K 500 0 1 MT2 POSITIVE 10 100 RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) 1000 MT2 NEGATIVE
100
TJ = 125C 10
100C
75C
tw VDRM
f=
1 2 tw
6f I (di/dt)c = TM 1000
1 10
15 20 25 30 35 40 45 50 55 60 (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 8. Critical Rate of Rise of Off-State Voltage (Exponential)
1N4007
+ 1N914 51 MT2 MT1 G
CHARGE
200 V
NON-POLAR CL
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373
MAC12D, MAC12M, MAC12N

Preferred Device
Triacs

Designed for high performance fullwave ac control applications where high noise immunity and commutating di/dt are required. Blocking Voltage to 800 Volts OnState Current Rating of 12 Amperes RMS at 70C Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3 High Immunity to dv/dt 250 V/s Minimum at 125C High Commutating di/dt 6.5 A/ms Minimum at 125C Industry Standard TO220 AB Package High Surge Current Capability 100 Amperes Device Marking: Logo, Device Type, e.g., MAC12D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC12D MAC12M MAC12N On-State RMS Current (All Conduction Angles; TC = 70C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.33 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM I2t PGM PG(AV) TJ Tstg 12 100 41 16 0.35 40 to +125 40 to +150 A A A2sec Watts Watts 1 C C 2 3 4 1 Value Unit Volts 4
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MT2 G
MT1
PIN ASSIGNMENT
374
September, 1999 Rev. 3

Characteristic Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Value 2.2 62.5 260 C Unit C/W
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 0.01 2.0 mA
ON CHARACTERISTICS
Peak OnState Voltage(1) (ITM =
"17 A) "150 mA)
VTM IGT
5.0 5.0 5.0
13 13 13 20 20 30 20 0.78 0.70 0.71
1.85 35 35 35 40 50 80 50
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Hold Current (VD = 12 V, Gate Open, Initiating Current = Latch Current (VD = 24 V, IG = 35 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G()
IH IL
mA mA
VGT 0.5 0.5 0.5 1.5 1.5 1.5
Volts
Rate of Change of Commutating Current (VD = 400 V, ITM = 4.4A, Commutating dv/dt = 18 V/s, Gate Open, TJ = 125C, f = 250 Hz, No Snubber) Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 200 mA/sec; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 6.5 A/ms
dv/dt di/dt
250
500
10
V/s A/s
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375

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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376

100 VGT, GATE TRIGGER VOLTAGE (VOLT) 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125 IGT, GATE TRIGGER CURRENT (mA) 1.10 1.00 Q3 0.90 Q1 0.80 Q2 0.70 0.60 0.50 0.40 40 25 10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125
Q3 Q2 Q1 10
1 40 25 10

100 100
HOLDING CURRENT (mA)
MT2 POSITIVE
LATCHING CURRENT (mA)
Q2 Q1 10 Q3
10 MT2 NEGATIVE
1 40 25 10
5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C)
110
125
1 40 25 10
95
110
125

125 TC, CASE TEMPERATURE (C) 120, 90, 60, 30 110 P(AV), AVERAGE POWER DISSIPATION (WATTS) 20 18 16 14 12 10 8 6 4 2 0 0
DC 180 120
95 180 80 DC 65 0 2 4 6 8 10 IT(RMS), RMS ON-STATE CURRENT (AMP) 12
60 30
90
2 4 6 8 10 IT(AV), AVERAGE ON-STATE CURRENT (AMP)
12
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377

100 I T, INSTANTANEOUS ON-STATE CURRENT (AMP) TYPICAL @ TJ = 25C r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1
MAXIMUM @ TJ = 125C
10
0.1
0.01
0.1
10 100 t, TIME (ms)
1000
10000

0.1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 5
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378
MAC12HCD, MAC12HCM, MAC12HCN

Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as motor controls, heating controls or dimmers; or wherever fullwave, silicon gatecontrolled devices are needed. Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3 High Commutating di/dt and High Immunity to dv/dt @ 125C Minimizes Snubber Networks for Protection Blocking Voltage to 800 Volts On-State Current Rating of 12 Amperes RMS at 80C High Surge Current Capability 100 Amperes Industry Standard TO-220AB Package for Ease of Design Glass Passivated Junctions for Reliability and Uniformity Device Marking: Logo, Device Type, e.g., MAC12HCD, Date Code
Rating Peak Repetitive Off-State Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC12HCD MAC12HCM MAC12HCN On-State RMS Current (All Conduction Angles; TC = 80C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.33 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM I2t PGM PG(AV) TJ Tstg 12 100 41 16 0.35 40 to +125 40 to +150 A A A2sec 1 Watts Watts C 2 3 4 TO220AB CASE 221A STYLE 4 Value Unit Volts
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MT2 G
MT1
PIN ASSIGNMENT
C Device MAC12HCD MAC12HCM MAC12HCN Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
379
September, 1999 Rev. 1
Publication Order Number: MAC12HC/D

OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 2.0
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 17 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 150 mA) Latch Current (VD = 12 V, IG = 10 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() VTM IGT 10 10 10 IH IL VGT 0.5 0.5 0.5 1.5 1.5 1.5 60 80 60 V 60 mA 50 50 50 mA 1.85 mA V
Rate of Change of Commutating Current (VD = 400 V, ITM = 4.4 A, Commutating dv/dt = 18 V/s, Gate Open, TJ = 125C, f = 250 Hz, CL = 10 F, LL = 40 mH, with Snubber) Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 200 mA/sec; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 15 A/ms
dv/dt
600
V/s
di/dt
10
A/s
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380

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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381

100 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) Q3 Q2 Q1 10 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 40 25 10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125 Q1 Q2 Q3
1 40 25 10
110
125

100 MT2 NEGATIVE HOLDING CURRENT (mA) LATCHING CURRENT (mA) 100
Q2 Q3 Q1
MT2 POSITIVE 10
10
1 40 25 10
110
125
1 40 25 10
95
110
125

125 TC, CASE TEMPERATURE (C) 120, 90, 60, 30 110 P(AV), AVERAGE POWER DISSIPATION (WATTS) 20 18 16 14 12 10 8 6 4 2 0 0
DC 180 120
95 180 80 DC 65 0 2 4 6 8 10 IT(RMS), RMS ON-STATE CURRENT (AMP) 12
60 30
90
2 4 6 8 10 IT(AV), AVERAGE ON-STATE CURRENT (AMP)
12
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382

MAXIMUM @ TJ = 125C
10
0.1
0.01
0.1
10 100 t, TIME (ms)
1000
10000

0.1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 5
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383
MAC12SM, MAC12SN
Preferred Device

Designed for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications. Sensitive Gate Allows Triggering by Microcontrollers and other Logic Circuits Blocking Voltage to 800 Volts On-State Current Rating of 12 Amperes RMS at 70C High Surge Current Capability 90 Amperes Rugged, Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design High Commutating di/dt 8.0 A/ms Minimum at 110C Immunity to dV/dt 15 V/sec Minimum at 110C Operational in Three Quadrants: Q1, Q2, and Q3 Device Marking: Logo, Device Type, e.g., MAC12SM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MAC12SM MAC12SN On-State RMS Current (All Conduction Angles; TC = 70C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.33 ms) Peak Gate Power (Pulse Width = 1.0 sec, TC = 70C) Average Gate Power (t = 8.3 msec, TC = 70C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) ITSM 12 90 Amps Amps 1 I2t PGM PG(AV) TJ Tstg 33 16 0.35 40 to 110 40 to 150 A2sec Watts Watt C C 2 3 4 Value Unit Volts 1 2 3
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MT2 G
MT1
PIN ASSIGNMENT
Device MAC12SM MAC12SN Package TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail
384
Publication Order Number: MAC12SM/D
MAC12SM, MAC12SN
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 17 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latching Current (VD = 12 V, IG = 5 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() VTM IGT 0.8 0.8 0.8 IH IL 2.0 2.0 2.0 VGT 0.45 0.45 0.45 0.68 0.62 0.67 1.5 1.5 1.5 3.0 5.0 3.0 15 20 15 V 1.0 1.5 2.5 2.7 2.5 5.0 5.0 5.0 10 mA mA 1.85 V mA
Critical Rate of Change of Commutating Current (VD = 400 V, ITM = 3.5 A, Commutating dV/dt = 10 V/s, Gate Open, TJ = 110C, f = 500 Hz, Snubber: Cs = 0.01 f, Rs = 15 ) Critical Rate of Rise of Off-State Voltage (VD = 67% VDRM, Exponential Waveform, RGK = 1 K, TJ = 110C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 1 A/sec; Igt = 100 mA; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 8.0 10 A/ms
dV/dt
15
40
V/s
di/dt
10
A/s
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385
MAC12SM, MAC12SN
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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386
MAC12SM, MAC12SN
IGT, GATE TRIGGER CURRENT (mA) 100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 0.90 0.85 0.80 Q3 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 40 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C) Q2 Q1
10 Q3
Q2
Q1 1
0.1 40 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C)
95
110
95 110

100 IL , LATCHING CURRENT (mA) 100 IH, HOLDING CURRENT (mA)
10
Q1 Q2 Q3
10
MT2 Positive 1 MT2 Negative
95
110
95 110

100 30, 60 90 90 80 180 70 DC 60 0 4 6 8 10 IT(RMS), RMS ON-STATE CURRENT (AMPS) 2 12
20 90 60
DC 180 120
15
10
30
5 0
2 6 8 12 4 10 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
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387
MAC12SM, MAC12SN
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) Typical @ TJ = 25C Maximum @ TJ = 110C Maximum @ TJ = 25C 10 r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 100 1
0.1
0.01 0.1
10 100 t, TIME (ms)
1000
10000

0.1 1.5 2.5 3.5 4.5 0.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
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388
MAC15 Series Triacs

Preferred Device

Designed primarily for full-wave ac control applications, such as solidstate relays, motor controls, heating controls and power supplies; or wherever fullwave silicon gate controlled solidstate devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied main terminal voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Three Modes (MAC15 Series) or Four Modes (MAC15A Series) Device Marking: Logo, Device Type, e.g., MAC15A6, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MAC15A6 MAC158, MAC15A8 MAC1510, MAC15A10 Peak Gate Voltage (Pulse Width 1.0 sec; TC = 90C) Symbol VDRM, VRRM 400 600 800 VGM IT(RMS) 10 15 Volts A Value Unit Volts
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MT2 G MT1
OnState Current RMS Full Cycle Sine Wave 50 to 60 Hz (TC = +90C) Circuit Fusing Consideration (t = 8.3 ms) Peak Nonrepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TC = +80C) Preceded and followed by rated current Peak Gate Power (TC = +80C, Pulse Width = 1.0 s) Average Gate Power (TC = +80C, t = 8.3 ms) Peak Gate Current (Pulse Width 1.0 sec; TC = 90C)
PIN ASSIGNMENT
1 I2t ITSM 93 150 A2s A 2 3 4 PGM PG(AV) IGM TJ Tstg 20 0.5 2.0 40 to +125 40 to +150 Watts Watts A C C Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Device MAC158 MAC1510 MAC15A6 MAC15A8 MAC15A10 Package TO220AB TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box 500/Box
Operating Junction Temperature Range Storage Temperature Range
389
Publication Order Number: MAC15A4/D
MAC15 Series
Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Value 2.0 62.5 260 Unit C/W C
OFF CHARACTERISTICS
Peak Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
"21 A Peak)
VTM IGT
1.3
1.6
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) A SUFFIX ONLY Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) A SUFFIX ONLY Gate NonTrigger Voltage (VD = 12 V, RL = 100 Ohms, TJ = 110C) MT2(+), G(+); MT2(), G(); MT2(+), G() MT2(), G(+) A SUFFIX ONLY Holding Current (VD = 12 Vdc, Gate Open, Initiating Current =
VGT VGD 0.2 0.2
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2 2 2 2.5 Volts
6.0 1.5
mA 40 s
"200 mA)
IH tgt
Turn-On Time (VD = Rated VDRM, ITM = 17 A) (IGT = 120 mA, Rise Time = 0.1 s, Pulse Width = 2 s)
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 21 A, Commutating di/dt = 7.6 A/ms, Gate Unenergized, TC = 80C) (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt(c) 5.0 V/s
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390
MAC15 Series
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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391
MAC15 Series
130 = 30 = 60 = 90 = 180 90 80 0 = CONDUCTION ANGLE 2 4 6 8 10 12 14 16 IT(RMS), RMS ONSTATE CURRENT (AMP) dc TJ 125 PAV, AVERAGE POWER (WATTS) 20 = 180 16 TJ 125 120 dc 90 60 30
TC, CASE TEMPERATURE (C)
120
110
12
100
8 = CONDUCTION ANGLE
4 0 0 2 4 6 8 10 12 14 16 IT(RMS), ONSTATE CURRENT (AMP)
1.8 VGT, GATE TRIGGER VOLTAGE (VOLTS) 1.6 1.4 1.2 1.0 0.8 QUADRANTS 0.6 0.4 60 40 20 1 2 3 0 20 40 60 80 100 120 140 QUADRANT 4 IGT, GATE TRIGGER CURRENT (mA) OFFSTATE VOLTAGE = 12 V
50 OFFSTATE VOLTAGE = 12 V 30 20
10 7.0 5.0 60
1 2 QUADRANT 3 4 40 20 0 20 40 60 80 100 120 140
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392
MAC15 Series
100 70 50 TJ = 25C 125C I H, HOLDING CURRENT (mA) 10 7.0 5.0 MAIN TERMINAL #2 POSITIVE 3.0 2.0 60 20 MAIN TERMINAL #1 POSITIVE GATE OPEN
30 20
i TM, INSTANTANEOUS FORWARD CURRENT (AMP)
10 7 5
40
20
20
40
60
80
100
120
140

3 2 300 1 0.7 0.5 TSM, PEAK SURGE CURRENT (AMP) 200
100 70 50 TC = 80C T f = 60 Hz Surge is preceded and followed by rated current
0.3 0.2
0.1 0.4
30 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 1 2 3 NUMBER OF CYCLES 5 7 10 vTM, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
1 r(t) TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.5
0.2 0.1 0.05
ZJC(t) = r(t) RJC
0.02 0.01 0.1
0.2
0.5
10
20
50
100
200
500
1k
2k
5k
10 k
t, TIME (ms)
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393
MAC15A6FP, MAC15A8FP, MAC15A10FP

Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as solid-state relays, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied main terminal voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC15A6FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MAC15A6FP MAC15A8FP MAC15A10FP On-State RMS Current (TC = +80C)(2) Full Cycle Sine Wave 50 to 60 Hz (TC = +95C) Peak Nonrepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TC = +80C) Preceded and followed by rated current Circuit Fusing (t = 8.3 ms) Peak Gate Power (TC = +80C, Pulse Width = 2.0 s) Average Gate Power (TC = +80C, t = 8.3 ms) Peak Gate Current (Pulse Width 1.0 sec; TC = 80C) Symbol VDRM, VRRM 400 600 800 IT(RMS) 15 12 ITSM 150 Amps Amps 1 2 3 Value Unit Volts
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ISOLATED TRIAC ( 15 AMPERES RMS 400 thru 800 VOLTS
MT2 G
MT1
I2t PGM PG(AV) IGM VGM V(ISO) TJ Tstg
93 20 0.5 2.0 10 1500 40 to +125 40 to +150
A2s Watts 1 Watt Amps Volts Volts 2 3
ISOLATED TO220 Full Pack CASE 221C STYLE 3
PIN ASSIGNMENT
v v
Peak Gate Voltage (Pulse Width 1.0 sec; TC = 80C) RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( )
Device MAC15A6FP Package ISOLATED TO220FP ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box 500/Box
Operating Junction Temperature Storage Temperature Range
C C
MAC15A8FP MAC15A10FP
(1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic body.
394
Publication Order Number: MAC15A6FP/D

Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Case to Sink Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RCS RJA TL Max 2.0 2.2 (typ) 60 260 Unit C/W C/W C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 21 A Peak
"
VTM IGT
1.3
1.6
Volts mA
Gate Trigger Current (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Main Terminal Voltage = Rated VDRM, RL = 100 , TJ = +110C) All 4 Quadrants Holding Current (Main Terminal Voltage = 12 Vdc, Gate Open, Initiating Current = 200 mA)
VGT VGD 0.2 IH
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2.0 2.0 2.0 2.5 Volts
6.0
40 mA
"
Turn-On Time (VD = Rated VDRM, ITM = 17 A, IGT = 120 mA, Rise Time = 0.1 s, Pulse Width = 2 s)
t gt
1.5
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, VRRM, ITM = 21 A, Commutating di/dt = 7.6 A/ms, Gate Unenergized, TC = 80C) (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt(c) 5.0 V/s
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395

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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396

130 30 60 90 125C 150 to 180 90 80 0 = CONDUCTION ANGLE 2 4 6 8 10 12 14 16 IT(RMS), RMS ONSTATE CURRENT (AMP) dc
IGTM , GATE TRIGGER CURRENT (NORMALIZED)
3 2 OFFSTATE VOLTAGE = 12 Vdc ALL MODES
120
110
1 0.7 0.5
100
0.3 60
40
20
20
40
60
80
100
120
140

PD(AV), AVERAGE POWER DISSIPATION (WATTS) 20 TJ = 125C 16 dc 12 8 = CONDUCTION ANGLE i F, INSTANTANEOUS FORWARD CURRENT (AMP) = 180 120 90 60 30 30 20 100 70 50
TJ = 25C 125C
4 0 0 2 4 6 8 10 12 14 16 IT(RMS), RMS ONSTATE CURRENT (AMP)
10 7 5 3 2
VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)
3 2 OFFSTATE VOLTAGE = 12 Vdc ALL MODES
1 0.7 0.5
1 0.7 0.5 0.3 0.2
0.3 60
40
20
20
40
60
80
100
120
140
0.1 0.4
0.8
1.2
1.6
2.4
2.8
3.2
3.6
4.4
vT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
Figure 3. Typical Gate Trigger Voltage http://onsemi.com

397

3 I H, HOLDING CURRENT (NORMALIZED) 2 I TSM, PEAK SURGE CURRENT (AMP) GATE OPEN APPLIES TO EITHER DIRECTION
300 200
1 0.7 0.5
100 70 50 TC = 80C f = 60 Hz SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 1 2 3 NUMBER OF CYCLES 5 7 10
0.3 60
40
20
20
40
60
80
100
120 140
30

r(t) TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 7. Maximum Nonrepetitive Surge Current
1 0.5
0.2 0.1 0.05
ZJC(t) = r(t) RJC
0.02 0.01 0.1
0.2
0.5
10
20
50
100
200
500
1k
2k
5k
10 k
t, TIME (ms)
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398
MAC15M, MAC15N
Preferred Device
Triacs

Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. Blocking Voltage to 800 Volts On-State Current Rating of 15 Amperes RMS at 80C Uniform Gate Trigger Currents in Three Modes High Immunity to dv/dt 250 V/s minimum at 125C Minimizes Snubber Networks for Protection Industry Standard TO-220AB Package High Commutating di/dt 9.0 A/ms minimum at 125C Operational in Three Quadrants, Q1, Q2, and Q3 Device Marking: Logo, Device Type, e.g., MAC15M, Date Code
Rating Peak Repetitive OffState Voltage(1) ( 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC15M MAC15N OnState RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 80C) Peak Non-repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 15 A 1 2 Value Unit Volts 4
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MT2 G MT1
ITSM
150
93 20 0.5 40 to +125 40 to +150
A2s Watts Watts C C 1 2 3 4
PIN ASSIGNMENT
Device Package TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail
MAC15M MAC15N
399
Publication Order Number: MAC15M/D
MAC15M, MAC15N
Symbol RJC RJA TL Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Value 2.0 62.5 260 Unit C/W C
Symbol Characteristic Min Typ Max Unit
OFF CHARACTERISTICS
IDRM, IRRM Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) mA TJ = 25C TJ = 125C 0.01 2.0
ON CHARACTERISTICS
VTM IGT Peak On-State Voltage(1) (ITM = 21 A Peak) Gate Trigger Current (Continuous DC) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Hold Current (VD = 12 Vdc, Gate Open, Initiating Current = 150 mA) Latching Current (VD = 24 V, IG = 35 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Volts 5.0 5.0 5.0 0.5 0.5 0.5 1.2 13 16 18 20 33 36 33 0.75 0.72 0.82 1.6 mA 35 35 35 mA 40 mA 50 80 50 Volts 1.5 1.5 1.5
IH IL
VGT
(di/dt)c Rate of Change of Commutating Current; See Figure 10. (VD = 400 V, ITM = 6.0 A, Commutating dv/dt = 24 V/s, Gate Open, TJ = 125C, f = 250 Hz, No Snubber) 9.0 CL = 10 F LL = 40 mH 250 V/s A/ms
dv/dt
Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C)
(1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.
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400
MAC15M, MAC15N
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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401
MAC15M, MAC15N
125 PAV, AVERAGE POWER (WATTS) 120 TC, CASE TEMPERATURE (C) 115 110 105 100 95 90 85 80 0 2 6 8 10 12 IT(RMS), RMS ON-STATE CURRENT (AMP) 4 14 16 = 180 = 30 and 60 = 90 = 120 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 IT(RMS), ON-STATE CURRENT (AMP) 14 16 = 30 DC 180 120 90 60
DC
100
TYPICAL AT TJ = 25C
MAXIMUM @ TJ = 125C
0.1
10
0.01
0.1
10
100 t, TIME (ms)
1000
1 104
40
I H, HOLD CURRENT (mA)
MT2 POSITIVE
MT2 NEGATIVE
0.1
0.5 1 1.5 2 2.5 3 3.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
5 40
10
110 125
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402
MAC15M, MAC15N
100 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) 1 OFF-STATE VOLTAGE = 12 V RL = 140
Q2
Q3 Q1
Q1 Q3 Q2
OFF-STATE VOLTAGE = 12 V RL = 140 1 40 10 20 50 80 TJ, JUNCTION TEMPERATURE (C) 110 125
0.5 40
10
+20 50 80 TJ, JUNCTION TEMPERATURE (C)
110
125

(dv/dt) c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s) dv/dt , CRITICAL RATE OF RISE OF OFF-STATE VOLTAGE (V/ s)
Figure 7. Gate Trigger Voltage versus Junction Temperature
5000 VD = 800 Vpk TJ = 125C
100
4K
3K
TJ = 125C 10
ITM tw VDRM f=
100C
75C
2K
1 2 tw
1K
6f I (di/dt)c = TM 1000
10
100 1000 RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS)
10000
10
20 30 40 50 60 70 80 90 100 (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 8. Critical Rate of Rise of OffState Voltage (Exponential)
1N4007
+ 1N914 51 MT2 MT1 G
CHARGE
200 V
NON-POLAR CL
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403

Preferred Device

Designed for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications. Sensitive Gate allows Triggering by Microcontrollers and other Logic Circuits High Immunity to dv/dt 25 V/ms minimum at 110_C High Commutating di/dt 8.0 A/ms minimum at 110_C Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design On-State Current Rating of 15 Amperes RMS at 70_C High Surge Current Capability 120 Amperes Blocking Voltage to 800 Volts Rugged, Economical TO220AB Package Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3 Device Marking: Logo, Device Type, e.g., MAC15SD, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60Hz, Gate Open) MAC15SD MAC15SM MAC15SN OnState RMS Current (Full Cycle Sine Wave, 60Hz, TJ = 70C) Peak Non-repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 70C) Average Gate Power (t = 8.3 ms, TC = 70C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) 15 A 1 2 ITSM 120 A 3 4 I2t PGM PG(AV) TJ Tstg 60 20 0.5 40 to +110 40 to +150 A2s Watts Watts C C Value Unit Volts 1 2 3
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MT2 G MT1
PIN ASSIGNMENT
Device MAC15SD MAC15SM MAC15SN Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
404
Publication Order Number: MAC15S/D

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM =
"21A) "150mA)
VTM IGT
.8 .8 .8
2.0 3.0 3.0 3.0 5.0 10 5.0 0.62 0.60 0.65
1.8 5.0 5.0 5.0 10 15 20 15
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100) MT2(+), G(+) MT2(+), G() MT2(), G() Hold Current (VD = 12 V, Gate Open, Initiating Current = Latching Current (VD = 24V, IG = 5mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100) MT2(+), G(+) MT2(+), G() MT2(), G()
IH IL
1.0 2.0 2.0 2.0
mA mA
VGT 0.45 0.45 0.45 1.5 1.5 1.5
Volts
Rate of Change of Commutating Current (VD = 400V, ITM = 3.5A, Commutating dv/dt = 10Vm/sec, Gate Open, TJ = 110_C, f= 500Hz, Snubber: CS = 0.01 mF, RS =15 , see Figure 15.) (di/dt)c 8.0 10 A/ms
Critical Rate of Rise of Off-State Voltage (VD = Rate VDRM, Exponential Waveform, RGK = 510 , TJ = 110_C)
dv/dt
25
75
V/ s
(1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.
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405

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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406

T C , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) 110 P(AV), AVERAGE POWER DISSIPATION (WATTS) 25
DC 180 120 90 60
100
20
a = 30 and 60
90

15
80
10
70
120 180
a = 30
5
60
14
DC 16
4 6 8 10 12 IT(RMS), RMS ONSTATE CURRENT (AMPS)
14
16

R(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED) I T, INSTANTANOUS ON-STATE CURRENT (AMPS)
100
Typical @ TJ = 25 C
10
Maximum @ TJ = 25 C
ZqJC(t) = RqJC(t) r(t) 0.1
Maximum @ TJ = 110C
0.1 0.5
1 1.5 2 2.5 3 3.5 4 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
4.5
0.01 0.1
10 100 t, TIME (ms)
1000
1@ 10 4
7 I L , LATCHING CURRENT (mA) 6 5 MT2 NEGATIVE 4 3 MT2 POSITIVE 2 1 40
9 8 7 Q1 6 5 Q3 4 3 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C) 95 110 2 40 25 10 5 20 35 50 65 TJ, JUNCTION TEMPERATURE (C) 80 95 110
Figure 5. Typical Holding Current Versus Junction Temperature
Figure 6. Typical Latching Current Versus Junction Temperature
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407

7 6 5 4 3 Q2 2 1 0 40 Q1 Q3 V GT, GATE TRIGGER VOLTAGE (VOLTS) IGT, GATE TRIGGER CURRENT (mA) 0.9 0.8 0.7 Q3 0.6 0.5 Q2 0.4 0.3 40 Q1
25
10
80
95
110
25
10
80
95
110
Figure 7. Typical Gate Trigger Current Versus Junction Temperature
Figure 8. Typical Gate Trigger Voltage Versus Junction Temperature
140 VPK = 400V 120 STATIC dv/dt (V/ mS) 600V TJ = 110C
110 100 STATIC dv/dt (V/ S) 90 80 70 120C 60 RG MT1 = 510 110C TJ = 100C
100 800V 80
W
700 750 800
60 100
200
300 400 500 600 700 800 RGK, GATEMT1 RESISTANCE (OHMS)
900
1000
50 400
450
500
550 600 650 VPK, Peak Voltage (Volts)
Figure 9. Typical Exponential Static dv/dt Versus GateMT1 Resistance, MT2(+)
Figure 10. Typical Exponential Static dv/dt Versus Peak Voltage, MT2(+)
110 100 STATIC dv/dt (V/ S) STATIC dv/dt (V/ S) 90 80 600V 70 60 50 40 100 800V RG MT1 = 510 VPK = 400V
180 160 140 120 100 80 60 40 105 110 115 TJ, Junction Temperature (C) 120 125 20 400 450 500 550 600 650 VPK, Peak Voltage (Volts) 700 750 800 RG MT1 = 510 120C TJ = 100C
110C
Figure 11. Typical Exponential Static dv/dt Versus Junction Temperature, MT2(+)
Figure 12. Typical Exponential Static dv/dt Versus Peak Voltage, MT2( )
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408

(dv/dt)c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s)
200
150 STATIC dv/dt (V/ S) 600V 100 800V 50 RG MT1 = 510 0 100 105 VPK = 400V
m
100
90C 10
1 2 tw 6f ITM 1000
100C
f= tw (di/dt)c = VDRM
110C
W
120 125
110 115 TJ, Junction Temperature (C)
1 5 10 15 20 25 (di/dt)c, CRITICAL RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 13. Typical Exponential Static dv/dt Versus Junction Temperature, MT2( )
1N4007
CHARGE
200 V
NON-POLAR CL
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409
MAC16CD, MAC16CM, MAC16CN

Preferred Device
Triacs

Designed primarily for full wave ac control applications, such as motor controls, heating controls or dimmers; or wherever fullwave, silicon gatecontrolled devices are needed. High Commutating di/dt and High Immunity to dv/dt @ 125C Minimizes Snubber Networks for Protection Blocking Voltage to 800 Volts On-State Current Rating of 16 Amperes RMS High Surge Current Capability 150 Amperes Industry Standard TO-220AB Package for Ease of Design Glass Passivated Junctions for Reliability and Uniformity Operational in Three Quadrants, Q1, Q2, and Q3 Device Marking: Logo, Device Type, e.g., MAC16CD, Date Code
Rating Peak Repetitive Off-State Voltage(1) (TJ = 40 to 125C) MAC16CD MAC16CM MAC16CN IT(RMS) Symbol VDRM, VRRM 400 600 800 16 A Value Unit Volts
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MT2 G
MT1
On-State RMS Current (Full Cycle Sine Wave 50 to 60 Hz; TC = 80C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.33 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range
150 93 20 0.5 40 to +125 40 to +150
A A2sec 1 Watts Watts C 2 3 4
PIN ASSIGNMENT
C Device MAC16CD MAC16CM MAC16CN Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
410
Publication Order Number: MAC16C/D

OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 2.0
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 21 A Peak) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 150 mA) Latching Current (VD = 12 V, IG = 35 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() VTM IGT 8.0 8.0 8.0 IH IL VGT 0.5 0.5 0.5 .75 .72 .82 1.5 1.5 1.5 25 40 24 50 80 50 V 20 50 mA 12 16 20 35 35 35 mA 1.2 1.6 mA V
Rate of Change of Commutating Current (VD = 400 V, ITM = 6.0 A, Commutating dv/dt = 24 V/s, Gate Open, TJ = 125C, f = 250 Hz, CL = 10 F, LL = 40 mH, with Snubber) Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 200 mA/sec; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 15 A/ms
dv/dt
600
V/s
di/dt
10
A/s
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411

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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412

100 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) Q3 Q2 1.10 1.00 0.90 Q1 0.80 0.70 Q2 0.60 0.50 0.40 40 25 10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125 Q3
10
Q1
1 40 25 10
110
125

100 100
Q2 HOLDING CURRENT (mA) MT2 NEGATIVE LATCHING CURRENT (mA)
Q1
10
MT2 POSITIVE
10
Q3
1 40 25 10
110
125
1 40 25 10
95
110
125

125 120 TC, CASE TEMPERATURE (C) 115 110 105 100 95 90 85 80 75 70 0 2 4 6 8 10 12 IT(RMS), RMS ON-STATE CURRENT (AMP) 14 16 120 180 DC 30 60 90 PAV, AVERAGE POWER (WATTS) 24 22 20 18 16 14 12 10 8 6 4 2 0
DC 180 120
30 0 2
60
90
4 6 8 10 12 14 IT(AV), AVERAGE ON-STATE CURRENT (AMP)
16
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413

100 I T, INSTANTANEOUS ON-STATE CURRENT (AMP) TYPICAL AT TJ = 25C r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0
MAXIMUM @ TJ = 125C
10
0.1
0.01
0.1
10 100 t, TIME (ms)
1000
10000

0.1 0 0.5 1 1.5 2 2.5 3 3.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 4
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414

Preferred Device
Triacs

Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. Blocking Voltage to 800 Volts On-State Current Rating of 16 Amperes RMS at 80C Uniform Gate Trigger Currents in Three Quadrants High Immunity to dv/dt 500 V/s minimum at 125C Minimizes Snubber Networks for Protection Industry Standard TO-220AB Package High Commutating di/dt 9.0 A/ms minimum at 125C Device Marking: Logo, Device Type, e.g., MAC16D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC16D MAC16M MAC16N On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 80C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) 16 Amps 1 ITSM 150 Amps Value Unit Volts 4
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MT2 G
MT1
93 20 0.5 40 to +125 40 to +150
PIN ASSIGNMENT
415
May, 2000 Rev. 2
Publication Order Number: MAC16D/D

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage* (ITM = 21 A Peak) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = 150 mA) Latching Current (VD = 24 V, IG = 50 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() VTM IGT 10 10 10 IH IL VGT 0.5 0.5 0.5 0.75 0.72 0.82 1.5 1.5 1.5 33 36 33 50 80 50 Volts 16 18 22 20 50 50 50 50 mA mA 1.2 1.6 Volts mA
Rate of Change of Commutating Current, See Figure 10. (VD = 400 V, ITM = 6.0 A, Commutating dv/dt = 24 V/s, Gate Open, TJ = 125C, f = 250 Hz, No Snubber) CL = 10 F LL = 40 mH Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) *Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 9.0 A/ms
dv/dt
500
V/s
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416

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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417

125 120 TC, CASE TEMPERATURE (C) 115 110 105 100 95 90 85 80 0 2 6 8 10 12 IT(RMS), RMS ON-STATE CURRENT (AMP) 4 14 16 = 180 = 30 and 60 = 90 = 120 20 PAV, AVERAGE POWER (WATTS) 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 IT(RMS), ON-STATE CURRENT (AMP) 14 16 = 30 DC 180 120 90 60
DC
100
TYPICAL AT TJ = 25C
MAXIMUM @ TJ = 125C
0.1
10
0.01
0.1
10
100 t, TIME (ms)
1000
1 104
40
I H, HOLD CURRENT (mA)
MT2 POSITIVE
MT2 NEGATIVE
0.1
0.5 1 1.5 2 2.5 3 3.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
5 40
10
110 125

418

100 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) 1 VD = 12 V RL = 100
Q2
Q3 Q1
Q1 Q3 Q2
VD = 12 V RL = 100 1 40 10 20 50 80 TJ, JUNCTION TEMPERATURE (C) 110 125
0.5 40
10
+20 50 80 TJ, JUNCTION TEMPERATURE (C)
110
125

5000 (dv/dt) c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s) VD = 800 Vpk TJ = 125C
100
4K
3K
TJ = 125C 10
ITM tw VDRM f=
100C
75C
2K
1 2 tw
1K
6f I (di/dt)c = TM 1000
10
100 1000 RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS)
10000
1 10
20 30 40 50 60 70 80 90 100 (di/dt)c, RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 8. Critical Rate of Rise of Off-State Voltage (Exponential Waveform)
1N4007
+ 1N914 51 MT2 MT1 G
CHARGE
200 V
NON-POLAR CL
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419

Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as motor controls, heating controls or dimmers; or wherever fullwave, silicon gatecontrolled devices are needed. High Commutating di/dt and High Immunity to dv/dt @ 125C Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3 Blocking Voltage to 800 Volts OnState Current Rating of 16 Amperes RMS at 80C High Surge Current Capability 150 Amperes Industry Standard TO220AB Package for Ease of Design Glass Passivated Junctions for Reliability and Uniformity Device Marking: Logo, Device Type, e.g., MAC16HCD, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC16HCD MAC16HCM MAC16HCN OnState RMS Current (Full Cycle Sine Wave 50 to 60 Hz; TC = 80C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TJ = 125C) Circuit Fusing Consideration(2) (t = 8.33 ms) Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Average Gate Power (t = 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) 16 A Value Unit Volts 4
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MT2 G
MT1
150 93 20 0.5 40 to +125 40 to +150
A A2sec 1 Watts Watts C 2 3 4
PIN ASSIGNMENT
C Device MAC16HCD MAC16HCM MAC16HCN Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
420
Publication Order Number: MAC16HC/D

OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 0.01 2.0 mA
ON CHARACTERISTICS
"21 A Peak) "150 mA)
VTM IGT
10 10 10
16 18 22 20 33 36 33 0.80 0.73 0.82
1.6 50 50 50 50 60 80 60
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() Holding Current (VD = 12 V, Gate Open, Initiating Current = Latch Current (VD = 12 V, IG = 50 mA) MT2(+), G(+) MT2(+), G() MT2(), G() Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G()
IH IL
mA mA
VGT 0.5 0.5 0.5 1.5 1.5 1.5
Volts
Rate of Change of Commutating Current (VD = 400 V, ITM = 6A, Commutating dv/dt = 20 V/s, CL = 10 F Gate Open, TJ = 125C, f = 250 Hz, with Snubber) LL = 40 mH Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of On-State Current IPK = 50 A; PW = 40 sec; diG/dt = 200 mA/sec; f = 60 Hz (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. (di/dt)c 15 A/ms
dv/dt di/dt
750
10
V/s A/s
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421

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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422

100 VGT, GATE TRIGGER VOLTAGE (VOLT) IGT, GATE TRIGGER CURRENT (mA) 1.10 Q3 1.00 Q1 0.90 0.80 0.70 0.60 0.50 0.40 40 25 10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125 Q2
Q3 Q2 Q1 10
1 40 25 10
110
125

100 100
HOLDING CURRENT (mA)
LATCHING CURRENT (mA)
MT2 NEGATIVE
Q2 Q1 Q3 10
10 MT2 POSITIVE
1 40 25 10
110
125
1 40 25 10
95
110
125

125 120 TC, CASE TEMPERATURE (C) 115 110 105 100 95 90 85 80 75 70 120 180 DC 60, 30 90 P(AV), AVERAGE POWER DISSIPATION (WATTS) 24 22 20 18 16 14 12 10 8 6 4 2 0
180 120
DC
60 30
90
4 6 8 10 12 14 IT(RMS), RMS ON-STATE CURRENT (AMP)
16
4 6 8 10 12 14 IT(AV), AVERAGE ON-STATE CURRENT (AMP)
16
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423

MAXIMUM @ TJ = 125C
10
0.1
0.01
0.1
10 100 t, TIME (ms)
1000
10000

0.1 0 0.5 1 1.5 2 2.5 3 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 3.5
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424
MAC97 Series Sensitive Gate Triacs

Designed for use in solid state relays, MPU interface, TTL logic and any other light industrial or consumer application. Supplied in an inexpensive TO92 package which is readily adaptable for use in automatic insertion equipment. OnePiece, InjectionMolded Package Blocking Voltage to 600 Volts Sensitive Gate Triggering in Four Trigger Modes (Quadrants) for all possible Combinations of Trigger Sources, and especially for Circuits that Source Gate Drives All Diffused and Glassivated Junctions for Maximum Uniformity of Parameters and Reliability Device Marking: Device Type, e.g., MAC97A4, Date Code
Rating Peak Repetitive Off-State Voltage (TJ = 40 to +110C)(1) Sine Wave 50 to 60 Hz, Gate Open MAC97A4 MAC97A6 MAC978, MAC97A8 On-State RMS Current Full Cycle Sine Wave 50 to 60 Hz (TC = +50C) Peak NonRepetitive Surge Current One Full Cycle, Sine Wave 60 Hz (TC = 110C) Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Voltage (t 2.0 ms, TC = +80C) Symbol VDRM, VRRM 200 400 600 IT(RMS) 0.6 Amp Value Unit Volts
Preferred Device
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TRIACS 0.8 AMPERE RMS 200 thru 600 VOLTS
MT2 G
MT1
ITSM
8.0
Amps
I2t VGM PGM PG(AV) IGM TJ Tstg
0.26 5.0 5.0 0.1 1.0 40 to +110 40 to +150
A2s Volts Watts Watt 1 2 3
PIN ASSIGNMENT
Main Terminal 1 Gate Main Terminal 2
v v v
Peak Gate Power (t 2.0 ms, TC = +80C) Average Gate Power (TC = 80C, t 8.3 ms)
Amp C C
Peak Gate Current (t 2.0 ms, TC = +80C) Operating Junction Temperature Range Storage Temperature Range
425
May, 2000 Rev. 6
MAC97 Series
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes for 10 Seconds Symbol RJC RJA TL Max 75 200 260 Unit C/W C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = +110C IDRM, IRRM 10 100 A A
ON CHARACTERISTICS
Peak OnState Voltage (ITM = .85 A Peak; Pulse Width
"
v 2.0 ms, Duty Cycle v 2.0%)
VTM IGT
1.9
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MAC978 Device MT2(+), G() MT2(), G() MT2(), G(+) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) MAC97A4,A6,A8 Devices
VGT VGD 0.1
10 10 10 10 5.0 5.0 5.0 7.0 Volts
Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) All Types MT2(+), G() All Types MT2(), G() All Types MT2(), G(+) All Types Gate NonTrigger Voltage (VD = 12 V, RL = 100 Ohms, TJ = 110C) All Four Quadrants Holding Current (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (VD = Rated VDRM, ITM = 1.0 A pk, IG = 25 mA)
.66 .77 .84 .88
2.0 2.0 2.0 2.5 Volts
IH tgt
1.5 2.0
10
mA s
Critical RateofRise of Commutation Voltage (VD = Rated VDRM, ITM = .84 A, Commutating di/dt = .3 A/ms, Gate Unenergized, TC = 50C) Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, TC = 110C, Gate Open, Exponential Waveform dv/dt(c) 5.0 V/s
dv/dt
25
V/s
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426
MAC97 Series
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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427
MAC97 Series
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (C) 110 I T(RMS) , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (C) 110
100 90 DC 80 70 60 50 40 30 0 = CONDUCTION ANGLE 0.1 0.2 0.3 180
T = 30
60 90 120
100 90 80 70 60 50 40 30 20 = CONDUCTION ANGLE 0 0.05 0.1 0.15 DC 180
T = 30
60 90
120
0.4
0.5
0.6
0.7
0.8
0.2
0.25
0.3
0.35
0.4
P(AV), MAXIMUM AVERAGE POWER DISSIPATION (WATTS)
1.2 1.0 0.8 = CONDUCTION ANGLE 0.6 120 DC 180
6.0 4.0 TJ = 110C 2.0 25C
1.0 90 ITM, INSTANTANEOUS ON-STATE CURRENT (AMP) 0.4 0.2 0 60 0.6 0.4
T = 30
0 0.1 0.2 0.3 0.4 0.5
0.6
0.7
0.8
0.2
0.1 0.06 0.04
0.02
0.01 0.006
0.4
1.2
2.0
2.8
3.6
4.4
5.2
6.0
VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
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428
MAC97 Series
R(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 I TSM , PEAK SURGE CURRENT (AMPS) 10
Z JC(t) = R JC(t) @ r(t) 0.1
5.0
3.0 2.0 TJ = 110C f = 60 Hz
CYCLE
Surge is preceded and followed by rated current. 1.0 1.0 2.0 3.0 5.0 10 30 50 100
0.01
0.1
1.0
10
100
1S103
1S104
t, TIME (ms)
NUMBER OF CYCLES

100 I GT , GATE TRIGGER CURRENT (mA) VGT, GATE TRIGGER VOLTAGE (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0 40 25 10 5 20 35 50 65 80 95 110
Q4 Q3 Q2 Q1
10
Q4 Q3 Q2
Q1
0.3 40 25
10
20
35
50
65
80
95
110

100 10
IL , LATCHING CURRENT (mA)
10
Q2
MT2 Negative 1 MT2 Positive
Q4 1 Q1
Q3
0 40 25
10
20
35
50
65
80
95
110
0.1 40 25
10
20
35
50
65
80
95
110
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429
MAC97 Series
1N4007
CS 1N914 51 MT2 MT1 G ADJUST FOR + dv/dt(c)
CHARGE
200 V
NON-POLAR CL
Note: Component values are for verification of rated (dv/dt)c. See AN1048 for additional information.
Figure 11. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Voltage (dv/dt)c
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430
MAC97 Series TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A H2B H2B

Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
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431
MAC97 Series
ORDERING & SHIPPING INFORMATION: MAC97 Series packaging options, Device Suffix
U.S. Europe Equivalent MAC97A6RL1, A8RL1 MAC978, MAC97A4,A6,A8 MAC97A6RLRF MAC97A8RLRP, MAC97A6RLRP MAC97A8RLRM Shipping Radial Tape and Reel (2K/Reel) Bulk in Box (5K/Box) Radial Tape and Reel (2K/Reel) Radial Tape and Fan Fold Box (2K/Box) Radial Tape and Fan Fold Box (2K/Box) Description of TO92 Tape Orientation Flat side of TO92 and adhesive tape visible N/A, Bulk Round side of TO92 and adhesive tape on reverse side Round side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible
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432
MAC210A8, MAC210A10 Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever fullwave silicon gate controlled solidstate devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied main terminal voltage with positive or negative gate triggering. Blocking Voltage to 600 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Four Modes (Quadrants) Device Marking: Logo, Device Type, e.g., MAC210A8, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MAC210A8 MAC210A10 OnState RMS Current (TC = +70C) Full Cycle Sine Wave 50 to 60 Hz Peak NonRepetitive Surge Current (One Full Cycle, Sine Wave 60 Hz, TC = +25C) Preceded and followed by rated current Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Power (TC = +70C, Pulse Width = 10 s) Average Gate Power (TC = +70C, t = 8.3 ms) Peak Gate Current (TC = +70C, Pulse Width = 10 s) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) 10 Amps 1 2 3 Value Unit Volts
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MT2 G MT1
ITSM
100
Amps
PIN ASSIGNMENT
I2t PGM PG(AV) IGM TJ Tstg 40 20 0.35 2.0 40 to +125 40 to +150 A2s Watts Watt Amps C C 1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Device MAC210A8 MAC210A10 Package TO220AB TO220AB Shipping 500/Box 500/Box
433
March, 2000 Rev. 1
MAC210A8, MAC210A10
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = +125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak On-State Voltage (ITM = 14 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle
"
p 2%)
VTM IGT
1.2
1.65
Volts mA
Gate Trigger Current (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Continuous dc) (Main Terminal Voltage = 12 V, RL = 100 , TJ = +125C) All Four Quadrants Holding Current (Main Terminal Voltage = 12 Vdc, Gate Open, Initiating Current = 200 mA, TC = +25C)
VGT VGD 0.2
12 12 20 35
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2.0 2.0 2.0 2.5 Volts
IH
6.0
50
mA
"
Turn-On Time (Rated VDRM, ITM = 14 A) (IGT = 120 mA, Rise Time = 0.1 s, Pulse Width = 2 s)
tgt
1.5
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 14 A, Commutating di/dt = 5.0 A/ms, Gate Unenergized, TC = 70C) Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Voltage Rise, Gate Open, TC = +70C) dv/dt(c) 5.0 V/s
dv/dt
100
V/s
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434
MAC210A8, MAC210A10
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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435
MAC210A8, MAC210A10
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) CONDUCTION ANGLE = 360 120 110 100 90 80 70 60 0 1.0 3.0 4.0 5.0 6.0 7.0 8.0 IT(RMS), RMS ON-STATE CURRENT (AMPS) 2.0 9.0 10.0 P (AV) , AVERAGE POWER DISSIPATION 130 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 IT(RMS), RMS ON-STATE CURRENT (AMPS) 9.0 10.0 CONDUCTION ANGLE = 360
100 IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) 50
100 ITSM , PEAK SURGE CURRENT (AMP) 80
20 10 5.0 TJ = 25C TJ = 125C
60 40 CYCLE TC = 70C f = 60 Hz Surge is preceded and followed by rated current 2.0 3.0 NUMBER OF CYCLES 5.0 7.0 10
20
2.0 1.0 0.5 0.2
1.0

0.1 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) VGT , GATE TRIGGER VOLTAGE (NORMALIZED)
2.0 OFF-STATE VOLTAGE = 12 Vdc ALL MODES
1.6
1.2
0.8
0.4 0 60
40
20 20 0 40 TC, CASE TEMPERATURE (C)
60
80
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436
MAC210A8, MAC210A10
I GT, GATE TRIGGER CURRENT (NORMALIZED) 2.0 IH , HOLDING CURRENT (NORMALIZED) OFF-STATE VOLTAGE = 12 Vdc ALL MODES 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 60 OFF-STATE VOLTAGE = 12 Vdc ALL MODES
1.6
1.2
0.8
0.4
0 60
40
20
20
40
60
80
40
20
20
40
60
80

1.0 0.5 0.2 0.1 0.05 ZJC(t) = r(t) RJC
0.02 0.01 0.1 0.2 0.5 1.0 2.0 5.0 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k t, TIME (ms)
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437
MAC210A8FP , MAC210A10FP Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied main terminal voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC210A8FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC210A8FP MAC210A10FP On-State RMS Current (TC = +70C)(2) Full Cycle Sine Wave 50 to 60 Hz Peak Nonrepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TC = +70C) Preceded and followed by rated current Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (TC = +70C, Pulse Width = 10 s) Average Gate Power (TC = +70C, t = 8.3 ms) Peak Gate Current (TC = +70C, Pulse Width = 10 sec) RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( ) Symbol VDRM, VRRM 600 800 IT(RMS) ITSM 10 100 Amps Amps 1 2 3 Value Unit Volts
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MT2 G
MT1
I2t PGM PG(AV) IGM V(ISO) TJ Tstg
40 20 0.35 2.0 1500 40 to +125 40 to +150
A2s Watts
PIN ASSIGNMENT
Watt Amps Volts C C 1 2 3 Main Terminal 1 Main Terminal 2 Gate
Device MAC210A8FP Package ISOLATED TO220FP Shipping 500/Box 500/Box
MAC210A10FP ISOLATED TO220FP
438
MAC210A8FP, MAC210A10FP
OFF CHARACTERISTICS
ON CHARACTERISTICS
"
p 2%)
VTM IGT
1.2
1.65
Volts mA
Gate Trigger Current (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Continuous dc) (Main Terminal Voltage = 12 V, RL = 100 , TJ = +125C) All Four Quadrants Holding Current (Main Terminal Voltage = 12 Vdc, Gate Open, Initiating Current = 200 mA)
VGT VGD 0.2 IH
12 12 20 35
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2.0 2.0 2.0 2.5 Volts
6.0
50 mA
"
Turn-On Time (Rated VDRM, ITM = 14 A, IGT = 120 mA, Rise Time = 0.1 s, Pulse Width = 2 s)
t gt
1.5
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 14 A, Commutating di/dt = 5.0 A/ms, Gate Unenergized, TC = +70C) Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Voltage Rise, Gate Open, TC = +70C) dv/dt(c) 5.0 V/s
dv/dt
100
V/s
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439
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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440
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) PD(AV), AVERAGE POWER DISSIPATION (WATTS) 130 120 110 100 90 80 70 60 0 1 3 4 5 6 7 8 IT(RMS), RMS ONSTATE CURRENT (AMPS) 2 9 10 CONDUCTION ANGLE = 360 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 IT(RMS), RMS ONSTATE CURRENT (AMPS) 9 10 CONDUCTION ANGLE = 360
100 i T, INSTANTANEOUS ONSTATE CURRENT (AMPS) 50 20 10 5 2 1 0.5 0.2 TJ = 25C TJ = 125C ITSM , PEAK SURGE CURRENT (AMP)
100
80
60 CYCLE TC = 70C f = 60 Hz SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 1 2 3 5 NUMBER OF CYCLES 7 10
40
20
VGT, GATE TRIGGER VOLTAGE (NORMALIZED)
0.1 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
2 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
1.6
1.2
0.8
0.4
0 60
40
60
80
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441
I GT, GATE TRIGGER CURRENT (NORMALIZED) 2 I H , HOLDING CURRENT (NORMALIZED) MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS 2.8 2.4 2 1.6 1.2 0.8 0.4 0 60 40 20 0 20 40 TC, CASE TEMPERATURE (C) 60 80 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
1.6
1.2
0.8
0.4
0 60
40
60
80

1 0.5
0.2 0.1 0.05
ZJC(t) = r(t) RJC
0.02 0.01 0.1
0.2
0.5
20 50 t, TIME (ms)
100
200
500
1k
2k
5k
10 k
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442
MAC212A6FP , MAC212A8FP , MAC212A10FP

Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied main terminal voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC212A6FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave, 50 to 60 Hz, Gate Open) MAC212A6FP MAC212A8FP MAC212A10FP On-State RMS Current (TC = +85C)(2) Full Cycle Sine Wave 50 to 60 Hz Peak Nonrepetitive Surge Current (One Full Cycle, Sine Wave, 60 Hz, TC = +85C) Preceded and followed by rated current Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (TC = +85C, Pulse Width = 10 s) Average Gate Power (TC = +85C, t = 8.3 ms) Peak Gate Current (TC = +85C, Pulse Width = 10 s) RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( ) Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM 12 100 Amps Amps Value Unit Volts
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MT2 G
MT1
1 2 3
40 20 0.35 2.0 1500 40 to +125 40 to +150
A2s Watts Watt Amps Volts C C 1 2 3
PIN ASSIGNMENT
Device MAC212A6FP MAC212A8FP Package ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box 500/Box
MAC212A10FP ISOLATED TO220FP
443

OFF CHARACTERISTICS
ON CHARACTERISTICS
"
p 2%)
VTM IGT
1.3
1.75
Volts mA
VGT VGD 0.2 IH
12 12 20 35
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2.0 2.0 2.0 2.5 Volts
6.0
50 mA
"
t gt
1.5
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms, Gate Unenergized, TC = +85C) Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Voltage Rise, Gate Open, TC = +85C) dv/dt(c) 5.0 V/s
dv/dt
100
V/s
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444

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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445

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( 125 PD(AV), AVERAGE POWER DISSIPATION (WATTS) 28 24 20 = CONDUCTION ANGLE 16 12 8.0 4.0 0 0 2.0 4.0 6.0 8.0 10 12 IT(RMS), RMS ONSTATE CURRENT (AMPS) 14 dc = 180 90 60 30
115
105 85 = CONDUCTION ANGLE
= 30 60 90 180 dc
95
75
2.0
4.0 6.0 8.0 10 12 IT(RMS), RMS ONSTATE CURRENT (AMPS)
14
100 i T, INSTANTANEOUS ONSTATE CURRENT (AMPS) 50 20 10 5 2 1 0.5 0.2 0.1 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 vT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) VGT, GATE TRIGGER VOLTAGE (NORMALIZED) TJ = 25C TJ = 125C ITSM , PEAK SURGE CURRENT (AMP)
100
80
60 CYCLE TC = 70C f = 60 Hz SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 1 2 3 5 NUMBER OF CYCLES 7 10
40
20
2 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
1.6
1.2
0.8
0.4
0 60
40
60
80
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446

I GT, GATE TRIGGER CURRENT (NORMALIZED) 2 I H , HOLDING CURRENT (NORMALIZED) MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS 2.8 2.4 2 1.6 1.2 0.8 0.4 0 60 40 20 0 20 40 TC, CASE TEMPERATURE (C) 60 80 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
1.6
1.2
0.8
0.4
0 60
40
60
80
r(t), TRANSIENT THERMAL RESISTANCE(NORMALIZED)
1 0.5
0.2 0.1 0.05
ZJC(t) = r(t) RJC
0.02 0.01 0.1
0.2
0.5
20 50 t, TIME (ms)
100
200
500
1k
2k
5k
10 k
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447
MAC212A8, MAC212A10
Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied anode voltage with positive or negative gate triggering. Blocking Voltage to 800 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Four Modes Device Marking: Logo, Device Type, e.g., MAC212A8, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MAC212A8 MAC212A10 On-State RMS Current (TC = +85C) Full Cycle Sine Wave 50 to 60 Hz Peak Nonrepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TC = +25C) Preceded and followed by rated current Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Power (TC = +85C, Pulse Width = 10 s) Average Gate Power (TC = +85C, t = 8.3 ms) Peak Gate Current (TC = +85C, Pulse Width = 10 s) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) ITSM 12 100 Amp Amp 1 2 3 Value Unit Volts
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MT2 G MT1
40 20 0.35 2.0 40 to +125 40 to +150
A2s 1 Watts Watt Amp 2 3 4
PIN ASSIGNMENT
C C Device MAC212A8 MAC212A10 Package TO220AB TO220AB Shipping 500/Box 500/Box
448
March, 2000 Rev. 1
MAC212A8, MAC212A10
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage ITM = 17 A Peak; Pulse Width = 1 to 2 ms, Duty Cycle
"
p 2%
VTM IGT
1.3
1.75
Volts mA
VGT VGD 0.2 IH
12 12 20 35
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2.0 2.0 2.0 2.5 Volts
6.0
50 mA
"
tgt
1.5
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 17 A, Commutating di/dt = 6.1 A/ms, Gate Unenergized, TC = +85C) Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Voltage Rise, Gate Open, TC = +85C) dv/dt(c) 5.0 V/s
dv/dt
100
V/s
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449
MAC212A8, MAC212A10
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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450
MAC212A8, MAC212A10
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) PD(AV), AVERAGE POWER DISSIPATION (WATT) 125 28 24 20 16 12 8.0 4.0 0 0 2.0 4.0 6.0 8.0 10 12 14 IT(RMS), RMS ON-STATE CURRENT (AMP) = CONDUCTION ANGLE dc = 180 90 60 30
115 = 30 85 = CONDUCTION ANGLE 60 90 180 dc
105
95
75 0 2.0 4.0 6.0 8.0 10 12 14 IT(RMS), RMS ON-STATE CURRENT (AMP)
100 IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) 50 20 10 5.0 TJ = 25C TJ = 125C
100 ITSM , PEAK SURGE CURRENT (AMP) 80 60 CYCLE TC = 70C f = 60 Hz Surge is preceded and followed by rated current 2.0 3.0 NUMBER OF CYCLES 5.0 7.0 10
40
20 0 1.0
2.0 1.0 0.5
0.2 0.1 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 VGT , GATE TRIGGER VOLTAGE (NORMALIZED) VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS) 2.0
Figure 3. Maximum OnState Voltage Characteristics
1.6
MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
1.2
0.8
0.4 0 60
40
20
20
40
60
80
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451
MAC212A8, MAC212A10
I GT, GATE TRIGGER CURRENT (NORMALIZED) 2.0 IH , HOLDING CURRENT (NORMALIZED) MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 60 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
1.6
1.2
0.8
0.4
0 60
40
20
20
40
60
80
40
20
20
40
60
80

1.0 0.5 0.2 0.1 0.05 ZJC(t) = r(t) RJC
0.02 0.01 0.1 0.2 0.5 1.0 2.0 5.0 20 50 100 200 500 1.0 k 2.0 k 5.0 k 10 k t, TIME (ms)
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452
Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies. Blocking Voltage to 800 Volts Glass Passivated Junctions for Greater Parameter Uniformity and Stability Isolated TO220 Type Package for Ease of Mounting Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC218A6FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MAC218A6FP MAC218A10FP On-State RMS Current (TC = +80C)(2) Full Cycle Sine Wave 50 to 60 Hz Peak NonRepetitive Surge Current (One Full Cycle, 60 Hz, TC = +80C) Preceded and followed by rated current Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Power (TC = +80C, Pulse Width = 10 s) Average Gate Power (TC = +80C, t = 8.3 ms) Peak Gate Current (TC = +80C, Pulse Width = 10 s) RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( ) Symbol VDRM, VRRM 400 800 IT(RMS) ITSM 8.0 100 Amps Amps Value Unit Volts
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MT2 G
MT1
40 16 0.35 4.0 1500 40 to +125 40 to +150
A2s Watts Watt Amps 1 Volts C C 2 3
1 2 3
PIN ASSIGNMENT
Device MAC218A6FP MAC218A10FP Package ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box
453
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25 TJ = 125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 11.3 A Peak)
"
VTM IGT
1.7
2.0
Volts mA
Gate Trigger Current (Continuous dc) (V D = 12 Vdc, R L = 100 ) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Continuous dc) (Main Terminal Voltage = 12 V, RL = 100 , TJ = +125C) All Four Quadrants Holding Current (VD = 12 Vdc, Gate Open, Initiating Current =
VGT VGD 0.2
50 50 50 75 Volts
0.9 0.9 1.1 1.4
2.0 2.0 2.0 2.5 Volts
"200 mA)
IH
50
mA
Critical Rate of Rise of Commutating OffState Voltage (VD = Rated VDRM, ITM = 11.3 A, Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80C) Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Voltage Rise, Gate Open, TJ = 125C) (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt(c) 5.0 V/s
dv/dt
100
V/s
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454
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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455
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) 125 PD(AV), AVERAGE POWER DISSIPATION (WATTS) 10
115
105
95
85
75
0 0 1 2 3 4 5 6 IT(RMS), RMS ONSTATE CURRENT (AMPS) 7 8

VGT, NORMALIZED GATE TRIGGER VOLTAGE (VOLTS)
I GT, NORMALIZED GATE TRIGGER CURRENT (mA)
5 MAIN TERMINAL VOLTAGE = 12 V 3 2
1.8 MAIN TERMINAL VOLTAGE = 12 V 1.6 1.4 QUADRANT 4 1.2 1 0.8 QUADRANTS 0.6 0.4 60 40 20 1 2 3 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140
1 0.7 QUADRANT
1 2 3 4 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140
0.5 60 40
20
Figure 3. Normalized Gate Trigger Current
Figure 4. Normalized Gate Trigger Voltage
I H , NORMALIZED HOLDING CURRENT (mA)
2 GATE OPEN MAIN TERMINAL #1 POSITIVE
1 0.7 0.5 MAIN TERMINAL #2 POSITIVE 0.3 0.2 60 40
20
20
40
60
80
100
120
140
Figure 5. Normalized Holding Current
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456
MAC223A6, MAC223A8, MAC223A10

Preferred Device
Triacs

Designed primarily for full-wave ac control applications such as lighting systems, heater controls, motor controls and power supplies; or wherever fullwave silicongatecontrolled devices are needed. OffState Voltages to 800 Volts All Diffused and Glass Passivated Junctions for Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Thermal Resistance and High Heat Dissipation Gate Triggering Guaranteed in Four Modes Device Marking: Logo, Device Type, e.g., MAC223A6, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave 50 to 60 Hz, Gate Open) MAC223A6 MAC223A8 MAC223A10 OnState Current RMS Full Cycle Sine Wave 50 to 60 Hz (TC = 80C) Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = 80C) Preceded and followed by rated current Circuit Fusing (t = 8.3 ms) Peak Gate Current (t 2.0 sec; TC = +80C) Symbol VDRM, VRRM 400 600 800 IT(RMS) 25 A Value Unit Volts 4
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MT2 G MT1
ITSM
250
I2t IGM VGM PGM PG(AV) TJ Tstg
260 2.0
A2s A Volts Watts 1 2
PIN ASSIGNMENT
v v v
Peak Gate Voltage (t 2.0 sec; TC = +80C) Peak Gate Power (t 2.0 sec; TC = +80C) Average Gate Power (TC = 80C, t = 8.3 ms) Operating Junction Temperature Range Storage Temperature Range Mounting Torque
"10
20 0.5 40 to 125 40 to 150 8.0
3 4
Watts Device C C in. lb. MAC223A6 MAC223A8 MAC223A10 Package TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box
457
Publication Order Number: MAC223A/D

Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Value 1.2 60 260 Unit C/W C/W C
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise indicated; Electricals apply in both directions)
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak OnState Voltage (ITM = Duty Cycle 2%)
"35 A Peak, Pulse Width v 2 ms,
VTM IGT
1.4
1.85
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(), G(); MT(+), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(), G(); MT(+), G() MT2(), G(+) Gate Nontrigger Voltage (VD = 12 V, TJ = 125C, RL = 100 ) All Quadrants Holding Current (VD = 12 Vdc, Gate Open, Initiating Current =
VGT VGD 0.2
20 30
50 75 Volts
1.1 1.3 0.4 10 1.5
2.0 2.5 Volts 50 mA s
"200 mA)
IH tgt
TurnOn Time (VD = Rated VDRM, ITM = 35 A Peak, IG = 200 mA)
Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, TC = 125C) Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 35 A Peak, Commutating di/dt = 12.6 A/ms, Gate Unenergized, TC = 80C) dv/dt dv/dt(c) 40 5.0 V/s V/s
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458

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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459

PD, AVERAGE POWER DISSIPATION (WATTS) TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) 125 115 105 95 85 75 40
30
20
10
0 0 0 5.0 10 15 20 25 IT(RMS), RMS ONSTATE CURRENT (AMPS) 5.0 10 15 20 IT(RMS), RMS ONSTATE CURRENT (AMPS) 25
NORMALIZED GATE CURRENT
3.0 2.0 1.0 0.5 0.3 0.2 0.1 60 40 VD = 12 V RL = 100
NORMALIZED GATE VOLTAGE
3.0 2.0 1.0 0.5 0.3 0.2 0.1 60 40 VD = 12 V RL = 100
20
120
140
20
120
140

i TM, INSTANTANEOUS ONSTATE CURRENT (AMPS)
NORMALIZED HOLD CURRENT
200 100 50 10 5.0 1.0 0.5 0.1 TJ = 25C
2.0 1.0 0.5 0.3 0.2 0.1 60 40
ITM = 200 mA Gate Open
20
20
40
60
80
100
120
140
1.0
2.0
3.0
4.0
VTM, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
Figure 5. Typical Hold Current
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460
MAC223A6FP , MAC223A8FP , MAC223A10FP

Preferred Device
Triacs

Designed primarily for full-wave ac control applications, such as lighting systems, heater controls, motor controls and power supplies; or wherever fullwave silicongatecontrolled devices are needed. OffState Voltages to 800 Volts All Diffused and Glass Passivated Junctions for Parameter Uniformity and Stability Small, Rugged Thermowatt Construction for Thermal Resistance and High Heat Dissipation Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC223A6FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MAC223A6FP MAC223A8FP MAC223A10FP On-State RMS Current (TC = +80C)(2) Full Cycle Sine Wave 50 to 60 Hz Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = 80C) Preceded and followed by rated current Circuit Fusing (t = 8.3 ms) Peak Gate Power (t 2 sec; TC = +80C) Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM 25 250 Amps Amps 1 2 3 Value Unit Volts
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MT2 G
MT1
I2t PGM PG(AV) IGM VGM V(ISO) TJ Tstg
260 20 0.5 2.0
A2s Watts Watt 1 Amps Volts Volts C C in. lb. 2 3
p p p
Average Gate Power (t = 8.3 ms; TC = +80C) Peak Gate Current (t 2 sec; TC = +80C) Peak Gate Voltage (t 2 sec; TC = +80C) RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( )
PIN ASSIGNMENT
"10
1500 40 to +125 40 to +150 8.0
Device MAC223A6FP MAC223A8FP MAC223A10FP Package ISOLATED TO220FP ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box 500/Box
Operating Junction Temperature Storage Temperature Range Mounting Torque
461

Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Case to Sink Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RCS RJA TL Max 1.2 2.2 60 260 Unit C/W C/W C/W C
OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak On-State Voltage (ITM = 35 A Peak, Pulse Width
"
p 2 ms; Duty Cycle p 2%)
VTM IGT
1.4
1.85
Volts mA
Gate Trigger Current (Continuous dc) (V D = 12 V, R L = 100 ) MT2(+), G(+); MT2(), G(); MT2(+), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (V D = 12 V, R L = 100 ) MT2(+), G(+); MT2(), G(); MT2(+), G() MT2(), G(+) Gate Nontrigger Voltage (VD = 12 V, TJ = 125C, RL = 100 ) All Quadrants Holding Current (VD = 12 Vdc, Gate Open, Initiating Current =
VGT VGD 0.2
20 30
50 75 Volts
1.1 1.3 0.4 10 1.5
2.0 2.5 Volts 50 mA s
"200 mA)
IH t gt
Gate Controlled TurnOn Time (VD = Rated VDRM, ITM = 35 A Peak, IG = 200 mA)
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, TC = 125C) Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 35 A Peak, Commutating di/dt = 12.6 A/ms, Gate Unenergized, TC = 80C) dv/dt dv/dt(c) 40 5.0 V/s V/s
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462

Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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463

TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) PD(AV) , AVERAGE POWER DISSIPATION (WATTS) 125 115 105 95 85 75 40
30
20
10
0 0 5 10 15 20 25 IT(RMS), RMS ONSTATE CURRENT (AMPS)
10
15
20
25
3 2 1 0.5 0.3 0.2 0.1 60
VD = 12 V RL = 100
3 2 1 0.5 0.3 0.2 0.1 60
VD = 12 V RL = 100
40
20
20
40
60
80
100
120
140
40
20
20
40
60
80
100
120
140
i TM , INSTANTANEOUS ONSTATE CURRENT (AMPS)
200 100 50 10 5 1 0.5 0.1 0 1 2 3 4 vTM, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) TJ = 25C
2 1 0.5 0.3 0.2 0.1 60
ITM = 200 mA GATE OPEN
40
20
20
40
60
80
100
120
140
Figure 5. Typical Hold Current
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464
MAC224A Series Triacs

Preferred Device

Designed primarily for full-wave ac control applications such as lighting systems, heater controls, motor controls and power supplies. Blocking Voltage to 800 Volts All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability Gate Triggering Guaranteed in Four Modes High Current and Surge Ratings Device Marking: Logo, Device Type, e.g., MAC224A4, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave 50 to 60 Hz, Gate Open) MAC224A4 MAC224A6 MAC224A8 MAC224A10 OnState RMS Current (TC = 75C)(2) (Full Cycle Sine Wave 50 to 60 Hz) Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TJ = 125C) Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Current (Pulse Width 2.0 sec; TC = 75C) Symbol VDRM, VRRM 200 400 600 800 IT(RMS) 40 A 1 ITSM I2t IGM VGM PGM PG(AV) TJ Tstg 350 500 A A2s A Value Unit Volts
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MT2 G MT1
v v v
"2.0 "10
20 0.5 40 to 125 40 to 150 8.0
PIN ASSIGNMENT
Volts Watts Watts C C in. lb. 1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Peak Gate Voltage (Pulse Width 2.0 sec; TC = 75C) Peak Gate Power (Pulse Width 2.0 sec; TC = 75C) Average Gate Power (TC = 75C, t = 8.3 ms) Operating Junction Temperature Range Storage Temperature Range Mounting Torque
Device MAC224A4 MAC224A6 MAC224A8 MAC224A10 Package TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box
(1) VDRM, VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) This device is rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device is to be used at high sustained currents. (See Figure 1 for maximum case temperatures.)
465
MAC224A Series
Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Value 1.0 60 260 Unit C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak OnState Voltage (ITM = 56 A Peak, Pulse Width
"
p 2 ms, Duty Cycle p 2%)
VTM IGT
1.4
1.85
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(+), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(), G(); MT(+), G() MT2(), G(+) Gate Non-Trigger Voltage (VD = 12 V, TJ = 125C, RL = 100 ) All Quadrants Holding Current (VD = 12 Vdc, Gate Open, Initiating Current =
VGT VGD 0.2
25 40
50 75 Volts
1.1 1.3
2.0 2.5 Volts
"200 mA)
IH tgt
30 1.5
75
mA s
Gate Controlled Turn-On Time (VD = Rated VDRM, ITM = 56 A Peak, IG = 200 mA)
Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, TC = 125C) Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 56 A Peak, Commutating di/dt = 20.2 A/ms, Gate Unenergized, TC = 75C) dv/dt dv/dt(c) 50 5.0 V/s V/s
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466
MAC224A Series
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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467
MAC224A Series
T C, MAXIMUM ALLOWABLE CASE TEMPERATURE ( C) PD , AVERAGE POWER DISSIPATION (WATTS) 0 5.0 10 15 20 25 30 35 40 125 120 115 110 105 100 95 90 85 80 75 IT(RMS), RMS ON-STATE CURRENT (AMPS)* 60 54 48 42 36 30 24 18 12 6.0 0 0 5.0 10 15 20 25 30 35 40 IT(RMS), RMS ON-STATE CURRENT (AMPS)*
*This device is rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device is to be used at high sustained currents.
3.0 2.0 1.0 0.5 0.3 0.2 0.1 60
3.0 2.0 1.0 0.5 0.3 0.2 0.1 60 VD = 12 V RL = 100
VD = 12 V RL = 100
40
20
20
40
60
80
100
120
140
40
20
20
40
60
80
100
120 140
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468
MAC224A Series
I TM, INSTANTANEOUS ON-STATE CURRENT (AMPS) 1000
2.0 1.0 0.5 0.3 0.2 0.1 60 40 20 0 20
100 TJ = 25C 10
ITM = 200 mA Gate Open
1.0 0 1.0 2.0 3.0 VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
40
60
80
100
120
140
1 0.5 0.2 0.1 0.05 0.02 0.01 0.1
ZJC(t) = r(t) RJC
0.2
0.5
20
50
100
200
500
1k
2k
5k
10 k
t, TIME (ms)
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469
MAC228A Series Sensitive Gate Triacs

Designed primarily for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications. Sensitive Gate Triggering in 3 Modes for AC Triggering on Sinking Current Sources Four Mode Triggering for Drive Circuits that Source Current All Diffused and GlassPassivated Junctions for Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance and High Heat Dissipation Center Gate Geometry for Uniform Current Spreading Device Marking: Logo, Device Type, e.g., MAC228A4, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MAC228A4 MAC228A6 MAC228A8 MAC228A10 On-State RMS Current (TC = 80C) Full Cycle Sine Wave 50 to 60 Hz Peak NonRepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Current (t 2 s, TC = 80C) Symbol VDRM, VRRM 200 400 600 800 IT(RMS) ITSM 8.0 80 Amps Amps Value Unit Volts 4
Preferred Device
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MT2 G MT1
I2t IGM VGM PGM PG(AV) TJ Tstg
26
A2s 1 Amps Volts Watts 2 3 4
PIN ASSIGNMENT
v v v v
"2.0 "10
20 0.5 40 to 110 40 to 150 8.0
Peak Gate Voltage (t 2 s, TC = 80C) Peak Gate Power (t 2 s, TC = 80C) Average Gate Power (t 8.3 ms, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Mounting Torque
Watt C C in. lb. Device MAC228A4 MAC228A6 MAC228A8 MAC228A10 Package TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box
470
MAC228A Series
OFF CHARACTERISTICS
ON CHARACTERISTICS
"
v 2 ms, Duty Cycle v 2%)
VTM IGT
1.8
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Continuous dc) (VD = 12 V, TC = 110C, RL = 100 ) All Four Quadrants Holding Current (VD = 12 Vdc, Initiating Current =
VGT VGD 0.2
5.0 10 Volts
2.0 2.5 Volts
"200 mA, Gate Open)
IH tgt
1.5
15
mA s
GateControlled TurnOn Time (VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)
Critical Rate of Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, TC = 110C) Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 11.3 A, Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80C) dv/dt dv/dt(c) 25 5.0 V/s V/s
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471
MAC228A Series
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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472
MAC228A Series
110 P(AV) , AVERAGE POWER (WATTS) TC , CASE TEMPERATURE ( C) 10 dc 8.0 = CONDUCTION ANGLE TJ 110C 4.0 30 90 60
104
a = 30
60 90 120 180
a = 180
120
98
6.0
92
86
= CONDUCTION ANGLE 80 0 1.0 2.0 3.0 4.0 5.0
dc
2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 IT(RMS), RMS ONSTATE CURRENT (AMP)
6.0
7.0
8.0
IT(RMS), RMS ONSTATE CURRENT (AMP)
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473
MAC229A8FP, MAC229A10FP Triacs

Designed primarily for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications. All Diffused and GlassPassivated Junctions for Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance and High Heat Dissipation Center Gate Geometry for Uniform Current Spreading Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC229A8FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave 50 to 60 Hz, Gate Open) MAC229A8FP MAC229A10FP On-State RMS Current (TC = 80C) Full Cycle Sine Wave 50 to 60 Hz Peak NonRepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Current (t 2 s,TC = 80C) Symbol VDRM, VRRM 600 800 IT(RMS) ITSM 8.0 80 Amps Amps 1 2 26 A2s Amps 3 Value Unit Volts
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MT2 G
MT1
I2t IGM VGM PGM PG(AV) V(ISO) TJ Tstg
p p p
"2.0 "10
20 0.5 1500 40 to 110 40 to 150 8.0
PIN ASSIGNMENT
Volts Watts Watt 1 2 3 Main Terminal 1 Main Terminal 2 Gate
Peak Gate Voltage (t 2 s, TC = 80C) Peak Gate Power (t 2 s,TC = 80C) Average Gate Power (TC = 80C, t 8.3 ms)
Volts C C in. lb. Device MAC229A8FP MAC229A10FP Package ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box
RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( )
Operating Junction Temperature Range Storage Temperature Range Mounting Torque
474
March, 2000 Rev. 2
OFF CHARACTERISTICS
Peak Repetitive Blocking Current(1) (VD = Rated VDRM, VRRM; Open Gate) TJ = 25C TJ = 110C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
"
VTM IGT
1.8
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) MT2(+), G(+); MT2(+), G(); MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Continuous dc) (VD = 12 V, TC = 110C, RL = 100 ) All Four Quadrants Holding Current (VD = 12 Vdc, Initiating Current =
VGT VGD 0.2
10 20 Volts
2.0 2.5 Volts
"200 mA, Gate Open)
IH t gt
1.5
15
mA s
GateControlled TurnOn Time (VD = Rated VDRM, ITM = 16 A Peak, IG = 30 mA)
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, TC = 110C) Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 11.3 A, Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80C) dv/dt dv/dt(c) 25 5.0 V/s V/s
(1) Ratings apply for open gate conditions. Devices shall not be tested with a constant current source for blocking voltage such that the voltage applied exceeds the rated blocking voltage.
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475
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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476
110 P(AV) , AVERAGE POWER (WATTS) TC , CASE TEMPERATURE ( C) 10 dc 8.0 = CONDUCTION ANGLE TJ 110C 4.0 30 90 60
104
a = 30
60 90 120 180
a = 180
120
98
6.0
92
86
= CONDUCTION ANGLE 80 0 1.0 2.0 3.0 4.0 5.0
dc
2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 IT(RMS), RMS ONSTATE CURRENT (AMP)
6.0
7.0
8.0
IT(RMS), RMS ONSTATE CURRENT (AMP)
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477
MAC320A8FP Triacs
Designed primarily for full-wave ac control applications, such as solid-state relays, motor controls, heating controls and power supplies; or wherever full-wave silicon gate controlled solid-state devices are needed. Triac type thyristors switch from a blocking to a conducting state for either polarity of applied anode voltage with positive or negative gate triggering. Blocking Voltage to 600 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Gate Triggering Guaranteed in Four Modes Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MAC320A8FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) On-State RMS Current (TC = +75C, Full Cycle Sine Wave 50 to 60 Hz)(2) Peak NonRepetitive Surge Current (One Full Cycle, 60 Hz, TC = +75C, preceded and followed by rated current) Peak Gate Power (T C = +75 C, Pulse Width = 2 s) Peak Gate Voltage (T C = +75 C, Pulse Width = 2 s) Average Gate Power (TC = +75C, t = 8.3 ms) Peak Gate Current (T C = +75 C, Pulse Width = 2 s) RMS Isolation Voltage (TA = 25C, Relative Humidity 20%) ( ) Symbol VDRM, VRRM IT(RMS) ITSM Value 600 Unit Volts
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ISOLATED TRIACs ( 20 AMPERES RMS 600 VOLTS
MT2 G
MT1
20 150
Amps Amps
1 2 3
PGM VGM PG(AV) IGM V(ISO) TJ Tstg
20 10 0.5 2.0 1500 40 to +125 40 to +150
Watts Volts
PIN ASSIGNMENT
Watt Amps Volts C C 1 2 3 Main Terminal 1 Main Terminal 2 Gate
Device MAC320A8FP Package ISOLATED TO220FP Shipping 500/Box
478
MAC320A8FP
Characteristic Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = +125C Symbol IDRM, IRRM Min Typ Max 10 2.0 Unit A mA
OFF CHARACTERISTICS
"
p 2%)
VTM
1.4
1.7
Volts
ON CHARACTERISTICS
Peak Gate Trigger Current (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Peak Gate Trigger Voltage (Main Terminal Voltage = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate NonTrigger Voltage (Main Terminal Voltage = 12 V, RL = 100 , TJ = +110C) All Four Quadrants Holding Current (Main Terminal Voltage = 12 Vdc, Gate Open, Initiating Current = 200 mA) IGT VGT VGD 0.2 0.9 0.9 1.1 1.4 2.0 2.0 2.0 2.5 Volts 50 50 50 75 Volts mA
IH
6.0
40
mA
"
t gt
1.5
10
Critical Rate of Rise of Commutation Voltage (VD = Rated VDRM, ITM = 28 A, Commutating di/dt = 10 A/ms, Gate Unenergized, TC = +75C) dv/dt(c) 5.0 V/s
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479
MAC320A8FP
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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480
MAC320A8FP
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (C) 130 PD(AV) , AVERAGE POWER (WATT) 120 110 100 90 80 70 60 50 0 2.0 = Conduction Angle 4.0 6.0 8.0 10 12 14 16 IT(RMS), RMS ON-STATE CURRENT (AMP) 18 20 180 dc = 30 60 90 40 35 30 25 20 15 10 5.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 IT(RMS), RMS ON-STATE CURRENT (AMP) 18 20 60 = 30 = Conduction Angle 90 180 dc

VGTM , GATE TRIGGER VOLTAGE (NORMALIZED)
3 2 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
100 70 50 30 20 TJ = 25C 125C
1 0.7 0.5 i TM , INSTANTANEOUS FORWARD CURRENT (AMP)
10 7 5 3 2
0.3 60 40
20
20
40
60
80
100
120
140

I GTM , GATE TRIGGER CURRENT (NORMALIZED)
3 2 MAIN TERMINAL VOLTAGE = 12 Vdc ALL QUADRANTS
0.7 0.5
1 0.7 0.5 0.3 60 0.3 0.2
0.1 40 20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 vTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
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481
MAC320A8FP
3 I H , HOLDING CURRENT (NORMALIZED) 2 300 TSM , PEAK SURGE CURRENT (AMP) GATE OPEN APPLIES TO EITHER DIRECTION 200
1 0.7 0.5
100 70 50 TC = 80C f = 60 Hz SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 1 2 3 NUMBER OF CYCLES 5 7 10
0.3 60
30 40 20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C)
1 0.5 0.2 0.1 0.05 0.02 0.01 0.1 ZJC(t) = r(t) RJC
0.2
0.5
10
20
50
100
200
500
1k
2k
5k
10 k
t, TIME (ms)
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482
MAC997 Series Sensitive Gate Triacs

Designed for use in solid state relays, MPU interface, TTL logic and any other light industrial or consumer application. Supplied in an inexpensive TO92 package which is readily adaptable for use in automatic insertion equipment. OnePiece, InjectionMolded Package Blocking Voltage to 600 Volts Sensitive Gate Triggering in Four Trigger Modes (Quadrants) for all possible Combinations of Trigger Sources, and especially for Circuits that Source Gate Drives All Diffused and Glassivated Junctions for Maximum Uniformity of Parameters and Reliability Improved Noise Immunity (dv/dt Minimum of 20 V/sec at 110C) Commutating di/dt of 1.6 Amps/msec at 110C High Surge Current of 8 Amps Device Marking: Device Type, e.g., for MAC997A6: MAC7A6, Date Code
Rating Peak Repetitive Off-State Voltage (TJ = 40 to +110C)(1) Sine Wave 50 to 60 Hz, Gate Open MAC997A6,B6 MAC997A8,B8 On-State RMS Current Full Cycle Sine Wave 50 to 60 Hz (TC = +50C) Peak NonRepetitive Surge Current One Full Cycle, Sine Wave 60 Hz (TC = 110C) Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Voltage (t 2.0 ms, TC = +80C) Symbol VDRM, VRRM 400 600 IT(RMS) 0.8 Amp Value Unit Volts 3 2 1
Preferred Device
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TRIACS 0.8 AMPERE RMS 400 thru 600 VOLTS
MT2 G
MT1
PIN ASSIGNMENT
ITSM 8.0 Amps 1 2 I2t VGM PGM PG(AV) IGM TJ Tstg .26 5.0 5.0 0.1 1.0 40 to +110 40 to +150 A2s Volts 3 Main Terminal 1 Gate Main Terminal 2
v v v
Watts Watt
Preferred devices are recommended choices for future use and best overall value. See detailed ordering and shipping information in the package dimensions section on page 490 of this data sheet.
Peak Gate Power (t 2.0 ms, TC = +80C) Average Gate Power (TC = 80C, t 8.3 ms)
Peak Gate Current (t 2.0 ms, TC = +80C) Operating Junction Temperature Range Storage Temperature Range
Amp C C
483
May, 2000 Rev. 1
MAC997 Series
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes for 10 Seconds Symbol RJC RJA TL Max 75 200 260 Unit C/W C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = +110C IDRM, IRRM 10 100 A A
ON CHARACTERISTICS
Peak OnState Voltage (ITM = .85 A Peak; Pulse Width
"
v 2.0 ms, Duty Cycle v 2.0%)
VTM IGT
1.9
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MAC997A6,A8 MT2(+), G() MT2(), G() MT2(), G(+) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) MAC997B6,B8
IL VGT VGD 0.1
5.0 5.0 5.0 7.0 3.0 3.0 3.0 5.0 mA
Latching Current (VD = 12 V, IG = 10 mA) MT2(+), G(+) All Types MT2(+), G() All Types MT2(), G() All Types MT2(), G(+) All Types Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) All Types MT2(+), G() All Types MT2(), G() All Types MT2(), G(+) All Types Gate NonTrigger Voltage (VD = 12 V, RL = 100 Ohms, TJ = 110C) All Four Quadrants Holding Current (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (VD = Rated VDRM, ITM = 1.0 A pk, IG = 25 mA)
1.6 10.5 1.5 2.5
15 20 15 15 Volts
.66 .77 .84 .88
2.0 2.0 2.0 2.5 Volts
IH tgt
1.5 2.0
10
mA s
Rate of Change of Commutating Current (VD = 400 V, ITM = .84 A, Commutating dv/dt = 1.5 V/s, Gate Open, TJ = 110C, f = 250 Hz, with Snubber) Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 110C) Repetitive Critical Rate of Rise of OnState Current Pulse Width = 20 s, IPKmax = 15 A, diG/dt = 1 A/s, f = 60 Hz di/dt(c) 1.6 A/ms
dv/dt di/dt
20
60
10
V/s A/s
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484
MAC997 Series
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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485
MAC997 Series
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (C) 110 I T(RMS) , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE (C) 110
100 90 DC 80 70 60 50 40 30 0 = CONDUCTION ANGLE 0.1 0.2 0.3 180
T = 30
60 90 120
100 90 80 70 60 50 40 30 20 = CONDUCTION ANGLE 0 0.05 0.1 0.15 DC 180
T = 30
60 90
120
0.4
0.5
0.6
0.7
0.8
0.2
0.25
0.3
0.35
0.4
P(AV), MAXIMUM AVERAGE POWER DISSIPATION (WATTS)
1.2 1.0 0.8 = CONDUCTION ANGLE 0.6 120 DC 180
6.0 4.0 TJ = 110C 2.0 25C
1.0 90 ITM, INSTANTANEOUS ON-STATE CURRENT (AMP) 0.4 0.2 0 60 0.6 0.4
T = 30
0 0.1 0.2 0.3 0.4 0.5
0.6
0.7
0.8
0.2
0.1 0.06 0.04
0.02
0.01 0.006
0.4
1.2
2.0
2.8
3.6
4.4
5.2
6.0
VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
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486
MAC997 Series
R(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 I TSM , PEAK SURGE CURRENT (AMPS) 10
Z JC(t) = R JC(t) @ r(t) 0.1
5.0
3.0 2.0 TJ = 110C f = 60 Hz
CYCLE
Surge is preceded and followed by rated current. 1.0 1.0 2.0 3.0 5.0 10 30 50 100
0.01
0.1
1.0
10
100
1S103
1S104
t, TIME (ms)
NUMBER OF CYCLES

100 I GT , GATE TRIGGER CURRENT (mA) VGT, GATE TRIGGER VOLTAGE (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0 40 25 10 5 20 35 50 65 80 95 110
Q4 Q3 Q2 Q1
10
Q4 Q3 Q2
Q1
0.3 40 25
10
20
35
50
65
80
95
110

100 10
10
Q2
MT2 Negative 1 MT2 Positive
Q4 1 Q1
Q3
0 40 25
10
20
35
50
65
80
95
110
0.1 40 25
10
20
35
50
65
80
95
110
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487
MAC997 Series
1N4007
CHARGE
200 V
NON-POLAR CL
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488
MAC997 Series TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A H2B H2B

Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
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489
MAC997 Series
ORDERING & SHIPPING INFORMATION: MAC97 Series packaging options, Device Suffix
U.S. Europe Equivalent MAC997A6RL1, A8RL1 MAC997B6RL1, B8RL1 MAC997A6,A8 MAC997B6,B8 MAC997A6RLRP, A8RLRP MAC997B6RLRP, B8RLRP Shipping Radial Tape and Reel (2K/Reel) Bulk in Box (5K/Box) Radial Tape and Fan Fold Box (2K/Box) Description of TO92 Tape Orientation Flat side of TO92 and adhesive tape visible N/A, Bulk Round side of TO92 and adhesive tape visible
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490
MCR08B, MCR08M
Preferred Device
Sensitive Gate Silicon Controlled Rectifiers

PNPN devices designed for line powered consumer applications such as relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and sensing and detection circuits. Supplied in surface mount package for use in automated manufacturing. Sensitive Gate Trigger Current Blocking Voltage to 600 Volts Glass Passivated Surface for Reliability and Uniformity Surface Mount Package Device Marking: MCR08BT1: CR08B; MCR08MT1: CR08M, and Date Code
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G A K

Rating Peak Repetitive OffState Voltage(1) (Sine Wave, RGK = 1000 , TJ = 25 to 110C) MCR08BT1 MCR08MT1 On-State Current RMS (All Conduction Angles; TC = 80C) Peak Non-repetitive Surge Current (1/2 Cycle Sine Wave, 60 Hz, TC = 25C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Power (TC = 80C, t = 1.0 s) Average Gate Power (TC = 80C, t = 8.3 ms) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 200 600 IT(RMS) ITSM 0.8 8.0 Amps Amps 1 I2t PGM PG(AV) TJ Tstg 0.4 0.1 0.01 40 to +110 40 to +150 A2s Watts Watts 2 3 4 Value Unit Volts 1 2 3 4
SOT223 CASE 318E STYLE 10
PIN ASSIGNMENT
C C Device MCR08BT1 Package SOT223 Shipping 16mm Tape and Reel (1K/Reel) 16mm Tape and Reel (1K/Reel)
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant source such that the voltage ratings of the devices are exceeded.
MCR08MT1
SOT223
491
May, 2000 Rev. 3
Publication Order Number: MCR08BT1/D
MCR08B, MCR08M
Characteristic Thermal Resistance, Junction to Ambient PCB Mounted per Figure 1 Thermal Resistance, Junction to Tab Measured on Anode Tab Adjacent to Epoxy Maximum Device Temperature for Soldering Purposes (for 10 Seconds Maximum) Symbol RJA RJT TL Value 156 25 260 Unit C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current(2) (VAK = Rated VDRM or VRRM, RGK = 1000 ) TJ = 25C TJ = 110C IDRM, IRRM 10 200 A A
ON CHARACTERISTICS
Peak Forward On-State Voltage(1) (IT = 1.0 A Peak) Gate Trigger Current (Continuous dc)(3) (VAK = 12 Vdc, RL = 100 ) Holding Current(3) (VAK = 12 Vdc, Initiating Current = 20 mA) Gate Trigger Voltage (Continuous dc)(3) (VAK = 12 Vdc, RL = 100 ) VTM IGT IH VGT 1.7 200 5.0 0.8 Volts A mA Volts
Critical Rate-of-Rise of Off State Voltage (Vpk = Rated VDRM, TC = 110C, RGK = 1000 , Exponential Method) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) RGK = 1000 is included in measurement. (3) RGK is not included in measurement. dv/dt 10 V/s
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492
MCR08B, MCR08M
Symbol
Parameter
0.15 3.8 0.079 2.0 0.091 0.091 2.3 2.3 0.079 2.0 0.984 25.0 0.059 0.059 0.059 1.5 1.5 1.5
inches mm
0.244 6.2
BOARD MOUNTED VERTICALLY IN CINCH 8840 EDGE CONNECTOR. BOARD THICKNESS = 65 MIL., FOIL THICKNESS = 2.5 MIL. MATERIAL: G10 FIBERGLASS BASE EPOXY
0.096 2.44 0.059 1.5
0.096 2.44 0.059 1.5
0.096 2.44
0.472 12.0
Figure 1. PCB for Thermal Impedance and Power Testing of SOT-223
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493
MCR08B, MCR08M
IT, INSTANTANEOUS ON-STATE CURRENT (AMPS) 10 R JA , JUNCTION TO AMBIENT THERMAL RESISTANCE, ( C/W) 160 150 140 130 120 110 100 90 80 70 60 50 40 30
TYPICAL MAXIMUM DEVICE MOUNTED ON FIGURE 1 AREA = L2 PCB WITH TAB AREA AS SHOWN
1.0
L
4
1 2 3
0.1 TYPICAL AT TJ = 110C MAX AT TJ = 110C MAX AT TJ = 25C 0 1.0 2.0 3.0 4.0 vT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
MINIMUM FOOTPRINT = 0.076 cm2 0 1.0 2.0 3.0 6.0 FOIL AREA (cm2) 4.0 5.0 7.0 8.0 9.0 10
0.01

110 T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( C) 1.0 cm2 FOIL, 50 OR 60 Hz HALFWAVE 180 120 = 30 60
CONDUCTION ANGLE
110 100 T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( C) 50 OR 60 Hz HALFWAVE 90 80 70 60 50 40 30 20 0 0.1 0.2 0.3 0.4 0.5 = 30 60 90 dc 180 120
ANGLE
= CONDUCTION
100 90 80 70 60 50 40 30 = 20 0
dc
90
0.1
0.2
0.3
0.4
0.5
IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
Figure 4. Current Derating, Minimum Pad Size Reference: Ambient Temperature

110 T A , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( C) 100 90 80 70 60 50
ANGLE

110 dc T(tab) , MAXIMUM ALLOWABLE TAB TEMPERATURE ( C) 50 OR 60 Hz HALFWAVE 180 = 30 60 90 120
dc
PAD AREA = 4.0 cm2, 50 OR 60 Hz HALFWAVE 180
= 30 60 90
120
= CONDUCTION
ANGLE
= CONDUCTION
0.1
0.2
0.3
0.4
0.5
85
0.1
0.2
0.3
0.4
0.5
Figure 7. Current Derating Reference: Anode Tab
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494
MCR08B, MCR08M
1.0 0.9 MAXIMUM AVERAGE POWER P(AV),DISSIPATION (WATTS) 0.8 = 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 120 180 dc
CONDUCTION ANGLE
1.0 = 30 60 90 r T , TRANSIENT THERMAL RESISTANCE NORMALIZED
0.1
0.01 0.0001
0.001
0.01
0.1
1.0
10
100
t, TIME (SECONDS)

VGT , GATE TRIGGER VOLTAGE (VOLTS) 0.7 VAK = 12 V RL = 100 2.0
Figure 9. Thermal Response Device Mounted on Figure 1 Printed Circuit Board
0.5
I H , HOLDING CURRENT (NORMALIZED)
0.6
VAK = 12 V RL = 3.0 k
1.0
0.4
0.3 40
20
20
40
60
80
110
0 40
20
20
40
60
80
110
TJ, JUNCTION TEMPERATURE, (C)
TJ, JUNCTION TEMPERATURE, (C)

0.7 V GT , GATE TRIGGER VOLTAGE (VOLTS) 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.1 1.0 10 100 1000 VAK = 12 V RL = 100 TJ = 25C 1000 I GT , GATE TRIGGER CURRENT ( A)
Figure 11. Typical Normalized Holding Current versus Junction Temperature
RGK = 1000 , RESISTOR CURRENT INCLUDED
100 VAK = 12 V RL = 100 10 WITHOUT GATE RESISTOR
1.0 40
20
20
40
60
80
110
IGT, GATE TRIGGER CURRENT (A)
Figure 12. Typical Range of VGT versus Measured IGT
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495
MCR08B, MCR08M
100 TJ = 25C STATIC dv/dt (V/ S) 10 IGT = 48 A 10000 5000 IH , HOLDING CURRENT (mA) 1000 500 100 50 10 5.0 1.0 0.5 0.1 1.0 10 100 1000 10,000 100,000 0.1 10 100 1000 125 110 75 10,000 100,000 50 TJ = 25 Vpk = 400 V
IGT = 7 A 1.0
RGK, GATE-CATHODE RESISTANCE (OHMS)
Figure 14. Holding Current Range versus Gate-Cathode Resistance

10000 1000 500 STATIC dv/dt (V/ S) 100 50 500 V 10 5.0 1.0 10 100 1000 10,000 400 V 50 V
Figure 15. Exponential Static dv/dt versus Junction Temperature and Gate-Cathode Termination Resistance
10000
300 V 200 V 100 V
TJ = 110C 1000 500 STATIC dv/dt (V/ S) 100 50 10 5.0 1.0 0.01
TJ = 110C 400 V (PEAK)
RGK = 100
RGK = 1.0 k
RGK = 10 k 0.1 1.0 10 100 CGK, GATE-CATHODE CAPACITANCE (nF)
Figure 16. Exponential Static dv/dt versus Peak Voltage and Gate-Cathode Termination Resistance
Figure 17. Exponential Static dv/dt versus Gate-Cathode Capacitance and Resistance
10000 1000 500 STATIC dv/dt (V/ S) 100 50 IGT = 70 A 10 5.0 1.0 10 100 IGT = 15 A 1000 10,000 100,000 IGT = 5 A IGT = 35 A
GATE-CATHODE RESISTANCE (OHMS)
Figure 18. Exponential Static dv/dt versus Gate-Cathode Termination Resistance and Product Trigger Current Sensitivity
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496
MCR08B, MCR08M INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
0.15 3.8 0.079 2.0
0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5
0.091 2.3
0.248 6.3
0.059 1.5
inches mm
SOT-223
SOT-223 POWER DISSIPATION The power dissipation of the SOT-223 is a function of the anode pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows:
PD = TJ(max) TA RJA
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 550 milliwatts.
PD = 110C 25C = 550 milliwatts 156C/W
The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 550 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the anode pad. By increasing the area of the anode pad, the power dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus anode pad area is shown in Figure 3. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.
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497
MCR08B, MCR08M
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference should be a maximum of 10C. The soldering temperature and time should not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient should be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
STEP 5 STEP 6 STEP 7 STEP 4 HEATING VENT COOLING HEATING ZONES 3 & 6 ZONES 4 & 7 205 TO SPIKE SOAK 219C 170C PEAK AT SOLDER 160C JOINT SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 50C 140C
TMAX
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498
MCR8DCM, MCR8DCN
Preferred Device

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and Holding Characteristics Available in Surface Mount Lead Form Case 369A Device Marking: Device Type, e.g., MCR8DCM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8DCM MCR8DCN Symbol VDRM, VRRM 600 800 8.0 5.1 80 Amps Amps Amps DPAK CASE 369A STYLE 4 1 2 3 Value Unit Volts A
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G K
OnState RMS Current IT(RMS) (180 Conduction Angles; TC = 105C) Average OnState Current (180 Conduction Angles; TC = 105C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 msec) Forward Peak Gate Power (Pulse Width 1.0 msec, TC = 105C) Forward Average Gate Power (t = 8.3 msec, TC = 105C) Forward Peak Gate Current (Pulse Width 1.0 msec, TC = 105C) Operating Junction Temperature Range Storage Temperature Range IT(AV) ITSM
26 5.0 0.5 2.0 40 to 125 40 to 150
A2sec 1 Watts Watts Amps C C 2 3 4
PIN ASSIGNMENT
Device MCR8DCMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
(1) VDRM, VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded.
MCR8DCNT4
DPAK 369A
499
May, 2000 Rev. 2
Publication Order Number: MCR8DCM/D
MCR8DCM, MCR8DCN
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)

Characteristics Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Peak Repetitive Forward or Peak Repetitive Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 5.0
ON CHARACTERISTICS
Peak OnState Voltage(3) (ITM = 16 A) Gate Trigger Current (Continuous dc) (VAK = 12 V, RL = 100 , TJ = 25C) (TJ = 40C) VTM IGT 2.0 VGT 0.5 0.2 TJ = 25C TJ = 40C IH 4.0 IL 4.0 22 30 60 22 30 60 mA 0.65 1.0 2.0 mA 7.0 15 30 Volts 1.4 1.8 mA Volts
W W
Gate Trigger Voltage (Continuous dc) (VAK = 12 V, RL = 100 , TJ = 25C) (TJ = 40C) (TJ = 125C) Holding Current (VAK = 12 V, Initiating Current = 200 mA, Gate Open) Latching Current (VAK = 12 V, IG = 15 mA, TJ = 25C) (VAK = 12 V, IG = 30 mA, TJ = 40C)
Critical Rate of Rise of OffState Voltage (VAK = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. (3) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt 50 200 V/ s
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500
MCR8DCM, MCR8DCN
Symbol
Parameter
P(AV) , AVERAGE POWER DISSIPATION (WATTS)
125
10 180 8.0
120
115
a = Conduction
Angle
6.0
a = Conduction
Angle
60
90
120 dc
110 dc
4.0
a = 30
105
2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
a = 30
0 1.0 2.0
60 3.0
90 4.0
120 5.0
180 6.0
100 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
100
TYPICAL @ TJ = 25C MAXIMUM @ TJ = 125C r(t) , TRANSIENT RESISTANCE (NORMALIZED)
1.0
10
MAXIMUM @ TJ = 25C 1.0
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
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501
MCR8DCM, MCR8DCN
100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 35 I GT, GATE TRIGGER CURRENT (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 5.0 20 50 65 80 95 110 125 40 25 10 5.0 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
10
1.0 40 25 10

100 100
10
IL, LATCHING CURRENT (mA) 5.0 20 35 50 65 80 95 110 125
10
1.0 40 25 10
1.0 40 25 10
5.0
20
35
50
65
80
95
110
125
1000 VD = 800 V TJ = 125C STATIC dv/dt (V/ ms) 100 10 100 1000 10 K RGK, GATECATHODE RESISTANCE (OHMS)
Figure 9. Exponential Static dv/dt versus GateCathode Resistance
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502
MCR8DCM, MCR8DCN
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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503
MCR8DSM, MCR8DSN
Preferred Device

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and Holding Characteristics Available in Two Package Styles Surface Mount Lead Form Case 369A Miniature Plastic Package Straight Leads Case 369 Device Marking: Device Type, e.g., for MCR8DSM: CR8DSM, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8DSM MCR8DSN OnState RMS Current (180 Conduction Angles; TC = 90C) Average OnState Current (180 Conduction Angles; TC = 90C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 msec) Forward Peak Gate Power (Pulse Width 10 msec, TC = 90C) Forward Average Gate Power (t = 8.3 msec, TC = 90C) Forward Peak Gate Current (Pulse Width 10 msec, TC = 90C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) IT(AV) ITSM 8.0 5.1 90 Amps Amps Value Unit Volts 1 2 3 4
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G A K
PIN ASSIGNMENT
Amps 1 2 3 Cathode Anode Gate Anode
34 5.0 0.5 2.0 40 to 110 40 to 150
A2sec Watts
Watt Amps C C Device MCR8DSMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
MCR8DSNT4
DPAK 369A
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded.
504
May, 2000 Rev. 2
Publication Order Number: MCR8DSM/D
MCR8DSM, MCR8DSN
Characteristic Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance Junction to Ambient(1) Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RqJC RqJA RqJA TL Max 2.2 88 80 260 Unit C/W

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM; RGK = 1.0 K )(2)
TJ = 25C TJ = 110C
IDRM IRRM
10 500
mA
ON CHARACTERISTICS
Peak Reverse Gate Blocking Voltage (IGR = 10 A)
VGRM 10 IRGM VTM TJ = 25C TJ = 40C TJ = 25C TJ = 40C TJ = 110C TJ = 25C TJ = 40C TJ = 25C TJ = 40C IGT 5.0 VGT 0.45 0.2 IH 0.5 IL 0.5 tgt 2.0 5.0 1.0 6.0 10 1.0 6.0 10 0.65 1.0 1.5 12 200 300 1.4 1.8 1.2 12.5 18
Volts
Peak Reverse Gate Blocking Current (VGR = 10 V) Peak Forward OnState Voltage(3) (ITM = 16 A) Gate Trigger Current (Continuous dc)(4) (VD = 12 V, RL = 100 )
mA
Volts
W W
mA
Volts
Gate Trigger Voltage (Continuous dc)(4) (VD = 12 V, RL = 100 )
Holding Current (VD = 12 V, Initiating Current = 200 mA, Gate Open) Latching Current (VD = 12 V, IG = 2.0 mA)
mA
mA
Total TurnOn Time (Source Voltage = 12 V, RS = 6.0 K , IT = 16 A(pk), RGK = 1.0 K ) (VD = Rated VDRM, Rise Time = 20 ns, Pulse Width = 10 s)
ms
Characteristics Critical Rate of Rise of OffState Voltage (VD = 0.67 X Rated VDRM, Exponential Waveform, RGK = 1.0 K , TJ = 110C) Symbol dv/dt 2.0 10 Min Typ Max Unit V/ s
(1) Surface mounted on minimum recommended pad size. (2) Ratings apply for negative gate voltage or RGK = 1.0 K . Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. (3) Pulse Test; Pulse Width 2.0 msec, Duty Cycle 2%. (4) RGK current not included in measurements.
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505
MCR8DSM, MCR8DSN
Symbol
Parameter
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (C)
110
12 10
105
a
8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0
100
a = Conduction
Angle
a = Conduction
Angle
90 60
120
180 dc
95 dc 90
a = 30
a = 30
85 0 1.0 2.0
60 3.0
90 4.0
120 5.0
180 6.0
6.0
IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
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506
MCR8DSM, MCR8DSN
I T, INSTANTANEOUS ONSTATE CURRENT (AMPS) 100 r(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED) TYPICAL @ TJ = 25C MAXIMUM @ TJ = 110C 10 1.0
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
1000
1.0
RGK = 1.0 K 100
10
GATE OPEN
VGT, GATE TRIGGER VOLTAGE (VOLTS) 0.1 110
I GT, GATE TRIGGER CURRENT ( A)
m
1.0 40 25
10
5.0
20
35
50
65
80
95
40 25
10
5.0
20
35
50
65
80
95
110
10 RGK = 1.0 K IH , HOLDING CURRENT (mA)
10
W
RGK = 1.0 K
1.0
1.0
0.1 40 25
10
5.0
20
35
50
65
80
95
110
0.1 40 25
10
5.0
20
35
50
65
80
95
110
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507
MCR8DSM, MCR8DSN
10 TJ = 25C IH, HOLDING CURRENT (mA) 8.0 STATIC dv/dt (V/m s) 100 70C 90C TJ = 110C 10 1000
6.0 IGT = 25 mA 4.0 IGT = 10 mA
2.0 0 100
1.0 1000 RGK, GATECATHODE RESISTANCE (OHMS) 10 K 100 RGK, GATECATHODE RESISTANCE (OHMS) 1000
Figure 9. Holding Current versus GateCathode Resistance
Figure 10. Exponential Static dv/dt versus GateCathode Resistance and Junction Temperature
1000 TJ = 110C 400 V STATIC dv/dt (V/ ms) 100
1000 VD = 800 V TJ = 110C STATIC dv/dt (V/ ms) 100 IGT = 25 mA
600 V VPK = 800 V
IGT = 10 mA 10
10
1.0 100 RGK, GATECATHODE RESISTANCE (OHMS) 1000
Figure 11. Exponential Static dv/dt versus GateCathode Resistance and Peak Voltage
Figure 12. Exponential Static dv/dt versus GateCathode Resistance and Gate Trigger Current Sensitivity
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508
MCR8DSM, MCR8DSN
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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509
MCR8M, MCR8N
Preferred Device

Designed primarily for half-wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever halfwave, silicon gatecontrolled devices are needed. Blocking Voltage of 600 thru 800 Volts OnState Current Rating of 8 Amperes RMS at 80C High Surge Current Capability 80 Amperes Rugged, Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design High Immunity to dv/dt 100 V/sec Minimum at 125C Device Marking: Logo, Device Type, e.g., MCR8N, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8M MCR8N On-State RMS Current (180 Conduction Angles; TC = 80C) Peak Non-Repetitive Surge Current (One Full Cycle, 60 Hz, TC = 125C) Circuit Fusing Consideration (t = 8.33 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) ITSM I2t PGM PG(AV) IGM TJ Tstg 8.0 80 26.5 5.0 0.5 2.0 40 to 125 40 to 150 Amps Amps A2sec Watts 1 Watt Amps C C 2 3 4 1 2 3 Value Unit Volts
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G A K
PIN ASSIGNMENT
Device MCR8M MCR8N Package TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.
510
March, 2000 Rev. 3
Publication Order Number: MCR8/D
MCR8M, MCR8N

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VD = Rated VDRM and VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 2.0
ON CHARACTERISTICS
Peak Forward OnState Voltage* (ITM = 16 A) Gate Trigger Current (Continuous dc) (VD = 12 V; RL = 100 ) Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latch Current (VD = 12 V, IG = 15 mA) Gate Trigger Voltage (Continuous dc) (VD = 12 V; 100 ) Gate NonTrigger Voltage (VD = 12 V; RL = 100 ) TJ = 25C TJ = 125C VTM IGT IH IL VGT VGD 2.0 4.0 6.0 0.5 0.2 7.0 17 20 0.65 1.8 15 30 40 1.0 Volts mA mA mA Volts Volts
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Critical Rate of Rise of OnState Current IPK = 50 A, Pw = 40 sec, diG/dt = 1 A/sec, Igt = 50 mA *Indicates Pulse Test: Pulse Width dv/dt di/dt 100 250 50 V/s A/s
v 2.0 ms, Duty Cycle v 2%.
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511
MCR8M, MCR8N
Symbol
Parameter
125 TC, CASE TEMPERATURE (C) 120 115 110 105 dc 100 95 90 0 1 2 30 3 60 4 5 90 180 6 7 8
P(AV), AVERAGE POWER DISSIPATION (WATTS)
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 IT(AV), AVERAGE ONSTATE CURRENT (AMPS) 30 60 90 180 dc

100
GATE TRIGGER CURRENT (mA)
MAXIMUM @ TJ = 25C MAXIMUM @ TJ = 125C
20 18 16 14 12 10 8 6 4 2 0 40 25 10 5 20 35 50 65 80 95 110 125
10
0.1 0.5 1.0 1.5 2.0 2.5 3.0 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
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512
MCR8M, MCR8N
VGT, GATE TRIGGER VOLTAGE (VOLTS) 35 95 100 IH, HOLDING CURRENT (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110 125
10
1 40 25 10
20
50
65
80
110 125
100 IL, LATCHING CURRENT (mA)
10
1 40 25 10
20
35
50
65
80
95 110 125
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513
MCR8SD, MCR8SM, MCR8SN

Preferred Device

Designed primarily for half-wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever halfwave, silicon gatecontrolled devices are needed. Sensitive Gate Allows Triggering by Microcontrollers and other Logic Circuits Blocking Voltage to 800 Volts OnState Current Rating of 8 Amperes RMS at 80C High Surge Current Capability 80 Amperes Rugged, Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design Immunity to dv/dt 5 V/sec Minimum at 110C Device Marking: Logo, Device Type, e.g., MCRSD, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8SD MCR8SM MCR8SN On-State RMS Current (180 Conduction Angles; TC = 80C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.33 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM 8.0 80 Amps Amps 1 2 3 4 I2t PGM PG(AV) IGM TJ Tstg 26.5 5.0 0.5 2.0 40 to 110 40 to 150 A2sec Value Unit Volts TO220AB CASE 221A STYLE 3
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G A K
PIN ASSIGNMENT
Watts Device Watt Amps MCR8SN C C
Package TO220AB TO220AB TO220AB
Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
MCR8SD MCR8SM
514
March, 2000 Rev. 1
Publication Order Number: MCR8S/D


OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current(1) (VD = Rated VDRM and VRRM; RGK = 1 k) TJ = 25C TJ = 110C IDRM, IRRM A 10 500
ON CHARACTERISTICS
Peak Forward OnState Voltage* (ITM = 16 A) Gate Trigger Current (Continuous dc)(2) (VD = 12 V; RL = 100 ) Holding Current(2) (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latch Current(2) (VD = 12 V, IG = 200 A) Gate Trigger Voltage (Continuous dc)(2) (VD = 12 V; RL = 100 ) Gate NonTrigger Voltage (VD = 12 V, RL = 100 ) TJ = 25C TJ = 40C VTM IGT IH IL 5.0 0.3 0.2 25 0.5 0.6 0.65 1.8 200 6.0 8.0 1.0 1.5 Volts A mA mA Volts Volts
VGT VGD
TJ = 110C
Critical Rate of Rise of OffState Voltage (VD = 67% VDRM, RGK = 1 K, CGK = 0.1 F, TJ = 110C) Critical Rate of Rise of OnState Current IPK = 50 A, Pw = 40 sec, diG/dt = 1 A/sec, Igt = 10 mA *Indicates Pulse Test: Pulse Width (1) RGK = 1000 Ohms included in measurement. (2) Does not include RGK in measurement. dv/dt di/dt 5.0 15 100 V/s A/s
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515

Symbol
Parameter
110 TC, CASE TEMPERATURE (C) 105 100 95 90 85 80 75 0 1 dc 30 2 60 3 90 120 180 4 5 6 7 8
15 dc
12
9 90 6 30 3 0 0 1 2 3 4 5 60 120
180

100
GATE TRIGGER CURRENT ( m A)
TYPICAL @ TJ = 25C MAXIMUM @ TJ = 110C
100 90 80 70 60 50 40 30 20 10 0 40 25 10 5 20 35 50 65 80 95 110
10
MAXIMUM @ TJ = 25C
0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
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516

VGT, GATE TRIGGER VOLTAGE (VOLTS) 35 95 1000 IH, HOLDING CURRENT ( m A) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110
100
10
1 40 25 10
20
50
65
80
110
1000 IL, LATCHING CURRENT ( m A)
100
10
1 40 25 10
20
35
50
65
80
95
110
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517
MCR12D, MCR12M, MCR12N

Preferred Device

Designed primarily for half-wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever halfwave silicon gatecontrolled devices are needed. Blocking Voltage to 800 Volts OnState Current Rating of 12 Amperes RMS at 80C High Surge Current Capability 100 Amperes Rugged, Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT an IH Specified for Ease of Design High Immunity to dv/dt 100 V/sec Minimum at 125C Device Marking: Logo, Device Type, e.g., MCR12D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR12D MCR12M MCR12N On-State RMS Current (180 Conduction Angles; TC = 80C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.33 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM 12 100 A A TO220AB CASE 221A STYLE 3 Value Unit Volts
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G A K
41 5.0 0.5 2.0 40 to +125 40 to +150
A2sec Watts Watts A C C
PIN ASSIGNMENT
Device MCR12D MCR12M MCR12N Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
518
December, 1999 Rev. 2


OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VD = Rated VDRM and VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 2.0
ON CHARACTERISTICS
Peak Forward OnState Voltage* (ITM = 24 A) Gate Trigger Current (Continuous dc) (VD = 12 V; RL = 100 ) Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latch Current (VD = 12 V, IG = 20 mA) Gate Trigger Voltage (Continuous dc) (VD = 12 V; RL =100 ) VTM IGT IH IL VGT 2.0 4.0 6.0 0.5 8.0 20 25 0.65 2.2 20 40 60 1.0 Volts mA mA mA Volts
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Repetitive Critical Rate of Rise of OnState Current IPK = 50 A, Pw = 40 sec, diG/dt = 1 A/sec, Igt = 50 mA *Indicates Pulse Test: Pulse Width dv/dt di/dt 100 250 50 V/s A/s
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519

Symbol
Parameter
125 TC , CASE TEMPERATURE ( C) 120 115 110 105 100 95 90 0 1 2 3 30 4 5 60 6 7 90 8 9 180 10 11 12 dc
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 9 10 11 12 IT(AV), AVERAGE ONSTATE CURRENT (AMPS) 30 90 180 dc
100
MAXIMUM @ TJ = 25C GATE TRIGGER CURRENT (mA) MAXIMUM @ TJ = 125C
20 18 16 14 12 10 8 6 4 2 0 40 25 10
10
20
35
50
65
80
95 110 125
http://onsemi.com
520

100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 35 95 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110 125
IH, HOLDING CURRENT (mA)
10
1 40 25 10
20
50
65
80
110 125
100
10
1 40 25 10
20
35
50
65
80
95 110 125
http://onsemi.com
521
MCR12DCM, MCR12DCN
Preferred Device

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and Holding Characteristics Device Marking: Device Type, e.g., for MCR12DCM: R12DCM, Date Code
http://onsemi.com

Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR12DCM MCR12DCN OnState RMS Current (180 Conduction Angles; TC = 90C) Average OnState Current (180 Conduction Angles; TC = 90C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 msec) Forward Peak Gate Power (Pulse Width 1.0 msec, TC = 90C) Forward Average Gate Power (t = 8.3 msec, TC = 90C) Forward Peak Gate Current (Pulse Width 1.0 msec, TC = 90C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) IT(AV) ITSM 12 7.6 100 Amps Amps Amps 1 2 Value Unit Volts A
G K
41 5.0 0.5 2.0 40 to 125 40 to 150
A2sec 1 Watts Watts Amps 2 3 4
PIN ASSIGNMENT
C C Device MCR12DCMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
(1) VDRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded.
MCR12DCNT4
DPAK 369A
522
May, 2000 Rev. 2
Publication Order Number: MCR12DCM/D
MCR12DCM, MCR12DCN

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM mA 0.01 5.0
ON CHARACTERISTICS
Peak Forward OnState Voltage(3) (ITM = 20 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) VTM TJ = 25C TJ = 40C IGT 2.0 VGT 0.5 VGD IH 4.0 IL 4.0 22 40 80 22 40 80 mA 0.2 0.65 1.0 2.0 Volts mA 7.0 20 40 Volts 1.3 1.9 mA Volts
W W W
* *
Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) Gate NonTrigger Voltage (VD = 12 V, RL = 100 )
TJ = 25C TJ = 40C TJ = 125C
Holding Current (VD = 12 V, Initiating Current = 200 mA, Gate Open) TJ = 25C TJ = 40C Latching Current (VD = 12 V, IG = 20 mA, TJ = 25C) (VD = 12 V, IG = 40 mA, TJ = 40C)
Characteristic Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) (1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. (3) Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%. Symbol dv/dt 50 200 Min Typ Max Unit V/ s
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523
MCR12DCM, MCR12DCN
Symbol
Parameter
125 120 115 110
16 14 12 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 90 120
180
60
a = Conduction
Angle
dc
105
100 95 90 85 0 1.0
dc
a = 30
a = Conduction
Angle
a = 30
2.0 3.0
60 4.0
90 5.0
120 6.0
180 7.0 8.0
8.0
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524
MCR12DCM, MCR12DCN
I T, INSTANTANEOUS ONSTATE CURRENT (AMPS) 100 TYPICAL @ TJ = 25C MAXIMUM @ TJ = 125C 10 r(t) , TRANSIENT RESISTANCE (NORMALIZED) 1.0
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
100 VGT, GATE TRIGGER VOLTAGE (VOLTS) 35 I GT, GATE TRIGGER CURRENT (mA)
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 5.0 20 50 65 80 95 110 125 40 25 10 5.0 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
10
1.0 40 25 10
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525
MCR12DCM, MCR12DCN
100 100
10
IL, LATCHING CURRENT (mA) 5.0 20 35 50 65 80 95 110 125
10
1.0 40 25 10
1.0 40 25 10
5.0
20
35
50
65
80
95
110
125
1000 VD = 800 V TJ = 125C STATIC dv/dt (V/ ms) 100 10 100 1000 10 K RGK, GATECATHODE RESISTANCE (OHMS)
Figure 9. Exponential Static dv/dt versus GateCathode Resistance
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526
MCR12DCM, MCR12DCN
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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527
MCR12DSM, MCR12DSN
Preferred Device

Designed for high volume, low cost, industrial and consumer applications such as motor control; process control; temperature, light and speed control. Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and Holding Characteristics Device Marking: Device Type, e.g., for MCR12DSM: R12DSM, Date Code
http://onsemi.com

G

Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR12DSM MCR12DSN OnState RMS Current (180 Conduction Angles; TC = 75C) Average OnState Current (180 Conduction Angles; TC = 75C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 msec) Forward Peak Gate Power (Pulse Width 1.0 msec, TC = 75C) Forward Average Gate Power (t = 8.3 msec, TC = 75C) Forward Peak Gate Current (Pulse Width 1.0 msec, TC = 75C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 600 800 IT(RMS) IT(AV) ITSM 12 7.6 100 Amps Amps Amps 1 I2t PGM PG(AV) IGM TJ Tstg 41 5.0 0.5 2.0 40 to 110 40 to 150 A2sec Watts Watts Amps C C 2 3 4 Value Unit Volts
4 1 2
PIN ASSIGNMENT
Device MCR12DSMT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the device are exceeded.
MCR12DSNT4
DPAK 369A
528
May, 2000 Rev. 2
Publication Order Number: MCR12DSM/D
MCR12DSM, MCR12DSN

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current(3) (VAK = Rated VDRM or VRRM; RGK = 1.0 K )
TJ = 25C TJ = 110C
IDRM, IRRM
10 500
mA
ON CHARACTERISTICS
Peak Reverse Gate Blocking Voltage (IGR = 10 A)
VGRM 10 IGRM VTM TJ = 25C TJ = 40C TJ = 25C TJ = 40C TJ = 110C TJ = 25C TJ = 40C TJ = 25C TJ = 40C IGT 5.0 VGT 0.45 0.2 IH 0.5 IL 0.5 tgt 2.0 5.0 1.0 6.0 10 1.0 6.0 10 0.65 1.0 1.5 12 200 300 1.3 1.9 1.2 12.5 18
Volts
Peak Reverse Gate Blocking Current (VGR = 10 V) Peak Forward OnState Voltage(4) (ITM = 20 A) Gate Trigger Current (Continuous dc)(5) (VD = 12 V, RL = 100 )
mA
Volts
W W
mA
Volts
Gate Trigger Voltage (Continuous dc)(5) (VD = 12 V, RL = 100 )
Holding Current (VD = 12 V, Initiating Current = 200 mA, Gate Open) Latching Current (VD = 12 V, IG = 2.0 mA)
mA
mA
TurnOn Time (Source Voltage = 12 V, RS = 6.0 K , IT = 16 A(pk), RGK = 1.0 K ) (VD = Rated VDRM, Rise Time = 20 ns, Pulse Width = 10 s)
ms
Characteristics Critical Rate of Rise of OffState Voltage (VD = 0.67 X Rated VDRM, Exponential Waveform, RGK = 1.0 K , TJ = 110C) Symbol dv/dt 2.0 10 Min Typ Max Unit V/ s
(1) Surface mounted on minimum recommended pad size. (2) 1/8 from case for 10 seconds. (3) Ratings apply for negative gate voltage or RGK = 1.0 K . Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. (4) Pulse Test: Pulse Width 2.0 msec, Duty Cycle 2%. (5) RGK current not included in measurement.
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529
MCR12DSM, MCR12DSN
Symbol
Parameter
110 105 100 95 90 85 80 75 70 0 dc
16 14 12 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS) 90 60 120 180
a = Conduction
Angle
dc
a = 30
180
a = Conduction
Angle
1.0 2.0
a = 30
3.0 4.0
60 5.0
90 6.0
120 7.0 8.0
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530
MCR12DSM, MCR12DSN
I T, INSTANTANEOUS ONSTATE CURRENT (AMPS) 100 r(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED) TYPICAL @ TJ = 25C MAXIMUM @ TJ = 110C 10 1.0
0.01 0.1 1.0 10 100 1000 10 K t, TIME (ms)
1000 I GT, GATE TRIGGER CURRENT ( A)
1.0
RGK = 1.0 K 100
10
GATE OPEN
1.0 40 25
10
5.0
20
35
50
65
80
95
110
VGT, GATE TRIGGER VOLTAGE (VOLTS) 0.1 40 25 10 5.0 20 35 50 65 80 95 110
10 RGK = 1.0 K IH , HOLDING CURRENT (mA)
10
W
RGK = 1.0 K
1.0
1.0
0.1 40 25
10
5.0
20
35
50
65
80
95
110
0.1 40 25
10
5.0
20
35
50
65
80
95
110
Figure 7. Typical Holding Current versus Junction Temperature http://onsemi.com

531
MCR12DSM, MCR12DSN
10 TJ = 25C IH, HOLDING CURRENT (mA) 8.0 STATIC dv/dt (V/m s) 100 70C 90C TJ = 110C 10 1000
6.0 IGT = 25 mA 4.0 IGT = 10 mA
2.0 0 100
1.0 1000 RGK, GATECATHODE RESISTANCE (OHMS) 10 K 100 RGK, GATECATHODE RESISTANCE (OHMS) 1000
Figure 9. Holding Current versus GateCathode Resistance
Figure 10. Exponential Static dv/dt versus GateCathode Resistance and Junction Temperature
1000
1000 TJ = 110C 400 V STATIC dv/dt (V/ ms) 100 STATIC dv/dt (V/ ms)
VD = 800 V TJ = 110C 100 IGT = 25 mA
600 V VPK = 800 V
IGT = 10 mA 10
10
Figure 11. Exponential Static dv/dt versus GateCathode Resistance and Peak Voltage
Figure 12. Exponential Static dv/dt versus GateCathode Resistance and Gate Trigger Current Sensitivity
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532
MCR12DSM, MCR12DSN
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
http://onsemi.com
533
MCR12LD, MCR12LM, MCR12LN

Preferred Device

Designed primarily for halfwave ac control applications, such as motor controls, heating controls, and power supplies; or wherever halfwave, silicon gatecontrolled devices are needed. Blocking Voltage to 800 Volts OnState Current Rating of 12 Amperes RMS at 80C High Surge Current Capability 100 Amperes Rugged, Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design High Immunity to dv/dt 100 V/sec Minimum at 125C Device Marking: Logo, Device Type, e.g., MCR12LD, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR12LD MCR12LM MCR12LN On-State RMS Current (180 Conduction Angles; TC = 80C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM 12 100 A A Value Unit Volts
http://onsemi.com
G A K
41 5.0 0.5 2.0 40 to 125 40 to 150
A2sec 1 Watts Watt A 2 3 4
PIN ASSIGNMENT
C C Device MCR12LD MCR12LM MCR12LN Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
534
Publication Order Number: MCR12L/D


OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VD = Rated VDRM and VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 0.01 2.0 mA
ON CHARACTERISTICS
Peak Forward OnState Voltage* (ITM = 24 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) Holding Current (VD = 12 V, Gate Open, Initiating Current = 200 mA) Latch Current (VD = 12 V, Ig = 20 mA) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) VTM IGT IH IL VGT 2.0 4.0 6.0 0.5 4.0 10 12 0.65 2.2 8.0 20 30 0.8 Volts mA mA mA Volts
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Critical Rate of Rise of OnState Current IPK = 50 A; Pw = 40 sec; diG/dt = 1 A/sec, Igt = 50 mA *Indicates Pulse Test: Pulse Width dv/dt di/dt 100 250 50 V/s A/s
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535

Symbol
Parameter
10 VGT , GATE TRIGGER VOLTAGE (VOLTS) 5.0 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125 9 GATE TRIGGER CURRENT (mA) 8 7 6 5 4 3 2 1 0 40 25 10
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5.0 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (C) 110 125
100
100
10
IL , LATCHING CURRENT (mA) 5.0 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C) 95 110 125
I H, HOLDING CURRENT (mA)
10
1.0 40 25 10
1.0 40 25 10
5.0
20
35
50
65
80
95
110 125
http://onsemi.com
536

P(AV), AVERAGE POWER DISSIPATION (WATTS) 125 120 TC, CASE TEMPERATURE ( C) 115 110 105 100 dc 95 = 30 90 0 1 2 3 60 90 180 11 12 4 6 8 5 7 9 10 IT(RMS), RMS ON-STATE CURRENT (AMP) = CONDUCTION ANGLE 20 18 16 14 12 10 8 6 4 2 0 0 1 TJ = 125C 2 3 4 5 6 7 8 9 10 11 IT(AV), AVERAGE ON-STATE CURRENT (AMPS) 12 = CONDUCTION ANGLE = 30 90 180
dc
100 70 50 30 20 I T , INSTANTANEOUS ONSTATE CURRENT (AMPS)
10 7.0 5.0 3.0 2.0
125C 25C
1.0 0.7 0.5 0.3 0.2
0.1 0.5 1.0 1.5 2.0 2.5 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) 3.0
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537
MCR16N Silicon Controlled Rectifiers

Designed primarily for halfwave ac control applications, such as motor controls, heating controls, and power supplies; or wherever halfwave, silicon gatecontrolled devices are needed. Blocking Voltage to 800 Volts OnState Current Rating of 16 Amperes RMS High Surge Current Capability 160 Amperes Rugged Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT, and IH Specified for Ease of Design High Immunity to dv/dt 100 V/sec Minimum at 125C Device Marking: Logo, Device Type, e.g., MCR16N, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR16N On-State RMS Current (180 Conduction Angles; TC = 80C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 800 IT(RMS) ITSM 16 160 A A 1 Value Unit Volts 4
Preferred Device
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SCRs 16 AMPERES RMS 800 VOLT
G A K
106 5.0 0.5 2.0 40 to +125 40 to +150
A2sec Watts
PIN ASSIGNMENT
Watts A C C 1 2 3 4 Cathode Anode Gate Anode
Device MCR16N Package TO220AB Shipping 50 Units/Rail
538
MCR16N
Thermal Resistance Junction to Case Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds RJC RJA TL 1.5 62.5 260 C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 0.01 2.0 mA
ON CHARACTERISTICS
Peak Forward OnState Voltage* (ITM = 32 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) Hold Current (Anode Voltage = 12 V, Initiating Current = 200 mA, Gate Open) Latch Current (VD = 12 V, Ig = 200 mA) VTM IGT VGT IH IL 2.0 0.5 4.0 10 0.65 25 30 1.7 20 1.0 40 60 Volts mA Volts mA mA
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Critical Rate of Rise of OnState Current (IPK = 50 A, Pw = 30 s, diG/dt = 1 A/sec, Igt = 50 mA) *Indicates Pulse Test: Pulse Width dv/dt di/dt 100 300 50 V/s A/s
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539
MCR16N
Symbol
Parameter
TC, CASE TEMPERATURE ( C)
120
= CONDUCTION ANGLE
130
32 180 60 90 dc
24
= CONDUCTION ANGLE = 30
110
16
100
90 80 0 2 4 = 30 6 60 8 90 10 180 12 14
dc
0 0 2 4 6 8 10 12 14 16 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
16
IT(RMS), ITRMS ONSTATE CURRENT (AMPS)
Figure 2. On State Power Dissipation
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540
MCR16N
R(t) TRANSIENT THERMAL R (NORMALIZED) 100 Typical @ TJ = 25C 1
Maximum @ TJ = 125C
0.1
ZqJC(t) = RqJC(t) r(t)
I T , INSTANTANEOUS ONSTATE CURRENT (AMPS)
10
0.01 0.1 1 10 100 1000 t, TIME (ms)
1104
Maximum @ TJ = 25C
100 IH, HOLDING CURRENT (mA) 1
10
0.1 0.5 1.3 1.7 2.1 0.9 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) 2.5
100 GATE TRIGGER CURRENT (mA) 40 25 10 5 20 35 50 65 80 95 110 125
30 25 20 15 10 5 0 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
10
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541
MCR16N
1.0 V GT, GATE TRIGGER VOLTAGE (VOLTS) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C) I TSM , PEAK SURGE CURRENT (AMP) 160 1 Cycle 150 140 130 120 110 TJ = 125C f = 60 Hz 100 90 1 2 3 4 5 6 7 8 9 10 NUMBER OF CYCLES
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542
MCR22-6, MCR22-8
Preferred Device

Designed and tested for repetitive peak operation required for CD ignition, fuel ignitors, flash circuits, motor controls and low-power switching applications. 150 Amperes for 2 s Safe Area High dv/dt Very Low Forward On Voltage at High Current Low-Cost TO-226AA (TO-92) Device Marking: Device Type, e.g., MCR226, Date Code
Rating Peak Repetitive OffState Voltage (RGK = IK, TJ = 40 to +110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR226 MCR228 Symbol VDRM, VRRM 400 600 IT(RMS) ITSM 1.5 15 Amps Amps 3 Value Unit Volts
http://onsemi.com
G A K
On-State Current RMS (180 Conduction Angles, TC = 80C) Peak Non-repetitive Surge Current, TA = 25C (1/2 Cycle, Sine Wave, 60 Hz) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 msec, TA = 25C) Forward Average Gate Power (t = 8.3 msec, TA = 25C) Forward Peak Gate Current (Pulse Width 1.0 s, TA = 25C) Reverse Peak Gate Voltage (Pulse Width 1.0 s, TA = 25C) Operating Junction Temperature Range @ Rated VRRM and VDRM Storage Temperature Range
I2t PGM PG(AV) IFGM VRGM TJ Tstg
0.9 0.5 0.1 0.2 5.0 40 to +110 40 to +150
A2s Watt Watt 1 Amp Volts C C 2 3
PIN ASSIGNMENT
Cathode Gate Anode
543
May, 2000 Rev. 2
MCR226, MCR228
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Lead Solder Temperature (Lead Length 1/16 from case, 10 s Max) Symbol RJC RJA TL Max 50 160 +260 Unit C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM; RGK = 1000 Ohms) TC = 25C TC = 110C IDRM, IRRM 10 200 A A
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (ITM = 1 A Peak) Gate Trigger Current (Continuous dc)(2) (VAK = 6 Vdc, RL = 100 Ohms) Gate Trigger Voltage (Continuous dc)(2) (VAK = 7 Vdc, RL = 100 Ohms) Gate NonTrigger Voltage(1) (VAK = 12 Vdc, RL = 100 Ohms) Holding Current (VAK = 12 Vdc, Gate Open) Initiating Current = 200 mA TC = 25C TC = 40C TC = 25C TC = 40C TC = 110C TC = 25C TC = 40C VTM IGT VGT VGD IH 2.0 5.0 10 0.1 1.2 30 1.7 200 500 0.8 1.2 Volts A Volts Volts mA
Critical Rate of Rise of OffState Voltage (TC = 110C) (1) Pulse Width = 1.0 ms, Duty Cycle 1%. (2) RGK Current not included in measurement. dv/dt 25 V/s
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544
MCR226, MCR228
Symbol
Parameter
CURRENT DERATING
TA , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( C) TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
140
140 120 100 80 60 40 20 0 0 dc = 180 = CONDUCTION ANGLE 0.2 0.4 0.6 0.8 1.0 IT(AV), AVERAGE ON-STATE CURRENT (AMP)
100 = 180 = CONDUCTION ANGLE dc
60
20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
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545
MCR226, MCR228
5.0
3.0 2.0 TJ = 110C 25C 1.0 I T , INSTANTANEOUS ON-STATE CURRENT (AMP) 0.7 0.5
0.3 0.2
0.1 0.07 0.05
0.03 0.02
0.01 0 0.5 1.0 1.5 2.0 2.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1
0.2
0.5
1.0
2.0
5.0
10
20
50 t, TIME (ms)
100
200
500
1000
2000
5000
10000
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546
MCR226, MCR228
0.8 VGT, GATE TRIGGER VOLTAGE (VOLTS) I GT GATE TRIGGER CURRENT ( A) 100 110 VAK = 7.0 V RL = 100
100 50 30 20 10 5.0 3.0 2.0 1.0 40
0.7
0.6
0.5
0.4 0.3 75
50
25
25
50
75
20
20
40
60
80
100 110
TJ JUNCTION TEMPERATURE (C)
10 I H , HOLDING CURRENT (mA)
P(AV) MAXIMUM AVERAGE POWER DISSIPATION (WATTS)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 dc 30 60 90 120 180
VAK = 12 V RL = 100 5.0
2.0
0.2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
1.0 40
20
20
40
60
80
100 110
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547
MCR226, MCR228 TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A H2B H2B

Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
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548
MCR226, MCR228
ORDERING & SHIPPING INFORMATION: MCR22 Series packaging options, Device Suffix
U.S. MCR226,8 MCR226RLRA MCR226RLRP MCR228ZL1 Europe Equivalent MCR228RL1 Shipping Radial Tape and Reel (2K/Reel) Bulk in Box (5K/Box) Radial Tape and Reel (2K/Reel) Radial Tape and Fan Fold Box (2K/Box) Radial Tape and Fan Fold Box (2K/Box) Description of TO92 Tape Orientation Flat side of TO92 and adhesive tape visible N/A, Bulk Round side of TO92 and adhesive tape visible Round side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible
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549

Preferred Device

Designed primarily for halfwave ac control applications, such as motor controls, heating controls, and power supplies; or wherever halfwave, silicon gatecontrolled devices are needed. Blocking Voltage to 800 Volts On-State Current Rating of 25 Amperes RMS High Surge Current Capability 300 Amperes Rugged, Economical TO220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT, and IH Specified for Ease of Design High Immunity to dv/dt 100 V/sec Minimum @ 125C Device Marking: Logo, Device Type, e.g., MCR25D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR25D MCR25M MCR25N On-State RMS Current (180 Conduction Angles; TC = 80C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Consideration (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 800 IT(RMS) ITSM 25 300 A A TO220AB CASE 221A STYLE 3 1 2 Value Unit Volts 4
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G A K
373 20.0 0.5 2.0 40 to +125 40 to +150
A2sec Watts Watt A C C
PIN ASSIGNMENT
Device MCR25D MCR25M MCR25N Package TO220AB TO220AB TO220AB Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
550


OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM IRRM mA 0.01 2.0
ON CHARACTERISTICS
Peak Forward On-State Voltage* (ITM = 50 A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) Holding Current (VD =12 Vdc, Initiating Current = 200 mA, Gate Open) Latching Current (VD = 12 V, IG = 30 mA) VTM IGT VGT IH IL 4.0 0.5 5.0 12 0.67 13 35 1.8 30 1.0 40 80 Volts mA Volts mA mA
Critical Rate of Rise of OffState Voltage (VD = 67% of Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) Critical Rate of Rise of OnState Current (IPK = 50 A, Pw = 30 sec, diG/dt = 1 A/sec, Igt = 50 mA) *Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt 100 250 V/s
di/dt
50
A/s
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551

Symbol
Parameter
40 I GT, GATE TRIGGER CURRENT (mA) VGT, GATE TRIGGER VOLTAGE (V) 35 30 25 20 15 10 5 0 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 95 110 125 TJ, JUNCTION TEMPERATURE (C)
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552

I T, INSTANTANEOUS ONSTATE CURRENT (A)
R(t) TRANSIENT THERMAL R (NORMALIZED) 100 Typical @ 25C Maximum @ 125C 1
10 Maximum @ 25C
Z 0.1
qJC(t)
+ RqJC @ R(t)
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9
0.01 0.1 1 10
VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS) Figure 3. Typical OnState Characteristics
100 t, TIME (ms)
1000
1@10 4
100
100
10
10
130
32 28 24 20 16 12 8 4 0 0 2 4 6 8 10 12 14 16 18 IT(AV), AVERAGE ONSTATE CURRENT (AMPS) 20 180 60 90 dc
120
110
a = Conduction
Angle
a = Conduction
Angle
100 dc
a = 30
90 80
a = 30
0
60
90
180 20
2 4 6 8 10 12 14 16 18 IT(RMS), RMS ONSTATE CURRENT (AMPS)
Figure 8. On State Power Dissipation
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553
1200 GateCathode Open, (dv/dt does not depend on RGK) STATIC dv/dt (V/us)
2500 Gate Cathode Open, (dv/dt does not depend on RGK ) 2000
1000
STATIC dv/dt (V/us)
800 85C 600 110C 400 TJ = 125C 100C
1500
VPK = 275
1000 VPK = 600 500 VPK = 800 0 VPK = 400
200
200
300
400
500
600
700
800
80
85
90
VPK , Peak Voltage (Volts)
95 100 105 110 TJ, Junction Temperature (C )
115
120
125
Figure 9. Typical Exponential Static dv/dt Versus Peak Voltage.
Figure 10. Typical Exponential Static dv/dt Versus Junction Temperature.
300 280 260 240 220 200 TJ=125 C f=60 Hz 180 160 1 2 3 4 5 6 7 NUMBER OF CYCLES 8 9 10 1 CYCLE
I TSM, SURGE CURRENT (AMPS)
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554
MCR68-2 Silicon Controlled Rectifiers

Glass-Passivated Junctions for Greater Parameter Stability and
Reliability Center-Gate Geometry for Uniform Current Spreading Enabling High Discharge Current Small Rugged, Thermowatt Package Constructed for Low Thermal Resistance and Maximum Power Dissipation and Durability High Capacitor Discharge Current, 300 Amps Device Marking: Logo, Device Type, e.g., MCR682, Date Code
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Designed for overvoltage protection in crowbar circuits.
SCRs 12 AMPERES RMS 50 VOLTS

G

Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Gate Open) MCR682 Symbol VDRM, VRRM 50 ITM IT(RMS) IT(AV) ITSM 300 12 8.0 100 Amps Amps Amps Value Unit Volts
Peak Discharge Current(2) On-State RMS Current (180 Conduction Angles; TC = 85C) Average On-State Current (180 Conduction Angles; TC = 85C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Current (t 1.0 s, TC = 85C) Forward Peak Gate Power (t 1.0 s, TC = 85C) Forward Average Gate Power (t = 8.3 ms, TC = 85C) Operating Junction Temperature Range Storage Temperature Range Mounting Torque
1 Amps
I2t IGM PGM PG(AV) TJ Tstg
40 2.0 20 0.5 40 to +125 40 to +150 8.0
A2s Amps 1 Watts Watt C 2 3 4
PIN ASSIGNMENT
C in. lb. Device MCR682 Package TO220AB Shipping 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) Ratings apply for tw = 1 ms. See Figure 1 for ITM capability for various duration of an exponentially decaying current waveform, t w is defined as 5 time constants of an exponentially decaying current pulse.
555
MCR682

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak Forward On-State Voltage (ITM = 24 A)(1) (ITM = 300 A, tw = 1 ms)(2) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) Gate NonTrigger Voltage (VD = 12 Vdc, RL = 100 , TJ = 125C) Holding Current (VD = 12 V, Initiating Current = 200 mA, Gate Open) Latching Current (VD = 12 Vdc, IG = 150 mA) Gate Controlled Turn-On Time(3) (VD = Rated VDRM, IG = 150 mA) (ITM = 24 A Peak) VTM IGT VGT VGD IH IL tgt 2.0 0.2 3.0 6.0 7.0 0.65 0.40 15 1.0 2.2 30 1.5 50 60 mA Volts Volts mA mA s Volts
Critical Rate-of-Rise of Off-State Voltage (VD = Rated VDRM, Gate Open, Exponential Waveform, TJ = 125C) Critical Rate-of-Rise of On-State Current IG = 150 mA TJ = 125C dv/dt di/dt 10 75 V/s A/s
(1) Pulse duration 300 s, duty cycle 2%. (2) Ratings apply for tw = 1 ms. See Figure 1 for ITM capability for various durations of an exponentially decaying current waveform. tw is defined as 5 time constants of an exponentially decaying current pulse. (3) The gate controlled turn-on time in a crowbar circuit will be influenced by the circuit inductance.
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556
MCR682
Symbol
Parameter
I TM, PEAK DISCHARGE CURRENT (AMPS)
NORMALIZED PEAK CURRENT
1000
300 200 100 50 20 0.5 ITM tw tw = 5 time constants 1.0 2.0 5.0 10 20 50
1.0 0.8 0.6 0.4 0.2 0 25 50 75 100 125 TC, CASE TEMPERATURE (C)
tw, PULSE CURRENT DURATION (ms)
Figure 1. Peak Capacitor Discharge Current
Figure 2. Peak Capacitor Discharge Current Derating
125 TC , MAXIMUM CASE TEMPERATURE ( C) 120 115 110 dc
20 18 Half Wave
14
dc
105 100 95 90 85 80 75 1.0 2.0 5.0 8.0 10 IT(AV), AVERAGE ON-STATE CURRENT (AMPS) Half Wave
10 8.0 TJ = 125C
4.0 2.0 1.0 2.0 4.0 5.0 8.0 IT(AV), AVERAGE ON-STATE CURRENT (AMPS) 10
Figure 4. Maximum Power Dissipation
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557
MCR682
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1k 2k 3k 5k 10 k ZJC(t) = RJC r(t)
t, TIME (ms)
10 NORMALIZED GATE TRIGGER CURRENT NORMALIZED GATE TRIGGER VOLTAGE 1.4 VD = 12 Volts RL = 100 5.0 3.0 2.0 1.0 0.5 0.3 0.2 60 40 20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140 VD = 12 Volts RL = 100
1.2
1.0
0.8
0.5 60
40
20
20
40
60
80
100
120
140
Figure 6. Gate Trigger Current
Figure 7. Gate Trigger Voltage
3.0 NORMALIZED HOLD CURRENT 2.0 VD = 12 Volts ITM = 100 mA 1.0 0.8
0.5
0.3 60
40
20
20
40
60
80
100
120
140
Figure 8. Holding Current
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558
MCR69-2, MCR69-3 Silicon Controlled Rectifiers

Glass-Passivated Junctions for Greater Parameter Stability and Center-Gate Geometry for Uniform Current Spreading Enabling Small Rugged, Thermowatt Package Constructed for Low Thermal
Resistance and Maximum Power Dissipation and Durability High Capacitor Discharge Current, 750 Amps Device Marking: Logo, Device Type, e.g., MCR692, Date Code High Discharge Current Reliability
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Designed for overvoltage protection in crowbar circuits.

G A K

Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Gate Open) MCR692 MCR693 Symbol VDRM, VRRM 50 100 ITM IT(RMS) IT(AV) ITSM 750 25 16 300 Amps Amps Amps Value Unit Volts
Peak Discharge Current(2) On-State RMS Current (180 Conduction Angles; TC = 85C) Average On-State Current (180 Conduction Angles; TC = 85C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 125C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Current (t 1.0 s, TC = 85C) Forward Peak Gate Power (t 1.0 s, TC = 85C) Forward Average Gate Power (t = 8.3 ms, TC = 85C) Operating Junction Temperature Range Storage Temperature Range Mounting Torque
1 Amps
I2t IGM PGM PG(AV) TJ Tstg
375 2.0 20 0.5 40 to +125 40 to +150 8.0
A2s Amps 1 Watts Watt C 2 3 4
PIN ASSIGNMENT
C in. lb. Device MCR692 MCR693 Package TO220AB TO220AB Shipping 500/Box 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) Ratings apply for tw = 1 ms. See Figure 1 for ITM capability for various duration of an exponentially decaying current waveform, t w is defined as 5 time constants of an exponentially decaying current pulse. (3) Test Conditions: IG = 150 mA, VD = Rated VDRM, ITM = Rated Value, TJ = 125 C.
559
MCR692, MCR693

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak Forward On-State Voltage (ITM = 50 A)(1) (ITM = 750 A, tw = 1 ms)(2) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 ) Gate NonTrigger Voltage (VD = 12 Vdc, RL = 100 , TJ = 125C) Holding Current (VD = 12 V, Initiating Current = 200 mA, Gate Open) Latching Current (VD = 12 Vdc, IG = 150 mA) Gate Controlled Turn-On Time(3) (VD = Rated VDRM, IG = 150 mA) (ITM = 50 A Peak) VTM IGT VGT VGD IH IL tgt 2.0 0.2 3.0 6.0 7.0 0.65 0.40 15 1.0 1.8 30 1.5 50 60 mA Volts Volts mA mA s Volts
Critical Rate-of-Rise of Off-State Voltage (VD = Rated VDRM, Gate Open, Exponential Waveform, TJ = 125C) Critical Rate-of-Rise of On-State Current IG = 150 mA TJ = 125C dv/dt di/dt 10 100 V/s A/s
(1) Pulse duration 300 s, duty cycle 2%. (2) Ratings apply for tw = 1 ms. See Figure 1 for ITM capability for various durations of an exponentially decaying current waveform. tw is defined as 5 time constants of an exponentially decaying current pulse. (3) The gate controlled turn-on time in a crowbar circuit will be influenced by the circuit inductance.
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560
MCR692, MCR693
Symbol
Parameter
I TM, PEAK DISCHARGE CURRENT (AMPS)
NORMALIZED PEAK CURRENT
1000
300 200 100 50 20 0.5 ITM tw tw = 5 time constants 1.0 2.0 5.0 10 20 50
1.0 0.8 0.6 0.4 0.2 0 25 50 75 100 125 TC, CASE TEMPERATURE (C)
tw, PULSE CURRENT DURATION (ms)
Figure 1. Peak Capacitor Discharge Current
Figure 2. Peak Capacitor Discharge Current Derating
125 120 115 110 dc
32 Half Wave 24
105 100 95 90 85 80 75 4.0 8.0 12
dc 16
Half Wave
8.0
TJ = 125C
0 0 4.0 8.0 12 16 20 IT(AV), AVERAGE ON-STATE CURRENT (AMPS)
16
20
Figure 4. Maximum Power Dissipation
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561
MCR692, MCR693
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1k 2k 3k 5k 10 k ZJC(t) = RJC r(t)
t, TIME (ms)
10 NORMALIZED GATE TRIGGER CURRENT NORMALIZED GATE TRIGGER VOLTAGE 1.4 VD = 12 Volts RL = 100 5.0 3.0 2.0 1.0 0.5 0.3 0.2 60 40 20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 140 VD = 12 Volts RL = 100
1.2
1.0
0.8
0.5 60
40
20
20
40
60
80
100
120
140
Figure 6. Gate Trigger Current
Figure 7. Gate Trigger Voltage
3.0 NORMALIZED HOLD CURRENT 2.0 VD = 12 Volts ITM = 100 mA 1.0 0.8
0.5
0.3 60
40
20
20
40
60
80
100
120
140
Figure 8. Holding Current
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562
MCR72-3, MCR72-6, MCR72-8

Preferred Device

Designed for industrial and consumer applications such as temperature, light and speed control; process and remote controls; warning systems; capacitive discharge circuits and MPU interface. Center Gate Geometry for Uniform Current Density All Diffused and Glass-Passivated Junctions for Parameter Uniformity and Stability Small, Rugged Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Low Trigger Currents, 200 A Maximum for Direct Driving from Integrated Circuits Device Marking: Logo, Device Type, e.g., MCR723, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR723 MCR726 MCR728 Symbol VDRM, VRRM 100 400 600 IT(RMS) ITSM I2t VGM IGM PGM PG(AV) TJ Tstg 8.0 100 40 Amps Amps Value Unit Volts 1
http://onsemi.com

G A K
On-State RMS Current (180 Conduction Angles; TC = 83C) Peak Non-Repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = 110C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Voltage (t 10 s, TC = 83C) Forward Peak Gate Current (t 10 s, TC = 83C) Forward Peak Gate Power (t 10 s, TC = 83C) Average Gate Power (t = 8.3 ms, TC = 83C) Operating Junction Temperature Range Storage Temperature Range Mounting Torque
PIN ASSIGNMENT
A2s Volts Amp Watts Watt C C in. lb. 1 2 3 4 Cathode Anode Gate Anode
"5.0
1.0 5.0 0.75 40 to +110 40 to +150 8.0
Device MCR723 MCR726 MCR728 Package TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box
563
MCR723, MCR726, MCR728


OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current(1) (VAK = Rated VDRM or VRRM; RGK = 1 k) TJ = 25C TJ = 110C IDRM, IRRM 10 500 A A
ON CHARACTERISTICS
Peak Forward On-State Voltage (ITM = 16 A Peak, Pulse Width
VTM IGT VGT VGD IH tgt
0.1
1.7 30 0.5 1.0
2.0 200 1.5 6.0
Volts A Volts Volts mA s
Gate Trigger Current (Continuous dc)(2) (VD = 12 V, RL = 100 ) Gate Trigger Voltage (Continuous dc)(2) (VD = 12 V, RL = 100 ) Gate NonTrigger Voltage (VD = 12 Vdc, RL = 100 , TJ = 110C) Holding Current (VD = 12 V, Initiating Current = 200 mA, Gate Open) Gate Controlled Turn-On Time (VD = Rated VDRM, ITM = 16 A, IG = 2 mA)
Critical Rate-of-Rise of Off-State Voltage (VD = Rated VDRM, RGK = 1 k, TJ = 110C, Exponential Waveform) dv/dt 10 V/s
(1) Ratings apply for negative gate voltage or R GK = 1 k. Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. (2) RGK current not included in measurement.
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564
MCR723, MCR726, MCR728

Symbol
Parameter
PAV , AVERAGE POWER DISSIPATION (WATTS)
T C , MAXIMUM CASE TEMPERATURE ( C)
110
16 dc 12 = Conduction Angle 8.0 = 30 60 90 180
100 90 = 30 60 90 180 dc 70 = Conduction Angle
80
4.0
2.0
4.0
6.0
8.0
2.0
4.0
6.0
8.0
3.0 VGT , GATE TRIGGER VOLTAGE (VOLTS) NORMALIZED GATE CURRENT 2.0 VD = 12 Vdc 0.7 0.6 0.5 0.4 0.3 0.2 0.1 60 40 20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (C) 120 VD = 12 Vdc
1.0
0.5
0.3 40
20
120
140
Figure 3. Normalized Gate Current
Figure 4. Gate Voltage
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565
MCR100 Series Sensitive Gate Silicon Controlled Rectifiers

PNPN devices designed for high volume, line-powered consumer applications such as relay and lamp drivers, small motor controls, gate drivers for larger thyristors, and sensing and detection circuits. Supplied in an inexpensive plastic TO-226AA package which is readily adaptable for use in automatic insertion equipment. Sensitive Gate Allows Triggering by Microcontrollers and Other Logic Circuits Blocking Voltage to 600 Volts OnState Current Rating of 0.8 Amperes RMS at 80C High Surge Current Capability 10 Amperes Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design Immunity to dV/dt 20 V/sec Minimum at 110C Glass-Passivated Surface for Reliability and Uniformity Device Marking: Device Type, e.g., for MCR1003: 1003, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave, 50 to 60 Hz; Gate Open) MCR1003 MCR1004 MCR1006 MCR1008 Symbol VDRM, VRRM Value Unit Volts 100 200 400 600 0.8 10 Amp Amps 1 I2t PGM PG(AV) IGM VGRM TJ Tstg 0.415 0.1 0.10 1.0 5.0 40 to 110 40 to 150 A2s Watt Watt 2 3 3 2 1
Preferred Device
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G A K
On-State RMS Current (TC = 80C) 180 Conduction Angles Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 25C) Circuit Fusing Consideration (t = 8.3 ms) Forward Peak Gate Power (TA = 25C, Pulse Width
IT(RMS) ITSM
PIN ASSIGNMENT
Cathode Gate Anode
v 1.0 s) v v
Forward Average Gate Power (TA = 25C, t = 8.3 ms) Forward Peak Gate Current (TA = 25C, Pulse Width 1.0 s) Reverse Peak Gate Voltage (TA = 25C, Pulse Width 1.0 s) Operating Junction Temperature Range @ Rate VRRM and VDRM Storage Temperature Range
Amp Volts C C
566
May, 2000 Rev. 3
MCR100 Series
Characteristic Thermal Resistance Junction to Case Junction to Ambient Lead Solder Temperature ( 1/16 from case, 10 secs max) Symbol RJC RJA TL Max 75 200 260 Unit C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current(1) (VD = Rated VDRM and VRRM; RGK = 1 k) TC = 25C TC = 110C IDRM, IRRM 10 100 A
ON CHARACTERISTICS
Peak Forward OnState Voltage(*) (ITM = 1.0 Amp Peak @ TA = 25C) Gate Trigger Current (Continuous dc)(2) (VAK = 7.0 Vdc, RL = 100 Ohms) Holding Current (2) (VAK = 7.0 Vdc, Initiating Current = 20 mA) Latch Current (VAK = 7.0 V, Ig = 200 A) Gate Trigger Voltage (Continuous dc)(2) (VAK = 7.0 Vdc, RL = 100 Ohms) TC = 40C VTM TC = 25C TC = 25C TC = 40C TC = 25C TC = 40C TC = 25C IGT IH IL VGT 40 0.5 0.6 0.62 1.7 200 5.0 10 10 15 0.8 1.2 Volts A mA mA Volts
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, Exponential Waveform, RGK = 1000 Ohms, TJ = 110C) Critical Rate of Rise of OnState Current (IPK = 20 A; Pw = 10 sec; diG/dt = 1 A/sec, Igt = 20 mA) *Indicates Pulse Test: Pulse Width 1.0 ms, Duty Cycle 1%. (1) RGK = 1000 Ohms included in measurement. (2) Does not include RGK in measurement. dV/dt 20 35 V/s
di/dt
50
A/s
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567
MCR100 Series
Symbol
Parameter
100 GATE TRIGGER VOLTAGE (VOLTS) 95 90 GATE TRIGGER CURRENT ( m A) 80 70 60 50 40 30 20 10 40 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C) 110
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 40 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C) 95 110
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568
MCR100 Series
1000 1000
100
LATCHING CURRENT ( m A) 95 110
HOLDING CURRENT (m A)
100
10 40 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C)
10 40 25 10 5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C)
95
110
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
120 110 100 90 DC 80 70 60 50 40 0 0.1 30 60 90 120 0.5 180
10 MAXIMUM @ TJ = 25C MAXIMUM @ TJ = 110C
0.2 0.3 0.4 IT(RMS), RMS ON-STATE CURRENT (AMPS)
0.1
0.5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 3.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
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569
MCR100 Series TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL
H2A H2A H2B H2B

Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
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570
MCR100 Series
ORDERING & SHIPPING INFORMATION: MCR100 Series packaging options, Device Suffix
U.S. MCR1003,4,6,8 MCR1006RLRA MCR1006RLRM Europe Equivalent MCR1003RL,6RL,8RL MCR1006ZL1 Shipping Bulk in Box (5K/Box) Radial Tape and Reel (2K/Reel) Radial Tape and Fan Fold Box (2K/Box) Description of TO92 Tape Orientation N/A, Bulk Round side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible
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571
MCR106-6, MCR106-8
Preferred Device

PNPN devices designed for high volume consumer applications such as temperature, light and speed control; process and remote control, and warning systems where reliability of operation is important. Glass-Passivated Surface for Reliability and Uniformity Power Rated at Economical Prices Practical Level Triggering and Holding Characteristics Flat, Rugged, Thermopad Construction for Low Thermal Resistance, High Heat Dissipation and Durability Device Marking: Device Type, e.g., MCR1066, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 110C, Sine Wave 50 to 60 Hz, Gate Open) MCR1066 MCR1068 On-State RMS Current (TC = 93C) (180 Conduction Angles) Average OnState Current (180 Conduction Angles; TC = 93C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 110C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Power (TC = 93C, Pulse Width Symbol VDRM, VRRM 400 600 IT(RMS) IT(AV) ITSM 4.0 2.55 25 Amps Amps Amps 3 Value Unit Volts A
http://onsemi.com

G K
2 1
I2t PGM PG(AV) IGM VRGM TJ Tstg
2.6 0.5 0.1 0.2 6.0 40 to +110 40 to +150 6.0
A2s Watt Watt 1 Amp Volts C C in. lb. 2 3
v 1.0 s) v 1.0 s) v 1.0 s)
Forward Average Gate Power (TC = 93C, t = 8.3 ms) Forward Peak Gate Current (TC = 93C, Pulse Width
PIN ASSIGNMENT
Cathode Anode Gate
Peak Reverse Gate Voltage (TC = 93C, Pulse Width
Device MCR1066 MCR1068 Package TO225AA TO225AA Shipping 500/Box 500/Box
Operating Junction Temperature Range Storage Temperature Range Mounting Torque(2)
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) Torque rating applies with use of compression washer (B52200-F006 or equivalent). Mounting torque in excess of 6 in. lb. does not appreciably lower case-to-sink thermal resistance. Anode lead and heatsink contact pad are common. (See AN209B). For soldering purposes (either terminal connection or device mounting), soldering temperatures shall not exceed +200C. For optimum results, an activated flux (oxide removing) is recommended.
572
May, 2000 Rev. 3
MCR1066, MCR1068

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM; RGK = 1000 Ohms) TJ = 25C TJ = 110C IDRM, IRRM 10 200 A A
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (ITM = 4 A Peak) Gate Trigger Current (Continuous dc)(2) (VAK = 7 Vdc, RL = 100 Ohms) (TC = 40C) Gate Trigger Voltage (Continuous dc)(2) (VAK = 7 Vdc, RL = 100 Ohms) Gate Non-Trigger Voltage(2) (VAK = 12 Vdc, RL = 100 Ohms, TJ = 110C) Holding Current (VAK = 7 Vdc, Initiating Current = 200 mA, Gate Open) VTM IGT VGT VGD IH 0.2 200 500 1.0 5.0 Volts Volts mA 2.0 Volts A
Critical RateofRise of OffState Voltage (TJ = 110C) (1) Pulse Test: Pulse Width 1.0 ms, Duty Cycle 1%. (2) RGK current is not included in measurement. dv/dt 10 V/s
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573
MCR1066, MCR1068
Symbol
Parameter
CURRENT DERATING
110 TA , MAXIMUM ALLOWABLE AMBIENTTEMPERATURE ( C) TC , MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)
110
106 102 98 94 90 = 30 86 82 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 IT(AV), AVERAGE FORWARD CURRENT (AMP) 3.6 4.0 60 90 120 180 dc 0
90 0 70 f = 60 Hz
f = 60 Hz
50 = 30 30 0 0.1 60 90 180
dc 0.8
0.2 0.3 0.4 0.5 0.6 0.7 IT(AV), AVERAGE FORWARD CURRENT (AMP)
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574
MCR218-2, MCR218-4, MCR218-6

Preferred Device

Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supplies; or wherever half-wave silicon gate-controlled, solid-state devices are needed. Glass-Passivated Junctions Blocking Voltage to 400 Volts TO-220 Construction Low Thermal Resistance, High Heat Dissipation and Durability Device Marking: Logo, Device Type, e.g., MCR2182, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Gate Open) MCR2182 MCR2184 MCR2186 Symbol VDRM, VRRM 50 200 400 IT(RMS) ITSM 8.0 100 A A 1 Value Unit Volts 4
http://onsemi.com

G A K
On-State RMS Current (180 Conduction Angles; TC = 70C) Peak Non-repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing Considerations (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 70C) Forward Average Gate Power (t = 8.3 ms, TC = 70C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 70C) Operating Junction Temperature Range Storage Temperature Range
26 5.0 0.5 2.0 40 to +125 40 to +150
A2s Watts
PIN ASSIGNMENT
Watts A C C 1 2 3 4 Cathode Anode Gate Anode
Device Package TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box
MCR2182 MCR2184 MCR2186
575
March, 2000 Rev. 2
MCR2182, MCR2184, MCR2186

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted.)

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak Forward On-State Voltage(1) (ITM = 16 A Peak) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 Ohms) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ohms) Gate NonTrigger Voltage (Rated 12 V, RL = 100 Ohms, TJ = 125C) Holding Current (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) VTM IGT VGT VGD IH 0.2 1.5 10 16 1.8 25 1.5 30 Volts mA Volts Volts mA
Critical Rate-of-Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C) (1) Pulse Test: Pulse Width = 1.0 ms, Duty Cycle 2%. dv/dt 100 V/s
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576
MCR2182, MCR2184, MCR2186

Symbol
Parameter
P(AV), AVERAGE ON-STATE POWER DISSIPATION (WATTS)
125
15
115
= CONDUCTION ANGLE
12
= Conduction Angle 120 60 = 30 90 180 dc
105
9.0
95 dc = 30 0 1 2 60 3 90 120 4 180 5 6 7 8
6.0
85 75
3.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 IT(AV), AVG. ON-STATE CURRENT (AMPS) 7.0 8.0
IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)
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577
MCR2182, MCR2184, MCR2186

I GT , NORMALIZED GATE TRIGGER CURRENT (mA) V GT , NORMALIZED GATE TRIGGER VOLTAGE 3.0 2.0 VD = 12 Vdc 1.5 1.0 0.9 0.7 0.5 0.4 0.3 60 40 20 0 20 40 60 80 100 120 140 1.3 1.2
VD = 12 Vdc 1.0 0.9 0.7 0.5 0.4 0.3 60 40 20 0 20 40 60 80 100 120 140
I H , NORMALIZED HOLDING CURRENT (mA)
4.0 3.0 2.0 VD = 12 Vdc 1.5 1.0 0.9 0.7 0.5 0.4 60 40 20 0 20 40 60 80 100 120 140
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578
MCR218-6FP, MCR218-10FP
Preferred Device

Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supply crowbar circuits. Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 800 Volts 80 A Surge Current Capability Insulated Package Simplifies Mounting Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MCR2186, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave 50 to 60 Hz, Gate Open) MCR2186FP MCR21810FP On-State RMS Current (TC = +70C)(2) (180 Conduction Angles) Peak Nonrepetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Circuit Fusing (t = 8.3 ms) Forward Peak Gate Power (TC = +70C, Pulse Width Symbol VDRM, VRRM 400 800 IT(RMS) ITSM 8.0 100 Amps Amps Value Unit Volts
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ISOLATED SCRs ( 8 AMPERES RMS 400 thru 800 VOLTS
G A K
1 2 3
I2t
26 5.0 0.5 2.0 1500 40 to +125 40 to +150
A2s Watts Watt 1 Amps Volts C C
v 1.0 s) v 1.0 s)
PGM PG(AV) IGM V(ISO) TJ Tstg
Forward Average Gate Power (TC = +70C, t = 8.3 ms) Forward Peak Gate Current (TC = +70C, Pulse Width
PIN ASSIGNMENT
Cathode Anode Gate 2 3
Device MCR2186FP MCR21810FP Package ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) The case temperature reference point for all TC measurements is a point on the center lead of the package as close as possible to the plastic body.
579
Publication Order Number: MCR218FP/D
MCR2186FP, MCR21810FP
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Case to Sink Thermal Resistance, Junction to Ambient Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RCS RJA TL Max 2 2.2 (typ) 60 260 Unit C/W C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VD = Rated VDRM, Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2 A mA
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (ITM = 16 A Peak) Gate Trigger Current (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) Gate Trigger Voltage (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) Gate Non-Trigger Voltage (VAK = 12 Vdc, RL = 100 Ohms, TJ = 125C) Holding Current (VAK = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (ITM = 8 A, IGT = 40 mAdc) Turn-Off Time (VD = Rated VDRM, ITM = 8 A, IR = 8 A) TJ = 25C TJ = 125C VTM IGT VGT VGD IH tgt tq 15 35 0.2 1 10 16 1.5 1.8 25 1.5 30 Volts mA Volts Volts mA s s
Critical Rate-of-Rise of Off-State Voltage (Gate Open, VD = Rated VDRM, Exponential Waveform) (1) Pulse Test: Pulse Width = 1 ms, Duty Cycle dv/dt 100 V/s
p 2%.
http://onsemi.com
580
Symbol
Parameter
125
P(AV) , AVERAGE ON-STATE POWER DISSIPATION (WATTS)
15
115 a 105 = CONDUCTION ANGLE
12
a = CONDUCTION ANGLE 60 = 30 90 120 180 dc
95 dc 85 75 0 = 30 1 2 60 3 90 120 4 180 5 6 7 8
3 0 0 1 2 3 4 5 6 7 8 IT(AV), AVG. ON-STATE CURRENT (AMPS)
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581
100 70 50 30 i F , INSTANTANEOUS ON-STATE FORWARD CURRENT (AMP) 20 TJ = 25C 125C
10 7 5 3 2 80 1 0.7 0.5 0.3 0.2 I TSM , PEAK SURGE CURRENT (AMP) 1 CYCLE 75
70
65 TC = 85C f = 60 Hz 60 SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 55 1 2 3 4 6 8 10 NUMBER OF CYCLES
0.1 0.4
1.2
2.8
3.6
4.4
5.2
v F, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
Figure 3. Maximum On-State Characteristics
Figure 4. Maximum Non-Repetitive Surge Current
1 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 t, TIME (ms) 100 200 300 500 1.0 k 2.0 k 3.0 k 5.0 k 10 k ZJC(t) = RJC r(t)
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582
I GT, GATE TRIGGER CURRENT (NORMALIZED) 2 VD = 12 V VGT , GATE TRIGGER VOLTAGE (NORMALIZED) 2 VD = 12 V 1.6
1.6
1.2
1.2
0.8
0.8
0.4 0 60
0.4 0 60
40
20
20
40
60
80
100
120
140
40
20
20
40
60
80
100
120
140

2 IH , HOLDING CURRENT (NORMALIZED)
VD = 12 V 1.6
1.2
0.8
0.4 0 60
40
20
20
40
60
80
100
120
140
http://onsemi.com
583
MCR225-8FP, MCR225-10FP
Preferred Device

Designed primarily for half-wave ac control applications, such as motor controls, heating controls and power supply crowbar circuits. Glass Passivated Junctions with Center Gate Fire for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Constructed for Low Thermal Resistance, High Heat Dissipation and Durability Blocking Voltage to 800 Volts 300 A Surge Current Capability Insulated Package Simplifies Mounting Indicates UL Registered File #E69369 Device Marking: Logo, Device Type, e.g., MCR2258FP, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR2258FP MCR22510FP On-State RMS Current (TC = +70C) (180 Conduction Angles) Peak Nonrepetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TC = +70C) Circuit Fusing (t = 8.3 ms) Forward Peak Gate Power (TC = +70C, Pulse Width Symbol VDRM, VRRM 600 800 IT(RMS) ITSM 25 300 Amps Amps 1 2 I2t 375 20 0.5 2.0 1500 40 to +125 40 to +150 A2s Watts Watt Amps Volts C C 1 2 V(ISO) TJ Tstg 3 3 Value Unit Volts
http://onsemi.com
ISOLATED SCRs ( 25 AMPERES RMS 600 thru 800 VOLTS
G A K
v 1.0 s) v 1.0 s)
PGM PG(AV) IGM
Forward Average Gate Power (TC = +70C, t = 8.3 ms) Forward Peak Gate Current (TC = +70C, Pulse Width
PIN ASSIGNMENT
Cathode Anode Gate
Device MCR2258FP MCR22510FP Package ISOLATED TO220FP ISOLATED TO220FP Shipping 500/Box 500/Box
584
Publication Order Number: MCR225FP/D

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 125C IDRM, IRRM 10 2 A mA
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (ITM = 50 A) Gate Trigger Current (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) Gate Trigger Voltage (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) Gate Non-Trigger Voltage (VAK = 12 Vdc, RL = 100 Ohms, TJ = 125C) Holding Current (VAK = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (ITM = 25 A, IGT = 40 mAdc) Turn-Off Time (VDRM = Rated Voltage) (ITM = 25 A, IR = 25 A) (ITM = 25 A, IR = 25 A, TJ = 125C) VTM IGT VGT VGD IH tgt tq 15 35 0.2 0.8 20 1.5 1.8 40 1.5 40 Volts mA Volts Volts mA s s
Critical Rate-of-Rise of Off-State Voltage (Gate Open, VD = Rated VDRM, Exponential Waveform) (1) Pulse Test: Pulse Width = 1.0 ms, Duty Cycle 2%. dv/dt 100 V/s
http://onsemi.com
585
Symbol
Parameter
130 TC, MAXIMUM CASE TEMPERATURE ( C) P(AV) , AVERAGE POWER (WATTS)
32 180 60 90 dc
120
= CONDUCTION ANGLE
24
= CONDUCTION ANGLE = 30
110
16 TJ = 125C
100 = 30 60 90 180 dc
90 80 0
0 4 8 12 16 20 0 4 8 12 16 20 IT(AV), ON-STATE FORWARD CURRENT (AMPS) IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)
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586
100 70 50 30 125C 20 i F , INSTANTANEOUS FORWARD CURRENT (AMPS) 25C
10 7 5 3 2
300 1 0.7 0.5 0.3 0.2 I TSM , PEAK SURGE CURRENT (AMP) 1 CYCLE 275
250
225 TC = 85C f = 60 Hz 200 SURGE IS PRECEDED AND FOLLOWED BY RATED CURRENT 175 1 2 3 4 6 8 10
0.1 0 0.4 0.8 1.2 1.6 2 vF, INSTANTANEOUS VOLTAGE (VOLTS) 2.4 2.8
NUMBER OF CYCLES
Figure 3. Maximum Forward Voltage
Figure 4. Maximum Non-Repetitive Surge Current
1 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 0.2 0.3 0.5 1 2 3 5 10 50 20 30 t, TIME (ms) 100 200 300 500 1.0 k 2.0 k 3.0 k 5.0 k 10 k ZJC(t) = RJC r(t)
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587
I GT, GATE TRIGGER CURRENT (NORMALIZED) 2 VD = 12 V VGT , GATE TRIGGER VOLTAGE (NORMALIZED) 2 VD = 12 V 1.6
1.6
1.2
1.2
0.8
0.8
0.4 0 60
0.4 0 60
40
20
20
40
60
80
100
120
140
40
20
20
40
60
80
100
120
140
2 IH , HOLDING CURRENT (NORMALIZED) VD = 12 V 1.6
1.2
0.8
0.4 0 60
40
20
20
40
60
80
100
120
140
http://onsemi.com
588
MCR264-4, MCR264-6, MCR264-8

Preferred Device

Designed for back-to-back SCR output devices for solid state relays or applications requiring high surge operation. Photo Glass Passivated Blocking Junctions for High Temperature Stability, Center Gate for Uniform Parameters 400 Amperes Surge Capability Blocking Voltage to 600 Volts Device Marking: Logo, Device Type, e.g., MCR2644, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to 125C, Sine Wave 50 to 60 Hz; Gate Open) MCR2644 MCR2646 MCR2648 Symbol VDRM, VRRM 200 400 600 IT(RMS) IT(AV) ITSM 400 450 PGM PG(AV) IGM TJ Tstg 20 0.5 2.0 40 to +125 40 to +150 Watts 1 Watt A C C 2 3 4 40 25 A A A Value Unit Volts
http://onsemi.com

G A K
On-State RMS Current (TC = 80C; 180 Conduction Angles) Average On-State Current (TC = 80C; 180 Conduction Angles) Peak Non-repetitive Surge Current (TC = 80C) (1/2 Cycle, Sine Wave 60 Hz, TJ = 125C) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 80C) Forward Average Gate Power (t = 8.3 ms, TC = 80C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 80C) Operating Junction Temperature Range Storage Temperature Range
PIN ASSIGNMENT
Device MCR2644 MCR2646 MCR2648 Package TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. These devices are rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device is to be used at high sustained currents.
589
MCR2644, MCR2646, MCR2648


OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM, Gate Open) TJ = 25C TJ = 125C I DRM , I RRM 10 2.0 A mA
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (ITM = 80 A) Gate Trigger Current (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms, TC = 40C) Gate Trigger Voltage (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) Gate Non-Trigger Voltage (VAK = 12 Vdc, RL = 100 Ohms, TJ = 125C) Holding Current (VAK = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (ITM = 40 A, IGT = 60 mAdc) VTM IGT VGT VGD IH tgt 0.2 1.4 15 30 1.0 30 1.5 2.0 50 90 1.5 60 Volts mA Volts Volts mA s
Critical Rate-of-Rise of Off-State Voltage (Gate Open, VD = Rated VDRM, Exponential Waveform) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. dv/dt 50 V/s
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590
MCR2644, MCR2646, MCR2648

Symbol
Parameter
125 = CONDUCTION ANGLE P(AV) , AVERAGE POWER (WATTS)
50 45 40 35 30 25 20 15 10 5.0 0 0 5.0 10 15 20 = 30 60 90
180
115
105 dc 95 = 30 60 90 0 5.0 10 15 20 180 25
dc
85 75
= CONDUCTIVE ANGLE 25
IT(AV), ON-STATE FORWARD CURRENT (AMPS)
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591
MCR2644, MCR2646, MCR2648

40 VGT , GATE TRIGGER VOLTAGE (VOLTS) I GT , GATE TRIGGER CURRENT (mA) 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 60 OFF-STATE VOLTAGE = 12 V
OFF-STATE VOLTAGE = 12 V 20
10 7.0 5.0 4.0 60 40 20 0 20 40 60 80 100 120 140
40
20
20
40
60
80
100
120
140

IF , INSTANTANEOUS FORWARD CURRENT (AMPS) 70 IH , HOLDING CURRENT (mA) 50 OFF-STATE VOLTAGE = 12 V 100
30 20
TJ = 25C 10
10 7.0 60
1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 vF, INSTANTANEOUS VOLTAGE (VOLTS)
40
20
20
40
60
80
100
120
140

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1
ZJC(t) = RJC r(t)
0.2 0.3
0.5
1.0
2.0 3.0
5.0
10
20
30
50
100
200 300
500
1k
2k 3k
5k
10 k
t, TIME (ms)
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592
MCR265-4 Series
Preferred Device

Designed for inverse parallel SCR output devices for solid state relays, welders, battery chargers, motor controls or applications requiring high surge operation. Photo Glass Passivated Blocking Junctions for High Temperature Stability, Center Gate for Uniform Parameters 550 Amperes Surge Capability Blocking Voltage to 800 Volts Device Marking: Logo, Device Type, e.g., MCR2654, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 25 to 125C, Sine Wave, 50 to 60 Hz, Gate Open) MCR2654 MCR2656 MCR2658 MCR26510 On-State RMS Current (180 Conduction Angles; TC = 70C) Average On-State Current (180 Conduction Angles; TC = 70C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 70C) Forward Peak Gate Power (Pulse Width 1.0 s, TC = 70C) Forward Average Gate Power (t = 8.3 ms, TC = 70C) Forward Peak Gate Current (Pulse Width 1.0 s, TC = 70C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 200 400 600 800 IT(RMS) IT(AV) ITSM 55 35 550 Amps Amps Amps 1 Value Unit Volts
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G A K
PGM PG(AV) IGM TJ Tstg
20 0.5 2.0 40 to +125 40 to +150
Watts
PIN ASSIGNMENT
Watt Amps C C 1 2 3 4 Cathode Anode Gate Anode
Device MCR2654 MCR2656 MCR2658 MCR26510 Package TO220AB TO220AB TO220AB TO220AB Shipping 500/Box 500/Box 500/Box 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; however, positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. These devices are rated for use in applications subject to high surge conditions. Care must be taken to insure proper heat sinking when the device is to be used at high sustained currents.
593
MCR2654 Series

OFF CHARACTERISTICS
ON CHARACTERISTICS
Peak Forward OnState Voltage(1) (ITM = 110 A) Gate Trigger Current (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) (TC = 40C) Gate Trigger Voltage (Continuous dc) (VAK = 12 Vdc, RL = 100 Ohms) Gate Non-Trigger Voltage (VAK = 12 Vdc, RL = 100 Ohms, TJ = 125C) Holding Current (VAK = 12 Vdc, Initiating Current = 200 mA, Gate Open) Turn-On Time (ITM = 55 A, IGT = 200 mAdc) VTM IGT VGT VGD IH tgt 0.2 20 40 1.0 30 1.5 50 90 1.5 75 Volts Volts mA s 1.5 1.9 Volts mA
Critical Rate-of-Rise of Off-State Voltage (Gate Open, VD = Rated VDRM, Exponential Waveform) (1) Pulse Width dv/dt 50 V/s
p 300 s, Duty Cycle p 2%.
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594
MCR2654 Series
Symbol
Parameter
125 121 117 113 109 105 101 97 93 89 85 81 77 73 69 0
60 P(AV) , AVERAGE POWER (WATTS) 54 48 42 36 30 24 18 12 6.0 0 4.0 8.0 12 16 20 24 28 32 36 40 0 5.0 10 15 20 25 30 = 30 dc 60 90
180
= CONDUCTION ANGLE = 30 dc
60
90
180
= CONDUCTION ANGLE 35 40
IT(AV), AVERAGE ON-STATE FORWARD CURRENT (AMPS)*
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595
MCR2654 Series
2.5 2.0 NORMALIZED GATE CURRENT 1.5 1.0 0.7 0.5 0.4 NORMALIZED GATE VOLTAGE VD = 12 Vdc 2.0 VD = 12 Vdc 1.5 1.0 0.8 3.0
0.5
0.3 0.25 60
40
20
20
40
60
80
100
120
140
0.3 60
40
20
20
40
60
80
100
120
140
I TM , INSTANTANEOUS ON-STATE CURRENT (AMPS)
3.0 NORMALIZED HOLDING CURRENT 2.0 VD = 12 Vdc
1000
100 TJ = 25C 10
1.0 0.7 0.5
0.3 60
40
20
20
40
60
80
100
120
140
1.0 0 1.0 2.0 3.0 VTM, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
1.0 0.7 0.5 0.3 0.2 ZJC(t) = RJC r(t) 0.1 0.07 0.05 0.03 0.02 0.01 0.1
0.2 0.3
0.5
1.0
2.0
3.0
5.0
10
20
30
50
100
200 300
500
1k
2k
3k
5k
10k
t, TIME (ms)
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596
MCR703A Series Sensitive Gate Silicon Controlled Rectifiers

PNPN devices designed for high volume, low cost consumer applications such as temperature, light and speed control; process and remote control; and warning systems where reliability of operation is critical. Small Size Passivated Die Surface for Reliability and Uniformity Low Level Triggering and Holding Characteristics Recommend Electrical Replacement for C106 Surface Mount Package Case 369A Device Marking: Device Type, e.g., for MCR703A: CR703A, Date Code
Rating Peak Repetitive OffState Voltage(1) (TC = 40 to +110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR703A MCR704A MCR706A MCR708A Peak Non-Repetitive OffState Voltage (Sine Wave, 50 to 60 Hz, Gate Open, TC = 40 to +110C) MCR703A MCR704A MCR706A MCR708A OnState RMS Current (180 Conduction Angles, TC = 90C) Average OnState Current (180 Conduction Angles) TC = 40 to +90C TC = +100C Non-Repetitive Surge Current (1/2 Sine Wave, 60 Hz, TJ = 110C) (1/2 Sine Wave, 1.5 ms, TJ = 110C) Circuit Fusing (t = 8.3 ms) Forward Peak Gate Power (Pulse Width 10 ms, TC = 90C) Forward Average Gate Power (t = 8.3 ms, TC = 90C) Forward Peak Gate Current (Pulse Width 10 ms, TC = 90C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM Value Unit Volts 100 200 400 600 Volts 150 250 450 650 IT(RMS) IT(AV) 2.6 1.6 ITSM Amps 25 35 2.6 0.5 0.1 0.2 40 to +110 40 to +150 A2s Watt Watt Amp MCR706AT4 TJ Tstg C C DPAK 369A MCR704AT4 DPAK 369A 4.0 Amps Amps 1 2 4
Preferred Device
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G A K
VRSM
PIN ASSIGNMENT
1 2 3 4 Gate Anode Cathode Anode
Device MCR703AT4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
I2t PGM PG(AV) IGM
MCR708AT4
DPAK 369A
597
May, 2000 Rev. 4
Publication Order Number: MCR703A/D
MCR703A Series
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient(1) Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Max 8.33 80 260 Unit C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current (VAK = Rated VDRM or VRRM; RGK = 1 K) TC = 25C TC = 110C IDRM, IRRM 10 200 A
ON CHARACTERISTICS
Peak Forward On Voltage (ITM = 8.2 A Peak, Pulse Width = 1 to 2 ms, 2% Duty Cycle) Gate Trigger Current (Continuous dc)(2) (VAK = 12 Vdc, RL = 24 Ohms) TC = 25C TC = 40C Gate Trigger Voltage (Continuous dc)(2) TC = 25C (VAK = 12 Vdc, RL = 24 Ohms) TC = 40C Gate Non-Trigger Voltage(2) (VAK = 12 Vdc, RL = 100 Ohms, TC = 110C) Holding Current (VAK = 12 Vdc, Gate Open) (Initiating Current = 200 mA) Peak Reverse Gate Blocking Voltage (IGR = 10 A) Peak Reverse Gate Blocking Current (VGR = 10 V) Total Turn-On Time (Source Voltage = 12 V, RS = 6 k Ohms) (ITM = 8.2 A, IGT = 2 mA, Rated VDRM) (Rise Time = 20 ns, Pulse Width = 10 s) TC = 25C TC = 40C VTM IGT VGT VGD IH VRGM IRGM tgt 10 12.5 2.0 5.0 10 18 1.2 Volts A s 0.2 25 75 300 0.8 1.0 Volts Volts mA 2.2 Volts A
Critical Rate of Rise of OffState Voltage (VD = Rated VDRM, RGK = 1 K, Exponential Waveform, TC = 110C) Repetitive Critical Rate of Rise of OnState Current (Cf = 60 Hz, IPK = 30 A, PW = 100 s, diG/dt = 1 A/s) (1) Case 369A when surface mounted on minimum pad sizes recommended. (2) RGK current not included in measurement. dv/dt 10 V/s
di/dt
100
A/s
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598
MCR703A Series
Symbol
Parameter
110
5.0 30C 60C 90C 120C 180C 2.0 DC
30C 105
4.0
60C 90C 120C 180C
3.0
DC 100
1.0 0 0 1.0 2.0 3.0 4.0 5.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
95 0 1.0 2.0 3.0 4.0 5.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
r(t), TRANSIENT RESISTANCE (NORMALIZED)
100
1.0
10
ZqJC(t) = RqJC(t)r(t)
0.1
Maximum @ TJ = 25C 1.0
0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
0.01 0.1 1.0 10 100 1000 10,000 t, TIME (ms)
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599
MCR703A Series
35 VGT, GATE TRIGGER VOLTAGE (VOLTS) 20 20 40 60 80 100 110 I GT, GATE TRIGGER CURRENT ( m A) 1.0
30
25
0.5
20
15 40
0 0 40 20 0 20 40 60 80 100 110 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
2.0
2.0
1.5
IL , LATCHING CURRENT (mA) 20 0 20 40 60 80 100 110
1.5
1.0
1.0
0.5
0.5
0 40
0 40
20
20
40
60
80
100 110
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600
MCR703A Series
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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601
MCR716, MCR718
Preferred Device

Designed for high volume, low cost, industrial and consumer applications such as motor control, process control, temperature, light and speed control. Small Size Passivated Die for Reliability and Uniformity Low Level Triggering and Holding Characteristics Surface Mount Lead Form Case 369A Device Marking: Device Type, e.g., MCR716, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +110C, Sine Wave, 50 to 60 Hz, Gate Open) MCR716 MCR718 OnState RMS Current (180 Conduction Angles; TC = 90C) Average OnState Current (180 Conduction Angles; TC = 90C) Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 msec) Forward Peak Gate Power (Pulse Width 10 ms, TC = 90C) Forward Average Gate Power (t = 8.3 msec, TC = 90C) Forward Peak Gate Current (Pulse Width 10 ms, TC = 90C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM 400 600 IT(RMS) IT(AV) ITSM 4.0 2.6 25 Amps Amps Amps DPAK CASE 369A STYLE 4 Value Unit Volts 4 1 2
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G A K
PIN ASSIGNMENT
1 I2t PGM PG(AV) IGM TJ Tstg 2.6 0.5 0.1 0.2 40 to +110 40 to +150 A2sec Watt Watt 2 3 4 Cathode Anode Gate Anode
Amp C C MCR718T4 DPAK 369A Device MCR716T4 Package DPAK 369A Shipping 16mm Tape and Reel (2.5K/Reel) 16mm Tape and Reel (2.5K/Reel)
602
May, 2000 Rev. 3
MCR716, MCR718
Characteristic Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient (Case 369A)(1) Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC RJA TL Max 3.0 80 260 Unit C/W C/W C

OFF CHARACTERISTICS
Peak Repetitive Forward or Reverse Blocking Current; RGK = 1 K (2) (VAK = Rated VDRM or VRRM) TC = 25C TC = 110C
IDRM IRRM
A 10 200
ON CHARACTERISTICS
Peak Reverse Gate Blocking Voltage (IGR = 10 A) Peak Reverse Gate Blocking Current (VGR = 10 V) Peak Forward OnState Voltage(3) (ITM = 5.0 A Peak) (ITM = 8.2 A Peak) Gate Trigger Current (Continuous dc)(4) (VD = 12 Vdc, RL = 30 Ohms) Gate Trigger Voltage (Continuous dc)(4) (VD = 12 Vdc, RL = 30 Ohms) TC = 25C TC = 40C TC = 25C TC = 40C TC = 110C TC = 25C TC = 40C VRGM IRGM VTM IGT 1.0 VGT 0.3 0.2 IH 0.4 IL 2.0 5.0 10 5.0 s 1.0 5.0 10 mA 0.55 0.8 1.0 mA 25 75 300 Volts 1.3 1.5 1.5 2.2 A 10 12.5 18 1.2 Volts A Volts
Holding Current(2) (VD = 12 Vdc, Initiating Current = 200 mA, Gate Open) Latching Current(2) (VD = 12 Vdc, IG = 2.0 mA, TC = 25C) (VD = 12 Vdc, IG = 2.0 mA, TC = 40C)
Total Turn-On Time (Source Voltage = 12 V, RS = 6 K , IT = 8 A(pk), RGK = 1 K ) (VD = Rated VDRM, Rise Time = 20 ns, Pulse Width = 10 s)
tgt
Critical Rate of Rise of OffState Voltage (VD = 0.67 x Rated VDRM, RGK = 1 K , Exponential Waveform, TJ = 110C)
dv/dt
5.0
10
V/s
Repetitive Critical Rate of Rise of OnState Current (f = 60 Hz, IPK = 30 A, PW = 100 s, dIG/dt = 1 A/s)
di/dt
100
A/s
(1) Case 369A, when surface mounted on minimum recommended pad size. (2) Ratings apply for negative gate voltage or RGK = 1 K . Devices shall not have a positive gate voltage concurrently with a negative voltage on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage applied exceeds the rated blocking voltage. (3) Pulse Test: Pulse Width 2 ms, Duty Cycle 2%. (4) RGK current not included in measurements.
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603
MCR716, MCR718
Symbol
Parameter
110
5.0 30C 60C 90C 120C 180C 2.0 DC
30C 105
4.0
60C 90C 120C 180C
3.0
DC 100
1.0 0 0 1.0 2.0 3.0 4.0 5.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
95 0 1.0 2.0 3.0 4.0 5.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
r(t), TRANSIENT RESISTANCE (NORMALIZED)
100
1.0
10
ZqJC(t) = RqJC(t)r(t)
0.1
Maximum @ TJ = 25C 1.0
0.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
0.01 0.1 1.0 10 100 1000 10,000 t, TIME (ms)
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604
MCR716, MCR718
35 VGT, GATE TRIGGER VOLTAGE (VOLTS) 20 0 20 40 60 80 100 110 I GT, GATE TRIGGER CURRENT ( m A) 1.0
30
25
0.5
20
15 40
0 40 20 0 20 40 60 80 100 110 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)
2.0
2.0
1.5
IL , LATCHING CURRENT (mA) 20 0 20 40 60 80 100 110
1.5
1.0
1.0
0.5
0.5
0 40
0 40
20
20
40
60
80
100 110
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605
MCR716, MCR718
0.165 4.191
0.100 2.54
0.118 3.0
0.063 1.6 0.190 4.826 0.243 6.172
inches mm
DPAK
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606
MKP1V120 Series Sidac High Voltage

Bidirectional Triggers
Bidirectional devices designed for direct interface with the ac power line. Upon reaching the breakover voltage in each direction, the device switches from a blocking state to a low voltage onstate. Conduction will continue like a Triac until the main terminal current drops below the holding current. The plastic axial lead package provides high pulse current capability at low cost. Glass passivation insures reliable operation. Applications are: High Pressure Sodium Vapor Lighting Strobes and Flashers Ignitors High Voltage Regulators Pulse Generators Used to Trigger Gates of SCRs and Triacs Indicates UL Registered File #E116110 Device Marking: Logo, Device Type, e.g., MKP1V120, Date Code
Rating Peak Repetitive OffState Voltage (Sine Wave, 50 to 60 Hz, TJ = 40 to 125C) MKP1V120, MKP1V130, MKP1V160 MKP1V240 On-State Current RMS (TL = 80C, Lead Length = 3/8, All Conduction Angles) Peak Nonrepetitive Surge Current (60 Hz One Cycle Sine Wave, TJ = 125C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM Value Unit Volts
Preferred Device
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SIDACS ( ) 0.9 AMPERES RMS 120 thru 240 VOLTS
MT1
MT2
IT(RMS)
"90 "180 "0.9 "4.0

40 to +125 40 to +150
Amp
DO41 PLASTIC AXIAL (No Polarity) CASE 059A
ITSM
Amps
Device Package DO41 DO41 DO41 DO41 DO41 DO41 Shipping Tape and Reel 5K/Reel Tape and Reel 5K/Reel Bulk 1K/Bag Tape and Reel 5K/Reel Bulk 1K/Bag Tape and Reel 5K/Reel
TJ Tstg
C C
MKP1V120RL MKP1V130RL MKP1V160 MKP1V160RL MKP1V240 MKP1V240RL
607
May, 2000 Rev. 5
Publication Order Number: MKP1V120/D
MKP1V120 Series
Characteristic Thermal Resistance, Junction to Lead Lead Length = 3/8 Lead Solder Temperature (Lead Length 1/16 from Case, 10 s Max) Symbol RJL TL Max 40 260 Unit C/W C
OFF CHARACTERISTICS
Repetitive Peak OffState Current TJ = 25C (50 to 60 Hz Sine Wave) VDRM = 90 V, MKP1V120, MKP1V130 and MKP1V160 VDRM = 180 V, MKP1V240 IDRM 5.0 A
ON CHARACTERISTICS
Breakover Voltage IBO = 35 A 35 A 200 A 35 A VBO MKP1V120 MKP1V130 MKP1V160 MKP1V240 VTM IH RS 110 120 150 220 0.1 130 140 170 250 1.5 100 Volts mA k Volts
Peak OnState Voltage (ITM = 1 A Peak, Pulse Width 300 s, Duty Cycle 2%) Dynamic Holding Current (Sine Wave, 50 to 60 Hz, RL = 100 Ohm) Switching Resistance (Sine Wave, 50 to 60 Hz)
1.3
Critical RateofRise of OnState Current, Critical Damped Waveform Circuit (IPK = 130 Amps, Pulse Width = 10 sec) di/dt 120 A/s
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608
MKP1V120 Series
Voltage Current Characteristic of SIDAC (Bidirectional Device)
+ Current ITM IH IS IDRM VS I(BO) + Voltage V(BO) V S) VTM Slope = RS
Symbol
IDRM VDRM VBO IBO IH VTM ITM
Parameter
Off State Leakage Current Off State Repetitive Blocking Voltage Breakover Voltage Breakover Current Holding Current On State Voltage Peak on State Current
VDRM
RS
+ (V (I
(BO) S
I (BO))
TL , MAXIMUM ALLOWABLE LEAD TEMPERATURE ( C)
140 3/8 3/8 IT(RMS) , ONSTATE CURRENT (AMPS) 130 120 110 100 90 80 70 60 50 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TJ = 125C Sine Wave Conduction Angle = 180C TL
1.0
0.8
TJ = 125C Sine Wave Conduction Angle = 180C Assembled in PCB Lead Length = 3/8
0.6
0.4
0.2
20
40
60
80
100
120
140
IT(RMS), ONSTATE CURRENT (AMPS)
TA, MAXIMUM AMBIENT TEMPERATURE (C)
Figure 1. Maximum Lead Temperature

I T , INSTANTANEOUS ONSTATE CURRENT (AMPS) 10 7.0 5.0 3.0 2.0 1.0 0.7 0.5 0.3 0.2 0.1 0 1.0 2.0 3.0 4.0 5.0 0 TJ = 25C 125C 1.25 PRMS , POWER DISSIPATION (WATTS)
1.00
TJ = 25C Conduction Angle = 180C
0.75
0.50
0.25
0.2
0.4
0.6
0.8
1.0
VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
IT(RMS), ONSTATE CURRENT (AMPS)
Figure 3. Typical OnState Voltage
Figure 4. Typical Power Dissipation
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609
MKP1V120 Series
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.1 ZqJL(t) = RqJL r(t) DTJL = Ppk RqJL[r(t)] tp TIME where: DTJL = the increase in junction temperature above the lead temperature r(t) = normalized value of transient thermal resistance at time, t from this figure. For example, r(tp) = normalized value of transient resistance at time tp. 0.2 0.5 1.0 2.0 5.0 10 20 t, TIME (ms) 50 100 200 The temperature of the lead should be measured using a thermocouple placed on the lead as close as possible to the tie point. The thermal mass connected to the tie point is normally large enough so that it will not significantly respond to heat surges generated in the diode as a result of pulsed operation once steadystate conditions are achieved. Using the measured value of TL, the junction temperature may be determined by: TJ = TL + DTJL 500 1.0 k 2.0 k 5.0 k 10 k
VBO , BREAKOVER VOLTAGE (NORMALIZED) 1.4 IH , HOLDING CURRENT (NORMALIZED)
1.0
1.2
1.0
0.9
0.8
0.6 0.4 60
0.8 60
40
20
20
40
60
80
100
120
140
40
20
20
40
60
80
100
120
140
Figure 6. Typical Breakover Voltage
100
IPK, PEAK CURRENT (AMPS)
10
IPK
10% tw 1.0 0.1 1.0 tw, PULSE WIDTH (ms) 10 100
Figure 8. Pulse Rating Curve http://onsemi.com

610
MKP3V120, MKP3V240
Preferred Device
Sidac High Voltage
Bidirectional Triggers
Bidirectional devices designed for direct interface with the ac power line. Upon reaching the breakover voltage in each direction, the device switches from a blocking state to a low voltage onstate. Conduction will continue like a Triac until the main terminal current drops below the holding current. The plastic axial lead package provides high pulse current capability at low cost. Glass passivation insures reliable operation. Applications are: High Pressure Sodium Vapor Lighting Strobes and Flashers Ignitors High Voltage Regulators Pulse Generators Used to Trigger Gates of SCRs and Triacs Indicates UL Registered File #E116110 Device Marking: Logo, Device Type, e.g., MKP3V120, Date Code
Rating Peak Repetitive OffState Voltage (Sine Wave, 50 to 60 Hz, TJ = 40 to 125C) MKP3V120 MKP3V240 On-State RMS Current (TL = 80C, Lead Length = 3/8, All Conduction Angles) Peak NonRepetitive Surge Current (60 Hz One Cycle Sine Wave, Peak Value, TJ = 125C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM Value Unit Volts
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SIDACS ( ) 1 AMPERE RMS 120 and 240 VOLTS
MT1
MT2
IT(RMS)
"90 "180 "1.0 "20

40 to +125 40 to +150
Amp
SURMETIC 50 PLASTIC AXIAL (No Polarity) CASE 267 STYLE 2
ITSM
Amps
C C Device MKP3V120 Package SURMETIC 50 Shipping Bulk 500/Bag Tape and Reel 1.5K/Reel Bulk 500/Bag Tape and Reel 1.5K/Reel
TJ Tstg
MKP3V120RL SURMETIC 50 MKP3V240 SURMETIC 50
MKP3V240RL SURMETIC 50
611
May, 2000 Rev. 3
Publication Order Number: MKP3V120/D
MKP3V120, MKP3V240
Characteristic Thermal Resistance, Junction to Lead (Lead Length = 3/8) Lead Solder Temperature (Lead Length 1/16 from Case, 10 s Max) Symbol RJL TL Max 15 260 Unit C/W C
OFF CHARACTERISTICS
Repetitive Peak OffState Current (50 to 60 Hz Sine Wave) VDRM = 90 V VDRM = 180 V IDRM MKP3V120 MKP3V240 10 A
ON CHARACTERISTICS
Breakover Voltage, IBO = 200 A MKP3V120 MKP3V240 Breakover Current Peak OnState Voltage (ITM = 1 A Peak, Pulse Width 300 s, Duty Cycle 2%) Dynamic Holding Current (Sine Wave, 60 Hz, RL = 100 ) Switching Resistance (Sine Wave, 50 to 60 Hz) IBO VTM IH RS VBO 110 220 0.1 1.1 130 250 200 1.5 100 A Volts mA k Volts
Critical RateofRise of OnState Current, Critical Damped Waveform Circuit (IPK = 130 Amps, Pulse Width = 10 sec) di/dt 120 A/s
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612
MKP3V120, MKP3V240
Voltage Current Characteristic of SIDAC (Bidirectional Device)
+ Current ITM IH IS IDRM VS I(BO) + Voltage V(BO) V S) VTM Slope = RS
Symbol
IDRM VDRM VBO IBO IH VTM ITM
Parameter
Off State Leakage Current Off State Repetitive Blocking Voltage Breakover Voltage Breakover Current Holding Current On State Voltage Peak on State Current
VDRM
RS
+ (V (I
(BO) S
I (BO))
CURRENT DERATING
TC , MAXIMUM ALLOWABLE CASE TEMPERATURE (C) 130 TA , MAXIMUM ALLOWABLE AMBIENT TEMPERATURE ( C)
120 = Conduction Angle TJ Rated = 125C
140 120 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 = Conduction Angle TJ Rated = 125C
110
100
a = 180
90
80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
a = 180
1.6 1.8 2.0 IT(AV), AVERAGE ONSTATE CURRENT (AMPS)
1.0 0.8 0.6 0.4 0.3 0.2 25C 125C
PAV , MAXIMUM AVERAGE POWER DISSIPATION (WATTS)
I T , INSTANTANEOUS ONSTATE CURRENT (AMPS)
1.25
a = 180
= Conduction Angle TJ Rated = 125C
1.00
0.75
0.50
0.25
0.2
0.4
0.6
0.8
1.0
Figure 4. Typical Power Dissipation
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613
MKP3V120, MKP3V240
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.5 0.3 0.2 0.1 0.05 0.03 0.02 0.01 0.2 0.5 1.0 2.0 5.0 10 20 50 t, TIME (ms) 100 200 500 1.0 k ZqJL(t) = RqJL r(t) DTJL = Ppk RqJL[r(t)] tp TIME where: DTJL = the increase in junction temperature above the lead temperature r(t) = normalized value of transient thermal resistance at time, t from this figure. For example, r(tp) = normalized value of transient resistance at time tp. LEAD LENGTH = 1/4 The temperature of the lead should be measured using a thermocouple placed on the lead as close as possible to the tie point. The thermal mass connected to the tie point is normally large enough so that it will not significantly respond to heat surges generated in the diode as a result of pulsed operation once steadystate conditions are achieved. Using the measured value of TL, the junction temperature may be determined by: TJ = TL + DTJL 2.0 k 5.0 k 10 k 20 k
100 90 I(BO) , BREAKOVER CURRENT ( mA) IH , HOLDING CURRENT (mA) 80 70 60 50 40 30 20 10 0 60 40 20 0 20 40 60 80 100 120 140 250 225 200 175 150 125 100 75 50 25 0 60 40 20 0 20 40 60 80 100 120 140
Figure 6. Typical Breakover Current
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614
MMT05B230T3, MMT05B260T3, MMT05B310T3

Preferred Device
Thyristor Surge Protectors
High Voltage Bidirectional TSPD

These Thyristor Surge Protective devices (TSPD) prevent overvoltage damage to sensitive circuits by lightning, induction and power line crossings. They are breakovertriggered crowbar protectors. Turnoff occurs when the surge current falls below the holding current value. Secondary protection applications for electronic telecom equipment at customer premises. High Surge Current Capability: 50 Amps 10 x 1000 sec Guaranteed at the extended temp range of 20C to 65C The MMT05B230T3 Series is used to help equipment meet various regulatory requirements including: Bellcore 1089, ITU K.20 & K.21, IEC 950, UL 1459 & 1950 and FCC Part 68. Bidirectional Protection in a Single Device Little Change of Voltage Limit with Transient Amplitude or Rate Freedom from Wearout Mechanisms Present in NonSemiconductor Devices FailSafe, Shorts When Overstressed, Preventing Continued Unprotected Operation. Surface Mount Technology (SMT) Indicates UL Registered File #E116110 Device Marking: MMT05B230T3: RPBF; MMT05B260T3: RPBG; MMT05B310T3: RPBJ, and Date Code
Rating OffState Voltage Maximum MMT05B230T3 MMT05B260T3 MMT05B310T3 Maximum Pulse Surge Short Circuit Current NonRepetitive Double Exponential Decay Waveform Notes 1, 2 10 x 1000 sec (20C to +65C) 8 x 20 sec 10 x 160 sec 10 x 560 sec Maximum NonRepetitive Rate of Change of OnState Current Double Exponential Waveform, R = 1.0, L = 1.5 H, C = 1.67 F, Ipk = 110A Symbol VDM Value Unit Volts MMT05B310T3 SMB MMT05B260T3 SMB
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BIDIRECTIONAL TSPD ( 50 AMP SURGE 265 thru 365 VOLTS
MT1
MT2
SMB (No Polarity) (Essentially JEDEC DO214AA) CASE 403C
Device MMT05B230T3 Package SMB Shipping 12mm Tape and Reel (2.5K/Reel) 12mm Tape and Reel (2.5K/Reel) 12mm Tape and Reel (2.5K/Reel)
"170 "200 "270 "50 "150 "100 "70 "150
A(pk)
IPPS1 IPPS2 IPPS3 IPPS4 di/dt
A/s
615
May, 2000 Rev. 4
Publication Order Number: MMT05B230T3/D

Characteristic Operating Temperature Range Blocking or Conducting State Overload Junction Temperature Maximum Conducting State Only Instantaneous Peak Power Dissipation (Ipk = 50A, 10x1000 sec @ 25C) Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol TJ1 TJ2 PPK TL Max 40 to + 125 + 175 2000 260 Unit C C W C
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Devices are bidirectional. All electrical parameters apply to forward and reverse polarities.
Characteristics Breakover Voltage (Both polarities) (dv/dt = 100 V/s, ISC = 1.0 A, Vdc = 1000 V) (+65C) MMT05B230T3 MMT05B260T3 MMT05B310T3 Breakover Voltage (Both polarities) (f = 60 Hz, ISC = 1.0 A(rms), VOC = 1000 V(rms), RI = 1.0 k, t = 0.5 cycle, Note 2) (+65C) MMT05B230T3 MMT05B260T3 MMT05B310T3 Breakover Voltage Temperature Coefficient Breakdown Voltage (I(BR) = 1.0 mA) Both polarities MMT05B230T3 MMT05B260T3 MMT05B310T3 Off State Current (VD1 = 50 V) Both polarities Off State Current (VD2 = VDM) Both polarities OnState Voltage (IT = 1.0 A) (PW 300 s, Duty Cycle 2%, Note 2) Breakover Current (f = 60 Hz, VDM = 1000 V(rms), RS = 1.0 k) Both polarities Holding Current (Both polarities) VS = 500 Volts; IT (Initiating Current) = ID1 ID2 VT IBO IH dv/dt CO dV(BO)/dTJ V(BR) 175 130 2000 190 240 280 1.53 230 340 22 53 2.0 5.0 3.0 75 A Volts mA mA V/s pF 0.08 280 340 400 %/C Volts V(BO) MMT05B230T3 MMT05B260T3 MMT05B310T3 265 320 365 280 340 400 Volts MMT05B230T3 MMT05B260T3 MMT05B310T3 Symbol V(BO) 265 320 365 Min Typ Max Unit Volts
"1.0 Amp
Note 2 (+65C)
Critical Rate of Rise of OffState Voltage (Linear waveform, VD = Rated VBR, TJ = 25C) Capacitance (f = 1.0 MHz, 50 Vdc, 1.0 V rms Signal) Capacitance (f = 1.0 MHz, 2.0 Vdc, 15 mV rms Signal) (1) Allow cooling before testing second polarity. (2) Measured under pulse conditions to reduce heating.
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616

Voltage Current Characteristic of TSPD (Bidirectional Device)
+ Current
Symbol
ID1, ID2 VD1, VD2 VBR VBO IBO IH VTM
Parameter
Off State Leakage Current Off State Blocking Voltage Breakdown Voltage Breakover Voltage Breakover Current Holding Current On State Voltage + Voltage VD1 VD2 V(BR) IH ID1 ID2 I(BO) VTM V(BO)
100 I D1, OFFSTATE CURRENT ( A)

VD1 = 50V
340 V BR , BREAKDOWN VOLTAGE (VOLTS) 320 300 280 260 240 220 200 180 160 50 25 0 25 50 TEMPERATURE (C) 75 100 125
MMT05B230T3 MMT05B260T3 MMT05B310T3
10
0.1
0.01
20
40
60 80 100 TEMPERATURE (C)
120
140
Figure 1. OffState Current versus Temperature
Figure 2. Breakdown Voltage versus Temperature
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617

380 V BO , BREAKOVER VOLTAGE (VOLTS) 360 I H , HOLDING CURRENT (mA) 75 100 125 340 320 300 280 260 240 220 200 50 25 0 25 50 TEMPERATURE (C)
1000 900 800 700 600 500 400 300 200 100 50 25 0 25 50 TEMPERATURE (C) 75 100 125
Figure 3. Breakover Voltage versus Temperature
Figure 4. Holding Current versus Temperature
100 Ipp PEAK PULSE CURRENT %Ipp Peak Value tr = rise time to peak value tf = decay time to half value
100
CURRENT (A)
10
50
Half Value
0 0 tr tf TIME (ms)
1 0.001
0.01
0.1 1 TIME (sec)
10
100
Figure 5. Exponential Decay Pulse Waveform
Figure 6. Peak Surge OnState Current versus Surge Current Duration, Sinusoidal Waveform
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618
TIP
OUTSIDE PLANT
GND
TELECOM EQUIPMENT
RING
PPTC*
TIP
OUTSIDE PLANT
GND
TELECOM EQUIPMENT
RING
PPTC* *Polymeric PTC (positive temperature coefficient) overcurrent protection device
HEAT COIL
TIP
OUTSIDE PLANT
GND
TELECOM EQUIPMENT
RING HEAT COIL
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619

0.089 2.261
0.108 2.743
0.085 2.159
inches mm
SMB
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620

Preferred Device
Thyristor Surge Protectors
High Voltage Bidirectional TSPD

These Thyristor Surge Protective devices (TSPD) prevent overvoltage damage to sensitive circuits by lightning, induction and power line crossings. They are breakovertriggered crowbar protectors. Turnoff occurs when the surge current falls below the holding current value. Secondary protection applications for electronic telecom equipment at customer premises. Outstanding High Surge Current Capability: 100 Amps 10x1000 sec Guaranteed at the extended temp range of 20C to 65C The MMT10B230T3 Series is used to help equipment meet various regulatory requirements including: Bellcore 1089, ITU K.20 & K.21, IEC 950, UL 1459 & 1950 and FCC Part 68. Bidirectional Protection in a Single Device Little Change of Voltage Limit with Transient Amplitude or Rate Freedom from Wearout Mechanisms Present in NonSemiconductor Devices FailSafe, Shorts When Overstressed, Preventing Continued Unprotected Operation. Surface Mount Technology (SMT) Complies with GR1089 Second Level Surge Spec at 500 Amps 2x10 sec Waveforms Indicates UL Registered File #E116110 Device Marking: MMT10B230T3: RPDF; MMT10B260T3: RPDG; MMT10B310T3: RPDJ, and Date Code
Rating OffState Voltage Maximum MMT10B230T3 MMT10B260T3 MMT10B310T3 Maximum Pulse Surge Short Circuit Current NonRepetitive Double Exponential Decay Waveform Notes 1, 2 10 x 1000 sec (20C to +65C) 2 x 10 sec 10 x 700 sec Maximum NonRepetitive Rate of Change of OnState Current Double Exponential Waveform, R = 2.0, L = 1.5 H, C = 1.67 F, Ipk = 110A Symbol VDM Value Unit Volts MMT10B310T3 SMB
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BIDIRECTIONAL TSPD ( 100 AMP SURGE 265 thru 365 VOLTS
MT1
MT2
SMB (No Polarity) (Essentially JEDEC DO214AA) CASE 403C
Device MMT10B230T3 Package SMB Shipping 12mm Tape and Reel (2.5K/Reel) 12mm Tape and Reel (2.5K/Reel) 12mm Tape and Reel (2.5K/Reel)
MMT10B260T3
SMB
"170 "200 "270 "100 "500 "180 "100
A(pk)
IPPS1 IPPS2 IPPS3 di/dt
A/s
621
May, 2000 Rev. 4
Publication Order Number: MMT10B230T3/D

Characteristic Operating Temperature Range Blocking or Conducting State Overload Junction Temperature Maximum Conducting State Only Instantaneous Peak Power Dissipation (Ipk = 100A, 10x1000 sec @ 25C) Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol TJ1 TJ2 PPK TL Max 40 to + 125 + 175 4000 260 Unit C C W C
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Devices are bidirectional. All electrical parameters apply to forward and reverse polarities.
Characteristic Breakover Voltage (Both polarities) (dv/dt = 100 V/s, ISC = 1.0 A, Vdc = 1000 V) (+65C) MMT10B230T3 MMT10B260T3 MMT10B310T3 Breakover Voltage (Both polarities) (f = 60 Hz, ISC = 1.0 A(rms), VOC = 1000 V(rms), MMT10B230T3 RI = 1.0 k, t = 0.5 cycle, Note 2) MMT10B260T3 MMT10B310T3 (+65C) MMT10B230T3 MMT10B260T3 MMT10B310T3 Breakover Voltage Temperature Coefficient Breakdown Voltage (I(BR) = 1.0 mA) Both polarities MMT10B230T3 MMT10B260T3 MMT10B310T3 Off State Current (VD1 = 50 V) Both polarities Off State Current (VD2 = VDM) Both polarities OnState Voltage (IT = 1.0 A) (PW 300 s, Duty Cycle 2%, Note 2) Breakover Current (f = 60 Hz, VDM = 1000 V(rms), RS = 1.0 k) Both polarities Holding Current (Both polarities) VS = 500 Volts; IT (Initiating Current) = ID1 ID2 VT IBO IH dv/dt CO V(BO) dV(BO)/dTJ V(BR) 175 130 2000 190 240 280 1.53 260 270 65 160 2.0 5.0 5.0 200 A Volts mA mA V/s pF 0.08 265 320 365 290 340 400 %/C Volts 290 340 400 Volts MMT10B230T3 MMT10B260T3 MMT10B310T3 Symbol V(BO) 265 320 365 Min Typ Max Unit Volts
"1.0 A
Note 2 (+65C)
Critical Rate of Rise of OffState Voltage (Linear waveform, VD = Rated VBR, TJ = 25C) Capacitance (f = 1.0 MHz, 50 Vdc, 1.0 V rms Signal) Capacitance (f = 1.0 MHz, 2.0 Vdc, 15 mV rms Signal) (1) Allow cooling before testing second polarity. (2) Measured under pulse conditions to reduce heating.
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622

Voltage Current Characteristic of TSPD (Bidirectional Device)
+ Current
Symbol
ID1, ID2 VD1, VD2 VBR VBO IBO IH VTM
Parameter
Off State Leakage Current Off State Blocking Voltage Breakdown Voltage Breakover Voltage Breakover Current Holding Current On State Voltage + Voltage VD1 VD2 V(BR) IH ID1 ID2 I(BO) VTM V(BO)
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623

100 I D1, OFFSTATE CURRENT ( A)
VD1 = 50V
340 V BR , BREAKDOWN VOLTAGE (VOLTS) 320 300 280 260 240 220 200 180 160 50 25 0 25 50 TEMPERATURE (C) 75 100 125
10
0.1
0.01
20
40
60 80 100 TEMPERATURE (C)
120
140
Figure 1. OffState Current versus Temperature
Figure 2. Breakdown Voltage versus Temperature
360 V BO , BREAKOVER VOLTAGE (VOLTS) 340 I H , HOLDING CURRENT (mA)

MMT10B310T3
1000 900 800 700 600 500 400 300 200 25 0 50 25 TEMPERATURE (C) 75 100 125 100 50 25 0 50 25 TEMPERATURE (C) 75 100 125
320 300 280 260 240 220 200 180 50

MMT10B230T3 MMT10B260T3
Figure 3. Breakover Voltage versus Temperature
Figure 4. Holding Current versus Temperature
100 Ipp PEAK PULSE CURRENT %Ipp Peak Value tr = rise time to peak value tf = decay time to half value
100
CURRENT (A)
10
50
Half Value
0 0 tr tf TIME (ms)
1 0.01
0.1
1 TIME (sec)
10
100
Figure 5. Exponential Decay Pulse Waveform
Figure 6. Peak Surge OnState Current versus Surge Current Duration, Sinusoidal Waveform
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624
TIP
OUTSIDE PLANT
GND
TELECOM EQUIPMENT
RING
PPTC*
TIP
OUTSIDE PLANT
GND
TELECOM EQUIPMENT
RING
PPTC* *Polymeric PTC (positive temperature coefficient) overcurrent protection device
HEAT COIL
TIP
OUTSIDE PLANT
GND
TELECOM EQUIPMENT
RING HEAT COIL
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625

0.089 2.261
0.108 2.743
0.085 2.159
inches mm
SMB
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626
T2322B Sensitive Gate Triacs

Designed primarily for ac power switching. The gate sensitivity of these triacs permits the use of economical transistorized or integrated circuit control circuits, and it enhances their use in low-power phase control and load-switching applications. Very High Gate Sensitivity Low On-State Voltage at High Current Levels Glass-Passivated Chip for Stability Small, Rugged Thermopad Construction for Low Thermal Resistance, High Heat Dissipation and Durability Device Marking: Device Type, e.g., T2322B, Date Code
Rating Peak Repetitive Off-State Voltage(1) (TJ = 25 to 110C, Gate Open) On-State RMS Current (TC = 70C) (Full Cycle Sine Wave 50 to 60 Hz) Peak NonRepetitive Surge Current (One Full Cycle, Sine Wave 60 Hz, TC = 70C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width 10 s, TC = 70C) Average Gate Power (t = 8.3 ms, TC = 70C) Peak Gate Current (Pulse Width = 10 s, TC = 70C) Operating Junction Temperature Range Storage Temperature Range Mounting Torque (6-32 Screw)(2) Symbol VDRM, VRRM IT(RMS) ITSM Value 200 2.5 25 Unit Volts Amps Amps
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MT2 G
MT1
2.6 10 0.5 0.5 40 to +110 40 to +150 8.0
A2s Watts Watt Amp C C in. lb. 1 2 3
2 1
PIN ASSIGNMENT
Device T2322B Package TO225AA Shipping 500/Box
(1) VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. (2) Torque rating applies with use of torque washer (Shakeproof WD19523 or equivalent). Mounting Torque in excess of 6 in. lb. does not appreciably lower case-to-sink thermal resistance. Main terminal 2 and heat-sink contact pad are common.
627
May, 2000 Rev. 3
Publication Order Number: T2322/D
T2322B
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 110C IDRM, IRRM 0.2 10 0.75 A mA
ON CHARACTERISTICS
Peak On-State Voltage(1) (ITM = 10 A)
"
VTM IGT
1.7
2.2 10
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 ) All Quadrants Gate Trigger Voltage (Continuous dc) (VD = 12 Vdc, RL = 100 , TC = 25C) Gate NonTrigger Voltage (VD = 12 V, RL = 100 , TC = 110C) Holding Current (VD = 12 V, IT (Initiating Current) =
VGT VGD IH tgt
0.15
1.0 15 1.8
2.2 30 2.5
Volts Volts mA s
"200 mA, Gate Open)
Gate Controlled Turn-On Time (VD = Rated VDRM, ITM = 10 A pk, IG = 60 mA, tr = 0.1 sec)
Critical Rate-of-Rise of Off-State Voltage (VD = Rated VDRM, Exponential Waveform, TC = 100C) Critical Rate-of-Rise of Commutation Voltage (VD = Rated VDRM, ITM = 3.5 A pk, Commutating di/dt = 1.26 A/ms, Gate Unenergized, TC = 90C) (1) Pulse Test: Pulse Width 1.0 ms, Duty Cycle 2%. dv/dt dv/dt(c) 10 1.0 100 4.0 V/s V/s
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628
T2322B
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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629
T2500D Triacs
Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies. Blocking Voltage 400 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability High Surge Current Capability 60 Amps Peak at TC = 80C Device Marking: Logo, Device Type, e.g., T2500D, Date Code
Rating Peak Repetitive OffState Voltage(1) (Sine Wave 50 to 60 Hz, TJ = 40 to +100C, Gate Open) OnState RMS Current (TC = +80C) (Full Cycle Sine Wave 50 to 60 Hz) Peak Nonrepetitive Surge Current (One Full Cycle, 60 Hz, TC = +80C) Circuit Fusing Considerations (t = 8.3 ms) Peak Gate Power (TC = +80C, Pulse Width = 10 sec) Average Gate Power (TC = +80C, t = 8.3 ms) Peak Gate Current (Pulse Width = 10 sec) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM IT(RMS) Value 400 Unit Volts 4 6.0 A
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TRIACS 6 AMPERES RMS 400 VOLTS

MT2 G MT1
ITSM I2t PGM PG(AV) IGM TJ Tstg
60 15 16 0.2 4.0 40 to +125 40 to +150
A A2s Watts Watt 1 2
PIN ASSIGNMENT
A C C 1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
(1) VDRM, VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.
Device T2500D Package TO220AB Shipping 500/Box
630
T2500D
Characteristic Thermal Resistance Junction to Case Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC TL Value 2.7 260 Unit C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (Rated VDRM, VRRM; Gate Open) TJ = 25C TJ = 100C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak On-State Voltage* (ITM = 30 A Peak)
"
VTM IGT
2.0
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (All Four Quadrants) (VD = 12 Vdc, RL = 100 Ohms) Gate NonTrigger Voltage (VD = 12 V, RL = 100 Ohms, TC = 100C) Holding Current (Main Terminal Voltage = 12 Vdc, Gate Open, Initiating Current = 200 mA)
VGT VGD IH 0.2
10 20 15 30 1.25 15
25 60 25 60 2.5 30 Volts Volts mA
"
Gate Controlled Turn-On Time (Rated VDRM, IT = 10 A , IGT = 160 mA, Rise Time = 0.1 s)
tgt
1.6
Critical Rate-of-Rise of Commutation Voltage (Rated VDRM, IT(RMS) = 6 A, Commutating di/dt = 3.2 A/ms, Gate Unenergized, TC = 80C) Critical Rate-of-Rise of Off-State Voltage (Rated VDRM, Exponential Voltage Rise, Gate Open, TC = 100C) * Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt(c) 10 V/s
dv/dt
75
V/s
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631
T2500D
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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632
T2800D Triacs
Designed primarily for full-wave ac control applications, such as light dimmers, motor controls, heating controls and power supplies. Blocking Voltage to 400 Volts All Diffused and Glass Passivated Junctions for Greater Parameter Uniformity and Stability Small, Rugged, Thermowatt Construction for Low Thermal Resistance, High Heat Dissipation and Durability Four Quadrant Gating Device Marking: Logo, Device Type, e.g., T2800D, Date Code
Rating Peak Repetitive OffState Voltage(1) (TJ = 40 to +125C, Gate Open) OnState RMS Current (All Conduction Angles, TC = +80C) Peak NonRepetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = +80C) Circuit Fusing Consideration (t = 8.3 ms) Peak Gate Power (Pulse Width = 10 s, TC = +80C) Average Gate Power (t = 8.3 ms, TC = +80C) Peak Gate Current (Pulse Width = 10 s, TC = +80C) Operating Junction Temperature Range Storage Temperature Range Symbol VDRM, VRRM IT(RMS) ITSM Value 400 8.0 100 Unit Volts Amps Amps 4
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TRIACS 8 AMPERES RMS 400 VOLTS

MT2 G MT1
40 16 0.35 4.0 40 to +125 40 to +150
A2s Watts Watt Amps
PIN ASSIGNMENT
C C 1 2 3 4 Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Device T2800D Package TO220AB Shipping 500/Box
633
T2800D
Characteristic Thermal Resistance, Junction to Case Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds Symbol RJC TL Value 2.2 260 Unit C/W C
OFF CHARACTERISTICS
Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) TC = 25C TC = 100C IDRM, IRRM 10 2.0 A mA
ON CHARACTERISTICS
Peak On-State Voltage(1) (IT = 30 A Peak)
"
VTM IGT
1.7
2.0
Volts mA
Gate Trigger Current (Continuous dc) (VD = 12 Vdc, RL = 100 Ohms) MT2(+), G(+) MT2(+), G() MT2(), G() MT2(), G(+) Gate Trigger Voltage (Continuous dc) (All Quadrants) (VD = 12 Vdc, RL = 100 Ohms) Gate NonTrigger Voltage (Continuous dc) (VD = 12 V, RL = 100 Ohms, TC = 100C) Holding Current (VD = 12 Vdc, Initiating Current =
VGT VGD IH tgt 0.2
10 20 15 30 1.25 15 1.6
25 60 25 60 2.5 30 Volts Volts mA s
"200 mA, Gate Open)
Gate Controlled Turn-On Time (VD = Rated VDRM, IT = 10 A, IGT = 80 mA, Rise Time = 0.1 s)
Critical Rate-of-Rise of Commutation Voltage (VD = Rated VDRM, IT(RMS) = 8 A, Commutating di/dt = 4.1 A/ms, Gate Unenergized, TC = 80C) Critical Rate-of-Rise of Off-State Voltage (VD = Rated VDRM, Exponential Voltage Rise, Gate Open, TC = 100C) (1) Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. dv/dt(c) 10 V/s
dv/dt
60
V/s
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634
T2800D
Symbol
Parameter
VTM IH
off state

(+) MT2
(+) MT2
Quadrant II
() IGT GATE MT1 REF
Quadrant I
IGT () MT2 () MT2
+ IGT
Quadrant III
() IGT GATE MT1 REF
Quadrant IV
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635
T2800D
TC, MAXIMUM ALLOWABLE CASE TEMPERATURE (C) P(AV) , AVERAGE POWER DISSIPATION (WATTS) 100 12 10 8 6 4 2 0 0 2 4 6 8 10 12 IT(RMS), RMS ON-STATE CURRENT (AMP) FULL CYCLE SINUSOIDAL WAVEFORM MAXIMUM TYPICAL
95
FULL CYCLE SINUSOIDAL WAVEFORM
90
85
80 0 2 4 6 8 IT(RMS), RMS ON-STATE CURRENT (AMP)
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636
CHAPTER 4 Surface Mounting Guide Package Information and Tape and Reel Specifications
Information for Using Surface Mount Thyristors . . . . . Tape and Reel Packaging Specifications . . . . . . . . . . . Surface Mount (DPAK, SMB, SOT223) . . . . . . . . AxialLead (DO41, Surmetic 50) . . . . . . . . . . . . . . TO92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 638 641 641 644 645
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637
INFORMATION FOR USING SURFACE MOUNT THYRISTORS

0.089 2.261
0.165 4.191 0.118 3.0
0.100 2.54
0.108 2.743
0.063 1.6 0.190 4.826 0.085 2.159 inches mm inches mm 0.243 6.172
SMB DPAK
0.15 3.8 0.079 2.0
0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5
0.091 2.3
0.248 6.3
0.059 1.5
inches mm
SOT-223
POWER DISSIPATION The power dissipation of a surface mount thyristor is a function of the MT2 or anode pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheets for various packages, PD can be calculated as follows:
P D
The values for the equation are found in the maximum ratings table on the data sheets. For example, substituting these values into the equation for a SOT-223 at an ambient temperature TA of 25C, one can calculate the power dissipation of the device to be 550 milliwatts.
P D C * 25C + 550 milliwatts + 110 156CW
T T J(max) A R JA http://onsemi.com
638
The 156C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 550 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the MT2 or anode pad. By increasing the area of the MT2 or anode pad, the power dissipation
160 150 140 130 120 110 100 90 80 70 60 50 40 30
can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus MT2 or anode pad area for a SOT-223 package is shown in Figure 1.
R JA , JUNCTION TO AMBIENT THERMAL RESISTANCE, C/W
TYPICAL MAXIMUM DEVICE MOUNTED ON FIGURE 1 AREA = L2 PCB WITH TAB AREA AS SHOWN
L 4 1 2 3
MINIMUM FOOTPRINT = 0.076 cm2 0 2.0 4.0 6.0 FOIL AREA (cm2) 8.0 10
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same footprint.
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. The stencil opening size should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device. The delta temperature between the preheat and soldering should be 100C or less.* When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. The soldering temperature and time shall not exceed 260C for more than 10 seconds. When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. Mechanical stress or shock should not be applied during cooling. *Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
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STEP 2 STEP 3 VENT HEATING SOAK ZONES 2 & 5 RAMP
STEP 4 STEP 5 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SOAK SPIKE 170C 160C
STEP 6 STEP 7 VENT COOLING 205 TO 219C PEAK AT SOLDER JOINT
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
150C
100C 100C
140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
50C
DESIRED CURVE FOR LOW MASS ASSEMBLIES
TMAX
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Tape and Reel Packaging Specifications

SURFACE MOUNT (DPAK, SMB, SOT223) Embossed Tape and Reel is used to facilitate automatic pick and place equipment feed requirements. The tape is used as the shipping container for various products and requires a minimum of handling. The antistatic/conductive tape provides a secure cavity for the product when sealed with the peel-back cover tape. Two Reel Sizes Available (7 and 13) Used for Automatic Pick and Place Feed Systems Minimizes Product Handling EIA 481, 1, 2
Use the standard device title and add the required suffix as listed in the option table below. Note that the individual reels have a finite number of devices depending on the type of product contained in the tape. Also note the minimum lot size is one full reel for each line item, and orders are required to be in increments of the single reel quantity.
DEVICE ORIENTATION IN TAPE

SOT223
12 mm
SMB
12 mm
DPAK
16 mm
DIRECTION OF FEED
EMBOSSED TAPE AND REEL ORDERING INFORMATION

Tape Width (mm) 16 12 12 Pitch mm (inch) 8.0 0.1 (.315 .004) 8.0 0.1 (.315 .004) 8.0 0.1 (.315 .004) Reel Size mm (inch) 330 330 178 (13) (13) (7) Devices Per Reel and Minimum Order Quantity 2,500 2,500 1,000 Device Suffix T4 T3 T1
Package DPAK SMB SOT223
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SURFACE MOUNT (Continued)
EMBOSSED TAPE AND REEL DATA FOR DISCRETES

CARRIER TAPE SPECIFICATIONS
10 Pitches Cumulative Tolerance on Tape 0.2 mm ( 0.008) E Top Cover Tape A0 B0 P Embossment Center Lines of Cavity D1 For Components 2.0 mm x 1.2 mm and Larger
K t D
P0 P2
B1
K0 See Note 1
For Machine Reference Only Including Draft and RADII Concentric Around B0
User Direction of Feed * Top Cover Tape Thickness (t1) 0.10 mm (.004) Max.
Bar Code Label R Min Tape and Components Shall Pass Around Radius R Without Damage Bending Radius 10 Maximum Component Rotation 100 mm (3.937) 1 mm Max Typical Component Cavity Center Line Embossed Carrier
Embossment
Tape 1 mm (.039) Max Typical Component Center Line
Camber (Top View) Allowable Camber To Be 1 mm/100 mm Nonaccumulative Over 250 mm
250 mm (9.843)
DIMENSIONS
Tape Size 12 mm 16 mm B1 Max 8.2 mm (.323) 12.1 mm (.476) D 1.5 + 0.1 mm 0.0 (.059 + .004 0.0) D1 1.5 mm Min (.060) E 1.75 0.1 mm (.069 .004) F 5.5 0.05 mm (.217 .002) 7.5 0.10 mm (.295 .004) K 6.4 mm Max (.252) 7.9 mm Max (.311) P0 4.0 0.1 mm (.157 .004) P2 2.0 0.1 mm (.079 .002) R Min 30 mm (1.18) T Max 0.6 mm (.024) W Max 12 .30 mm (.470 .012) 16.3 mm (.642)
Metric dimensions govern English are in parentheses for reference only. NOTE 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within .05 mm min. to .50 mm max., the component cannot rotate more than 10 within the determined cavity. NOTE 2: Pitch information is contained in the Embossed Tape and Reel Ordering Information on pg. 641.
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SURFACE MOUNT (Continued)
EMBOSSED TAPE AND REEL DATA FOR DISCRETES
T Max Outside Dimension Measured at Edge
1.5 mm Min (.06) A 20.2 mm Min (.795)
13.0 mm 0.5 mm (.512 .002) 50 mm Min (1.969)
Full Radius
Inside Dimension Measured Near Hub
Size 12 mm 16 mm
A Max 330 mm (12.992) 360 mm (14.173)
G 12.4 mm + 2.0 mm, 0.0 (.49 + .079, 0.00) 16.4 mm + 2.0 mm, 0.0 (.646 + .078, 0.00)
T Max 18.4 mm (.72) 22.4 mm (.882)
Reel Dimensions
Metric Dimensions Govern English are in parentheses for reference only
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LEAD TAPE PACKAGING STANDARDS FOR AXIALLEAD COMPONENTS (DO41, Surmetic 50)
Table 1. Packaging Details (all dimensions in inches)
Device Title Suffix RL RL MPQ Quantity Per Reel (Item 3.3.7) 5000 1500 Component Spacing A Dimension 0.2 +/ 0.02 0.4 +/ 0.02 Tape Spacing B Dimension 2.062 +/ 0.059 2.062 +/ 0.059 Reel Dimension C 3 3 Reel Dimension D (Max) 14 14 Max Off Alignment E 0.047 0.047
Case Type Case 059A01 Case 26703
Product Category DO41 Plastic Axial Surmetic 50 Plastic Axial
Kraft Paper Reel Roll Pad Item 3.1.1 Max Off Alignment E Item 3.3.5 Both Sides
Overall LG Item 3.1.2 B A
Container Tape, Blue Item 3.2 (Cathode) Tape, White Item 3.2 (Anode)
D1
D2
0.250 Item 3.3.2 0.031 Item 3.3.5
Figure 3. Reel Packing

Optional Design 1.188 3.5 Dia.
Figure 4. Component Spacing
Item 3.4 D C
Figure 5. Reel Dimensions
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TO92 EIA, IEC, EIAJ Radial Tape in Fan Fold Box or On Reel
Radial tape in fan fold box or on reel of the reliable TO92 package are the best methods of capturing devices for automatic insertion in printed circuit boards. These methods of taping are compatible with various equipment for active and passive component insertion. Available in Fan Fold Box Available on 365 mm Reels Accommodates All Standard Inserters Allows Flexible Circuit Board Layout 2.5 mm Pin Spacing for Soldering EIA468, IEC 2862, EIAJ RC1008B
TO92 RADIAL TAPE IN FAN FOLD BOX OR ON REEL
Ordering Notes: When ordering radial tape in fan fold box or on reel, specify the style per Figures 7, 8, and 14 through 17. Add the suffix RLR and Style to the device title, i.e. 2N5060RLRA. This will be a standard 2N5060 radial taped and supplied on a reel per Figure 14. Fan Fold Box Information Minimum order quantity 1 Box. Order in increments of 2000. Reel Information Minimum order quantity 1 Reel. Order in increments of 2000.
US/EUROPEAN SUFFIX CONVERSIONS

U.S. RLRA RLRE RLRF RLRM RLRP ZL1 Europe Equivalent RL RL1 Reel or Fan Fold Box Radial tape & reel Radial tape & reel Radial tape & reel Radial tape & fan fold box Radial tape & fan fold box Qty Per 2K 2K 2K 2K 2K Description of TO92 & Tape Orientation Round side of TO92 and adhesive tape visible Flat side of TO92 and adhesive tape visible Round side of TO92 and adhesive tape on reverse side Flat side of TO92 and adhesive tape visible Round side of TO92 and adhesive tape visible
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TO92 EIA RADIAL TAPE IN FAN FOLD BOX OR ON REEL (Continued)
H2A
H2A
H2B
H2B

Millimeter Max Min

3.8 0.38 2.4 1.5 8.5 0 0 18 15.5 8.5 2.5 12.5 5.95 3.55 0.15 0.35 17.5 5.5 .15
Min
0.1496 0.015 0.0945 .059 0.3346 0 0 0.7086 0.610 0.3346 0.09842 0.4921 0.2342 0.1397 0.06 0.014 0.6889 0.2165 .0059
Max
4.2 0.51 2.8 4.0 9.5 1.0 1.0 19.5 16.5 11 12.9 6.75 3.95 0.20 1.44 0.65 19 6.3 0.5
0.1653 0.020 0.110 .156 0.3741 0.039 0.051 0.768 0.649 0.433 0.5079 0.2658 0.1556 0.08 0.0567 0.027 0.7481 0.2841 0.01968
NOTES:
1. Maximum alignment deviation between leads not to be greater than 0.2 mm. 2. Defective components shall be clipped from the carrier tape such that the remaining protrusion (L) does not exceed a maximum of 11 mm. 3. Component lead to tape adhesion must meet the pull test requirements established in Figures 10, 11 and 12. 4. Maximum noncumulative variation between tape feed holes shall not exceed 1 mm in 20 pitches. 5. Holddown tape not to extend beyond the edge(s) of carrier tape and there shall be no exposure of adhesive. 6. No more than 1 consecutive missing component is permitted. 7. A tape trailer and leader, having at least three feed holes is required before the first and after the last component. 8. Splices will not interfere with the sprocket feed holes.
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ADHESIVE TAPE ON TOP SIDE

FLAT SIDE

Figure 7. Style RLRM
FAN FOLD BOX STYLES

ADHESIVE TAPE ON TOP SIDE
ROUNDED SIDE 330 mm 13 MAX
CARRIER STRIP
CARRIER STRIP
252 mm 9.92
MAX
FLAT SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE. Style M fan fold box is equivalent to styles E and F of reel pack dependent on feed orientation from box.
ROUNDED SIDE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE. Style P fan fold box is equivalent to styles A and B of reel pack dependent on feed orientation from box.
58 mm 2.28 MAX
Figure 8. Style RLRP
Figure 9. Fan Fold Box Dimensions
ADHESION PULL TESTS

500 GRAM PULL FORCE
100 GRAM PULL FORCE

16 mm
70 GRAM PULL FORCE

16 mm
HOLDING FIXTURE
HOLDING FIXTURE
HOLDING FIXTURE There shall be no deviation in the leads and no component leads shall be pulled free of the tape with a 500 gram load applied to the component body for 3 1 second.
The component shall not pull free with a 300 gram load applied to the leads for 3 1 second.
The component shall not pull free with a 70 gram load applied to the leads for 3 1 second.
Figure 10. Test #1
Figure 11. Test #2
Figure 12. Test #3
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REEL STYLES
CORE DIA. 82mm 1mm
ARBOR HOLE DIA. 30.5mm 0.25mm MARKING NOTE
HUB RECESS 76.2mm 1mm RECESS DEPTH 9.5mm MIN 365mm + 3, 0mm 38.1mm 1mm 48 mm MAX
Material used must not cause deterioration of components or degrade lead solderability
Figure 13. Reel Specifications
CARRIER STRIP ADHESIVE TAPE
CARRIER STRIP ROUNDED SIDE FLAT SIDE ADHESIVE TAPE
FEED
FEED
Rounded side of transistor and adhesive tape visible.
Flat side of transistor and adhesive tape visible.
Figure 14. Style RLRA
Figure 15. Style RLRE
ADHESIVE TAPE ON REVERSE SIDE CARRIER STRIP ROUNDED SIDE
FEED
Rounded side of transistor and carrier strip visible (adhesive tape on reverse side).
Figure 16. Style RLRF
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CHAPTER 5 Outline Dimensions and Leadform Options
Page Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Leadform Options TO225AA (Case 77) . . . . . . . . . . . . . . . . . . . . . . . . . . 654 TO220 (Case 221A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
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Outline Dimensions
A R P L
SEATING PLANE
CASE 02911 TO-92 (TO226AA) STYLES 10, 12, 16 B

STYLE 10: PIN 1. CATHODE 2. GATE 3. ANODE STYLE 12: PIN 1. MAIN TERMINAL 1 2. GATE 3. MAIN TERMINAL 2
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 0.250 0.080 0.105 0.100 0.115 0.135 MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 6.35 2.04 2.66 2.54 2.93 3.43
STYLE 16: PIN 1. ANODE 2. GATE 3. CATHODE
X X G H V
1
D C N J
SECTION XX
DIM A B C D G H J K L N P R V
CASE 059A01 DO41 PLASTIC AXIAL (No Polarity)

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.260 0.110 0.120 0.030 0.034 1.100 MILLIMETERS MIN MAX 5.97 6.60 2.79 3.05 0.76 0.86 27.94
DIM A B D K
B U Q
CASE 07709 TO225AA (Formerly TO-126) STYLES 2, 5 F M C

STYLE 2: PIN 1. CATHODE 2. ANODE 3. GATE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D F G H J K M Q R S U V INCHES MIN MAX 0.425 0.435 0.295 0.305 0.095 0.105 0.020 0.026 0.115 0.130 0.094 BSC 0.050 0.095 0.015 0.025 0.575 0.655 5 _ TYP 0.148 0.158 0.045 0.065 0.025 0.035 0.145 0.155 0.040 MILLIMETERS MIN MAX 10.80 11.04 7.50 7.74 2.42 2.66 0.51 0.66 2.93 3.30 2.39 BSC 1.27 2.41 0.39 0.63 14.61 16.63 5 _ TYP 3.76 4.01 1.15 1.65 0.64 0.88 3.69 3.93 1.02
A
1 2 3
STYLE 5: PIN 1. MT 1 2. MT 2 3. GATE
V G S D 2 PL 0.25 (0.010)
M
J R 0.25 (0.010) A
M
A
M
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Outline Dimensions (continued)

CASE 221A07 TO220AB STYLES 3, 4 B F T
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.014 0.022 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.36 0.55 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 2.04
Q
1 2 3
C S
STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE
H K Z L V G D N J R U
STYLE 4: PIN 1. 2. 3. 4.
MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2
CASE 221A09 TO220AB STYLES 3, 4

4
T A C T S
SEATING PLANE STYLE 3: PIN 1. 2. 3. 4.
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 2.04
Q
1 2 3
H K Z L V G D N R J U
CATHODE ANODE GATE ANODE
STYLE 4: PIN 1. 2. 3. 4.
MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2
CASE 221C02 ISOLATED TO220 Full Pack STYLES 2, 3 B P N E

STYLE 3: PIN 1. MT 1 2. MT 2 3. GATE
F C
T S
SEATING PLANE STYLE 2: PIN 1. CATHODE 2. ANODE 3. GATE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. LEAD DIMENSIONS UNCONTROLLED WITHIN DIMENSION Z. DIM A B C D E F G H J K L N P Q R S Z INCHES MIN MAX 0.680 0.700 0.388 0.408 0.175 0.195 0.025 0.040 0.340 0.355 0.140 0.150 0.100 BSC 0.110 0.155 0.018 0.028 0.500 0.550 0.045 0.070 0.049 0.270 0.290 0.480 0.500 0.090 0.120 0.105 0.115 0.070 0.090 MILLIMETERS MIN MAX 17.28 17.78 9.86 10.36 4.45 4.95 0.64 1.01 8.64 9.01 3.56 3.81 2.54 BSC 2.80 3.93 0.46 0.71 12.70 13.97 1.15 1.77 1.25 6.86 7.36 12.20 12.70 2.29 3.04 2.67 2.92 1.78 2.28
H Y
Q
1 2 3
K Z L G D
3 PL
J R
M
0.25 (0.010)
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CASE 26703 SURMETIC 50 PLASTIC AXIAL (No Polarity) STYLE 2 K D
1 2 STYLE 2: NO POLARITY DIM A B D K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.370 0.380 0.190 0.210 0.048 0.052 1.000 MILLIMETERS MIN MAX 9.40 9.65 4.83 5.33 1.22 1.32 25.40
CASE 318E04 SOT223 STYLES 10, 11 A F

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES DIM MIN MAX A 0.249 0.263 B 0.130 0.145 C 0.060 0.068 D 0.024 0.035 F 0.115 0.126 G 0.087 0.094 H 0.0008 0.0040 J 0.009 0.014 K 0.060 0.078 L 0.033 0.041 M 0_ 10 _ S 0.264 0.287 MILLIMETERS MIN MAX 6.30 6.70 3.30 3.70 1.50 1.75 0.60 0.89 2.90 3.20 2.20 2.40 0.020 0.100 0.24 0.35 1.50 2.00 0.85 1.05 0_ 10 _ 6.70 7.30
STYLE 10: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE
S
1 2 3
STYLE 11: PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2
D L G J C 0.08 (0003) H M K
CASE 36907 DPAK STYLES 4, 5, 6
B V R
4
C E
STYLE 4: PIN 1. 2. 3. 4. STYLE 5: PIN 1. 2. 3. 4. STYLE 6: PIN 1. 2. 3. 4.
CATHODE ANODE GATE ANODE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.175 0.215 0.050 0.090 0.030 0.050 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.46 1.27 2.28 0.77 1.27
A
1 2 3
S T
SEATING PLANE
GATE ANODE CATHODE ANODE
MT1 MT2 GATE MT2
F D G
3 PL
J H 0.13 (0.005)
M
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CASE 369A13 DPAK STYLES 4, 5, 6 T B V R
4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
C E Z
A S
1 2 3
K F L D G
2 PL
U
STYLE 4: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 5: PIN 1. 2. 3. 4. GATE ANODE CATHODE ANODE
J H 0.13 (0.005) T
STYLE 6: PIN 1. 2. 3. 4.
DIM A B C D E F G H J K L R S U V Z
INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 0.030 0.050 0.138
MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 0.77 1.27 3.51
MT1 MT2 GATE MT2
CASE 403C01 SMB (No Polarity) (Essentially JEDEC DO214AA) S A

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. D DIMENSION SHALL BE MEASURED WITHIN DIMENSION P. INCHES DIM MIN MAX A 0.160 0.180 B 0.130 0.150 C 0.075 0.095 D 0.077 0.083 H 0.0020 0.0060 J 0.006 0.012 K 0.030 0.050 P 0.020 REF S 0.205 0.220 MILLIMETERS MIN MAX 4.06 4.57 3.30 3.81 1.90 2.41 1.96 2.11 0.051 0.152 0.15 0.30 0.76 1.27 0.51 REF 5.21 5.59
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Leadform Options TO-225AA (Case 77)

Plastic packaged semiconductors may be leadformed to a variety of configurations for insertion into sockets or circuit boards. Leadform options require assignment of a special part number before ordering. To order leadformed product, determine the desired leadform, the case number and applicable leadform number, then contact your local ON Semiconductor representative for the special part number and pricing. Leadform orders require a minimum order quantity of 25,000 and are non-cancellable after processing. Additional leadform options not listed in this document may also be available. Please consult product engineering for information.
CASE 77 LEADFORM VC
CASE 77 LEADFORM VP
0.340 .005 0.510 .005 0.365 0.015
UNDERSIDE OF LEAD
0.050 REF.
0.100 0.02 0.220 .005
C L
0.500 .005 0.330 .005

C L
BOTTOM OF HEATSINK
0.187 0.03
0.378 0.02
MOUNTING SURFACE (Metal)
0.025 R MAX. TYP.
CASE 77 LEADFORM VS
0.278 REF. 0.740 MIN. 0.840 MIN.
UNDERSIDE OF LEAD 0.050 REF. 0.018 RAW LEAD (REF.)
0.050 MAX. BOTTOM OF HEATSINK 0.200 .01 30 REF. 0.180 .03
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Leadform Options TO-220 (Case 221A)

Leadform options require assignment of a special part number before ordering. Contact your local ON Semiconductor representative for special part number and pricing. 25,000 piece minimum quantity orders are required. Leadform orders are non-cancellable after processing. Leadforms apply to both ON Semiconductor Case 221A-07 and 221A-09 except as noted. Additional leadform options not listed in this document may also be available. Please consult product engineering for information.
CASE 221A (TO220) LEADFORM AJ CASE 221A (TO220) LEADFORM BV
CASE 221A-07 221A-09
A 0.360 0.010 Lead Not Trimmed 0.300 Min. 0.005 0.005
.100 REF. .200 REF. .050 REF. .032 REF. 0.102 0.005
"
.765 .01
0.680 0.005
" .004
.017 A
" .010
.580 .06 R
CASE 221A (TO220) LEADFORM DP
CASE 221A (TO220) LEADFORM CG
0.500 REF. 0.625 0.01 0.03 RAD. TYP. SEATING PLANE 0.120 0.020 0.600 0.015 0.100 0.015
0.100 0.030
0.060 0.065 0.005 0.20 RAD. TYP.
0.95 REF. UNDERSIDE OF LEAD BOTTOM OF HEATSINK
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CHAPTER 6 Index and Cross Reference
Page
Index and Cross Reference . . . . . . . . . . . . . . . . . . . . . . 657
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Index and Cross Reference

The following table represents a cross reference guide for all Thyristors that ON Semiconductor manufactures. Where ON Semiconductor part numbers are shown in bold the device is a form, fit, and function replacement for the industry part number, although some very minor differences may exist.

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number 2N1601 2N1602 2N1603 2N1604 2N1770 2N1771 2N1771A 2N1772 2N1772A 2N1773 2N1773A 2N1774 2N1774A 2N1775 2N1775A 2N1776 2N1776A 2N1777 2N1777A 2N1778 2N1778A 2N2575 2N2576 2N2679 2N2680 2N2682 2N2683 2N2684 2N2685 2N2686 2N2687 2N2688 2N2689 2N2690 2N2919 2N3001 2N3002 2N3003 2N3004 2N3005 2N3006 2N3007 2N3008 2N3027 2N3028 2N3029 2N3030 MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12M MCR12M 2N6505 2N6507 MCR1003 MCR1003 MCR1004 MCR1003 MCR1003 MCR1003 MCR1004 MCR1003 MCR1003 MCR1003 MCR1004 MCR12M MCR1003 MCR1003 MCR1003 MCR1004 MCR1003 MCR1003 MCR1003 MCR1004 MCR1003 MCR1003 MCR1003 MCR1003 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 251, 298 251, 298 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 250, 518 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 2N3031 2N3032 2N3228 2N3254 2N3255 2N3256 2N3257 2N3258 2N3259 2N3269 2N3270 2N3271 2N3272 2N3668 2N3669 2N3936 2N3937 2N3938 2N3939 2N3940 2N4096 2N4097 2N4098 2N4101 2N4102 2N4103 2N4108 2N4109 2N4110 2N4144 2N4145 2N4147 2N4148 2N4149 2N4167 2N4168 2N4169 2N4170 2N4171 2N4172 2N4173 2N4174 2N4183 2N4184 2N4185 2N4186 2N4187 MCR1003 MCR1003 MCR12M MCR1003 MCR1003 MCR1003 MCR1003 MCR1003 MCR1003 MCR12D MCR12D MCR12D MCR12D 2N6507 2N6507 MCR12D MCR12D MCR12D MCR12D MCR12M MCR1003 MCR1003 MCR1004 MCR12M MCR12M 2N6508 MCR1003 MCR1003 MCR1004 MCR1003 MCR1003 MCR1003 MCR1003 MCR1004 MCR12D MCR12D MCR12D MCR12D MCR12D MCR12D MCR12M MCR12M MCR12D MCR12D MCR12D MCR12D MCR12D 249, 566 249, 566 250, 518 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 250, 518 250, 518 250, 518 250, 518 251, 298 251, 298 250, 518 250, 518 250, 518 250, 518 250, 518 249, 566 249, 566 249, 566 250, 518 250, 518 251, 298 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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657

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number 2N4188 2N4189 2N4190 2N4332 2N4333 2N4334 2N4335 2N4336 2N4441 2N4442 2N4443 2N4444 2N5060 2N5061 2N5062 2N5064 2N5722 2N5724 2N5725 2N5726 2N5754 2N5755 2N5756 2N5757 2N6027 2N6028 2N6068 2N6068A 2N6069 2N6069A 2N6070 2N6070A 2N6071A 2N6071B 2N6072 2N6072A 2N6073 2N6073A 2N6073B 2N6074B 2N6075A 2N6075B 2N6151 2N6152 2N6153 2N6154 2N6155 2N6156 2N6234 2N6235 2N6236 2N6237 2N6238 2N6239 MCR12D MCR12M MCR12M MCR1003 MCR1003 MCR1003 MCR1004 MCR1004 MCR2182 MCR2184 MCR2186 MCR12M 2N5060 2N5061 2N5062 2N5064 MCR1006 MCR1003 MCR1003 MCR1004 2N6071A 2N6071A 2N6073A 2N6073A 2N6027 2N6028 2N6071A 2N6071A 2N6071A 2N6071A 2N6071A 2N6071A 2N6071A 2N6071B 2N6073A 2N6073A 2N6073A 2N6073A 2N6073B 2N6075B 2N6075A 2N6075B MAC210A8 MAC210A8 MAC210A8 MAC210A8 MAC210A8 MAC210A8 MCR1066 MCR1066 MCR1066 MCR1066 MCR1066 MCR1066 250, 518 250, 518 250, 518 249, 566 249, 566 249, 566 249, 566 249, 566 250, 575 250, 575 250, 575 250, 518 249, 258 249, 258 249, 258 249, 258 249, 566 249, 566 249, 566 249, 566 252, 272 252, 272 252, 272 252, 272 256, 265 256, 265 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 252, 272 254, 433 254, 433 254, 433 254, 433 254, 433 254, 433 249, 572 249, 572 249, 572 249, 572 249, 572 249, 572 2N6240 2N6241 2N6342 2N6342A 2N6343 2N6343A 2N6344 2N6344A 2N6345 2N6345A 2N6346 2N6346A 2N6347 2N6347A 2N6348 2N6348A 2N6349 2N6349A 2N6394 2N6395 2N6396 2N6397 2N6398 2N6399 2N6400 2N6401 2N6402 2N6403 2N6404 2N6405 2N6504 2N6505 2N6506 2N6507 2N6508 2N6509 2N877 2N878 2N879 2N880 2N881 2N884 2N885 2N886 2N887 2N888 2N889 2N948 2N949 2N950 B136500F B136600F B136800F B149B MCR1066 MCR1068 2N6344 2N6344 2N6344 2N6344A 2N6344 2N6344A 2N6349 2N6349A 2N6348A 2N6348A 2N6348A 2N6348A 2N6348A 2N6348A 2N6349 2N6349A 2N6394 2N6395 2N6397 2N6397 2N6399 2N6399 2N6400 2N6401 2N6402 2N6403 2N6404 2N6405 2N6504 2N6505 2N6507 2N6507 2N6508 2N6509 MCR1003 MCR1003 MCR1003 MCR1004 MCR1004 MCR1003 MCR1003 MCR1003 MCR1003 MCR1004 MCR1004 MCR1003 MCR1003 MCR1003 MAC4M MAC4M MAC4N MCR1004 249, 572 249, 572 253, 278 253, 278 253, 278 254, 283 253, 278 254, 283 253, 278 254, 283 254, 283 254, 283 254, 283 254, 283 254, 283 254, 283 253, 278 254, 283 251, 288 251, 288 251, 288 251, 288 251, 288 251, 288 251, 293 251, 293 251, 293 251, 293 251, 293 251, 293 251, 298 251, 298 251, 298 251, 298 251, 298 251, 298 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 253, 348 253, 348 253, 348 249, 566 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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658

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number B149D B149E B149G BCR10CM12 BCR10CM8 BCR10PM12 BCR10PM8 BCR12CM12 BCR12CM8 BCR12PM12 BCR12PM8 BCR16CM12 BCR16CM8 BCR16PM12 BCR16PM8 BCR20AM12 BCR20AM8 BCR5AM12 BCR5AM8 BCR5AS4 BCR5AS8 BCR5PM12 BCR5PM8 BCR6AM12 BCR6AM8 BCR8CM12 BCR8CM8 BRB10400B BRX44 BRX45 BRX46 BRX47 BRX49 BRY55100 BRY55200 BRY5530 BRY55400 BRY55500 BRY5560 BRY55600 BRY55M300 BRY55M400 BRY55M600 BT131500 BT131600 BT132500D BT132600D BT134500D BT134600D BT134W500D BT134W500E BT134W600D BT134W600E BT136500 MCR1006 MCR1008 MCR1008 MAC210A8 MAC210A8 MAC210A8FP MAC210A8FP MAC12M MAC12D MAC212A8FP MAC212A6FP MAC16CM MAC16CD MAC15A8FP MAC15A6FP MAC223A8 MAC223A6 MAC8SM MAC8SD MAC4DCMT4 MAC4DCMT4 MAC229A8FP MAC229A8FP MAC8M MAC8D MAC8M MAC8D MAC12D MCR1003 MCR1003 MCR1003 MCR1004 MCR1006 MCR1003 MCR1004 MCR1003 MCR1006 MCR1008 MCR1003 MCR1008 MCR1006 MCR1006 MCR1008 MAC997B8 MAC997B8 MAC997A8 MAC997A8 2N6075A 2N6075A MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC4M 249, 566 249, 566 249, 566 254, 433 254, 433 254, 438 254, 438 254, 374 254, 374 254, 443 254, 443 255, 410 255, 410 255, 394 255, 394 255, 457 255, 457 253, 363 253, 363 252, 320 252, 320 253, 474 253, 474 253, 358 253, 358 253, 358 253, 358 254, 374 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 252, 483 252, 483 252, 483 252, 483 252, 272 252, 272 252, 311 252, 311 252, 311 252, 311 253, 348 BT136500D BT136500E BT136500G BT136600 BT136600D BT136600E BT136600G BT136800 BT136800E BT136800G BT136F500G BT136F600G BT136F800G BT136S500 BT136S500D BT136S500E BT136S600 BT136S600D BT136S600E BT136S800 BT136S800E BT136X500G BT136X600G BT136X800G BT137500 BT137500D BT137500E BT137600 BT137600D BT137600E BT137800 BT137800E BT137F500 BT137F600 BT137F800 BT137G500 BT137G600 BT137G800 BT137X500D BT137X500E BT137X500G BT137X600D BT137X600E BT137X600G BT137X800E BT137X800G BT138500 BT138500E BT138500G BT138600 BT138600E BT138600G BT138800 BT138800E MAC8SM MAC4SM MAC9M MAC4M MAC8SM MAC4SM MAC9M MAC4N MAC4SN MAC9N MAC218A10FP MAC218A10FP MAC218A10FP MAC4DCMT4 MAC4DHMT4 MAC4DSMT4 MAC4DCMT4 MAC4DHMT4 MAC4DSMT4 MAC4DCNT4 MAC4DSNT4 MAC218A10FP MAC218A10FP MAC218A10FP MAC8M MAC228A8 MAC228A8 MAC8M MAC228A8 MAC228A8 MAC8N MAC228A10 MAC218A10FP MAC218A10FP MAC218A10FP MAC9M MAC9M MAC9N MAC229A8FP MAC229A8FP MAC218A10FP MAC229A8FP MAC229A8FP MAC218A10FP MAC229A10FP MAC218A10FP MAC12HCM MAC12SM MAC12M MAC12HCM MAC12SM MAC12M MAC12HCN MAC12SN 253, 363 253, 353 253, 369 253, 348 253, 363 253, 353 253, 369 253, 348 253, 353 253, 369 253, 453 253, 453 253, 453 252, 320 252, 328 252, 340 252, 320 252, 328 252, 340 252, 320 252, 340 253, 453 253, 453 253, 453 253, 358 253, 470 253, 470 253, 358 253, 470 253, 470 253, 358 253, 470 253, 453 253, 453 253, 453 253, 369 253, 369 253, 369 253, 474 253, 474 253, 453 253, 474 253, 474 253, 453 253, 474 253, 453 254, 379 254, 384 254, 374 254, 379 254, 384 254, 374 254, 379 254, 384 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
http://onsemi.com
659

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number BT138800G BT138X500 BT138X500F BT138X500G BT138X600 BT138X600F BT138X600G BT138X800 BT138X800F BT138X800G BT139500 BT139500E BT139500F BT139500G BT139500H BT139600 BT139600E BT139600F BT139600G BT139600H BT139800 BT139800E BT139800F BT139800G BT139800H BT139X500 BT139X500F BT139X500G BT139X500H BT139X600 BT139X600F BT139X600G BT139X600H BT139X800 BT139X800F BT139X800G BT139X800H BT145500R BT145600R BT145800R BT148400R BT148500R BT148600R BT148S600Z BT148W400R BT148W500R BT148W600R BT150500R BT150600R BT150800R BT150M500R BT150M600R BT150S500R BT150S600R MAC12N MAC212A8FP MAC212A8FP MAC212A8FP MAC212A8FP MAC212A8FP MAC212A8FP MAC212A10FP MAC212A10FP MAC212A10FP MAC16M MAC15SM MAC16M MAC16M MAC16HCM MAC16M MAC15SM MAC16M MAC16M MAC16HCM MAC16N MAC15SN MAC16N MAC16N MAC16HCN MAC15A8FP MAC15A8FP MAC15A8FP MAC15A8FP MAC15A8FP MAC15A8FP MAC15A8FP MAC15A8FP MAC15A10FP MAC15A10FP MAC15A10FP MAC15A10FP MCR25M MCR25M MCR25N MCR1066 MCR1068 MCR1068 MCR708AT4 MCR08MT1 MCR08MT1 MCR08MT1 MCR8SM MCR8SM MCR8SN MCR718T4 MCR718T4 MCR708AT4 MCR708AT4 254, 374 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 255, 415 254, 404 255, 415 255, 415 255, 420 255, 415 254, 404 255, 415 255, 415 255, 420 255, 415 254, 404 255, 415 255, 415 255, 420 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 255, 394 251, 550 251, 550 251, 550 249, 572 249, 572 249, 572 249, 597 249, 491 249, 491 249, 491 250, 514 250, 514 250, 514 249, 602 249, 602 249, 597 249, 597 BT151500R BT151650R BT151800R BT151S500R BT151S650R BT151S800R BT151X500R BT151X650R BT151X800R BT152400R BT152600R BT152800R BT152X400R BT152X600R BT152X800R BT168B BT168BW BT168D BT168DW BT168E BT168EW BT168G BT168GW BT169B BT169D BT169DW BT169E BT169G BT258500R BT258600R BT258800R BT300500R BT300600R BT300800R BT300S500R BT300S600R BT300S800R BT300X500R BT300X600R BT300X800R BTA06400B BTA06400C BTA06600B BTA06600C BTA06700B BTA06700C BTA06800B BTA06800C BTA08400B BTA08400BW BTA08400C BTA08400SW BTA08400TW BTA08600B MCR12M MCR12N MCR12N MCR12DCMT4 MCR12DCNT4 MCR12DCNT4 MCR21810FP MCR21810FP MCR21810FP MCR25D MCR25M MCR25N MCR2258FP MCR2258FP MCR22510FP MCR1004 MCR08BT1 MCR1006 MCR08MT1 MCR1008 MCR08MT1 MCR1008 MCR08MT1 MCR1004 MCR1006 MCR08MT1 MCR1008 MCR1008 MCR8SM MCR8SM MCR8SN MCR8M MCR8M MCR8N MCR12DCMT4 MCR12DCMT4 MCR12DCNT4 MCR21810FP MCR21810FP MCR21810FP MAC218A6FP MAC229A8FP MAC218A10FP MAC229A8FP MAC218A10FP MAC229A10FP MAC218A10FP MAC229A10FP MAC218A6FP MAC218A6FP MAC229A8FP MAC229A8FP MAC229A8FP MAC218A10FP 250, 518 250, 518 250, 518 250, 522 250, 522 250, 522 250, 579 250, 579 250, 579 251, 550 251, 550 251, 550 251, 584 251, 584 251, 584 249, 566 249, 491 249, 566 249, 491 249, 566 249, 491 249, 566 249, 491 249, 566 249, 566 249, 491 249, 566 249, 566 250, 514 250, 514 250, 514 250, 510 250, 510 250, 510 250, 522 250, 522 250, 522 250, 579 250, 579 250, 579 253, 453 253, 474 253, 453 253, 474 253, 453 253, 474 253, 453 253, 474 253, 453 253, 453 253, 474 253, 474 253, 474 253, 453 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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660

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number BTA08600BW BTA08600C BTA08600SW BTA08600TW BTA08700B BTA08700BW BTA08700C BTA08700SW BTA08700TW BTA08800B BTA08800BW BTA08800C BTA10400B BTA10400BW BTA104500 BTA104600 BTA104800 BTA10600B BTA10600BW BTA10700B BTA10700BW BTA10800B BTA10800BW BTA12400B BTA12400BW BTA12600B BTA12600BW BTA12700B BTA12700BW BTA12800B BTA12800BW BTA16400BW BTA16600BW BTA16700BW BTA16800BW BTA204500B BTA204500C BTA204500D BTA204500E BTA204500F BTA204600B BTA204600C BTA204600D BTA204600E BTA204600F BTA204800B BTA204800C BTA204800E BTA204800F BTA204S500B BTA204S500C BTA204S500D BTA204S500E BTA204S500F MAC218A10FP MAC229A8FP MAC229A8FP MAC229A8FP MAC218A10FP MAC218A10FP MAC229A10FP MAC229A10FP MAC229A10FP MAC218A10FP MAC218A10FP MAC229A10FP MAC210A8FP MAC210A8FP MAC223A8 MAC223A8 MAC223A10 MAC210A8FP MAC210A8FP MAC210A10FP MAC210A10FP MAC210A10FP MAC210A10FP MAC212A6FP MAC212A6FP MAC212A8FP MAC212A8FP MAC212A10FP MAC212A10FP MAC212A10FP MAC212A10FP MAC15A6FP MAC15A8FP MAC15A10FP MAC15A10FP MAC4M MAC4M MAC4SM MAC4SM MAC4M MAC4M MAC4M MAC4SM MAC4SM MAC4M MAC4N MAC4N MAC4SN MAC4N MAC4DCMT4 MAC4DCMT4 MAC4DHMT4 MAC4DSMT4 MAC4DCMT4 253, 453 253, 474 253, 474 253, 474 253, 453 253, 453 253, 474 253, 474 253, 474 253, 453 253, 453 253, 474 254, 438 254, 438 255, 457 255, 457 255, 457 254, 438 254, 438 254, 438 254, 438 254, 438 254, 438 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 254, 443 255, 394 255, 394 255, 394 255, 394 253, 348 253, 348 253, 353 253, 353 253, 348 253, 348 253, 348 253, 353 253, 353 253, 348 253, 348 253, 348 253, 353 253, 348 252, 320 252, 320 252, 328 252, 340 252, 320 BTA204S600D BTA204S600E BTA204S600F BTA204S800B BTA204S800C BTA204S800E BTA204S800F BTA204W500B BTA204W500C BTA204W500D BTA204W500E BTA204W500F BTA204W600B BTA204W600C BTA204W800B BTA204W800C BTA204X500B BTA204X500C BTA204X500D BTA204X500E BTA204X500F BTA204X600B BTA204X600C BTA204X600D BTA204X600E BTA204X600F BTA204X800B BTA204X800C BTA204X800E BTA204X800F BTA208500B BTA208600B BTA208600D BTA208600E BTA208600F BTA208800B BTA208800E BTA208800F BTA208X600D BTA208X600E BTA208X600F BTA208X800E BTA208X800F BTA210500B BTA210600B BTA210800B BTA212500B BTA212600B BTA212600D BTA212600E BTA212600F BTA212800B BTA212800E BTA212800F MAC4DHMT4 MAC4DSMT4 MAC4DCMT4 MAC4DCNT4 MAC4DCNT4 MAC4DSNT4 MAC4DCNT4 MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC08MT1 MAC218A10FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC218A10FP MAC229A10FP MAC229A8FP MAC229A8FP MAC229A8FP MAC218A10FP MAC229A10FP MAC229A10FP MAC229A10FP MAC9M MAC9M MAC8SM MAC8SM MAC8M MAC9N MAC8SN MAC8N MAC229A8FP MAC229A8FP MAC229A10FP MAC229A10FP MAC229A10FP MAC16HCM MAC16HCM MAC16HCN MAC12HCM MAC12HCM MAC12SM MAC12SM MAC12SM MAC12HCN MAC12SN MAC12SN 252, 328 252, 340 252, 320 252, 320 252, 320 252, 340 252, 320 252, 311 252, 311 252, 311 252, 311 252, 311 252, 311 252, 311 252, 311 252, 311 253, 453 253, 474 253, 474 253, 474 253, 474 253, 453 253, 474 253, 474 253, 474 253, 474 253, 453 253, 474 253, 474 253, 474 253, 369 253, 369 253, 363 253, 363 253, 358 253, 369 253, 363 253, 358 253, 474 253, 474 253, 474 253, 474 253, 474 255, 420 255, 420 255, 420 254, 379 254, 379 254, 384 254, 384 254, 384 254, 379 254, 384 254, 384 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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661

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number BTA216600D BTA216600E BTA216600F BTA216800E BTA216800F BTA216X500B BTA216X600B BTA216X800B BTA225500B BTA225500C BTA225600B BTA225600C BTA225800B BTA225800C BTA24600BW BTA24700BW BTA24800BW BTB08400B BTB08400BW BTB08400C BTB08400CW BTB08600B BTB08600BW BTB08600C BTB08600CW BTB08700B BTB08700BW BTB08700C BTB08700CW BTB08800B BTB08800BW BTB08800CW BTB10400B BTB10400BW BTB10400C BTB10400CW BTB10600B BTB10600BW BTB10600C BTB10600CW BTB10700B BTB10700BW BTB10700C BTB10700CW BTB10800B BTB10800BW BTB10800C BTB10800CW BTB12400B BTB12400BW BTB12400C BTB12400CW BTB12600B BTB12600BW MAC15SM MAC15SM MAC16CM MAC15SN MAC16CN MAC15A8FP MAC15A8FP MAC15A10FP MAC223A8 MAC223A8 MAC223A8 MAC223A8 MAC223A10 MAC223A10 MAC223A8FP MAC223A10FP MAC223A10FP MAC9D MAC9D MAC8SD MAC8D MAC9M MAC9M MAC8SM MAC8M MAC9N MAC9N MAC8SN MAC8N MAC9N MAC9N MAC8N MAC210A8 MAC210A8 MAC12D MAC12D MAC210A8 MAC210A8 MAC12M MAC12M MAC210A10 MAC210A10 MAC12N MAC12N MAC210A10 MAC210A10 MAC12N MAC12N MAC12HCD MAC12HCD MAC12D MAC12D MAC12HCM MAC12HCM 254, 404 254, 404 255, 410 254, 404 255, 410 255, 394 255, 394 255, 394 255, 457 255, 457 255, 457 255, 457 255, 457 255, 457 255, 461 255, 461 255, 461 253, 369 253, 369 253, 363 253, 358 253, 369 253, 369 253, 363 253, 358 253, 369 253, 369 253, 363 253, 358 253, 369 253, 369 253, 358 254, 433 254, 433 254, 374 254, 374 254, 433 254, 433 254, 374 254, 374 254, 433 254, 433 254, 374 254, 374 254, 433 254, 433 254, 374 254, 374 254, 379 254, 379 254, 374 254, 374 254, 379 254, 379 BTB12600C BTB12600CW BTB12700B BTB12700BW BTB12700C BTB12700CW BTB12800B BTB12800BW BTB12800C BTB12800CW BTB16400B BTB16400BW BTB16400CW BTB16600B BTB16600BW BTB16600CW BTB16700B BTB16700BW BTB16700CW BTB16800B BTB16800BW BTB16800CW BTB24400B BTB24600B BTB24600BW BTB24700B BTB24700BW BTB24800B BTB24800BW C106B C106D C106D1 C106F C106M C106M1 C122A1 C122B1 C122D1 C122F1 C122M1 C122N1 CR1800SA CR1800SB CR1800SC CR2300SA CR2300SB CR2300SC CR2600SA CR2600SB CR2600SC CR3100SA CR3100SB CR3100SC CR5AS12 MAC12M MAC12M MAC12HCN MAC12HCN MAC12N MAC12N MAC12HCN MAC12HCN MAC12N MAC12N MAC223A6 MAC16HCD MAC16CD MAC223A8 MAC16HCM MAC16CM MAC223A10 MAC16HCN MAC16CN MAC223A10 MAC16HCN MAC16CN MAC223A6 MAC223A8 MAC223A8 MAC223A10 MAC223A10 MAC223A10 MAC223A10 C106B C106D C106D1 C106B C106M C106M1 C122B1 C122B1 MCR2186 C122F1 MCR2186 MCR8N MMT05B230T3 MMT10B230T3 MMT10B230T3 MMT05B260T3 MMT10B260T3 MMT10B260T3 MMT05B260T3 MMT10B260T3 MMT10B260T3 MMT05B310T3 MMT10B310T3 MMT10B310T3 MCR8DSNT4 254, 374 254, 374 254, 379 254, 379 254, 374 254, 374 254, 379 254, 379 254, 374 254, 374 255, 457 255, 420 255, 410 255, 457 255, 420 255, 410 255, 457 255, 420 255, 410 255, 457 255, 420 255, 410 255, 457 255, 457 255, 457 255, 457 255, 457 255, 457 255, 457 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 250, 308 250, 308 250, 575 250, 308 250, 575 250, 510 256, 615 256, 621 256, 621 256, 615 256, 621 256, 621 256, 615 256, 621 256, 621 256, 615 256, 621 256, 621 250, 504 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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662

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number CR5AS8 CR6CM12 CR6CM8 CR8AM12 CR8AM8 EC103A EC103A3 EC103B EC103B3 EC103C EC103C3 EC103D EC103D3 EC103E EC103E3 EC103M EC103M3 EC113A EC113A3 EC113B EC113B3 EC113C EC113C3 EC113D EC113D3 EC113E EC113E3 EC113M EC113M3 K1200G K2400G L2004F31 L2004F51 L2004F61 L2004F81 L2004L5 L2004L6 L2004L8 L2006L5 L2006L6 L2006L8 L2008L6 L2008L8 L201E3 L201E5 L201E6 L201E8 L2X8E3 L2X8E5 L2X8E6 L2X8E8 L4004F31 L4004F51 L4004F61 MCR8DSMT4 MCR12LM MCR12LD MCR12LM MCR12LD MCR1003 MCR1003 MCR1004 MCR1004 MCR1006 MCR1006 MCR1006 MCR1006 MCR1008 MCR1008 MCR1008 MCR1008 MCR1003 MCR1003 MCR1004 MCR1004 MCR1006 MCR1006 MCR1006 MCR1006 MCR1008 MCR1008 MCR1008 MCR1008 MKP3V120 MKP3V240 2N6071B 2N6071B 2N6071A 2N6071A MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC997B6 MAC997B6 MAC97A4 MAC978 MAC997B6 MAC997B6 MAC97A4 MAC978 2N6073B 2N6073B 2N6073A 250, 504 250, 534 250, 534 250, 534 250, 534 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 256, 611 256, 611 252, 272 252, 272 252, 272 252, 272 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 252, 483 252, 483 252, 425 252, 425 252, 483 252, 483 252, 425 252, 425 252, 272 252, 272 252, 272 L4004F81 L4004L5 L4004L6 L4004L8 L4006L5 L4006L6 L4006L8 L4008L6 L4008L8 L401E3 L401E5 L401E6 L401E8 L4X8E3 L4X8E5 L4X8E6 L4X8E8 L6004F31 L6004F51 L6004F61 L6004F81 L6004L5 L6004L8 L6006L5 L6006L6 L6006L8 L6008L6 L6008L8 L601E3 L601E5 L601E6 L601E8 L694L6 L6X8E3 L6X8E5 L6X8E6 L6X8E8 MAC08BT1 MAC08DTI MAC08MT1 MAC12D MAC12HCD MAC12HCM MAC12HCN MAC12M MAC12N MAC12SM MAC12SN MAC1510 MAC1510FP MAC154 MAC154FP MAC156 MAC156FP 2N6073A MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC997B6 MAC997B6 MAC97A6 MAC978 MAC997B6 MAC997B6 MAC97A6 MAC978 2N6075B 2N6075B 2N6075A 2N6075A MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC229A8FP MAC997B8 MAC997B8 MAC97A8 MAC978 MAC229A8FP MAC997B8 MAC997B8 MAC97A8 MAC978 MAC08BT1 MAC08MT1 MAC08MT1 MAC12D MAC12HCD MAC12HCM MAC12HCN MAC12M MAC12N MAC12SM MAC12SN MAC1510 MAC15A10FP MAC15A6 MAC15A6FP MAC15A6 MAC15A6FP 252, 272 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 252, 483 252, 483 252, 425 252, 425 252, 483 252, 483 252, 425 252, 425 252, 272 252, 272 252, 272 252, 272 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 253, 474 252, 483 252, 483 252, 425 252, 425 253, 474 252, 483 252, 483 252, 425 252, 425 252, 311 252, 311 252, 311 254, 374 254, 379 254, 379 254, 379 254, 374 254, 374 254, 384 254, 384 255, 389 255, 394 255, 389 255, 394 255, 389 255, 394 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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663

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number MAC158 MAC158FP MAC15A10 MAC15A10FP MAC15A4 MAC15A4FP MAC15A6 MAC15A6FP MAC15A8 MAC15A8FP MAC15D MAC15M MAC15N MAC15SD MAC15SM MAC15SN MAC16CD MAC16CM MAC16CN MAC16D MAC16HCD MAC16HCM MAC16HCN MAC16M MAC16N MAC21010 MAC21010FP MAC2104 MAC2104FP MAC2106 MAC2106FP MAC2108 MAC2108FP MAC210A10 MAC210A10FP MAC210A4 MAC210A4FP MAC210A6 MAC210A6FP MAC210A8 MAC210A8FP MAC21210 MAC21210FP MAC2124 MAC2124FP MAC2126 MAC2126FP MAC2128 MAC2128FP MAC212A10 MAC212A10FP MAC212A4 MAC212A4FP MAC212A6 MAC158 MAC15A8FP MAC15A10 MAC15A10FP MAC15A6 MAC15A6FP MAC15A6 MAC15A6FP MAC15A8 MAC15A8FP MAC15M MAC15M MAC15N MAC15SD MAC15SM MAC15SN MAC16CD MAC16CM MAC16CN MAC16D MAC16HCD MAC16HCM MAC16HCN MAC16M MAC16N MAC210A10 MAC210A10FP MAC210A8 MAC210A8FP MAC210A8 MAC210A8FP MAC210A8 MAC210A8FP MAC210A10 MAC210A10FP MAC210A8 MAC210A8FP MAC210A8 MAC210A8FP MAC210A8 MAC210A8FP MAC212A10 MAC212A10FP MAC212A8 MAC212A6FP MAC212A8 MAC212A6FP MAC212A8 MAC212A8FP MAC212A10 MAC212A10FP MAC212A8 MAC212A6FP MAC212A8 255, 389 255, 394 255, 389 255, 394 255, 389 255, 394 255, 389 255, 394 255, 389 255, 394 254, 399 254, 399 254, 399 254, 404 254, 404 254, 404 255, 410 255, 410 255, 410 255, 415 255, 420 255, 420 255, 420 255, 415 255, 415 254, 433 254, 438 254, 433 254, 438 254, 433 254, 438 254, 433 254, 438 254, 433 254, 438 254, 433 254, 438 254, 433 254, 438 254, 433 254, 438 254, 448 254, 443 254, 448 254, 443 254, 448 254, 443 254, 448 254, 443 254, 448 254, 443 254, 448 254, 443 254, 448 MAC212A6FP MAC212A8 MAC212A8FP MAC21810 MAC21810FP MAC2184 MAC2184FP MAC2186 MAC2186FP MAC2188 MAC2188FP MAC218A10 MAC218A10FP MAC218A4 MAC218A4FP MAC218A6 MAC218A6FP MAC218A8 MAC218A8FP MAC22310 MAC22310FP MAC2234 MAC2234FP MAC2236 MAC2236FP MAC2238 MAC2238FP MAC223A10 MAC223A10FP MAC223A4 MAC223A4FP MAC223A6 MAC223A6FP MAC223A8 MAC223A8FP MAC22410 MAC2244 MAC2246 MAC2248 MAC224A10 MAC224A4 MAC224A6 MAC224A8 MAC22810 MAC22810FP MAC2284 MAC2284FP MAC2286 MAC2286FP MAC2288 MAC2288FP MAC228A10 MAC228A10FP MAC228A4 MAC212A6FP MAC212A8 MAC212A8FP MAC210A10 MAC218A10FP MAC210A8 MAC218A6FP MAC210A8 MAC218A6FP MAC210A8 MAC218A10FP MAC210A10 MAC218A10FP MAC210A8 MAC218A6FP MAC210A8 MAC218A6FP MAC210A8 MAC218A10FP MAC223A10 MAC223A10FP MAC223A6 MAC223A6FP MAC223A6 MAC223A6FP MAC223A8 MAC223A8FP MAC223A10 MAC223A10FP MAC223A6 MAC223A6FP MAC223A6 MAC223A6FP MAC223A8 MAC223A8FP MAC224A10 MAC224A4 MAC224A6 MAC224A8 MAC224A10 MAC224A4 MAC224A6 MAC224A8 MAC228A10 MAC229A10FP MAC228A4 MAC229A8FP MAC228A6 MAC229A8FP MAC228A8 MAC229A8FP MAC228A10 MAC229A10FP MAC228A4 254, 443 254, 448 254, 443 254, 433 253, 453 254, 433 253, 453 254, 433 253, 453 254, 433 253, 453 254, 433 253, 453 254, 433 253, 453 254, 433 253, 453 254, 433 253, 453 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 465 255, 465 255, 465 255, 465 255, 465 255, 465 255, 465 255, 465 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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664

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number MAC228A4FP MAC228A6 MAC228A6FP MAC228A8 MAC228A8FP MAC22910 MAC22910FP MAC2294 MAC2294FP MAC2296 MAC2296FP MAC2298 MAC2298FP MAC229A10 MAC229A10FP MAC229A4 MAC229A4FP MAC229A6 MAC229A6FP MAC229A8FP MAC30308 MAC3104 MAC3106 MAC3108 MAC310A4 MAC310A6 MAC310A8 MAC32010 MAC32010FP MAC3204 MAC3204FP MAC3206 MAC3206FP MAC3208 MAC3208FP MAC320A10 MAC320A10FP MAC320A4 MAC320A4FP MAC320A6 MAC320A6FP MAC320A8 MAC320A8FP MAC32110 MAC3214 MAC3216 MAC3218 MAC4DCM1 MAC4DCMT4 MAC4DCN1 MAC4DCNT4 MAC4DHM1 MAC4DHMT4 MAC4DLM1 MAC229A8FP MAC228A6 MAC229A8FP MAC228A8 MAC229A8FP MAC228A10 MAC229A10FP MAC228A4 MAC229A8FP MAC228A6 MAC229A8FP MAC228A8 MAC229A8FP MAC228A10 MAC229A10FP MAC228A4 MAC229A8FP MAC228A6 MAC229A8FP MAC229A8FP MAC210A8 MAC12SM MAC12SM MAC12SM MAC12SM MAC12SM MAC12SM MAC223A10 MAC223A10FP MAC223A6 MAC223A6FP MAC223A6 MAC223A6FP MAC223A8 MAC223A8FP MAC223A10 MAC223A10FP MAC223A6 MAC223A6FP MAC223A6 MAC223A6FP MAC223A8 MAC320A8FP MAC223A10 MAC223A6 MAC223A6 MAC223A8 MAC4DCM1 MAC4DCMT4 MAC4DCN1 MAC4DCNT4 MAC4DHM1 MAC4DHMT4 MAC4DLM1 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 470 253, 474 253, 474 254, 433 254, 384 254, 384 254, 384 254, 384 254, 384 254, 384 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 461 255, 457 255, 478 255, 457 255, 457 255, 457 255, 457 252, 320 252, 320 252, 320 252, 320 252, 328 252, 328 252, 334 MAC4DLMT4 MAC4DSM1 MAC4DSMT4 MAC4DSN1 MAC4DSNT4 MAC4M MAC4N MAC4SM MAC4SN MAC8D MAC8M MAC8N MAC8SD MAC8SM MAC8SN MAC974 MAC976 MAC978 MAC97A4 MAC97A6 MAC97A8 MAC97B4 MAC97B6 MAC97B8 MAC997A6 MAC997A8 MAC997B6 MAC997B8 MAC9D MAC9M MAC9N MCR08BT1 MCR08DT1 MCR08MT1 MCR1003 MCR1004 MCR1006 MCR1008 MCR102 MCR103 MCR1062 MCR1063 MCR1064 MCR1066 MCR1068 MCR12D MCR12DCMT4 MCR12DCNT4 MCR12DSMT4 MCR12DSNT4 MCR12LD MCR12LM MCR12LN MCR12M MAC4DLMT4 MAC4DSM1 MAC4DSMT4 MAC4DSN1 MAC4DSNT4 MAC4M MAC4N MAC4SM MAC4SN MAC8D MAC8M MAC8N MAC8SD MAC8SM MAC8SN MAC97A4 MAC97A6 MAC978 MAC97A4 MAC97A6 MAC97A8 MAC997B6 MAC997B6 MAC997B8 MAC997A6 MAC997A8 MAC997B6 MAC997B8 MAC9D MAC9M MAC9N MCR08BT1 MCR08MT1 MCR08MT1 MCR1003 MCR1004 MCR1006 MCR1008 MCR1003 MCR1003 MCR1066 MCR1066 MCR1066 MCR1066 MCR1068 MCR12D MCR12DCMT4 MCR12DCNT4 MCR12DSMT4 MCR12DSNT4 MCR12LD MCR12LM MCR12LN MCR12M 252, 334 252, 340 252, 340 252, 340 252, 340 253, 348 253, 348 253, 353 253, 353 253, 358 253, 358 253, 358 253, 363 253, 363 253, 363 252, 425 252, 425 252, 425 252, 425 252, 425 252, 425 252, 483 252, 483 252, 483 252, 483 252, 483 252, 483 252, 483 253, 369 253, 369 253, 369 249, 491 249, 491 249, 491 249, 566 249, 566 249, 566 249, 566 249, 566 249, 566 249, 572 249, 572 249, 572 249, 572 249, 572 250, 518 250, 522 250, 522 250, 528 250, 528 250, 534 250, 534 250, 534 250, 518 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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665

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number MCR12N MCR16D MCR16M MCR16N MCR21810 MCR21810FP MCR2182 MCR2182FP MCR2183 MCR2184 MCR2184FP MCR2186 MCR2186FP MCR2188 MCR2188FP MCR222 MCR223 MCR224 MCR22510FP MCR2252FP MCR2254FP MCR2256FP MCR2258FP MCR226 MCR228 MCR25D MCR25M MCR25N MCR26410 MCR2644 MCR2646 MCR2648 MCR26510 MCR2652 MCR2654 MCR2656 MCR2658 MCR31010 MCR3102 MCR3103 MCR3104 MCR3106 MCR3108 MCR5062 MCR5063 MCR5064 MCR5066 MCR5068 MCR682 MCR692 MCR693 MCR703A MCR703A1 MCR703ARL MCR12N MCR16N MCR16N MCR16N MCR12N MCR21810FP MCR2182 MCR2186FP MCR2184 MCR2184 MCR2186FP MCR2186 MCR2186FP MCR12M MCR21810FP MCR226 MCR226 MCR226 MCR22510FP MCR2258FP MCR2258FP MCR2258FP MCR2258FP MCR226 MCR228 MCR25D MCR25M MCR25N MCR26510 MCR2644 MCR2646 MCR2648 MCR26510 MCR2654 MCR2654 MCR2656 MCR2658 MCR728 MCR12DSMT4 MCR12DSMT4 MCR12DSMT4 MCR12DSMT4 MCR12DSMT4 MCR1066 MCR1066 MCR1066 MCR1066 MCR1068 MCR682 MCR692 MCR693 MCR703AT4 MCR703AT4 MCR703AT4 250, 518 251, 538 251, 538 251, 538 250, 518 250, 579 250, 575 250, 579 250, 575 250, 575 250, 579 250, 575 250, 579 250, 518 250, 579 249, 543 249, 543 249, 543 251, 584 251, 584 251, 584 251, 584 251, 584 249, 543 249, 543 251, 550 251, 550 251, 550 251, 593 251, 589 251, 589 251, 589 251, 593 251, 593 251, 593 251, 593 251, 593 250, 563 250, 528 250, 528 250, 528 250, 528 250, 528 249, 572 249, 572 249, 572 249, 572 249, 572 250, 555 251, 559 251, 559 249, 597 249, 597 249, 597 MCR703AT4 MCR704A1 MCR704ARL MCR704AT4 MCR706A MCR706A1 MCR706ARL MCR706AT4 MCR708A MCR708A1 MCR708AT4 MCR716T4 MCR718RL MCR718T4 MCR722 MCR723 MCR724 MCR726 MCR728 MCR8D MCR8DCMT4 MCR8DCNT4 MCR8DSMT4 MCR8DSNT4 MCR8M MCR8N MCR8SD MCR8SM MCR8SN MKP1V120 MKP1V120RL MKP1V130 MKP1V130RL MKP1V160 MKP1V160RL MKP1V240 MKP1V240RL MKP3V110 MKP3V120 MKP3V120RL MKP3V130 MKP3V240 MKP3V240RL MKP9V160RL MMT05B230T3 MMT05B260T3 MMT05B310T3 MMT10B230T3 MMT10B260T3 MMT10B310T3 P0102AN P0102BN P0102CN P0102DN MCR703AT4 MCR706AT4 MCR704AT4 MCR704AT4 MCR706AT4 MCR708AT4 MCR706AT4 MCR706AT4 MCR708AT4 MCR708AT4 MCR708AT4 MCR716T4 MCR718T4 MCR718T4 MCR723 MCR723 MCR726 MCR726 MCR728 MCR8M MCR8DCMT4 MCR8DCNT4 MCR8DSMT4 MCR8DSNT4 MCR8M MCR8N MCR8SD MCR8SM MCR8SN MKP1V120RL MKP1V120RL MKP1V130RL MKP1V130RL MKP1V160 MKP1V160RL MKP1V240 MKP1V240RL MKP3V120RL MKP3V120 MKP3V120RL MKP3V120RL MKP3V240 MKP3V240RL MKP1V160RL MMT05B230T3 MMT05B260T3 MMT05B310T3 MMT10B230T3 MMT10B260T3 MMT10B310T3 MCR08MT1 MCR08MT1 MCR08BT1 MCR08BT1 249, 597 249, 597 249, 597 249, 597 249, 597 249, 597 249, 597 249, 597 249, 597 249, 597 249, 597 249, 602 249, 602 249, 602 250, 563 250, 563 250, 563 250, 563 250, 563 250, 510 250, 499 250, 499 250, 504 250, 504 250, 510 250, 510 250, 514 250, 514 250, 514 256, 607 256, 607 256, 607 256, 607 256, 607 256, 607 256, 607 256, 607 256, 611 256, 611 256, 611 256, 611 256, 611 256, 611 256, 607 256, 615 256, 615 256, 615 256, 621 256, 621 256, 621 249, 491 249, 491 249, 491 249, 491 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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666

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number P102AA P102BA P102CA P102DA P2300SA P2300SB P2300SC P2600SA P2600SB P2600SC P3100SA P3100SB P3100SC Q2004F41 Q2006F41 Q2006L4 Q2006R4 Q2008F41 Q2008L4 Q2008R4 Q2010F51 Q2010L5 Q2010R5 Q20110F51 Q2015L5 Q2015R5 Q201E3 Q201E4 Q2025R5 Q2X8E3 Q2X8E4 Q4004F41 Q4006F41 Q4006L4 Q4006R4 Q4008F41 Q4008L4 Q4008R4 Q4010F51 Q4010L5 Q4010R5 Q40110F51 Q4015L5 Q4015R5 Q401E3 Q401E4 Q4925R5 Q4X8E3 Q4X8E4 Q5004F41 Q5006F41 Q5006L4 Q5006R4 Q5008F41 MCR1003 MCR1004 MCR1006 MCR1006 MMT05B230T3 MMT10B230T3 MMT10B230T3 MMT05B260T3 MMT10B260T3 MMT10B260T3 MMT05B310T3 MMT10B310T3 MMT10B310T3 MAC4SM MAC228A4 MAC218A10FP MAC228A4 MAC228A4 MAC218A10FP MAC228A4 MAC210A8 MAC210A8FP MAC210A8 MAC15A8FP MAC15A6FP MAC158 MAC978 MAC978 MAC223A6 MAC978 MAC978 MAC4SM MAC228A6 MAC218A10FP MAC228A6 MAC228A6 MAC218A10FP MAC228A6 MAC210A8 MAC210A8FP MAC210A8 MAC15A8FP MAC15A6FP MAC158 MAC978 MAC978 MAC223A6 MAC978 MAC978 MAC4SM MAC228A8 MAC218A10FP MAC228A8 MAC228A8 249, 566 249, 566 249, 566 249, 566 256, 615 256, 621 256, 621 256, 615 256, 621 256, 621 256, 615 256, 621 256, 621 253, 353 253, 470 253, 453 253, 470 253, 470 253, 453 253, 470 254, 433 254, 438 254, 433 255, 394 255, 394 255, 389 252, 425 252, 425 255, 457 252, 425 252, 425 253, 353 253, 470 253, 453 253, 470 253, 470 253, 453 253, 470 254, 433 254, 438 254, 433 255, 394 255, 394 255, 389 252, 425 252, 425 255, 457 252, 425 252, 425 253, 353 253, 470 253, 453 253, 470 253, 470 Q5008L4 Q5008R4 Q5010F51 Q5010L5 Q5010R5 Q5015R5 Q501E3 Q501E4 Q5025R5 Q5X8E3 Q5X8E4 Q6004F41 Q6006F51 Q6006L5 Q6006R5 Q6008F51 Q6008L5 Q6008R5 Q6010F51 Q6010L5 Q6010R5 Q6015R5 Q601E3 Q601E4 Q6025R5 Q6X8E3 Q6X8E4 Q7006L5 Q7006R5 Q7008L5 Q7008R5 Q7010L5 Q7010R5 Q7015R5 Q7025R5 Q8006L5 Q8006R5 Q8008L5 Q8008R5 Q8010L5 Q8010R5 Q8015R5 Q8025R5 S0402BH S0402DH S0402MH S0402NH S0506F1 S0506FS21 S0506FS31 S0506L S0508F1 S0508FS21 S0508FS31 MAC218A10FP MAC228A8 MAC15A10FP MAC210A8FP MAC210A8 MAC158 MAC978 MAC978 MAC223A8 MAC978 MAC978 MAC4SM MAC9M MAC218A10FP MAC9M MAC9M MAC218A10FP MAC9M MAC15A10FP MAC210A8FP MAC210A8 MAC158 MAC978 MAC978 MAC223A8 MAC978 MAC978 MAC218A10FP MAC9N MAC218A10FP MAC9N MAC210A10FP MAC210A10 MAC1510 MAC223A10 MAC218A10FP MAC9N MAC218A10FP MAC9N MAC210A10FP MAC210A10 MAC1510 MAC223A10 MCR8SD MCR8SD MCR8SM MCR8SN MCR8M MCR8SD MCR8SD MCR2186FP MCR12D MCR8SD MCR8SD 253, 453 253, 470 255, 394 254, 438 254, 433 255, 389 252, 425 252, 425 255, 457 252, 425 252, 425 253, 353 253, 369 253, 453 253, 369 253, 369 253, 453 253, 369 255, 394 254, 438 254, 433 255, 389 252, 425 252, 425 255, 457 252, 425 252, 425 253, 453 253, 369 253, 453 253, 369 254, 438 254, 433 255, 389 255, 457 253, 453 253, 369 253, 453 253, 369 254, 438 254, 433 255, 389 255, 457 250, 514 250, 514 250, 514 250, 514 250, 510 250, 514 250, 514 250, 579 250, 518 250, 514 250, 514 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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667

Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number S0508L S0508R S0510F1 S0510FS21 S0510FS31 S0510L S0510R S0512R S0515L S0516R S0520L S0525L S0525R S0540R S0555R S0602BH S0602DH S0602MH S0602NH S0802BH S0802DH S0802MH S0802NH S1006F1 S1006FS21 S1006FS31 S1006L S1008F1 S1008FS21 S1008FS31 S1008L S1008R S1010F1 S1010FS21 S1010FS31 S1010L S1010R S1012R S1015L S1016R S1020L S1025L S1025R S1040R S1055R S2006F1 S2006FS21 S2006FS31 S2006L S2008F1 S2008FS21 S2008FS31 S2008L S2008R MCR2186FP MCR12D MCR12LD MCR723 MCR723 MCR2258FP MCR12LD MCR12LD MCR2258FP 2N6400 MCR2258FP MCR2258FP MCR25D MCR2644 MCR2654 MCR8SD MCR8SD MCR8SM MCR8SN MCR8SD MCR8SD MCR8SM MCR8SN MCR8M MCR8SD MCR8SD MCR2186FP MCR12D MCR8SD MCR8SD MCR2186FP MCR12D MCR12LD MCR726 MCR726 MCR2258FP MCR12LD MCR12LD MCR2258FP 2N6401 MCR2258FP MCR2258FP MCR25D MCR2644 MCR2654 MCR8M MCR8SD MCR8SD MCR2186FP MCR12D MCR8SD MCR8SD MCR2186FP MCR12D 250, 579 250, 518 250, 534 250, 563 250, 563 251, 584 250, 534 250, 534 251, 584 251, 293 251, 584 251, 584 251, 550 251, 589 251, 593 250, 514 250, 514 250, 514 250, 514 250, 514 250, 514 250, 514 250, 514 250, 510 250, 514 250, 514 250, 579 250, 518 250, 514 250, 514 250, 579 250, 518 250, 534 250, 563 250, 563 251, 584 250, 534 250, 534 251, 584 251, 293 251, 584 251, 584 251, 550 251, 589 251, 593 250, 510 250, 514 250, 514 250, 579 250, 518 250, 514 250, 514 250, 579 250, 518 S2010F1 S2010FS21 S2010FS31 S2010L S2010R S2012R S2015L S2016R S2020L S2025L S2025R S2040R S2055R S2800A S2800B S2800D S2800F S2800M S2800N S4006F1 S4006FS21 S4006FS31 S4006L S4008F1 S4008FS21 S4008FS31 S4008L S4008R S4010F1 S4010FS21 S4010FS31 S4010L S4010R S4012R S40156R S4015L S4020L S4025L S4025R S4040R S4055R S6006F1 S6006FS21 S6006FS31 S6006L S6008F1 S6008FS21 S6008FS31 S6008L S6008R S6010F1 S6010FS21 S6010FS31 S6010L MCR12LD MCR726 MCR726 MCR2258FP MCR12LD MCR12LD MCR2258FP 2N6402 MCR2258FP MCR2258FP MCR25D MCR2644 MCR2654 MCR12M MCR12M MCR12M MCR12M MCR12M MCR12N MCR8M MCR8SD MCR8SD MCR2186FP MCR12D MCR8SD MCR8SD MCR2186FP MCR12D MCR12LD MCR726 MCR726 MCR2258FP MCR12LD MCR12LD 2N6403 MCR2258FP MCR2258FP MCR2258FP MCR25D MCR2646 MCR2654 MCR8M MCR8SM MCR8SM MCR21810FP MCR12M MCR8SM MCR8SM MCR21810FP MCR12M MCR12LM MCR728 MCR728 MCR2258FP 250, 534 250, 563 250, 563 251, 584 250, 534 250, 534 251, 584 251, 293 251, 584 251, 584 251, 550 251, 589 251, 593 250, 518 250, 518 250, 518 250, 518 250, 518 250, 518 250, 510 250, 514 250, 514 250, 579 250, 518 250, 514 250, 514 250, 579 250, 518 250, 534 250, 563 250, 563 251, 584 250, 534 250, 534 251, 293 251, 584 251, 584 251, 584 251, 550 251, 589 251, 593 250, 510 250, 514 250, 514 250, 579 250, 518 250, 514 250, 514 250, 579 250, 518 250, 534 250, 563 250, 563 251, 584 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number S6010R S6012R S6015L S6016R S6020L S6025L S6025R S6040R S6055R S8006L S8008L S8008R S8010L S8010R S8012R S8015L S8016R S8020L S8025L S8025R S8055R SC141D SC146D SF10G41A SF10J41A SF5G41A SF5G42 SF5GZ47 SF5J41A SF5J42 SF5JZ47 SF8G41A SF8GZ47 SF8J41A SF8JZ47 SFOR5J43 SFORG43 SM12G45 SM12GZ47 SM12J45 SM12JZ47 SM16G45 SM16GZ47 SM16J45 SM16JZ47 SM1G43 SM1J43 SM3J45 SM3JZ47 SM6G45 SM6GZ47A SM6J45 SM6JZ47A SM8G45 MCR12LM MCR12LM MCR2258FP 2N6404 MCR2258FP MCR2258FP MCR25M MCR2648 MCR2658 MCR21810FP MCR21810FP MCR12N MCR22510FP MCR12LN MCR12LN MCR22510FP 2N6405 MCR22510FP MCR22510FP MCR25N MCR26510 MAC210A8 MAC15A6 2N6403 2N6404 MCR8SD MCR8SD MCR2186FP MCR8SM MCR8SM MCR21810FP MCR726 MCR726 MCR728 MCR728 MCR1008 MCR1006 MAC12D MAC212A6FP MAC12M MAC212A8FP MAC16CD MAC16CD MAC16CM MAC16CM MAC997A6 MAC997A8 MAC4M MAC4M MAC8D MAC229A8FP MAC8M MAC229A8FP MAC8D 250, 534 250, 534 251, 584 251, 293 251, 584 251, 584 251, 550 251, 589 251, 593 250, 579 250, 579 250, 518 251, 584 250, 534 250, 534 251, 584 251, 293 251, 584 251, 584 251, 550 251, 593 254, 433 255, 389 251, 293 251, 293 250, 514 250, 514 250, 579 250, 514 250, 514 250, 579 250, 563 250, 563 250, 563 250, 563 249, 566 249, 566 254, 374 254, 443 254, 374 254, 443 255, 410 255, 410 255, 410 255, 410 252, 483 252, 483 253, 348 253, 348 253, 358 253, 474 253, 358 253, 474 253, 358 SM8GZ47 SM8J45 SM8JZ47 SM8LZ47 SMO8G43 SMP100140 SMP100200 SMP100230 SMP100270 SMTBJ170A SMTBJ170B SMTBJ200A SMTBJ200B SMTPA180 SMTPA200 SMTPA220 SMTPA270 T106A1 T106B1 T106C1 T106D1 T106E1 T106F1 T106M1 T107A1 T107B1 T107C1 T107D1 T107E1 T107F1 T107M1 T2322B T2322D T2322M T2323B T2323D T2323M T2500B T2500BFP T2500D T2500DFP T2500M T2500MFP T2500N T2500NFP T2800B T2800D T2800M T405400B T405400T T405400W T405600B T405600T T405600W MAC8D MAC8M MAC8M MAC229A10FP MAC997B6 MMT10B230T3 MMT10B260T3 MMT10B260T3 MMT10B310T3 MMT05B230T3 MMT10B230T3 MMT05B260T3 MMT10B260T3 MMT05B230T3 MMT05B260T3 MMT05B260T3 MMT05B310T3 C106B C106B C106D C106D C106M C106B C106M C106B C106B C106D C106D C106M C106B C106M T2322B 2N6073A 2N6075A T2322B 2N6073A 2N6075A T2500D MAC229A8FP T2500D MAC229A8FP MAC8M MAC229A8FP MAC8N MAC229A10FP T2800D T2800D 2N6344 MAC4DLMT4 MAC8SD MAC229A8FP MAC4DLMT4 MAC8SM MAC229A8FP 253, 358 253, 358 253, 358 253, 474 252, 483 256, 621 256, 621 256, 621 256, 621 256, 615 256, 621 256, 615 256, 621 256, 615 256, 615 256, 615 256, 615 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 249, 303 252, 627 252, 272 252, 272 252, 627 252, 272 252, 272 253, 630 253, 474 253, 630 253, 474 253, 358 253, 474 253, 358 253, 474 253, 633 253, 633 253, 278 252, 334 253, 363 253, 474 252, 334 253, 363 253, 474 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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Industry Part Number ON Semiconductor Nearest Replacement Page Number Industry Part Number ON Semiconductor Nearest Replacement Page Number T410400B T410400T T410400W T410600B T410600T T410600W T410700B T410700T T410700W T410800B T410800T T410800W T435400B T435400T T435400W T435600B T435600T T435600W T435700B T435700T T435700W T435800B T435800T T435800W TCR222 TCR223 TCR224 TCR226 TCR228 TIC116D TIC116M TIC116N TIC126D TIC126M TIC126N TIC236N TIC246D TIC246M TIC246N TN1215600B TN1215600G TN1215800G TN41A TN41B TP30100 TP30120 TP30130 TP30180 TP30200 TS1220600B TS420400B TS420400T TS420600B TS420600T MAC4DSMT4 MAC4SM MAC229A8FP MAC4DSMT4 MAC4SM MAC229A8FP MAC4DSNT4 MAC4SN MAC229A10FP MAC4DSNT4 MAC4SN MAC229A10FP MAC4DCMT4 MAC8SD MAC229A8FP MAC4DCMT4 MAC8SM MAC229A8FP MAC4DCNT4 MAC8SN MAC229A10FP MAC4DCNT4 MAC8SN MAC229A10FP MCR226 MCR226 MCR226 MCR226 MCR228 MCR8SD MCR8SM MCR8SN MCR12D MCR12M MCR12N MAC12HCN MAC16HCD MAC16HCM MAC16HCN MCR12DCMT4 MCR8DCMT4 MCR8DCNT4 2N6027 2N6028 MKP1V120RL MKP1V130RL MKP1V160RL MKP1V240RL MKP1V240RL MCR12DSMT4 MCR706AT4 MCR8SD MCR706AT4 MCR8SM 252, 340 253, 353 253, 474 252, 340 253, 353 253, 474 252, 340 253, 353 253, 474 252, 340 253, 353 253, 474 252, 320 253, 363 253, 474 252, 320 253, 363 253, 474 252, 320 253, 363 253, 474 252, 320 253, 363 253, 474 249, 543 249, 543 249, 543 249, 543 249, 543 250, 514 250, 514 250, 514 250, 518 250, 518 250, 518 254, 379 255, 420 255, 420 255, 420 250, 522 250, 499 250, 499 256, 265 256, 265 256, 607 256, 607 256, 607 256, 607 256, 607 250, 528 249, 597 250, 514 249, 597 250, 514 TS420700T TS820400B TS820400T TS820600B TS820600T TS820700B TS820700T TSMBJ0516C TSMBJ0518C TSMBJ0522C TSMBJ0524C TSMBJ0527C TSMBJ1016C TSMBJ1018C TSMBJ1022C TSMBJ1024C TSMBJ1027C X00602MA 1AA2 X00602MA 2AL2 X0202BA X0202DA X0202MA X0203BA X0203DA X0203MA Z00607DA Z00607MA Z0103DA Z0103MA Z0107DA Z0107MA Z0109DA Z0109DN Z0109MA Z0109MN Z0110DN Z0110MN MCR8SN MCR8DSMT4 MCR8SD MCR8DSMT4 MCR8SM MCR8DSNT4 MCR8SN MMT05B230T3 MMT05B230T3 MMT05B260T3 MMT05B310T3 MMT05B310T3 MMT10B230T3 MMT10B230T3 MMT10B260T3 MMT10B310T3 MMT10B310T3 MCR1008 MCR1008 MCR226 MCR226 MCR228 MCR226 MCR226 MCR228 MAC997A8 MAC997A6 MAC997B6 MAC997B8 MAC997A6 MAC997A8 MAC997A6 MAC08MT1 MAC997A8 MAC08MT1 MAC08MT1 MAC08MT1 250, 514 250, 504 250, 514 250, 504 250, 514 250, 504 250, 514 256, 615 256, 615 256, 615 256, 615 256, 615 256, 621 256, 621 256, 621 256, 621 256, 621 249, 566 249, 566 249, 543 249, 543 249, 543 249, 543 249, 543 249, 543 252, 483 252, 483 252, 483 252, 483 252, 483 252, 483 252, 483 252, 311 252, 483 252, 311 252, 311 252, 311 Bold items are a form, fit, and function replacement for the industry part number, although some very minor differences may exist.
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ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS

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DL137/D Rev.

Thyristor Device Data

Thyristor Device Data

DL137/D Rev. 7, May2000

SCILLC, 2000 Previous Edition 1995 All Rights Reserved

PUBLICATION ORDERING INFORMATION

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ON SEMICONDUCTOR DEVICE CLASSIFICATIONS

ABOUT THIS REVISION 7 . . .

WHATS DIFFERENT IN THE REV. 7 DATA BOOK?

THYRISTOR PART NUMBER PREFIX*

Silicon Controlled Rectifiers (SCR)

*2N Devices JEDEC Registered Series

Chapter 1: Theory and Applications

Chapter 2: Selector Guide

Chapter 3: Data Sheets

Table of Contents (continued)

Chapter 3: Data Sheets (continued)

Chapter 5: Outline Dimensions and Leadform Options

Chapter 6: Index and Cross Reference

CHAPTER 1 Theory and Applications

SECTION 1 SYMBOLS AND TERMINOLOGY

Thyristor Surge Protective Devices & Sidac

Programmable Unijunction Transistor (PUT)

Terminology CRITICAL RATE OF RISE OF ONSTATE CURRENT

RATE OF CHANGE OF COMMUTATING CURRENT (Triacs)

CRITICAL RATE OF RISE OF OFFSTATE VOLTAGE

PEAK REPETITIVE BLOCKING CURRENT

PEAK REPETITIVE REVERSE BLOCKING CURRENT

AVERAGE ONSTATE CURRENT (SCR)

ONSTATE RMS CURRENT

PEAK NONREPETITIVE SURGE CURRENT

CIRCUIT FUSING CONSIDERATIONS (Current squared time)

FORWARD AVERAGE GATE POWER (SCR) AVERAGE GATE POWER (Triac)

FORWARD PEAK GATE POWER (SCR) PEAK GATE POWER (Triac)

OPERATING JUNCTION TEMPERATURE

TURNOFF TIME (SCR)

PEAK REPETITIVE OFFSTATE FORWARD VOLTAGE

GATE NONTRIGGER VOLTAGE

FORWARD PEAK GATE VOLTAGE (SCR) PEAK GATE VOLTAGE (Triac)

GATE TRIGGER VOLTAGE

RMS ISOLATION VOLTAGE

PEAK REVERSE GATE BLOCKING VOLTAGE (SCR)

PEAK REPETITIVE REVERSE OFFSTATE VOLTAGE

TRANSIENT THERMAL IMPEDANCE, JUNCTIONTOAMBIENT TRANSIENT THERMAL IMPEDANCE, JUNCTIONTOCASE

Thyristor Surge Protector Devices (TSPD) and Sidac Terminology*

Terminology BREAKOVER CURRENT

OFFSTATE CURRENT (TSPD)

PULSE SURGE SHORT CIRCUIT CURRENT NONREPETITIVE (TSPD)

INSTANTANEOUS PEAK POWER DISSIPATION (TSPD)

SWITCHING RESISTANCE (Sidac)

BREAKDOWN VOLTAGE (TSPD)

OFFSTATE VOLTAGE (TSPD)

ONSTATE VOLTAGE (TSPD)

SECTION 2 THEORY OF THYRISTOR OPERATION

Edited and Updated

{ Not generally available.

V Ig4 Ig3 Ig2 Ig1 = 0

Figure 2.2. Thyristor Characteristics Illustrating Breakover as a Function of Gate Current

a2 IG ) ICS1 ) ICS2 + A 1a a