MIC50395/50396/50397

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MIC50395/50396/50397
Six Decade Counter / Display Decoder Not Recommended for New Designs

General Description
The MIC50395 is an ion-implanted, P-channel MOS sixdecade synchronous up/down-counter/display driver with compare-register and storage-latches. The counter as well as the register can be loaded digit-by-digit with BCD data. The counter has an asynchronous-clear function. Scanning is controlled by the scan oscillator input which is self-oscillating or can be driven by an external signal. The six-decade register is constantly compared to the state of the six-decade counter and when both the register and the counter have the same content, an EQUAL signal is generated. The contents of the counter can be transferred into the 6-digit latch which is then multiplexed from MSD to LSD in BCD and 7-segment format to the output. The sevensegment decoder incorporates a leading-zero blanking circuit which can be disabled by an external signal. This device is intended to interface directly with the standard CMOS logic families. The MIC50396 and MIC50397 operate identically to the MIC50395 except that two digits in each were reprogrammed to provide divide by six circuitry instead of divide by ten. The MIC50396 is well suited for industrial timer applications while the MIC50397 is best suited for stop watch or real time computer clock applications.

Features
Single power supply Schmitt-Trigger on the count-input Drives common anode or cathode displays (CA with buffer) Six decades of synchronous up/down counting Look-ahead carry or borrow Loadable counter Loadable compare-register with comparator output Multiplexed BCD and seven-segment outputs Internal scan oscillator Direct LED segment drive Interfaces directly with CMOS logic Leading zero blanking MIC50396 programmed to count time: 99 hrs. 59 min. 59 sec. MIC50397 programmed to count time: 59 hrs. 59 min. 99/100 min.

Ordering Information
Part Number MIC50395CN MIC50396CN MIC50397CN Temp. Range 0C to 70C 0C to 70C 0C to 70C Package 40-pin Plastic DIP 40-pin Plastic DIP 40-pin Plastic DIP

Pin Connection
V SS SET LZB a b SEGMENTS c d e f 1 2 3 4 5 6 7 8 9 MIC50395CN MIC50396CN MIC50397CN 40 39 38 37 36 35 34 33 32 31 30 UP/DOWN ZERO CARRY COUNT INHIBIT COUNT RA RB RC RD LOAD COUNTER LOAD REGISTER REGISTER BCD IN

Segment Identification
a f e d g b c

g 10 A 11 BCD OUT B 12 C 13 D 14 STORE 15 C D 16 COUNTER BCD C B 18 IN C A 19 CLEAR 20 C C 17

29 D 6 MSD 28 D 5 27 D 4 DIGIT 26 D 3 STROBES 25 D 2 24 D 1 LSD 23 22 21 EQUAL V DD SCAN

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following a negative transition of Load Counter or Load Register. The carry output goes high with the leading edge of the count input at the count of 000000 when counting up or at 999999* when counting down and goes low with the negative going edge of the same count input. A count frequency of 1 MHz can be achieved if the equal output, zero output and carry output are not used. These outputs do not respond at this frequency due to their output delay illustrated on the timing diagram.

Operations:
Six Decade Counter, Latch
The six decade counter is synchronously incremented or decremented on the positive edge of the count input signal. A Schmitt trigger on this input provides hysteresis for protection against both a noisy environment and double triggering due to a slow rising edge at the count input. The count inhibit can be changed in coincidence with the positive transition of the count input; the count input is inhibited when the count inhibit is high. The counter will increment when up/down input is high (VSS) and will decrement when up/down input is low. The up/down input can be changed 0.75 s prior to the positive transition of the count input. The clear input is asynchronous and will reset all decades to zero when brought high but does not affect the six digit latch or the scan counter. As long as store input is low, data is continuously transferred from the counter to the display. Data in the counter will be latched and displayed when store input is high. Store can be changed in coincidence with the positive transition of the count input. The counter is loaded digit by digit corresponding to the digit strobe outputs. BCD thumb wheel switches with four diodes per decade connected between the digit strobe outputs and the BCD inputs is one method to supply BCD data for loading the counter decades. The load counter pulse must be at VSS 2 s prior to the positive transition of the digit strobe of the digit to be loaded. The load counter pulse may be removed after the positive transition of the digit strobe since the chip internally latches this signal. The BCD data to be loaded must be valid through the negative transition of the digit strobe.

Six Decade Compare Register

The register is loaded identically to the load counter paragraph described previously. The register may be loaded independently of the counter, however, the clear input will not remove the register contents. Contents of the register are not displayed by the BCD or seven segment outputs.

BCD Seven Segment Outputs

BCD or seven segment outputs are available. Digit strobes are decoded internally by a divide by six Johnson counter. This counter scans from MSD to LSD. By bringing the SET input low, this counter will be forced to the MSD decade count. During this time the segment outputs are blanked to protect against display burn out. BCD outputs are valid for MSD when SET is low. Applying VSS to SET allows normal scan to resume. Digit 6 output is active (VSS) until the next scan clock pulse brings up digit 5 output. The segment outputs and digit strobes are blanked during the interdigit blanking time. Leading zero blanking affects only the segment outputs. This option is disabled by bringing the LZB input high. Typically the interdigit blanking time is 5 to 25 s when using the internal scan oscillator. BCD output data changes at the beginning of the interdigit blanking time. Therefore the BCD output data is valid when the positive transition of a digit output occurs.

Inputs, Outputs
The seven segment outputs are open drain capable of sourcing 10mA average current per segment over one digit cycle. Segments are on when at VSS. The Carry, Equal, Zero, BCD and digit strobe outputs are push pull and are on when at VSS. All inputs except Counter BCD, Register BCD, and SCAN inputs are high impedance CMOS compatible. Three basic outputs originate from the counter: zero output, equal output, and carry output. Each output goes high on the positive (VSS) going edge of the count input under the following conditions: Zero output goes high for one count period when all decades contain zero. During a load counter operation the zero output is inhibited. Equal output goes high for one count period when the contents of the counter and compare register are equal. The equal output is inhibited by a load counter or load register operation, which lasts until the next interdigit blanking period
*Carry occurs at 99:59:59 for the 50396 and 59:59:99 for the 50397

Scan Oscillator
The MIC50395 has an internal scan oscillator. The frequency of the scan oscillator is determined by an external capacitor between VSS or VDD and scan input. The wave form present on the scan oscillator input is triangular in the self oscillate mode. An external oscillator may also be used to drive the scan input. In either case, external capacitors of 150pF each will be required from VSS to Counter BCD inputs and register BCD inputs. This will allow asynchronous loading of the BCD inputs. In the internal drive mode the interdigit blanking time will be the sum of the negative dwell period of the external oscillator and the normal self oscillate blanking time. (525 s). Display brightness can be controlled by the duty cycle of the external scan oscillator.

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If external capacitors on the BCD inputs are undesirable, it will be necessary to synchronize the negative going edge of the load register and/or load counter command to coincide with the positive going edge of the scan input signal. Also the VSS range should be limited from 10.8 to 13.2 Volts. Typically, the scan oscillator will oscillate at the following frequencies with these nominal capacitor values from VSS to scan input. CIN 820 pF 470 pF 120 pF Min 1.4 kHz 2.0 kHz 7.0 kHz Max 4.8 kHz 6.8 kHz 20 kHz

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Functional Diagram

SN75492A

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Absolute Maximum Ratings

Voltage on Any Terminal Relative to VSS +0.3V to 20V Operating Temperature Range (Ambient) 0C to +70C Storage Temperature Range (Ambient) 40C to +100C

Maximum Operating Conditions

Symbol TA VSS ISS BV PD Parameter Operating Temperature Supply voltage (VDD = 0V) Supply Current Break Down Voltage (Segment only @ 10 A) Power Dissipation Min 0 10 Max 70 15 35 VSS 26 670 Units C V mA V mW 3 1 2 Notes

Electrical Characteristics
(VDD = 0V, VSS = +10.0V to +15.0, 0C TA 70C)

Static Operating Conditions

Symbol VIL VIH VOL VOH IOH Parameter Input Low Voltage, 0 Input High Voltage, 1 Output Voltage 0 @ 30 A Output Voltage 1 @ 1.5 mA Output Current 1 Digit strobes Segment outputs Scan Input Pullup Current @ 0 V Scan Input Pulldown Current @ 15 V SET Input Pullup Current @ 0V 2 5 0.8 VSS 3.0 10.0 5.5 40 60 Min VDD VSS 1 Max 0.2 VSS VSS 0.2 VSS Units V V V V mA mA mA A A 4 5 5 6 7 Notes

ISCAN ISCAN ISET

Note 1: With 150 pF capacitor to VSS from counter BCD and register BCD inputs. Note 2: ISS with inputs and outputs open at 0C. 33 mA at 25C and 28 mA at 70C. This does not include segment current. Total power per segment must be limited not to exceed power dissipation of package. (JA = 100C/Watt) Note 3: All outputs loaded. Note 4: MIN VIH from RA RB RC RD CA CB CC CD inputs is VSS 2.5 V. Those inputs have internal pulldown resistors to VDD. Note 5: This applied to the push pull CMOS compatible outputs. Does not include digit strobes or segment outputs. Note 6: For VOUT = VSS 2.0 Volts. Average value over one digit cycle. Note 7: For VOUT = VSS 3.0 Volts. Average value over one digit cycle.

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Timing
1 COUNT 2 3 4 5 6 7 8 9 10 11

t UDS
UP/DOWN

t UDS t CIS t CIS

COUNT INHIBIT

t SS
STORE

t PCW
CLEAR

t SPW

t CS
COUNT

t OA
ZERO

t OH t CH t EH

t CA
CARRY

t EA
EQUAL

SCAN

tL
LOAD COUNTER

tL
LOAD REGISTER

Loading Counter, Register (1 Digit)

t LS
LOAD COUNTER OR REGISTER

t DV
BCD DATA INPUT

tLS 2.0 s min NOTE: REF. TO POSITIVE TRANSITION OF DIGIT OUTPUT tDV 2.0 s min NOTE: REF. TO NEGATIVE EDGE OF DIGIT OUTPUT

DIGIT OUTPUT 6

DIGIT OUTPUT 5 ETC COUNT INPUT, CARRY EQUAL, ZERO OUTPUT INHIBITED DURING THIS TIME COUNT INPUT

t OA
ZERO OUTPUT

t OH
NOTE: The inhibit function of the zero or equal outputs does not end when the Load Counter input goes to a 0 unless that transition occurs during interdigit blanking period at least 2.0 s prior to a positive transition of a digit output. This same timing restriction holds for Equal and Load Register.

t CA t CH
CARRY OUTPUT

t EA
EQUAL OUTPUT

t EH

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Dynamic Operating Conditions

Symbol fCI fSI tCPW tSPW tSS tCIS tUDS tCPW tCS tOA tOH tCA tCH tEA tEH tL Parameter Count Input Frequency Scan Input Frequency Count Pulse Width Store Pulse Width Store Setup Time Count Inhibit Setup Time Up/Down Setup Time Clear Pulse Width Clear Setup Time Zero Access Time Zero Hold Time Carry Access Time Carry Hold Time Equal Access Time Equal Hold Time Load Time 0.9 2.0 1.5 1/6 fSI Min 0 0 400 2.0 0 0 0.75 2.0 0.5 3.0 1.5 1.5 Max 1.00 20 Units MHz kHz ns s s s s s s s s s s s s 11 11 11 11 11 11 11 11 12 11 11 10 Notes 8,9

Note 8: Measured at 50% duty cycle. Note 9: If carry, equal, or zero outputs are used, the count frequency will be limited by their respective output times. Note 10: The count pulse width must be greater than the carry access time when using the carry output. Note 11: The positive edge of the count input is the t = 0 reference. Note 12: Measured from negative edge of count input.

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