Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 97 views

    Aldec Active-HDL Simulation

    Uploaded by

    Sushil Kumar
    This document provides a tutorial on using Aldec Active-HDL software to simulate VHDL designs. It discusses compiling VHDL files to create simulation models, debugging compilation errors, and performing functional simulation by running test benches to verify circuit behavior. Waveforms of desired signals can be viewed and simulation can be run continuously, until a specified time, or for a set duration. The tutorial helps students develop and simulate their VHDL designs using the integrated simulation environment.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Aldec Active-HDL Simulation

    Uploaded by

    Sushil Kumar
    97 views13 pages
    This document provides a tutorial on using Aldec Active-HDL software to simulate VHDL designs. It discusses compiling VHDL files to create simulation models, debugging compilation errors, and performing functional simulation by running test benches to verify circuit behavior. Waveforms of desired signals can be viewed and simulation can be run continuously, until a specified time, or for a set duration. The tutorial helps students develop and simulate their VHDL designs using the integrated simulation environment.

    Original Description:

    Aldec Active-HDL Simulation

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document provides a tutorial on using Aldec Active-HDL software to simulate VHDL designs. It discusses compiling VHDL files to create simulation models, debugging compilation errors, and performing functional simulation by running test benches to verify circuit behavior. Waveforms of desired signals can be viewed and simulation can be run continuously, until a specified time, or for a set duration. The tutorial helps students develop and simulate their VHDL designs using the integrated simulation environment.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    97 views13 pages

    Aldec Active-HDL Simulation

    Uploaded by

    Sushil Kumar
    This document provides a tutorial on using Aldec Active-HDL software to simulate VHDL designs. It discusses compiling VHDL files to create simulation models, debugging compilation errors, and performing functional simulation by running test benches to verify circuit behavior. Waveforms of desired signals can be viewed and simulation can be run continuously, until a specified time, or for a set duration. The tutorial helps students develop and simulate their VHDL designs using the integrated simulation environment.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 13

    Tutorial on

    Simulation
    using
    Aldec Active-HDL

    Ver 2.0


    by Shashi Karanam, Kishore Kumar Surapathi







    lnLroducLlon

    AcLlve-PuL ls an lnLegraLed envlronmenL deslgned for developmenL of vPuL deslgns. 1he core of
    Lhe sysLem ls a vPuL slmulaLor. Along wlLh debugglng and deslgn enLry Lools, lL makes up a compleLe
    sysLem LhaL allows you Lo wrlLe, debug and slmulaLe vPuL code. 8ased on Lhe concepL of a deslgn,
    AcLlve-PuL allows you Lo organlze your vPuL resources lnLo a convenlenL and clear sLrucLure.

    SLudenLs can use AcLlve-PuL Lo perform followlng Lasks:
    developmenL of Lhe vPuL based deslgns,
    funcLlonal slmulaLlon of Lhelr code,
    funcLlonal slmulaLlon of Lhe synLheslzed code,
    Llmlng slmulaLlon of Lhe hardware lmplemenLaLlon.

    !"#$%&'($)

    1hls LuLorlal helps you Lo
    CreaLe a new deslgn or add .vhd flles Lo your deslgn
    Complle and debug your deslgn
    erform slmulaLlon

    noLe : 1hls LuLorlal does noL explaln Lhe synLhesls or lmplemenLaLlon sLeps.

    *&+,&-./)
    )
    1. SLarL >> vLSl 1ools >> AcLlve-PuL 8.2
    !
    !
    !
    !
    !
    "#!$%&%'(!')%"(%!*%+!+,)-./"'%!"*0!'&1'-!234!')%"(%.!*%+!+,)-./"'%!1*!5,6)!01)%'(,)5#!
    7#!$%&%'(1*8!,/%*!%91.(1*8!+,)-./"'%!81:%.!5,6!(;%!,/(1,*!(,!';,,.%!<),=!5,6)!/)%:1,6.!>,)-./"'%?.#!
    !
    !
    !"!! @5/%! (;%! *"=%! "*0! .%&%'(! &,'"(1,*! ,<! 5,6)! 0%.1)%0! +,)-./"'%! "*0! '&1'-! #$#! A<! 5,6?)%! 6.1*8!
    .';,,&?.! &"74! 1(! 1.! )%',==%*0%0! (,! +,)-! 1*! 5,6)! &,'"&?.! 0)1:%! BC! 0)1:%D4! ".! 5,6)! (;6=7! 0)1:%! "*0! 5,6)!
    *%(+,)-!0)1:%!B3!0)1:%D!")%!.&,+#!E,)!*,+4!6.%!F&"70%=,G!".!5,6)!+,)-./"'%#!
    !
    !
    !
    !
    !
    !
    !
    !
    !
    %"! $%&%'(!&'()*(+),+-./*0+1(234,4!"*0!'&1'-!5(6*#!
    !
    !
    !
    !"! "#$$%&!'($)*!+,-./-0!)$12,.3/-4,$1!-%!#$%&'()*+#,*(&-.'&.&!-1+!5&2-3(4!657!(-1.3-.&!-%!/+#,8!
    7&-9&!4#&!:-/.&4!:&)#1$($.;!'(-1*%!-%!1$4!+&2,1&+8!"(,)*!0$1)<!
    !
    !
    !
    !
    !
    !
    !"! "#$%!&'%!(%)*+,!,-.%!#/0!1-,&!&/!23%-&%!-,(!45*26!#$%&7!8/3!&'*)!&0&/3*-59!0)%!:-,(+-&%;!-)!#/03!
    (%)*+,!,-.%7!
    !
    !
    !
    !
    !"!! "#$%&'!'()#!('*!*#$%&'!*%+#,-.+/!0%11!2#!*%$31(/#*!3+.,##*!45+-6#+!2/!,1%,7%'&!#$%$&'8!!
    !
    !
    !
    !"!! "#!$%&!'&($!)#*+,-./&!.01!0&)!1&,230!.*&!12,-'.4&15!
    !
    !
    !
    !
    #"!! 6#7!/.0!.11!.'*&.14!&82,$203!9:;<!,#7*/&!(2'&,5!"#!/*&.$&!.!0&)!9:;<!,#7*/&!(2'&!7,203!$%&!,#7*/&!
    /#1&!)2=.*1!$%&'%&(!
    &
    6
    2. Compiling designs

    Compilation of the VHDL code is necessary to create simulation model of
    the described circuit. The compiler checks all the syntax and writes all the
    necessary information in the internal binary format. It should be clearly noted that
    the compilers ability to find errors is limited to syntax errors only. Many other
    errors and mistakes can be found only when performing thorough simulation. It is
    also important to understand that the compilation does not produce any
    synthesized code for implementation purposes. This task is performed in
    Foundation Series exclusively.

    2.1 Compiling selected files

    Select the file you want to compile and press button or press F11 on
    the keyboard. This will start compilation.



    7
    If everything went right during the compilation, you should see check mark
    near your file. You can also expand the branch headed by the library icon to
    see that all compiled entities and architectures have been added to the project
    library.

    check mark
    compiled
    entities
    messages
    from
    compiler


    If the compilation process did not end with success, the compiler will
    produce meaningful descriptions of errors. All places in your code where errors
    were found will be highlighted.

    errors found in
    this entity
    architecture has
    not been
    compiled to the
    library
    located errors

    8
    2.2 Compiling all files

    The entire design can be compiled at once by pressing buttons: or .
    If all the entities in the design are organized in the clear hierarchical structure, the
    compiler will automatically recognize the top-level entity. However, if distinct
    hierarchies of entities exist, the compiler will leave the choice of the top-level
    entity for you.

    More than one
    top-level entities
    detected



    9
    3. Simulating the design

    Simulation can be performed when the entire design has been
    successfully compiled. It means that the simulation model of all elements has
    been created. Simulator can be configured to stimulate all inputs to the circuit,
    however students should learn to write test benches top-level testers described
    behaviorally. The task of test bench is to produce all the stimulation to the tested
    circuit to verify its correctness. Once the test bench is created, performing
    simulation becomes an easy task.

    Simulation is performed in a graphical way simulator plots waveforms of
    all signals being of designers interest. To create an empty waveform click on the
    button . Next add desired signals by clicking on the button .

    select desired
    signals
    signals can be selected
    from any level in hierarchy


    10
    When you are done with adding signals, you can attempt to perform
    simulation. There are three slightly different ways to run it:

    by pressing button - the simulation will run until you will stop it by pressing
    .
    by pressing button - the simulation will run until specified point of time will
    be reached.
    by pressing button - the simulation will run for specified amount of time.

    The result of simulation is represented in the form of waveforms.



    You can always restart simulation by pressing button .

    You might also like