Verilog HDL Basics

What is Verilog
Hardware Description Language (HDL) Developed in 1984 Standard: IEEE 1364, Dec 1995

Verilog HDL Basics

Verilog vs. VHDL

VHDL
Used throughout Europe, Japan and IBM More strict syntax

Verilog
Preferred in commercial product design Easy to learn and use C-like language

Reality
Impossible to say which is better: matter of taste

Verilog HDL Basics

Basic Limitation of Verilog

Description of digital systems only

Verilog HDL Basics

Abstraction Levels in Verilog

Behavioral Behavioral RTL RTL Gate Gate Layout Layout(VLSI) (VLSI) Our focus

Verilog HDL Basics

User Identifiers
Formed from {[A-Z], [a-z], [0-9], _, $}, but .. .. cant begin with $ or [0-9]
myidentifier m_y_identifier 3my_identifier $my_identifier _myidentifier$

    

Case sensitivity
myid

Myid
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Comments
// The rest of the line is a comment /* Multiple line comment */ /* Nesting /* comments */ do NOT work */

Verilog HDL Basics

Verilog Value Set

0 1 x z represents low logic level or false condition represents high logic level or true condition represents unknown logic level represents high impedance logic level
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Nets (i)
Can be thought as hardware wires driven by logic Equal z when unconnected Various types of nets
wire wand wor tri

(wired-AND) (wired-OR) (tri-state)

In following examples: Y is evaluated, automatically, every time A or B changes

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Nets (ii)
A B Y
wire Y; // declaration assign Y = A & B;

A Y B

wand Y; // declaration assign Y = A; assign Y = B;

wor Y; // declaration assign Y = A; assign Y = B;

dr A Y
tri Y; // declaration assign Y = (dr) ? A : z;

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Verilog HDL Basics

Registers
Variables that store values Do not represent real hardware but .. .. real hardware can be implemented with registers Only one type: reg
reg A, C; // declaration // assignments are always done inside a procedure A = 1; C = A; // C gets the logical value 1 A = 0; // C is still 1 C = 0; // C is now 0

Register values are updated explicitly!!

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Vectors
Represent buses
wire [3:0] busA; reg [1:4] busB; reg [1:0] busC;

Left number is MS bit Slice management

busC = busA[2:1];

busC[1] = busA[2]; busC[0] = busA[1];

Vector assignment (by position!!)

busB[1] = busA[3]; busB = busA; busB[2] = busA[2]; busB[3] = busA[1]; busB[4] = busA[0];
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Integer & Real Data Types

Declaration
integer i, k; real r;

Use as registers (inside procedures)

i = 1; // assignments occur inside procedure r = 2.9; k = r; // k is rounded to 3

Integers are not initialized!! Reals are initialized to 0.0

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Logical Operators
&& logical AND || logical OR

logical NOT Operands evaluated to ONE bit value: 0, 1 or x Result is ONE bit value: 0, 1 or x
!
A = 6; B = 0; C = x; A && B 1 && 0 0 A || !B 1 || 1 1 but C || B x || 0 x butC&&B=0 C&&B=0

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Verilog HDL Basics

Bitwise Operators (i)

&

bitwise AND | bitwise OR ~ bitwise NOT ^ bitwise XOR ~^ or ^~ bitwise XNOR

Operation on bit by bit basis

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Bitwise Operators (ii)

c = ~a; c = a & b;

a = 4b1010; b = 4b1100;

c = a ^ b;

a = 4b1010; b = 2b11;
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Shift Operators
shift right << shift left
>>

Result is same size as first operand, always zero filled

a = 4b1010; ... d = a >> 2; // d = 0010 c = a << 1; // c = 0100

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Verilog HDL Basics

Conditional Operator
cond_expr ? true_expr : false_expr

Like a 2-to-1 mux ..

A B 1 0 sel

Y = (sel)? A : B;

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Verilog HDL Basics

Arithmetic Operators (i)

+, -, *, /, %

Negative registers:
regs can be assigned negative but are treated as unsigned
reg [15:0] regA; .. regA = -4d12; regA/3 // stored as 216-12 = 65524

evaluates to 21861

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Verilog HDL Basics

Arithmetic Operators (ii)

Negative integers:
can be assigned negative values different treatment depending on base specification or not
reg [15:0] regA; integer intA; .. intA = -12/3; intA = -d12/3; // evaluates to -4 (no base spec) // evaluates to 1431655761 (base spec)

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Verilog HDL Basics

Operator Precedence

Use parentheses to enforce your priority

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Verilog HDL Basics

Hierarchical Design
Top TopLevel Level Module Module Sub-Module Sub-Module 11 Basic BasicModule Module Basic BasicModule Module 11 22 Sub-Module Sub-Module 22 Basic BasicModule Module 33 E.g. Full FullAdder Adder

Half HalfAdder Adder

Half HalfAdder Adder

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Verilog HDL Basics

Module
module my_module(out1, .., inN);

in1 in2

my_module

out1 out2

output out1, .., outM; input in1, .., inN;

f
inN outM

.. // declarations .. // description of f (maybe .. // sequential)

endmodule

Everything you write in Verilog must be inside a module exception: compiler directives
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Example: Half Adder

A B C wire S, C, A, B; A B S assign S = A ^ B; assign C = A & B; endmodule S module half_adder(S, C, A, B); output S, C; input A, B;

Half Half Adder Adder

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Verilog HDL Basics

Example: Full Adder

in1 in2 A B

Half Half Adder Adder11 ha1 ha1

I1

A B

C I2

Half Half Adder Adder ha2 ha2

S C I3

sum cout

cin
module full_adder(sum, cout, in1, in2, cin); output sum, cout; input in1, in2, cin; wire sum, cout, in1, in2, cin; wire I1, I2, I3; half_adder ha1(I1, I2, in1, in2); half_adder ha2(sum, I3, I1, cin); assign cout = I2 || I3; endmodule
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Module name

Instance name

Hierarchical Names
ha2.A
in1 in2 A B

Half Half Adder Adder11 ha1 ha1

I1

A B

C I2

Half Half Adder Adder ha2 ha2

S C I3

sum cout

cin

Remember to use instance names, not module names

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Port Assignments
module

Inputs

reg or net

net

module

Outputs

reg or net

net

module

Inouts

net

net

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Verilog HDL Basics

Structural Model (Gate Level)

Built-in gate primitives:
and, nand, nor, or, xor, xnor, buf, not, bufif0, bufif1, notif0, notif1

Usage:
nand (out, in1, in2); 2-input NAND without delay and #2 (out, in1, in2, in3); 3-input AND with 2 t.u. delay not #1 N1(out, in); NOT with 1 t.u. delay and instance name xor X1(out, in1, in2); 2-input XOR with instance name

Write them inside module, outside procedures

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Example: Half Adder, 2nd Implementation

A B C wire S, C, A, B; xor #2 (S, A, B); and #1 (C, A, B); endmodule S module half_adder(S, C, A, B); output S, C; input A, B;

Assuming: XOR: 2 t.u. delay AND: 1 t.u. delay

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Verilog HDL Basics

Behavioral Model - Procedures (i)

Procedures = sections of code that we know they execute sequentially Procedural statements = statements inside a procedure (they execute sequentially) e.g. another 2-to-1 mux implem:
Execution Flow

begin if (sel == 0) Y = B; else Y = A; end

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Procedural Proceduralassignments: assignments: Y Ymust mustbe bereg reg!! !!

Verilog HDL Basics

Behavioral Model - Procedures (ii)

Modules can contain any number of procedures Procedures execute in parallel (in respect to each other) and .. .. can be expressed in two types of blocks:
initial they execute only once always they execute for ever (until simulation finishes)

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Verilog HDL Basics

Initial Blocks
Start execution at sim time zero and finish when their last statement executes
module nothing; initial $display(Im first); initial begin #50; $display(Really?); end endmodule
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Will Willbe bedisplayed displayed at atsim simtime time00 Will Willbe bedisplayed displayed at atsim simtime time50 50

Always Blocks
Start execution at sim time zero and continue until sim finishes

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Verilog HDL Basics

Events (i)
@
always @(signal1 or signal2 or ..) begin .. end execution triggers

execution triggersevery every time timeany anysignal signalchanges changes

always @(posedge clk) begin .. end

execution executiontriggers triggersevery every time timeclk clkchanges changes from from0 0to to1 1 execution executiontriggers triggersevery every time timeclk clkchanges changes from from1 1to to0 0
Verilog HDL Basics

always @(negedge clk) begin .. end

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Examples
3rd half adder implem
module half_adder(S, C, A, B); output S, C; input A, B; reg S,C; wire A, B; always @(A or B) begin S = A ^ B; C = A && B; end endmodule

Behavioral edge-triggered DFF implem

module dff(Q, D, Clk); output Q; input D, Clk; reg Q; wire D, Clk; always @(posedge Clk) Q = D; endmodule

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Verilog HDL Basics

Events (ii)
wait (expr)
always begin wait (ctrl) #10 cnt = cnt + 1; #10 cnt2 = cnt2 + 2; end

execution executionloops loopsevery every time timectrl ctrl= =1 1(level (level sensitive sensitivetiming timingcontrol) control)

e.g. Level triggered DFF ?

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Verilog HDL Basics

Example
always @(res or posedge clk) begin if (res) begin Y = 0; W = 0; end else begin Y = a & b; W = ~c; end end

res a b c clk Y

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Verilog HDL Basics

Procedural Statements: if
E.g. 4-to-1 mux:

if (expr1) true_stmt1; else if (expr2) true_stmt2; .. else def_stmt;

module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) if (sel == 0) out = in[0]; else if (sel == 1) out = in[1]; else if (sel == 2) out = in[2]; else out = in[3]; endmodule
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Procedural Statements: case

E.g. 4-to-1 mux:

case (expr) item_1, .., item_n: stmt1; item_n+1, .., item_m: stmt2; .. default: def_stmt; endcase

module mux4_1(out, in, sel); output out; input [3:0] in; input [1:0] sel; reg out; wire [3:0] in; wire [1:0] sel; always @(in or sel) case (sel) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcase endmodule
Verilog HDL Basics

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Procedural Statements: for

for (init_assignment; cond; step_assignment) stmt;
E.g.
module count(Y, start); output [3:0] Y; input start; reg [3:0] Y; wire start; integer i; initial Y = 0; always @(posedge start) for (i = 0; i < 3; i = i + 1) #10 Y = Y + 1; endmodule
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Procedural Statements: while

E.g.
module count(Y, start); output [3:0] Y; input start; reg [3:0] Y; wire start; integer i;

while (expr) stmt;

initial Y = 0; always @(posedge start) begin i = 0; while (i < 3) begin #10 Y = Y + 1; i = i + 1; end end endmodule
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Mixed Model
Code that contains various both structure and behavioral styles
module simple(Y, c, clk, res); output Y; input c, clk, res; reg Y; wire c, clk, res; wire n;

res c clk n Y

not(n, c); // gate-level always @(res or posedge clk) if (res) Y = 0; else Y = n; endmodule
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