PBL10 Project Compal Confidential: LA-6731P Schematic REV1.0

5
Compal Confidential
s
e
.
PBL10 Project
e
s
er
iv
n
U
LA-6731P REV1.0
Schematic
k
o
o
b
e
t
o
Intel
Bridge/Cougar Point(UMA)
N Sandy2010-12-06
Rev 1.0
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/05/17
Issued Date
Deciphered Date
2011/05/17
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
Wednesday, March 09, 2011
Sheet
1
of
45
CK505
Compal Confidential
Model Name : PBL10
File Name : LA-6731P
Fan Control
page 5
Clock Generator
ICS9LRS Page 14
Mobile Sandy Bridge

CPU Dual Core
Memory BUS(DDRIII)
Socket-rPGA989
page 5,6,7,8,9,10,11
37.5mm*37.5mm
204pin DDRIII-SO-DIMM X2
Dual Channel
DMI X4
1.5V DDRIII 1066/1333
BANK 0, 1, 2, 3
FDI X4
LCD Conn.
USB/B Right USB/B Left
page 15
USB port 0,1
USB port 2
s
e
.
page 29
CRT
page 16
page 17
RTS5138 3IN1
USB port 11
USB port 3
page 15
Intel Cougar Point
page 17
FCBGA989
25mm*25mm
PCIeMini Card
WLAN & BT 2.0
o
b
te
USB port 5
PCIe port 2
page 29
RJ45
USB&Audio/B
page 30
page 29
Power/B
o
N
RTL8111E Giga
RTL8105E 10/100
PCIe 1x
SATA port 1
U
k
o
USB
5V 1.5GHz(150MB/s)
SATA port 4
5V 1.5GHz(150MB/s)
1.5V 2.5GHz(250MB/s)
page 29
Int. Camera
e
s
r
e
niv
USB
HDMI
Level Shifter
HDMI Conn.
page 12,13
page 32
SATA HDD0
page 27
SATA ODD
page 27
SPI ROM
page 28
B
PCIe 1x
1.5V 2.5GHz(250MB/s)
page 18,19,20,21
22,23,24,25,26
PCIe port 3
page 30
HD Audio
3.3V 24.576MHz/48Mhz
HDA Codec
page 34
ALC259
page 31
Touch Pad/B
page 34
ENE KB930
page 33
RTC CKT.
Int.
MIC CONN
page 15
page 36
DC/DC Interface CKT.
page 32
2010/05/17
Issued Date
Deciphered Date

2011/05/17
Title
Size
page 36,37,38,39,
40,41,42,43,44
Date:
SPK CONN
page 31
page 32
Compal Secret Data
Power Circuit DC/DC
HP CONN
page 29
SPI ROM
Int.KBD
page 35
MIC CONN
page 29
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
Sheet
1
of
45
POK
B+
+3VL
+5VL
+5VALW
UP6182CQAG
B+
+VSB
TP0610K
+CPU_CORE
SUSP
ISL95831CRZ
+5VS
SI4800BDY
+VGFX_CORE
SYSON
+HDMI_5V_OUT
RB161M
+1.5V
G5603RU1U
SUSP
+CRT_VCC
RB491D
USB_EN#
SUSP#
USB_EN#
+USB_VCCB
RT9715BGS
SUSP
e
v
i
SUSP#
UP7711U8
+1.8VS
SY8033BDBC
n
U
k
o
o
b
+3VALW
PCH_PWR_EN#
SI4800BDY
+0.75VS
SUSP#
G5603RU1U
+VCCSA
+3VALW_PCH
e
t
o
N
VGA_ENVDD
+1.05VS_VCCP
e
s
r
G5603RU1U
SUSP
s
e
.
+USB_VCCA
RT9715BGS
SI4800BDY
+1.5VS
SI4856ADY
AO3413
+3VS
+LCD_VDD
+3V_LAN
2010/05/17
Issued Date
Compal Secret Data
2011/05/17
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
Sheet
1
of
45
Voltage Rails
Power Plane
Description
EC SM Bus1 address
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.0VSDGPU
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.05VS_VCCP
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
ON
OFF
OFF
+1.05VS_PCH
+1.05VS_VCCP to +1.05VS_PCH power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII
ON
ON
OFF
+1.5VS
+1.5V to +1.5VS switched power rail
ON
OFF
OFF
+1.5VSDGPU
+1.5VS to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.8VS
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON
OFF
OFF
+3VALW
+3VALW always on power rail
ON
ON
ON*
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
+3V_LAN
+3VALW to +3V_LAN power rail for LAN
ON
ON
ON*
+3VALW_PCH
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
+5VALW_PCH
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
HIGH
HIGH
HIGH
HIGH
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
LOW
Full ON
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VS
Clock
ON
ON
ON
ON
e
t
o
N
ON
ON
ON
OFF
ON
OFF
OFF
ON
OFF
OFF
Device
Device
Address
Clock Generator (9LVS3199AKLFT,

RTM890N-631-VB-GRT)
1101 0010b
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
BOM configu table

SKU
Bom config
46196830L01
DA6@/HDMI@/8105E@/PCH@
46196830L02
s
r
e
v
ni
3
4
DA6@/HDMI@/8111E@/PCH@
U
k
o
o
b
+V
ON
0001 011X b
7
8
s
e
e.
LOW
Bom configu(HDMI@/8105E@/8111E@/DA6@/DAZ@/45@)
OFF
PCH And PCBA table
OFF
OFF
Address
PCH SM Bus address
+VALW
ON
Address
Smart Battery
SIGNAL
Device
EC SM Bus2 address
Description
C
PBL10 UMA DUAL 10-100

PBL10 UMA DUAL GIGA LAN
U4
BD82HM65 SLH9D B2 FCBGA 989P PCH
PCH@
PCH
ZZZ
DAZ@
ZZZ
DA6@
ZZZ
DA4@
ZZZ
DA2@
PCB
PCB LA-6731P REV10
PCB LA-6731P REV10
PCB LS-6732P REV10
PCB LS-6731P REV10
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title
Size Document Number
Custom
SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet
1
of
45
H_PM_SYNC
PM_SYS_PWRGD_BUF
BUF_CPU_RST#
T5
23,33
2@
0.1U_0402_16V4Z
2@
0.1U_0402_16V4Z
1
C238
1
C243
H_PECI
1 62_0402_5%
H_CATERR#
H_PECI_ISO
1
10K_0402_5%
23 H_THRMTRIP#
R54
0_0402_5%
1
2
H_THEMTRIP#_R
AN32
THERMTRIP#
20 H_PM_SYNC
23 H_CPUPWRGD
R64
0_0402_5%
1
2
H_PM_SYNC_R
H_CPUPWRGD_R
R60
75_0402_5%
U2
R66
43_0402_1%
1
2 BUF_CPU_RST#
BUFO_CPU_RST#
NC
A
e
t
o
N
+1.05VS_VCCP
C82
0.1U_0402_16V4Z
SN74LVC1G07DCKR_SC70-5
@
R68
0_0402_5%
UNCOREPWRGOOD
SM_DRAMPWROK
AR33
RESET#
20 PM_DRAM_PWRGD
33
+1.5V_CPU_VDDQ
EN_DFAN1
10mil
+1.05VS_VCCP
H_DRAMRST# 7
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
AK1
A5
A4
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
AP29
AP27
TCK
TMS
TRST#
AR26
AR27
AP30
XDP_TCK
XDP_TMS
XDP_TRST#
TDI
TDO
AR28
AP26
XDP_TDI_R
XDP_TDO_R
s
e
.
SM_RCOMP0 R49
1 140_0402_1%
SM_RCOMP1 R51
1 25.5_0402_1%
SM_RCOMP2 R53
1 200_0402_1%
XDP_TMS
e
s
r
e
v
ni
DBR#
AL35
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
+1.05VS_VCCP
R55
1 51_0402_5%
XDP_TDI_R R56
1 51_0402_5%
XDP_TDO_R R57
1 51_0402_5%
XDP_TCK
R59
1 51_0402_5%
XDP_TRST# R62
1 51_0402_5%
R266 1K_0402_5%
1
2
+3VS
XDP_DBRESET#
XDP_DBRESET# 18,20
JFAN
1
U3
74AHC1G09GW_TSSOP5
R81
200_0402_5%
EN
VIN
VOUT
VSET
+FAN1
1
2
3
1
2
3
@ C864
@C864
1000P_0402_50V7K
4
5
GND
GND
2
GND
GND
GND
GND
8
7
6
5
ACES_85205-03001
CONN@
G996P11U SOP 8P
C17
10U_0805_10V4Z
R219
2
10K_0402_5%
1
+3VS
FAN_SPEED1 33
PM_SYS_PWRGD_BUF
G
3
C865@
0.01U_0402_25V7K
20 SYS_PWROK
1 2
@
R83
39_0402_5%
35,42
SUSP
SUSP
Compal Secret Data
D
2
G
3
1
2
3
4
+FAN1
CLK_CPU_DMI 19
CLK_CPU_DMI# 19
2
C863
10U_0805_10V4Z
+3VALW
R82
0_0402_5%
1
2
2 0_0402_5%
2 0_0402_5%
1A
U58
C83
0.1U_0402_16V4Z
CLK_BUF_CPU_BCLK 14
CLK_BUF_CPU_BCLK# 14
FAN Control Circuit
PLT_RST# 22,29,30,33
Follow DG 0.71
2 0_0402_5%
2 0_0402_5%
+5VS
PLT_RST# 2
V8
PM_SYNC
Sandy Bridge_rPGA_Rev1p0
CONN@
Buffered reset to CPU
AP33
1
1
2 1K_0402_5%
2 1K_0402_5%
H_DRAMRST#
R8
SM_DRAMRST#
U
k
o
o
b
H_CPUPWRGD_R
2
330P_0402_50V7K
CLOSE TO PCH, EMI DEMAND
+3VS
AM34
R43
R44
@
@
PU/PD for JTAG signals
H_PROCHOT#
PECI
PROCHOT#
R58
0_0402_5%
1
2
A16 R234 1
A15 R240 1
DPLL_REF_CLK
DPLL_REF_CLK#
1
1
DDR3 Compensation Signals
AL32
R65
130_0402_5%
PM_SYS_PWRGD_BUF 1
2 PM_DRAM_PWRGD_R
1
C312
AN33
CLK_CPU_DMI_R
CLK_CPU_DMII#_R
A28
A27
R41
R42
CATERR#
H_PROCHOT#_R
BUF_CPU_RST#
2
R50
AL33
SKTOCC#
33 H_PROCHOT#
Processor Pullups
2
AN34
R52
56_0402_5%
1
2
R47
PAD
R48
0_0402_5%
1
2
EMI Demand
+1.05VS_VCCP
SKTOCC#
CLOCKS
H_THRMTRIP#
PAD
DDR3
MISC
2@
0.1U_0402_16V4Z
2@
0.1U_0402_16V4Z
2@
0.1U_0402_16V4Z
1
C234
1
C235
1
C236
BCLK
BCLK#
JTAG & BPM
T68
H_PROCHOT#
PROC_SELECT#
THERMAL
C26
22 H_SNB_IVB#
PWR MANAGEMENT
MISC
JCPUB
@
Q4
2N7002_SOT23
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Rev
D
401968
Date:
Sheet

1
of
45
+1.05VS_VCCP
20
20
20
20
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
20
20
20
20
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
20
20
20
20
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
20
20
20
20
20
20
20
20
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
20
20
20
20
20
20
20
20
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
20 FDI_FSYNC0
20 FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
20 FDI_INT
H20
FDI_INT
20 FDI_LSYNC0
20 FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
R185 1
A18
A17
B16
eDP_COMPIO
eDP_ICOMPO
eDP_HPD
C15
D15
eDP_AUX
eDP_AUX#
C17
F16
C16
G15
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
2 1K_0402_5%
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
s
e
.
e
s
r
e
niv
U
k
o
o
b
e
t
o
N
EDP_COMP
+1.05VS_VCCP
DMI
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
Intel(R) FDI
B27
B25
A25
B24
PCI EXPRESS* - GRAPHICS
R18
24.9_0402_1%
2
eDP_COMPIO and ICOMPO signals

should be shorted near balls
and routed with typical
impedance <25 mohms
+1.05VS_VCCP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
eDP
20
20
20
20
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
R17
24.9_0402_1%
JCPUA
CONN@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
of
45
JCPUC
JCPUD
12 DDR_A_BS0
12 DDR_A_BS1
12 DDR_A_BS2
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
AE10
AF10
V6
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
SA_CAS#
SA_RAS#
SA_WE#
12 DDR_A_CAS#
12 DDR_A_RAS#
12 DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
AB6
AA6
V9
M_CLK_DDR0 12
M_CLK_DDR#0 12
DDR_CKE0_DIMMA 12
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
AA5
AB5
V10
M_CLK_DDR1 12
M_CLK_DDR#1 12
DDR_CKE1_DIMMA 12
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
AB4
AA4
W9
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
AB3
AA3
W10
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
AK3
AL3
AG1
AH1
DDR_CS0_DIMMA# 12
DDR_CS1_DIMMA# 12
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
AH3
AG3
AG2
AH2
M_ODT0 12
M_ODT1 12
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
C4
G6
J3
M6
AL6
AM8
AR12
AM15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
12
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
AE2
AD2
R9
M_CLK_DDR2 13
M_CLK_DDR#2 13
DDR_CKE2_DIMMB 13
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
AE1
AD1
R10
M_CLK_DDR3 13
M_CLK_DDR#3 13
DDR_CKE3_DIMMB 13
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
AB2
AA2
T9
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
AA1
AB1
T10
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
AD3
AE3
AD6
AE6
DDR_CS2_DIMMB# 13
DDR_CS3_DIMMB# 13
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
AE4
AD4
AD5
AE5
M_ODT2 13
M_ODT3 13
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
s
e
.
e
s
r
e
niv
12
U
k
o
o
b
e
t
o
N
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#[0..7]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
13 DDR_B_D[0..63]
12
13 DDR_B_BS0
13 DDR_B_BS1
13 DDR_B_BS2
13 DDR_B_CAS#
13 DDR_B_RAS#
13 DDR_B_WE#
CONN@
AA9
AA7
R6
SB_BS[0]
SB_BS[1]
SB_BS[2]
AA10
AB8
AB9
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
DDR SYSTEM MEMORY A
12 DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
13
13
13
CONN@
+1.5V
R85
1K_0402_5%
2
@ R84
0_0402_5%
1
2
H_DRAMRST#
DDR3_DRAMRST#_R
1
Q5
BSS138_NL_SOT23-3
3
2
5 H_DRAMRST#
R89
33 DRAMRST_CNTRL_EC
DDR3_DRAMRST# 12,13
R88
0_0402_5%
1
2
19 DRAMRST_CNTRL_PCH
R86
1K_0402_5%
2
R87
4.99K_0402_1%
DRAMRST_CNTRL
Compal Secret Data
2 0_0402_5%
1
Issued Date
C84
0.047U_0402_16V4Z
2010/05/17
2011/05/17
Deciphered Date
Title
Rev
D
401968
Date:

SCHEMATICS,MB A6731
Sheet

1
of
45
CFG Straps for Processor

JCPUE
PEG Static Lane Reversal - CFG2 is for the 16x

T63
T60
T62
T59
T61
T74
T76
T75
T78
T80
T77
T85
T83
T84
T82
T79
T81
PAD
PAD
PAD
PAD
PAD
PAD
PAD
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
L7
AG7
AE7
AK2
W8
RSVD33
RSVD34
RSVD35
AT26
AM33
AJ27
RSVD37
RSVD38
RSVD39
RSVD40
T8
J16
H16
G16
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
AR35
AT34
AT33
AP35
AR34
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
B34
A33
A34
B35
C35
1: Normal Operation; Lane #

socket pin map definition
CFG2
definition matches
0:Lane Reversed
Display Port Presence Strap
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
CFG4
s
e
.
*
e
s
r
0 : Enabled; An external Display Port device is

connected to the Embedded Display Port
PCIE Port Bifurcation Straps
T6
T7
T8
T9
PAD
PAD
PAD
PAD
AJ31
AH31
AJ33
AH33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AJ26
RSVD5
B4
D1
RSVD6
RSVD7
CPU_RSVD6
CPU_RSVD7
R93
1K_0402_1%
2
R92
1K_0402_1%
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
J20
B18
A19
RSVD24
RSVD25
VCCIO_SEL
J15
RSVD27
e
v
ni
U
k
o
o
b
te
o
N
RESERVED
RSVD51
RSVD52
AJ32
AK32
VCC_DIE_SENSE
AH27
RSVD54
RSVD55
AN35
AM35
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
CFG7
PAD
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2
T10
R187 1
2 1K_0402_5%
CLK_RES_ITP 19
CLK_RES_ITP# 19
B
RSVD56
RSVD57
RSVD58
KEY
AT2
AT1
AR1
B1
CONN@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
of
45
POWER
+CPU_CORE
s
e
.
SVID
1
+
2
1
+ @ C122
330U_D2_2V_Y
2
R98
75_0402_5%
R99
43_0402_1%
1
2
R100 1
2 0_0402_5%
R101 1
2 0_0402_5%
VR_SVID_ALRT# 44
VR_SVID_CLK 44
VR_SVID_DAT 44
Place the PU
resistors close to VR
B
Place the PU
resistors close to CPU
+CPU_CORE
R102
100_0402_1%
VCC_SENSE
VSS_SENSE
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
R103 1
R104 1
2
2
0_0402_5%
0_0402_5%
VCCSENSE 44
VSSSENSE 44
1
SENSE LINES
1
2
1
2
CORE SUPPLY
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
+1.05VS_VCCP
1
2
2
1
2
change C137 from 440U to 330U for PWR demand--1201
C105
22U_0805_6.3V6M
e
t
o
N
C121
330U_D2_2V_Y
C114
22U_0805_6.3V6M
R97
130_0402_5%
AJ29
AJ30
AJ28
+1.05VS_VCCP
VIDALERT#
VIDSCLK
VIDSOUT
e
s
r
e
niv
U
k
o
o
b
C92
22U_0805_6.3V6M
Bottom Socket Edge
J23
C117
330U_D2_2V_Y
C140
330U_D2_2V_Y
C139
470U_D2_2VM_R4.5M
C138
330U_D2_2V_Y
C137
330U_D2_2VM_R4.5M
VCCIO40
C113
22U_0805_6.3V6M
+CPU_CORE
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
C91
22U_0805_6.3V6M
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
C112
22U_0805_6.3V6M
C136
22U_0805_6.3V6M
C132
22U_0805_6.3V6M
C127
22U_0805_6.3V6M
C120
22U_0805_6.3V6M
C135
22U_0805_6.3V6M
C131
22U_0805_6.3V6M
C126
22U_0805_6.3V6M
C119
22U_0805_6.3V6M
C134
22U_0805_6.3V6M
C133
22U_0805_6.3V6M
C130
22U_0805_6.3V6M
C129
22U_0805_6.3V6M
C125
22U_0805_6.3V6M
C118
22U_0805_6.3V6M
C124
22U_0805_6.3V6M
C128
22U_0805_6.3V6M
C116
22U_0805_6.3V6M
C123
22U_0805_6.3V6M
1
C
C115
22U_0805_6.3V6M
C104
22U_0805_6.3V6M
10U_0805_6.3V6M
C111
22U_0805_6.3V6M
C98
10U_0805_6.3V6M
Top Socket Edge 22U * 11

Top Socket Cavity 22U * 8
1
C110
22U_0805_6.3V6M
10U_0805_6.3V6M
C97
C109
22U_0805_6.3V6M
10U_0805_6.3V6M
C96
+1.05VS_VCCP
1
C108
22U_0805_6.3V6M
C95
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
C107
22U_0805_6.3V6M
C94
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
C106
22U_0805_6.3V6M
C93
10U_0805_6.3V6M
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
C90
22U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
+CPU_CORE
C100
10U_0805_6.3V6M
C103
22U_0805_6.3V6M
10U_0805_6.3V6M
C87
+1.05VS_VCCP
C89
22U_0805_6.3V6M
C86
C88
22U_0805_6.3V6M
C85
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
C102
22U_0805_6.3V6M
C99
10U_0805_6.3V6M
Top Socket Cacity 22U *9

Bottom Socket Cacity 22U *10
C101
22U_0805_6.3V6M
10U_0805_6.3V6M
8.5A
PEG AND DDR
94A
Bottom Socket Cacity
JCPUF
VCCIO_SENSE
VSSIO_SENSE
B10
A10
1
R117
R105
100_0402_1%
VCCIO_SENSE 41
2
10_0402_5%
CONN@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
of
45
+1.5V_CPU_VDDQ Source
+1.5V
Q6
AO4728L_SO8
+VSB
+3VALW
R107
470_0603_5%
RUN_ON_CPU1.5VS3
R108
100K_0402_5%
+1.5V_CPU_VDDQ
+1.5V
D
R106
100K_0402_5%
+1.5V_CPU_VDDQ
1
2
3
8
7
6
5
R109
330K_0402_5%
Q7A
2N7002DW-T/R7_SOT363-6
C142
S
0.1U_0402_16V4Z
DDR3 -1.5V RAILS
SA RAIL
C156
0.1U_0402_16V4Z
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
R114
1K_0402_1%
+V_SM_VREF
@Q9
@
Q9
AP2302GN-HF_SOT23-3
R115
1K_0402_1%
RUN_ON_CPU1.5VS3
2
SENSE
LINES
e
s
r
+V_SM_VREF_CNT
+1.5V_CPU_VDDQ
+1.5V
PJ4
10A
1
+
@ JUMP_43X118
C169
330U_D2_2V_Y
PJ5
2
@ JUMP_43X118
Bottom Socket Edge

B
6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA_SENSE
+VCCSA
+VCCSA
M27
M26
L26
J26
J25
J24
H26
H25
H23
R116
2 0_0402_5%
VCCSA_SENSE
1
+
C174
330U_D2_2V_Y
VCCSA_SENSE 43
C22 H_FC_C22
C24
VCCSA_SEL 43
1
FC_C22
VCCSA_VID1

Bottom Socket Edge 10U *1
C173
10U_0603_6.3V6M
MISC
AL1
+1.5V_CPU_VDDQ
R113
0_0402_5%
2
1
C172
10U_0603_6.3V6M
VCCPLL1
VCCPLL2
VCCPLL3
SM_VREF
C171
10U_0603_6.3V6M
R119
10K_0402_5%
CONN@
@R120
@
R120
0_0402_5%
B6
A6
A2
s
e
.
+V_SM_VREF should
have 20 mil trace width
C170
10U_0603_6.3V6M
C178
1U_0402_6.3V6K
C177
1U_0402_6.3V6K
C176
10U_0603_6.3V6M
C175
330U_D2_2V_Y
42
C168
10U_0603_6.3V6M
+1.8VS_VCCPLL
1 0.1U_0402_10V7K
C167
10U_0603_6.3V6M
R118
0_0805_5%
1
2
1
C166
10U_0603_6.3V6M
C237
0.1U_0402_16V4Z
@
EMI DEMAND
+1.8VS
C143
C165
10U_0603_6.3V6M
1 0.1U_0402_10V7K
Follow DG 0.71 page 6
VCC_AXG_SENSE 44
VSS_AXG_SENSE 44
C164
10U_0603_6.3V6M
AK35
AK34
e
v
ni
U
k
o
o
b
e
t
o
N
2
VAXG_SENSE
VSSAXG_SENSE
C163
10U_0603_6.3V6M
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
GRAPHICS
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
1.8V RAIL
C162
22U_0805_6.3V6M
C233
0.1U_0402_16V4Z
@
C152
22U_0805_6.3V6M
C148
22U_0805_6.3V6M
C232
0.1U_0402_16V4Z
@
C161
22U_0805_6.3V6M
+VGFX_CORE
C151
22U_0805_6.3V6M
Bottom Socket Edge

B
C147
22U_0805_6.3V6M
C160
22U_0805_6.3V6M
C155
22U_0805_6.3V6M
C146
22U_0805_6.3V6M
C159
22U_0805_6.3V6M
C154
22U_0805_6.3V6M
C158
470U_D2_2VM_R4.5M
C157
470U_D2_2VM_R4.5M
C150
22U_0805_6.3V6M
C149
22U_0805_6.3V6M
C145
22U_0805_6.3V6M
C144
22U_0805_6.3V6M
C153
22U_0805_6.3V6M
POWER
JCPUG
26A
VREF
+VGFX_CORE
Top Socket Cacity 22U *2

Top Socket Edge 22U *6
Bottom Socket Edge 22U *6
C141
RUN_ON_CPU1.5VS3#
2 RUN_ON_CPU1.5VS3#
G
Q8
2N7002E-T1-GE3_SOT23-3
@ R111
@R111
0_0402_5%
1
2
28,33,35,39,41,43 SUSP#
1
3
RUN_ON_CPU1.5VS3#
6
33 CPU1.5V_S3_GATE
Q7B
2N7002DW-T/R7_SOT363-6
R110
0_0402_5%
1
2
Bottom Socket Edge

Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
10
of
45
JCPUH
D
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUI
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
s
e
.
e
s
r
e
v
ni
U
k
o
o
b
e
t
o
N
CONN@
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
CONN@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
11
of
45
+1.5V
+1.5V
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
R123
1K_0402_1%
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
7 DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
7 DDR_A_WE#
7 DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
+3VS
DDR_A_DM7
D_CK_SDATA
+3VS
2
G
3
D_CK_SCLK
Q2
2N7002E-T1-GE3_SOT23-3
R135
10K_0402_5%
R134
10K_0402_5%
19 PCH_SMBCLK
C200
2.2U_0603_6.3V6K
R4
4.7K_0402_5%
1
2
+3VS
C199
0.1U_0402_16V4Z
+3VS
A
+0.75VS
Q1
2N7002E-T1-GE3_SOT23-3
DDR_A_D58
DDR_A_D59
19 PCH_SMBDATA
2
G
R1
4.7K_0402_5%
1
2
+3VS
205
G1
G2
206
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 7
M_CLK_DDR#1 7
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1 7
DDR_A_RAS# 7
DDR_CS0_DIMMA#
M_ODT0
DDR_CS0_DIMMA# 7
M_ODT0 7
M_ODT1
M_ODT1
DDR_A_D38
DDR_A_D39
+1.5V
1
+
2
R124
1K_0402_1%
Layout Note:
Place near JDIMM1.203,204
DDR_A_D44
DDR_A_D45
+0.75VS
R125
1K_0402_1%
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA 13,14,29
D_CK_SCLK 13,14,29
+0.75VS
A
LCN_DAN06-K4526-0101
CONN@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
+1.5V
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
C198
1U_0402_6.3V6K
DDR_A_D42
DDR_A_D43
e
s
r
e
niv
DDR_A_MA11
DDR_A_MA7
C197
1U_0402_6.3V6K
DDR_A_DM5
s
e
.
DDR_CKE1_DIMMA 7
DDR_A_MA15
DDR_A_MA14
C196
1U_0402_6.3V6K
DDR_A_D40
DDR_A_D41
DDR_CKE1_DIMMA
C195
1U_0402_6.3V6K
DDR_A_D34
DDR_A_D35
DDR_A_D30
DDR_A_D31
C194
0.1U_0402_16V4Z
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#3
DDR_A_DQS3
C193
2.2U_0603_6.3V6K
t
o
N
DDR_A_D32
DDR_A_D33
DDR_A_D28
DDR_A_D29
U
k
o
o
b
e
7 DDR_CS1_DIMMA#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D22
DDR_A_D23
C191
10U_0603_6.3V6M
7 M_CLK_DDR0
7 M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_DM2
C190
10U_0603_6.3V6M
DDR_A_MA3
DDR_A_MA1
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
+1.5V
C189
10U_0603_6.3V6M
DDR_A_MA8
DDR_A_MA5
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
Layout Note:
Place near JDIMM1
DDR_A_D20
DDR_A_D21
C188
10U_0603_6.3V6M
DDR_A_MA12
DDR_A_MA9
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR3_DRAMRST# 7,13
DDR_A_D14
DDR_A_D15
C187
10U_0603_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_A_DM1
DDR3_DRAMRST#
C186
10U_0603_6.3V6M
DDR_A_BS2
7 DDR_A_BS2
DDR_A_D12
DDR_A_D13
C185
10U_0603_6.3V6M
7 DDR_CKE0_DIMMA
DDR_A_D[0..63]
DDR_A_MA[0..15]
C192
330U_B2_2.5VM_R15M
DDR_CKE0_DIMMA
DDR_A_D6
DDR_A_D7
C184
1U_0402_6.3V6K
DDR_A_D26
DDR_A_D27
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_DQS[0..7]
C183
1U_0402_6.3V6K
DDR_A_DM3
DDR_A_DQS#[0..7]
DDR_A_D4
DDR_A_D5
C182
1U_0402_6.3V6K
DDR_A_D24
DDR_A_D25
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C181
1U_0402_6.3V6K
DDR_A_D18
DDR_A_D19
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
DDR_A_D0
DDR_A_D1
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
1
2
All VREF traces should

C180
0.1U_0402_16V4Z
+V_DDR_REF
+1.5V
+V_DDR_REF
C179
2.2U_0603_6.3V6K
R122
1K_0402_1%
JDIMM1
+V_DDR_REF
Sheet

1
12
of
45
+V_DDR_REF
+1.5V
+1.5V
JDIMM2
+V_DDR_REF
C202
0.1U_0402_16V4Z
All VREF traces should

C201
2.2U_0603_6.3V6K
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_D26
DDR_B_D27
7 DDR_B_WE#
7 DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
+3VS
+3VS
C222
2.2U_0603_6.3V6K
C221
0.1U_0402_16V4Z
DDR_B_D56
DDR_B_D57
1
R149
10K_0402_5%
DDR_B_D50
DDR_B_D51
DDR_B_DM7
DDR_B_D58
DDR_B_D59
205
G1
G2
206
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
Layout Note:
Place near JDIMMB
s
e
.
DDR_CKE3_DIMMB 7
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 7
M_CLK_DDR#3 7
DDR_B_BS1
DDR_B_RAS#
DDR_B_BS1 7
DDR_B_RAS# 7
DDR_CS2_DIMMB#
M_ODT2
DDR_CS2_DIMMB# 7
M_ODT2 7
M_ODT3
M_ODT3
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
+1.5V
<BOM
1 Structure>
+
2
Layout Note:
Place near JDIMMB.203,204
+0.75VS
7
+VREF_CA
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA 12,14,29
D_CK_SCLK 12,14,29
+0.75VS
+0.75VS
C218
1U_0402_6.3V6K
DDR_B_D42
DDR_B_D43
C217
1U_0402_6.3V6K
DDR_B_DM5
DDR_B_D28
DDR_B_D29
C216
1U_0402_6.3V6K
DDR_B_D40
DDR_B_D41
C215
1U_0402_6.3V6K
DDR_B_D34
DDR_B_D35
DDR_B_D22
DDR_B_D23
C220
0.1U_0402_16V4Z
t
o
N
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_DM2
C219
2.2U_0603_6.3V6K
o
b
e
DDR_B_D32
DDR_B_D33
+1.5V
DDR_B_D20
DDR_B_D21
e
s
r
e
niv
U
k
o
DDR_B_MA13
DDR_CS3_DIMMB#
7 DDR_CS3_DIMMB#
DDR_B_D14
DDR_B_D15
C213
10U_0603_6.3V6M
7 DDR_B_BS0
DDR_B_MA10
DDR_B_BS0
DDR3_DRAMRST# 7,12
C212
10U_0603_6.3V6M
7 M_CLK_DDR2
7 M_CLK_DDR#2
DDR_B_DM1
DDR3_DRAMRST#
C211
10U_0603_6.3V6M
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA[0..15]
C210
10U_0603_6.3V6M
DDR_B_MA8
DDR_B_MA5
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
7
7
DDR_B_D12
DDR_B_D13
C209
10U_0603_6.3V6M
DDR_B_MA12
DDR_B_MA9
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_B_D[0..63]
DDR_B_D6
DDR_B_D7
C208
10U_0603_6.3V6M
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_B_DQS[0..7]
C207
10U_0603_6.3V6M
DDR_B_BS2
7 DDR_B_BS2
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_DQS#[0..7]
DDR_B_DQS#0
DDR_B_DQS0
C214
330U_B2_2.5VM_R15M
DDR_CKE2_DIMMB
7 DDR_CKE2_DIMMB
DDR_B_D4
DDR_B_D5
C206
1U_0402_6.3V6K
DDR_B_DM3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C205
1U_0402_6.3V6K
DDR_B_D24
DDR_B_D25
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C204
1U_0402_6.3V6K
DDR_B_D18
DDR_B_D19
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C203
1U_0402_6.3V6K
DDR_B_DQS#2
DDR_B_DQS2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
R150
10K_0402_5%
2
LCN_DAN06-K4926-0101
CONN@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
13
of
45
SM010014520 3000ma 220ohm@100mhz DCR 0.04

@ L1
FBMA-L11-201209-221LMA30T_0805
2
1
+3VS
@ L2
FBMA-L11-201209-221LMA30T_0805
2
1
+1.05VS_PCH
C12
0.1U_0402_16V4Z
C13
0.1U_0402_16V4Z
C9 @
10U_0603_6.3V6M
C11
0.1U_0402_16V4Z
C10
10U_0603_6.3V6M
40mil
@ L4
2
1
FBMA-L11-201209-221LMA30T_0805
+1.5VS
C8
0.1U_0402_16V4Z
+CLK_1.5VS
1
C5 @
10U_0603_6.3V6M
C7
0.1U_0402_16V4Z
+CLK_1.05VS
40mil
C6
10U_0603_6.3V6M
C4
0.1U_0402_16V4Z
1
@ L3
@L3
FBMA-L11-201209-221LMA30T_0805 2
2
1
C3
0.1U_0402_16V4Z
C2
10U_0603_6.3V6M
@ C1
10U_0603_6.3V6M
+CLK_3VS
40mil
s
e
.
e
s
r
Use internal Clock first, reseve external clock.
@U1
@
U1
+CLK_1.5VS
+CLK_3VS
1
5
+CLK_1.05VS
15
18
+CLK_3VS
Silego Have Internal Pull-Up
12,13,29 D_CK_SDATA
IDT 9LVS3199AKLFT NC
12,13,29 D_CK_SCLK
@ R9
2 10K_0402_5%
H_STP_CPU#
e
t
o
N
20,33,44
CLK_XTAL_IN
@ C15
27P_0402_50V8J
1
2
Change to 5x3.2
Y1 @
14.31818MHZ 20PF 7A14300003
2
@ C14
1
27P_0402_50V8J
VGATE
19 CLK_BUF_ICH_14M
CLK_XTAL_OUT
VDDSRC_IO
VDDCPU_IO
n
U
k
o
o
b
17
24
29
+CLK_1.5VS
+CLK_3VS
e
v
i
VDD_DOT
VDD_27
CPU_0
23
CPU_0#
22
CLK_BCLK# R3 @ 2
1 33_0402_5% CLK_BUF_CPU_BCLK#
CLK_BUF_CPU_BCLK#
CPU_1
20
R2 @ 2
1 33_0402_5% CLK_BUF_CPU_BCLK
CLK_BUF_CPU_BCLK
5
5
CPU_1#
19
SRC_1/SATA
10
CLK_SATA
1 33_0402_5% CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA 19
SRC_1/SATA#
11
CLK_SATA# R6 @ 2
1 33_0402_5% CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA# 19
R5 @ 2
@R13
@
R13
0_0402_5%
2
1
D_CK_SDATA_R 31
SDA
SRC_2
13
CLK_DMI
R7 @ 2
1 33_0402_5% CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI
2
R14
D_CK_SCLK_R 32
0_0402_5%
SCL
SRC_2#
14
CLK_DMI#
R8 @ 2
1 33_0402_5% CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI#
DOT_96
CLK_96M
R10 @ 2
1 33_0402_5% CLK_BUF_DREF_96M
CLK_BUF_DREF_96M 19
DOT_96#
CLK_96M#
R11 @ 2
1 33_0402_5% CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M# 19
H_STP_CPU#
@ R12
0_0402_5%
2
1
CLK_BUF_ICH_14M
VDDSRC_3.3
VDDCPU_3.3
VDDREF_3.3
CLK_BCLK
@ R15
33_0402_5%
2
1
16
CK505_PWRGD
25
CPU_STOP#
CKPWRGD/PD#
CLK_XTAL_IN
28
XTAL_IN
CLK_XTAL_OUT
27
XTAL_OUT
REF_0/CPU_SEL
30
REF_0/CPU_SEL
27MHz
27MHz_SS
VSS_DOT
VSS_27
VSS_SATA
VSS_SRC
VSS_CPU
VSS_REF
EP
2
8
9
12
21
26
33
19
19
SLG8SP585VTR_QFN32_5X5
Standard
IDT: 9LRS3199AKLFT, SA000030P00
SILEGO: SLG8SP587V(WF), SA00002XY10
IDT Have Internal Pull-Down
FOR Realtek
R16
2 10K_0402_5% REF_0/CPU_SEL
1
@
PIN 30
0 (Default)
1
CPU_0
CPU_1
133MHz
133MHz
100MHz
100MHz
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet
14
H
of
45
+LCD_VDD
2
R1438
0_0402_5%
1
R1441
+3VS
+3VS
Vds=-20V
Id=-3A
Rds=130m ohm
Vgs=-4.5
Vth=-1
1
Q61A
2N7002DW-T/R7_SOT363-6
R688
2
C908
100K_0402_5%
0.1U_0402_16V7K
C958
180P_0402_50V8J
1
R697
Q61B
21
PCH_ENVDD
C712
0.01U_0402_25V7K
5
4
R1379
0_0402_5%
2
47K_0402_5%
R698
300_0603_5%
+3VS
+LCD_VDD
1
2N7002DW-T/R7_SOT363-6
W=80mils
1
@C711
@
C711
4.7U_0805_10V4Z
R693
100K_0402_5%
Q18
AO3413_SOT23
21 PCH_BL_PWM
4.7K_0402_5%
LCD_BL_PWM
6 2
R1440
2
@ 0_0402_5%
1
INVT_PWM
33
+LCDVDD_R
L24 2
1
0_0805_5%
C713
0.1U_0402_16V4Z
C710
4.7U_0805_10V4Z
C709
0.1U_0402_16V4Z
+5VS
21
21
21
21
21
21
33
BKOFF#
R1421
10K_0402_5%
USB20_P10
USB20_N10
LCD_TXOUT0+
LCD_TXOUT0LCD_TXOUT1+
LCD_TXOUT2-
USB20_P10
USB20_N10
47P_0402_50V8J
1
R143
2 @
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
GND GMD
U
k
o
LCD_TXOUT0+
LCD_TXOUT2-
o
b
e
t
o
N
C912
2
JLVDS
22
22
R121
33_0402_5%
1
2 BKOFF#_R
0_0603_5%
1
100_0402_1%
1
+LCD_INV
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
LCD_TXCLK+
LCD_TXCLK-
EDID_CK
EDID_DAT
R1382 1
R1392 1
2 0_0402_5%
2 0_0402_5%
CE_EN_R
R183 1
2 1K_0402_5%
LCD_EDID_CLK 21
LCD_EDID_DATA 21
CE_EN 23
+3VS
LCD_BL_PWM
+LCDVDD_R
BKOFF#_R
1.5A
1
C715
68P_0402_50V8J
L23
2
1
FBMA-L11-201209-221LMA30T_0805
1 Rated Current 1MAX:3000mA
C319
0.1U_0402_25V4K
100K_0402_5%
R1191
C399
C714
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
B+
+LCD_INV
ACES_87242-4001-09
CONN@
LCD_TXCLK+ 21
LCD_TXCLK- 21
R1427
2 @
+3VS
0_0603_5%
1
W=30mils
R1426
2
s
e
.
e
s
r
e
niv
LCD/PANEL BD. Conn.
Close to JLVDS
8/25 For +3VS leakage
@ C400
680P_0402_50V7K
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet

1
15
of
45
2
R701
@ C716
@C716
470P_0402_50V8J
R702
R703
1
C723
C722
CRT_G_L
L20
1
2
NBQ100505T-800Y_0402
CRT_B_L
C720
C721
e
s
r
e
niv
s
e
.
C724
C719
2.2P_0402_50V8C
L19
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
CRT_R_L
2.2P_0402_50V8C
CRT_DDC_CK
2N7002DW-T/R7_SOT363-6
1
@ C717
@ C867
470P_0402_50V8J
33P_0402_50V8K
2
L18
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
VGA_CRT_B
2
1
150_0402_1%
21
2.2P_0402_50V8C
VGA_CRT_G
2.2P_0402_50V8C
21
2
1
150_0402_1%
VGA_CRT_R
2
1
150_0402_1%
2
5
1
@ C866
33P_0402_50V8K
CRT_DDC_DAT
21
2N7002DW-T/R7_SOT363-6
Q157B
4
21 VGA_CRT_CLK
4.7K_0402_5%
4.7K_0402_5%
Q157A
6
R700
R699
PESD5V0U2BT_SOT23-3
+CRT_VCC
21 VGA_CRT_DATA
D31
PESD5V0U2BT_SOT23-3
+3VS
D30
+5VS
1
L21
D_CRT_VSYNC1
L22
P
OE#
5
1
1
2
C868
0.1U_0402_16V4Z
21 VGA_CRT_VSYNC
D_CRT_HSYNC
U46
SN74AHCT1G125GW_SOT353-5
+CRT_VCC
10K_0402_5%
1
+CRT_VCC_R
+CRT_VCC
F3
1
1
2
RB491D_SOT23-3
1
1.1A_6V_MINISMDC110F-2
C718
0.1U_0402_16V4Z
2
@
HSYNC
2
10_0402_5%
JCRT
T65
CRT11
CRT_R_L
PAD
CRT_DDC_DAT
CRT_G_L
VSYNC
2
10_0402_5%
U45
SN74AHCT1G125GW_SOT353-5
1
@ C726
@C726
@ C727
HSYNC
CRT_B_L
+CRT_VCC
10P_0402_50V8J
5
1
P
OE#
21 VGA_CRT_HSYNC
3
e
t
o
N
R1436
2
1
2
C725
0.1U_0402_16V4Z
U
k
o
o
b
10P_0402_50V8J
+CRT_VCC
D58
2
T66
VSYNC
CRT12
PAD
CRT_DDC_CK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
16
17
GND
GND
SUYIN_070546FR015S293ZR
CONN@
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet

E
16
of
45
+3VS
+5VS_HDMI
HDMI_R_D0-
2 R249
0_0402_5%
HDMI@
2 2
HDMI_R_D1-
R405 1 @
R407 1
@
+3VS
WCM-2012-121T_0805
@
1
2 R247
0_0402_5%
VGA_DVI_TXD1+
2.2K_0402_5% 3
2.2K_0402_5% 4
2
2
2 @
1
R410
3.3K_0402_1%
VGA_HDMI_HPD
HDMI_R_D1+
VGA_HDMI_DATA
VGA_DVI_TXD2-
1
L13
1
2 R251
0_0402_5%
HDMI@
2 2
HDMI_R_D2VGA_HDMI_CLK
+3VS
WCM-2012-121T_0805
@
1
2 R223
0_0402_5%
VGA_DVI_TXD2+
0.1U_0402_16V4Z
PCIE_MTX_GRX_HDMI_N3
21
21
21
21
PCIE_MTX_GRX_HDMI_P3
CV174 1
CV179 1
CV175 1
CV177 1
HPD_SINK
30
HDMI_HPD_R
DDC_EN
32
R408 2
@
FUNCTION3
FUNCTION4
34
35
HPD_SOURCE
SDA_SOURCE
ANALOG2
OUT_D4+
OUT_D4-
VGA_DVI_TXD0+ 16
VGA_DVI_TXD0- 17
OUT_D3+
OUT_D3-
VGA_DVI_TXD1+ 19
VGA_DVI_TXD1- 20
OUT_D2+
OUT_D2-
VGA_DVI_TXD2+ 22
VGA_DVI_TXD2- 23
OUT_D1+
OUT_D1-
IN_D4+
IN_D4-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U
k
o
o
b
IN_D3+
IN_D3IN_D2+
IN_D2IN_D1+
IN_D1-
THERMAL_PAD
2
1
1
1
CV178 1
2 0.1U_0402_16V7K HDMI@
CV172 1
2 0.1U_0402_16V7K HDMI@
2 0.1U_0402_16V7K HDMI@
CV176 1
2 0.1U_0402_16V7K HDMI@
CV173 1
2 0.1U_0402_16V7K HDMI@
2 0.1U_0402_16V7K HDMI@
1
2
R221 0_0402_5% HDMI@
1
2
R254 0_0402_5% HDMI@
1
2
R413 0_0402_5% HDMI@
1
2
R222 0_0402_5% HDMI@
1 4.7K_0402_5% +3VS
1
2
2
2
0_0402_5%
2.2K_0402_5%
2.2K_0402_5%
0_0402_5%
48
47
PCIE_MTX_C_GRX_HDMI_P3
PCIE_MTX_C_GRX_HDMI_N3
45
44
42
41
39
38
HDMI_HPD
2
R572
100K_0402_5%
@
U47
Y
HDMI_HPD_R
74AHCT1G125GW_SOT353-5
@
s
e
.
@
@
@
@
1
2HDMI_HPD_R
R432 0_0402_5%
HDMI@
C728
HDMI@
1
0.1U_0402_16V4Z
+3VS
e
s
r
e
niv
SCL_SOURCE
13
14
R406
R411
R403
R404
+3VS
+3VS
+HDMI_5V_OUT
R1328
2.2K_0402_5%
HDMI@
HDMI_SCLK
R1329
2.2K_0402_5%
HDMI@
1
HDMI_SDATA
R1332
2.2K_0402_5%
HDMI@
R1331
2.2K_0402_5%
HDMI@
VGA_HDMI_CLK 21
BSH111_SOT23-3
HDMI@
Q183
3
Q182
BSH111_SOT23-3
HDMI@
1
VGA_HDMI_DATA 21
49
2 0.1U_0402_16V7K HDMI@
2 0.1U_0402_16V7K HDMI@
HDMI_R_CK+
R1560 1
HDMI_R_CK-
R1561 1
HDMI_R_D1-
R1562 1
HDMI_R_D1+
R1563 1
HDMI_R_D0-
R1564 1
HDMI_R_D0+
R1565 1
HDMI_R_D2+
R1566 1
HDMI_R_D2-
R1567 1
1
2
R402 0_0402_5% HDMI@
1
2
R253 0_0402_5% HDMI@
VGA_DVI_TXCVGA_DVI_TXD2VGA_DVI_TXD1VGA_DVI_TXD0-
1
2
R412 0_0402_5% HDMI@
1
2
R414 0_0402_5% HDMI@
VGA_DVI_TXC+
VGA_DVI_TXD2+
VGA_DVI_TXD1+
VGA_DVI_TXD0+
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
HDMI@
2 680_0402_5%
2 680_0402_5%
JHDMI
HDMI_HPD
2 680_0402_5%
+HDMI_5V_OUT
2 680_0402_5%
HDMI_SDATA
HDMI_SCLK
2 680_0402_5%
2 680_0402_5%
HDMI_R_CK-
2 680_0402_5%
HDMI_R_CK+
HDMI_R_D0-
2
G
HDMI Connector
Intel spec suggest

to use 680 ohm
2 680_0402_5%
+3VS
2
G
C869
@
0.1U_0402_16V4Z
1
HDMI_SDATA
R1530
2
1
1K_0402_5%
ASM1442 QFN 48P HDMI SHIFTER_QFN48_7X7

@
EMI DEMAND
21
21
21
21
ANALOG1(REXT)
e
t
o
N
0.1U_0402_16V4Z
1
5
12
18
24
27
31
36
37
43
FUNCTION1
FUCNTION2
10
HDMI_R_D2+
C729
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C730
C731
C732
@
1
2
R705 2.2K_0402_5%
VGA_DVI_TXC+
VGA_DVI_TXC-
+3VS
SDA_SINK
29
@
2
HDMI_SCLK
1
1
L12
1
28
2
2
+5VL
SCL_SINK
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VGA_DVI_TXD1-
HDMI_R_D0+
10K_0402_5% R409
2
1
@
25
G S
2
VGA_DVI_TXD0+
WCM-2012-121T_0805
@
1
2 R236
0_0402_5%
2
11
15
21
26
33
40
46
OE
OE*
VGA_HDMI_HPD 21
U10
+3VS
2 R237
0_0402_5%
HDMI@
2 2
OE#
1
L15
1
VGA_DVI_TXD0-
HDMI_R_CK+
R573
100K_0402_5%
HDMI@
VGA_DVI_TXC+
2N7002_SOT23-3
Q16 HDMI@
1
HDMI_HPD_R
1.1A_6V_MINISMDC110F-2
F2 HDMI@
2
1
+HDMI_5V_OUT
1
C308
HDMI@
0.1U_0402_16V4Z
2
HDMI@
1
WCM-2012-121T_0805
@
1
2 R227
0_0402_5%
40mil
1
@
RB161M-20_SOD123-2 D53
2
+5VS
R1568
1M_0402_5%
HDMI@
RB161M-20_SOD123-2 D32
2
+5VL
HDMI_R_CK-
1
1
2 R225
0_0402_5%
HDMI@
2 2
2
2
L14
1
VGA_DVI_TXC-
Q15
2N7002_SOT23-3
HDMI@
HDMI_R_D0+
HDMI_R_D1-
1
2
R704 HDMI@ 100K_0402_5%
HDMI_R_D1+
HDMI_R_D2-
C309
0.1U_0402_16V4Z
HDMI@
HDMI_R_D2+
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
20
21
22
23
SUYIN_100042MR019S153ZL
CONN@
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet

1
17
of
45
PCH_RTCX1
HIntegrated VRM enable

LIntegrated VRM disable
(INTVRMEN should always be pull high.)

3
HDA_SDO
D20
RTCRST#
PCH_SRTCRST#
G22
SRTCRST#
SM_INTRUDER#
K22
INTRUDER#
PCH_INTVRMEN
C17
INTVRMEN
HDA_BIT_CLK
N34
HDA_BCLK
HDA_SYNC
L34
HDA_SYNC
HDA_SPKR
T10
SPKR
HDA_RST#
K34
HDA_RST#
HDA_SDIN0
HDA_SDIN0
R438
1M_0402_5%
HDA_SDOUT
ME debug mode,this signal has a weak internal PD

Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
R189
51_0402_5%
2
1
+3VALW_PCH
R181
1 1K_0402_5% HDA_SYNC
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by

1.5V when smapled high
Prevent back drive issue.
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
R184
33_0402_5%
1
2 HDA_BIT_CLK
R186
33_0402_5%
HDA_SYNC_R
1
2
R190
33_0402_5%
1
2 HDA_RST#
R191
33_0402_5%
1
2 HDA_SDOUT
31 HDA_BITCLK_AUDIO
31 HDA_SYNC_AUDIO
B
31 HDA_RST_AUDIO#
31 HDA_SDOUT_AUDIO
PCH_JTAG_TCK
E34
HDA_SDIN0
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
H7
PCH_JTAG_TDI
K5
JTAG_TDI
PCH_JTAG_TDO
H1
JTAG_TDO
JTAG_TMS
e
t
o
N
28 PCH_SPI_MOSI
28 PCH_SPI_MISO
LPC_FRAME#
E36
K36
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AM3
AM1
AP7
AP5
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AM10
AM8
AP11
AP10
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AD7
AD5
AH5
AH4
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AB8
AB10
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
Y7
Y5
AD3
AD1
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
Y3
Y1
AB3
AB1
SATAICOMPO
Y11
SATAICOMPI
Y10
SERIRQ
33
SATA_PRX_C_DTX_N0 27
SATA_PRX_C_DTX_P0 27
SATA_PTX_DRX_N0 27
SATA_PTX_DRX_P0 27
NB HDD
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
s
e
.
SATA_PTX_DRX_N2 27
SATA_PTX_DRX_P2 27
e
s
r
e
niv
NB ODD
R192
37.4_0402_1%
1
2
SATA_COMP
SATA3RCOMPO
AB12
SATA3COMPI
AB13
SATA3RBIAS
AH1
RBIAS_SATA3
SATA3_COMP
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
P3
SATA_LED#
PCH_SPI_MOSI
V4
SPI_MOSI
SATA0GP / GPIO21
V14
PCH_GPIO21
PCH_SPI_MISO
U3
SPI_MISO
SATA1GP / GPIO19
P1
BBS_BIT0_R
SATALED#
33
33
33
33
LPC_FRAME# 33
V5
T3
PCH_SPI_CS0#
28 PCH_SPI_CS0#
D36
LDRQ0#
LDRQ1# / GPIO23
U
k
o
o
b
JTAG_TCK
PCH_JTAG_TMS
PCH_SPI_CLK
28 PCH_SPI_CLK
FWH4 / LFRAME#
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
SERIRQ
G34
HDA_SDO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC
PCH_RTCRST#
HDA_SDOUT
31
@ R179
1K_0402_5%
2
1
R178
0_0402_5%
2
1
HDA_SPKR
@R188
@
R188
0_0402_5%
HIGH= Enable ( No Reboot )

LOW= Disable (Default)
+3VALW_PCH
33
HDA_SYNC_R
HDA_SPKR
2 1K_0402_5%
RTCX2
31
@
Q10
BSS138_NL_SOT23-3
1
+3VS
R176 1
+3VS
C20
C38
A38
B37
C37
SATA 6G
C227
1U_0603_10V4Z
INTVRMEN
RTCX1
PCH_RTCX2
SATA
PCH_INTVRMEN
2 330K_0402_5%
A20
RTC
SM_INTRUDER#
JME1
SHORT PADS
R171 1
C226
1U_0603_10V4Z
1
2
R177 20K_0402_5%
1
2
R180 20K_0402_5%
U4A
PCH_RTCX1
IHDA
2 1M_0402_5%
JTAG
+RTCVCC
SPI
R170 1
CMOS
+RTCVCC
C225
18P_0402_50V8J
4
OSC
OSC
NC
NC
JCMOS1
SHORT PADS
18P_0402_50V8J
C224
32.768KHZ_12.5PF_Q13MC14610002
Y2
PCH_RTCX2
2
10M_0402_5%
1
R151
R200
R195
49.9_0402_1%
1
2
1
+1.05VS_VCC_SATA
+1.05VS_SATA3
+3VS
BBS_BIT0_R
R193
1 10K_0402_5%
SERIRQ
R174
1 10K_0402_5%
SATA_LED#
R175
1 10K_0402_5%
PCH_GPIO21
@ R205
1 10K_0402_5%
R207
1 10K_0402_5%
+3VS
2
750_0402_1%
SATA_LED# 34
XDP Connector
COUGARPOINT_FCBGA989~D
@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
20,33 PCH_RSMRST#
20,33 PBTN_OUT#
PCH_JTAG_TDI
+1.05VS_VCCP
R399
0_0402_5%
2
1
1
2
@ R264 0_0402_5%
XDP_RSMRST#
XDP_HOOK1
1
2
@ R398 0_0402_5%
+3VS
R203
100_0402_1%
XDP_DBRESET#
5,20 XDP_DBRESET#
PCH_JTAG_TDO
R202
100_0402_1%
2
R201
100_0402_1%
R199
200_0402_5%
PCH_JTAG_TMS
PCH_JTAG_TDO
R198
200_0402_5%
2
R197
200_0402_5%
2
+3VALW_PCH
+3VALW_PCH
+3VALW_PCH
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTAG_TCK
trace width 10mil
W=20mils
+RTCBATT
+CHGRTC
W=20mils
+RTCVCC
27
28
ACES_87152-26051
D1
R209
1K_0402_5%
2
1
JPXDP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 G1
26 G2
2
1
3
BAS40-04_SOT23-3
C230
1U_0603_10V4Z
Place CH7 close to PCH.
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
18
of
45
+3VALW_PCH
U4B
+3VS
R218
R220
1 10K_0402_5%
CLKREQ_WLAN#
1 10K_0402_5%
PCH_GPIO20
1 10K_0402_5%
PCH_GPIO73
+3VALW_PCH
R224
R226
1 10K_0402_5%
CLKREQ_LAN#
R228
1 10K_0402_5%
PCH_GPIO26
R229
1 10K_0402_5%
PCH_GPIO44
R230
1 10K_0402_5%
PCH_GPIO45
R231
1 10K_0402_5%
PCH_GPIO46
R235
1 10K_0402_5%
PCH_GPIO56
BE34
BF34
BB32
AY32
PERN2
PERP2
PETN2
PETP2
BG36
BJ36
AV34
AU34
PERN3
PERP3
PETN3
PETP3
BF36
BE36
AY34
BB34
PERN4
PERP4
PETN4
PETP4
BG37
BH37
AY36
BB36
PERN5
PERP5
PETN5
PETP5
BJ38
BG38
AU36
AV36
PERN6
PERP6
PETN6
PETP6
BG40
BJ40
AY40
BB40
PERN7
PERP7
PETN7
PETP7
BE38
BC38
AW38
AY38
PERN8
PERP8
PETN8
PETP8
Y40
Y39
C
PCH_GPIO73
R152 1
R1212 1
29 CLK_WLAN#
29 CLK_WLAN
WLAN
2 0_0402_5%
2 0_0402_5%
CLK_R_WLAN#
CLK_R_WLAN
CLKREQ_WLAN#
29 CLKREQ_WLAN#
PCH_GPIO20
30 CLK_LAN#
30 CLK_LAN
LAN
2 0_0402_5%
2 0_0402_5%
CLK_R_LAN#
CLK_R_LAN
AB49
AB47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
M1
t
o
N
PCH_GPIO44
L14
AB42
AB40
PCH_GPIO56
PCH_GPIO45
PCH_GPIO46
8 CLK_RES_ITP#
8 CLK_RES_ITP
R258
R260
2
2
@
@
1 0_0402_5% CLK_BCLK_ITP#
1 0_0402_5% CLK_BCLK_ITP
E6
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
E14
PCH_SML1CLK
SML1DATA / GPIO75
M16
PCH_SML1DATA
CL_RST1#
P10
PEG_A_CLKRQ# / GPIO47
M10
V38
V37
CLKOUT_PCIE7N
CLKOUT_PCIE7P
10K_0402_5%
DRAMRST_CNTRL_PCH
R211
1K_0402_5%
PCH_SMBCLK
R212
2.2K_0402_5%
PCH_SMBDATA
R213
2.2K_0402_5%
PCH_GPIO74
R214
10K_0402_5%
PCH_SML1CLK
R215
2.2K_0402_5%
PCH_SML1DATA
R216
2.2K_0402_5%
PCH_GPIO47
R217
10K_0402_5%
PCH_SML0CLK
R242
2.2K_0402_5%
PCH_SML0DATA
R244
2.2K_0402_5%
PCH_SML1CLK
PCH_SML1DATA 3
s
e
.
PCH_GPIO47
e
s
r
e
niv
CLKOUT_DMI_N
CLKOUT_DMI_P
AB37
AB38
CLK_CPU_DMI#
CLK_CPU_DMI
AV22
AU22
CLK_CPU_DMI# 5
CLK_CPU_DMI 5
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM12
AM13
CLKIN_DMI_N
CLKIN_DMI_P
U
k
o
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLKIN_DMI2_N
CLKIN_DMI2_P
BJ30
BG30
CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DOT_96N
CLKIN_DOT_96P
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
AK7
AK5
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
REFCLK14IN
K45
CLK_BUF_ICH_14M
CLKIN_PCILOOPBACK
H45
CLK_PCI_LPBACK
XTAL25_IN
XTAL25_OUT
V47
V49
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
Y47
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
K43
CLK_FKEX0
T70
PAD
F47
CLK_FKEX1
T69
PAD
H47
CLK_FKEX2 R299
K49
CLK_FKEX3
CLK_BUF_CPU_DMI# 14
CLK_BUF_CPU_DMI 14
Q11A
2N7002DW-T/R7_SOT363-6
EC_SMB_CK2
1
EC_SMB_CK2 33
Q11B
2N7002DW-T/R7_SOT363-6
EC_SMB_DA2
4
EC_SMB_DA2 33
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R238
R239
1
1
2
2
10K_0402_5%
10K_0402_5%
CLKIN_DMI2#
CLKIN_DMI2
R241
R243
1
1
2
2
10K_0402_5%
10K_0402_5%
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R245
R246
1
1
2
2
10K_0402_5%
10K_0402_5%
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
R248
R250
1
1
2
2
10K_0402_5%
10K_0402_5%
CLK_BUF_ICH_14M
R252
10K_0402_5%
CLK_BUF_DREF_96M# 14
CLK_BUF_DREF_96M 14
CLK_BUF_PCIE_SATA# 14
CLK_BUF_PCIE_SATA 14
XTAL25_IN
CLK_BUF_ICH_14M 14
XTAL25_OUT
1
R255
CLK_PCI_LPBACK 22
2
1M_0402_5%
Y3
R256
90.9_0402_1%
1
2
PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCH_GPIO74
M7
CL_DATA1
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
T13
AK14
AK13
SML1CLK / GPIO58
V40
V42
K12
C13
T11
R210
PCH_SML0DATA
SML1ALERT# / PCHHOT# / GPIO74
o
b
e
CLKOUT_PCIE4N
CLKOUT_PCIE4P
DRAMRST_CNTRL_PCH 7
LID_SW#_R
PCH_SML0CLK
C8
G12
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCH_SMBDATA 12
A12 DRAMRST_CNTRL_PCH
SML0DATA
CL_CLK1
LID_SW_OUT# 33
PCH_SMBCLK 12
PCH_SMBDATA
C9
1 0_0402_5%
+3VS
Y37
Y36
V45
V46
SML0CLK
CLKOUT_PCIE2N
CLKOUT_PCIE2P
V10
L12
SML0ALERT# / GPIO60
Y43
Y45
PCH_GPIO26
PCH_SMBCLK
SMBDATA
A8
30 CLKREQ_LAN#
H14
CLKOUT_PCIE0N
CLKOUT_PCIE0P
J2
AA48
AA47
R1213 1
R1214 1
SMBCLK
R267
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
LID_SW#_R
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
SMBUS
C231 1
C229 1
SMBALERT# / GPIO11
E12
Link
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
Controller
29
29
29
29
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
PERN1
PERP1
PETN1
PETP1
FLEX CLOCKS
C223 1
C228 1
BG34
BJ34
AV32
AU32
CLOCKS
WLAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
PCI-E*
LAN
30
30
30
30
+1.05VS_VCCDIFFCLKN
2 0_0402_5%
1
T71
CLK_48M_CR 32
C239
18P_0402_50V8J
CLK_BUF_ICH_14M
PAD
25MHZ_20PF_7A25000012 1
@ R265
33_0402_5%
2
1
C240
18P_0402_50V8J
@ C241
22P_0402_50V8J
1
2
Reserve for EMI please close to UH4
@
CLK_PCI_LPBACK
@ R269
33_0402_5%
2
1
@ C242
22P_0402_50V8J
1
2
Reserve for EMI please close to UH4
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
19
of
45
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
BC24
BE20
BG18
BG20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
6
6
6
6
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
6
6
6
6
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
6
6
6
6
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
+1.05VS_PCH
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%
1
R274
1
R275
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
FDI
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
U4C
6
6
6
6
5,18 XDP_DBRESET#
IN2
GND
14,33,44 VGATE
IN1
PM_PWROK
U6
VCC
R287
OUT
R285
33 PCH_APWROK
R286
SYS_PWROK 5
5 PM_DRAM_PWRGD
MC74VHC1G08DFT2G_SC70-5
R303 2
1 10K_0402_5%
SYS_PWROK
1 10K_0402_5%
33
PM_PWROK
0621
SUSACK#_R
SUSWARN#_R
1
R290
SUSWARN#
1
R291
18,33 PBTN_OUT#
33,37
R283
0_0402_5%
2
1
@
R288
ACIN
D2
C12
SUSACK#
K3
P12
2
0_0402_5%
PM_PWROK_R L22
2
0_0402_5%
U
k
o
o
b
e
t
o
N
18,33 PCH_RSMRST#
R276
2 PCH_DBRESET#_R
0_0402_5%
R280
SYS_PWROK
+3VS
33 PM_PWROK
2 SUSACK#_R
0_0402_5%
R278
APWROK
0_0402_5%
PM_DRAM_PWRGD
L10
B13
PCH_RSMRST#_R
2
0_0402_5%
C21
SUSWARN#_R
0_0402_5%
K16
PBTN_OUT#_R
2
0_0402_5%
E20
System Power Management
SUSACK#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
6
6
6
6
6
6
6
6
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
6
6
6
6
6
6
6
6
FDI_INT
AW16
FDI_INT
FDI_FSYNC0
AV12
FDI_FSYNC0
FDI_FSYNC1
BC10
FDI_FSYNC1
FDI_LSYNC0
AV14
FDI_LSYNC0
FDI_LSYNC1
BB10
FDI_LSYNC1
DSWVRMEN
A18
DPWROK
E22
WAKE#
DSWODVREN
B9
CLKRUN# / GPIO32
N3
PCH_GPIO32
SUS_STAT# / GPIO61
G8
SUS_STAT#
N14
SUSCLK_R 1
2
R306 0_0402_5%
SUSCLK / GPIO62
PM_SLP_S5#
SLP_S4#
H4
PM_SLP_S4#
SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#
F4
PM_SLP_S3#
PWRBTN#
G10
RSMRST#
SLP_S5# / GPIO63
SLP_A#
PCH_ACIN
2
CH751H-40PT_SOD323-2
H20
PCH_GPIO72
E10
BATLOW# / GPIO72
RI#
A10
RI#
ACPRESENT / GPIO31
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
SLP_SUS#
G16
PM_SLP_SUS#
PMSYNCH
AP14
H_PM_SYNC
K14
PCH_GPIO29
SLP_LAN# / GPIO29
DSWODVREN
R272
R273
1 330K_0402_5%
@
1 330K_0402_5%
DSWODVREN - On Die DSW VR Enable

HEnable
LDisable
@ R277
0_0402_5%
2 PCH_RSMRST#_R
WAKE#
PCH_GPIO29
PCH_PCIE_WAKE# 29,30
SUSCLK
T12
PAD
T13
PAD
T14
PAD
T15
PAD
+3VALW_PCH
PCH_DPWROK 33
R281
0_0402_5%
1
2
D10
DRAMPWROK
s
e
.
FDI_FSYNC0
PCH_DPWROK
WAKE#
+RTCVCC
FDI_INT 6
e
s
r
e
niv
4mil width and place

within 500mil of the PCH
33
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
R279
R282
2 10K_0402_5%
@
2 10K_0402_5%
R1192
1
100K_0402_5%
2
1
2
+3VS
@C316
@
C316
22P_0402_50V8J
R305
@
1
2 8.2K_0402_5%
PCH_GPIO32
R284
1 10K_0402_5%
SUSCLK 33
PM_SLP_S5# 33
PM_SLP_S4# 33
PM_SLP_S3# 33
T16
PAD
T17
PAD
Can be left NC
when IAMT is not
support on the
platfrom
PM_SLP_SUS# 33
H_PM_SYNC 5
@
+3VALW_PCH
R289
1 200_0402_5%
PM_DRAM_PWRGD
R292
1 10K_0402_5%
SUSWARN#
R293
1 330K_0402_5%
PCH_ACIN
R294
1 10K_0402_5%
PCH_GPIO72
R295
1 10K_0402_5%
RI#
R296
1 10K_0402_5%
PCH_RSMRST#
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
20
of
45
ENBKL
ENBKL
R297
1 0_0402_5%
IGPU_BKLT_EN
2
33
R298
100K_0402_5%
Pull high at LVDS conn side.

U4D
CTRL_CLK
L_BKLTEN
L_VDD_EN
2 2.2K_0402_5%
CTRL_DATA
15 PCH_BL_PWM
P45
L_BKLTCTL
15 LCD_EDID_CLK
15 LCD_EDID_DATA
T40
K47
L_DDC_CLK
L_DDC_DATA
T45
P39
L_CTRL_CLK
L_CTRL_DATA
CTRL_CLK
CTRL_DATA
2.37K_0402_1%
2
1
RH244
RH290
15 LCD_TXCLK15 LCD_TXCLK+
+3VS
RH291
2 2.2K_0402_5%
VGA_CRT_CLK
RH292
2 2.2K_0402_5%
VGA_CRT_DATA
RH131
0_0402_5%
2
1
2 150_0402_1%
15 LCD_TXOUT015 LCD_TXOUT115 LCD_TXOUT2-
RH132
2 150_0402_1%
VGA_CRT_G
RH133
2 150_0402_1%
VGA_CRT_R
2 2.2K_0402_5%
LCD_EDID_CLK
R304
2 2.2K_0402_5%
LCD_EDID_DATA
LVD_IBG
LVD_VBG
AE48
AE47
LVD_VREFH
LVD_VREFL
LCD_TXCLKLCD_TXCLK+
AK39
AK40
LVDSA_CLK#
LVDSA_CLK
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
AN48
AM47
AK47
AJ48
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
AN47
AM49
AK49
AJ47
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
LVDSB_CLK#
LVDSB_CLK
e
t
o
N
16 VGA_CRT_B
16 VGA_CRT_G
16 VGA_CRT_R
16 VGA_CRT_CLK
16 VGA_CRT_DATA
2
R1250
AH45
AH47
AF49
AF45
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
VGA_CRT_B
VGA_CRT_G
VGA_CRT_R
N48
P49
T49
CRT_BLUE
CRT_GREEN
CRT_RED
VGA_CRT_CLK
VGA_CRT_DATA
T39
M40
CRT_DDC_CLK
CRT_DDC_DATA
VGA_CRT_HSYNC
VGA_CRT_VSYNC
16 VGA_CRT_HSYNC
16 VGA_CRT_VSYNC
1CRT_IREF
1K_0402_1%
SDVO_TVCLKINN
SDVO_TVCLKINP
AP43
AP45
SDVO_STALLN
SDVO_STALLP
AM42
AM40
SDVO_INTN
SDVO_INTP
AP39
AP40
SDVO_CTRLCLK
SDVO_CTRLDATA
SDVO_CTRLDATA strap pull high

at level shift page
P38
M39
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
AT49
AT47
AT40
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
VGA_HDMI_CLK 17
VGA_HDMI_DATA 17
s
e
.
e
s
r
e
niv
U
k
o
o
b
+3VS
R301
AF37
AF36
LVD_VREF
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
15 LCD_TXOUT0+
15 LCD_TXOUT1+
15 LCD_TXOUT2+
VGA_CRT_B
LVDS_IBG
M47
M49
T43
T42
Digital Display Interface
R302
2 2.2K_0402_5%
PCH_ENVDD
LVDS
R300
J47
M45
15
DDPC_CTRLCLK
DDPC_CTRLDATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
P46
P42
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
AP47
AP49
AT38
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
IGPU_BKLT_EN
+3VS
R1475
100K_0402_5%
2
1
@
R1476
100K_0402_5%
2
1
@
VGA_HDMI_HPD 17
17
17
17
17
17
17
17
17
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
M43
M36
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
AT45
AT43
BH41
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
21
of
45
PCH_GPIO55
PCI_GNT1#
PCH_GPIO5
PCI_GNT2#
1
2
3
4
8.2K_0804_8P4R_5%
RP2
8
7
6
5
PCH_GPIO2
PCI_REQ3#
PCH_GPIO4
ODD_DA#
1
2
3
4
B21
M20
AY16
BG46
TP21
TP22
TP23
TP24
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
8.2K_0804_8P4R_5%
R310
2 8.2K_0402_5%
R311
R312
2 8.2K_0402_5%
2 8.2K_0402_5%
PCI_REQ2#
PCI_REQ1#
R112 100K_0402_5%
1
2
5,29,30,33 PLT_RST#
19 CLK_PCI_LPBACK
33 CLK_PCI_LPC
PLT_RST#
CLK_PCI_LPBACK
CLK_PCI_LPC
ODD_DA#
PAD
R316
R317
T18 @
2
1
PAD
PAD
PAD
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
C46
C44
E40
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
PCI_GNT1#
PCI_GNT2#
PCH_GPIO55
D47
E42
F46
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
1 22_0402_5%
2 22_0402_5%
T19 @
T20 @
T21 @
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
H49
H43
J48
K42
H40
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AY1
NV_RB#
AT8
AY5
BA2
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
NV_CLE
AV10
NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1
K40
K38
H38
G38
C6
AT10
BC8
NV_RCOMP
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K10
NV_DQS0
NV_DQS1
NV_ALE
NV_CLE
DMI Termination Voltage
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USBRBIAS#
C33
USBRBIAS
B33
29
29
29
29
29
29
NV_CLE
Set to Vss when LOW
+VCCPNAND
e
s
r
USB20_N10
USB20_P10
USB20_N11
USB20_P11
R-CONN
L-CONN
NV_CLE
2
R314
1
1K_0402_5%
15
15
32
32
USB20_N13 29
USB20_P13 29
RP4
Camera
USB_OC5#
Card Reader
4
3
2
1
USB_OC7#
USB_OC0#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
5
6
7
8
10K_1206_8P4R_5%
BT
Within 500 mils

1
R315
2
22.6_0402_1%
RP5
USB_OC6#
4
3
2
1
USB_OC1#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
H_SNB_IVB# 5
CLOSE TO THE BRANCHING POINT
PME#
PLTRST#
R313
2.2K_0402_5%
R-CONN
+3VALW_PCH
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N13
USB20_P13
USBRBIAS
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
Set to Vcc when HIGH
s
e
.
AT12
BF3
e
v
ni
U
k
o
o
b
te
o
N
27
AY7
AV7
AU3
BG4
RP3
8
7
6
5
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
USB
8.2K_0804_8P4R_5%
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
RSVD
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
1
2
3
4
PCI
RP1
8
7
6
5
NVRAM
U4E
+3VS
USB_OC0#
USB_OC1#
PROJECT_ID0
PROJECT_ID1
PROJECT_ID2
USB_OC5#
USB_OC6#
USB_OC7#
A14
K20
B17
C16
L16
A16
D14
C14
USB_OC0# 29
USB_OC1# 29
5
6
7
8
10K_1206_8P4R_5%
+3VALW_PCH
@
PROJECT_ID0
@
1
2
0_0402_5% R333
1
2
0_0402_5% R352
PROJECT_ID1
1
2
0_0402_5% R400
@
1
2
0_0402_5% R401
PROJECT_ID2 PROJECT_ID1 PROJECT_ID0
PROJECT_ID2
Boot BIOS Strap bit1 BBS1

Bit11
A
BBS bit1
/BBS bit0
Bit10
1
0_0402_5%
1
0_0402_5%
PBL10
@ 2
R348
2
R354
PBL11
Boot BIOS
Destination
PCI
SPI
LPC
Reserved
*
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
22
of
45
GPIO8
Integrated Clock Chip Enable

+3VALW_PCH
H ; Disable
L ; Enable
R437 1
R327
2 10K_0402_5%
@
2 1K_0402_5%
EC_SMI#
Reserve for ICC

enable.
GPIO28
On-Die PLL Voltage Regulator

This signal has a weak internal pull up
HOn-Die voltage regulator enable

LOn-Die PLL Voltage Regulator disable
+3VS
+3VALW_PCH
KB_RST#
PCH_GPIO28
U4F
PCH_GPIO27 (Have internal Pull-High)

VCCVRM VR Enable
*High:
Low: VCCVRM VR Disable
PCH_GPIO0
T7
PCH_GPIO1
2 10K_0402_5%
R332
PCH_GPIO37
ODD_EN#
C41
PCH_GPIO70
@T25
@
T25
PAD
+3VS
TACH7 / GPIO71
A40
PCH_GPIO71
@T22
@
T22
PAD
33
EC_SMI#
EC_SMI#
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
PCH_GPIO15
G2
GPIO15
U2
D40
T5
SCLOCK / GPIO22
E8
GPIO24 / MEM_LED
2 10K_0402_5%
PCH_GPIO24
2 10K_0402_5%
PCH_GPIO27
PCH_GPIO34
o
b
e
ODD_DETECT#
PCH_GPIO37
CE_EN
PCH_GPIO39
PCH_GPIO48
TACH0 / GPIO17
PECI
RCIN#
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
N2
SLOAD / GPIO38
SDATAOUT0 / GPIO39
V13
AU16
PCH_PECI_R
P5
KB_RST#
AY11
THRMTRIP#
AY10
INIT3_3V#
1
0_0402_5%
PCH_THRMTRIP#_R 1
R334
T14
NC_1
AH8
NC_2
AK11
NC_3
AH10
NC_4
AK10
NC_5
P37
SATA3GP / GPIO37
M3
P4
PROCPWRGD
U
k
o
PCH_GPIO28
t
o
N
SATA4GP / GPIO16
PCH_GPIO22
R439 1
CE_EN
A20GATE
PCH_GPIO17
R425 1
15
e
s
r
e
niv
PCH_GPIO12
+3VS
SDATAOUT1 / GPIO48
VSS_NCTF_15
BG2
@T26
@
T26
PAD
PCH_GPIO49
V3
SATA5GP / GPIO49
VSS_NCTF_16
BG48
@T27
@
T27
PAD
PCH_GPIO57
D6
GPIO57
VSS_NCTF_17
BH3
@T28
@
T28
PAD
VSS_NCTF_18
BH47
@T29
@
T29
PAD
PAD
T30 @
A4
VSS_NCTF_1
VSS_NCTF_19
BJ4
@T31
@
T31
PAD
PAD
T32 @
A44
VSS_NCTF_2
VSS_NCTF_20
BJ44
@T33
@
T33
PAD
PAD
T34 @
A45
VSS_NCTF_3
VSS_NCTF_21
BJ45
@T35
@
T35
PAD
VSS_NCTF_22
BJ46
@T37
@
T37
PAD
VSS_NCTF_23
BJ5
@T39
@
T39
PAD
2 10K_0402_5%
PCH_GPIO0
2 10K_0402_5%
PCH_GPIO1
R336
2 10K_0402_5%
PCH_GPIO6
R337
2 10K_0402_5%
PCH_GPIO16
R338
2 10K_0402_5%
PCH_GPIO17
PAD
T36 @
A46
VSS_NCTF_4
R339
2 10K_0402_5%
PCH_GPIO22
PAD
T38 @
A5
VSS_NCTF_5
R340
2 10K_0402_5%
CE_EN
PAD
T40 @
A6
VSS_NCTF_6
VSS_NCTF_24
BJ6
@T41
@
T41
PAD
R341
2 10K_0402_5%
PCH_GPIO39
PAD
T42 @
B3
VSS_NCTF_7
VSS_NCTF_25
C2
@T43
@
T43
PAD
R342
2 10K_0402_5%
ODD_DETECT#
PAD
T44 @
B47
VSS_NCTF_8
VSS_NCTF_26
C48
@T45
@
T45
PAD
R343
2 10K_0402_5%
PCH_GPIO34
PAD
T46 @
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
@T47
@
T47
PAD
R344
2 10K_0402_5%
PCH_GPIO48
PAD
T48 @
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
@T49
@
T49
PAD
R345
2 10K_0402_5%
PCH_GPIO49
PAD
T50 @
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
@T51
@
T51
PAD
PAD
T52 @
BE49
VSS_NCTF_12
VSS_NCTF_30
E49
@T53
@
T53
PAD
PAD
T54 @
BF1
VSS_NCTF_13
VSS_NCTF_31
F1
@T55
@
T55
PAD
PAD
T56 @
BF49
VSS_NCTF_14
VSS_NCTF_32
F49
@T57
@
T57
PAD
2 10K_0402_5%
PCH_GPIO12
R347
2 1K_0402_5%
PCH_GPIO15
R349
R435
2 10K_0402_5%
PCH_GPIO57
2 10K_0402_5%
IGPU/DGPU MODE SELECT
5,33
KB_RST# 33
H_CPUPWRGD
H_THRMTRIP#
2
390_0402_5%
H_THRMTRIP# 5
INIT3_3V
This signal has weak internal

PU, can't pull low
C311
330P_0402_50V7K
@
Compal Secret Data
PCH_GPIO35
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
CLOSE TO PCH, EMI DEMAND
2 10K_0402_5%
H_PECI
GATEA20 33
Issued Date
R350@ 1
NCTF
2
R331
R329
10K_0402_5%
R335
R346
ODD_EN# 27
Intel schematic reviwe recommand.
R424
+3VALW_PCH
s
e
.
TACH6 / GPIO70
TACH3 / GPIO7
PCH_GPIO35
B41
TACH2 / GPIO6
27 ODD_DETECT#
+3VS
TACH5 / GPIO69
E38
1 100K_0402_5%
TACH1 / GPIO1
H36
+3VALW_PCH
PAD
A42
2 10K_0402_5%
2 10K_0402_5%
EC_SCI#
PCH_GPIO37
2 10K_0402_5%
@T24
@
T24
PCH_GPIO68
PCH_GPIO6
PCH_GPIO16
R426@ 1
PCH_GPIO69
C40
EC_SCI#
PCH_GPIO27
+3VS
R436 1
TACH4 / GPIO68
33
R328
+3VS
BMBUSY# / GPIO0
2 1K_0402_5%
R325
R326
2 10K_0402_5%
CPU/MISC
GPIO
R351
Sheet

1
23
of
45
+1.05VS_VCCP
+1.05VS_VCCDPLLEXP
AN19
VSSALVDS
AK37
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
60mA VCCTX_LVDS[3]
AP36
VCCTX_LVDS[4]
AP37
+VCCA_LVDS
AN17
+1.05VS_VCCP
C
+1.05VS_VCC_EXP
R359
0_0805_5%
1
2
+VCCAFDI_VRM
Place C264 Near BG6 pin
@ C264
1U_0402_6.3V6K
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
+1.05VS_PCH
VCCIO[26]
R363
AP16
BG6
+VCCP_VCCDMI
AU20
C251
0.01U_0402_16V7K
V33
VCC3_3[7]
V34
2
VCCVRM[3]
VCCDMI[1]
20mA
VCCIO[1]
+3VS
AT16
AT20
AB36
VCCFDIPLL
AG16
190mA VCCPNAND[2]
AG17
VCCPNAND[3]
AJ16
e
s
r
VCCPNAND[4]
AJ17
20mA VCCSPI
V1
C263
0.1U_0402_10V7K
C261
1U_0402_6.3V6K
+VCCPNAND
+1.05VS_PCH
e
v
i
R360
0_0805_5%
1
2
s
e
.
+1.05VS_VCCP
R357
0_0805_5%
1
2
+VCCP_VCCDMI
+1.05VS_VCC_DMI_CCI
0.001
V5REF_Sus
0.001
Vcc3_3
3.3
0.266
VccADAC
3.3
0.001
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.3
VccDMI
1.05
0.042
VccIO
1.05
2.925
VccASW
1.05
1.01
VccSPI
3.3
0.02
VccDSW
3.3
0.003
VccpNAND
1.8
0.19
VccRTC
3.3
6 uA
VccSus3_3
3.3
0.119
0.1uH inductor, 200mA
+VCCAFDI_VRM
R358
0_0805_5%
1
2
V5REF
C254
0.1U_0402_10V7K
n
U
k
o
o
b
VCCPNAND[1]
VCCVRM[2]
VCCDMI[2]
1
C252
0.01U_0402_16V7K
0.001
2
0_0805_5%
+VCCP_VCCDMI
VCC3_3[3]
VCCIO[27]
S0 Iccmax
Current (A)
+3VS
VCCIO[25]
AN34
1
2+1.05VS_VCCDPLL_FDI AP17
0_0805_5%
VCCIO[24]
AN33
BH29
VCC3_3[6]
2925mA
e
t
o
N
+1.05VS_VCCAPLL_FDI
1
1
VCCIO[16]
C262
0.1U_0402_10V7K
2
@R361
@
R361
0_0603_5%
2
VCCIO[15]
AN21
AT24
+3VS_VCCA3GBG
1
+1.05VS_PCH
C260
1U_0402_6.3V6K
C259
1U_0402_6.3V6K
+3VS
C258
1U_0402_6.3V6K
C257
1U_0402_6.3V6K
C256
10U_0603_6.3V6M
0624
HVCMOS
AN16
DMI
This pin can be left as no connect in

On-Die VR enabled mode (default).
1
R423
R355
0_0805_5%
+3VS_VCC3_3_6 1
2
VCCAPLLEXP
NAND / SPI
BJ22
VCCIO
+VCCAPLLEXP
T58 @
FDI
PAD
Voltage
1.05
V_PROC_IO
+1.8VS
L6
0.1UH_MLF1608DR10KT_10%_1608
2
1
+VCCTX_LVDS
1
VCCIO[28]
10U_0603_6.3V6M
1mA VCCALVDS
AK36
10U_0603_6.3V6M
CRT
LVDS
VCC CORE
C253
22U_0805_6.3V6M
1 0_0603_5%
U47
Voltage Rail
C310
R353
VSSADAC
+VCCADAC
1
C250
+1.05VS_PCH
VCCADAC
U48
C249
0.1U_0402_10V7K
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
1mA
C248
0.01U_0402_16V7K
C247
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C246
1U_0402_6.3V6K
C245
10U_0603_6.3V6M
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
PCH Power Rail Table
L5
MBK1608221YZF_2P
2
1
1300mA
+1.05VS_PCH
+3VS
POWER
U4G
R356
0_0805_5%
1
2
+1.8VS
C255
1U_0402_6.3V6K
VccSusHDA
3.3 / 1.5
0.01
VccVRM
1.8 / 1.5
0.16
VccCLKDMI
1.05
0.02
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.06
R362
0_0805_5%
1
2
+3V_VCCPSPI
+3VS
C265
1U_0402_6.3V6K
+VCCAFDI_VRM
+1.5VS
A
R364
0_0603_5%
0_0603_5%
+VCCAFDI_VRM
+1.8VS
R365
Intel recommand
stuff R364 and unstuff R365
VCCVRM==>1.5V FOR MOBILE

VCCVRM==>1.8V FOR DESKTOP
Compal Secret Data
Issued Date
VCCVRM = 160mA detal waiting for newest spec
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
24
of
45
Have internal VRM

+1.05VS_PCH @ R367
0_0603_5%
2
1
+1.05VS_VCCDIFFCLKN
C293
0.1U_0402_10V7K
+1.05VS_SSCVCC
+VCCAFDI_VRM
C297
1U_0402_6.3V6K
AA24
VCCASW[3]
AA26
VCCASW[4]
AA27
VCCASW[5]
AA29
VCCASW[6]
AA31
VCCASW[7]
AC26
VCCASW[8]
AC27
VCCASW[9]
AC29
VCCASW[10]
AC31
VCCASW[11]
VCCSUS3_3[10]
V24
VCCSUS3_3[6]
P24
VCCIO[34]
T26
1mA V5REF_SUS
M26
+PCH_V5REF_SUS
DCPSUS[4]
AN23
+VCCA_USBSUS
VCCSUS3_3[1]
AN24
+3V_VCCPSUS
1mA V5REF
P34
+PCH_V5REF_RUN
VCCSUS3_3[2]
N20
+3V_VCCPSUS
VCCSUS3_3[3]
N22
VCCSUS3_3[4]
P20
1010mA
VCCASW[12]
AD31
VCCASW[13]
W21
VCCASW[14]
W23
VCCASW[15]
W24
VCCASW[16]
W26
VCCASW[17]
W29
VCCASW[18]
W31
VCCASW[19]
W33
VCCASW[20]
N16
Y49
BD47
+1.05VS_VCCAUPLL
VCCVRM[4]
80mA
BF47
VCCADPLLB
+VCCDIFFCLK
AF17
AF33
AF34
AG34
VCCIO[7]
VCCIO[8]
55mA
VCCIO[9]
VCCIO[11]
AG33
VCC3_3[1]
P22
80mA
W16
T34
VCCIO[10]
AJ2
VCCIO[5]
AF13
VCCIO[12]
AH13
VCCIO[13]
AH14
VCCIO[6]
AF14
VCCVRM[1]
95mA
C279
+PCH_V5REF_SUS
+3VS_VCCPCORE
VCCIO[2]
AC16
VCCIO[3]
AC17
VCCIO[4]
AD17
R383
0_0805_5%
2
1
+VCC3_3_2
R385
0_0603_5%
2
1
+3VS
+PCH_V5REF_RUN
1
C284
1U_0603_10V6K
+3VS
C290
0.1U_0402_10V7K
2
+1.05VS_SATA3
+3VS
R384
0_0603_5%
1
D4
C285
0.1U_0402_10V7K
+3VS
R381
100_0402_5%
C283
1U_0402_6.3V4Z
+5VS
+3VALW_PCH
R380
0_0603_5%
2
1
+3VS_VCCPPCI
C291
0.1U_0402_10V7K
+1.05VS_PCH
R387
0_0805_5%
2
1
+1.05VS_SATA3
C292
1U_0402_6.3V6K
@
@
L11
R389
10UH_LB2012T100MR_20%
0_0805_5%
+VCCSATAPLL_R 2
1
2
1
+VCCSATAPLL
+VCCAFDI_VRM
AK1
AF11
s
e
.
C276
0.1U_0603_25V7K
2 1U_0402_6.3V6K
e
s
r
e
v
i
AA16
VCC3_3[4]
VCCAPLLSATA
D3
VCC3_3[8]
VCC3_3[2]
+1.05VS_VCCA_B_DPL
+1.05VS_SSCVCC
VCCSUS3_3[5]
+3VALW_PCH
R377
100_0402_5%
+1.05VS_PCH
R378
0_0603_5%
2
1
DCPRTC
VCCADPLLA
+5VALW_PCH
1
VCCASW[2]
+3VALW_PCH
R376
0_0603_5%
+3V_VCCAUBG 2
1
1
C274
0.1U_0402_10V7K
USB
VCCASW[1]
AA21
V23
35 PCH_PWR_EN#
+3VALW_PCH
R374
0_0603_5%
2
1
T24
VCCSUS3_3[9]
VCCSUS3_3[8]
+3V_VCCPUSB
+5VALW_PCH
T23
+1.05VS_VCCDIFFCLKN
119mA VCCSUS3_3[7]
n
U
k
o
o
b
+1.05VS_VCCA_A_DPL
C295
1U_0402_6.3V6K
DCPSUS[3]
AA19
AD29
+1.05VS_VCCDIFFCLKN
T29
C269
1U_0402_6.3V6K
+VCCRTCEXT
C294
1U_0402_6.3V6K
R390
0_0603_5%
2
1
+VCCAFDI_VRM
+1.05VS_VCC_SATA R391
+1.05VS_PCH
0_0805_5%
+1.05VS_VCC_SATA
2
1
1
+1.05VS_PCH
@ C296
10U_0603_6.3V6M
Place C296 Near AK1 pin
C298
1U_0402_6.3V6K
C299
0.1U_0402_10V7K
C300
1U_0402_6.3V6K
+VCCSST
V16
DCPSST
+1.05VM_VCCSUS
T17
V19
DCPSUS[1]
DCPSUS[2]
+1.05VS_PCH
+1.05VS_VCCP
R395
0_0603_5%
1
2
+V_CPU_IO
V_PROC_IO 1mA
T21
+VCCME_22
R393
1 0_0603_5%
VCCASW[23]
V21
+VCCME_23
R394
1 0_0603_5%
VCCASW[21]
T19
+VCCME_21
R396
1 0_0603_5%
10mA VCCSUSHDA
P32
+VCCSUSHDA
R397
1 0_0603_5%
+RTCVCC
+3VALW_PCH
A22
1
C306
0.1U_0402_10V7K
C305
0.1U_0402_10V7K
C304
1U_0402_6.3V6K
C303
0.1U_0402_10V7K
C302
0.1U_0402_10V7K
C301
4.7U_0603_6.3V6K
BJ8
VCCASW[22]
MISC
+1.05VM_VCCSUS
VCCRTC
HDA
@ R392
0_0603_5%
2
1
+1.05VM_VCCASW
1
e
t
o
N
+VCCDIFFCLK
+1.05VS_PCH
AL24
@
C275
1U_0402_6.3V6K
C282
1U_0402_6.3V6K
+1.05VS_PCH
VCCIO[14]
C289
1U_0402_6.3V6K
C287
220U_B2_2.5VM_R35
R388
0_0603_5%
2
1
C288
1U_0402_6.3V6K
+1.05VS_PCH
C286
220U_B2_2.5VM_R35
VCCAPLLDMI2
AL29
+1.05VS_VCCA_B_DPL
R386
0_0603_5%
2
1
BH23
+VCCDPLL_CPY
+1.05VS_VCCA_A_DPL
L10
10UH_LB2012T100MR_20%
+1.05VS_PCH
+VCCAPLL_CPY_PCH
C281
1U_0402_6.3V6K
L9
10UH_LB2012T100MR_20%
+VCCA_DPLL_L
1
2
C280
1U_0402_6.3V6K
VCCIO[33]
PCI/GPIO/LPC
add for 1.05vs_pch loading
VCC3_3[5]
VCCIO[32]
T27
SATA
+1.05VS_VCCP
2
+1.05VS_PCH
R382
0_0805_5%
1
2
T38
C278
22U_0805_6.3V6M
DCPSUSBYP
+3VS_VCC_CLKF33
C277
22U_0805_6.3V6M
R440
0_0805_5%
1
2
V12
Clock and Miscellaneous
2
+1.05VS_VCCP R379
0_0805_5%
1
2
P28
Q14
AO3413_SOT23-3
R373
20K_0402_5%
VCCIO[31]
3mA
VCCDSW3_3
+PCH_VCCDSW
+VCCSUS1
P26
R372
0_0603_5%
2
C271
0.1U_0402_10V7K
2 0_0603_5%
VCCIO[30]
+1.05VS_PCH
R369
0_0603_5%
2
1
+1.05VS_VCCUSBCORE
1
R375
+1.05VS_PCH
T16
N26
C268
0.1U_0402_10V7K
VCCIO[29]
VCCACLK
C273
0.1U_0402_10V7K
@ C272
10U_0603_6.3V6M
+1.05VS_PCH
AD49
@ L8
10UH_LB2012T100MR_20%
+VCCAPLL_CPY 1
2
1
POWER
U4J
+VCCPDSW
1
@ R368
0_0603_5%
2
1
C267
1U_0402_6.3V6K
C266
10U_0603_6.3V6M
R370
0_0603_5%
1
2
@
1
2
R433
+3VALW_PCH 0_0603_5%
C270
0.1U_0402_10V7K
2
1
@
+3VALW
+3VS_VCC_CLKF33
1
1
@ R371
@R371
0_0603_5%
1
2
VCCDMI = 42mA detal waiting for newest spec

+5VALW
L7
10UH_LB2012T100MR_20%
1
2
+1.05VS_PCH
VCC3_3 = 266mA detal waiting for newest spec

+VCCACLK
@ R366
0_0805_5%
2
CPU
RTC
+3VS
@
C307
0.1U_0402_16V4Z
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
25
of
45
U4I
U4H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
e
t
o
N
@
s
e
.
e
s
r
e
niv
U
k
o
o
b
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
@
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
26
of
45
SATA HDD1 Conn.

+5VS
1.2A
SATA ODD Conn
Place closely JP25 SATA CONN.
+5VS_ODD
1.7A
1
C387
10U_0805_10V4Z
C388
0.1U_0402_16V4Z
C389
0.1U_0402_16V4Z
C390
0.1U_0402_16V4Z
10U_0805_10V4Z
1
1
C952
C414
1
C416
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
10U_0805_10V4Z
C415
1
C417
0.1U_0402_16V4Z
C418
0.1U_0402_16V4Z
Place component's closely ODD CONN.
13.3" ODD
GND
A+
AGND
BB+
GND
24
23
GND
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C-H_13-22202201CP_22P
CONN@
SATA_PTX_C_DRX_P0 C512 1
SATA_PTX_C_DRX_N0C513 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P0 18
SATA_PTX_DRX_N0 18
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
C410 1
C412 1
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
e
s
r
e
niv
15
14
U
k
o
o
b
+5VS
GND
A+
AGND
BB+
GND
GND
GND
SATA_PTX_C_DRX_P2 C518 1
SATA_PTX_C_DRX_N2C519 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P2 18
SATA_PTX_DRX_N2 18
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD_DETECT#_R
0_0402_5%
R834
+5VS_ODD
R833
ODD_DETECT# 23
+5VS_ODD
ODD_DA# 22
+5VS_ODD
+5VS
@ R415
0_0805_5%
1
2
+VSB
1.7A
S
G
2
Q62
SI3456BDV-T1-E3 1N TSOP6
Q63
SSM3K7002FU_SC70-3
1
2
G
C870
0.1U_0402_16V4Z
R831
1.5M_0402_5%
ODD_EN
D
6
5
2
1
3
2
1
CS27
1U_0402_6.3V6K
R832
470K_0402_5%
ODD_EN#
0_0402_5%
SANTA_204901-1
CONN@
e
t
o
N
23
C424 1
C425 1
ODD_DA#_R
s
e
.
JODD
13.3" HDD
JHDD
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet

1
27
of
45
SPI ROM For Basic ME ROM size

(w/o Braidwood & system BIOS):
4MByte
D
+5VALW
+5VALW
+5VALW
+3VALW
@
C928
10P_0402_50V8J
U142B
@
O 7
D5 @
RB715F_SOT323-3
2
1
3
8
-
@
PCH_SPI_CLK 1
2
R1455 0_0402_5%
R419
10K_0402_5%
@
10,33,35,39,41,43 SUSP#
C397
LM393DG_SO8
0.1U_0402_16V4Z
@
+5VALW
LM393DG_SO8
C396
0.1U_0402_16V4Z
@
2 @
R46
1
10K_0402_5%
2 R1550
1 0_0402_5%
PCH_SPI_CLK
2 R1551
1 0_0402_5%
PCH_SPI_CS0#
2 R1552
1 0_0402_5%
2 R1553
1 0_0402_5%
e
t
o
N
PCH_SPI_MISO
18
18
18
18
PCH_SPI_MISO
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_MOSI
1OE#
2OE#
3OE#
4OE#
PCH_SPI_MISO
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_MOSI
2
5
9
12
1A
2A
3A
4A
+3VS
14
VCC
U59
1B
2B
3B
4B
GND
PCH_SPI_MOSI_R 5
3
6
8
11
PCH_SPI_CLK_R
EC_ON
PCH_SPI_CS0#_R 1
SN74CBT3125PWRG4_TSSOP14
C395
0.1U_0402_16V4Z
@
KSI3
KSI7
KSI6
KSI5
+3V_SPI
1
C394
@
1
4
10
13
1OE#
2OE#
3OE#
4OE#
2
5
9
12
1A
2A
3A
4A
14
VCC
+3V_SPI
U11 @
PCH_SPI_MISO_R
32,33
32,33
32,33
32,33
For EMI close U59
U7 @
1
4
10
13
33,34,38 EC_ON
e
s
r
e
niv
+3V_SPI
U
k
o
o
b
PCH_SPI_MOSI
s
e
.
Q19
AO3416_SOT23-3
@
R417
100K_0402_5%
1
10K_0402_5%
2
G
+5VALW
2 @
R45
R418
100K_0402_5%
@
U142A
@
O 1
8
EC_ON
2
100K_0402_5%
1
1 @
R434
R416
10K_0402_5%
@
0.1U_0402_16V4Z
+5VALW
@
C398
2
SO
GND
SI
SCLK
CS
HOLD
WP
VCC
MX25L3205AZMC-20G_SON8
C393
0.1U_0402_16V4Z
0915: P/N: SA000010Z00 & SA000021A00

1B
2B
3B
4B
GND
3
6
8
11
9/8 PVT change to 4MB for SW demand
R1549
7
+3VS
SN74CBT3125PWRG4_TSSOP14
+3V_SPI
0_0402_5%
0.1U_0402_16V4Z
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
28
of
45
Function Board
+5VALW
C756
0.1U_0402_16V4Z
@1
2
Left USB
+5VALW
C754
0.1U_0402_16V4Z
@
2
1
+USB_VCCB
1
2
3
4
U26
33
1
2
3
4
USB_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
USB_EN#
W=30mils
1
1 R427
RT9715BGS_SO8
W=60mils
+USB_VCCA
U25
2
0_0402_5%
C439
4.7U_0805_10V4Z
2 @
USB20_N0_R
USB20_P0_R
8
7
6
5
1
1 R422
RT9715BGS_SO8
USB20_N0 22
WCM2012F2SF-900T04_0805
@ R428 0_0402_5%
2
1
USB_OC1# 22
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
2
0_0402_5%
USB_OC0# 22
C438
4.7U_0805_10V4Z
2 @
+USB_VCCA
L17
USB20_N2_R
USB20_P2_R
USB20_N2_R
L16
2
2
2
USB20_P2_R
R421 0_0402_5%
1
2
3
4
GND
GND
GND
GND
USB20_N1 22
WCM2012F2SF-900T04_0805
@ R430 0_0402_5%
2
1
3
+5VALW
+1.5VS
2
47P_0402_50V8J
For SED request
CM20
USB20_P1_R
CM21
47P_0402_50V8J
For SED request
CM22
2
4.7U_0805_10V4Z
e
s
r
e
niv
+1.5VS
33
BT_PWRON
19 CLKREQ_WLAN#
19
19
CLK_WLAN#
CLK_WLAN
19 PCIE_PRX_WLANTX_N2
19 PCIE_PRX_WLANTX_P2
19 PCIE_PTX_C_WLANRX_N2
19 PCIE_PTX_C_WLANRX_P2
WLAN/ WiFi
+3VS
33
33
1
2
1R1430 0_0402_5%
2
R1431 0_0402_5%
E51_TXD
E51_RXD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
31
31
31
31
USB20_N1_R
USB20_P1_R
HP_L
HP_R
MIC1_L
MIC1_R
MIC1_L
MIC1_R
NBA_PLUG
MIC_SENSE
ACES_85201-2005N
CONN@
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+3VS
GND2
54
PLT_RST#
WL_OFF# 33
PLT_RST# 5,22,30,33
D_CK_SCLK 12,13,14
D_CK_SDATA 12,13,14
USB20_N13 22
USB20_P13 22
Bluetooth 2.0
53
Debug card using
31
USB20_N0_R
USB20_P0_R
JWLAN
2WLAN_WAKE
0_0402_5%
BT_PWRON
1
RH121
20,30 PCH_PCIE_WAKE#
C750
s
e
.
Ext.MIC/LINE IN JACK
U
k
o
o
b
HeadPhone/LINE Out JACK 31
USB20_P1 22
e
t
o
N
0.1U_0402_16V4Z
1
+3VS
2
4.7U_0805_10V4Z
Slot 1 Half PCIe Mini Card-WLAN & BT2.0
CM19
USB20_N1_R
@ R431 0_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C733
0.1U_0402_16V4Z
EMI DEMAND
C735
C734
C736
CM18
L25
2
CM17
DEMAND
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
W=60mils
@ EMI
EMI DEMAND
@
USB20_P2 22
USB20_P0 22
ACON_UAR4E-4K1920
CONN@
0.1U_0402_16V4Z
1
@ R429 0_0402_5%
0.1U_0402_16V4Z
JUSB3
1
2
3
4
5
6
7
8
0.1U_0402_16V4Z
+USB_VCCB
JFT
C747
2
USB20_N2 22
WCM2012F2SF-900T04_0805
R420 0_0402_5%
2
1
ACES_88910-5204
CONN@
100K_0402_5%
R1315
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet

E
29
of
45
UL1
CL1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1
22
HSOP
19 PCIE_PRX_C_LANTX_N1
CL2
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1
23
HSON
17
18
RL19
19 CLKREQ_LAN#
19
19
2PCH_PCIE_WAKE#
100K_0402_5%
HSIP
HSIN
EECS/SCL
EEDI/SDA
30
32
16
CLKREQB
PLT_RST#
25
PERSTB
CLK_LAN
CLK_LAN#
19
20
REFCLK_P
REFCLK_N
LAN_X1
1
2
4
5
7
8
10
11
43
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
CLK_LAN
CLK_LAN#
CKXTAL1
LAN_X2
44
CKXTAL2
13
29
41
28
DVDD10
DVDD10
DVDD10
+LAN_VDD10
PCH_PCIE_WAKE#
LANWAKEB
ISOLATEB
26
ISOLATEB
DVDD33
DVDD33
27
39
+3V_LAN
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
+3VS
1
1
RL3
31
37
40
0_0402_5% CLKREQ_R_LAN#
5,22,29,33 PLT_RST#
+3V_LAN
LED3/EEDO
LED1/EESK
LED0
PCIE_PTX_C_LANRX_P1
PCIE_PTX_C_LANRX_N1
19 PCIE_PTX_C_LANRX_P1
19 PCIE_PTX_C_LANRX_N1
RL6
1K_0402_1%
RTL8111E
RTL8105E
20,29 PCH_PCIE_WAKE#
NC
Pin15
NC
Pin38
1K ohm Pull-high
NC
Pin14
10K ohm PD
RL7
15K_0402_5%
+3V_LAN
RL21 2 8111E@ 1 10K_0402_5%

RL22 1
2 1K_0402_5%
ENSWREG
+LAN_VDDREG
33
ENSWREG
34
35
VDDREG
VDDREG
1
RL5
2
2.49K_0402_1%
46
24
49
RSET
GND
PGND
RL2 2
RL1 2
1 10K_0402_5%
1 10K_0402_5%
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
+LAN_VDD10
EVDD10
21
+LAN_EVDD10
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
+LAN_REGOUT
36
REGOUT
U
k
o
o
b
RL8
JUMP_43X79
@
CL840
4.7U_0805_10V4Z
@
B
CL841
1
1U_0402_6.3V4Z
2
CL10
2
CL4
1
2
0.1U_0402_16V4Z
CL5
1
2
0.1U_0402_16V4Z
CL6
1
2
0.1U_0402_16V4Z
CL7 8111E@
CL7 close to pin12
0.1U_0402_16V4Z
CL17
0.1U_0402_16V4Z
1
1
1
Close to Pin 3,6,9,13,29,41,45

+LAN_VDD10
+3V_LAN
+LAN_VDD10
2
0_0603_5%
1
LL3
CL28
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+LAN_VDDREG
CL29
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
2
CL19
2
CL20
2
CL21
2
CL22
2
CL23
2
CL24
2
CL25
8111E@
8111E@
8111E@
CL23,CL24,CL25 close to pin6,9,41, respectively
+3V_LAN
e
t
o
N
CL11
0.1U_0402_16V4Z
25MHZ_20PF_7A25000012
CL27
27P_0402_50V8J
UL5
24
23
22
LAN_MDI2LAN_MDI2+
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
LAN_MDI1LAN_MDI1+
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
LAN_MDI0LAN_MDI0+
10
11
12
MCT4
MX4+
MX4-
15
14
13
Place CL34 colse

to LAN chip
RJ45_MIDI3+
PR4+
RJ45_MIDI1-
PR2-
RJ45_MIDI2-
PR3-
RJ45_MIDI2+
CL39 1000P_0402_50V7K
2
1
1 8111E@ 2
8111E@
RL11
75_0402_1%
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
CL40 1000P_0402_50V7K
2
1
1 8111E@ 2
RL12
75_0402_1%
8111E@
CL41 1000P_0402_50V7K
2
1
1
2
RL13
75_0402_1%
CL42 1000P_0402_50V7K
2
1
1
2
RL15
75_0402_1%
RJ45_MIDI3RJ45_MIDI3+
PR1-
RJ45_MIDI0+
PR1+
SHLD4
12
SHLD3
11
PR4-
SHLD2
10
SHLD1
SANTA_130451-Y
CONN@
RJ45_GND
2 1000P_1808_3KV7K
1
CL36
LANGND
remove cl37,cl38 for emi
RJ45_GND
UL5
TCT4
TD4+
TD4-
RJ45_MIDI3-
8111E@
MCT1
MX1+
MX1-
8105E 10/100M
8105E@
JLAN
RL23
0_0402_5%
@
LAN_X2
TCT1
TD1+
TD1-
UL1
LAN Conn.
ENSWREG
YL1
LAN_X1
1
2
3
LAN_MDI3LAN_MDI3+
RL4
0_0402_5%
CL11 close to pin42
CL26
27P_0402_50V8J
2
For P/N and footprint

Please place them to ISPD page
CL9
0.1U_0402_16V4Z
Reserved For 1.05V Crystal
s
e
.
e
s
r
e
v
ni
60 mils
RL9
@ 0_0402_5%
PJ35
2
CL18
1U_0402_6.3V4Z
+3V_LAN
+3V_LAN
1
LL2
+3V_LAN
Close to Pin 27,39,12,47,48

2
+LAN_EVDD10
2
0_0603_5%
+3V_AVDDXTAL
0_0402_5%
+LAN_REGOUT
1
2
4.7UH_1008HC-472EJFS-A_5%_1008
Close to Pin 21
+3V_AVDDXTAL
+3V_LAN
+LAN_VDD10
LL1
0.1U_0402_16V4Z
+3VALW TO +3V_LAN
Vgs=-4.5V,Id=3A,Rds<97mohm
LL1,CL13 will be changed to

2.2uH&4.7uF after EVT test
1
Layout Note: LL1 must be
within 200mil to Pin36,
CL13
CL13,CL9 must be within 22U_0805_6.3V6M
2
200mil to LL1
RTL8111E-GR_QFN48_6X6
+3VALW
8111E@
19 PCIE_PRX_C_LANTX_P1
SUPERWORLD_SWG150401
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
CL34
0.1U_0402_25V4K
1
LL4
1
LL5
1
LL6
1
LL7
10/100M transformer
8105E@
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet

1
30
of
45
0_0603_5%
1
+3VS_DVDD
35 mA
RA1
2
+3VS
RA32 0_0603_5%
2
1
+3VS
+DVDD_IO
CA8
CA7
10U_0805_10V4Z 0.1U_0402_16V4Z
2
CA1
CA2
0.1U_0402_16V4Z 10U_0805_10V4Z
2
place close to chip
0624
2
D
place close to chip

+AVDD
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
0_0603_1%
68 mA
+5VS
UA12
0624 MIC1_LINE1_R_R
MIC1_LINE1_R_L
MIC1
1
2
1
2
GND
GND
3
4
MIC
1
2MIC2R_R
RA25 1K_0402_5%
1
2MIC2R_L
RA26 1K_0402_5%
2
CA9
4.7U_0603_6.3V6K
1
2
CA10
4.7U_0603_6.3V6K
1U_0402_6.3V4Z 2
1CA26
1U_0402_6.3V4Z
MIC1_LINE1_R
MIC1_LINE1_L
1
CA28 +MIC1_VREFO_L
+MIC1_VREFO_R
+MIC2_VREFO
ACES_88231-02001
CONN@
22
21
MIC2_R 17
MIC2_L 16
DA10
MIC1_R
MIC1_L
DVDD
DVDD_IO
CA3
1
9
PESD5V0U2BT_SOT23-3
+MIC2_VREFO
RA51 4.7K_0402_5%
18 HDA_SYNC_AUDIO
1
CA12
MONO_IN
2
100P_0402_50V8J
HDA_SYNC_AUDIO
18 HDA_RST_AUDIO#
MIC2_R
MIC2_L
AVDD1
AVDD2
31
30
29
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
PVDD1
PVDD2
39
46
15
14
LINE2_R
LINE2_L
SPK_OUT_R+
SPK_OUT_R-
45
44
SPKR+
SPKR-
20
MONO_OUT
SPK_OUT_L+
SPK_OUT_L-
40
41
SPKL+
SPKL-
12
PCBEEP_IN
10
SYNC
HPOUT_R
HPOUT_L
33
32
11
RESET#
CA17
2.2U_0603_6.3V4Z
20K_0402_1% 1
RA10 2AC_JDREF
19
CA35
2
110U_0805_10V4Z28
AC_VREF 27
CPVEE
2.2U_0603_6.3V4Z
CA14
34
2
1
35
1
2
CA16
36
2.2U_0603_6.3V4Z
JDREF
LDO_CAP
VREF
CPVEE
CBN
CBP
SDATA_OUT
SDATA_IN
5
8
BITCLK
NC
NC
NC
24
23
48
AVSS1
AVSS2
PVSS1
PVSS2
DVSS
26
37
42
43
7
THERMAL_PAD
49
CA18
2
3
1
2
0.1U_0402_16V4Z
SENSE_A
place close to chip
EAPD
EC_MUTE#
33 EAPD
33 EC_MUTE#
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
13
18
SENSE_A
SENSE_B
47
4
EAPD
PD#
+PVDD1
+PVDD2
CA48 1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
1
RA43
2 0.1U_0603_50V7K
CA5
CA6
CA57
MIC1_LINE1_R_L
0624
place close to chip
75_0402_1%
75_0402_1%
HP_R
29
HP_L
29
HDA_SDOUT_AUDIO
HDA_SDIN0 18
18
HDA_BITCLK_AUDIO
18
AGND
39.2K
SPKL-
2
1
1K_0402_5%
RA45
RA13
2
1
0_0603_1%
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 37)
5.1K
PORT-I (PIN 32, 33)
SPKR-
RA46 1
2
4.7K_0402_5%
CA51
100P_0402_50V8J2
RA44
2
1
0_0603_1%
SPKR+
29
MIC_SENSE
1
RA18
2
20K_0402_1%
CA39
100P_0402_50V8J
Beep sound
DA9
1
2
3
4
ACES_85204-0400N
CONN@
2
CA45
1U_0402_6.3V4Z
@
3
B
PESD5V0U2BT_SOT23-3
SPK_R2
RA8
1
2
47K_0402_5%
BEEP#
PCI Beep
CA15
1
2
RA9
1
2
47K_0402_5%
HDA_SPKR
29
NBA_PLUG
1
RA16
MONO_IN
0.1U_0402_16V4Z
2
39.2K_0402_1%
1
RA11
10K_0402_5%
CA20
0.1U_0402_16V4Z
SPK out
Int. MIC
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Headphone out
Date:
1
2
3
4
EC Beep
18
Ext. MIC
JSPK
SPK_L2
SPK_L1
SPK_R2
SPK_R1
SENSE_A
1 RA19
2
10K_0402_1%
3
PESD5V0U2BT_SOT23-3
1
CA46
100P_0402_50V8J
SPK_L2
+MIC1_VREFO_L
0624
29
2
CA42
1U_0402_6.3V4Z
@
SPK_R1
29
DA8
+MIC1_VREFO_R
MIC1_R
CA19
100P_0402_50V8J2
SENSE B
2
10U_0805_10V4Z
SPK_L1
RA14
2
1
0_0603_1%
RA15
2
1
0_0603_1%
SPKL+
MIC1_L
PORT-A (PIN 39, 41)
20K
0624
RA47
2 RA48
1
1K_0402_5% 4.7K_0402_5%
2
1
2
0_0603_5%
Function
2
10U_0805_10V4Z
SENSE A
Codec Signals
2
10U_0805_10V4Z
placement near Audio Codec
U
k
o
DGND
33
Impedance
RA12
2
1 0.1U_0402_16V4Z
+5VS
1 BLM18PG181SN1D_0603
1
1
CA60
CA59
CA58
s
e
.
e
s
r
e
niv
1
33_0402_5%
place close to chip

Sense Pin
2
10U_0805_10V4Z
+PVDD2
RA5
RA2
2
1 0.1U_0402_16V4Z
+5VS
1 BLM18PG181SN1D_0603
1
1
CA44
CA56
CA43
place close to chip
Ext.MIC/LINE IN JACK
MIC1_LINE1_R_R
Speaker Connector
o
b
e
t
o
N
2 0.1U_0603_50V7K
CA4
RA4
HDA_SDOUT_AUDIO
HDA_SDIN0_R
2
RA6
HDA_BITCLK_AUDIO
ALC259-VB5-GR_QFN48_7X7
CA47 1
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
25
38
2
1
600 mA 0.1U_0402_16V4Z
+PVDD1
1
Sheet

1
31
of
45
Close to OSC1
48MHz_SSW048000I3CH
3 in 1 Card Reader
GND CONT
OUT
1
@ RC27
2
0_0402_5%
+3VS_CR
1
2
@ CC15 100P_0402_50V8J
VDD 4
OSC1
+3VS_CR
1
CLK_48M_CR
RC4
6.19K_0402_1%
2
1
+3VS
UC2
22
22
+3VS_CR
RC5
0_0603_5%
USB20_N11
USB20_P11
USB20_N11
USB20_P11
+3VS_CR
1
1 CC8
0.1U_0402_16V4Z
CC11
4.7U_0805_10V4Z
+VCC_3IN1
1
V1_8
CC12
1U_0402_6.3V4Z
SDWP_MSCLK_R
1
RC25
2
0_0402_5%
REFE
2
3
DM
DP
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
8
9
10
11
12
SP1
SP2
SP3
SP4
SP5
25
CC14
10P_0402_50V8J
@
SDWP_MSCLK
MSCD#
SD_DATA1
SD_DATA0
MS_DATA3_SD_DATA7
EPAD
1
RC26
GPIO0
17
CLK_IN
24
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
OSC_48M_CR_R
2
0_0402_5%
CC7
0.1U_0402_16V4Z
2
1
CLK_48M_CR
CLK_48M_CR 19
< 48MHz >
MSBS
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
SDCMD
MS_DATA0_SD_DATA5
MS_DATA2_SDCLK
1
RC23
2
0_0402_5%
SDCD#
MS_DATA2_SDCLK_R
1 CC13
10P_0402_50V8J
@
RTS5138-GR_QFN24_4X4
2
JCR
SDWP_MSCLK_R
SD_DATA1
SD_DATA0
0.1U_0402_16V4Z
1
MSCD#
MS_DATA3_SD_DATA7
SDCMD
CC16
0.1U_0402_16V4Z
CC19
CC18
0.1U_0402_16V4Z
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
CC17
1U_0402_6.3V4Z
JKB
27
28
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
U
k
o
o
b
e
t
o
N
KEYBOARD CONN.
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
SD_DATA2_MS_DATA5
SDCD#
For EMC
1
C803
1
C804
1
C805
1
C807
1
C808
1
C810
1
C824
1
C826
1
C823
1
C825
1
C871
1
C822
1
C793
1
C790
1
C791
1
C792
1
C795
1
C796
1
C797
1
C798
1
C799
1
C800
1
C801
1
C802
e
s
r
e
niv
+VCC_3IN1
1
TAITW_R009-025-LR_NR
CONN@
KSO10
s
e
.
MSBS
MS_DATA2_SDCLK_R
MS_DATA1_SD_DATA3
MS_DATA0_SD_DATA5
SPI Flash (1MByte*1)
Lid SW
+3VALW
+3VALW
U36
APX9132ATI-TRL_SOT23-3
C789
0.1U_0402_16V4Z
20mils
U49
VCC
HOLD
33
SPI_CLK
4
1
33 SPI_CS#
33 EC_SO_SPI_SI
2
VSS
VDD
VOUT
LID_SW#
33
C648
0.1U_0402_16V4Z
C649
0.1U_0402_16V4Z
EC_SI_SPI_SO 33
MX25L2005CMI-12G SO8
P/N :SA00003GK00 & SA00003GM10
ACES_88514-02601-071
CONN@
@ C931
@C931
@ R1369
2
1 2
1
6P_0402_25V
KSI[0..7]
KSO[0..15]
KSI[0..7]
SPI_CLK
10_0402_5%
28,33
KSO[0..15] 33
Issued Date
Compal Secret Data
2010/05/17
2011/05/17
Deciphered Date
Title
SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
GND
22
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SD-WP
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
GND1 SD-DAT2
GND2
SD-CD
Sheet

E
32
of
45
VCC
VCC
VCC
VCC
VCC
VCC
U32
C742
1000P_0402_50V7K
C741
1000P_0402_50V7K
C740
0.1U_0402_16V4Z
C739
0.1U_0402_16V4Z
CLK_PCI_LPC
C738
0.1U_0402_16V4Z
@ R716
33_0402_5%
2
1
C737
0.1U_0402_16V4Z
1
D
22 CLK_PCI_LPC
5,22,29,30 PLT_RST#
10/1 ENE Recommand

R723
2 47K_0402_5%
KSO1
R728
2 47K_0402_5%
KSO2
R725
1 @
2 10K_0402_5%
EC_SMI#
R729
2 2.2K_0402_5%
EC_SMB_DA1
R731
2 2.2K_0402_5%
EC_SMB_CK1
23
PAD
EC_SCI#
T64 @
0621
@R732
@
R732
33_0402_5%
1
2
28,32
32
KSI[0..7]
KSI[0..7]
KSO[0..15]
KSO[0..15]
Reserve for EMI please close to U32
+3VS
R738
2 2.2K_0402_5% EC_SMB_CK2
R739
2 2.2K_0402_5% EC_SMB_DA2
2 10K_0402_5% EC_SCI#
R741
4
OSC
1 @
C752
15P_0402_50V8J
2
NC
OSC
2
NC
X1 @
32.768KHZ_12.5PF_Q13MC14610002
CLK_PCI_LPC
EC_RST#
EC_SCI#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
20 PM_SLP_S3#
20 PM_SLP_S5#
23
EC_SMI#
44 GFX_CORE_PWEGD
34 WL_BT_LED#
20 PM_SLP_SUS#
20 SUSWARN#
15 INVT_PWM
5 FAN_SPEED1
35 PCH_PWR_EN
29 E51_TXD
29 E51_RXD
31 EAPD
1
+3VALW
R744
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
12
13
37
20
38
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
21
23
26
27
CPU1.5V_S3_GATE
BEEP#
PCH_DPWROK
ACOFF
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
BATT_TEMPA
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
PWM Output
AD
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
GFX_CORE_PWEGD
WL_BT_LED#
PM_SLP_SUS#
SUSWARN#
INVT_PWM
FAN_SPEED1
PCH_PWR_EN
E51_TXD
E51_RXD
EAPD
2EC_GPIO19
10K_0402_5%
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
EC_XCLK1
EC_XCLK0
122
123
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
EN_DFAN1
IREF
CHGVADJ
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
EC_ACIN
EC_ON
ON/OFFBTN#
LID_SW#
SUSP#
PBTN_OUT#
V18R
124
+V18R
GPI
XCLK1
XCLK0
11
24
35
94
113
36,37
44
s
e
.
e
s
r
e
niv
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
SM Bus
IMON
EC_MUTE# 31
USB_EN# 29
DRAMRST_CNTRL_EC
TP_CLK
TP_DATA
PM_PWROK
EC_PECI R740 1
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
PWR_ON_LED#
SYSON
VR_ON
PM_SLP_S4#
KB930QF A1 LQFP 128P
EC_GPXO05
BT_PWRON
H_PROCHOT#_EC
BKOFF#
ENBKL
PCH_APWROK
SA_PGOOD
DRAMRST_CNTRL_EC 7
TP_CLK 34
TP_DATA 34
SUSACK# 20
WL_OFF# 29
HDA_SDO 18
VGATE
14,20,44
SPI Device Interface
GPIO
ADP_I
EN_DFAN1 5
IREF
37
CHGVADJ 37
SUSACK#
WL_OFF#
HDA_SDO
VGATE
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPI Flash ROM
1 100P_0402_50V8J ECAGND
BATT_TEMPA 36
R742
0_0402_5%
2
1
@
IMON_R
97
98
99
109
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
U
k
o
o
b
77
78
79
80
C746 2
EC_MUTE#
USB_EN#
PS2 Interface
CPU1.5V_S3_GATE 10
BEEP#
31
PCH_DPWROK 20
ACOFF
37
ADP_I
83
84
85
86
87
88
GND
GND
GND
GND
GND
20 SUSCLK
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
1
2
3
4
5
7
8
10
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
e
t
o
N
36
36
19
19
EC_XCLK0
@ 1
C751
15P_0402_50V8J
EC_XCLK1
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
EC_SI_SPI_SO 32
EC_SO_SPI_SI 32
SPI_CLK 32
SPI_CS# 32
+3VALW
EC_MUTE#
PM_PWROK 20
2 43_0402_1%
H_PECI
5,23
FSTCHG 37
BATT_FULL_LED# 34
CAPS_LED# 34
BATT_CHG_LOW_LED# 34
PWR_ON_LED# 34
SYSON
35,40
VR_ON
44
PM_SLP_S4# 20
R717
LID_SW#
R1210 1
EC_GPXO05
R1211 1
1 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
+5VS
@
TP_CLK
R720
4.7K_0402_5%
TP_DATA
R727
4.7K_0402_5%
GFX_CORE_PWEGD
R722
2 10K_0402_5%
BKOFF#
R724
+3VS
PCH_RSMRST# 18,20
LID_SW_OUT# 19
BT_PWRON 29
2 10K_0402_5%
0621
BKOFF# 15
ENBKL
21
PCH_APWROK 20
SA_PGOOD 43
EC_ON
28,34,38
ON/OFFBTN# 34
LID_SW# 32
SUSP# 10,28,35,39,41,43
PBTN_OUT# 18,20
+3VALW
R730
D15
EC_ACIN
C749
1 200K_0402_5%
2
2
1
2
ACIN
20,37
1 100P_0402_50V8J
C753
4.7U_0805_10V4Z
20mil
36,44
L54
ECAGND 2
1
FBMA-L11-160808-800LMT_0603
VR_HOT#
VR_HOT#
R737
0_0402_5%
2
1
H_PROCHOT# 5
1
23
GATEA20
23 KB_RST#
18
SERIRQ
18 LPC_FRAME#
18
LPC_AD3
18
LPC_AD2
18
LPC_AD1
18
LPC_AD0
0.1U_0402_16V4Z
+3VALW
@ C748
22P_0402_50V8J
2
1
EC_RST#
1 47K_0402_5%
1
C743
0.1U_0402_16V4Z
C745 2
AGND
R718 2
+3VALW
69
@ C744
22P_0402_50V8J
2
1
L53
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
+3VALW_EC
ECAGND
R714
0_0805_5%
2
67
AVCC
+3VALW
9
22
33
96
111
125
H_PROCHOT#_EC
2
G
Q37
2N7002_SOT23
Compal Secret Data
Issued Date
2010/05/17
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Rev
D
401968
Date:
Sheet

1
33
of
45
Power Button/ PWR/B
Touch/B Connector
JPOWER
1
2
3
4
5
6
7
8
+5VALW
PWR_ON_LED# 33
+5VS
R155
1
2
ON/OFFBTN# 33
51_ON#
ACES_88058-060N
CONN@
36
CHN202UPT SC-70
H_3P0
H7
H8
H9
H10
H_3P0
H_3P0
H_3P0
H_3P0
H23
H24
H25
UD
NB
2 BLUE
H_3P3
CPU
H22
H_4P5
H_4P5
H_4P5
BATT_CHG_LOW_LED# 33
2
220_0402_5%
BATT_FULL_LED# 33
FD1
HT-210UD/NB_AMB/BLUE
H_4P5
PCB Fedical Mark PAD
2
220_0402_5%
FD2
1
1
R271
H_3P0x3P5N
H20
D26
+5VALW
H_3P0
JWLAN
Vf=2.1V(typ),2.4V(max) for amber

Vf=2.2V(typ),2.4V(max) for green
If=25mA(max)
1
AMB R270
H15
BATT CHARGE/FULL LED
H13
Q210B 2N7002DW-T/R7_SOT363-6
H_3P0
del R204, add R270 and R271 for LED issue, 1103
FD3
FD4
Q210A
4
H_3P0
H_3P0
H_3P0
D25
HT-110NBQA_BULE_1204
H3
2
1
H6
+5VS
1
10K_0402_5%
2
2
220_0402_5%
3
H5
2N7002DW-T/R7_SOT363-6
1
2
R232
SATA_LED# 18
H4
SATA_LED#
1
R233
e
t
o
N
WL_BT_LED# 33
HDD LED
+3VS
HT-110UD_1204
H2
SW4
SMT1-05-A_4P
1
Screw Hole
D74
2
300_0402_5%
5
6
2
3
HT-110NBQA_BULE_1204
1
R777
s
e
e.
U
k
o
o
b
1AMB PWR_ON_LED#
WL&BT LED
+5VS
s
r
e
v
ni
D75
2
300_0402_5%
RIGHT_BTN#
1
R779
SW9
SMT1-05-A_4P
1
1
+5VALW
DC-IN LED
2N7002_SOT23-3
Q23
R156
10K_0402_5%
D16
PJDLC05C_SOT23-3
2
G
3
EC_ON
D18
PJDLC05C_SOT23-3
TP_CLK 33
TP_DATA 33
LEFT_BTN#
28,33,38
3
LEFT_BTN#
RIGHT_BTN#
D8
ON/OFFBTN#_R
1
2
3
4
5
6
7
8
C759
100P_0402_50V8J
Bottom Side
100K_0402_5%
1
2
3
4
5
6
GND
GND
foot print to 8 pin---0617
RIGHT_BTN#
5
6
change conn
LEFT_BTN#
TP_DATA
JTP
+3VALW
1
10K_0603_5%
1
10K_0603_5%
TP_CLK
C757
100P_0402_50V8J
2
R153 @
2
R154 @
2
0.1U_0402_16V4Z
ACES_88058-060N
CONN@
TOP Side
C755
1
ON/OFFBTN#_R
1
2
3
4
5
6
GND
GND
CAP LOCK LED

D27
+5VALW
1
R268
2
2
220_0402_5%
1CAPS_LED#
CAPS_LED# 33
LED 19-213A/T1D-CP2Q2HY/3T 0603 WHIT
Issued Date
Compal Secret Data
2010/05/17
Deciphered Date
2011/05/17
Title
Size
B
Date:
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
Sheet
34
of
45
+5VALW
+3VALW TO +3VALW_PCH
+5VALW
R802
100K_0402_5%
+5VS
6
0.1U_0402_16V7K
0.1U_0402_16V7K
C839
C849
2
0.1U_0402_16V7K
C847
10mil
R792
330K_0402_5%
C874
SI4800BDY_SO8
2
R791
1U_0402_6.3V4Z
1 R790
2
47K_0402_5%
Q216A
+VSB
20mil
Q44A
33,40
SYSON
SYSON
C875 C846
DMN66D0LDW-7_SOT363-6
R805
100K_0402_5%
+5VALW
Q216B
PCH_PWR_EN#5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
C848
1
2
3
4
S
S
S
G
D
D
D
D
3 1
8
7
6
5
1
4.7U_0805_10V4Z
R808
100K_0402_5%
SUSP
SUSP
5,42
Q38
0.1U_0402_16V7K
0.1U_0402_16V7K
40mil
Q36B
SYSON#
2
Q36A
SUSP 5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
JUMP_43X79
470_0805_5%
J2
C855
+VSB
0.022U_0402_25V7K
R788
330K_0402_5%
R782
C853
4.7U_0805_10V4Z
0.1U_0402_16V7K
1 R785
2
47K_0402_5%
470_0805_5%
RUN_ON
1
C845
4.7U_0805_10V4Z
C842
2
C843
4.7U_0805_10V4Z
0.01U_0402_25V7K
C856
SI4800BDY_SO8
2
3 1
C852
1U_0402_6.3V4Z
1
2
3
4
S
S
S
G
D
D
D
D
Q33
8
7
6
5
+3VALW_PCH
1
+3VALW
+5VALW TO +5VS
+3VALW TO +3VS
Q44B
DMN66D0LDW-7_SOT363-6
Vgs=-0V,Id=9A,Rds=18.5mohm
Q34
D
D
D
D
S
S
S
G
1
2
3
4
1
C838
1U_0402_6.3V4Z
1 R786
2
+VSB
220K_0402_5%
R789
820K_0402_5%
C837
2
C836
0.1U_0603_25V7K
4.7U_0805_10V4Z
FDS6676AS
Q214A
2
1
1
PCH_PWR_EN#
25 PCH_PWR_EN#
Q49
2N7002E-T1-GE3_SOT23-3
2
G
R816
100K_0402_5%
SUSP
C315
330P_0402_50V7K
@
Q214B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
2
R813
100K_0402_5%
33 PCH_PWR_EN
e
t
o
N
R783
SI4856ADY_SO8
1
C829
4.7U_0805_10V4Z
3 1
8
7
6
5
+1.5VS
n
U
k
o
o
b
+5VALW
C313
330P_0402_50V7K
@
+1.5V to +1.5VS
3 1
Q35B
Vgs=10V,Id=14.5A,Rds=6mohm
+1.5V
e
s
r
e
v
i
Q35A
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
s
e
.
R787
330K_0402_5%
+VSB
1 R784
2
47K_0402_5%
0.1U_0402_16V7K
C834
C830
2
0.022U_0402_25V7K
C872
4.7U_0805_10V4Z
SI4800BDY_SO8
2
R781
R809
10K_0402_5%
2
C873 C844
2
1U_0402_6.3V4Z
1
2
3
4
S
S
S
G
1
4.7U_0805_10V4Z
470_0805_5%
D
D
D
D
C827
C314
330P_0402_50V7K
@
EMI DEMAND
8
7
6
5
C828
Q32
10,28,33,39,41,43 SUSP#
0.1U_0402_16V7K
0.1U_0402_16V7K
+3VS
470_0805_5%
+3VALW
+5VS
+0.75VS
+1.8VS
+1.5V
R827
470_0603_5%
R826
22_0603_5%
+1.05VS_VCCP
R828
470_0603_5%
R829
470_0603_5%
C851
0.1U_0402_16V7K
C854
0.1U_0402_16V7K
1 1
D
2 SUSP
G
Q59
S
2N7002E-T1-GE3_SOT23-3
D
2 SUSP
G
Q58
S
2N7002E-T1-GE3_SOT23-3
D
2 SUSP
G
Q57
S
2N7002E-T1-GE3_SOT23-3
1 1
1 1
2
1
2
G
SYSON#
Q60
2N7002E-T1-GE3_SOT23-3
Issued Date
Compal Secret Data
2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
0.75VS speed up discharge
2010/05/17
2011/05/17
Deciphered Date
Title
Custom
SCHEMATICS,MB A6731
Rev
D
401968
Date:
0.1U_0402_16V7K
C850
Sheet

E
35
of
45
PL1
HCB2012KF-121T50_0805
1
2
ADP_OCP_1
OTP_N_001
GND RHYST1
OTP_N_002
OT1 TMSNS2
ADP_OCP_3
OT2 RHYST2
ADP_OCP_2
2
2
PR13
100K_0402_1%
EC_SMB_DA1 33
POK
PR16
0_0402_5%
2VSB_N_002 2
G
1
38
EC_SMB_CK1 33
1
2
1
1
2
PC8
0.22U_0603_25V7K
1
PR10
100K_0402_1%
PR12
22K_0402_1%
1
2
+VSBP
PQ1
TP0610K-T1-E3_SOT23-3
VSB_N_001
PQ2
SSM3K7002FU_SC70-3
Reserve when EC use +3VL.

Install when EC use +3VALW.
VIN
VL
e
t
o
N
BATT_TEMPA 33
1VSB_N_003
PJSOT24CW_SOT323-3
B+
U
k
o
o
b
+3VALW
PC7
0.01U_0402_25V7K
PC9
0.1U_0603_25V7K
e
s
r
e
niv
2
PD2
3
1
PR9
6.49K_0402_1%
100_0402_1%
2
PR11
1K_0402_1%
s
e
.
3
PC6
1000P_0402_50V7K
EC_SMB_DA1_1
1
@
2
PR14
100_0402_1%
PR15
PD1
SUYIN_200275MR009G10PZR
EC_SMB_CK1_1
GND
38
PC10
.1U_0402_16V7K
+3VALW
100K_0402_1%
PR7
1K_0402_1%
TS_A
PH1
100K_0402_1%_NCP15WF104F03RC
VS_ON 38
BATT+
PR6
1
BATT_P4
@
1
PR25
100K_0402_1%
If EC use 3VL and can not detect VGATE,

must connect EN0
PL4
HCB2012KF-121T50_0805
1
2
GND
PJSOT24CW_SOT323-3
2
1
3
11
10
9
8
7
6
5
4
3
2
1
0_0402_5%
PL3
HCB2012KF-121T50_0805
1
2
VMB
GND
GND
9
8
7
6
5
4
3
2
1
EN0
1
PR4
PJP1
11.5K_0402_1%
0_0402_5%
1
PR2
PR24
49.9k_0402_1%
G718TM1U_SOT23-8
@PR3
@
PR3
BATT_1
VCC TMSNS1
OTP_N_003
2
PR23
100K_0402_1%
2
G
PU1
VL
PQ4
SSM3K7002FU_SC70-3
PR1
24K_0402_1%
PR26
7.87k_0402_1%
X7R type
33,44 VR_HOT#
need confirm: ME give us battery

connector P/N is DC040006H00
ADP_I
PC5
0.1U_0603_16V7K
33,37
1
PC4
100P_0402_50V8J
1
2
PC13
0.1U_0402_25V6
VL
PC3
1000P_0402_50V7K
PC2
100P_0402_50V8J
SINGA_4TRJWT-R2513
4
3
2
1
PC1
1000P_0402_50V7K
PJPDC1 @
4
3
2
1
PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
VIN
PL2
HCB2012KF-121T50_0805
1
2
ADPIN
PC14
0.1U_0402_25V6
DCIN jack P/N:DC301009U00,

need doble confirm P/N with ME
PD3
RLS4148_LL34-2
VS_N_001
1
2
PR22
22K_0402_1%
+VSB
PBJ1 @
2
PC12
0.1U_0603_25V7K
+
1
PR19
PR20
560_0603_5%
560_0603_5%
+RTCBATT1 1
2+RTCBATT2 1
2
@
+RTCBATT
+CHGRTC
3.3V
1
MAXEL_ML1220T10
Must close PBJ1
VS_N_002
SP093MX0000
Reserve when EC use +3VL.

Install when EC use +3VALW.
Issued Date
Compal Secret Data
2010/05/17
Deciphered Date
2011/05/17
Title
Size
Date:
PJ3
JUMP_43X39
1
1
51_ON#
+3VL
VS
34
RTC Battery
PR18
68_1206_5%
PC11
0.22U_0603_25V7K
PR21
100K_0402_1%
(120mA,40mils ,Via NO.= 1)
PJ2
JUMP_43X39
PQ3
PR17
TP0610K-T1-E3_SOT23-3 68_1206_5%
N1
PD4
RLS4148_LL34-2
BATT+
@
+VSBP
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
D
Sheet
36
of
45
PL403
1.2UH +-30% 1231AS-H-1R2N=P3 2.9A
1
2
PR105
18.2K_0402_1%
1
2
VREF
UGATE
17
CHLIM
PC106
2200P_0402_25V7K
1
2
2
PR111
14.3K_0402_1%
1CHG_N_008
1
VDDP
15
11
VADJ
LGATE
14
12
GND
PGND
13
6251VDDP
DL_CHG
PC121
0.1U_0603_25V7K
BST_CHGA 2
1
26251VDD
PR129
4.7_0603_5%
PL101
PR102
10U_LF919AS-100M-P3_5.3A_20%
0.02_1206_1%
CHG
1
2
1
4
PQ110
AO4468L_SO8
PC123
4.7U_0805_6.3V6K
ISL6251A_SSOP24
BATT+
PR106
31.6K_0402_1%
6251VDD
PR131
47K_0402_1%
2
PR132
10K_0402_1%
PR133
10K_0402_1%
1
2
ACIN
20,33
PACIN
ACPRN
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K

90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N
PQ112
2
B
CP= 85%*Iada;
PD106
RB751V-40TE17_SOD323-2
DH_CHG
PR126
0_0603_5%
BST_CHG 1
U
k
o
ACLIM
16
e
s
r
e
v
ni
PR122
2.2_0603_1%
LX_CHG
2 ACPRN
G
PQ109 @
SSM3K7002FU_SC70-3
PC102
10U_0805_25V6K
2
1
18
PHASE
PC101
10U_0805_25V6K
2
1
ICM
19
CSIP
PR125
4.7_1206_5%
VCOMP
s
e
.
CHG_SNUB 2
20
CSIN
BOOT
2CHG_N_006
PC124
680P_0603_50V7K
ICOMP
3
2
1
PQ108
AON7408L_DFN8-5
5
6
7
8
21
CSOP
3
2
1
CSOP
CSON
CELLS
10
PR118
20_0603_5%
CHG_CSON 1
2
PC113
0.047U_0603_16V7K
CHG_CSOP 1
2
PR119
20_0603_5%
CHG_CSIN
2
1
PC118
PR120
0.1U_0603_25V7K
20_0603_5%
CHG_CSIP
1
2
22
CSON
PQ106
DTC115EUA_SC70-3
t
o
N
EN
DCIN
PR115
100K_0402_1%
1
2 CHG_N_001
ACPRN
23
ACSET ACPRN
o
b
e
PR128
20K_0402_1%
PC105
0.1U_0402_25V6
2
1
Rtop
33 CHGVADJ
3
24
PR104
140K_0402_1%
6251aclim
CHG_VADJ
PQ111
DTC115EUA_SC70-3
PR127
226K_0402_1%
6251VREF 1
2
DCIN
VIN
ACOFF
PC122
0.01U_0402_25V7K
2
1
ACOFF
6251VREF
CHG_CHLIM
33
1
2
PC120
.1U_0402_16V7K
VDD
PR112
10K_0402_1%
PC112
1U_0603_25V6K
1
2
ADP_I
IREF
PR103
33,36
150K_0402_1%
2
1
CHG_VCOMP
PR123 100_0402_1%
1
2CHG_ICM
0.01U_0402_25V7K
PC120 must close EC pin.

33
6.81K_0402_1%
2
PR110
47K_0402_1%
1
2
PR124
22K_0402_5%
PACIN 1
2
6800P_0402_25V7K
CHG_ICOMP
2
PC116
1
PC117
PR121
1
2CHG_VCOMP1 1
10_1206_5%
8
7
6
5
CHG_N_005
PU101
CHG_N_009
PR113
6251_EN
PQ107B
SSM6N7002FU-2N_SOT363-6
3CHG_N_002
PC110
1000P_0402_25V8J
3
6
PQ107A
2
PD101
CHG_VIN 1
PC109
2.2U_0603_6.3V6K
2
1
FSTCHG
PR116
150K_0402_1%
PR117
100K_0402_1%
33
RB751V-40TE17_SOD323-2
ACSETIN
PR114
10K_0402_1%
2
1
ACSETIN
PC104
4.7U_0805_25V6-K
2
1
1
2
1
2
PQ105
DTC115EUA_SC70-3
CHG_N_001
PR108
191K_0402_1%
1
2
6251VDD
CHG_N_003
PQ103
AO4407AL_SO8
1
2
3
CSIN
CSIP
PR107
200K_0402_1%
PC108
0.1U_0603_25V7K
PR109
47K_0402_1%
1CHG_N_010
PQ104
DTA144EUA_SC70-3
VIN
8
7
6
5
B+
CHG_B+
@PL102
@
PL102
HCB2012KF-121T50_0805
1
2
0.02_2512_1%
1
4
PC103
10U_0805_25V6K
2
1
1
2
3
8
7
6
5
B+
PR101
P3
PC107
5600P_0402_25V7K
1
2
VIN
PQ102
AO4409 1P SO8
1
2
3
P2
PQ101
AO4435L_SO8
PC114
2200P_0402_25V7K
PR136
20K_0402_1%
Add
E
MMBT3904W_SOT323-3
CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A
CC=0.25A~3A
CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge
Vcell
IREF=0.254V~3.048V
4V
VCHLIM need over 95mV
4.2V
CHGVADJ
Issued Date
Compal Secret Data
0V
1.882V
2010/05/17
Deciphered Date
2011/05/17
Title
Size
Date:
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
D
Sheet
37
of
45
2VREF_51125
PQ307A
19
LG_5V
POK
NC
1
2
36
RT8205EGQW_WQFN24_4X4
PQ306
IRF8707GTRPBF_SO8
VL
PC318
4.7U_0805_10V6K
+3VLP
@
PR317
100K_0402_5%
PR318
1K_0402_1%
1
2
2
2
+5VALW
(6A,240mils ,Via NO.= 12)
+3VALW
(4.5A,180mils ,Via NO.= 9)
1
PAD-OPEN 2x2m
PAD-OPEN 4x4m
@ PJP303
VL
+3VALWP
+5VL
VL
@
2
PJP301
1
PAD-OPEN 2x2m
1
2
PR319
100K_0402_1%
PC321
0.01U_0402_16V7K
2
2
1
PR320
40.2K_0402_1%
+3VL
@
PJP302
PJP305
PQ308
DTC115EUA_SC70-3
36 VS_ON
EC:+3VL, reserve PR319, install PR318, PR320 100K

EC:+3VALW, reserve PR318, install PR319, PR320 40.2K
Compal Secret Data
2010/05/17
Issued Date
2011/05/17
Deciphered Date
Title

SCHEMATICS,MB A6731
Date:
PC305
220U_6.3V_M
PC319
0.1U_0603_25V7K
PAD-OPEN 4x4m
+
2
2VREF_51125
B++
+5VALWP
VS
+5VALWP
PC317
680P_0603_50V7K
LGATE1
PL305
4.7UH_PCMC063T-4R7 MN_5.5A_20%
1
2
PR313
4.7_1206_5%
2
1
LX_5V
SNUB_5V
20
3
2
1
UG_5V
PHASE1
5
6
7
8
22
21
18
VIN
VREG5
17
PC307
10U_0805_25V6K
PC312
2200P_0402_50V7K
2
1
2
FB1
REF
ENTRIP1
BOOT1
UGATE1
PC320
1U_0603_10V6K
e
s
r
PQ307B
N_3_5V_001
EC_ON
TONSEL
PR510
0_0402_5%
1
2
t
o
N
GND
s
e
.
PR309
PC315
2.2_0402_5%
0.1U_0402_10V7K
BST_5V 1
2 BST1_5V 1
2
o
b
e
PR315
95K_0402_1%
23
3
2
1
EN0
15
EN
13
36
24
e
v
ni
U
k
o
PR314
499K_0402_1%
2
16
LGATE2
VO1
PGOOD
PQ305
AON7408L_DFN8-5
12
PHASE2
PR307
105K_0402_1%
2
6ENTRIP1
BOOT2
1
2
3
AO4468L_SO8
ENTRIP2
8
7
6
5
1
2
B++
11
LG_3V
4
SNUB_3V
VREG3
UGATE2
LX_3V
VO2
UG_3V 10
PQ304
PC316
680P_0603_50V7K
PR312
4.7_1206_5%
+3VALWP
BST_3V
B++
PC314
PR308
0.1U_0402_10V7K
BST1_3V 1
1
2
2
0_0402_5%
PL303
4.7UH_PCMC063T-4R7 MN_5.5A_20%
2
1
28,33,34
P PAD
14
1
2
3
PC303
220U_6.3V_M
25
2
ENTRIP2
PU301
PC313
4.7U_0805_10V6K
PR306
20K_0402_1%
2
PQ303
AON7408L_DFN8-5
FB2
1
2
PC304
4.7U_0805_25V6-K
PC310
2200P_0402_50V7K
2
1
PC309
0.1U_0402_25V6
2
1
PR303
105K_0402_1%
1
ENTRIP2
+3VLP
FB_5V 1
PR305
30.9K_0402_1%
2
ENTRIP1
FB_3V
SKIPSEL
PL301
HCB2012KF-121T50_0805
1
PR302
20K_0402_1%
1
2
B++
B+
PC311
0.1U_0402_25V6
2
1
PR301
13.7K_0402_1%
1
PC308
1U_0603_16V
Rev
D
401968
Sheet

E
38
of
45
PC402
22U_0805_6.3VAM
e
t
o
N
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
s
e
.
e
s
r
e
niv
PR402
10K_0402_1%
U
k
o
o
b
PC404
68P_0402_50V8J
2
1
1
2
PR401
20K_0402_1%
PC401
22U_0805_6.3VAM
SY8033BDBC_DFN10_3X3
+1.8VSP
NC
TP
1.8VSP_FB
PR405
300K_0402_5%
11
EN_1.8VSP
FB
EN
PR403
4.7_1206_5%
LX
SVIN
PC405
0.1U_0402_10V7K
PR404 0_0402_5%
10,28,33,35,41,43 SUSP#
2
PL401
1UH_MMD-06CZ-1R0M-11A_20%
1
2
1.8VSP_LX
SNUB_1.8VSP
PVIN
PC406
680P_0603_50V7K
LX
NC
PVIN
PC403
22U_0805_6.3VAM
10
1.8VSP_VIN
PU401
HCB1608KF-121T30_0603
1
2
PG
PL402
+3VALW
+1.8VSP
PJP401
2
+1.8VS
(1.5A, 60mils, Via NO.= 3)
PAD-OPEN 3x3m
3
Issued Date
Compal Secret Data
2010/05/17
Deciphered Date
2011/05/17
Title
Size
Date:
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
D
Sheet
39
of
45
1.5V_B+
3
2
1
ILIM
11
FB
VDD
10
PGOOD
PR502
2.15K_0402_1%
DL
TRIP_1.5V 1
PR508
+5VALW
LG_1.5V
+5VALW
U
k
o
o
b
RT8209B_WQFN14_3P5X3P5
IRF8707GTRPBF_SO8
1
2
2200P_0402_50V7K
PC506
PC507
0.1U_0402_25V6
PR509
4.7_1206_5%
PQ502
PC510
4.7U_0805_10V6K
e
t
o
N
e
s
r
e
niv
15K_0402_1%
PC501
VCC
+1.5VP
PL501
2.2UH_PCMC063T_8A_20%
1
2
LX
LX_1.5V
PC511
680P_0603_50V7K
UG_1.5V
12
PQ501
AON7408L_DFN8-5
5
6
7
8
13
s
e
.
220U_D2_2VY_R15M
14
TP
BST
DH
2.21K_0402_1%
PC509
4.7U_0603_10V6K
FB_1.5V
PGND
1 PR501
+1.5VP
PR507
100_0402_1%
AGND
+5VALW 1
+5VALW
OUT
3
2
1
TON
+1.5VP
2
0_0402_5%
V5FILT_1.5V
PC508
0.1U_0402_10V7K
EN_SKIP
PU501
15
PR504
0_0402_5%
BST_1.5V 1
2BST1_1.5V
1
PR505
2
PC503
10U_0805_25V6K
PC505 @
0.1U_0402_10V7K
PR506
255K_0402_1%
1
2TON_1.5V
B+
PL502
HCB1608KF-121T30_0603
2
1
0_0402_5%
1SNUB_1.5V 2
33,35 SYSON
EN_1.5V
PR503
PJP502
2
PAD-OPEN 4x4m
PJP501
+1.5VP
+1.5V
PAD-OPEN 4x4m
Compal Secret Data
2010/05/17
Issued Date
Deciphered Date
2011/05/17
Title
Size
Date:

SCHEMATICS,MB A6731
Document Number
Rev
D
401968
Sheet
1
40
of
45
VCCP_B+
@ PR710
1
LG_VCCP
5
6
7
8
10_0402_5%
VOUT_VCCP
PC710
4.7U_0805_10V6K
U
k
o
o
b
1
2
2200P_0402_50V7K
PC706
PR709
4.7_1206_5%
PQ702
AO4726L 1N SO8
VTTPWRGOOD
PC704
4.7U_0805_25V6-K
1
2
e
s
r
e
niv
+5VALW
220U_D2_2VY_R15M
DL
+5VALW
PC701
PGOOD
s
e
.
3
2
1
BST
VDD
FB
PC711
680P_0603_50V7K
15
TRIP_VCCP1 PR708 2 13.7K_0402_1%
10
10K_0402_1%
PR712
14
11
+VCCPP
PL701
0.68UH_FMJ-0630T-R68 HF_15.5A_20%
1
2
FB_VCCP1
TP
ILIM
PR702
10.2K_0402_1%
+3VS
PR711
0_0402_5%
LX
VCC
OUT
LX_VCCP
3
2
1
4.12K_0402_1%
PC709
4.7U_0603_10V6K
FB_VCCP 5
UG_VCCP
12
PR701
13
DH
TON
B+
PC708
0.1U_0402_10V7K
PGND
PR707
100_0402_1%
+5VALW 1
VOUT_VCCP
AGND
+5VALW
2
0_0402_5%
V5FILT_VCCP
+VCCPP
C
1
PR706
2
EN_SKIP
PU701
PR705
255K_0402_1%
1
2TON_VCCP 2
PC702
10U_0805_25V6K
PQ701
AO4406AL_SO8
PR704
2.2_0402_5%
BST_VCCP1
2BST1_VCCP 1
5
6
7
8
PC705 @
0.1U_0402_10V7K
PL702
HCB1608KF-121T30_0603
2
1
0_0402_5%
1SNUB_VCCP 2
10,28,33,35,39,43 SUSP#
EN_VCCP
PC707
0.1U_0402_25V6
PR703
e
t
o
N
@ PJP701
1
PAD-OPEN 4x4m
B
+VCCPP
VCCIO_SENSE 9
@ PJP702
1
+1.05VS_VCCP
PAD-OPEN 4x4m
@ PJP703
VSSIO_SENSE connect to GND directly.
(14A,560mils ,Via NO.= 28)
2
PAD-OPEN 4x4m
Compal Secret Data
2010/05/17
Issued Date
Deciphered Date
2011/05/17
Title

SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet
1
41
of
45
+1.5V
PU601
VIN
NC
GND
NC
VREF VCNTL
VOUT
NC
TP
+3VALW
1
2
PR602
1K_0402_1%
@ PR817
@
PR820
0_0402_5%
s
r
e
v
ni
s
e
e.
U
k
o
o
b
PJP601
+0.75VSP
PC605
10U_0805_6.3V6M
RUN_ON_CPU1.5VS3#
SUSP
0_0402_5%
+0.75VSP
1
2
G
@ PQ602
SSM3K7002FU_SC70-3
2
G
2
1
PC604
.1U_0402_16V7K
PQ603
SSM3K7002FU_SC70-3
0.75VS_N_002
47K_0402_5%
PC94
.1U_0402_16V7K
PC603
1U_0603_10V6K
APL5336KAI-TRL_SOP8P8
10 RUN_ON_CPU1.5VS3#
PR134
VREF_G2992
PR130
47K_0402_5%
PR601
1K_0402_1%
SUSP
2
5,35
PC601
4.7U_0805_6.3V6K
+0.75VS
PAD-OPEN 3x3m
e
t
o
N
Compal Secret Data
Issued Date
2010/05/17
Deciphered Date
2011/05/17
Title
Size
Date:

SCHEMATICS,MB A6731
Document Number
Rev
D
401968
1
Sheet
42
of
45
VCCSA_B+
0_0402_5%
LG_VCCSA
SA_PGOOD 33
e
t
o
N
1
10_0402_5%
VOUT_VCCSA
PQ802
IRF8707GTRPBF_SO8
PC806
0.1U_0402_25V6
5
6
7
8
e
s
r
e
niv
PC809
4.7U_0805_10V6K
PR809
4.7_1206_5%
3
2
1
220U_D2_2VY_R15M
+5VALW
+VCCSAP
PL801
2.2UH_FMJ-0630T-2R2 HF_8A_20%
1
2
PC801
DL
+5VALW
U
k
o
o
b
10K_0402_1%
5
PGOOD
s
e
.
3
2
1
VDD
FB
PR812
BST
PR808
15K_0402_1%
TRIP_VCCSA
1
2
10
PR810
+5VS
TP
11
PR802
9.09K_0402_1%
+3VS
PR811
0_0402_5%
14
ILIM
FB_VCCSA_A
LX
VCC
680_0402_1%
PC808
4.7U_0603_10V6K
OUT
LX_VCCSA
FB_VCCSA5
UG_VCCSA
12
PGND
PR801
PC807
0.1U_0402_10V7K
13
PR807
100_0402_1%
PQ801
AON7408L_DFN8-5
4
DH
TON
AGND
+5VALW 1
+VCCSAP
+5VALW
VOUT_VCCSA
2
0_0402_5%
V5FILT_VCCSA
EN_SKIP
PU801
PR805
255K_0402_1%
1
2TON_VCCSA 2
15
PR804
2.2_0402_5%
BST_VCCSA
1
2BST1_VCCSA1
1
PR806
2
PC802
10U_0805_25V6K
PC804 @
0.1U_0402_10V7K
PR803
B+
PL802
HCB1608KF-121T30_0603
2
1
2200P_0402_50V7K
PC805
0_0402_5%
1SNUB_VCCSA 2
10,28,33,35,39,41 SUSP#
EN_VCCSA
PC810
680P_0603_50V7K
VTTPWRGOOD
@ PR821
2
VCCSA_SENSE 10
PJP801
+VCCSAP
100K_0402_5%
PR815
1
PR816
5.1K_0402_1%
1 1
2
PQ803
VCCSA Vout
0.9V
0.8V
FB_VCCSA
SSM3K7002FU_SC70-3
10K_0402_5%
100K_0402_5%
VID[1]
0
1
VID[0]
0
0
PR818
1
PQ906
PMBT2222A_SOT23-3
PR819
10 VCCSA_SEL
+VCCSA(6A,240mils ,Via NO.= 12)
2
PAD-OPEN 4x4m
PR814
2
1
10K_0402_5%
PC811
0.01U_0402_16V7K
PR813
10K_0402_5%
Compal Secret Data
2010/05/17
Issued Date
Deciphered Date
2011/05/17
Title

SCHEMATICS,MB A6731
Custom
Rev
D
401968
Date:
Sheet
1
43
of
45
CPU_B+
UGATEG
470K_0402_J_NCP18WM474J03RB
PQ210
BOOT2 2
2.2_0603_5%
+5VALW
1
2
VGN1VGN1
VGN3
PC234 @
470P_0402_50V7K
590_0402_1%
PC255 @
0.01U_0402_16V7K
ISNG
4
PQ205
3
2
1
AON6788 1N
PL203 @
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
LF3 2
1
+
2
PC219
+CPU_CORE
@ PR230
2
1ISEN1
10K_0402_1%
V3N
@ PR229
2
1
10K_0402_1%
B+
1
100U_25V_M
PC218
PL205
HCB2012KF-121T50_0805
2
1
PL206
HCB2012KF-121T50_0805
2
1
100U_25V_M
PC239
0.1U_0402_25V6
2
1
PC210
10U_0805_25V6K
2
1
PC240
PR228
2
1CPU_SNUB3
2
1
4.7_1206_5%
CPU_B+
CPU_B+
@ PR232
VSUM+ 2
@ PR233
2
1ISEN2
10K_0402_1%
3.65K_0805_1%
@ PR238
VSUM-
1
1_0402_5%
PC247
0.1U_0402_25V6
2
1
PC244
2200P_0402_50V7K
2
1
CPU_B+
LF2 2
+CPU_CORE
ISEN2
PR249
2
1
10K_0402_1%
PR251
VSUM+ 2
1
3.65K_0805_1%
PR250
2
1
10K_0402_1%
ISEN1
@ PR252
2
1
10K_0402_1%
ISEN3
PR255
VSUM-
1
1_0402_5%
PR260
2
1UGATE1_1
0_0603_5%
4
PQ201
AON6428L_DFN8-5
PL201
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
PHASE1
BOOT1
2
2.2_0603_5%
PC269
1BOOT1_1 2
1
0.22U_0603_10V7K
LGATE1
3
2
1
PQ202
AON6788 1N
LF1
+CPU_CORE
3
V1N
PR264
PC270
PR263
2
1CPU_SNUB1 2
1
4.7_1206_5%
680P_0603_50V7K
VSUM-
PC262
0.1U_0402_25V6
2
1
PC201
10U_0805_25V6K
2
1
PC202
10U_0805_25V6K
2
1
UGATE1
PC261
2200P_0402_50V7K
2
1
CPU_B+
5
2.61K_0402_1%
1
PR256
100_0402_1%
PR220
680P_0603_50V7K
3
2
1
3
2
1
0.22U_0603_10V7K
VSUM+
330P_0402_50V7K
PC249
1BOOT2_1 2
1
0.22U_0603_25V7K
PH201
@ 100_0402_1%
PL202
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
1_0603_5%
@ PC267
@ PR262
2
1 CPU_N_003 2
1
ISEN3
PQ204
LGATE2
.1U_0402_16V7K
1 PR214
V2N
PR247
PR248
PC254
PR246
2
1CPU_SNUB2 2
1
4.7_1206_5%
680P_0603_50V7K
0_0603_5%
PC209
10U_0805_25V6K
2
1
2BOOT3_1
CPU_B+
2
11K_0402_1%
PC230
.1U_0402_16V7K
1
2
AON6428L_DFN8-5
PHASE2
PQ208 @
AON6788 1N
PR244
1.69K_0402_1%
1.5K_0402_1%
PR261
1
PR241
2
1UGATE2_1
0_0603_5%
1 PR212
PC205
10U_0805_25V6K
2
1
PC206
10U_0805_25V6K
2
1
2
1
PR243
3
2
1
0_0603_5%
UGATE2
LGATE3
0_0402_5%
PR208
1_0402_5%
PH202
PC224
10KB_0402_5%_ERTJ1VR103J
VGN2 1
2
1
2
PR210
1
2
7.5K_0402_1%
AON6428L_DFN8-5
e
s
r
e
v
i
+5VALW
2
+VGFX_CORE
VGN
PR207
10K_0603_1%
s
e
.
PQ207 @
1U_0603_10V6K
1U_0603_10V6K
PC243
2
1
BOOT1
UGATE3_1
PR231
0_0402_5%
1
2
PC242
1
UGATE1
0.22U_0603_10V7K
BOOT3
PC233
2
1
FCCM_CPU 2
3
2
1
PC266
0.01U_0402_16V7K
GND
UGATE3 2
1
0_0603_5%
10KB_0402_5%_ERTJ1VR103J
PHASE3
.1U_0402_16V7K
PC263
2
1
330P_0402_50V7K
PWM PHASE
2LFG
CPU_B+
ISL6208CRZ-T_QFN8
9 VSSSENSE
1PWM3_CPU1
37
LGG
26
25
PROG1
VIN
UG1
BOOT1
PC258
2
1
0.22U_0603_10V7K
330P_0402_50V7K
9 VCCSENSE
@ PR225
FCCM UGATE
24
23
PHASE1
VIN_CPU
ISUMP
VDD
22
21
VDD_CPU
PC253
1
2
1
0.22U_0603_10V7K
27
316K_0402_1%
2K_0402_1%
LGATE
@
PC237
PROG1_CPU
PR272
1
LGATEG
PHASEG
UGATEG
39
38
UGG
PHG
40
41
PROG2
BOOTG
42
43
ISNG
NTCG
ISUMN
ISUMN_CPU
1
0.22U_0603_10V7K
PH1
1CPU_N_004 2
470P_0402_50V7K
PR258
1
3.24K_0402_1%
PC257
2
BOOT
1 PR234
PC268
2
1
VSUM-
29
28
1U_0603_10V6K
PC251
2
1
PC256
1
LGATE1
LG1
VSSP1
PR259
2
1
11K_0402_1%
1FB1_CPU 2
VCC
PWM3_CPU
30
1U_0603_10V6K
1
0_0603_5%
PR222
16.5K_0402_1%
2
1
PROG2_GFX
NTCG
ISNG
ISPG
e
t
o
N
PC250 10P_0402_50V8J
2
1
PC265
2
1
PC275
2
1
VDDP_CPU
PC264
2
1
150P_0402_50V8J
560P_0402_50V8J
PR254
RTN
NTC_CPU
20
VW
19
NTC
12
VSEN
11
18
VR_HOT#
ISEN1
10
FB_CPU
22P_0402_50V8J
PC259
PR257
1CPU_N_002 2
1
PU202
PR227
@
LGATE2
0.068U_0402_16V7K
@ PR221
2
1
2.2_0603_5%
n
U
k
o
o
b
ISL95831CRZ-T_TQFN48_6X6
17
IMON
ISEN2
PGOOD
16
PWM3
PU201
0.22U_0603_10V7K
499K_0402_1%
RTNG
VR_ON
ISEN3/ FB2
COMP_CPU
2
499_0402_1%
44
31
PC260
2
1
ISPG
32
ISEN1
PC248
2
1
PC273
2
1
VSENG
LG2
VDDP
SCLK
PR242 1
27.4K_0402_1%
1000P_0402_50V7K
10K_0402_1%
PR253
45
33
@ PC252
2
@
1
RTNG
VSSP2
ALERT#
VW_CPU
46
SDA
470K_0402_J_NCP18WM474J03RB
2
VSENG
ISEN2
3.83K_0402_1%
47
PHASE2
FB
PC246
1
PH203
470P_0402_50V7K
2CPU_N_001 1
48
34
13
PR240
FBG
PH2
VGATE 14,20,33
47P_0402_50V1
PGOODG
VR_SVID_CLK
VRON_CPU
PC245
PR245
UGATE2
15
PR239
1
2
499_0402_1%
BOOT2
35
1.91K_0402_1%
VR_HOT#
36
UG2
VR_SVID_ALRT#
0_0402_5%
+3VS
33,36
+1.05VS_VCCP
VR_ON
PR236
0.047U_0603_16V7K
1
PR270
2
33 IMON
7.5K_0402_1%
PC241
2
1
VSSSENSE
1 PR235
BOOT2
IMONG
VWG
ISEN3
33
PR219
@
14
VR_SVID_DAT
COMPG
49
Alert# PU resister need close CPU,

so the PU resister in HW schematic.
but DAT and CLK need close PWM-IC,
so the PU resister in POWER schematic.
VWG 1
COMP
GFX_CORE_PWEGD
GND
PR226
2
1
10K_0402_1%
33
FBG
COMPG
2
1
54.9_0402_1%
PR224
2
1
130_0402_1%
PR223
PC236
.1U_0402_16V7K
1
2
9 VR_SVID_ALRT#
9 VR_SVID_CLK
BOOTG
10K_0402_5%
PR218
1
+5VALW
+3VS
9 VR_SVID_DAT
PR217
2
1
10_0402_1%
0.01U_0402_16V7K
+1.05VS_VCCP
0.22U_0603_10V7K
LGATEG
3
2
1
PC228
2
1
2
PR271
2K_0402_1%
1
PC274
2
1
PC235
2
1
330P_0402_50V7K
VSS_AXG_SENSE
2.2_0603_5%
VCC_AXG_SENSE 10
VSS_AXG_SENSE 10
330P_0402_50V7K
PC229
2
1
+5VALW
0.047U_0603_16V7K
18.2K_0402_1%
PR237
2
1
PR213
PC227
2
1GFX_N_001 2
1
422_0402_1%
680P_0402_50V7K
PC231
PR215
PR216
2
1GFX_N_0022
1
2
1
475K_0402_1%
2.15K_0402_1%
150P_0402_50V8J
IMONG
1BOOTG_1
PQ211
AON6784 1N
330P_0402_50V7K
1
2
39P_0402_50V7K
2
1
BOOTG 2 PR205
2
1
10_0402_1%
PC222
2
1
ISPGISPG
PR209
PC225
1
2
PL204
0.36UH_PCMC104T-R36MN1R15_30A_20%
1
4
AON6428L_DFN8-5
PHASEG
3
2
1
+VGFX_CORE
27.4K_0402_1%
PC226
499K_0402_1%
PR211
@
UGATEG1 4
<Data Sheet>
D
PR202
2
1
0_0603_5%
PC238
2200P_0402_50V7K
2
1
PR204
1
PC272
0.1U_0402_25V6
2
1
GFX_N_003 2
PC232
PR206
2
1GFX_SNUB 2
1
4.7_1206_5%
680P_0603_50V7K
1000P_0402_50V7K
PC223
2
1
1
PR201
2
8.06K_0402_1%
2
1
3.83K_0402_1%
PH204
1
PC271
2200P_0402_50V7K
2
1
NTCG
470P_0402_50V7K
PR203
PC215
10U_0805_25V6K
2
1
PC214
10U_0805_25V6K
2
1
CPU_B+
PC221
2
1
ISEN1
VSUM+
PR265
1
10K_0402_1%
PR266
PR267
1
3.65K_0805_1%
1 ISEN2
10K_0402_1%
@ PR268
2
1 ISEN3
10K_0402_1%
PR269
VSUM-
1
1_0402_5%
Compal Secret Data
Issued Date
20010/05/17
Deciphered Date
20010/05/17
Title
Size
C
Date:

SCHEMATICS,MB A6731
Document Number
Rev
D
401968
1
Sheet
44
of
45
PIR (Product Improve Record)
Revision Change: 0.1 to 0.2

NO DATE PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------------1
08/13
25
Reserve R433
08/13
31
DEL RA17, RA19-->RA19@,
Reserve +3VLW power for VCCPDSW
08/13
17
Add R432,unpop R572,R1530,U47,C869 for HDMI HPD
HDMI HPD design change
08/23
31
change CA9 CA10 to 4.7u(0603)
Audio test
08/23
28
Change
Change
Change
Change
change degug schematic to follow PBL21
08/23
34
09/03
35
change LED(D74,D75,D25,D26) to follow ID and

ME define
Change ODD_EN# from GPIO24 to GPIO68
GPIO24 PU +3VS 10K
EMI demand
09/03
41
Reserve C729,C730,C731,C732 to +3VS
EMI demand
10
09/03
Reserve C330,C311 on H_PWRGD
EMI demand
11
09/03
Reserve C314,C315,C315 on SUSP
EMI demand
12
09/03
Reserve C850,C851, C854 on 5VS
EMI demand
change RA16 to 39.2K
Audio MIC sense from B to A
U142A compare circuit

U142B compare circuit
new Bus switch for 3V system
KB930 programming strap pin
Issue
s
e
.
GPIO Common design
e
s
r
e
niv
U
k
o
o
b

PURPOSE
------------------------------------------------------------------------------------------------------
09/28
31
change MIC1 from onboard MIC to Conn
change onboard MIC.
2
3
10/22
18
swap HP_R and HP_L
error
10/28
20
Del R734, Add R1192 for SUSCLK PD
EC Request, Common Design
10/28
10
R114,R115 change to 1K fro SM_VREF
Follow Intel DG
10/28
R92,R93 change to mount for RSVD6,7
10/28
18
Del T72, Add R193 for PCH_GPIO19,Del R182
Follow Intel DG
10/28
22
change R314 to 1K for NV_CLE
Follow Intel DG
10/28
24
change VCC_SPI to +3VS
10/28
18
add R438(1M) for HAD_SNC_R PD
10
10/28
add C234,C235,C236,C238,C243 for EMI demand
EMI demand
11
10/29
33
add R744,R1211
EC GPIO Common design for USB30_OC# and P_USB#
e
t
o
N
Follow Intel DG
Common DG
Follow Intel DG

PURPOSE
-----------------------------------------------------------------------------------------------------1
12/06
34
Charge LED:del R204, add R270,R271
2
3
12/06
10
change C137 from 470U to 330U for PWR demand
to fit the SPEC
12/06
20
add C316 for EC demand
EC Request, Common Design
12/06
05
XDP:del XDP for ESD demand
ESD DEMAND
12/06
31
MIC:add DA10 A-GND
EMI DEMAND
12/06
23
PCH_GPIO24:add R439 for 3VALW_PCH PU(reserve)
Follow Intel DG
CPU_CORE CAP COST
Issued Date
Compal Secret Data
2010/05/27
2011/03/04
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A6731
Document Number
Rev
D
401968
Sheet
1
45
of
45

PBL10 Project Compal Confidential: LA-6731P Schematic REV1.0

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5

Compal Electronics, Inc.

Compal Secret Data

Mobile Sandy Bridge

1.5V DDRIII 1066/1333

USB/B Right USB/B Left

USB port 0,1

Intel Cougar Point

DC/DC Interface CKT.

Compal Electronics, Inc.

Compal Secret Data

Power Circuit DC/DC

Compal Electronics, Inc.

Compal Secret Data

Adapter power supply (19V)

Battery power supply (12.6V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for GPU

Core voltage for UMA graphic

+0.75VP to +0.75VS switched power rail for DDR terminator

+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

+1.05VS_VCCP to +1.05VS_PCH power for PCH

+1.5VP to +1.5V power rail for DDRIII

+1.5V to +1.5VS switched power rail

+1.5VS to +1.5VSDGPU switched power rail for GPU

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON

+3VALW always on power rail

+3VALW always to KBC

+3VALW to +3V_LAN power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

+5VALW to +5VS switched power rail

+VSBP to +VSB always on power rail for sequence control

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Clock Generator (9LVS3199AKLFT,

BOM configu table

PCH And PCBA table

PCH SM Bus address

PBL10 UMA DUAL 10-100

PCB LA-6731P REV10

PCB LS-6732P REV10

PCB LS-6731P REV10

Compal Secret Data

Compal Electronics, Inc.

Wednesday, March 09, 2011

Compal Secret Data

FAN Control Circuit

Buffered reset to CPU

PU/PD for JTAG signals

DDR3 Compensation Signals

JTAG & BPM

Compal Electronics, Inc.

Wednesday, March 09, 2011

PCI EXPRESS* - GRAPHICS

eDP_COMPIO and ICOMPO signals