The RS232 - Interface

The RS232 - Interface
The heart of the serial interface in the PC is the serial module UART 8250 (Universal Asynchronous Receiver Transmitter). This module allows serial data transmission, during which it takes over every conversion of data from parallel to serial and from serial to parallel. The 8250 contains over 10 internal registers which allow control of the serial interface lines and transmitting and receiving of data. The major part of these registers are used during initializing of the module, while during data transmission, usually only one or two registers are used. The registers of the 8250 are accessed with the assembler command OUT and IN. After initializing the interface, the data, which is transferred to the 8250 through the transmitter register (Transmitter Holding Register), automatically transmits serial so that the main program can devote itself to other tasks. It merely has to check the status register (Line Status Register) before it can transfer another character to the transmitter register
The BIOS-Interface
The BIOS of the PC contains functions which support a serial data transmission. These functions can be used to - without much effort - initialize the serial interface and transmit data.
The RS232 - Interface 1
The BIOS functions are invoked through a software interrupt (INT14h). Upon entering, the register AH must include the function number and DX the serial interface. A detailed explanation can be found in the corresponding BIOS-literature. For simple uses these BIOS functions should be sufficient, nevertheless they are not flexible and quick enough to overcome complex tasks. A system programmer must therefore concern himself in more detail with the programming of the UART if he wishes to realise a data transmission in the background in his appliaction which should run interruption-driven with maximum speed and security, complicated flow control and under various protocols.
Programming the 8250

The 8250 contains 10 internal registers which at first appear to be quite complicated. This complexity vanishes though as soon as one looks closer at these registers. Furthermore, not all registers are used in each situation. The following table lists the registers and their addresses.
Programming the 8250 Register Transmitter Holding Register (THR) Receive Data Register (RDR) Baud Rate Divisor LSB Baud Rate Divisor MSB Interrupt Enable Register (IER) Interrupt Identification Register (IIR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR) Adress (Offset) 0 1)
0 1)
0 2) 1 2) 1 1)
1) Bit 7 in the Line Control Register = 0 2) Bit 7 in the Line Control Register = 1
The RS232 - Interface 3
Initializing
The following 5 registers must be initialized before the serial interface is accessible. These registers are:
q q q q q
Baud Rate Divisor LSB Baud Rate Divisor MSB Line Control Register Modem Control Register Interrupt Enable Register
Please be aware that Bit 7 (DLAB) ot the Line Control Register is set on 1, in order to address the Baud Rate Divisor Register. In all other cases this Bit = 0. In the further course of the data transmission the individual data is transmitted through the Transmitter Holding Register and received through the Receiver Data Register. The Line Status Register informs the application program whether a character can be transmitted or whether a character was received and is ready for fetching. In order to transmit a character, Bit 5 in the Line Status Register is checked. If Bit 5 = 1 then the Transmitter Holding Register is empty, i.e. the 8250 is ready to accept and transmit another character. Whether a character is ready for fetching is ascertained through Bit 0 of the Line Status Register. Here Bit 0 must equal 1.
Baud Rate Divisor

The transmission speed of the serial interface is set by the two Baud Rate Registers.
As a result the divisor value (1 word) is determined through the exact division Divisor = 115200 / Baud rate and the LSB part of the divisor value transferred into the Baud Rate Register LSB and the MSB part to the Baud Rate Register MSB. For initializing in 9600 Baud the above formula gives 115200 / 9600 = 12 = 0Ch. Thus the Baud Rate Register LSB is initialized with OCh and the Baud Rate Register MSB with 00h. As already mentioned, for initializing the Baud Rate Register Bit 7 (DLAB) of the Line Control Register must be set to 1. Example:
MOV MOV OUT MOV MOV OUT MOV MOV OUT AL, DX, DX, DX, AX, DX, DX, AL, DX, 80h IO Reg+3 AL IOReg Divisor AL IOReg+1 AH AL ; ; ; ; ; ; ; Bit 7 Mask Line Control Register Set Bit 7 Baud Rate Register LSB divisor value LSB Baud Rate Register MSB
; MSB
Line Control Register

After completing the setting of the transmission speed, setting the protocol (character length, number of stop Bits, parity etc.) through the Line Control Register must take place. This time Bit 7 must be equal to 0 (DLAB), so that it does not address to the Baud Rate Register MSB
0 CHARACTER LENGTH
0 0 1 1
0 1 0 1
= = = =
5 6 7 8
BITS BITS BITS BITS
STOP BITS 0 = 1 1 = 1.5 IF CHARACTER LENGTH = 5 BITS = 2 IF CHARACTER LENGTH = 6, 7, OR 8 BITS PARITY 0 = GENERATE PARITY BIT 1 = DO NOT GENERATE PARITY BIT PARITY TYPE 0 = ODD 1 = EVEN STICK PARITY 0 = SUPPRESS 1 = IF BIT 3=1 AND BIT 4=0 THEN PARITY BIT ALWAYS 1 IF BIT 3=1 AND BIT 4=1 THEN PARITY BIT ALWAYS 0 IF BIT 3=0 THEN NO PARITY SET BREAK 0 = SUPPRESS BREAK SIGNAL 1 = TRANSMIT BREAK SIGNAL DIVISOR LATCH ACCESS BIT (DLAB) 0 = ADRESS REGISTERS THR, RDR AND IER 1 = ADRESS BAUD RATE REGISTER (LSB AND MSB)
THR - TRANSMITTER-HOLDING-REGISTER RDR - RECEIVER-DATA-REGISTER IER - INTERRUPT-ENABLE-REGISTER
Figure 2-1 Line Control Register
Example:
MOV AL,00000011b ; ; ; ; DX,IOReg+3 ; DX,AL ; Bit mask for 8 data Bits, 1 Stop Bit no parity Line Control Register initialize
MOV OUT
Modem Control Register

The Modem Control Register serves to control the modem line and is initialized in the uninterruptable operating mode with 03h (DTR = 1 and RTS = 1), which for most cases is correct and, if no modems are connected, doesnt interfere. If the serial interface should operate in the interrupt mode (communication in the background), Bit 3 (OUT 2) is to be set to 1. In the Loop Mode, however, Bit 4 is to be set to 1. In the interrupt mode an IRQ line must exist for the interface, through which the interrupt can be invoked. Additionally the 8259 Interrupt Controller must be set (appropriate Bit set to 0) such that an interrupt is invoked through the IRQ line.
ALWAYS 0
1=DTR SIGNAL ON 1=RTS SIGNAL ON OUT 1. (NOT USED) OUT 2. (1 = interrupt enable) 0=NO ACTION 1=LOOP MODE (SELF TEST)
DTR - DATA TERMINAL READY RTS - REQUEST TO SEND
Figure 2-2 Modem Control Register
In the Loop Mode (test mode) each transmitted character is received again by the interface. Thus the operating mode of the interface may be tested. Example:
MOV MOV OUT AL,00001011b ; ; DX,IOReg+4 ; DX,AL ; Bit mask for DTR, RTS OUT2 Modem Control Register initialize
ALWAYS 0
1=INTERRUPT ON RECEIVING CHARACTER 1=INTERRUPT IF THR EMPTY 1=INTERRUPT ON OVERRUN/ FRAMING/ PARITY ERROR OR BREAK SIGNAL 1=INTERRUPT ON CHANGE IN THE MODEM STATUS
IF BIT = 0 THEN THE CORRESPONDING INTERRUPT IS SUPPRESSED.
THR - TRANSMITTER-HOLDING-REGISTER
Figure 2-3 Interrupt Enable Register
Interrupt Enable Register

The 8250 contains several interrupt sources, but can only release one interrupt itself. If OUT2 in the Modem Control Register was set to 1 then the events which would lead to an interruption, can be stopped through the Interrupt Enable Register.
The events possible are:

q q q
Interrupt after receiving a character Interrupt if Transmitter Holding Register empty Interrupt if error while transmitting or if a break signal is detected. Interrupt after a change in the status of the modem line.
Example:
MOV MOV OUT AL,00001111b DX,IOReg+1 DX,AL ; ; ; ; ; Bit mask for all interrupt sources Interrupt Enable Register initialize
Data transmission with the 8250

Three registers are very important during the data transmission:
q q q
Line Status Register Transmitter Holding Register Receiver Data Register
Each piece of data is transmitted through the Transmitter Holding Register and received through the Receiver Data Register. To transmit a character, Bit 5 in the Line Status Register must be checked. If Bit 5 = 1, then the Transmitter Holding Register is empty and the 8250 is ready to accept and transmit another character. Bit 5 has the value 0 as long as a character is being transmitted.
STATUS EXISTS IF BIT = 1 7 6 5 4 3 2 1 0
RECEIVED DATA READY OVERRUN ERROR PARITY ERROR FRAMING ERROR BREAK DETECT TRANSMITTER HOLDING REGISTER EMPTY TRANSMITTER SHIFT REGISTER EMPTY TIME OUT (NOT USED, SET BY BIOS OR SOFTWARE)
Figure 2-4 Line Status Register
Bit 0 of the Line Status Register must be checked for a character to be received. If this Bit is 1, then a character was received and it is ready to be fetched. Bit 0 is reset when the received character has been read out from the Receiver Data Register. A transmission error has occured if Bits 1,2 or 4 of the Line Status Register have the value of 1. A recognition break signal is given through Bit 4. Possible errors during data transmission are:
q
Framing error if e.g. wrong word length, wrong number of data Bits or stop Bits is used. Parity error if the parity setting doesnt match Overrun error if received characters have been overwritten by newly received characters
q q
The status of the modem line may be found through the Modem Status Register. Bits 0...3 show the delta state of the CTS, DSR, RI and DCA lines and Bits 4 to 7 contain the current status of the CTS, DSR, RI and DCD lines.
10
STATUS EXISTS IF BIT = 1 7 6 5 4 3 2 1 0
DELTA CLEAR TO SEND DELTA DATA SET READY DELTA RING INDICATOR DELTA DATA CARRIER DETECT CLEAR TO SEND DATA SET READY RING INDICATOR DATA CARRIER DETECT
Figure 2-5 Modem Status Register
Modem Signals
From computer to modem DTR: informs the modem that the computer is switched on and ready RTS: informs the modem that the program in the computer wants to transmit data From modem to computer DSR: the modem informs the computer that it is switched on and ready. CTS: the modem informs the computer that it is ready to receive data. DCD: the modem informs the computer that it has set up a connection with a remote modem
11
RI: the modem informs the computer that it has identified an incoming call on the telephone line.
The interrupt mode of the 8250

The interrupt mode of the 8250 is selected if the application doesnt have the time to serve the interface (interface status inquiry etc.) and the data transmission must therefore take place in the background. In this case the interrupt mode of the 8250 is set up through the appropriate registers and communication takes place in the background. The 8250 generates an interruption, if the event on the serial interface is monitored by the Interrupt Enable Register. This interruption must then be processed by an interrupt routine. The interrupt routine must be able to manage one or more tasks depending on the setup of the Interrupt Enable Register.
ALWAYS 0
0=INTERRUPT CONDITION PRESENT 1=NO INTERRUPT OCCURED INTERRUPT IDENTIFIER =CHANGE IN MODEM STATUS =THR EMPTY =CHARACTER WAS RECEIVED =OVERRUN/ FRAMING/ PARITY ERROR OR BREAK SIGNAL RECEIVED
0 0 1 1
0 1 0 1
THR - TRANSMITTER-HOLDING-REGISTER
Figure 2-6 Interrupt Identification Register
12
As several events trigger only one Hardware-Interrupt, the interrupt routine is able to receive information through the Interrupt Identification Register about which event triggered the interruption and, depending on this, start the appropriate process. If several events occur simultaneously, then they must be worked off by the interrupt routine successively. In this case, the priority of the interrupt type determines which event is handled first. Bit 0 stays 0 until all events that caused the interruption are processed. Only the first three Bits in the Interrupt Identification Register are important.
q q
Bit 0 has the value 0, if an interrupt exists. Bit 1 and 2 report the Interrupt Code, if Bit 0 = 0.
The Interrupt Code reports information about the interruption type and thus about the priority with which the event is to be treated. Each interrupt type has its own priority. The Interrupt Code 11 has the first priority, the Interrupt Code 10 the second, 01 the third and 00 the fourth priority. The Interrupt Codes have the following interrupt types
Code
11 10 01 00
Priority
1 2 3 4
Typ
Receiver error or break signal is received Character was received Transmitter Holding Register empty Change in modem status
13
For the interrupt mode to be possible, the initialization must occur with the following 6 steps. 1. Initialize Baud Rate Divisor LSB and MSB 2. Set the transmission characteristics in the Line Control Register (Data Bits, Stop Bits etc.) 3. Set Modem Control Register such that the interrupt mode is possible (OUT2=1) 4. Define the events in the Interrupt Enable Register which should be monitored 5. Install the Interrupt Routine on the appropriate interrupt vector 6. Free the appropriate IRQ line in the 8259 Interrupt Controller (e.g. Bit 4=0, fr IRQ4 und COM1) Assuming the Interrupt Enable Register was set up on the interrupt type 10 and the OUT2 line of the Modem Control Register and also the 8259 IC are activated, then the following Interrupt Routine is able, after an interruption from the serial interface, to file the received character in a designated buffer. Example:
TITLE COMISR LOCALS DATA SEGMENT WORD PUBLIC
ASSUME DS:DATA WrPtr dw 0 Buffer db 32 dup (?) DATA ENDS 3F8h ; COM1
IOReg EQU
14
CODE
SEGMENT
BYTE PUBLIC
ISR
; ; MOV DS,AX ; MOV BX,WrPtr ; MOV DX,IOReg ; ; ; IN AL,DX ; MOV Buffer [BX],AL ; INC BX ; MOV AL,020h ; OUT 20h,AL ; POP DS ; POP BX POP AX IRET ; ; ISR ENDP CODE ENDS END
ASSUME CS:CODE PROC FAR PUSH AX PUSH BX PUSH DS MOV AX,SEG Data
; save register
Set data segment of the receiving buffer as new DS fetch write pointer Port address of serial interface fetch character ; file character in buffer inc. write counter load EOI value transmit EOI to 8259 recover register
return to interrupted program
This interrupt routine is quite easy in its operation since it only shows one example how an interrupt routine can process the interruption of the 8250. It can be easily extended to intercept the overflow of the buffer, to execute flow control, to be able to process other events, variable transmit and receive buffers...
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Pin configuration of the RS232-Interface

DB 25 Connector plug
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25
The pin configuration for the DB25 connector plug is as follows:

Pin 1 2 3 4 5 6 7 8 9 20 22 DB25
TXD RXD RTS CTS DSR GND DCD DTR RI
16
DB 9 Connector plug
1 6 2 7 3 8 4 9 5
The pin configuration of the DB9 connector plug is as follows:
Pin 1 2 3 4 5 6 7 8 9
DB9 m DCD RXD TXD DTR GND DSR RTS CTS RI
The abreviations used are explained in the glossary.
17
NULL Modem Connection with DB25
TXD RXD RTS CTS DSR DTR
2 3 4 5 6 20
2 3 4 5 6 20
TXD RXD RTS CTS DSR DTR
GND
GND
18
3-wire NULL Modem with DB25

Important: If only a 3-wire connection is used then the modem line should be short circuited as depicted, otherwise blind interrupts for these lines will result, very often through interfering signals, and unnecessary load will thereby be produced which can negatively influence the data throughput.
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The RS232 - Interface

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The RS232 - Interface

Programming the 8250