This document discusses different processor technologies including Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), and Network on Chip (NoC). It provides details on CISC, which aims to execute multiple low-level operations with a single instruction. RISC is introduced as the opposite of CISC, using a small, optimized set of instructions to enable higher performance. NoC is described as a communication subsystem that improves scalability and power efficiency over conventional interconnects. The document also includes a comparison chart of various microprocessors listing their features.
This document discusses different processor technologies including Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), and Network on Chip (NoC). It provides details on CISC, which aims to execute multiple low-level operations with a single instruction. RISC is introduced as the opposite of CISC, using a small, optimized set of instructions to enable higher performance. NoC is described as a communication subsystem that improves scalability and power efficiency over conventional interconnects. The document also includes a comparison chart of various microprocessors listing their features.
This document discusses different processor technologies including Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), and Network on Chip (NoC). It provides details on CISC, which aims to execute multiple low-level operations with a single instruction. RISC is introduced as the opposite of CISC, using a small, optimized set of instructions to enable higher performance. NoC is described as a communication subsystem that improves scalability and power efficiency over conventional interconnects. The document also includes a comparison chart of various microprocessors listing their features.
This document discusses different processor technologies including Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), and Network on Chip (NoC). It provides details on CISC, which aims to execute multiple low-level operations with a single instruction. RISC is introduced as the opposite of CISC, using a small, optimized set of instructions to enable higher performance. NoC is described as a communication subsystem that improves scalability and power efficiency over conventional interconnects. The document also includes a comparison chart of various microprocessors listing their features.
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Week 2 - Processor Technologies
Complex Instruction Set Computing (CISC)
Complex Instruction set computing (CISC) primary purpose is to enable single instruction to execute a multiple low level operations. Generally a load from memory, arithmetic operation and memory storage. CISC allows capability of multistep operations or addressing using single instructions to address models. CISC was bac! dated from reduced instruction set computer ("ISC) #efore the "ISC concept was introduced, computer architects attempted to bridge semantic gap which designed instruction sets supporting high level programming. $his was done to construct procedure calls, loop control and complex addressing models. $his allowed single instructions to be combined by data structure and array accessory. $hese compact instructions resulted in smaller program si%es and fewer main memory accesses. $his resulted in a large amount of money being saving on the cost of computer memory and dic! storage in early &'()s and onwards. $his meant faster execution in programming productivity which even applied to high level languages as such assembly language. *icroprocessors are still programmed in assembly language for certain applications. Reduced Instruction Set Computing (RISC). "educed instruction set computing is a C+, design and was introduced as opposite to complex which simplified instructions to enable higher performance. $he whole strategy of "ISC was to add simplicity to instructions for much faster execution. "ISC uses a small highly optimi%ed set of instructions, whereas CISC uses more speciali%ed set of instructions. -oad and store architecture is used where memory is normally accessed only through specific instructions by "ISC. Network on Chip .etwor! on a Chip is a communication subsystem on an integrated circuit. .etwor! on a chip can span synchronous and asynchronous cloc! domains or use unloc!ed asynchronous logic. $his technology applies on networ!ing theory and methods to on chip communication. $his has made improvement over conventional bus and cross bar interconnections, compared to other designs. .etwor! on a Chip has been shown to improve scalability in addition to the power efficiency. $his is a Single Chip +CI /ast 0thernet .IC Controller 1*'&)21 Comprison o! "rchitectures #or $i!!erent %icroprocessors 3"* is the industry4s leading supplier of microprocessor technology. $hey offer the wide range of microprocessor cores. 3"* are !nown as the 53rchitecture for the 1igital 6orld7 as they have development tools and software for more than 8) billion processors. 3"* are the industries top supplier for ma9ority of application mar!ets and offer the widest range of microprocessors cores for top performance. Cortex application processors are commonly used in mobile internet devices. $hey perform with 82 and (: bit for next generation of mobile internet devices and come in single and multi core. $he processers support the following devices; Smart +hones Smart #oo!s and .et boo!s 0#oo! readers 1igital $< =ome Getaways There are many microprocessors available in the market. They differentiate between manufactures and consumers need to choose wisely depending upon which media device they intend to use. Certain micro processers may need to be used to suit the users needs. Below is a chart which compares and contrasts the important features found on some of the most popular chips in the market today. Trnsistors CP& Speed '2 Cche #ront-Side (us Speed Celeron >,?)),))) &.)( G=% 2 G=% 2?( @#, full speed &88 *=% and :)) *=% Pentium II >,?)),))) 288 *=% :?) *=% ?&2 @#, half speed &)) *=% Pentium III ',?)),))) :?) *=% & G=% 2?( @#, full speed &88 *=% Pentium III )eon 2A,&)),))) ?)) *=% & G=% 2?( @# 2 *#, full speed &)) *=% Pentium * ??,))),))) &.: G=% 8.: G=% 2?( @#, full speed A)) *=% +,-II ',8)),))) ?)) *=% ??) *=% .B3 &)) *=% +,-III 2&,8)),))) :)) *=% :?) *=% 2?( @#, full speed &)) *=% "thlon (+-) 22,))),))) A?) *=% &.2 G=% 2?( @#, full speed 2)) *=% and 2(( *=% "thlon )P 8>,?)),))) &.(> G=% 8A: @#, full speed 2(( *=% $uron .B3 >))A)) *=% (: @#, full speed 2)) *=% PowerPC ./ (,?)),))) 288 *=% 888 *=% ?&2 @#, & *#, half speed &)) *=% PowerPC .* &),?)),))) :)) *=% A)) *=% & *#, half speed &)) *=% "thlon ,* &)?,')),)) ) A)) *=% & *#, half speed &.( G=% .0 ?A,))),))) 2.?G=% ?&2 @# '))*=% &.2?G=% Next .enertion 1rdwre !or Smrt 1omes Since Immerge has produced products which allow users of smart family homes to upload and share media content via the media server. I thought having an voice activation for every hardware device would be useful to launch applications without having to search manually which may save users time and effort. ,sing voice activation for hardware for such $<4s and computers may be most effective. 3 voice recorder device will need to be attached to every system allowing voice commands to be transferred. Giving family users the option to add additional word commands to the device will be useful, since some users may prefer to give commands which is not pre added. =aving security in smart homes is crucial as highly valuable hardware could be in ris! of being stolen. Installing eye scanners in every room may be beneficial for the home users. $he eye scanner will operate by scanning the pattern of each house userCs iris and provided by the software, the main server administrator will have the option to save each house users uniDue pattern. If an stranger enters a room with an unidentified iris pattern, the house users will be alerted via text message. $he server administrator will also be alerted on his computer screen, showing the live recording of the camera in the room the person is currently in. $he iris pattern will automatically be saved on the computer. $he administrator will have software installed giving the option to alert the police immediately within seconds. If there is a case where the administrator is not at home, security buttons will be provided to the house users allowing them to alert the police. References 3rm.com. 2)&:. +rocessors 3"*. EonlineF 3vailable at; http;BBwww.arm.comBproductsBprocessorsBindex.php E3ccessed; ( *ar 2)&:F. 6ebopedia.com. 2)&:. *icroprocessor Comparison Chart 6ebopedia.com. EonlineF 3vailable at; http;BBwww.webopedia.comBDuic!GrefBprocessor.asp E3ccessed; ( *ar 2)&:F. 6i!ipedia. 2)&:. Network on a chip. EonlineF 3vailable at; http;BBen.wi!ipedia.orgBwi!iB.etwor!GHnGChip E3ccessed; &8 *ar 2)&:F. 6i!ipedia. 2)&:. Complex instruction set computing. EonlineF 3vailable at; http;BBen.wi!ipedia.orgBwi!iBComplexGinstructionGsetGcomputer E3ccessed; &8 *ar 2)&:F. 3G, S. 2)&:. 2.2.7 DM9102D: DACM !est. EonlineF 3vailable at; http;BBwww.dacomwest.deBprodu!tauswahlBdavicomBmacphyBdm'&)2d.html E3ccessed; &8 *ar 2)&:F.