Sensorless Current-Mode Control of a Digital Dead-

Beat DC-DC Converter

Anthony Kelly
CAD dept
Analog Devices
Limerick, Ireland
anthony-l.kelly@analog.com
Karl Rinne
Department of Electronic & Computer Engineering
University of Limerick
Limerick, Ireland
karl.rinne@ul.ie

Abstract A digital current-mode controller for dc-dc converters
is introduced. The current-mode loop is sensorless, relying on
constants and internal loop states; removing the need to sense
controlled voltages or currents for the inner loop. Furthermore,
a fast current-mode control mechanism is implemented by
utilizing dead-beat control. The resulting controller is robust and
surprisingly uncomplicated. It is well suited to VLSI integration
in a low geometry process. An interesting aspect of this control
scheme is that it facilitates the application of a low resolution
PWM.
Keywords digital control, dc-dc conversion, pulse width
modulation, sensorless, current mode control.
I. INTRODUCTION
Analog components are predominantly used in dc-dc
converters. However, a Digital controller has several potential
advantages over its analog counterpart [1] and [2], including
flexibility, reliability, integration and the possibility of
automatic tuning. More sophisticated control schemes can be
envisaged in the digital domain, e.g. Vallittu et.al. [1]
envisaged a digital current mode controller that could estimate
the average inductor current, with current measurement used
only as a checking action.
The drawbacks of a digital implementation include the
effects of quantization and latency on system performance.
Latency does not cause a problem for loop stability in a current
mode controller to the same extent as a voltage mode type.
Thats because a current mode control scheme sees the LCR
filters transimpedance, which is a single pole plant, compared
to the two-pole plant of a voltage controlled converter. It will
be shown that the proposed control scheme also reduces the
limit cycle problems related to the PWMs quantization,
therefore a low resolution digital PWM can be used.
A dead-beat control scheme has been proposed for a digital
current-mode DC-DC converter [5] which is independent of
converter operating point and load. The dead-beat control
method for the current-loop, effectively guarantees that the
instantaneous error between the sampled inductor current and
the desired reference current will be reduced to zero after a
specified number of cycles. Chen et.al [6] proposed a similar
method based upon the measurement of inductor current and
two cycle ahead prediction. They further showed that peak,
valley and average current mode control were all feasible using
this technique, and furthermore, that dead-beat control is
equally applicable in buck, boost, and buck-boost topologies.
Current-mode controllers are considered to be superior to
voltage mode controllers [3], due to the fast inner current loop
and its improved dynamics resulting in a more robust control
scheme [9]. However, the measurement of the current in a
L=33H
C
22F
R
22R
I
L
(t)
V
i
=10V
PWM
Digital
Controller
ADC
V
o
(t)
d(n)
ADSP21992
AD1991
Figure 1. Circuit Configuration
current-mode controller can be problematic [4] because of its
susceptibility to noise. The need for current sensing
components increases system cost, and reduces reliability.
Sensorless current mode control overcomes these problems.
Sensorless control of dc-dc converters has been proposed for
analog control [8]. It falls in to the class of observer based
control systems whereby a state-variable such as the inductor
current is synthesized from measured variables such as input-
voltage or load-voltage.
Not sensing the inductor current, makes this a special type
of voltage mode controller. However, the compensation
procedure, its performance, and the presence of an inner loop
are all indicative of current mode control. Therefore this
control scheme has far more in common with traditional
current mode control than with voltage mode control.
Furthermore, the presence of the inner loop severely reduces
the presence of PWM induced limit cycles at the output of the
converter when compared to voltage mode control.
The proposed controller combines the advantages of current
mode control, digital control, dead-beat techniques and
sensorless inductor current estimation, into a unique controller.
It offers simplicity, robustness, high performance and
flexibility. It will be shown that performance is not sacrificed
by adopting the sensorless control scheme.
II. SYSTEM ARCHITECTURE AND PERFORMANCE
Ultimately targeted at VLSI implementation, the controller
has been prototyped using a mixed-signal dsp board combined
with a power stage, as shown in figure 1. Its a standard buck
converter configuration, with a digital controller, and PWM. Of
course, boost and buck-boost configurations are also feasible.
Note that the sensorless nature of the current-loop means that
only the output voltage is sensed, even though this is a current-
mode controller.
Despite the novel control mechanism, this scheme performs
excellently. Figure 2 shows measured transient load regulation
for the circuit of figure 1. The max rated current is 1 Amp. The
measured over/undershoot is less than 80mV for a 0.5A step,
and recovers completely in around 50 s. This compares
favorably with commercially available current mode dc-dc
converters based upon conventional techniques.
III. CONTROL METHOD
The overall control scheme is for all intents and purposes, a
standard dual-loop current mode controller. However in this
case, the inductor current is estimated rather than measured,
and the current controller is a dead beat type. A diagram of the
control scheme is depicted in figure 3. Where, V
os
is the output
voltage setpoint, Ve(z) represents the error voltage in the
discrete time domain, i
ref
(z) represents the reference current
output from the voltage controller in the discrete time domain,
d(z) is the duty cycle, dq(z) is the quantized duty cycle, Vo(t) is
the output voltage from the dc-dc converter power stage, Vo(z)
is the sampled version of Vo(t) following A-D conversion, i
L
(z)
represents the estimated inductor current values and TI(s)
represents the current to voltage relationship of the LCR plant,
its transimpedance, which can be modeled as a single pole in
the current mode controller.
The resolution of the digital PWM is limited. Therefore the
duty cycle value must be quantized to a value which the PWM
can resolve. The quantized duty cycle value in the previous
cycle is utilized in the control process.
The ADC is represented as a sampler in figure 3. For the
purposes of modeling, the ADC has a latency before sampling
and includes offset and gain errors.
The current in the inductor is controlled by a dead-beat
scheme in which a duty cycle is calculated for the next cycle
such that the error between the inductor current expected at the
end of the cycle and reference current, i
ref
(n), is zero. In order
to understand how the dead-beat scheme works, we must
review how the inductor current behaves during the switching
cycle.
Figure 2. Experimental 25% - 75% load steps. L=33H, C=22F, Fs=1MHz, Vin=10V, Vo=2.5V, PWM resolution 1/50 (200mV).
Trace1: 50mV/div vertical scale, 100s/div horizontal scale.
As the digital PWM switches on, over one switching cycle,
as illustrated in figure 4, the inductor current may be expressed
as:

)) ( 1 .( .
) (
). ( .
) ( ) (
) ( ) 1 ( n d T
L
n v
T n d
L
n v n v
n i n i
s
o
s
o i
L L

+ = +

(1)
where i
L
(n+1) is the value of the inductor current at the end
of the cycle n; v
i
(n) and v
o
(n) are the input and output voltages
of the dc-dc converter respectively, Ts is the sampling period
and d(n) is the duty cycle ratio in the nth cycle.
It is possible to rearrange this equation, solving for the duty
ratio, as follows:
[ ]
) (
) (
) ( ) 1 (
). (
) (
n v
n v
n i n i
T n v
L
n d
i
o
L L
s i
+ + =
(2)

A dead-beat controller will exhibit zero steady state error
after a minimum number of sampling instants [7]. We can
derive a one cycle dead-beat control equation for the inductor
current from (2) by noting that i
L
(n+1) must equal the current-
loop setpoint for that cycle i
ref
(n).


[ ]
) (
) (
) ( ) (
). (
) (
n v
n v
n i n i
T n v
L
n d
i
o
L ref
s i
+ =
(3)

Thus, the duty cycle d(n) is calculated in (3) such that the
inductor current at the end of the cycle will be equal to the
desired value; Iref(n), and therefore the error between the
desired value of inductor current and the actual value, is closed
in one-cycle.
As described, the valley current is the controlled state-
variable. It has been shown [6], that the well known problem of
period doubling oscillation in current mode converters can be
eliminated if the choice of PWM modulation strategies (trailing
edge, leading edge, triangle) is matched to the inductor current
control strategy (valley current, peak current, average current).
Thus period doubling oscillation is not exhibited by this
controller, in which a trailing edge PWM modulation strategy
is combined with valley current control. In [6] it was also
shown that the principles apply equally to buck, boost and
buck-boost converter configurations.
As in any conventional dual-loop current mode scheme, the
reference current is set by the voltage loop. In this case we use
a discrete time PI controller as follows:

) 1 ( )] 1 ( ) ( [ ) ( + = n Iref n Ve n Ve K n Iref (4)

where Ve(n) is the error voltage in cycle n, the proportional
gain K
p
=K., the integral gain K
i
=K(1-). In calculating the
values of K and alpha, we assume there is a one-cycle delay
between the sampling and availability of Ve(n), to account for
ADC conversion time and system calculation delay.
A. Sensorless Predictive Current Mode Control
In a practical system, finite time is required for
Hv(z) Hc(z) TI(s)
E(z)
Digital
PWM
s
T
d(z)
) (

z i
L
) (z i
ref

Vo(z)
Vos
Ve(z)

dq(z)
Vo(t)
Figure 4. Inductor Current in cycle n for the experimental circuit
configuration of figure 1.
Figure 3. Overall Control Scheme
) 1 ( + n i
L
s
T n ). 1 ( +
Switch on time dn.Ts
L
n v
o
) (

L
n v n v
o i
) ( ) (

s
T n.
) (n L
i
measurement of i
L
(n) and calculation of d(n). Figure 4 shows
that the inductor current measurement and the calculation of
d(n) must be done in zero time, making such a system non-
causal and therefore unrealizable. However, it is possible to
overcome this limitation by predicting i
L
(n) ahead of time
[5][6]. Furthermore, its possible to envisage a system in which
i
L
(n-1) is also estimated, leading to the concept of sensorless
control of the current loop (5), where the caret is used to
indicate that the inductor current is an estimate.
s
o
s
i
L L
T
L
n v
T n dq
L
n v
n i n i .
) 1 (
). 1 ( .
) 1 (
) 1 (

) (

+ =

(5)
Beginning the inductor current estimation from startup
gives a known value of zero at n=0.
B. Simplification of Equations
For VLSI implementation of the deadbeat current control
equation (3), we would like to rewrite it in terms of constants
to reduce the complexity of the calculation.
[ ]
i
o
L ref
s i
V
V
n i n i
T V
L
n d + = ) ( ) (
.
) (
(6)
In many applications, the input voltage and output voltage
of the dc-dc converter have limited range, and therefore we
propose to use constants in the prediction of the inductor
current also (7).
L
T V
n dq
L
T V
n i n i
S O s i
L L
+ = ) 1 ( .
.
) 1 (

) (

(7)
When in control, the output voltage deviates very little from
its steady-state value. Any constant error in the estimation will
be removed by an integral action in the voltage controller; that
is, the system being of at least type-1. The integral gain in (4),
which is a type-1 controller, dictates the strength of the integral
control action. We may also assume the input voltage is
constant, if required. The work of Chen et al. [6] has shown
that it is reasonable to use constants for the values of Vo and L
in practical circuits, and this has been borne out by experiment.
IV. ESTIMATION ERROR ANALYSIS
It is informative to analyze the inductor current estimation
error. Let us define the estimation error as the actual inductor
current minus the estimated value:
) (

) ( ) ( n i n i n
L L i
L
= (8)
We may write an equation to describe the error at sample
n=1 by substituting (7) and (1) into (8), given that i
L
(0)=0 :
[ ]
[ ] )) 0 ( ) 0 ( ( ) 0 ( )) 0 ( ) 0 ( (
) 1 (
) 1 (
) 0 ( ) 0 ( ) 0 ( ( ) 1 (
o o i i
L
T s
o i
s
i
v v dq v v
L
T
v dq v
L
T
L
+ +
+
+

=

(9)

where the constant values of Vi and Vo are represented as the
actual value plus a time variant delta; T and L represent
deviations in the sample time and inductor values respectively.
This simplifies to:

) 1 ( )) 0 ( ) 0 ( ) 0 ( (
) 1 (
) 1 (
) 1 (
L
L
T
o i
L
T s
i
i v dq v
L
T
L

+
+
=
(10)

For any sample n:

) ( )) ( ) ( ) ( (
) 1 (
) 1 (
) (
1
0
n i j v j dq j v
L
T
n
L
L
T
o
n
j
i
L
T s
i
L

+
+
=

(11)

So the error in the inductor current estimation at any sample
n, is composed of two components. The first is the major error
source, a time variant component which relates to the sum of
all previous errors between the actual voltages and the constant
values assumed. The second term is proportional to the actual
inductor current.
In practice the magnitude of the estimation error will
increase over time, resulting in a constant error voltage in the
steady state, due to the integral action of the controller. In the
example implementation of the system this error could be made
very small.
V. PERFORMANCE COMPARISON TO SENSED CURRENT
MODE CONTROL
It is informative to compare the performance of the
proposed sensorless current mode control scheme to the
traditional sensed method. Comparing the performance through
the use of modeling is advantageous in that inaccuracies in the
practical measurement of current are avoided. Figures 5 and 6
below, illustrate the simulated output voltage and inductor
current for a digital current mode controller where the inductor
current is sensed (fig. 5) and for the proposed sensorless
scheme (fig. 6).
Note the offset due to the inductor current estimation error
in figure 6. The difference in steady state voltage between load
current steps is around 25mV in this simulation of the
sensorless scheme. From the discussion of the estimation error,
it can be concluded that this change in offset is due to the term
proportional to the inductor current in (11). Offset voltage and
gain error in the model of the ADC causes the actual output
voltage in both cases to deviate slightly from the 2.5V setpoint.
VI. DIGITAL PWM
The limit cycle behavior of digital dc-dc control schemes
has been the subject of much attention in the recent past, and is
an active area of research in the field. In the context of voltage
mode control, it is understood that one condition in order to
eliminate limit cycles at the converter output is that the
resolution of the PWM must be greater than that of the ADC
[10][11]. In contrast, in the proposed controller the PWM
resolution can be less than the ADC. In the experimental
design, PWM resolution was 1/50, which corresponds to
200mV for a 10V input. A resolution of as little as 1/20
(500mV in this case) has demonstrated acceptable
performance.
The explanation for this is that the PWM limit cycle occurs
around the inner loop, as the quantized value of the duty cycle,
dq(n), is fed back into the estimated inductor current for the
next cycle. Thus, the estimated inductor current at the end of
the cycle, including the error due to quantization, is taken in to
account when the next duty cycle is calculated. Thus, the
inductor current is controlled over time to match i
ref
, despite
the quantization errors due to the PWM resolution. This gives
rise to a duty cycle frequency comparable to the sample rate as
shown in figure 7. Therefore it is attenuated by the LCR of the
power stage. In the example circuit this attenuation is around
40dB. Thus a 200mV PWM step size gets attenuated to 2mV at
the output of the converter, with the plant effectively averaging
the PWM output to yield the desired output voltage. The
spectrum of PWM quantization error is noise shaped [12].
VII. EXPERIMENTAL RESULTS
The synchronous buck converter circuit of figure 1 was
constructed. The digital controller was prototyped using the
ADSP-21992 mixed signal DSP. The ADSP-21992 is a 16 bit
integer DSP with integrated digital PWMs, 8-channel ADC,
timers, on chip RAM and CAN interface. It executes at up to
160MIPS. The power switch used the AD1991 class-D power
output driver, which integrates the power switches, over-
current protection and thermal shutdown protection for the
Figure 5. Output Voltage (top) and Inductor Current (bottom) when
the Inductor current is sensed.
Figure 6. Output Voltage (top) and Inductor Current (bottom) using
the proposed sensorless scheme.
0 50 100 150 200 250 300 350 400 450
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Figure 7. Quantized duty cycle values, dq(n), in steady state
operation. The y-axis shows the duty cycle value. The x-axis shows
the cycle number. Each cycle corresponds to 1s.
power devices. Component values were: L=33H, C=22F .
Switching frequency and sample rate were 1MHz. The PWMs
operated with a resolution of 20ns (50MHz) based upon a DSP
operation frequency of 100MHz.
The transient load regulation of the system has been shown
in figure 2. With a 25% - 75% load current step, the output is
seen to deviate much less than 5% and recover within 50s.
The line regulation of the system is also excellent, as detailed
in table 1.

Line regulation
Vin
(V)
Vo(V) : (setpoint = 2.5V)
Deviation
(mV)
Deviation
(%)
12 2.532 36 1.4
11 2.516 20 0.8
10 2.496 - -
9 2.471 25 1.0
8 2.442 54 2.2
Table 1. Line regulation of the experimental converter

The behavior of the output voltage during a setpoint change
is shown in figure 8.
VIII. CONCLUSION
A new type of digital controller for switching regulators has
been introduced. The controller combines the advantages of
current mode control, digital control, dead-beat techniques and
sensorless inductor current estimation. Performance is not
sacrificed by adopting the sensorless control scheme. The
experimental implementation of the control scheme as a
synchronous buck converter, demonstrates comparable
performance to known control schemes but offers simplicity
and robustness of digital implementation and sensorless current
control.
It has been demonstrated that the PWM can be of low
resolution compared to digital voltage mode control schemes.
More details of this aspect of the work, and more details on
how it was implemented are expected to published in a future
paper.
Future work will apply the control scheme to a VLSI
controller. Applications of the work outside of dc-dc converters
is also being investigated, and is showing promising results.
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Figure 8. Output voltage of the experimental circuit during a setpoint
change from 4V to 6V to 4V. Vertical scale 1V/div; Horizontal scale
100s/div