Lab 5: Audio Amplifier - Appendix

1. The VBE Multiplier

A V
BE
multiplier, sometimes called an amplified diode, (Figure 2) is used to provide a tunable
voltage between te bases of te !arlingtons "1 and "2. #e purpose of tis voltage is to bias te bases
of te two !arlingtons, $eeping tem in a %sligtl&' () state * a +uiescent current of about 2, mA is
desirable. #uning is obtained troug te use of potentiometer "-V1. #e +uiescent current minimi.es
te .ero crossing distortion associated wit te power stage emitter followers. /ince VBE is a function of
temperature, 01 sould be mounted on te same eat sin$ as "1 and "2 to minimi.e voltage drift.
Figure 2. Vbe 2ultiplier
#e value of te bias sould be about 3 4 V
BE
5 2.6V, enoug to forward bias eac of te four
base*emitter 7unctions in te pair of !arlingtons.
Operation
Assume a current 8 flows down out of node 2. Assume te gain of 01 is ig, so 8
b1
can be
ignored. A current 89 : 8 * 8
E
flows troug -1 and -2.
1
V
R1
= I' R1
V
R2
= I' R2 =
R2
R1
V
BE3
V 2,3 ( ) = V
R1
+ V
R2
= 1+
R2
R1






V
BE3
#us te voltage drop is a multiple of V
BE1
, and is not restricted to being an integral multiple.
B& placing a potentiometer at te base of 01 we can ad7ust te bias to accommodate tolerance variations
between !arlingtons. A capacitor can be used between nodes 2 and 1 to b&pass ac signals so tat te
VBE multiplier provides a simple dc bias.
Example 1
Design a VBE multiplier to provide a 3.0 V bias. Assume I = 2.5 mA ! = 100 and V
BE
= 0." V.

#et t$e resistors $ave standard values %2 = 3.3 &' %1 = 1.0 &'. (r )e *ould let %2 be a 2." &' +ixed
resistor and a 1 &' potentiometer in series. ,$is )ould allo) bias ad-ustment +rom 2.5. V to 3.2. V.
/ote t$at sin*e t$e 2/2222 transistor does not $ave t$e ideal V
BE
o+ 0." V t$e voltage drop a*ross t$e
V
BE
multiplier is not exa*tl0 3.0 V.
)ote tat in E4ample 1 te calculation produced te ratio of -2 to -1. ;ow do &ou coose uni+ue
values< #o get a better feel for te range of appropriate values, loo$ at te ac resistance of te VBE
multiplier=

#is can be derived from te ac e+uivalent circuit of te VBE multiplier. #o produce a nearl& pure
dc voltage drop of a given value &ou would want -2 small, > large and 8
c
large.
Example 2
1al*ulate t$e a* resistan*e o+ t$e VBE multiplier in t$e previous example.

2
I+ t$is value o+ r is too $ig$ 0ou *ould lo)er %2 2and %13 raise I or add a *apa*itor bet)een nodes 2
and 3 )it$ an impedan*e mu*$ less t$an r at t$e +re4uen*ies o+ interest.
2. Bootstrappin
?-eference= #ransistor @ircuit #ecni+ues * !iscrete and 8ntegrated, 1rd ed., A.B. -itcie, @apman and
;all, Condon, 1DD1E
Bootstrapping is a metod of increasing te open loop ?no feedbac$E gain of an amplifier. 8n tis
amplifier, capacitor @3 is te bootstrap capacitor. #e iger te open loop gain, te more accuratel& te
e+uation A
V
: F -
B
G-
A
will predict te closed loop ?wit feedbac$E gain of te audio amplifier using
tis design st&le. @onsider te circuit below, were 01 is used in a common emitter amplifier and 02 is
an emitter follower, or common collector (@@), amplifier.

Figure 1. Bootstrapping E4ample
8f te ac voltage at te collector of 01 is v, ten voltage Av is present at te emitter of 02 and
also at te common terminals of -1 and -3, assuming tat te impedance of @3 is ver& small at te
fre+uencies of interest.
#e gain A of te common emitter amplifier is

#e voltage across resistor -3 is v F Av : (1 F A) v.
/o for ac signals, te resistance of -3 appears to be -39 : -3 G (1 F A), wic is muc iger tan -3
since A is t&picall& 7ust sligtl& less tan 1 for te emitter follower.
/ince -39 is te collector resistance for te common emitter stage, te gain of te @E stage will
become

1
Hitout te bootstrapping, te gain would be

a value muc less tan tat seen if @3 is used.
Example 3. Bootstrapping
Design a 1E511 ampli+ier pair. 1ompare t$e voltage gains )it$ and )it$out bootstrapping.
Assumptions and Design 6arameters
V** = 12 V
I* +or ea*$ transistor is 2.5 mA
! +or ea*$ transistor is 100
%# = 1 &'
lo) +re4uen*0 *uto++ 7 20 89
:se 2/2222 +or simulations
;ee appendix +or detailed *omponent *al*ulations and 6;pi*e +iles
3
<igure =. 1ommon emitter *ommon *olle*tor ampli+iers )it$out bootstrapping.
>it$out bootstrapping 2<igure =3 t$e voltage gain is t$e produ*t o+ t$e gains o+ t$e 1E
stage and t$e 11 stage?

! x %E2 represents t$e input resistan*e o+ t$e *ommon *olle*tor ampli+ier and is t$e load +or t$e
*ommon emitter amp.
>it$ bootstrapping 2<igure 53 t$e *olle*tor resistor o+ t$e *ommon emitter is split into t)o pie*es and
t$e bootstrap *apa*itor 1= is added. ,$e impedan*e o+ 1= s$ould be small in t$e audio +re4uen*0 band.
I
Figure I. @ommon emitter, common collector amplifiers wit bootstrapping. -@ was split in alf and
capacitor @3 added. #e amplitude of te sine wave input was reduced in anticipation of iger gain.
,$e voltage gain o+ t$e ampli+ier pair is A
v
and t$e voltage gain o+ t$e *ommon *olle*tor stage is A.

6lug in t$e *omponent values and solve +or t$e bootstrap gain?

>$ile )e *an s$o) a large in*rease in gain 2a +a*tor o+ nearl0 203 +rom t$e no bootstrap *ase t$e
*al*ulation and simulation do not mat*$. ,$e reason +or t$is is not 0et &no)n.
!eedba"#
Jour te4tboo$ can give &ou a muc more detailed description of feedbac$ in amplifier design
tan will be presented ere. Jou are encouraged to read te appropriate sections.
K
H& use feedbac$ in an amplifier design<
L #e gain is stabili.ed against variations in te parameters of te active devices, so no tuning is
needed regardless of wic #8M12, !arlington transistor 8 coose from te bin, for e4ample. #e
gain of te amplifier is also protected from variations in temperature, supplies, or degradation
wit age.
L #e input and output impedance ma& be selectivel& increased or decreased.
L )on*linear signal distortion is reduced.
L #e midband fre+uenc& range is increased.
#ese last two properties ma$e feedbac$ ver& advantageous for audio circuits.
Mossible disadvantages of using negative feedbac$
L #e gain is reduced greatl& from te open loop case. 8f ig gain is needed, additional
amplification stages will be needed, wit te penalties of si.e and cost.
L #e circuit is more li$el& to go into oscillation.
#ere are several t&pes of feedbac$ and several wa&s te& can be implemented. Mositive feedbac$
results wen te signal being feed bac$ is in pase wit te input signal. )egative feedbac$ occurs wen
te signal being feed bac$ is 16, degrees out of pase wit te input signal. 8n a common emitter or
common collector amplifier, feedbac$ is introduced into te base of te first stage transistor. 8n a
common base design, feedbac$ is introduced into te emitter of te first stage.
/unt Feedbac$ vs. /eries Feedbac$
Nsing an opamp wit open loop gain A
o
to represent te amplifier, we can illustrate several
feedbac$ options.
O
Figure K. /unt negative feedbac$ (left), and series negative feedbac$ (rigt). #e opamps ave open
loop gain A
o
.
For sunt negative feedbac$,

For series negative feedbac$,

@onsidering te sunt case, we can simplif& te gain e+uation and remove (or nearl& so) te
sensitivit& of A
v
to variations in A
o
b& ma$ing A
o
ver& large. 8n tis case, A
v
: *-
B
G -
A
, an opamp
e4pression &ou probabl& remember from &our introductor& course and lab on circuits.
#e audio amplifier in Figure 1 ma$es use of sunt feedbac$. A portion of te output signal is fed
bac$ to te base of 03 in te @E amplifier. )ote tat anoter cange is to remove te top of resistor -I
from te dc suppl& (compare to figure 3 or I). #e bias networ$ now depends on te dc level of te
@lass AB amplifier output (node 1 in figure 1), a value sligtl& iger tan V
cc
G2. -esistor -O determines
te input resistance of te amplifier.
$esin
#e best plan for getting te most understanding of te sudio amplifier would be to design,
simulate and build te circuit of figure 3, modif& it wit bootstrapping (figure I) and ten add feedbac$.
For te sa$e of time, 8 am going to go directl& to te design of te audio amp of figure 1.
!esign /teps
1) !etermine te gain needed. #is will elp decide if &ou need a preamp. #&pical pro7ect specifications
are to produce 3 H into an 6P spea$er from a I, mV pea$ to pea$ input.
A
v
: * V
out
G V
in
6
Find te pea$ voltage needed at te load and compare it to te pea$ input voltage. A BFE# preamp stage
can produce a gain of 2 to 3.
2) !etermine te power suppl& voltage needed. 8f a preamp is needed it would also use tis suppl&
voltage. #o get good s&mmetrical swing, we set te dc voltage at node 1 to be V
cc
G2.

Coo$ at te
voltage drops from te suppl& to te output.

were all te dc voltage drops across te output capacitor. #en

Assume=
"1 : #8M12, )M) !arlington
"2 : #8M12I M)M !arlington
Qeep te voltage drops across -E1 and -E2 small. #ese resistors are present for termal stabilit& onl&,
and &ou sould not waste power in tem. Cet ,.I R V
-E1
, V
-E2
R 1 V.
Hat is te pea$ load current< Hat is te V
@E(sat)
for te )M) !arlington< #e output power
e+uals te product of te rms current and te load resistance=

#e #8M12, !arlington is rated for a continuous 8
@
current of I., A.
#e saturation value of V
@E
depends on te collector current. For te #8M12, !arlington (see a data
seet)=
#able 1. (V
@E
)
sat
vs @ollector @urrent data for #8M12, )M) !arlington #ransistor
8
@
(V
@E
)
sat
D
(A) (V)
,.I ,.OI
1., ,.6I
1., 1.1I
I., 1.3,
Mlug &our values of (8
load
)
pea$
, V
-E1
, -
load
, and (V
@E"1
)
sat
into e+uation 2, and solve for V
cc
.
-ound te suppl& to a common value (IV, 12V, 1IV, etc.). /ince eac !arlington transistor must be
able to witstand te full V
cc
voltage, cec$ tat te V
@E(
specification is at least e+ual to V
cc
plus 1,
to 2, S safet& margin. 8n tis case, te #8M12, and #8M12I eac ave V
@E(
: K, V.
%E& and %E2:
@oose a value between ,.I and 1., V for V
-E1
.

#e power dissipation in te emitter resistors will be (8
load
)
pea$
2
4 -E1, and ma& be a watt or more.
%& and %2:
#e VBE 2ultiplier design must ta$e into account bot te VBE drops across te !arlingtons
and te drops across -E1 and -E2. /o, V(2,1) : 2.6 V T 2V
BE1
. Nse te design procedure discussed
earlier to find -1 and -2.
%' and %(:
#e base current re+uired for te !arlingtons depends on teir minimum
FE
or b.

#e current troug 01 and 03 sould e4ceed tis value b& a margin of 2 to 1,.
#e voltage at node 2 sould be V(2) : V(1) T V
BE1
T 1.3 V. #en
1,
-1 T -3 : (Vcc * V(2)) G 8
c1
. /plit tis value about e+uall& between -1 and -3.
%E(:
8n a normal @E amplifier design, we would ave several volts dropped across -E3. 8n tis case,
since te collector of 03 drives a M)M !arlington, we ave to $eep te drop across -E3 small, oterwise
te voltage swing of te negative pase of te output will be limited (clipped).
Cet V(D) be about ,.I V. #en -E3 : (,.I V) G 8
c1
.
%5 and %):
#e value of -I effects several circuit properties= base bias of 03, gain, and input resistance. #e
voltage at node Vin and te re+uired base bias of 03 are=

#e current in te divider consisting of -I and -K must e4ceed 8
b3(ma4)
b& a factor of 2 to 1,. For a
reasonable input resistance, we want -O on te order of 1 $P. For a gain in te 1,,9s, -I will ave to be
on te order of 1,, $P. 8f -I is too large &ou will not ave sufficient base drive current. 8f -I is too
small, te input resistance (-O) will fall below acceptable values.
@oose several possible values of -I, and tr& te following calculations=

8
-I
must be greater tan 8
b3(ma4)
b& a factor of at least 2. 8f not, ad7ust -I. 8f -O is muc below 1 $P,
&ou migt want to consider adding te BFE# preamp to increase te input resistance and decrease te
gain re+uirement of tis audio amplifier to about 1,,. An alternative would be to reduce te collector
current troug 03. #is reduces te base bias re+uirement, and allows larger values of -I and -O.
%eferen"es
Aibilisco, /. and ). /clater, ed., Enc&clopedia of Electronics, 2nd ed., #AB Mrofessional -eference
Boo$s, Blue -idge /ummit, MA, 1DD,.
-itcie A.B., #ransistor @ircuit #ecni+ues * !iscrete and 8ntegrated, 1rd ed., @apman and ;all,
Condon, 1DD1.
/cubert, #. and E. Qim, Active and )on*Cinear Electronics, Bon Hile&, )ew Jor$, 1DDK.
/edra, A., and Q. /mit, 2icroelectronic @ircuits, 1rd ed., /aunders, Miladelpia, 1DD1.
11
12
Appendix
Amplifier @alculations (Figures 3 and I)
8c : 2.I mA, > : 1,,, -C : 1$P, Vcc : 12 V.
Cet te voltage at te base of 01, V
B
, be about VccG1 or 3 V for good output swing
#en at te emitter of 01, V
E
: 3 * V
BE
: 1.1 V.
Cet 8
E
: 8
@
to simplif& calculations.

Cet te current troug te divider consisting of -1 and -2 be about ten times te 01 base current, or
about ,.18
E
wen > : 1,,.

Cet te drop across 019s collector resistor be about VccG1.

#e dc bias at te base of 02 sould be 6 V. #e emitter voltage sould be O.1 V.

M/pice 8nput Files
@EG@@ Amplifier * no bootstrapping
U nominal gain : *1K,
U /pice e4traction from 2cCogic
@1 1 b1 D1uF
@2 e2 Vout 11uF
-@ Vcc c1 1.K$
-E1 e1 , 1.12$
-E2 e2 , 2.D$
Vin Vin , sin(,V 1,mV 1$;.)
11
Vcc Vcc , 12V
01 c1 b1 e1 02)2222
@E e1 , 1,,,uF
-1 Vcc b1 12$
-2 b1 , 1K$
-C Vout , 1$
02 Vcc c1 e2 02)2222
-s Vin 1 1,,
U Mull te transistor models from te eval librar&
.lib eval.lib
.probe
U -un simulation for 2 c&cles, 2,, points minimum
.tran ,.,2ms 2ms , 1,us
U /ow te output voltage in te dialog bo4 as sim runs
.watc tran V(?VoutE)
.end
UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
UUUU
Bootstrapped @@G@E amplifier
U )ominal gain : *2O,,
U /pice e4traction from 2cCogic
@1 1 b1 D1uF
@2 e2 Vout 11uF
-@1 Vcc 2 6,,
-@2 2 c1 6,,
-E1 e1 , 1.12$
Vin Vin , sin(,V 1mV 1$;.)
Vcc Vcc , 12V
01 c1 b1 e1 02)2222
@E e1 , 1,,,uF
-1 Vcc b1 12$
13
-2 b1 , 1K$
-C Vout , 1$
02 Vcc c1 e2 02)2222
-E2 e2 , 2.D$
-s Vin 1 1,,
@3 2 e2 3,,,uF
U Mull te transistor models from te eval librar&
.lib eval.lib
.probe
U -un simulation for 2 c&cles, 2,, points minimum
.tran ,.,2ms 2ms , 1,us
U /ow te output voltage in te dialog bo4 as sim runs
.watc tran V(?VoutE)
.end
1I