Published in IET Power Electronics

Received on 22nd January 2013

Revised on 23rd July 2013
Accepted on 29th July 2013
doi: 10.1049/iet-pel.2013.0057
ISSN 1755-4535
Extended multilevel converters: an attempt to reduce
the number of independent DC voltage sources
in cascaded multilevel converters
Ebrahim Babaei, Mohammad Farhadi Kangarlu, Mehran Sabahi
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
E-mail: e-babaei@tabrizu.ac.ir
Abstract: The cascaded multilevel converters are the most favorable topologies of multilevel converters. However, they have the
main disadvantage of using multiple independent dc voltage sources. This study proposes new cascaded multilevel converter
topologies in which the number of independent dc voltage sources is reduced. In the proposed topologies, for a specic
number of voltage levels, the number of dc voltage sources is halved. Beside the number of dc voltage sources, in one of the
proposed topologies the number of switches is also reduced in comparison with that of the conventional cascaded multilevel
converter. A new modied pulse-width modulation method is presented to control the proposed topologies. Also, a method
for compensating non-ideality of the dc voltage sources is presented. Simulation results using PSCAD software as well as
experimental results from a laboratory-scale prototype are presented to verify the proposed multilevel converters.
1 Introduction
A multilevel converter is a power electronic system that
synthesises a desired output voltage from several levels of
dc voltages as input [1]. In comparison with the two-level
converters, the multilevel converters have the advantages of
improved output voltage and current quality, lower stress on
the power electronic switches and reduced electromagnetic
interference. They are also capable of operating in higher
voltage/power levels [25].
One of the main types of the multilevel converters is the
cascaded multilevel converters in which several H-bridges
are cascaded. This topology is known as cascaded H-bridge
(CHB) multilevel converter. In the CHB topology, each
H-bridge needs an independent dc voltage source. Therefore
as the number of voltage levels increases, the number of
required independent dc voltage sources goes up. The CHB
multilevel converter can be symmetric [6] or asymmetric [7]
based on the values of the dc voltage sources.
Availability of the dc voltage sources could be a problem
for a CHB multilevel converter. Therefore some researches
have been conducted to reduce the number of the dc
voltage sources in the cascaded topologies and to use the
capacitors instead of dc voltage sources [811]. However,
the control algorithm to equally charge the capacitors
becomes complicated. Moreover, as the charging process is
not perfect, the output voltage may contain undesired
harmonics. This leads to relatively poor quality of the
output voltage. On the other hand, in the approaches
mentioned above, there is one dc voltage source that must
supply all the power needed. Therefore they may not be
suitable for high-power applications. Moreover, the methods
are dependent on the power factor of the load. For high
power factor loads, equally charging of the capacitors may
not be achieved. In [12] a ve-level converter has been
presented which uses one dc voltage source. Other hybrid
ying-capacitors and neutral-point-clamped-based
converters have been presented in [1316] which use
complicated topology and capacitor charging algorithms.
Although, these topologies can use one dc voltage source,
the charging procedure of the capacitors is complicated and
also the topologies have no modularity. Other topology of
multilevel converter has been presented in [17] which use
seriesparalleled dc sources. In this topology, the number of
switching devices is reduced but the number of dc voltage
sources is equal to that of symmetric CHB. The symmetric
[4, 5] and asymmetric [18, 19] multilevel converters with
reduced number of switching devices have been presented
in the literature. However, in the symmetric topology the
number of dc voltage sources is not reduced and in the
asymmetric ones, the unequal distribution of voltage on
the switches makes them unsuitable for high-voltage
applications.
Other approaches to reduce the number of dc sources
include, using isolation transformers in the output of the
H-bridges so that one common dc voltage source can be
used [2022]. However, increased number of the
transformers may result in higher costs.
It is important to note that using only one dc voltage source
is not very interesting especially for high-power applications.
The dc source in this condition is responsible for supplying
full load. One of the main characteristic of the cascaded
topologies is the capability of using multiple sources. This
is an important issue in a way that, in [23] a cascaded
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& The Institution of Engineering and Technology 2013
multilevel converter is presented that doubles the number of
dc sources in order to halve the power of each dc source.
However, in this approach the number of dc voltage sources
increases considerably which may not be economical in
practice. As a conclusion from this discussion, it seems that
both approaches (i) using only one dc voltage source and
(ii) using one dc voltage source for each H-bridge, are not
very effective. Therefore a compromised approach among
the two mentioned approaches is necessary.
This paper proposes new multilevel converter topologies in
both symmetric and asymmetric conditions, that use
considerably lower number of dc sources. Applying the
charge balance control method, the voltage balance between
the capacitors is guaranteed. Simulation results as well as
experimental results verify the proposed multilevel
converters. In the next section, the proposed topologies are
described. Then, the PWM control method of the proposed
topologies is presented and discussed along with a
compensation method of non-ideality of the dc voltage
sources. After a short discussion on the design
consideration, the simulation and experimental results are
presented and discussed.
2 Proposed multilevel converters
2.1 Basic cell
The proposed approach for multilevel converters uses
extension of a basic cell. The basic cell which would be
called a cell is shown in Fig. 1a. This cell consists of two
dc sources and four power electronic switches. The
insulated gate bipolar transistor (IGBT) with anti-parallel
diode is used as switch in this paper. Table 1 indicates the
output voltage of the cell in each switching combination.
Considering this Table, the cell provides full redundancy.
In other words, using proper switching method the power
drawn from the dc sources can be equalised [24]. This
promotes to use only one dc source and two capacitors in
the cell as shown in Fig. 1b. With this technique, the
number of dc sources is halved. To have a proper operation,
the voltage of the capacitors should be balanced. For this
purpose, all of the switching combination must be used.
As shown in Table 1, for the output voltage of V
d
there are
two switching combinations (S
2
, S
3
and S
1
, S
4
) both of
which must be used to balance the voltage of the
capacitors. The typical output voltage and switching
combinations are shown in Fig. 1c.
The cell shown in Fig. 1b can be extended in different ways
to form a multilevel converter. Before discussing on the
extended topologies, it is interesting to investigate the
voltage balance between the capacitors in the cell. Consider
a cell that is connected to an H-bridge supplying an
inductive load as shown in Fig. 1d. In this condition, the
typical output voltage and current of the cell (output
voltage and current of the cell before the H-bridge) would
be as shown in Fig. 1e. The voltage and current waveforms
are the same for the two intervals 0 and 2.
Therefore the current waveform (and also voltage
waveform) in the interval
1

2
is exactly the same as that
of the interval +
1
+
2
. Similarly, the current and
voltage waveforms in the interval
2

1
are exactly the same as those in the interval 2
2

2
1
. Therefore the average power in the interval

2
is equal to that of +
1
+
2
and similarly the
average power corresponding to interval
2

1
is
equal to that of 2
2
2
1
. Therefore the
following equations can be written
_
a
2
a
1
i
0
(t)v
0
(t)
_ _
d(vt) =
_
p+a
2
p+a
1
i
0
(t)v
0
(t)
_ _
d(vt) (1)
_
pa
1
pa
2
i
0
(t)v
0
(t)
_ _
d(vt) =
_
2pa
1
2pa
2
i
0
(t)v
0
(t)
_ _
d(vt) (2)
Consequently, if in the interval
1

2
one of the capacitors
is put to the current path (e.g. C
1
), in the interval +
1

Table 1 Output voltage in each switching combination of the

cell
Switching state S
1
S
2
S
3
S
4
Output voltage, v
o
1 on off on off 0
2 off on on off V
d
3 on off off on V
d
4 off on off on 2V
d
Fig. 1 Topology and operation of the basic cell
a Basic cell
b Basic cell supplied with one dc source
c Typical output voltage and switching combinations of the cell
d Basic cell connected to an H-bridge supplying an inductive load
e Typical output voltage and current of the cell connected to an H-bridge
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+
2
the other one (C
2
) must be put to the current path. The
same is true for the other two mentioned intervals.
It is important to note that the jump in the waveform of i
0
(t)
in the interval
1
is as a result of the fact that in this
interval another path through the switches of the H-bridge is
provided for the inductive output current.
The basic cell can be extended to form multilevel converter
with any number of voltage levels. The extended cells can
have the dc voltage sources with the same values leading to
the symmetric topology. On the other hand, the extended
topology can have dc voltage sources with different value
so that the asymmetric multilevel converter is achieved.
Also, two types of extended topologies are presented. The
extended topologies are presented in the next section.
Considering Fig. 1b, it may be concerned that there is no
path for inductive current if one the switches S
2
or S
4
is
turned off. However, it is important to note that, as the
switches include anti-parallel diodes, when S
2
or S
4
is
turned off, there is a free-wheeling path for inductive
current through the diodes of the switches and therefore
voltage spike will not appear theoretically. To make this
issue clearer, consider Fig. 2 which shows the basic unit in
Fig. 1b with more details. Even if all of the switches are
turned off, there will be a path for both positive and
negative currents to ow. Fig. 2a shows the current path for
positive currents through the diodes D
1
and D
3
(the
transistors are assumed to be off). In the case of the
off-state of the active switches, Fig. 2b shows the path for
negative currents through the diodes D
2
, D
4
and the voltage
source. Therefore there is always a path for current even if
all of the switches are turned off.
2.2 First extended topology
The rst method for extending the cell to form a multilevel
converter is shown in Fig. 3a. In this topology, m cells are
connected in series. In each cell, one dc voltage source is
used and by employing the switching method mentioned
before, the voltage balance between the capacitors is
obtained. It is worth noting that the cascaded cells cannot
generate the negative voltage levels and therefore an
H-bridge is connected to the output of them to change the
polarity of the voltage in each half cycle of the output voltage.
In reference to the value of the dc voltage sources used in
the different cascaded cells, two conditions can be
considered. If the value of all of the dc voltage sources are
equal the proposed topology will be called the symmetric
topology otherwise (i.e. different values for the dc sources)
it will be called the asymmetric topology. These two
conditions are described below.
2.2.1 Symmetric topology: In the symmetric topology
the value of all of the dc sources are assumed to be the
same, that is
V
1
= V
2
= = V
m
= V
d
(3)
In this condition, the following equations can be written
N
level
= 4m +1 (4)
N
switch
= 4m +4 (5)
Fig. 2 Current path in the case of the switches to be turned off
a For positive current
b For negative current
Fig. 3 The proposed extended multilevel converter topologies
a First extended topology
b Second extended topology of the proposed multilevel converter
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N
source
= m (6)
V
o, max
= 2mV
d
(7)
where N
level
, N
switch
and N
source
are the number of output
voltage levels, number of switches and number of dc
sources respectively. Also, V
0, max
is the maximum value of
the output voltage.
In the symmetric condition the cascaded cells are the same
and they use the same switches. Therefore the symmetric
topology offers good modularity.
2.2.2 Asymmetric topology: In order to get more
number of voltage levels with a specic number of
switches, the dc sources may be considered to be different
leading to the asymmetric topology. Various relations can
be considered among the value of the dc sources. One
possible relation can be considered as follows
V
1
= V
d
V
2
= 3V
d
.
.
.
V
m
= 3
m1
V
d
(8)
With these values of the dc sources all of the desired voltage
levels are produced and at the same time maximum number of
levels is obtainable. In this condition, the following relations
can be obtained
N
level
= 2 3
m
1 (9)
V
0, max
= 3
m
1
_ _
V
d
(10)
It is noticeable that in this condition the number of switches
and sources are as (5) and (6), respectively.
Comparing (9) and (4), it is clear that in the asymmetric
condition the number of voltage levels is considerably
increased. However, the cascaded cells are not the same and
therefore the modularity is lost.
2.3 Second extended topology
In the second extended topology, an H-bridge is connected to
each cell and then they are cascaded as shown in Fig. 3b.
Similar to the extended topology, here also two symmetric
and asymmetric conditions can be considered.
2.3.1 Symmetric topology: In the symmetric topology,
the values of the dc sources are considered to be equal. In
this condition, the number of voltage levels, number of dc
sources and maximum value of the output voltage are equal
to those stated by (4), (6) and (7), respectively. In this
topology, the number of switches can be written as follows
N
switch
= 8m (11)
The cascaded cells in this condition are the same which
provides good modularity.
2.3.2 Asymmetric topology: In the asymmetric
topology, the following relation can be obtained between
the values of the dc sources to get maximum number of
voltage levels as well as generating all of the desired
voltage levels
V
1
= V
d
V
2
= 5V
d
.
.
.
V
m
= 5
m1
V
d
(12)
In this condition, the number of the dc sources and switches
are m and 8m, respectively. The number of the output
voltage levels and maximum value of the output voltage
can be written as follows
N
level
= 5
m
(13)
V
0, max
=
5
m
1
2
_ _
V
d
(14)
2.4 Calculation of losses
The power electronic switch losses are calculated in this
section. Mainly two kinds of losses (i.e. conduction and
switching losses) are associated with the switches. Since the
switches include both transistors and diodes, the conduction
loss of a transistor ( p
c, T
(t)) and a diode ( p
c, D
(t)) are
calculated as follows [25, 26]
p
c, T
(t) = V
T
+R
T
i
b
(t)
_ _
i(t) (15)
p
c, D
(t) = V
D
+R
D
i(t)
_ _
i(t) (16)
where V
T
and V
D
are the forward voltage drop of the transistor
and diode, respectively. R
T
and R
D
are the equivalent
resistance of the transistor and diode, respectively and is a
constant related to the specication of the transistor.
The conduction loss of a multilevel converter is sum of
conduction losses of all of the semiconductor devices that
are in current path at the same time. Considering that at
instant t there are N
T
transistors and N
D
diodes in current
path, the average conduction power loss of the multilevel
converter can be written as follows
P
c
=
1
2p
_
2p
0
N
T
(t)p
c, T
(t) +N
D
(t)p
c, D
(t)
_ _
dt (17)
Based on the output voltage value and the direction of the
output current, the number of transistors and diodes in
current path varies. For any specic output voltage and
current, the value of N
T
and N
D
can be determined. These
values are used in a computer program to calculate the losses.
The switching losses are calculated based on the energy
loss calculation. The switching losses occur during turn-off
and turn-on period. For simplicity, the linear variations of
voltage and current of the switches in the switching period
is considered. Based on this assumption, the following
relations can be written [25, 26]
E
off , k
=
_
t
off
0
v(t)i(t) dt
=
_
t
off
0
V
sw, k
t
off
t
_ _

I
t
off
t t
off
_ _
_ _ _ _
dt
=
1
6
V
sw, k
It
off
(18)
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E
on, k
=
_
t
on
0
v(t)i(t) dt
=
_
t
on
0
V
sw, k
t
on
t
_ _

I

t
on
t t
on
_ _
_ _ _ _
dt
=
1
6
V
sw, k
I

t
on
(19)
where E
off, k
and E
on, k
are the turn off and turn -on loss of the
switch k, respectively. t
off
and t
on
are the turn off and turn on
time of the switch, respectively, I is the current through the
switch before turning off, I is the current through the
switch after turning on and V
sw, k
is the off-state voltage on
the switch.
The switching power loss is equal to the sum of all turn on
and turn off energy losses in a fundamental cycle of the output
voltage. This can be written as follows [25, 26]
P
sw
= f

N
switch
k=1

N
on, k
i=1
E
on, ki
+

N
off , k
i=1
E
off , ki
_ _
(20)
where f is the fundamental frequency, N
on, k
and N
off, k
are the
number of turn on and off the switch k during a fundamental
cycle. Also, E
on, ki
is the energy loss of the switch k during the
ith turn-on and E
off, ki
is the energy loss of the switch k during
the ith turn off.
The total loss of the multilevel converter is sum of the
conduction and switching losses as follows
P
loss
= P
c
+P
sw
(21)
3 Comparison
Both of the topologies presented in Figs. 3a and b use lower
number of independent dc voltage sources in comparison with
other cascaded topologies. The proposed topology shown in
Fig. 3a also uses lower number of switches.
Fig. 4a shows the number of dc voltage sources against the
number of voltage levels for the symmetric topologies. As the
gure shows, the proposed topology uses lower number of dc
voltage sources in comparison with the other topologies.
Actually, for any specic number of voltage levels, the
number of dc voltage sources used in the proposed
topology is half of the number of dc voltage sources used
in the other topologies. For the cascade multilevel
converters, providing multiple isolated dc voltage sources is
the main challenge. As the proposed topology uses lower
number of dc voltage sources, it can be a good candidate to
be used instead of cascade multilevel converters. It is
important to note that Fig. 4a is also true for the proposed
second symmetric topology.
Fig. 4b shows the number of switches against the number
of voltage levels for the rst proposed symmetric topology
and other symmetric topologies. As this gure shows, the
proposed topology uses lower number of switches for any
specic number of voltage levels in comparison with the
symmetric CHB topology and that of [17]. However, the
number of switches used in the proposed topology is equal
to that of [4, 5].
4 PWM control of the proposed symmetric
topologies
4.1 Modulation method
In this section, the PWM algorithm is presented to control the
proposed symmetric topologies. It is important to note that the
algorithm should be in a way that the voltage balance between
the capacitors in each cell is provided. The phase-shifted
pulse width modulation (PS-PWM) offers such a
characteristic and therefore it is used to control the
proposed topologies. However, a modication is needed to
be applied in PS-PWM so that it can be used for the
proposed topology. Fig. 5 shows the PS-PWM applied for
the proposed symmetric topology. As the output voltage of
the basic cell is always positive or zero, the absolute value
of the reference waveform is used in modulation and also
the carrier waveforms vary between 0 and 1 (instead of 1
and 1). Two carriers are used for each cell. These two
carriers have a phase angle difference equal to 180. The
carriers of each cell have a phase angle difference equal to
180/m with respect to the carriers of the previous cell.
The carriers are compared with the absolute value of the
reference waveform to achieve the switching pulses of the
switches. Two carriers are dedicated to each cell. For
example, carrier 1 and carrier 2 are used for the rst cell. If
|v
0, ref
| > Carrier1 then the switch S
21
is turned on, otherwise
the switch S
11
is turned on. When |v
0, ref
| > Carrier2 the
switch S
41
is turned on, otherwise the switch S
31
is turned
on. The same description can be given for the other cells.
4.2 Compensating non-ideality of the dc voltage
sources
In most of the studies the dc voltage sources used in
symmetric multilevel converters are supposed to be ideal.
In other words, it is assumed that all of the dc sources have
Fig. 4 Comparison of the proposed multilevel converters with conventional topologies
a Comparison of number of dc voltage sources (for both of the topologies shown in Figs. 3a and b)
b Comparison of number of switches (for the topology shown in Fig. 3a)
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a constant value equal to each other. However, this may not
be the case in practice and the dc voltage sources may have
some variations and uctuations. In this condition, if the
ordinary modulation method is used then the output voltage
quality may be affected. Moreover, the required magnitude
of fundamental frequency component may not be achieved.
Therefore it is necessary to compensate for non-ideality in
the dc sources. To do this, the reference waveform is
modied as follows in order to take into account the
variation of the dc voltage sources.
v
o, ref
=
v
o
(t)
2V
1
(t) +2V
2
(t) + +2V
m
(t)
(22)
where v
0
(t) is the desired output voltage and V
i
(t) is the online
value of the dc voltage source used in the ith basic cell.
To implement this complementary control method, the
value of the dc voltage sources should be measured. In the
proposed topologies, as the number of dc voltage sources
are reduced the required number of measures is also
reduced making the system more economic. It is important
to note that the PS-PWM is still used to provide the gate
signals and only the reference waveform is modied.
Therefore there is not any change in the control method
shown in Fig. 5.
5 Design considerations
In this section, design considerations of the proposed
topologies are presented. In order to design and realise a
power electronic converter, current and voltage ratings of its
switches should be determined. In the proposed multilevel
converter similar to the other multilevel converters, the
current rating of the switches is determined by load. Also,
the current ratings of all of the switches are the same. It is
noticeable that a safety factor should always be considered
to determine the ratings. Therefore the switches current
ratings must be higher than the maximum expected load
current. However, the voltage rating of the switches can be
different from each other. In reference to Figs. 3a and b,
the typical switch S
ij
(i = 1, 2, 3, 4; j = 1, 2, , m) must be
able to withstand the voltage V
j
. Also, the typical switch T
ij
of the topology shown in Fig. 3b must be able to tolerate
voltage equal to 2V
j
. Of course a safety factor must be
considered for safe operation of the switches.
Considering the proposed topology shown in Fig. 3a, the
switches T
1
T
4
have to withstand the whole operating
voltage of the converter. However, these switches operate in
fundamental frequency and therefore they have low stress.
In other words, these switches are low-frequency switches.
Although theses switches are low-frequency, they restrict
the operating voltage level of the converter. Therefore the
proposed topology shown in Fig. 3a is recommended for
lower voltage applications. When designing the multilevel
converter, it is necessary to take into account the
availability of power electronic switches and their ratings.
Although for higher voltage applications the switches can
be connected in series, some problems may arise such as
unequal distribution of voltage across the switches.
Therefore it is preferred not to use the series connected
switches. To satisfy this, the operating voltage of the
converter should be restricted. In general, suppose that the
voltage rating of the available highest-voltage switch is
V
sw, max
. The maximum operating voltage of the converter
can be stated as follows
V
conv, max
=
V
sw, max
a
(23)
where is a factor (larger than 1) to be sure of safe operation
of the switches.
If the current rating of the available switch is I
sw, max
, then
the VA rating of the converter (S
conv, max
) would be as follows
S
conv, max
=
V
sw, max
a

I
sw, max
a
=
V
sw, max
I
sw, max
a
2
(24)
Based on the discussion given above, the proposed
reduced-switch multilevel inverter (Fig. 3a) has limitations
in voltage and power ratings. For example, consider that the
voltage and current ratings of the available switch to be
1200 V (V
sw, max
= 1200 V) and 20 A respectively. can be
chosen based on the most severe operating conditions that
the converter may experience. If voltage spikes (for any
reason) are expected to happen, can be considered a
higher value. As an example = 1.5 2 is suitable to
Fig. 5 PS-PWM control method applied to the proposed topology
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doi: 10.1049/iet-pel.2013.0057
consider the effect of voltage spikes and other sever
conditions. In the example, let take = 1.7, using (24) the
maximum VA rating of the converter will be as follows
S
conv, max
=
1200 20
1.7
2
8304 VA
Although the topology shown in Fig. 3a has the limitation in
the operating voltage, it can be applied for low-voltage
high-quality applications such as dynamic voltage restorer
(DVR) and other custom power devices. Also, in order to
overcome to the mentioned limitation, several units of
Fig. 3a can be cascaded. In this way, the nominal operating
voltage of the multilevel converter is divided between the
cascaded units. Considering that k units are cascaded, the
nominal operating voltage of each unit is equal the nominal
output voltage of the multilevel converter divided by k.
Therefore it will be suitable for high-voltage applications
using low-voltage switches.
It is noticeable that the proposed topology shown in Fig. 3b
has not the restriction mentioned above and it can be designed
for any voltage level. In this topology, the switches T
ij
are
low-frequency switches.
6 Simulation and experimental results
The simulation results of the proposed topologies using
PSCAD/EMTDC are presented to verify them. Beside the
simulation results, the experimental results are also included
to validate the proposed multilevel converters.
6.1 Case study 1
In this case study the rst extended topology is studied. For
this case the converter is supposed to be a 13-level
converter as shown in Fig. 6a. The converter is designed to
produce 220 V RMS (root-mean square) (almost 311 V
peak) 50 Hz output voltage. The converter includes three dc
voltage sources; the value of each one should be almost
equal to 103.7 V. The converter feeds an inductive load
with R = 20 and L = 55 mH. The 13-level converter
shown in Fig. 6a uses 16 IGBTs and three dc voltage
sources whereas the 13-level CHB converter uses 24 IGBTs
and six dc voltage sources.
The PS-PWM algorithm mentioned in Section 4 with the
carrier frequency of 750 Hz is used for modulation.
Fig. 6b shows the simulation results for the converter
shown in Fig. 6a. The upper trace in the gure shows the
output voltage and the lower trace shows the output current.
The output voltage shows that the proposed topology
generates all of the expected voltage levels resulting in a
13-level inverter. The current waveform is sinusoidal and
also has a phase angle difference with respect to the voltage
owing to the inductive characteristic of the load.
Fig. 6 The proposed 13-level inverter and its simulation results
a 13-level inverter based on the proposed rst symmetric topology
b Simulation results, upper: output voltage, lower: output current
Fig. 7 Nine-level converter based on the proposed second
symmetric topology
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6.2 Case study 2
This case study is based on the second extended topology. For
this case, the converter is supposed to be a nine-level
converter and to produce 110 V RMS (155.6 V peak) 50 Hz
output voltage. Fig. 7 shows the nine-level converter based
on the second extended topology. The converter includes
two dc voltage sources that the value of each one is equal
to 77.8 V. The load data is as the same as the previous case.
For the experimental setup, the BUP306D type IGBT with
internal anti-parallel diode is used as switch. Also, to control
the multilevel converter, the switching table of the converter
is stored in the microcontroller ATMEGA32Awhich provides
the gate signals of the switches.
Experimental results of the proposed second extended
topology (Fig. 7) are shown in Fig. 8. Fig. 8a shows the
output voltage and current. Figs. 8b and c show the output
Fig. 8 Experimental results of the proposed nine-level converter
a Output voltage and current
b Output voltage of the rst cell (v
o1
)
c Output voltage of the second cell (v
o2
)
Fig. 9 Simulation results under non-ideal dc voltage sources, from
top to bottom: dc voltages, output voltage and output current
a With applying the compensation of non-ideality of the dc sources
b Without it
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voltage of the rst and second cell, respectively. As the output
voltage waveform indicates, the output voltage includes the
desired levels and it is a nine-level voltage as it was expected.
In the test condition, the measured output power is about
272 W and the input power is about 295 W. Therefore
efciency of the multilevel converter in the test condition is
about 92%. Based on the calculation given in Section 2.4,
the lost power is obtained 25 W which has a good
correspondence with the measured power loss (23 W).
6.3 Case study 3
This case study is also based on the rst extended topology
shown in Fig. 6a. As it was mentioned before, the dc
voltage sources may not have constant values. Another
simulation case study is done to show the effects of this
condition. In this simulation, the dc voltage sources are
supposed to vary.
Figs. 9a and b show the results for the conditions with and
without applying the compensation method respectively. The
top trace in the gure shows the varying dc voltages. When
the compensation of non-ideality of the dc voltage sources
is applied, the quality of output waveforms improves.
However, this is not very clear in the results shown in
Fig. 9 unless the difference in current waveform. In order to
show the improvement in the quality of output waveforms,
their harmonic spectra are shown in Fig. 10. Figs. 10a and
b show the harmonic spectra of output voltage with and
without applying the compensation method, respectively.
As the gures show, when the compensation is not applied,
the voltage contains considerable low-order harmonics
(second and third). Figs. 10c and d show the current
harmonic spectra in the two conditions. The THD of the
output voltage with and without applying the compensation
method is about 0.73 and 2.8%, respectively. The THD
value of the output current with and without the
compensation method is 0.05 and 1.32%, respectively.
These values show a major improvement in the quality of
output voltage and current when applying the compensation
method.
7 Conclusion
In this paper, new cascaded multilevel converters have been
proposed with the aim of using lower number of
independent dc voltage sources. Also, one of the proposed
topologies uses lower number of switches. The proposed
topologies can be both symmetric and asymmetric. As it
was discussed in the paper, the number of independent dc
voltage sources is halved for a specic number of output
voltage levels. The modulation scheme of the proposed
topologies has been presented based on PS-PWM. Also, a
method of compensating non-ideality of the dc voltage
sources by modifying the reference waveform is presented.
The simulation and experimental results validate the
proposed topology. Also, the results show a considerable
improvement in the quality of output waveforms when the
compensation of non-ideality of the dc voltage sources is
used.
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IET Power Electron., 2014, Vol. 7, Iss. 1, pp. 157166
doi: 10.1049/iet-pel.2013.0057