EE271

Advanced Digital System Design & Synthesis

Introduction
Lets take 2
lectures for this
chapter
Chapter 1: Introduction 1-1
Verification & Synthesis
Verification:
Functional (or logic) verification,
Timing verification,
Layout verification, and
Electrical verification.
Synthesis: Turning a desired circuit described in conventional forms
into a design implementation with basic hardware components
Conventional forms:
VHDL (Very High Speed Integrated Circuits HDL)
Verilog
ABEL (Advanced Boolean Equation Language (for PLDs))
Implementation:
Bit-streams for programmable logic devices
Placement and routing for ASICs
Chapter 1: Introduction 1-2
Chapter 1: Introduction
Moores law in Microprocessors
Transistors on Microprocessors
double every 2 years
An IC made in 2002 could hold about
15,000 chips of the logic density from 1981
1-3
Chapter 1: Introduction
Frequency
1-4
Chapter 1: Introduction
Power will be a major problem
Year
Model Core Clock Speed TDP (W)
1993
Pentium P5 (0.8 m) 66MHz 15.5
1996
Pentium MMX P55C (0.35 m) 233 MHz 17.0
1998
Pentium II 450 Deschutes (0.25 m) 450 MHz 27.1
2001
Pentium III 1400S Tualatin (0.13 m) 1.4 GHz 32.2
2005
Pentium 4 HT 672 Prescott 2M (90 nm) 3.8 GHz 115
2006
Pentium Extreme
Edition 965
Presler (65 nm) 3.73 GHz 130
2008
Core 2 Extreme
QX9775
Yorkfield XE
(45 nm)
3.2 GHz 150
2010
Core i3-560 Clarkdale (32 nm) 3.33 GHz 73
2010
Core i5-680 Clarkdale (32 nm) 3.6 GHz 73
2011
Core i7 3960X
Extreme Edition
Sandybridge-E
(32 nm)
3.3 GHz @ 6 cores 130
2012
Core i7 3770 (22 nm) 3.4 GHz @ 4 cores 77
1-5
Chapter 1: Introduction
Increasing Design Challenges (Courtesy, Synopsys)
250nm 180nm 130nm 90nm 65nm 45nm
Variation
Leakage Power
Signal Integrity
Timing, Area
Timing Closure
7.5M Gates
300MHz
35-45W
42M Gates
1.4GHz
55-75W
55M Gates
2.2GHz
55-95W
125M Gates
3.4GHz
90-105W
188M Gates
3.6GHz
85-95W
1-6
Design Challenges
* EE Times Survey 2006
2/3 of 90/65nm projects delayed due to power issues*
32%
33%
40%
44%
44%
47%
49%
50%
52%
57%
58%
60%
25%
25%
22%
Minimizing die size
IP selection/verification
Tool interoperability
Design for test
Engineering productivity
Analog/Mixed-signal blocks
Design for manufacturability
Meeting cost budgets
Completing functional verification
Lengthy design cycles
Meeting timing budgets
*Meeting power budgets (active/dynamic)
Signal integrity
Managing complexity
*Meeting power budgets (leakage)
How critical issues and challenges become as process geometries continue to shrink?
Chapter 1: Introduction 1-7
Top Issues in 65nm Design (Courtesy, Synopsys)
Power concerns with timing
closure (Multi-V
th
, Multi-V
DD
,
Clock Gating ...)
Power network design becomes
critical (e.g. total rail-to-rail
drop is 50mV)
Flip chip packaging becoming
more common (requiring
extensive flow modification)
Immature libraries, new IP and
advanced design rules
Concurrent optimization of area,
timing, routing, SI, test, and yield
(require full-chip flow)
Transition fault testing becomes
mandatory
Test data volume demands
compression
Physical verification decks 4X
more complex (checks to deal with
photolithography of feature size
well below exposure wavelength)
1 5
2
3
4
6
7
8
Chapter 1: Introduction 1-8
Timing vs. Power vs. Area (Courtesy, Synopsys)
90nm 65nm 45nm
Die Size (mm
2
) 1x 1x 1x
Gate Delay (ps) 1x 0.7x 0.5x
Capacitance (fF) 1x 0.7x 0.5x
Resistance ( ) 1x 2x 4x
Interconnect RC Delay (ps) 1x 2x 5x
Total Area for Repeater Cells 6% 15% 35%
Timing Variability (%) 40% 45% 50%
Voltage (V) 1x 0.85x 0.7x
PowerDyn (W) 1x 0.7x 0.5x
V
TH
(V) 1x .85x .7x
I
OFF
(nA/um) 1x 3x 9x
PowerDyn Density (W/cm
2
) 1x 1.4x 2x
PowerLeak Density (W/cm
2
) 1x 2.5x 6.5x
Power Density (W/cm
2
) 1x 2x 4x
Power Variability (%) 50% 55% 60%
Chapter 1: Introduction 1-9
Cost vs. Revenue: The Rule of 10
Technology Node
IC Development
Cost
IC Revenues
End-equipment
Revenues*
0.35m $1-2M $10-20M $100-200M
0.25m $2-6M $20-60M $200-600M
0.18m $5-10M $50-100M $0.5-1B
130nm $8-12M $80-120M $0.8-1.2B
90nm $10-20M $100-200M $1-2B
65nm $15-30M $150-300M $1.5-3B
45nm $20-50M $200-500M $2-5B
Source: I.B.S. Inc., 2005
Note: * IC products are 10 percent of system value
Chapter 1: Introduction 1-10
Development Costs
Chapter 1: Introduction 1-11
Design Metrics
Performance metrics in designing a digital circuit:
Area (yield and packaging cost)
Speed (latency/delay, cycle-time)
Power consumption/dissipation
Throughput (for pipeline applications)
Reliability
Scalability
Reuse
Integration
Chapter 1: Introduction 1-12
Levels of Design Abstraction
Continuous changes in the way industry does hardware design
Pervasive use of Computer-Aided Design tools
De-emphasis on hand design methods, emphasis on abstract
design representations
Hardware design continue to be closer to software design
Emergence and advancement of semiconductor technologies,
including programmable circuit technology
Design reuse, design integration, design scaling
Cost of a function decreases by 2x per generation
Technology shrinks by 0.7/generation (average)
Integrate 2x more functions per chip per generation, but chip cost does
not increase significantly
Population of design engineers does not double every two years
Chapter 1: Introduction 1-13
Five levels of design abstraction, from high to low
Behavioral/Algorithm Level
Dataflow/Register Transfer Level (RTL)
Gate/Logic Level
Transistor/Circuit Level
Polygon/Layout/Mask (Placement and Routing) Level
Chapter 1: Introduction 1-14
Chapter 1: Introduction
Hardware Abstraction Levels
n+ n+
S
G
D
+
Physical
Transistor/Circuit
Gate/Logic
Module
System
1-15
Behavioral
Forms
Synthesis
Types
Structural
Components
Final Physical
Objects
System Program,
executable
specification
System
synthesis
Processors,
ASICs,
memory, etc.
Printed circuit
boards,
SoC, etc.
Module/
Register-
Transfer
Algorithms,
instruction sets,
flowcharts,
FSM
Architecture/
behavioral/
high- level
synthesis
Datapaths:
Adders,
counters, etc.
Microchips:
Processors, ASICs,
etc.)
Gate/
Logic
1. Boolean
equation
2. FSM
1. Logic
synthesis
2. Sequential
synthesis
1. Gates,
latches
2. flip-flops
Modules: Adders,
registers, counters,
etc.
Transistor
/Circuit
Differential
equations,
current-voltage
diagrams
Several
different type
of synthesis
techniques
Transistors,
resistors,
capacitors,
etc.
Analog & digital
cells: Gates, flip-
flops, etc.
Chapter 1: Introduction 1-16
Elements of Modern Design
Circuit
Technologies
Design
Representations
Integrated Circuit
Types
ASICs
FPGA
Behaviors
Blocks
Gates
Boolean Algebra
Truth Tables
Switches
TTL CMOS
PAL, PLA,
PLD
Chapter 1: Introduction 1-17
Behavioral and Structural Views
Behavioral
view is an
abstract
function
Structural view
is an
interconnection
of parts.
Physical view includes
physical objects with
size and positions
Synthesis
Architecture level
Synthesis
Logic level
Gate level
Physical Design
Physical
view
Chapter 1: Introduction 1-18
Classification of ASICs
PLDs
Cell Based
Gate-Array Based
Programmable
Semi-custom Full-Custom
ASIC
FPGAs
Chapter 1: Introduction 1-19
ASIC and General Purpose IC
Application Specific Integrated Circuit (ASIC)
Designed to perform a particular operation as opposed to
General Purpose Integrated Circuits
Is NOT software programmable to perform a wide variety
of different tasks
Often has an embedded CPU to manage tasks
May be implemented as an FPGA
General Purpose Integrated Circuits:
Programmable microprocessors (e.g. Intel Pentium Series,
Motorola HC-11)
Programmable Digital Signal Processors (e.g. TI TMS 320
Series)
Chapter 1: Introduction 1-20
Full Custom ASICs
Every transistor is designed and drawn by hand (placing
transistors, sizing transistors, routing wires)
Typically only way to design analog portions of ASICs
Gives the highest performance but the longest design time
Gate-Array Based ASICs
Transistors level masks are fully defined and the designer
can not change them
The designer programs the wiring to implement the desired
function
The designs are slower than cell-based designs but the
implementation time is faster (less time in the factory)
RTL-based methods and synthesis together with other CAD
tools are often used for gate arrays.
Chapter 1: Introduction 1-21
Programmable Logic Devices (PLDs)
Off-the-shelf ICs that can be programmed by the user to
perform various functions (usually just combinational
logic functions)
There are no custom mask layers so final design
implementation is a few hours instead of a few weeks
Mostly are used for simple functions
Field Programmable Gate Arrays (FPGAs)
Off-the-shelf chips that the user programs to perform
simple functions (but more complex than PLDs)
Capable of capturing 100,000+ designed gates
Store logic in look-up table (RAM) with programmable interconnect
High power consumption, high (area) cost per-unit
Chapter 1: Introduction 1-22
Standard-Cell-Based/Cell Based IC (CBIC)/Semi-custom
Standard Cells (AND gates, OR gates, etc...) are custom
designed and then inserted into a library. These cells are
wired together using place and route CAD tools
Some standard cells such as RAM and ROM cells, and
some datapath cells (e.g. a multiplier) are wired together to
create macrocells
Custom designed blocks (e.g. microprocessors) might be
mixed in a library too (sometimes called megacells or hard
macros.)
The designs are usually synthesized at RTL level
Less efficient in size and performance but simplifies the
design and reduces the design cost.
Chapter 1: Introduction 1-23
Summary
ASIC Family Custom masks Custom cells
Full-custom Analog / digital All Some
Semi-custom Cell-based (CBIC) All None
Masked gate array Some None
(MGA)
Programmable Field-programmable None None
gate array (FPGA)
Programmable None None
logic device (PLD)
Chapter 1: Introduction 1-24
Overall Process of ASIC Design, Verification,
and Implementation
From ideas to design specifications
Specifications: List of goals that should be achieved in the design such as
process, clock frequencies, clock jitter, power supplies, power dissipation, die
area, operating temperature, etc
Defining functional structure and/or architecture
Developing and verifying HDL model
Synthesizing and optimizing HDL model
Physical implementation
Chapter 1: Introduction 1-25
Overall ASIC Design Flow
HDL Model (Behavioral, RTL)
(VHDL, Verilog, SystemVerilog, SystemC)
Functional Verification
(Test vectors & output data)
Synthesis &
Optimization
(Gate-level netlist)
Functional, Timing,
Formal Verification
(Test vectors & output data)
DFT/BIST
Tech.
Libraries
Transistor-Level
Synthesis & Optimization
(Transistor-level netlist)
Physical Layout &
Optimization
(IC Mask/FPGA Data)
Design Rule Checks (DRC)
Layout Versus Schematic (LVS)
Full-custom
Semi-
custom
Functional, Timing,
Formal Verification
(Test vectors &
output data)
Functional, Timing, Formal Verification
(Test vectors & output data)
Parasitic Extraction
Chapter 1: Introduction 1-26
Overall Standard-Cell Based ASIC Physical Design Flow
Floorplan
(Blocks/chip)
Std. cell
Layout
Libraries
Placement & Routing
Design Rule
Check
Gate-level netlist
Layout versus
Schematic Check
Back
Annotate
Mask Data
Generation
Design
Rules
Chapter 1: Introduction 1-27
Overall Programmable ASIC Physical Design Flow
Map to
FPGA or PLD
FPGA or PLD
Technology
Libraries
Placement & Routing
Gate-level netlist
Timing data/model
generation
Programming Data
Generation
Design
constraints
Chapter 1: Introduction 1-28
RTL Synthesis Flow
HDL
Synthesis
netlist
Logic
Optimization
netlist
Physical
Design
Layout
L
i
b
r
a
r
i
e
s
Testbench
Outputs
Outputs
Outputs
Chapter 1: Introduction 1-29
Verifications
Verification is a reverse process of the design:
Starts from the implementation and confirms that expectations are met
Confirm the design translation from one step to the next is as expected
Two fundamental errors & two major verification tasks
Specification errors and the implementation errors
Design verification and the implementation verification.
Implementation verifications check for the equivalence between different
levels of abstractions generated by the design process.
Specification validation checks for the completeness and consistency of
the specifications.
Errors in a design can be functional errors, timing errors,
layout errors, and electrical errors.
Simulation is a popular technique used for functional and
timing verifications at many design levels
Chapter 1: Introduction 1-30
Simulator is a program which dynamically executes an
abstract design description
Obtain verification of functional correctness and some
timing information before the design is physically
constructed
Easier to probe and debug a simulation than an
implemented design
Simulation cannot guarantee that a design will work
Only as good as the test cases attempted
Does not check electrical errors
Abstracts away some of the realities of a real system
Computer-Aid Simulations
Chapter 1: Introduction 1-31
Two Forms of Simulations
Logic Simulation
Design described in terms of logic gates
Values are 0, 1 (plus others to be introduced)
Good for truth table verification
Timing Simulation Dynamic Timing Analysis
Waveform inputs and outputs
Model of gate delays
Are the waveform shapes what was expected?
Identification of performance bottlenecks
Chapter 1: Introduction 1-32
Gate-Level (logic-level) Simulation
Advantages of gate-level simulation:
Verifies timing and functionality simultaneously
Approach well understood by designers
Disadvantages of gate-level simulation
Computationally intensive - only 1 - 10 clock cycles of
100K gate design per 1 CPU second
Incomplete - results only as good as your vector set - easy
to overlook incorrect timing/behavior
Simulation
driver
(input vectors)
Simulation
monitor
(Waveforms)
Netlist
(circuit)
Chapter 1: Introduction 1-33
Types of Logic Simulators
Logic Simulators
Emulator-based Schematic-based HDL-based
Event-driven Cycle-based Gate System
Chapter 1: Introduction 1-34
Emulators: Design is mapped into FPGA hardware for
prototype simulation. Used to perform hardware/software co-
simulation.
Schematic-based: Design is entered graphically using a
schematic editor
Event-driven (gate/RTL/behavioral) simulations
Verilog: VCS, Silos, NC-Verilog, Turbo-Verilog, etc.
VHDL: VSS, MTI, Leapfrog
Cycle-based (gate/RTL/behavioral) simulations
Since most digital designs are largely synchronous, state elements change
value on active edge of clock
So only boundary nodes are evaluated and internal nodes are ignored
Verilog: Frontline, Speedsim
VHDL: Cyclone
Circuit-level Simulations: Software such as Spice, Advice, etc.
Chapter 1: Introduction 1-35
Optimization Trade-off
Combinational Circuits
Multi-criteria optimization
Multiple objectives.
Delay
Area
max
max
Chapter 1: Introduction 1-36
Sequential Circuits
Delay
Area
max
max
Delay
Area
max
max
Delay
Area
max
max
Chapter 1: Introduction 1-37
Cell Libraries
FPGA has library of logic cells in the form of a design kit
(have no choice)
MGAs (masked gate array) and CBICs (cell based IC) have
three choices:
o ASIC vendor (company that build ASIC)
o Third-party library vendor
o Build your own cell library
An ASIC vendor library is normally a phantom library (the
cells are empty boxes)
Third-party library vendor normally:
Develops a cell library using information about a process supplied by
an ASIC foundry
Include the masks (tooling) that are used to manufacture the ASIC.
Chapter 1: Introduction 1-38
ASIC foundry only provides manufacturing, (ASIC vendor
provides manufacturing and design help)
Standard Cells are usually designed and synthesized from
RTL level
Each cell in an ASIC cell library contains the following
information:
o Behavioral model
o Verilog/VHDL model
o Detailed timing model
o Test strategy
o Circuit schematic
o Cell icon
o Wire-load model
o Routing model / Physical layout
Chapter 1: Introduction 1-39
ASIC designers also need a detailed timing model for each
cell to determine the performance of the critical pieces of an
ASIC (back-end timing)
Library designers/engineers calculate the delay of each cell
by simulation (a process called characterization)
It is too difficult, time-consuming and expensive to build every cell in
silicon and measure the cell delays.
Cell (circuit) schematic (netlist) describes each cell so that cell/library
designers can perform simulation for complex cells
Detailed cell (circuit) schematic is not necessary for all cells,
but enough information is needed to compare the cell
schematic with the layout ("Layout Versus Schematic
(LVS)" check
LVS is to make sure that a layout is workable with cell schematics
Chapter 1: Introduction 1-40
Cell icon, connector and naming information are needed for
each cell if schematic entry is used
Synthesizing an ASIC on different cell libraries is easier by logic
synthesis than by physical synthesis
Wire-load model: A (look-up table) model to estimate the
parasitic capacitance for of wires (nets) in a circuit block
Routing model for each cell is always necessary
But it is very complex for the physical design or layout tools to handle
directly for large cells
Other custom simpler representations of physical layout that contain all
the necessary information are mostly used
Place and route mostly are performed at fabrication
companies (VLSI, TSMC, etc.) or with their assistance
Chapter 1: Introduction 1-41
Standard Cell Libraries
Standard cell libraries are tuned for different performance,
power and area goals.
For low-power design the choice and mix of libraries may have a
significant impact on power, timing and area
One key characteristic of a cell library is cell height measured
in number of tracks, which is the metal one (M1) pitch
Tall track height libraries support more complex routing with larger
drive strength transistors and are tuned for performance (but may have
higher leakage). A tall track height library has 11 or 12 tracks
Low-track height libraries are optimized for area efficiency with lower
drive strength transistors (less appropriate for high-speed). A 7 or 8-track
library is considered as low track height library
Standard track height libraries are designed to give reasonable trade-off
between area efficiency and performance, and are used in most designs.
A standard track height library has 9 or 10 tracks
Chapter 1: Introduction 1-42
Libraries can be built with compatible footprints using
transistors with different threshold voltages:
High-VT libraries exhibit the lowest leakage power at the cost of lower
performance, a good choice for non-timing-critical designs, and for
non-critical paths in higher performance designs
Low-VT libraries are built with high-speed but leaky transistors. They
dissipate higher static and dynamic power as a result.
Regular- or Standard-VT libraries sit in between these and offer lower
performance than the Low-VT transistor versions at reduced leakage and
dynamic power
Libraries can also be further optimized for low static power:
Long channel-length gates can be used to reduce leakage, at some
costs in terms of timing and area
The stack-effect of series transistors inside gates can be exploited to
reduce source-drain leakage across other transistors for more complex
gate structures
Chapter 1: Introduction 1-43
Characterization of Standard Cell Libraries
Standard cells were characterized for various combinations of
process, voltage and temperature conditions (called PVT)
Several copies of the timing models are available: a worst
case (slow process, low voltage, high temperature), best case
(fast process, high voltage, low temperature) and typical
Worst case timing is used for checking setup times
Best case timing is for checking hold times
Characterization is more challenging for 90 nm technology
(and below) and for aggressive low power design
At 90nm and below, wires can be more resistive such that network
impedance can be higher than the output impedance of driving gate
With multi-voltage, voltage scaling and power gating designs,
the supply voltage may vary significantly from gate to gate or
module to module new library models are needed
Chapter 1: Introduction 1-44
Temperature Inversion
Larger saturation current leads to smaller gate delay
1. Saturation current increases linearly with carrier mobility and
quadratically with voltage headroom (V
DD
V
T
)
2. Increasing temperature will decrease mobility and increase voltage
headroom since V
T
drops at higher temperature
Older processes: Increase temperature increase gate delay
The effect of temperature on mobility dominates since (relative) change
in voltage headroom is small in compare to its large value (large V
DD
)
(linear dependent term still dominates quadratic dependent term)
90 nm & below: Increase temperature decrease gate delay
(this is known as temperature inversion)
The effect of temperature on voltage headroom dominate the change in
mobility since (relative) change in voltage headroom is large in compare
to its small value (small V
DD
) (quadratic dependent term dominates linear
dependent term)
Chapter 1: Introduction 1-45