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    Vlsi Test & Testability (Mel 626) Lecture - 1: Gavax Joshi

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    maxxtorr723
    This document discusses VLSI testing and testability. It defines testing as subjecting a system to inputs and checking outputs to verify correct behavior. Verification ensures design correctness through simulation, while testing checks manufactured chips for defects. Testing involves generating test patterns to detect faults using fault models, but these may not cover all real defects. The document outlines the VLSI design and testing process, and provides examples of testing a NAND gate and electrical iron. It discusses test economics and topics that will be covered, such as fault modeling, automatic test pattern generation, and design for testability.

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    Vlsi Test & Testability (Mel 626) Lecture - 1: Gavax Joshi

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    maxxtorr723
    72 views28 pages
    This document discusses VLSI testing and testability. It defines testing as subjecting a system to inputs and checking outputs to verify correct behavior. Verification ensures design correctness through simulation, while testing checks manufactured chips for defects. Testing involves generating test patterns to detect faults using fault models, but these may not cover all real defects. The document outlines the VLSI design and testing process, and provides examples of testing a NAND gate and electrical iron. It discusses test economics and topics that will be covered, such as fault modeling, automatic test pattern generation, and design for testability.

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    simulation based verification

    Original Title

    Lecture 1 16.08.2014 Introduction

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    This document discusses VLSI testing and testability. It defines testing as subjecting a system to inputs and checking outputs to verify correct behavior. Verification ensures design correctness through simulation, while testing checks manufactured chips for defects. Testing involves generating test patterns to detect faults using fault models, but these may not cover all real defects. The document outlines the VLSI design and testing process, and provides examples of testing a NAND gate and electrical iron. It discusses test economics and topics that will be covered, such as fault modeling, automatic test pattern generation, and design for testability.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    72 views28 pages

    Vlsi Test & Testability (Mel 626) Lecture - 1: Gavax Joshi

    Uploaded by

    maxxtorr723
    This document discusses VLSI testing and testability. It defines testing as subjecting a system to inputs and checking outputs to verify correct behavior. Verification ensures design correctness through simulation, while testing checks manufactured chips for defects. Testing involves generating test patterns to detect faults using fault models, but these may not cover all real defects. The document outlines the VLSI design and testing process, and provides examples of testing a NAND gate and electrical iron. It discusses test economics and topics that will be covered, such as fault modeling, automatic test pattern generation, and design for testability.

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    © All Rights Reserved
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    of 28

    VLSI TEST & TESTABILITY

    (MEL G626)
    LECTURE - 1
    GAVAX JOSHI
    INTRODUCTION TO PHILOSOPHY OF
    TESTING
    If anything can go wrong it
    will Murphys law
    Testing a system comprises
    subjecting it to inputs and
    checking its outputs to verify
    whether it behaves as per the
    specifications targeted during
    design.
    3
    VLSI REALIZATION PROCESS
    Determine requirements
    Write specifications
    Design synthesis and Verification
    Fabrication
    Manufacturing test
    Chips to customer
    Customers need
    Test development
    DEFINITIONS
    Design synthesis: Given an I/O function, develop a
    procedure to manufacture a device using known materials
    and processes.
    Verification: Predictive analysis to ensure that the
    synthesized design, when manufactured, will perform the
    given I/O function.
    Test: A manufacturing step that ensures that the physical
    device, manufactured from the synthesized design, has no
    manufacturing defect.
    5
    VERIFICATION VS. TEST
    Verifies correctness of
    design.
    Performed by simulation,
    hardware emulation, or
    formal methods.
    Performed once prior to
    manufacturing.
    Responsible for quality of
    design.
    Verifies correctness of manufactured
    hardware.
    Two-part process:
    1. Test generation: software
    process executed once during
    design
    2. Test application: electrical tests
    applied to hardware
    Test application performed on every
    manufactured device.
    Responsible for quality of devices.
    PROBLEMS OF IDEAL TESTS
    Ideal tests detect all defects produced in the
    manufacturing process.
    Ideal tests pass all functionally good devices.
    Very large numbers and varieties of possible
    defects need to be tested.
    Difficult to generate tests for some real defects.
    Defect-oriented testing is an open problem.
    REAL TESTS
    Based on analyzable fault models, which may not
    map on real defects.
    Incomplete coverage of modeled faults due to
    high complexity.
    Some good chips are rejected. The fraction (or
    percentage) of such chips is called the yield loss.
    Some bad chips pass tests. The fraction (or
    percentage) of bad chips among all passing chips
    is called the defect level.
    EXAMPLE: ELECTRICAL IRON
    Plug it in 220 AC and see if its heating.
    funtional specification, that also partially.
    Safety:
    All exposed metals parts of the iron are grounded
    Auto off on overheating
    Detailed Funtionality
    Heating when powered on
    Glowing of LED to indicate power ON.
    Temperature matching with specification for
    different ranges that can be set using the regulator
    (e.g., woolen, silk, cotton etc.)
    EXAMPLE: ELECTRICAL IRON
    Performance
    Power consumption as per the specification
    Time required to reach the desired temperature when
    range is changed using the regulator
    TEST FOR ONLY ELECTRICAL PARAMETERS
    Test for mechanical parameters, like maximum
    height from which there is resistance to breaking
    of plastic parts if dropped on a tiled floor etc.
    Number of tests performed depends on the time,
    equipments etc. which in turn is decided by the
    target price of the product.
    EXAMPLE: NAND GATE
    Check
    functionality
    Verify
    input/output of
    Table 1
    EXAMPLE NAND GATE
    Delay Test
    0 to 1: time taken by the gate to rise from 0 to 1.
    v1=1, v2=1 changed to v1=1, v2=0; After this change in input, time
    taken by o
    1
    to change from 0 to 1.
    v1=1, v2=1 changed to v1=0, v2=1; After this change in input,
    time taken by o
    1
    to change from 0 to 1.
    v1=1, v2=1 changed to v1=0, v2=0; After this change in input, time
    taken by o
    1
    to change from 0 to 1.
    1 to 0: time taken by the gate to fall from 1 to 0.
    v1=0, v2=0 changed to v1=1, v2=1; After this change in input, time
    taken by o
    1
    to change from 1 to 0.
    v1=1, v2=0 changed to v1=1, v2=1; After this change in input, time
    taken by o
    1
    to change from 1 to 0.
    v1=0, v2=1 changed to v1=1, v2=1; After this change in input, time
    taken by o
    1
    to change from 1 to 0.
    Fan-out capability:
    Number of gates connected at o
    1
    which can be driven by
    the NAND gate.
    EXAMPLE : NAND GATE
    Power consumption of the gate
    Static power: measurement of power when the
    output of the gate is not switching. This power is
    consumed because of leakage current
    Dynamic power: measurement of power when the
    output of the gate switches from 0 to 1 and from 1 to
    0.
    Threshold Level
    Minimum voltage at input considered at logic 1
    Maximum voltage at input considered at logic 0
    Voltage at output for logic 1
    Voltage at output for logic 0
    Switching noise
    Noise generated when the NAND gate switches from
    0 to 1 and from 1 to 0
    Test at extreme conditions
    Performing the tests at temperatures (Low and High
    Extremes) as claimed in the specification document.
    EXAMPLE: NAND GATE
    EXAMPLE: NAND GATE
    Output Characteristics
    a set of I
    DS
    vs V
    DS
    curves for different
    constant values of the gate-source
    voltage V
    GS
    Transfer characteristics
    a set of I
    DS
    vs V
    GS
    curves for different
    values of the substrate-source voltage
    V
    BS
    , at constant V
    DS
    Threshold Voltage Test
    Threshold Voltage obtained in test,
    matches the specifications
    EXAMPLE: NAND GATE
    OPTIMAL QUALITY OF TEST
    Given a digital logic gate, what tests are to be performed
    to assure an acceptable quality of product at reasonable
    price
    Test for the NAND gate should be such that results are
    accurate (say 99% above) yet time for testing is low (less
    than a millisecond)
    DIGITAL TESTING is not testing digital circuits (comprised
    of logic gates)
    DIGITAL TESTING is defined as testing a
    digital circuit to verify that it performs the
    specified logic functions and in proper time.
    VLSI CIRCUIT TESTING VERSUS CLASSICAL
    SYSTEM TESTING
    VLSI testing Classical Systems
    Technology matures and faults
    tend to decrease, a new technology
    based on lower sub-micron devices
    evolves
    Basic technology is matured and
    well testted
    Binned as defective and scrapped
    (i.e. not repaired)
    Diagnosed and repaired
    Yield is low Yield is almost 100%
    Expensive equipments and
    Specialized Manpower
    Simple test setups and Technicians
    All samples to be tested Random sample testing
    Test arrangements in design Rarely required
    Reference:
    http://newsroom.intel.com/community/intel_newsroom/blog/2014/08/11/
    intel-discloses-newest-microarchitecture-and-14-nanometer-
    manufacturing-process-technical-details
    DIGITAL VLSI TEST PROCESS
    AUTOMATIC TEST EQUIPMENT
    These test patters
    are generally
    applied and
    analyzed using
    automatic test
    equipment (ATE).
    Figure 7 shows the
    picture of an ATE
    from Teradyne.
    TAXONOMY OF DIGITAL TESTING
    TAXONOMY OF DIGITAL TESTING
    TAXONOMY OF DIGITAL TESTING
    TEST ECONOMICS
    The basic essence of economics of a product is
    minimum investments and maximum returns. To
    under test economics the investments (price paid)
    and returns (gains) for a VLSI testing process are to
    be enumerated.
    Investments
    1. Man hours for test plan development:
    Expert test engineers are required to make elaborate test
    plans.
    2. CAD tools for Automatic Test Pattern
    Generation
    Given a circuit, binary input patters required for testing is
    automatically generated by commercial CAD tools.
    TEST ECONOMICS
    3. Cost of ATE
    ATE is a multimillion dollar instrument. So cost of
    testing a chip in an ATE is dependent on
    time a chip is tested,
    the number of inputs/outputs pins
    frequency the test patters are to be applied
    At- speed testing by ATE is extremely expensive
    (TRADEOFF)
    4. DFT or BIST circuitry
    RETURNS
    Proper binning of Chips:
    In case of VLSI testing, it is not of much concern
    as how many chips are binned as faulty, rather
    important is how many faulty chips are binned as
    normal
    WHAT WE WILL STUDY?
    Functional and Structural Testing
    Fault Equivalence
    Fault Simulation and Testability Measures
    Fault Simulation
    Testability Measures (SCOAP)
    Combinational Circuit Test Pattern
    Generation
    Introduction to Automatic Test Pattern
    Generation (ATPG) and ATPG
    Algebras
    D-Algorithm
    WHAT WE WILL STUDY?
    Sequential Circuit Testing and Scan Chains
    ATPG for Synchronous Sequential Circuits
    Scan Chain based Sequential Circuit Testing
    Built in Self test (BIST)
    Built in Self Test
    Memory Testing
    Delay test
    Design for Testability (DFT)
    System-on-a-Chip (SoC) test
    Fault diagnosis
    Analog/RF test
    Test issues in nano-technology
    THANK YOU

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