8251 & 8253 Programmable Communication Interface &programmable Interval Timer

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Hi-Q Users Manual for 8251/8253 stud

8251 & 8253
PROGRAMMABLE COMMUNICATION INTERFACE
&PROGRAMMABLE INTERVAL TIMER

1. INTRODUCTION:

The 8251 and 8253 study card incorporates Intels 8251 (programmable communication
Interface) and 8253 (Programmable Interval Timer). This interface is designed to explain all
the facilities available in 8251 & 8253. This manual presents the functional description of
these devices, implementation of the circuit and some simple software examples for using
this card with Hi-Q 86 and 51 trainers.

2. DESCRIPTION OF THE CIRCUIT:
The study card provides 8251 as well as timer section. The interface has got 3 connectors.
J 3 (10 pin FRC right male connector) is used for connecting RS 232 cable to the COM 1
or COM 2 of the system. 10 RED LEDs are provided to indicate the important signals.
6.144 MHz crystal is provided to derive 1.5 MHz clock.

3. JUMPER DETAILS:

GATE1 J10 J2

GATE2 J9 J6

CLK1 J12 J7

CLK2 J8 J2

J11

CONNECTOR DETAILS:

For interfacing the study cards with HIQ-51 and HIQ 86 trainers. Connect 50 core FRC
cable between J 2 of the HQ 51 trainer and J 1 of the 8251&8253 study card. And if connected
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Hi-Q Users Manual for 8251/8253 study card
as 8086 trainer connected between J 8 of the HQ-86 to J 4 of the 8251&8253 Study card. The
interface derives its power Via system connector; no external power supply is required.

THE 8251 PROGRAMMABLE COMMUNICATION INTERFACES:

The 8251 is a programmable chip designed for synchronous and asynchronous serial data
communication, packaged in a 28 pin DIP. Fig 1 shows the block diagram of 8251. It
includes five sections : READ/WRITE CONTROL LOGIC, TRANSMITTER, DATA BUS
BUFFER and MODEM CONTROL.

The control logic interfaces the chip with the MPU, determines the functions of the chip
according to the control word in its register and monitors the data flow. The transmitter
section converts a parallel word received from the MPU in to serial bits and transmits them
over the TXD line to peripherals. The receiver section receives serial bits from a peripheral,
converts them in to a parallel word and transfers it to MPU. The 8251 is a complex device,
capable of performing various functions. For the sake of clarity, this chapter focuses only on
the asynchronous mode of serial I/O, and excludes any discussion of the synchronous mode
and the modem control. The asynchronous mode is often used for data communication
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FIG 1 FUNCTIONAL BLOCK DIAGRAM OF 8251
between the MPU and serial peripherals such as terminals and floppy disks.

READ/WRITE CONTROL LOGIC AND REGISTERS:

This section includes R/W control logic, six input signals, control logic, and three buffer
registers: data register, control register, and status register. The input signals to the control
logic are as follows.

INPUT SIGNALS:
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CS* (Input terminal)
This is the active low input terminal which selects the 8251 at low level when the CPU
accesses.

C/D (Input terminal)
This is an input terminal which receives a signal for selecting data or command words and
status Words when the 8251 is accessed by the CPU.
If C/D =low, data will be accessed.
If C/D =high, command word or status word will be accessed

WR (Input terminal)
This is the active low input terminal which receives a signal for writing transmit data and
control words from the CPU into The 8251.

RD (Input terminal)
This is the active low input terminal which receives a signal for reading receive data and
status words from the 8251.

CLK (Input terminal)
CLK signal is used to generate internal device timing.
CLK signal is independent of RXC or TXC.
However, the frequency of CLK must be greater than 30 times the RXC and TXC at
Synchronous mode and Asynchronous x1 mode, and must be greater than 5 times at
Asynchronous x16and x64 mode.

RESET (Input terminal)
A High on this input forces the MSM82C51A-2 into reset status. The device waits for
the writing of mode instruction. The min. reset width is six clock inputs during the
operating status of CLK.

Control Register: This 16 bit register for a control word consists of two independent bytes:
the first byte is called the mode instruction (word) and second byte is called Command
instruction (word). This register can be accessed as an Output port when the C/D* pin is
high.

Status Register: This input register checks the ready status of a peripheral. This register is
addressed as an input port when the C/D* pin is HIGH. It has the same port address as the
control register.

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Data Buffer: This bi directional register can be addressed as an input port and output port
when the C/D* pin is LOW. Table 1 summarizes all the interfacing and control signals.

CS* C/D* RD* WR*
0 1 1 0 MPU writes instruction in the control register
0 1 0 1 MPU reads status from the status register.
0 0 1 0 MPU outputs data to the data buffer
0 0 0 0 MPU accepts data from the data buffer
1 X X X USART is not selected.
TRANSMITTER SECTION:

The transmitter accepts parallel data from the MPU and converts them in to serial data. It has
two registers: a buffer register to hold eight bits and an output register to convert eight bits in
to a stream of serial bits. The MPU writes a byte in the buffer register is transferred to the
output register. This section transmits data on the TXD pin with a appropriate framing bits
(START AND STOP). Three output signals one input signal and associated with the
transmitter section.

TXD with appropriate framing bits (START & STOP). Three output signals and one input
signal are associated with the transmitter section.

TXD-Transmit Data: Serial bits are transmitted on this line.

TXC*-Transmitter Clock: This input signal controls the rate at which bits are transmitted by
the USART The clock frequency can be 1, 16, or 64 times the Baud.

TXRDY- Transmitter Ready: This is an output signal. When is high, it indicates the buffer
register is empty and the USART is ready to accept a byte. It can be used either to interrupt
the MPU or to indicate the status. This signal is reset when a data byte is loaded in to the
buffer.

TXE- Transmitter Empty: This is an Output signal. Logic 1 on this line indicates that the
output register is empty. This signal is reset when a byte is transferred from the buffer to the
output register.

RECEIVER SECTION:

The receiver accepts serial data on the RXD line from a peripheral and converts them in to
parallel data. The section has two registers: the receiver input register and the buffer register.

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When the RXD line goes LOW, the control logic assumes it is a START bit, waits for half a
bit time, and samples the line again. If the line is stil low, the input register accepts the
following bits, forms a character, and loads it into the buffer register. Subsequently, the
parallel byte is transferred to the MPU when requested. In the asynchronous mode, two input
signals and output signal are necessary, as described below.

RXD- Received Data: Bits are received serially on this line and converted in to a parallel
byte in the receiver input register.

RXC*- Receiver Clock: This is a clock signal that controls the rate at which bits are received
by the USART. In the asynchronous mode, the clock can be set to 1, 16, or 64 times the
Baud.

RXRDY- Receiver Ready: This is an output signal. It goes high when the USART has a
character in the buffer register and is ready to transfer it to the MPU. This line can be used
either to indicate the status or to interrupt the MPU.

INTIALIZING THE 8251:

To implement serial communication, the MPU must inform the 8251 of all details such
as mode; baud, stop bits, parity, etc therefore, prior to data transfer, a set of control words
must be loaded into the 8-bit control register of the 8251. In addition, the MPU must check
the readiness of a peripheral by reading the status register. The control words are divided in
to two formats: mode words command words. The mode word specifies the general
characteristics of operation (such as baud, parity, no. of stop bits), the command word
enables data transmission and /or reception. And the status word provides the information
concerning register status and transmission errors. Figure shows the definitions of these
words.

To initialize the 8251 in the asynchronous mode, a certain sequence of control words must be
followed. After a reset operation (system reset or through instruction), a mode word must be
written in the control register followed by a command word. Any control word written in to
the control register immediately after a mode word will be interpreted as a command word
can be changed any time during the operation. However, the 8251 should be reset prior to
writing a mode word, and it can be reset by using the internal reset bit (D6) in the command
word.

Control Words
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There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)

1) Mode Instruction
Mode instruction is used for setting the function of the 82C51. Mode instruction
Will be in wait for write at either internal reset or external reset. That is, the writing of a
Control word after resetting will be recognized as a mode instruction.
Items set by mode instruction are as follows:
Synchronous/asynchronous mode
Stop bit length (asynchronous mode)
Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous mode)
Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of
Synchronous mode, it is necessary to write one-or two byte sync characters.
If sync characters were written, a function will be set because the writing of sync characters
Constitutes part of mode instruction.

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Fig. 2 Bit Configuration of Mode Instruction (Asynchronous)

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Fig. 3 Bit Configuration of Mode Instruction (Synchronous)

Command
Command is used for setting the operation of the MSM82C51A-2.
It is possible to write a command whenever necessary after writing a mode instruction and
sync characters.
Items to be set by command are as follows:
Transmit Enable/Disable
Receive Enable/Disable
DTR, RTS Output of data.
Resetting of error flag.
Sending to break characters
Internal resetting
Hunt mode (synchronous mode)
The bit configuration of a command is shown in Fig. 4.

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Note: Seach mode for
synchronous
charactors in
synchronous mode.
Fig. 4 Bit Configuration of Command

Status Word
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It is possible to see the internal status of 8251 by reading a status word.
The bit configuration of status word is shown in Fig. 5.

Fig. 5 Bit Configuration of Status Word
Standby Status
It is possible to put the MSM82C51A-2 in standby status
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When the following conditions have been satisfied the MSM82C51A-2 is in standby
status.
(1) CS terminal is fixed at Vcc level.
(2) Input pins other CS, D0 to D7, RD, WR and C/D are fixed at Vcc or GND level
(including SYNDET in external synchronous mode).
Note: When all output currents are 0, ICCS specification is applied.

PIN DIAGRAM OF 8251:

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8253 PROGRAMMABLE INTERVEL TIMER
MCS-85 Compatible 8253
3 Independent 16-Bit Counters
Dc to 2MHz
Programmable counter Modes
Count Binary or BCD
Single +5V supply
24-Pin Dual in Package
The Intel 8253 is a programmable Timer/Counter Chip designed for use as an Intel micro
computer peripheral. It use nMOS technology with a single +5V supply and Packaged in a
24-DIP.It organized as 3 independent 16-Bit counters, each with a count rate of up to 2MHz
all MODES of operation are software programmable.

FUNCTIONAL DESCRIPTION:

General

The 82C54 is a programmable interval timer/counter designed for use with microcomputer
systems. It is a general purpose, multi-timing element that can be treated as an Array of I/O
ports in the system software. The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time delays under software control.
Instead of setting up timing loops in software, the programmer configures the 8253 to match
his requirements and programs one of the counters for the desired delay. After the desired
delay, the 82C54 will interrupt the CPU. Software overhead is minimal and variable length
delays can easily be accommodated. Some of the other computer/timer functions common to
microcomputers which can be implemented with the 8253 are:

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Real time clock
Event counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller

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Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to interface the 8253 to the system bus.
Data is transmitted or received by the buffer up on execution of INPUT or OUTPUT
instructions. The data bus buffer has three basic functions

Programming the MODES of the 8253.
Loading the count registers
Reading the Count Values

Read/Write Logic:
The Read/Write Logic accepts inputs from the system bus and generates control signals for
the other functional blocks of the8253. A1 and A0 select one of the three counters or the
Control Word Register to be read from/written into. A low on the RD input tells the 82C54
that the CPU is reading one of the counters. A low on the WR input tells the 82C54 that the
CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by
CS; RD and WR are ignored unless the 82C54 has been selected by holding CS low.

RD* (Read):
A low on this input informs the 8253 that the CPU is putting data in the form of a counter
value.

WR* (WRITE):
A low on this input informs the 8253 that the CPU is outputting the data in the form of
MODE information or loading counters.

A0, A1:
These inputs are normally connected to the address bus. Their function is to select one of the
three counters to be operated on and to address the control word register for mode selection.

CS* (Chip Select):
A low on this input informs the 8253. No reading or writing will occur unless the device is
selected. The CS* input has no effect upon the actual operation of the counters.

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Control Word Register
The Control Word Register (Figure 2) is selected by the Read/Write Logic when A1, A0 =
11. If the CPU then does a write operation to the 82C54, the data is stored in the Control
Word Register and is interpreted as a Control Word used to define the Counter operation.
The Control Word Register can only be written to; status information is available with the
Read-Back Command.

Counter 0, Counter 1, Counter 2

These three functional blocks are identical in operation, so only a single Counter will be
described. The internal block diagram of a signal counter is shown in Figure 3. The counters
are fully independent. Each Counter may operate in a different Mode. The Control Word
Register is shown in the figure; it is not part of the Counter itself, but its contents determine
how the Counter operates. The status register, shown in the figure, when latched, contains the
current contents of the Control Word Register and status of the output and null count flag.
(See detailed explanation of the Read-Back command.) The actual counter is labeled CE (for
Counting Element). It is a 16-bit presentable synchronous down counter. Count Register).
Both are normally referred to as one unit and called just CR. When a new count is written to
the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic
allows one register at a time to be loaded from the internal bus. Both bytes are transferred to
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the CE simultaneously. CRM and CRL are cleared when the Counter is programmed for one
byte counts (either most significant byte only or least significant byte only) the other byte
will be zero. Note that the CE cannot be written into; whenever a count is written, it is
written into the CR.

The Control Logic is also shown in the diagram. CLK n, GATE n, and OUT n are all
connected to the outside world through the Control Logic.

82C54 System Interface:

The 82C54 is treated by the system software as an array of peripheral I/O ports; three are
counters and the fourth is a control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1 address bus signals of the CPU.
The CS can be derived directly from the address bus using a linear select method or it can be
connected to the output of a decoder.

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FIGURE 3. 8253 SYSTEM INTERFACE

Operational Description
General
After power-up, the state of the 82C54 is undefined. The Mode, count value, and output of all
Counters are undefined. How each Counter operates is determined when it is programmed.
Each Counter must be programmed before it can be used. Unused counters need not be
programmed.

Programming the 82C54
Counters are programmed by writing a Control Word and then an initial count. All Control
Words are written into the Control Word Register, which is selected when A1, A0 =11. The
Control Word specifies which Counter is being programmed. By contrast, initial counts are
written into the Counters, not the Control Word Register. The A1, A0 inputs are used to
Select the Counter to be written into. The format of the initial count is determined by the
Control Word used.

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Control Word Format

A1, A0 =11; CS =0; RD =1; WR =0

DEFINATION OF CONTROL:

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COUNTER LOADING:

The count register is not loaded until the count value is written (one or two bytes, depending
on the mode selected by the RL bits), followed by a rising edge and a falling edge of the
clock. Any read of the counter prior to the falling clock edge may yield invalid data.

MODE DEFINATION:

Mode 0: Interrupt on Terminal Count
Mode 0 is typically used for event counting. After the Control Word is written, OUT is
initially low, and will remain low until the Counter reaches zero. OUT then goes high and
remains high until a new count or a new Mode 0 Control Word is written to the Counter.
GATE =1 enables counting; GATE =0 disables counting. GATE has no effect on OUT.
After the Control Word and initial count are written to a Counter, the initial count will be
loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial
count of N, OUT does not go high until N +1 CLK Pulses after the initial count are written.
If a new count is written to the Counter it will be loaded on the next CLK pulse and counting
will continue from the new count. If a two-byte count is written, the following happens:
(1)Writing the first byte disables counting. Out is set low immediately (no clock pulse
required).
(2)Writing the second byte allows the new count to be loaded on the next CLK pulse.

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This allows the counting sequence to be synchronized by software. Again OUT does not go
high until N +1 CLK pulses after the new count of N is written. If an initial count is written
while GATE =0, it will still be loaded on the next CLK pulse. When GATE goes high, OUT
will go high N CLK pulses later; no CLK pulse is needed to load the counter as this has
already been done.
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Mode 1: Hardware Retrigger able One-Shot

OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin
the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go
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high and remain high until the CLK pulse after the next trigger. After writing the Control
Word and initial count, the Counter is armed. A trigger results in loading the Counter and
setting OUT low on the next CLK pulse, thus starting the one-shot pulse N CLK cycles in
duration. The one-shot is retrigger able; hence OUT will remain low for N CLK pulses after
any trigger. The one-shot pulse can be repeated without rewriting the same count into the
counter. GATE has no effect on OUT. If a new count is written to the Counter during a one-
shot pulse, the current one-shot is not affected unless the Counter is retrigger able. In that
case, the Counter is loaded with the new count and the one-shot pulse continues until the new
count expires.

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FIG 5. MODE 1
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Mode 2: Rate Generator
This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time
Clock Interrupt. OUT will initially be high. When the initial count has decremented to 1,
OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial
count and the process is repeated. Mode 2 is periodic; the same sequence is repeated
indefinitely. For an initial count of N, the sequence repeats every N CLK cycles. GATE =1
enables counting; GATE =0 disables counting. If GATE goes low during an output pulse,
OUT is set high immediately. A trigger reloads the Counter with the initial count on the next
CLK pulse; OUT goes low N CLK pulses after the trigger. Thus the GATE input can be used
to synchronize the Counter. After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. OUT goes low N CLK pulses after the initial count is
written. This allows the Counter to be synchronized by software also. Writing a new count
while counting does not affect the current counting sequence. If a trigger is received after
writing a new count but before the end of the current period, the Counter will be loaded with
the new count on the next CLK pulse and counting will continue from the end of the current
counting cycle.

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FIG 6. MODE 2

Mode 3: Square Wave Mode

Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the
duty cycle of OUT. OUT will initially be high. When half the initial count has expired,
OUTgoes low for the remainder of the count. Mode 3 is periodic; the sequence above is
repeated indefinitely. An initial count of N results in a square wave with a period of N CLK
cycles.GATE =1 enables counting; GATE =0 disables counting. If GATE goes low while

OUT is low, OUT is set high immediately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to
synchronize the Counter.

After writing a Control Word and initial count, the Counter will be loaded on the next CLK
pulse. This allows the Counter to be synchronized by software also.

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FIG 7. MODE 3

Writing a new count while counting does not affect the current counting sequence. If a
trigger is received after writing a new count but before the end of the current half-cycle of the
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square wave, the Counter will be loaded with the new count on the next CLK pulse and
counting will continue from the new count. Otherwise, the new count will be loaded at the
end of the current half-cycle.

Mode 3 is implemented as Follows:

EVEN COUNTS: OUT is initially high. The initial count is loaded on one CLK pulse and
then is decremented by two on succeeding CLK pulses. When the count expires,
OUTchanges value and the Counter is reloaded with the initial count. The above process is
repeated indefinitely.

ODD COUNTS: OUT is initially high. The initial count is loaded on one CLK pulse,
decremented by one on the next CLK pulse, and then decremented by two on succeeding
CLK pulses. When the count expires, OUT goes low and the Counter is reloaded with the
initial count. The count is decremented by three on the next CLK pulse, and then by two on
succeeding CLK pulses. When the count expires, OUT goes high again and the Counter is
reloaded with the initial count. The above process is repeated indefinitely. So for odd counts,
OUT will be high for (N +1)/2 counts and low for (N - 1)/2 counts.

Mode 4: Software Triggered Mode

OUT will be initially high. When the initial count expires, OUT will go low for one CLK
pulse then go high again. The counting sequence is Triggered by writing the initial count.
GATE =1 enables counting; GATE =0 disables counting. GATE has no effect on OUT.
After writing a Control Word and initial count, the Counter will be loaded on the next CLK
pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does
not strobe low until N +1 CLK pulses after the initial count is written. If a new count is
written during counting, it will be loaded on the next CLK pulse and counting will continue
from the new count. If a two-byte count is written, the following happens:

(1)Writing the first byte has no effect on counting.

(2)Writing the second byte allows the new count to be loaded on the next CLK pulse.

This allows the sequence to be retriggered by software. OUT strobes low N +1 CLK
pulses after the new count of N is written.

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Mode 5: Hardware Triggered Strobe (Retrigger able)

OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial
count has expired, OUT will go low for one CLK pulse and then go high again. After writing
the Control Word and initial count, the counter will not be loaded until the CLK pulse after a
trigger. This CLK pulse does not decrement the count, so for an initial count of N, OUT does
not strobe low until N +1 CLK pulses after trigger. A trigger results in the counter being
loaded with the initial count on the next CLK pulse. The counting sequence is trigger able.
OUT will not strobe low for N +1 CLK pulses after any trigger GATE has no effect on
OUT. If a new count is written during counting, the current counting sequence will not be
affected. If a trigger occurs after the new count is written but before the current count
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expires, the Counter will be loaded with new count on the next CLK pulse and counting will
continue from there.

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FIG 8. MODE 5

FIG 9. GATE PIN OPERATION SUMMARY

READ/WRITE PROCEDURES:

WRITE OPERATIONS:
The programming procedure for the 82C54 is very flexible. Only two conventions need to be
remembered:
1. For Each Counter, the Control Word must be written before the initial count is written.
2. The initial count must follow the count format specified in the Control Word (least
significant byte only, most significant byte only, or least significant byte and then most
significant byte). Since the Control Word Register and the three Counters have separate
addresses (selected by the A1, A0 inputs), and each Control Word specifies the Counter it
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applies to (SC0, SC1 bits), no special instruction sequence is required. Any programming
sequence that follows the conventions above is acceptable.

Possible Programming Sequence:

Possible Programming Sequence:

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A new initial count may be written to a Counter at any time without affecting the Counters
programmed Mode in any way. Counting will be affected as described in the Mode
definitions. The new count must follow the programmed count format. If a Counter is
programmed to read/write two-byte counts, the following precaution applies. A program
must not transfer control between writing the first and second byte to another routine which
also writes into that same Counter. Otherwise, the Counter will be loaded with an incorrect
count. Counter in any way. If a Counter is latched and then, some time later, latched again
before the count is read, the second Counter Latch Command is ignored. The count read will
be the count at the time the first Counter Latch Command was issued. With either method,

the count must be read according to the programmed format; specifically, if the Counter is
programmed

Read Operations

It is often desirable to read the value of a Counter without disturbing the count in progress.
This is easily done in the 8253.
There are three possible methods for reading the Counters. The first is through the Read-
Back command, which is explained later. The second is a simple read operation of the
Counter, which is selected with the A1, A0 inputs? The only Requirement is that the CLK
input of the selected Counter Must be inhibited by using either the GATE input or external
Logic. Otherwise, the count may be in process of changing when it is read, giving an
undefined result.

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Counter Latch Command

The other method for reading the Counters involves a special software command called the
Counter Latch Command. Like a Control Word, this command is written to the Control
Word Register, which is selected when A1, A0 =11. Also, like a Control Word, the SC0,
SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this
command from a Control Word.

The selected Counters output latch (OL) latches the count when the Counter Latch
Command is received. This count is held in the latch until it is read by the CPU (or until the
Counter is reprogrammed). The count is then unlatched automatically and the OL returns to
following the counting element (CE). This allows reading the contents of the Counters on
the fly without affecting counting in progress. Multiple Counter Latch Commands may be
used to latch more than one Counter. Each latched Counters OL holds its count until read.
Counter Latch Commands do not affect the programmed Mode of the Counter in any way.
If a Counter is latched and then, some time later, latched again before the count is read, the
second Counter Latch Command is ignored. The count read will be the count at the time the
first Counter Latch Command was issued.

With either method, the count must be read according to the programmed format;
specifically, if the Counter is programmed for two byte counts, two bytes must be read. The
two bytes do not have to be read one right after the other; read or write or programming
operations of other Counters may be inserted between them. Another feature of the 82C54 is
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that reads and writes of the same Counter may be interleaved; for example, if the Counter is
programmed for two byte counts, the following sequence is valid.

1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.

If a counter is programmed to read or write two-byte counts, the following precaution
applies: A program MUST NOT transfer control between reading the first and second byte to
another routine which also reads from that same Counter. Otherwise, an incorrect count will
be read.

Reading while counting:

The order for the programmer to read the contents of any counter with out effecting or
disturbing the counting operation of the 8253 has special internal logic that can be accessed
using simple WR commands to the MODE register. Basically, in the programmer wishes to
read the contents of the selected counter on the fly the loads the MODE register with a
special code which latches the present count value into a storage register so that its contents
contain an accurate, stable quantity. The programmer then issues a normal read command to
the selected counter and the contents of the latched register is available.

MODE Register for Latching Count:

A0, A1=11
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 0 0 0 X X X

SC1, SC0 .. Specify counter to be latched.

D5, D4 .Do designates counter latching operation.

X . Dont Care

The same limitation applies to this mode of reading the counter as the previous method. That
is, it is mandatory to complete the entire read operation as programmed. This command has
no effect on the counters mode.

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8251 & 8253 REGISTER ADDRESSES

The addresses for the 8253 registers on this card for use with HQ-86 Trainer are as follows:

Timer 0 - 0058H
Timer 1 -005AH
Timer 2 -005CH
Command Register -005EH

The addresses for the 8251 registers on this card for use with HQ-86 Trainer are as follows:

Command/Status Register 007AH
Data Register - 0078H

EXAMPLE PROGRAMS FOR 8086 :

8251 Program for 8086:

1. Program to display WELCOME TO HiQ 8251 STUDY CARD for 9600 baud
by initializing 8251.

=007A M51 EQU 007AH
=0078 V51 EQU 0078H
=005E M53 EQU 005EH

=0058 TM0 EQU 0058H

0000 CODE SEGMENT
ASSUME CS:CODE,DS:CODE,SS:CODE,ES:CODE

1000 ORG 1000H
1000 B0 36 MOV AL,36H ; Initialize Timer 0
1002 BA 005E MOV DX,M53 ; for Mode 3 operation
1005 EE OUT DX,AL
1006 BA 0058 MOV DX,TM0
1009 B0 0A MOV AL,0AH
100B EE OUT DX,AL ; Load Timer 0 Count
100C B0 00 MOV AL,00H ; for 9600 baud
100E EE OUT DX,AL
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100F BC 0540 MOV SP,0540H
1012 BA 007A MOV DX,M51
1015 EE OUT DX,AL ; Reset 8251
1016 EE OUT DX,AL
1017 EE OUT DX,AL
1018 EE OUT DX,AL

1019 E8 1049 R CALL DLY
101C B0 40 MOV AL,040H ; Initialize 8251 for
101E EE OUT DX,AL ; Asynchronous 16x baud
101F E8 1049 R CALL DLY ; 8 data bits,no
1022 B0 CE MOV AL,0CEH ; parity
1024 EE OUT DX,AL
1025 E8 1049 R CALL DLY
1028 B0 27 MOV AL,27H
102A EE OUT DX,AL
102B E8 1049 R CALL DLY
102E BE 2100 MOV SI,2100H
1031 BA 007A STS: MOV DX,M51
1034 EC IN AL,DX ; Get USART status for
1035 24 81 AND AL,81H ; Transmitter ready &
1037 3C 81 CMP AL,81H ; DSR active
1039 75 F6 J NE STS
103B 8A 04 MOV AL,[SI] ; If yes, transmit
103D 46 INC SI ; stored character
103E 3C 00 CMP AL,00H
1040 74 06 J E OVR
1042 BA 0078 MOV DX,V51
1045 EE OUT DX,AL
1046 EB E9 J MP STS
1048 CC OVR: INT 3
1049 B9 0010 DLY: MOV CX,0010H
104C E2 FE XX: LOOP XX
104E C3 RET

2100 ORG 2100H ; Display message
2100 0D 0A DB 0DH,0AH

2102 57 45 4C 43 4F 4D DB 'WELCOME TO HiQ ELECTRONICS 8251/53
STUDY CARD'
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45 20 54 4F 20 48
69 51 20 45 4C 45
43 54 52 4F 4E 49
43 53 20 38 32 35
31 2F 35 33 20 53
54 55 44 59 20 43
41 52 44
212F 0D 00 DB 0DH,00H

2131 CODE ENDS
END

8253 Program For 8086 :

2. Program to run Timer 1 in Mode 3 .

0000 CODE SEGMENT
ASSUME
CS:CODE,DS:CODE,ES:CODE,SS:CODE

1000 ORG 1000H

1000 B0 76 MOV AL,76H ; Initialize Timer1
1002 BA 005E MOV DX,005EH ; for Mode 3 operation
1005 EE OUT DX,AL
1006 B0 FF MOV AL,0FFH
1008 BA 005A ODT: MOV DX,005AH ; Load Timer 1 data
100B EE OUT DX,AL ; LSB first
100C B0 02 MOV AL,02H ; Load MSB
100E EE OUT DX,AL
100F B0 96 MOV AL,96H ; Initialize Timer 2
1011 BA 005E MOV DX,005EH
1014 EE OUT DX,AL
1015 B0 FF MOV AL,0FFH ; Load Timer 2 data
1017 BA 005C MOV DX,005CH
101A EE OUT DX,AL
101B EE OUT DX,AL
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101C B0 86 BACK: MOV AL,86H
101E BA 005E MOV DX,005EH
1021 EE OUT DX,AL
1022 BA 005C MOV DX,005CH
1025 EC IN AL,DX
1026 3C 00 CMP AL,00H
1028 74 DE J E ODT
102A B4 00 MOV AH,00H
102C B9 0400 MOV CX,0400H
102F E2 FE ZZ: LOOP ZZ
1031 EB E9 J MP BACK ; Repeat Continuously

1033 CODE ENDS
END
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8251 Program for 8051 kit:

2. Program to display WELCOME TO HiQ 8251 STUDY CARD for 9600 baud
by initializing 8251.

Control Register = A003
Data Port = C01E
Command Port = C01F

ORG 0000H
J MP START
ORG 2000H

2000 START:
2000 7436 MOV A,#36H
2002 90A003 MOV DPTR,#0A003H ; Timer 0 for 9600 baud
2005 F0 MOVX @DPTR,A ; in mode 3
2006 90A000 MOV DPTR,#0A000H
2009 740A MOV A,#0AH
200B F0 MOVX @DPTR,A
200C 7400 MOV A,#00H
200E F0 MOVX @DPTR,A
200F 90C01F MOV DPTR,#0C01FH ; USART
2012 F0 MOVX @DPTR,A
2016 122059 CALL DELAY
2019 7440 MOV A,#40H ; Reset 8251
201C 122059 CALL DELAY
201F 74CE MOV A,#0CEH
2025 7427 MOV A,#27H
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202B 902500 MOV DPTR,#2500H
202E 7900 MOV R1,#00H
2030 STATUS:
2030 C082 PUSH DPL ; Get USART status
2032 C083 PUSH DPH
2034 90C01F MOV DPTR,#0C01FH
2037 E0 MOVX A,@DPTR
2038 5401 ANL A,#01H
203A D083 POP DPH
203C D082 POP DPL
203E B401EF CJ NE A,#01H,STATUS
2041 7400 MOV A,#00H
2043 93 MOVC A,@A+DPTR
2044 B40003 CJ NE A,#00H,CONT
2047 022047 XX: LJ MP XX
204A C082 CONT: PUSH DPL
204C C083 PUSH DPH
204E 90C01E MOV DPTR,#0C01EH
2052 D083 POP DPH
2054 D082 POP DPL
2056 A3 INC DPTR
2057 80D7 SJ MP STATUS

2059 DELAY:
2059 7802 MOV R0,#02H
205B 790A ZZ: MOV R1,#0AH
205D D9FE LOOP: DJ NZ R1,LOOP
205F D8FA DJ NZ R0,ZZ
2061 22 RET

ORG 2500H
2500 TABLE:
2500 0D0A DB 0DH,0AH
2502 57454C43 DB 'WELCOME TO HiQ 8251/8253 STUDY CARD'
2506 4F4D4520
250A 544F2048
250E 69512038
2512 3235312F
2516 38323533
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251A 20535455
251E 44592043
2522 415244
2525 0D00 DB 0DH,00H
END

8253 Program for 8051 Kit:

2. Program to run Timer 1 in Mode 3 .

Timer 0 - A000
Timer 1 - A001
Timer 2 - A002
Control Register - A003

ORG 0000H
0000 022000 J MP START
ORG 2000H

2000 START:
2000 7476 MOV A,#76H
2002 90A003 MOV DPTR,#A003H ; Timer 1 in mode 3
2006 74FF MOV A,#0FFH
2008 90A001 MOV DPTR,#A001H ; Timer 1 Data
200C F0 MOVX @DPTR,A
200D 7496 MOV A,#96H ; Load mode word
200F 90A003 MOV DPTR,#A003H
2013 74FF MOV A,#0FFH ; Data to Counter 2
2015 90A002 ODT:MOV DPTR,#A002H
2019 7486 BACK: MOV A,#86H
201B 90A003 MOV DPTR,#A003H
201E F0 MOVX @DPTR,A
201F 90A002 MOV DPTR,#A002H
2022 E0 MOVX A,@DPTR
2023 B40002 CJ NE A,#00H,NEXT
2026 80ED SJ MP ODT
2028 F571 NEXT: MOV 71H,A
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202A 75F000 MOV 0F0H,#00H
202D 79FF MOV R1,#0FFH
202F 7AFF X2: MOV R2,#0FFH
2031 DAFE X1: DJ NZ R2,X1
2033 D9FA DJ NZ R1,X2
2035 80E2 SJ MP BACK
END

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8251 & 8253 Programmable Communication Interface &programmable Interval Timer

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