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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009

A Comparator With Reduced Delay Time in 65-nm

CMOS for Supply Voltages Down to 0.65 V
Bernhard Goll, Member, IEEE, and Horst Zimmermann, Senior Member, IEEE

AbstractA comparator in a low-power 65-nm complementary

metaloxidesemiconductor process (only standard transistors
with threshold voltage Vt 0.4 V were used) is presented, where
the circuit of a conventional latch-type comparator consisting of
two cross-coupled inverters is modified for fast operation, even
with 0.6 GHz at a low supply voltage of 0.65 V. The advantages
of a high-impedance input, rail-to-rail output swing, robustness
against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of 109 at 1.2-V supply,
an amplitude at the input of 16.5 mV at 4 GHz has to be applied.
If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is
necessary. The power consumption of the comparator is 2.88 mW
at 5 GHz (1.2 V) and 128 W at 0.6 GHz (0.65 V). Simulations
show an offset standard deviation of about 6.1 mV at 0.65-V
supply. With an on-chip measurement circuit, the delay time of
the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V
supply, is obtained.
Index TermsComparator, complementary metaloxide
semiconductor (CMOS) analog circuits, low supply voltage,
modified latch, ultradeep submicrometer (UDSM) CMOS.

I. I NTRODUCTION

NALOG circuit design in ultradeep submicrometer

(UDSM) CMOS technologies suffers from low supply
voltages, thus having a small voltage headroom left, which
commonly decreases the dc performance at a given power
consumption [1]. In contrast to this, the ac performance tends
to become better in UDSM CMOS technologies due to lower
parasitic capacitances. Another problem is the increasing gate
tunnel current when the gate area is increased (supposing
optimal gm /ID ratio) to, e.g., reduce the input-referred offset.
Lowering the influence of mismatch by increasing the gate area
is limited by the gateleakage mismatch. It is now a challenge
to develop new circuit structures that either avoid a stack
of too many transistors between the supply rails, so that the
technology-given better ac performance does not degrade, or
keep the advantages of standard circuits, e.g., robustness against
the influence of noise and mismatch, or lower power consumption. An important circuit that is used for the transition from
the analog to the digital domain is the comparator. Commonly,
Manuscript received March 11, 2009; revised June 20, 2009 and August 7,
2009. First published October 9, 2009; current version published November 18,
2009. This work was supported in part by Infineon Technologies Austria AG
and in part by the Austrian BMVIT under Project Soft-RoC in FIT-IT via FFG.
This work was recommended by Associate Editor H.-S. Chen.
The authors are with the Institute of Electrodynamics, Microwave and Circuit
Engineering, Vienna University of Technology, 1040 Vienna, Austria (e-mail:
bernhard.goll@tuwien.ac.at; horst.zimmermann@ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2009.2030357

Fig. 1.

Widely used conventional latch-type comparator.

a comparator compares two analog input voltages and delivers

a logical value at the output, which indicates the polarity of
the input-voltage difference. Especially clocked regenerative
comparators are fundamental circuit blocks, which are mostly
based on cross-coupled inverters (latch) to force a fast decision
due to positive feedback [2]. This type of comparator is typically used in Flash analog-digital converters (ADCs) because
of their high decision speed. In ADCs, additional circuitry is
added to the comparator, e.g., a preamplifier for enhancing
the resolution [3][5] or an offset compensation block [6].
The applications of comparators are not only restricted to
Flash ADCs. A comparator based on a current-mode latch was
implemented in a 40-GBit/s demultiplexer in 1.2-V/0.11-m
CMOS technology. There, a 10-GHz clocked three-stage comparator with a bandwidth modulation technique was used to
extract every fourth bit of a 40-GBit/s data stream [7]. In [8],
a comparator was designed for an analog rank-order extractor,
and in [9], a latch-type voltage sense amplifier for a static
random-access memory is described.
A standard comparator circuit, which is widely used in circuit
design, with high-impedance input, rail-to-rail output swing,
and no static power consumption is shown in Fig. 1 [6], [9],
[10]. Before the comparison, the comparator is reset in the reset
phase (CLK = VSS , and N6 is off), where transistors P2 and P3
pull both output nodes OUT and OUT to VCo to define a start
condition and to have a valid logical level during reset. The
input voltages to be compared are applied to nodes CINP and
CINN. In the comparison phase (CLK = VCo , transistors P2
and P3 are off, and N6 is on), for the case where CINP > CINN,
the whole latch [cross-coupled inverters (N0, P0) and (N1, P1)]
will initiate regeneration when OUT has been discharged to
VCo Vtp by N3 before OUT (discharged by N2) reaches this
voltage level and P0 has turned on before P1. At this point
of time, OUT OUT is the amplified input voltage difference

1549-7747/$26.00 2009 IEEE

GOLL AND ZIMMERMANN: COMPARATOR IN 65-nm CMOS FOR SUPPLY VOLTAGES DOWN TO 0.65 V

CINP-CINN, which is initially applied to the latch for regeneration [6]. OUT is pulled to VCo , and OUT is pulled to VSS . In the
other case where CINP < CINN, the circuit works vice versa:
P1 is turned on before P0, and the latch pulls OUT to VSS and
OUT to VCo . In principle, this circuit has the advantage of good
robustness against noise and mismatch, because, among other
reasons, it can also be designed with large input transistors N2
and N3, e.g., to minimize the offset, where the larger parasitic
capacitances at their drains do not directly affect the switching
speed, which primarily depends on the load capacitances at
output nodes OUT and OUT. For example, when the latch
regenerates OUT toward VCo , then transistor N0 is turned off,
and node OUT is cut off from the parasitic capacitance at
the drain of N2. Thus, the effective load capacitance of the
latch is reduced in comparison to that of N2 and N3 directly
connected to the output nodes. Another reason for the lower
input-referred offset is the amplification of CINP-CINN for
the initial voltage difference, which causes the latch to switch
higher than in other structures (e.g., in [14]), where the input
transistors and the latch are parallel (additional parallel load
at the output nodes). Disadvantageous is the fact that, due to
the many stacked transistors, a sufficient high supply voltage is
needed for a proper delay time [11]. This may cause problems
in low-voltage UDSM CMOS, where even a stand-alone latch
(e.g., used in [11]), with its two cross-coupled inverters, suffers
from higher delay time if the supply voltage is reduced or a
low-power process with higher transistor threshold voltages is
used. For example, in Fig. 1, after the reset phase, the initial
condition of the comparison phase is OUT = OUT = VCo .
Thus, at the beginning of the decision, only transistors N0
and N1 of the latch contribute somewhat to positive feedback
until the voltage level of one output node has dropped enough
to turn on transistor P0 or P1 to start complete regeneration.
At a low supply voltage, this voltage drop only contributes a
small gatesource voltage for transistors N0 and N1, where the
gatesource voltage of P0 and P1 is also small; thus, the delay
time of the latch becomes large due to lower transconductances.
This brief describes a proposed comparator design, where the
latch of the conventional circuit in Fig. 1 has been replaced
by a new latch for low-supply-voltage operation, where the
advantages of a high-impedance input, a rail-to-rail output
swing, no static power consumption, and the indirect influence
of the parasitic capacitances of the input transistors (larger gate
area for lower offset) to the output nodes and, therefore, to the
switching speed have been kept. Furthermore, a structure with
parallel-connected input transistors as in [14] is avoided to get
a higher amplification of CINP-CINN for the initial voltage
difference, which causes the latch to flip with a lower inputreferred offset.
II. C IRCUIT D ESCRIPTION
The circuit of the proposed comparator is shown in Fig. 2. In
contrast to the conventional latch used in Fig. 1, where only N0
and N1 are initially on, the latch of the proposed comparator
is expanded into two paths between the supply rails (transistors
N0, N1, P0, P1, P4, and P5), so that, at the beginning of the
comparison phase, where both output nodes have the initial

811

Fig. 2. Proposed comparator with a modified latch.

Fig. 3. Transient simulations of the proposed comparator with an input

voltage difference of (gray case) 10 mV and (black case) 100 mV.

condition OUT = OUT = VCo (initially, internal nodes FB =

FB = VSS ), transistors N0 and N1 are turned on. However,
transistors P0 and P1 are also turned on and build, with input
transistors N2 and N3, an amplifier with a distinct working
point, which, in contrast to that in Fig. 1, contributes enough
gatesource voltage to transistors N0 and N1 at lower supply
voltages. Complete positive feedback of the latch starts when
one output node is discharged enough to turn on P4 or P5.
Regeneration is done with N0, N1, P0, and P1, where P4 and P5
help with additional amplification. To get a rail-to-rail output
swing and no static power consumption of the comparator,
one of the initial load transistors P0 or P1 is switched off,
when, during regeneration, FB or FB, respectively, is charged
to VCo . The other advantages of a high-impedance input and no
direct influence of parasitic capacitances of N2 and N3 to the
output nodes are kept. The corresponding transient simulations
of Fig. 2 can be seen in Fig. 3. A clock period is divided into two
phases: The reset phase (CLK = VSS ) is used to establish the
initial condition OUT = OUT = VCo for the following comparison phase. (CLK = VCo , VCo is the positive supply voltage
of the comparator.) During reset, transistor N6 is switched off,
and transistors P2, P3, N4, and N5 are on. Consequently, the

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009

Fig. 4. Comparison of the decision time (50% clock edge to 50% of the final
output voltage difference OUT OUT = VCo ) of the conventional comparator with the proposed comparator, depending on the supply voltage VCo .
Fig. 5.

output nodes OUT and OUT are pulled toward VCo by P2

and P3, which causes transistors P4 and P5 to be switched
off. N4 and N5 pull both nodes FB and FB to VSS . Hence,
transistors P0 and P1 are turned on and help in pulling OUT
and OUT to the final voltage level VCo . Comparison of the
voltage at input CINP with the voltage at CINN is started when
CLK switches to voltage level VCo (comparison phase). Hence,
transistor N6 is turned on, and P2, P3, N4, and N5 are switched
off. At the very beginning, transistors P4 and P5 are switched
off, and transistors P0 and P1 work in the linear region and
build the load for an amplifier with N2 and N3. Transistors
N0 and N1 are initially on. (The comparison phase starts with
OUT = OUT = VCo and FB = FB = VSS .) If, for the input
voltage, CINP > CINN is assumed, transistor N3 pulls the
voltage level at node OUT down faster than N2 does at node
OUT. Hence, transistor P4 begins to conduct. In this initial time
period, a small amount of positive feedback is also contributed
by transistors N0 and N1. When P4 begins to conduct, node
FB is charged toward VCo (N4 and N5 are off), and complete
positive feedback is started. Transistor P1 is turned off, and P0
keeps conducting, because node OUT is pulled to VCo . Thus, P5
remains off, and FB remains near VSS . (Sufficient input voltage
difference CINP-CINN is assumed.) Finally, N1, P4, and P0 are
switched on, and N0, P1, and P5 are turned off. Thus, OUT is
at voltage level VCo , OUT is at VSS , and no static current can
flow after the decision. In the other case where CINP > CINN,
OUT is pulled to VSS , and OUT is pulled to VCo , respectively.
A comparison of the decision times at different supply voltages of the proposed comparator in Fig. 2 with those of the
conventional comparator in Fig. 1 is shown in Fig. 4. Each comparator was designed in a similar way, so that the decision time
(50% clock edge to 50% of the final output voltage difference
OUT OUT = VCo ) is equal for VCo = 1.2 V with the same
transistors N0, N1, N2, N3, and N6. For example, at a supply
voltage of VCo = 0.6 V, the proposed comparator needs only
650 ps, instead of 2.95 ns, of the conventional comparator and
is therefore capable of low-voltage operation. For test purposes,
a test chip with the proposed comparator in 65-nm low-power
CMOS technology with a nominal supply voltage of VDD =
1.2 V was designed, whose block diagram is shown in Fig. 5.
The dashed rectangle marks an area that is separately supplied
with a voltage VCo to be able to investigate the behavior of

Block diagram of the test chip with the comparator.

Fig. 6. Detailed block diagram of on-chip delay-time measurement implementation, which consists of the transfer stage at node OUT and the appropriate
output driver with low-pass filters (R0 , C0 ) and (R1 , C1 ).

the comparator if VCo is lowered. The area outside is supplied

with nominal VDD = 1.2 V to always have the functionality
of the additional measurement circuitry for the characterization
of the implemented comparator. With the help of the clock
driver, a noninverted digital clock CLK and the appropriate
inverted clock CLK are generated, where the logical voltage
levels are VSS and VCo . To generate a clock signal, a sine
wave in which the frequency is defined by the on-chip clock
frequency and the duty cycle (adjusted to 50%) is defined
by the dc bias voltage level is applied to pad CLKIN. The RC
low-pass filters (R2, C2) and (R3, C3) are added to measure the
mean voltage (duty cycle) of the internal clock lines CLK and
CLK at pads CLKAVP and CLKAVN, respectively. All highfrequency inputs CLKIN, CINP, and CINN are terminated with
on-chip 50- resistors. The transfer stage (see Figs. 5 and 6)
dynamically holds the decision of the comparator during its
reset phase at node SHB. In the case where CLK1 and CLK1
are also switched to transmission gates P7 and N8, respectively
(case DIG = 1.2 V), P7 and N8 are turned off when P6 and N7
are on, and vice versa during a clock cycle. Therefore, at outputs
COUT and COU T , a single decision of the comparator lasts for
a whole clock period, and the overall delay time between (CLK,
CLK) and (COUT, COU T ) is kept constant to simplify bit

GOLL AND ZIMMERMANN: COMPARATOR IN 65-nm CMOS FOR SUPPLY VOLTAGES DOWN TO 0.65 V

813

Fig. 8. Micrograph of the test chip with the comparator.

Fig. 7. Transient simulation to illustrate the measurement of the delay time

of the comparator (see also Fig. 6, case DIG = VSS , where P7 and N8 are
always turned on). An amplitude at the input CINP of 100 mV (black case)
causes a delay time td1 , and a smaller amplitude of 10 mV (gray case) causes a
larger delay time td2 . The delay time is then determined by measuring the mean
voltage of nodes DM0 and DM1 at D0AV and D1AV, respectively. VDM =
D0AV D1AV is proportional to td .

error rate (BER) measurements with a BER analyzer, because

the delay time of the comparator varies, depending on, e.g., the
amplitude or the common-mode voltage at the inputs. In the
transfer stage (see also Fig. 6), adapters for the conversion of
the logical voltage levels VSS and VCo to levels VSS and VDD
are added at the input. Such an adapter consists of a chain of two
inverters, where each inverter is separately supplied for stepwise increasing the supply voltage from VCo to VDD = 1.2 V.
Each output driver of Fig. 5 consists of a chain of inverters and
is able to drive off-chip 50- measurement equipment. RC lowpass filters (R0, C0) and (R1, C1) have been added at the output
driver for COU T , with which, in addition to the transfer stage,
the delay time td of the comparator at OUT can be measured
(see Fig. 6). Delay time measurements can be done in the case
where DIG = VSS when only transmission gate (P6, N7) holds
the decision of the comparator during reset and transmission
gate (P7, N8) is switched to be always turned on. The delay
time is defined here as the time duration, which begins at the
time point when the voltage level has reached 50% of VCo at
the rising edge of CLK and ends at the time point when OUT
has fallen to the switching threshold of the following inverter
( 50% of VCo ). The transient simulations for Fig. 6 to illustrate
delay-time measurements are shown in Fig. 7. For measuring
the delay time, a rectangular signal with a period of two times
the clock period, which is superimposed by a bias voltage for
offset compensation, is applied to CINP, as shown in Fig. 7.
CINN is biased with a reference voltage, e.g., an amplitude at
the input CINP of 100 mV (black case) causes a delay time
td1 , and a smaller amplitude of 10 mV (gray case) causes a
larger delay time td2 at OUT. Signal OUT is led to a chain of
inverters, which are able to drive the parasitic capacitances of

transmission gate (P6, N7). To compensate the additional delay

time, which is caused by the inverter chain, signal CLK and
CLK are each led via an equal inverter chain as well. Thus, the
time difference between turning on (P6, N7) by CLK1 and the
rising edge at node SHA is the delay time td of the comparator.
The reset time of the comparator is not considered due to the
fact that it is replaced by TCLK /2 because transmission gate
(P6, N7) holds the decision of the comparator at node SHB
during reset TCLK /2 long. Transistors P7 and N8 are always
on. Thus, the duty cycle at nodes DM0 and DM1 in the output
driver comprises information on the comparators delay time.
To obtain this delay time td , the mean voltages of DM0 and
DM1 are measured at D0AV and D1AV, and then, the following
is used:
td =

D0AV D1AV
VDM
TCLK =
TCLK .
VDD
VDD

(1)

A Monte Carlo simulation with 50 runs for the delay-time

measurement system consisting of the transfer stage and output
driver, as shown in Fig. 6, has been done, where, instead of the
output signal of the comparator, a signal with a known delay
time has been introduced to the transfer stage. As a result, an
offset error of 6 ps and a standard deviation of < 4 ps of
the simulated delay time measurement result were obtained.
It should be mentioned that the measurement technique is
independent of the duty cycle of the signal CLK.
An analytical calculation of the delay time of the comparator
itself can be done in a similar way as in [9]: The threshold
voltage of P4 (= P5), for the first part (discharging time of the
output nodes), and the additional contribution of the transconductances of (P4, P5) and the parasitic capacitances of the
internal nodes FB and FB to positive feedback, for the second
part (regeneration time of the latch), have to be considered.
III. M EASUREMENT R ESULTS
A chip with an area of 930 500 m2 was fabricated in
low-power 65-nm CMOS technology (see Fig. 8). Thereof
28.4 49.1 m2 is dedicated to the comparator.
The influence of noise to the decision of the comparator
and, thus, the sensitivity can be characterized with the help
of statistical measurements by measuring the BER with an
appropriate pattern generator and receiver. A reference voltage
(at CINN) and a pseudorandom bit sequence 231 1 (at CINP)
were applied, which was superimposed to a bias voltage of

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 11, NOVEMBER 2009

IV. C ONCLUSION

Fig. 9. BER measurements.

A comparator with a modified latch for low-supply-voltage

operation has been fabricated in low-power 65-nm CMOS
(threshold voltage 0.4 V) and characterized with the help of
an on-chip delay-time measurement circuit. Compared to [9],
[11][13], the proposed comparator has shown a good tradeoff
between sensitivity, offset, and speed, with the big advantage
of working even at a supply voltage of 0.65 V with a clock
rate of 0.6 GHz, power consumption of 128 W, sensitivity of
12.1 mV, and simulated = 6.1 mV of the offset. On the contrary, in [12], transistors with a threshold voltage of 0.29 V
were used, and the comparator worked with 0.6 GHz at
0.5-V supply voltage with 60.5-mV sensitivity and a simulated
standard deviation of the offset = 57 mV but 18-W power
consumption. Compared to [14], the offset = 22 mV is
reduced to 1.9 mV at 1.2 V. By placing the input transistors
below the modified latch, the delay time is shortened to 650 ps,
compared with 900 ps in [14] at 0.6-V supply.
ACKNOWLEDGMENT
The authors would like to thank Infineon, Villach, Austria,
especially Ch. Sandner, L. Drrer, and A. Bertl for initiating
this work.
R EFERENCES

Fig. 10. With the help of the on-chip measurement implementation, determined mean delay time of the comparator (with ten test chip samples measured,
7 ps).

CINN + offset to compensate the offset of the comparator. The

amplitude of a bit sequence is defined here, i.e., the bits switch,
at CINP +/ amplitude, around voltage level CINN + offset,
whereas, at CINN, the reference voltage is applied. The BER
measurement results of a typical test chip are shown in Fig. 9.
To achieve BER = 109 at 1.2-V supply, an amplitude of
7.8 mV at 3 GHz, 16.5 mV at 4 GHz, and 145 mV at 5 GHz
had to be applied. If VCo was lowered, 7 mV at 1 GHz/0.75 V,
6.9 mV at 0.5 GHz/0.65 V, and 12.1 mV at 0.6 GHz/0.65 V
were measured.
The determined mean delay time of the comparator (ten chip
samples), which was measured with the on-chip measurement
implementation previously described, is shown in Fig. 10. For
an amplitude of, e.g., 15 mV, at the input of the comparator, the
mean delay times ( 7 ps) were 93 ps at CINN = 0.65 V,
104 ps at CINN = 0.6 V, and 115 ps at CINN = 0.55 V at
VCo = 1.2 V.
The power consumption of the comparator was 2.88 mW at
5 GHz (1.2 V), 295 W at 1 GHz (0.75 V), and 128 W at
0.6 GHz (0.65 V). To investigate the influence of mismatch,
Monte Carlo simulations were done. For a run of 50 samples,
the standard deviations of the offset were simulated to be
1.9 mV at CINN = 0.6 V (VCo = 1.2 V), 4 mV at CINN =
0.55 V (VCo = 0.75 V), and 6.1 mV at CINN = 0.5 V (VCo =
0.65 V).

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