STi7105 PM

STi7105
Programming manual
Preliminary Data
soft modem support: MAFE or DAA

dual smartcard controllers and interfaces,
with clock generators to minimize external
circuitry, ISO7816 compliant
17 GPIO ports (3.3V tolerant)
PWM4 with programmable frequency range
1 kHz to 8 kHz
four SSCs for I2C/SPI master/slave
interfaces
four ASCs (UARTs)
Interrupt level controller
front panel key scanning support
This volume contains information to assist with

programming of the peripherals and interfaces.
This includes but is not restricted to the following
functional units:
dual USB 2.0 host controller/PHY interface
eSATA 1.0a with integrated PHY and SSC
support
gigabit ethernet controller (GMAC), with
GMII, RMII, MII, over-clocked MII (3x), and
RevMII support
infrared/UHF transmitter/receiver interface
DDR1
DDR2
SDRAM
JTAG
6-ch
S/PDIF
out
PCM out
2-ch Audio L/R
PCM in
out
Serial ATA
Line side
HDD, int/ext Dual
DAA
USB 2.0
Digital
hosts
video in
Audio
DACs
16/32
32 K I cache 32 K D cache
Audio decoder
players and
interfaces
CPU/FPU core
ST231
core
TMUs/INTC MMU
LMI
Serial
Peripheral I/O
and external interrupts FLASH
Key
Scan
ST40-300 core 400 MHz

UDI
Information classified Confidential - Do not copy (See last page for obligations)
Confidential
Introduction
USB
2.0
e-SATA
interface
USB
2.0
DVP
Comms
SPI
2x I/F
SmCard
System
side
DAA
GPIOs
4x
IR Tx/Rx MAFE
UHF Rx interface SSC/I2C
ILC
4x
UARTs
PWM
STBus
capture
Sec
NSK
Dual
PTI
PDES
3
SWTS
2
TSmerger/router
TS TS TS TS
IN0 IN1 IN2 I/O
August 2008
CP
DUAL
FDMA
Delta Mu
Advanced
Video decoder
ST231
Clock gen
and
system
services Ethernet,
Output
MAC
stage
Resets/ MII/RMII/GMII
clocks/
modes
Bdisp
blitter
Main/aux Display
compositor and
pass through
Main video DEI

display
Aux video
display
PCI EMI
EMPI
iDTV
version
TXT
DENC
6 DACs HDMI VTGs
Analog video
output
(HD/SD)
TMDS
DVO0 DVO1
Digital Digital
video
video
output 0 output 1
8137791 RevA
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
FLASH
NOR/NAND
SFLASH
1/454
www.st.com
Contents
STi7105
Contents
Confidential
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
Conventions used in this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
EMI operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
EMI address map and memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
EMI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
2.4.1
Bank programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2
Clock reconfiguration for synchronous interfaces . . . . . . . . . . . . . . . . . 14
Default/reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1
2.6
2.7
2/454
Default/reset configuration for MPX boot . . . . . . . . . . . . . . . . . . . . . . . . 16
Peripheral interface (with synchronous flash memory support) . . . . . . . . 16

2.6.1
Synchronous burst flash support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.3
Burst interrupt and burst reiteration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.4
Synchronous burst enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6.5
Support for lower clock rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.6
Initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.7
Use of flash memories in different banks with contiguous memory spaces

22
2.6.8
Chip select allocation/bank configuration . . . . . . . . . . . . . . . . . . . . . . . 23
2.6.9
Address bus extension to low order bits . . . . . . . . . . . . . . . . . . . . . . . . 23
PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.2
Master Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.7.3
Target Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.7.4
Host/Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.7.5
Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.7.6
Master functionality operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.7.7
Target functionality operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.7.8
Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.7.9
Device configuration specific operation . . . . . . . . . . . . . . . . . . . . . . . . . 31
8137791 RevA
STi7105
2.8
NAND flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.9
SPIBOOT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.9.1
DVB-CI /POD and ATAPI support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.9.2
HDD PIO mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.10
PC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11
EMI buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.12
MPX interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2
EMI subsystem register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3
EMI register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Confidential
3.3.1
3.4
EMI buffer register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EMI NAND flash support registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1
EMI NAND flash addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2
EMI NAND flash register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3
EMIBank register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2
PCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.3
PCI Host Function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4
PCI Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
USB 2.0 host (USBH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.1
6.2
Configuration register formats for peripherals . . . . . . . . . . . . . . . . . . . . 48
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2.1
STBus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2.3
System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
USB 2.0 host (USBH) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8137791 RevA
3/454
Contents
Contents
7.1
Base Addresses and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.2
AHB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.3
AHBPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Serial ATA (SATA) subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

8.1
Introduction to the SATA subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.2
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.3
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Confidential
8.4
8.5
8.6
8.3.1
PHY feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.3.2
SATA Controller feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.4.1
SATA host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.4.2
DMA data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.4.3
SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

8.5.1
Low power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.5.2
Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.5.3
Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Serial ATA (SATA) host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.1.1
9.2
Host overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

9.2.1
9.3
10
Internal communication paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Host functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

9.3.1
STBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
9.3.2
Transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.3.3
Link layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9.3.4
Physical layer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Serial ATA (SATA) DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

10.1
4/454
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SATA DMA transfer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

10.1.1
Multi-block transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.1.2
Auto-reloading of channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.1.3
Contiguous address between blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 139
8137791 RevA
STi7105
STi7105
Contents
10.2
10.1.4
Suspension of transfers between blocks . . . . . . . . . . . . . . . . . . . . . . . 140
10.1.5
Ending multi-block transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Programming a channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10.2.1
10.3
Disabling a channel prior to transfer completion . . . . . . . . . . . . . . . . . . 162

10.3.1
Abnormal transfer termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Serial ATA (SATA) host registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

11.1
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

11.1.1
Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.1.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
11.1.3
Confidential
11.2
11.3
12
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SATA host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

11.2.1
Shadow ATA/ATAPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
11.2.2
SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
11.2.3
SATA host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
AHB to STBus protocol converter registers . . . . . . . . . . . . . . . . . . . . . . 214
Ethernet subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

12.1
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
12.1.1
PHY connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
12.1.2
Interface support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Ethernet subsystem features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

12.2.1
12.3
12.4
System Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Ethernet I/O Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

12.3.1
MII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12.3.2
RMII (Reduced MII) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.3.3
RevMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
12.3.4
GMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Ethernet Subsystem Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

12.4.1
STBus bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.4.2
DMA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.4.3
MTL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.4.4
GMAC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.4.5
XMII block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8137791 RevA
5/454
11
Programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Contents
STi7105
12.6
Confidential
12.7
13
14
DMA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

12.5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
12.5.2
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.5.3
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
12.5.4
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
12.5.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.6.1
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.6.2
Receive descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.6.3
Transmit descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.6.4
Alternate (Enhanced) Descriptor Structure . . . . . . . . . . . . . . . . . . . . . 245
MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.7.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.7.2
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
12.7.3
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
12.7.4
RMII Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.7.5
MAC management counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.7.6
Power Management block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
12.7.7
Station Management Agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Ethernet registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

13.1
Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
13.2
GMAC control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
13.3
GMAC management counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
13.4
DMA control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Programmable I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

14.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
14.1.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
14.1.2
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
15
Programmable I/O port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
16
Synchronous serial controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6/454
16.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
16.2
Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
8137791 RevA
12.5
Contents
16.2.1
Pin connection and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
16.2.2
Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
16.2.3
Baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
16.2.4
Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
16.2.5
Receive data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
16.2.6
Antiglitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
16.2.7
Transmit and receive buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
16.2.8
Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
16.2.9
Enabling operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
16.2.10 Master/slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

16.2.11 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
16.2.12 Interrupt mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Confidential
16.3
IC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
16.3.1
IC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
16.3.2
Clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
16.3.3
START/STOP condition detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
16.3.4
Slave address comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
16.3.5
Clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
16.3.6
START/STOP condition generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
16.3.7
Acknowledge bit generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
16.3.8
Arbitration checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
17
Synchronous serial controller (SSC) registers . . . . . . . . . . . . . . . . . . 355
18
Asynchronous serial controller (ASC) . . . . . . . . . . . . . . . . . . . . . . . . 366

18.1
18.2
18.3
18.4
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
18.1.1
Resetting the FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
18.1.2
Transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

18.2.1
8-bit data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
18.2.2
9-bit data frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
18.3.1
Transmission with FIFOs enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
18.3.2
Double buffered transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
18.3.3
ASC_n_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
18.4.1
Hardware error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
8137791 RevA
7/454
STi7105
Contents
STi7105
Input buffering modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
18.4.3
Time out mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Baudrate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

18.5.1
18.6
Confidential
18.7
Baudrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

18.6.1
Using the ASC interrupts when FIFOs are disabled (double buffered
operation) 375
18.6.2
Using the ASC interrupts when FIFOs are enabled . . . . . . . . . . . . . . . 377
Smart card operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

18.7.1
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
18.7.2
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
18.7.3
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
18.7.4
Divergence from ISO smart card specification . . . . . . . . . . . . . . . . . . 380
19
Asynchronous serial controller (ASC) registers . . . . . . . . . . . . . . . . 381
20
PWM and counter module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

20.1
Programmable PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
20.2
Periodic interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
20.3
Capture and compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

20.3.1
Capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
20.3.2
Compare function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
21
PWM and counter module registers . . . . . . . . . . . . . . . . . . . . . . . . . . 395
22
Modem analog front end (MAFE) interfaces . . . . . . . . . . . . . . . . . . . . 402

22.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
22.2
Using the MAFE to connect to a modem . . . . . . . . . . . . . . . . . . . . . . . . 402
22.3
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
22.3.1
Data exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
22.3.2
Control/status exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
23
Modem analog front end (MAFE) interface registers . . . . . . . . . . . . . 404
24
Direct access arrangement (DAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
25
Integrated modem codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
8/454
8137791 RevA
18.5
18.4.2
STi7105
Remote controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

26.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
26.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
26.3
Confidential
27
28
29
26.2.1
RC transmit code processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
26.2.2
RC receive code processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
26.2.3
Noise suppression filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Start code detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

26.3.1
Generation of subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
26.3.2
Signalling rates and pulse duration specification for IrDA . . . . . . . . . . 415
26.3.3
Start code detection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Remote controller interface registers . . . . . . . . . . . . . . . . . . . . . . . . . 418

27.1
RC transmitter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
27.2
RC receiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
27.3
Noise suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
27.4
I/O control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
27.5
Reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
27.6
Receive status and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
27.7
IrDA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
27.8
SCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Key scanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

28.1
Debounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
28.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
28.3
Key scanner pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Key scanner registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
List of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
8137791 RevA
9/454
26
Contents
Preface
STi7105
Preface
Comments on this or other manuals in the STi7105 documentation suite should be made by
contacting your local sales office.
1.1
References
ST231 Core and Instruction set architecture manual
ST40 Core architecture manual

This manual describes the architecture and instruction set for the ST40 core.
STi7105 datasheet
Confidential
This document describes the pins, package, electrical characteristics and timing information
for the STi7105 device. It is intended for hardware engineers.
1.2
Conventions used in this guide

General notation
The notation in this document uses the following conventions:
sample code, keyboard input and file names
variables, code variables and code comments
screens, windows, dialog boxes and tool names
instructions
Hardware notation
The following conventions are used for hardware notation:
REGISTER NAMES and FIELD NAMES (NOT_SIGNALNAME for inverted signal).
PIN NAMES and SIGNAL NAMES.
The following abbreviations are used to represent register behavior:
10/454
W: write only,
R: read only,
RW: read/write,
Res: reserved,
R/LLU: read/linked list update.
8137791 RevA
This manual describes the architecture and instruction set for the ST231 cores.
STi7105
Preface
Software notation
Syntax definitions are presented in a modified Backus-Naur Form (BNF).
Terminal strings of the language, that is those not built up by rules of the language, are
printed in teletype font. For example, void.
Nonterminal strings of the language, that is those built up by rules of the language, are
printed in italic teletype font. For example, name.
If a nonterminal string of the language starts with a nonitalicized part, it is equivalent to

the same nonterminal string without that nonitalicized part. For example, vspacename.
Each phrase definition is built up using a double colon and an equals sign to separate
the two sides (::=).
Alternatives are separated by vertical bars (|).
Optional sequences are enclosed in square brackets ([ and ]).
Items which may be repeated appear in braces ({ and }).
Confidential
8137791 RevA
11/454
External memory interface (EMI)
STi7105

The EMI is a general purpose external memory interface that allows the system to support a
number of memory types, external process interfaces and devices. This includes glueless
support for up to five independent memories or devices.
2.1
Features
MPX mode support
16-bit or 8-bit interface for FLASH, Burst-FLASH and peripherals. 32-bit MPX target
and initiator port
NAND FLASH interface
Serial FLASH interface
PCI interface
support for up to five separately configurable external memory banks
EMI as either bus master or slave
retiming stage always enabled
five chip-selects (CSA, CSB, CSC, CSD, CDE)
port size (8 or 16 bits) for the boot defined by static mode pins sampled at the end of
the reset phase. Port size automatically set to 32 bits in case of boot from MPX.
no SDRAM support
address shifting in the padlogic present in previous products not supported
supports an HDD interface in PIO mode4 and a DVB-CI/POD interface via dedicated
signals.
The EMI memory map is divided into five regions (EMI banks). Address range 0x0000 0000
to 0x07FF FFFF.
Bank boundaries are programmable between 4 MBytes and 64 MBytes. On RESET, the
allocated memory space is divided into five regions of 16 MBytes each.
Each bank can only accommodate one type of device, but different device types can be
placed in different banks to provide glueless support for mixed memory systems.
The EMI is little endian. Bit positions are numbered left to right from the most significant to
the least significant. Thus in a 32-bit word, the leftmost bit, bit 31, is the most significant bit
and the rightmost bit, bit 0, is the least significant.
The external data bus can be configured to be 8 or 16 bits wide on a per-bank basis, and is
automatically 32-bits wide for a bank configured in MPX mode.
,
12/454
8137791 RevA
Confidential
The main features include:
STi7105
2.2
EMI operating modes
Peripheral/SRAM
Asynchronous NOR-FLASH (ST, AMD, Intel types)
Synchronous NOR-FLASH
NAND-FLASH (large and small page boot, flex and advanced flex modes)
Serial FLASH (ST and Atmel types)
DVB-CI
ATAPI-PIO
PCI (host or device; configured on boot)
Refer to the STi7105 datasheet Basic chip operating modes and multiplexing scenarios for
detailed information.
Confidential
2.3
EMI address map and memory space

The EMI is allocated a 128 Mbyte memory region mapped onto five user configurable
memory banks, plus a configuration space used to control the behavior of the EMI.
Following reset, the EMI is configured with 5 banks of 16 Mbytes.
The configuration address space is organized as shown in the EMI register summary.
Each EMI_BANKn (n = 0 to 4) contains a set of four 32-bit registers that are used to
configure each bank depending on the type of device that is connected.
The type and organization of each set of bank registers depends on the value in
DEVICETYPE (EMI_CFG_DATA0) which defines the type of memory or device attached to
that bank.
The EMI supports nonmultiplexed address and data bus.
Each memory type and the associated control registers are described later in this chapter.
Table 1.
Memory space
Address range
Size (bytes)
Function
Start
End
0x0000 0000
0x00FF FFFF
16 Mbytes
EMI Bank0(CS[0])
0x0100 0000
0x01FF FFFF
16 Mbytes
EMI Bank1(CS[1])
0x0200 0000
0x02FF FFFF
16 Mbytes
EMI Bank2(CS[2])
0x0300 0000
0x03FF FFFF
16 Mbytes
EMI Bank3(CS[3])
0x0400 0000
0x04FF FFFF
16 Mbytes
EMI Bank4(CS[4])
8137791 RevA
13/454
The EMI can support the following device types, each one associated to different pin
mappings:

Table 2.
STi7105
Configuration registers
Address range
Function
End
0xFE70 0000
0xFE70 07FF
EMI configuration
0xFE70 0800
0xFE70 0FFF
EMI buffer
0xFE70 1000
0xFE70 1FFF
Nand configuration
EMI operation
The EMI is a highly flexible memory device which is able to support a large range of memory
components gluelessly. It accepts memory operations from the system and, depending on
the address of the operation, either accesses its internal configuration space or one of the
possible five external memory banks.
Confidential
The position, size, clock frequency and memory type supported, is dependent on how the
associated control registers, EMI_BANKS[0:4], are programmed.
Following reset, all banks start with the same configuration which allows the system to boot
from a large range of nonvolatile memory devices.
As part of the boot process, the user should program the EMI configuration registers to
match the memory supported in that system, defining the memory size, the location in the
address and the device type connected.
2.4.1
Bank programming
Refer to Section 2.6.8: Chip select allocation/bank configuration on page 23 for full bank
programming details.
2.4.2
Clock reconfiguration for synchronous interfaces

Following reset, the clocks for synchronous interfaces are disabled. This is due to the default
reset assuming a memory which may be accessed asynchronously.
To access the synchronous memory, the user sets up the configuration state associated with
that bank. The user then programs the required clock ratio in the register
EMI_FLASH_CLK_SEL associated with that memory type.
The external clocks and associated clock dividers are then enabled by a write of 1 to register
EMI_MPX_CLK_SEL or EMI_FLASH_CLK_SEL, depending upon the device connected on
the board. Once enabled, any attempt to reprogram the clock ratios may have undefined
effects.
2.5
Default/reset configuration
Following reset, a default configuration setting is loaded into all five banks. This allows the
EMI to access data from a slow ROM or FLASH memory. The default settings are detailed in
Table 3.
14/454
8137791 RevA
2.4
Start
STi7105

Default configuration for asynchronous boot
Parameter
Default value
DATADRIVEDELAY
10 phases
BUSRELEASETIME
4 cycles
CSACTIVE
Active during read only
OEACTIVE
BEACTIVE
Inactive
PORTSIZE
Value of the signal EMI_PRTSZ_INIT
DEVICETYPE
Peripheral
ACCESSTIMEREAD
(18 + 2 = 20 cycles)
CSE1TIMEREAD
0 phases
CSE2TIMEREAD
0 phases
OEE1TIMEREAD
0 phases
OEE2TIMEREAD
0 phases
LATCHPOINT
End of access cycle
WAITPOLARITY
Active high
CYCLEnotPHASE
Phase
BE1TIMEREAD
3 phases
BE2TIMEREAD
3 phases
The remaining configuration parameters are not relevant for an asynchronous boot; that is
the aim of the default configuration.
Figure 1.
Default asynchronous configuration
EMIADDR
NOTEMICS
NOTEMIOE
4 cycles
EMIDATA
(read)
10 phases
EMIDATA
(write)
Read data
latch point
8137791 RevA
15/454
Confidential
Table 3.
2.5.1
STi7105
Default/reset configuration for MPX boot

The default configuration is loaded into all six banks on reset.
2.6
Default configuration for MPX boot
Parameter
Default value
BUSRELEASETIME
3 cycles
DEVICETYPE
MPX
WAITSTATESREAD
3 cycles
WAITSTATESWRITE
3 cycles
WAITSTATESFRAME
1 cycle
EXTENDEDMPX
0 (Hitachi compatible transfer size set)
WAITPOLARITY
0 (Active high)
STROBESONFALLING
0 (strobes changing on rising edge)
MPXCLOCKRATIO
00 (full clock speed)
Peripheral interface (with synchronous flash memory

support)
A generic peripheral (for example SRAM, EPROM, SFlash) access is provided which is
suitable for direct interfacing to a wide variety of SRAM, ROM, flash, SFlash and other
peripheral devices.
Note:
Refer to Section 2.6.8 on page 23 for specific STi7105 settings.

Figure 2 shows a generic access cycle and the allowable values for each timing field.
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8137791 RevA
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Table 4.
STi7105

Figure 2.
Generic access cycle

ACCESSCYCLETIME
EMIADDR
CSE1 time
CSE2 time
NOTEMICS
OEE2Time
OEE1 time
NOTEMIOE
Constant high for reads
BE E2 time
Data drive delay

EMIDATA
(write)
BUSRELEASETIME
EMIDATA
(read)
Read data
latch point
Constant high for reads
EMIRDNOTWR
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Write
Table 5.
Strobe timing parameters for peripheral
Name
Programmable value
ACCESSTIME
2 cycles + 0 to125 cycles
BUSRELEASETIME
0 to15 cycles
DATADRIVEDELAY
0 to 31 phases after start of access cycle
CSE1TIME
Falling edge of CS. 0 to15 phases or cycles after start of access cycle
CSE2TIME
Rising edge of CS. 0 to15 phases or cycles before end of access cycle
OEE1TIME
Falling edge of OE. 0 to15 phases or cycles after start of access cycle
OEE2TIME
Rising edge of OE. 0 to15 phases or cycles before end of access cycle.
BEE1TIME
Falling edge of BE. 0 to15 phases or cycles after start of access cycle
BEE2TIME
Rising edge of BE. 0 to15 phases or cycles before end of access cycle
LATCHPOINT
0: End of access cycle.

1 to 16: 1 to 16 cycles before end of access cycle.
Separate configuration parameters are available for reads and writes. In addition, each
strobe can be configured to be active on read, writes, neither or both.
Table 6.
Active code settings
CS/OE/BE active code
Strobe activity
00
Inactive
01
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BEE1 time
NOTEMIBE

Table 6.
2.6.1
STi7105
Active code settings (continued)
CS/OE/BE active code
Strobe activity
10
Active during write only
11
Active during read and write
Synchronous burst flash support
The EMI supports the following memory devices:
AMD AM29BL162C,
ST M58LW064A/B,
Intel 28F800F3/ 28F160F3,
and any new part in these families with identical access protocol.
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Table 7 provides a brief description and comparison of EMI-supported flash memories.

Note:
Not all memory features are supported. Non-supported features are highlighted.
The EMI implements a superset of operational modes so that it is compatible with most of
the main functions listed for the three flash families. The following sections contain a brief
description of the EMI flash interface functionality.
Table 7.
ST/AMD/Intel flash features comparison

AM29BL162C
STM58LW064A/B
Intel
28F800F3/28F160F3
16 Mbits
64 Mbits
8/16 Mbits
Max
operating
frequency
40 MHz
60 MHz
60 MHz
Data bus
16 bits fixed
16/32 bits
16 bits fixed
Main
operations
Async single access

write
Sync burst read
Async single access
read
Size
(1)
Burst size
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32 word partially
supported by EMI:
burst is interrupted
Async single access write

Sync burst read
Async single access read
Async page read
Not supported by EMI
1-2-4-8 words(2) or
continuous.
Set by burst configuration
register. Continuous is not
supported by EMI
8137791 RevA
Async single access write

Sync burst read
Async single access read
Async page read
Sync single access read
4 to 8 words or continuous
Set by read configuration
register
Continuous is not
supported by EMI
Burst mode flash accesses consist of multiple read accesses which must be made in a
sequential order. The EMI maps system memory operations onto one or more burst flash
accesses depending on the burst size configuration, operation size and the starting address
of the memory access.
STi7105

ST/AMD/Intel flash features comparison (continued)
AM29BL162C
STM58LW064A/B
Intel
28F800F3/28F160F3
Burst style(3)
Linear burst -32 words
Sequential burst
Interleaved burst (Not
supported)
Linear burst
Intel burst (Not supported)
X-latency(4)
70-90-120 ns
7-8-9-10-12(5) cycles
2-3-4-5-6 cycles
1 cycle
1-2 cycles
1 cycle
Y-latency
(6)
Yes via burst address

Burst suspend/
advance
(7)
resume
(NOTEMIBAA) input
Yes via burst address advance

No automatic advance
(NOTEMIBAA) input
Ready/busy
pin(8)
Yes (RD/BY)
Yes (RD/BY)
No
Ready for
burst(9)
No
Yes (R)
Yes (W)
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1. The flash operating frequency, clock divide ratios and system frequency should be consistent with the
maximum operating frequency.
2. A burst length of eight words is not available in the x 32 data bus configuration.
3. Modulo burst is equivalent to linear burst and sequential burst. Interleaved burst is equivalent to Intel burst.
On AMD the burst is enabled by four async write operations. On ST and Intel the burst is enabled
synchronously via the burst configuration register.
4. X latency is the time elapsed from the beginning of the accesses (address put on the bus) to the first valid
data that is output during a burst. For ST, it is the time elapsed from the sample valid of starting address to
the data being output from memory for Intel and AMD.
5. 10 to 12 only for F = 50 MHz.
6. Y-latency is the time elapsed from the current valid data that is output to the next data valid in output during
a burst.
7. In AMD and ST devices, BAA (or B) can be tied active. This means that the address advance during a
burst is noninterruptable (Intel likewise). EMI assumes these pins are tied active and does not generate a
BAA signal.
8. When the pin is low, the device is busy with a program/erase operation. When high, the device is ready for
any read, write operation.
9. These signals are used to introduce wait states. For example, in the continuous burst mode the memory
may incur an output delay when the starting address is not aligned to a four word boundary. In this case a
wait is asserted to cope with the delay.
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Table 7.
2.6.2
STi7105
Operating modes
Note:
asynchronous single read
synchronous burst mode (default four words length: configurable to 1, 2, 4 and 8 words)
using a specific lower frequency clock selected using register EMI_FLASH_CLK_SEL.
Continuous burst is not supported by the EMI.
32-word burst size is partially supported by the EMI; the burst is interrupted when the
required data has been read.
Asynchronous page mode read is not supported by the EMI.
Interleaved burst mode is not supported by the EMI due to the implementation of multiple
reads only using synchronous burst mode (feature provided by all three families of flash
chips adopted).
The EMI supports an asynchronous single write.
The asynchronous single read/write uses the same protocol as that of the normal peripheral
interface.
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Figure 3 shows a typical burst access with burst length of four words.
Figure 3.
Synchronous burst mode flash read (burst length = 4)
EMIFLASHCLK
EMIADDR
NOTEMILBA
ACCESSTIMEREAD
DATAHOLDDELAY
NOTEMICS
NOTEMIOE
NOTEMIBAA
EMIDATA
D+1 D+2 D+3
The ACCESSTIMEREAD parameter is used to specify the time taken by the device to
process the burst request. The rate at which subsequent accesses can be made is then
specified by the DATAHOLDDELAY parameter, e1 and e2 delays can also be specified.
2.6.3
Burst interrupt and burst reiteration

The EMI interrupts the burst after the required amount of data has been read, thus making
the chip select of the burst device inactive. This operation is allowed by all three families of
flash devices (burst read interrupt for an ST device, standby for Intel, terminate current burst
read for AMD). Due to this operation, the flash device puts its outputs in tri-state. If a new
burst operation is then required, a new chip select and load burst address is provided
(NOTEMILBA) to the memory chip.
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Two different programmable read modes are supported:
STi7105

If the flash interface is configured to a burst sequence of n bytes, and a burst read request of
m bytes is presented to the EMI on the STBus interface, there are three possible outcomes.
1.
n=m
The EMI performs one burst access during which it gets the exact number of words as
requested (see example A on Figure 4 with n = m = 8). Depending on the starting address,
there is possibly a wrap that is automatically completed by the flash device. The wrap occurs
when the starting address is not aligned on an n-byte word boundary.
Figure 4.
Burst on a flash with a single access

0 1 2 3 4 5 6 7
Single burst
Start address = 0x0000B
Wrap to read last two bytes is automatically done by flash device
0 1 2 3 4 5 6 7
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B)
First burst
Start address = 0x0010B
2.
n>m
If the starting address is aligned on an m-byte word boundary, the EMI gets m bytes from a
single burst sequence as explained in the previous paragraph. Then the transfer on flash is
interrupted making the chip select inactive. This terminates the burst transfer and puts the
memory device in standby mode, waiting for a new request and starting address for a new
burst.
If the starting address is not aligned on an m-byte word boundary, a first burst on the flash
executes until the m-byte word boundary is crossed. The burst on the flash is interrupted
and there follows another burst with a starting address that wraps to an m-byte boundary
(directly given by STBus interface) to read the remaining data. After all the required bytes
have been read, the burst access on flash can be interrupted.
3.
n<m
The EMI needs to perform more burst accesses until it gets the required m words.
If the starting address is aligned on an n-byte word boundary, there are a series of flash
burst accesses until the exact number of bytes is met.
If the starting address is not aligned on an n-byte word boundary, there is a first access on
flash to read data until the n-byte word boundary is met. This access is then interrupted and
new series of accesses are started on a new address provided by STBus (that eventually
wraps at the m-bytes boundary). This is repeated until the exact number of bytes is reached.
This happens in the middle of the last flash burst that is interrupted in the usual manner.
2.6.4
Synchronous burst enable

This operation is controlled by software and must only be performed when all other
configuration registers in the EMI have been programmed.
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n = m = 8 words
A)
STi7105
Table 7 shows that for ST and Intel devices to operate in synchronous burst mode, the
configuration parameters must be set in a special configuration register inside the memory
device. The configuration software routine starts two asynchronous write operations for
each bank of burst memory, where address and data, respect precise configuration rules.
However, for AMD the burst enable is performed by a sequence of four normal
asynchronous writes.
Support for lower clock rates

Many SFlash devices operate in the 30 to 50 MHz clock range (Table 7) whereas the EMI
operates up to a clock frequency of 100 MHz. To deal with this difference, the EMI can run in
a lower speed mode. The hardware in the EMI needed for this mode forces accesses to
always start on the rising edge of the slower clock. It is up to the user to configure the other
EMI timings, to setup and latch, on the appropriate edge of this slower clock.
Figure 5.
Half speed EMI SFlash clock
CLK_EMI
EMIFLASHCLK
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EMIADDR
NOTEMILBA
NOTEMICS
ACCESSTIMEREAD
DATAHOLDDELAY
NOTEMIOE
NOTEMIBAA
EMIDATA
2.6.6
D+1
D+2
D+3
Initialization sequence
Peripheral interfaces are used immediately after reset to boot the device. Therefore, the
default state must be correct for either synchronous or normal ROM. An SFlash device can
be interfaced to normal ROM strobes with the addition of only the address valid signal and
the clock. When the CPU has run the initial bootstrap, it can configure both the SFlash
device and the EMI to make use of the burst features.
Note:
The flash devices are in asynchronous read mode after reset.
Caution:
The process of changing from default configuration to synchronous mode is not interruptible.
Therefore the CPU must not be reading from the device at the same time as changing the
configuration as there is a small window where the EMI configuration is inconsistent with the
memory device configuration.
2.6.7
Use of flash memories in different banks with contiguous memory

spaces
As shown in Table 7 on page 18, the maximum size of memory chip for SFlash is 64 Mbits.
This may not be enough for some of the variants that use the EMI.
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2.6.5
STi7105

It is however possible to place two flash devices in different banks and have their memory
space located contiguously in the overall address space. With this arrangement, the two
flash devices are seen the same way as a single, larger memory device from the software
point of view.
This is done through the use of the bank reconfiguration capability, controlled through the
EMI Buffer Registers.
2.6.8
Chip select allocation/bank configuration
2.6.9
Address bus extension to low order bits
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The STi7105 EMI is able to use either 8- or 16-bit wide memory devices. Selection is done
through field PORTSIZE of register EMI_CFG_DATA0. The width of the boot bank is
selected in hardware by the logic level to which mode pins MODE[8] are tied.
When using a 16-bit device, the low order address bit is on pin EMIADDR[1]. Pins
NOTEMIBE[1:0] are byte selectors: bit [0] enables the low order byte and bit [1] enables the
high order byte.
When using an 8-bit device, the low order address bit is on pin NOTEMIBE[1] (that is,
NOTEMIBE[1] is a virtual EMIADDR[0]). Pins NOTEMIBE[0] acts as byte enable.
2.7
PCI interface
The STBus-PCI bridge enables the EMI to support a PCI interface.
2.7.1
Overview
The STBus-PCI bridge can be configured to be Host or Multi-Function Device by register
access and supports both the Master and Target functionalities.
The PCI clock direction is controllable through register access.
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Each of the five EMI banks can be configured separately to support different types of
devices. There are restrictions on certain banks. The STi7105 provides five chip selects at
its outputs, one per bank (NOTEMICSA, NOTEMICSB, NOTEMICSC, NOTEMICSD,
NOTEMICSE).
STi7105
Host configuration
A PCI system with the STi7105 configured as a Host has the following connections:
Figure 6.
Example of PCI system with STi7105 as a Host

PCI bus
STi7105
Host
Device
PCI
bridge
Up to 4 lines,
1 per Device
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STbus
Note:
When the STBus-PCI bridge is operating as a Host, four PCI interrupts are available for
external PCI agents.
Device configuration
A PCI system with the STi7105 configured as a Device has the following connections:
Figure 7.
Example of PCI system with STi7105 as a Device

PCI bus
STi7105
Device
Host
PCI
Note:
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PCI
bridge
reset
req
gnt
int
When the STBus-PCI bridge is operating as a Device, it can generate one interrupt to the
Host.
8137791 RevA
PCI
req
gnt
int
STi7105
2.7.2
Master Functionality
In the Master functionality, a part of the STBus address space is mapped on to the PCI
memory space.
The STBus-PCI bridge generates the PCI frames on the PCI bus. When it is configured as
Device, the req/gnt protocol is used to get access to the PCI bus from the external Host.
Only memory frames can be generated by accessing to this address range. A specific
mechanism handles IO and Configuration frames.
Figure 8. shows the STBus address window mapped onto the PCI memory address and
onto the configuration registers housed inside the STBus-PCI bridge.
Figure 8.
Master Functionality: STBus address window on PCI memory space

STBus Address, 4GB
PCI Address, 4GB
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base address:
EMISS_PCI_BRIDGE_REG
STBus-PCI config,
base address:
PCI_MASTER
Min 1KByte,
Max 1GByte
STBus Address window on PCI

mapped on STBus Window size
and Base address
SW configurable
The PCI Master functionality has the following limitations:
2.7.3
All the configuration and IO accesses are of one data cycle.
Fast back-to-back frames on PCI are not supported.
Target Functionality
The PCI Target functionality is implemented as a multi-function device. It supports up to
8 functions, each function having its own configuration space.
The base addresses are defined in each configuration spaces to support a memory block,
an I/O and a dual address cycle access so that the PCI interface can respond to 24 PCI
addresses (3 addresses per function).
Each PCI Target memory function occupy up to 256 MB of PCI memory map whose base
address are defined by the Host, as shown in the Figure 9.:
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The base address with which the PCI frames are generated is software configurable. The
window size of the STBus address that is exposed onto the PCI address domain is also
software configurable. A minimum of 1KBytes and a maximum of 1 GByte of contiguous
memory space can be mapped on to the PCI address.
Target Functionality: PCI address window on STBus memory space

PCI Address, 4GB
(Memory or IO space)
System Memory
Space, 4GB
PCI Address window on System

Memory configured by the
depth of the buffer
up to 256 MB
mapped to
each function
SW configurable
8 functions max
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A PCI frame access for any of the Target functions accesses a buffer defined within the
STi7105 memory space. The association of the buffer with the target function is software
configurable. The process of accessing the destination buffers is called buffer function in
this document. A maximum of 8 buffer functions can be supported by the STBus-PCI bridge.
Each buffer can be configured as a circular buffer and associated to an interrupt generated
when the buffer limit is reached.
The PCI Target function has following limitations.
Any of given buffer functions can be associated with either memory or IO, not both.
The PCI slave interface supports 8 functions, each function has one memory, one IO
and one dual address cycle addresses. This makes total of 24 functions in the PCI
target.
In the case of read function, the read latencies have to be met.
2.7.4
Host/Device configuration
The STi7105 is set by default to the Host configuration. The Device configuration can be
selected by setting EMISS_CONFIG.PCI_HOST_NOT_DEVICE to 0.
2.7.5
Boot Configuration
At power on reset, the STBus-PCI bridge is held at reset. The software is expected to
program the boot configuration memory which defines the configuration space of the PCI
interface. The sequence for boot configuration memory initialization is as follows:
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the boot configuration memory pointer is reset to zero by writing 0x00 into the register
PCI_BOOTCFG_ADD.
Then data is written into the register PCI_BOOTCFG_DATA.
the boot configuration memory pointer is incremented after each write access. This
facilitates updating the next location in the boot configuration memory without updating
the pointer.
8137791 RevA
Figure 9.
STi7105
STi7105

After updating the boot configuration memory, the reset is de-asserted by setting
PCI_BRIDGE_CONFIG.PCI_RESET to 1.
2.7.6
Master functionality operation

Address space
Memory accesses
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The base address on the PCI memory map for which memory read or write frames have to
be generated, has to be written into the register PCI_FRAME_ADD. The unmasking bits
have to be set appropriately by writing the appropriate value into the register
PCI_FRAME_ADD_MASK.
The address of the generated PCI frame can be calculated by the following equation:
pci_address = [STBus_address & PCI_FRAME_ADD_MASK] | [PCI_FRAME_ADD &
~(PCI_FRAME_ADD_MASK)]
where:
the lowest 10 bits are inferred from the STBus address bits,
the bits 31 and 30 are inferred from the PCI_FRAME_ADD bits,
the other bits depend on the PCI_FRAME_ADD_MASK bit value: if the bit
PCI_FRAME_ADD_MASK.MASK_DISABLE[m] is set to 1, the bit [m] is inferred
from the STBus address bit [m] else if the bit
PCI_FRAME_ADD_MASK.MASK_DISABLE[m] is set to 0, the bit [m] is inferred
from the PCI_FRAME_ADD bit [m]
as detailed in Figure 10.:
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On reset a default 1KB of STBus address range, whose base address is defined as
PCI_MASTER_base_address, is mapped on to the PCI address space. This can be
increased to a maximum of 1 GB through the register PCI_FRAME_ADD_MASK. The
following rule must be ensured by software: If a bit m is set to 1, all the least significant bits
till m have to be set to 1. Not following this rule would result in the generation of PCI
frames at the wrong addresses.
STi7105
Figure 10. Master Functionality: address translation

31
PCI_FRAME_ADDRESS
30 29
10 9
STBus address
10 9
30 29
31
reserved
PCI_FRAME_ADD_MASK
30 29
31
reserved
10 9
select
30 29
10 9
PCI address
Confidential
If all PCI_FRAME_ADD_MASK.MASK_DISABLE bits are set to 1, then 1GB of the system

space are mapped to the PCI space. It is the responsibility of the software to program these
bits depending on the system configuration.
IO and Configuration accesses

The PCI IO and config frames generated by the STBus-PCI bridge are of one data beat. To
generate the IO or config frames, the address of the PCI IO or config frames has to be
written into the register PCI_CSR_ADDRESS. The byte enables and command for the
frame generated have to be written into the register PCI_CSR_BE_CMD. A read frame is
generated by reading the register PCI_CSR_RD_DATA and a write frame generated by
writing into the register PCI_CSR_WR_DATA.
2.7.7
Target functionality operation

Memory and IO accesses
Each received IO or memory frames on the PCI interface generate transactions on the
STBus and are managed through a maximum of 8 buffers. Each of the supported buffers
can be uniquely associated to an IO or memory access on the PCI function space and has
one physical buffer on which storing or reading operations can wrap.
The buffer-function association is done by the sw during the configuration phase. There is
no hw mechanism for managing any address range conflict functions.
The wrapping mode uses the buffer in a circular way. When the address exceeds the depth
of the programmed buffer, it is re-initialized with the start address. Circular buffers are
envisaged in scenarios where the read throughput on the PCI target interface has to be met.
Buffer Initialization
The procedure for association of the buffer to the target function is described as follows:
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Each of the buffer function has on physical buffers (usually defined in the external
memory) on which storing or reading operations can wrap. The address of these
8137791 RevA
31
0
reserved
STi7105
All the write frames received are posted, that is TRDY is asserted when the data is
received by the PCI interface.
For the read frames TRDY is asserted when the data is read from the physical buffer.
The buffer wrapping for the function n is enabled by setting

PCI_BRIDGE_CONFIG.WRAP_ENABLE[n] = 1.
The depth of the buffer (both the buffers have same depth) is written into the register
PCI_FUNCn_BUFF_DEPTH. The buffer depth has to be 2k, that is, if a bit in the buffer
depth is set to 1, all the LSB bits would be 0.
The PCI frame type associated to the buffer is defined in the register
PCI_FUNCn_BUFF_CONFIG.BAR_HIT field.
The function-buffer association is defined in the register

PCI_FUNCn_BUFF_CONFIG.FUNC_ID field and the activation of the association in
PCI_FUNCn_BUFF_CONFIG.FUNC_ENABLE bit.
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Processing frames
If correctly initialized, the reception of the first PCI frame is using the buffer 0 information to
transfer the content on the STBus: the address is translated using the content of the
PCI_BUFFADD0_FUNC0. If there is no function-buffer association, a frame reception
doesnt generate any STBus transaction but an interrupt, if the interrupt is enabled.
The address of the generated STBus frame depends on the bit field, as shown in Figure 11.,
the upper bits are inferred from the upper PCI_BUFFADD0_FUNCn register bits,
the lower bits are inferred from the lower PCI address bits,
the boundary between lower and upper bits being defined by the position of the unique 1
allowed in the PCI_FUNCn_BUFF_DEPTH register bits.
The bottom bits of the STbus address can also vary as they are auto-incremented based on
the length of the burst generated by the PCI access.
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buffers is written into the register PCI_BUFFADD0_FUNCn (m is the buffer number

and n is function number).
STi7105
Figure 11. Target Functionality: address translation
PCI address
PCI_BUFFADD0_FUNCn
31
k+1 k
31
k+1 k
31
0
k+1 k k-1
0 1 0
0
0
31
k+1 k
STBus address
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auto-increment
depending on
PCI burst length
The current buffers address pointer for the buffer function n is available for read access in
PCI_CURRADDPTR_FUNCn.CURR_ADDRESS field.
Interrupts
The interrupts are handled by 3 registers:
PCI_BRIDGE_INT_DMA_ENABLE for settings,
PCI_BRIDGE_INT_DMA_STATUS for status read operations,
PCI_BRIDGE_INT_DMA_CLEAR for de-assertion.
The standard interrupt corresponding to the function n is enabled when the corresponding
bit PCI_BRIDGE_INT_DMA_ENABLE.INT_FUNC_ENAB[n] is set to 1. Reading
PCI_BRIDGE_INT_DMA_STATUS.INT_FUNC_STS[n] accesses to the interrupt flag and
setting PCI_BRIDGE_INT_DMA_CLEAR.INT_FUNC_CLR[n] to 1 clears the
corresponding interrupts.
Two specific error cases are covered by dedicated interrupt enables:
If the bit PCI_BRIDGE_INT_DMA_ENABLE.INT_BRIDGE_UNDEF_FUNC_ENB is set to
1, an interrupt is asserted if a PCI frame is received attached to a function for which there is
no associated buffer. The corresponding status bit is located in
PCI_BRIDGE_INT_DMA_STATUS.INT_BRIDGE_UNDEF_FUNC_STS and the clear bit in
PCI_BRIDGE_INT_DMA_CLEAR.INT_BRIDGE_UNDEF_FUNC_CLR.
All interrupts can be disabled by the
PCI_BRIDGE_INT_DMA_ENABLE.INTERRUPT_ENABLE bit.
Received frame information

The register PCI_TARGID_BARHIT contains the target function ID (function space
addressed by the PCI frame) and the information if the PCI frame received was IO, memory
or dual address cycle.When an interrupt is asserted due to un-associated function, reading
this register helps in inferring the addressed function space and the type of the received PCI
frame .
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PCI_FUNC0_BUFF_DEPTH
STi7105
2.7.8
Configuration registers
The standard Configuration registers are listed in Table 18.: PCI Configuration registers
summary
In Host mode, they are defined during the Boot Configuration phase (refer to Section 2.7.5:
Boot Configuration). They can be accessed anytime by:
writing the register address in PCI_CRP_ADD register,
in case of write access, writing the register value in PCI_CRP_WR_DATA register or,
in case of read access, reading the register value in PCI_CRP_RD_DATA register.
2.7.9
Device configuration specific operation

Reset
Set in Device configuration, the STBus-PCI bridge can be reset by the Host through the
PCI_NOTRESET_FROM_HOST pin.
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Interrupts
Set in Device configuration, the STBus-PCI bridge may assert an interrupt to the Host on
the interrupt PCI_INT_TO_HOST line.
The interrupt for a function n is asserted by setting the PCI_INTERRUPT_OUT.PCI_INTn
to 1 if the PCI Interrupt Disable (Command register bit 10) bit is reset.The PCI Interrupt
Status (Status register bit 3) is set accordingly.
The STBus-PCI bridge can be programmed to assert an internal interrupt when the status of
the PCI Interrupt Disable (Command register bit 10) bit changes. This interrupt is
handled by 3 registers:
PCI_DEVICEMASK_INT_ENABLE for settings,
PCI_DEVICEMASK_INT_STATUS for status read operations,
PCI_DEVICEMASK_INT_CLEAR for de-assertion.
The interrupt corresponding to the function n is enabled when the corresponding bit
PCI_DEVICEMASK_INT_ENABLE.INT_ENABLEn is set to 1. The edge used to assert the
interrupt is programmable between rising, falling and both-edges options using the
PCI_DEVICEMASK_INT_ENABLE.EDGE_ENABLEn field.
Reading PCI_DEVICEMASK_INT_STATUS.INT_STATUSn bit accesses to the interrupt flag
and PCI_DEVICEMASK_INT_STATUS.EDGE_STATUSn field to the last flagged transition.
Reading PCI_DEVICEMASK_INT_STATUS.INTERRUPT_DISABLEn bit accesses the
status of the PCI Interrupt Disable for the corresponding function.
Setting PCI_DEVICEMASK_INT_CLEAR.INT_CLEARn to 1 clears the corresponding
interrupt.
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In Device mode, the Configuration registers are only accessible via the PCI interface.
2.8
STi7105
NAND flash interface

The features that are supported by the NAND controller are:
Note:
Boot capability from
large (2048 bytes) and small page (512 bytes) devices
8-bit as well as 16-bit devices
Devices with 3 - 5 address cycles
software programmable flex mode for all the NAND flash modes
ECC support in flex mode for read/write
FDMA/host managed, Advance flex mode, for bulk data movement
ECC support in Advance flex mode. Provision for writing the ECC data into the spare
location of the memory.
Error detection capability in advance flex mode. Error correction is the responsibility of
the software.
The EMI module of the STi7105 does not support Multi Level Cell (MLC) NAND devices
The Nand flash support has three modes of operation.
Confidential
NAND flash support on boot bank.

In this mode it is possible to boot the chip from the external NAND flash. This requires the
issue of a reset command which is followed by a read command (depending on the default
settings) and then reading the contents of external NAND flash. It is always possible (even
after the boot) to read the data from the external NAND flash by directly reading the boot
bank. The NAND flash on boot bank can be read at any time, even after reset, by executing
reads to the boot bank. Other functions such as erase, program etc. are supported only
through flex mode.
NAND flash support - Flex mode

In this mode it is possible to extend the NAND flash support to other banks and provide
features such as block erase, page program, read status, read ID etc. These functions are
not supported in the boot mode.
Using the flex mode operation, a sequence of reads and writes can be created, which can
achieve any functionality on the external Nand flash. The creation of a sequence is entirely
the responsibility of the software, and hardware offers no protection for a wrong sequence.
The flex mode also supports ECC on read/write. The ECC bits can be read out from the
configuration registers.
NAND flash support - Advance flex mode

This mode supports all the flash operations supported by flex mode, as well as providing a
capability for interacting with efficient FDMA data transfers for improving the bus utilization
time.
2.9
SPIBOOT Interface
This IP provides seamless interface to the serial flashes using the SPI protocol.
32/454
8137791 RevA
STi7105

Main features of the SPIBOOT are:
supports up to one external memory region (region0 only)
maximum size of serial flash supported is 16 Mbytes
boot frequency support of 30 MHz
The main function of the SPI is to take the normal STBus requests coming from EMI buffer
and convert them into Serial Access (SPI Protocol), to access serial flash devices that
support the SPI Interface.
The SPIBoot shares its pads with some of the bits of PIO2 and PIO6.
DVB-CI /POD and ATAPI support

Additional hardware logic is integrated around the EMI to enable a glueless POD interface
and low cost, low performance HDD support through an ATAPI interface in PIO mode.
EMI banks C and D support PC Card accesses and ATAPI PIO mode accesses when
enabled.
Confidential
DVB-CI/POD support
The signals required by the PC card interface (PCMCIA) (ANSI/SCTE-28/2001 Host/Pod
Interface Standard and PC Card 2.0 specification) are available directly from the EMI when
the EMI configuration bits EMI_GEN_CFG[4:3] are set. These signals are:
2.9.2
PCMCIA_OE# (active low)
PCMCIA_WE# (active low)
PCMCIA_IORD# (active low)
PCMCIA_IOWR# (active low)
HDD PIO mode support

The ATAPI interface in PIO mode also requires signals similar to the PCMCIA_IORD# and
PCMCIA_IOWR# signals. Therefore, implementing POD support also gives ATAPI-PIO
mode support in banks C or D.
The ATAPI PIO mode support is required for chip validation purpose (ability to have a simple
access to data or test streams from an HDD) because the STi7105 has a USB interface for
a high-performance HDD access.
PCMCIA signals generation

Using PCMCIA terminology, PCMCIA_OE (RESP. PCMCIA_WE) is asserted for common
(or attribute memory) read access (RESP. WRITE access).
PCMCIA_IORD (RESP. PCMCIA_IOWR) is asserted for IO read access (RESP. WRITE
access).
Distinction between memory accesses and I/O accesses to the PC Card is based on the
EMI address line A[15]: if 1 then the access will be a memory access, if 0 then the access
will be an I/O access.
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2.9.1

Table 8.
STi7105
PCMCIA signals
Read Operation
Write Operation
EMI Addr[15]
Memory
PCMCIA_OE
PCMCIA_WE
IO
PCMCIA_IOWR
PCMCIA_IORD
The PCMCIA_OE#, PCMCIA_WE#, PCMCIA_IORD#, PCMCIA_IOWR# boolean equations

are:
pcmcia_OE# = NOT(CS_x AND RdNotWr AND OE AND ADDR[15])
pcmcia_WE# = NOT(CS_x AND NOT(RdNotWr) AND OE AND ADDR[15])
pcmcia_IOWR# = NOT(CS_x AND NOT(RdNotWr) AND OE AND NOT(ADDR[15]))

Note:
OE is part of the equation both in Read and Writes, which means that the EMI4 will have to
be configured to do this (not classical case). This is required to control the timing of the
PCMCIA_WE# and PCMCIA_IOWR# signals (since RdNotWr cannot be restricted to be
active during just a part of the access).
Confidential
PCMCIA signals multiplexing and selection

The PCMCAI signals are multiplexed with regular EMI signals as follows :
EMI_nOE / PCMCIA_OE#
EMI_nLBA / PCMCIA_WE#
EMI_nBAA / PCMCIA_IORD#
EMI_nBE[0] / PCMCIA_IOWR#
The selection between the regular EMI signals and these alternate functions is based on
EMI General Configuration bits :
EMI_GEN_CFG[3]: enable_PCCard_bank_C
EMI_GEN_CFG[4]: enable_PCCard_bank_D
When these bits are set, the accesses to the banks C and D (as indicated by the state of
EMI_nCS[3] or EMI_nCS[4]) will use the PC Card specific signals instead of the regular EMI
signals.
NOTE: some additional logic is added to make sure that EMI_LBA_PHI1/2 and
EMI4_BAA_PHI1/2 are low (inactive) outside any burst Flash access. Burst Flash accesses
are characterized by the fact that EMI4_CURR_DEVTYPE[2:0]=1xx (100 actually) - for
any other type of access EMI4_CURR_DEVTYPE[2:0]=0xx. This precaution is taken
because the EMI controller does not guarantee the state of EMI_LBA_PHI1/2 (and
EMI_BAA_PHI1/2) outside Burst Flash access (it works because corresponding CS is not
asserted...) and this has caused issues on the EMISS DVBCI/ATAPI interface of the
STi5516/7.
NOTE: To avoid potential glitch problems, timings of the EMI for banks supporting PC Card
should be set such that the EMI_nOE low pulse is completely contained within the time slot
corresponding to the EMI_nCSx pulse, with a little margin.
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8137791 RevA
pcmcia_IORD# = NOT(CS_x AND RdNotWr AND OE AND NOT(ADDR[15]))
STi7105
2.10
PC card interface
The STi7105 offers a PC Card interface able to support PCMCIA and CableCARD modules
(to the ANSI/SCTE-28/2001 standard). This is done through the EMI interface pins, with
some of them modified as described in a later section.
The PC Card signals that are not available directly from the EMI, or anywhere else in the
STi7105 application, are:
PCCARD_OE#, PCCARD_WE#, PCCARD_IORD#, PCCARD_IOWR#
(asserted at logic low level).
Banks 3 and 4 support PC Card accesses.
For common (or attribute memory) read access, PCCARD_OE# gets asserted.
For I/O read access, PCCARD_IORD# gets asserted.
For common (or attribute memory) write access, PCCARD_WE# gets asserted.
For I/O write access, PCCARD_IOWR# gets asserted.
Confidential
Distinction between memory accesses and IO accesses to the PC Card are based on
subdecoding:
If EMI address line A[15] is 1 then it is a memory access
if 0 then it is an I/O access
Glue logic internal to the STi7105 generates the specific PC Card signals and multiplex
them with some regular EMI signals as follows:
NOTEMIOE = PCCARD_OE#
NOTEMILBA = PCCARD_WE#
NOTEMIBAA = PCCARD_IORD#
NOTEMIBE[0] = PCCARD_IOWR#
Enabling of banks 3 and 4 as PC Card banks is based on bits [3] and [4] of EMI General
Configuration bits EMI_GEN_CFG (refer to EMI configuration register list).
When these enables are set, during access to one of these banks (as indicated by the state
of EMI_nCS[3] or EMI_nCS[4]) the regular EMI signal is replaced by the PC Card specific
signals.
Note:
To avoid potential glitch problems, timings of the EMI when accessing a PC Card should be
set such that the NOTEMIOE low pulse is completely contained within the NOTEMICSx
pulse, with a little margin.
2.11
EMI buffer
The EMI buffer is split into six banks which define the EMI memory space. All banks are
contiguous and their size is defined by programming the base address of each bank, with
the base address of bank 0 fixed at 0x0000 0000. The address granularity is 4 Mbytes per
bank. The reset configuration is 16 Mbytes per bank with all five banks enabled.
8137791 RevA
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Using PCMCIA terminology:
STi7105
Figure 12. EMI buffer organization

Memory Map
0x0
EMI bank 0 base address

Bank 0
Bank select signal: NOTEMICSA
Bank 1
Bank select signal: NOTEMICSB
Bank 2
Bank select signal: NOTEMICSC
Bank 3
Bank select signal: NOTEMICSD
Bank 4
Bank select signal: NOTEMICSE

EMI
space
Confidential
64 Mbyte
Note:
There is a sixth virtual bank, bank 5, whose associated chip select is not brought out of the
chip, this bank is therefore not usable. However, knowledge of its existence helps program
the EMI buffer registers correctly. After booting, the EMI buffer can be reconfigured to
allocate bank 5, with a reduction in size for the other five banks.
2.12
MPX interface
MPX is an Hitachi proprietary standard that has been developed as an internal optimized
version of PCI standard. The MPX interface is mainly based on a multiplexed address/data
type protocol and enables easy connection with an external companion-chip. Generally, the
pin number of an interface with companion-chip affects system configuration cost. The MPX
bus can decrease the pin count maintaining the large bus bandwidth in burst data transfers.
MPX in general allows two companion-chips to exchange data in both directions: both sides
can initiate interactions (initiator), but only after it gains the bus mastership. The EMI
supports an initiator-only MPX interface with a fixed bus-width of 32 bits. Two cases are
possible:
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EMI is a bus master (statically set at power-on): in this case the EMI can access all the
six banks as a bus master. Eventually one or more of these banks can hold MPX target
devices. EMI will select the target MPX bank using the chip select signals, while the
other signals will be shared by all the MPX devices. EMI can release the bus on
demand. If some external master (MPX included) want to access a memory device, can
ask EMI to release (tri-state) its outputs on the bus signals and drive them to access
directly the memory. For EMI all the arbitration between external masters is completely
8137791 RevA
STi7105

transparent: what EMI will only deal with is the release of the bus when an external
request comes.
Note:
EMI is a bus slave (statically set at power-on): the bus master is external. In this case
EMI must require the bus before to access MPX or any memory devices.
In any case EMI cannot be accessed as a target by any external master (MPX included).
All signals on this interface are synchronous to the MPX clock, which can be set to full EMI
system clock OR 1/2 sys clock OR 1/3 sys clock. The set-up of the EMI.MPX_CLK_SEL will
properly set the MPX clock.
MPX pads connection
Confidential
EMI+Pads
MPX device
MPXCLOCK
CLK
NOT_CS
/CS
NOT_BS
/BS
NOT_FRAME
/FRAME
/WE
READNOTWRITE
MEM_WAIT
/RDY
MEM_ADDR/DATA<31:0>
I/O<31:0>
I/O<63:61>
MEM_DATA
<31:29>
DACK(n)
Where:
MPXCLOCK: output clock;
NOT_CS: chip select
NOT_BS: Bus Start: active at the beginning of the operation and used to latch the access
starting address
NOT_FRAME: when active (and no wait inserted) indicates a new data to be required. A
transfer of N words will require NOT_FRAME active at least for N cycles
MEM_WAIT (/RDY): during read/write operations when low data are valid/latched on next
cycle; otherwise a wait state is introduced
I/O: i/o bus where data and address are multiplexed.
MEM_DATA<31:29>: used as command bus to select the size of transfer access. The only
supported access sizes are 8-16-32 bits and 16 or 32 byte burst
The address is output to MEM_WRITEDATA[28:0] and the access size to
MEM_WRITEDATA[31:29] (on diagrams this bus for simplicity is referred as MEM_DATA)
8137791 RevA
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Figure 13. MPX initiator-only interface
STi7105
DACK(n): used to indicate that transfer is from DMA(n).

Note:
The command information is output on D63-D61 in the application processors MPX

interface. The MEM_DATA[31:29] of the EMI has to be connected with I/O<63:61> of an
MPX device. The meaning of these command bits is explained on Table 9.
D63
D62
D61
Transfer Size
8 bits
16 bits
32 bits
64 bits
16-byte Burst (1)
32-byte burst
1. This and next codings are a EMI dedicated super-set: actually for Hitachi the 1XX combinations all
correspond to 32byte burst: this super-set can be disabled by configuration
Note:
MPX burst cannot be interrupted: this means that, when the burst starts, the system MUST
ENSURE to deliver IN TIME to EMI all the data needed to keep the burst alive. The same
applies for SFLASH bursts.
MPX protocol has no byte enable signals. This means that, during a store 4-8-16-32 bytes,
even if some byte enables are disabled, EMI is forced to write anyway the bytes disabled
(Burst interruption is not possible). EMI will return an error opcode anyway to warn the
system that something wrong is happening.
External vs. internal wait states insertion

In the interface description, the signal /RDY has been introduced. This signal is usually used
by a slow MPX device to insert wait states on the other side. External wait has some delay.
It is difficult to provide correct ready value on time particularly in write operations.To deal
with variable response time of different implementation of external logic, programmability of
internal wait helps a lot. For this reason EMI MPX interface provide a configurable number of
internal wait for each bank of MPX.
MPX clock
The EMI padlogic provides clock to all MPX interface modules in all cases. So even when:
EMI releases the external bus to other masters (see Figure : MPX clock connection).
EMI is configured as a stable slave
other master must synchronize with the clock which EMI padlogic provides. At the 100 MHz
clock frequency, a companion chip has PLL inside the design to synchronize with EMI clock.
On the following pages there is a list of diagrams explaining the main transactions on MPX
interface.
The shortest READ transaction must last at least three clock cycles: the first to issue the
start of operations and latch the address, the second to avoid bus contention (address
comes from initiator while data from target), and the third to latch the data arriving from the
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8137791 RevA
Confidential
The signal DACK(n) is not generated within EMI but in an external wrapper (padlogic or
different block). It will be asserted continuously during the address phase and all the data
phases.
Table 9.
transfer size on MPX device
STi7105

target. Obviously this access time can be enlarged with external or internal (or both) wait
cycles.
The shortest WRITE transaction can last two cycles: the first to issue the start of operations
and latch the address, the second to effectively send the data to the target that will latch
them. No dummy cycle is needed between the start and completion of transaction because
both address and data come from the initiator and there is no bus contention hazard.
MPX clock connection
BUSREQ
MPX master
CLKIN
MPX slave
BUSACK
CLKIN
Confidential
MPX clock
EMI
HOST
MPX ADDRESS/DATA
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EMI registers
STi7105
EMI registers
Caution:
Register bits that are shown as reserved must not be modified by software as this will cause
unpredictable behavior.
3.1
Overview
EMI subsystem register addresses are provided as
where:
the EMISSConfigBaseAddress is: 0xFE40 0000
the arbiter offset is: 0x1000
Confidential
EMI Configuration register addresses are provided as

EMIConfigBaseAddress + offset
EMIBufferBaseAddress + offset, or
EMIBankBaseAddress + offset
The EMIConfigBaseAddress is: 0xFE70 0000
The EMIBankBaseAddress is: EMIConfigBaseAddress + EMIBank(n) (where n = 0 to 4)
The EMI subsystem registers are listed in Table 10.

Table 10.
EMI subsystem register summary
Address offset from
EMISSConfigBaseAddress +
arbiter offset
Register
Description
Page
0x00
EMISS_CONFIG
EMI subsystem configuration and

status
on page
42
The EMI configuration registers are listed in Table 11.

Table 11.
EMI configuration register summary
Address offset from
Register
Description
Page
0x010
EMI_STA_CFG
Status register (configuration flags

update)
on page
43
0x018
EMI_STA_LCK
Lock register (configuration flags lock)
on page
44
0x020
EMI_LCK
Lock register
on page
44
EMIConfigBaseAddress
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8137791 RevA
EMISSConfigBaseAddress + arbiter offset + offset
STi7105
EMI configuration register summary (continued)
Address offset from
Register
Description
0x028
EMI_GEN_CFG
General purpose configuration register on page

set
44
0x030 to 0x048
Reserved
0x050
EMI_FLASH_CLK_SEL
Select clock speed for flash devices
0x058
Reserved
0x0060
EMI_MPX_CLK_SEL
Select clock speed for MPX devices
0x0060
Reserved
0x070 to 0x0F8
Reserved
0x240 to 0xFFF8
Reserved
EMIBankBaseAddress + 0x00
EMI_MPX_CFG
MPX format
Reserved
Confidential
Page
on page
45
on page
46
on page
56
The configuration region of each bank is divided as shown in Table 12.

Table 12.
EMI_BANKn register organization
Address offset from

EMIBankBaseAddress
Register
Description
Page
0x00
EMI_CFG_DATA0
on page
48
0x08
EMI_CFG_DATA1
on page
49
0x10
EMI_CFG_DATA2
on page
49
0x18
EMI_CFG_DATA3
on page
50
0x200x38
RESERVED
The EMI buffer is characterized by seven internal registers:
five related to the accessible external memory banks (each composed of six bits)
one related to the virtual memory bank (composed of six bits)
one related to the value of the total number of banks registers enabled at the same time
(composed of three bits)
8137791 RevA
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Table 11.
EMI registers
EMI registers
Address offset from

0x100
0x140
0x180
0x1C0
0x200
0x240
Page
EMIB_BANK0_BASE_ADDR
External memory bank 0 address bits

[27:22]
on page
52

[27:22]
on page
53

[27:22]
on page
53

[27:22]
on page
53

[27:22]
on page
54
Virtual memory bank 5 address bits

[27:22]
on page
54
EMIB_BANK_EN
Total number of enabled banks
on page
55
EMI subsystem register descriptions

EMI subsystem configuration and status
9
PCI_HOST_NOT_DEVICE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
EMISSConfigBaseAddress + 0x1000 + 0x00
Type:
R/W
0
RESERVEDPCI_CLOCK_MASTER
EMISS_CONFIG
RESERVEDCLOCK_SELECT
3.2
Description
RESERVED
Confidential
0x280
Register
Reset:
Description:
For some bits reset state reflects the state on the static pins on reset. The value of the
static pin is expected to be updated into the register few clock edges after the reset
de-assertion.
[31:6] RESERVED
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8137791 RevA
EMI buffer register summary
BOOT_DEVICE[1:0]
Table 13.
STi7105
STi7105
EMI registers
[4:3] BOOT_DEVICE[1:0]:
The device on boot bank is identified by contents in these bits. They may be used for debug, to
cross check if the correct device is connected on boot bank.
00: NOR flash (EMI controller)NOR flash on boot bank (read only)
01: Nand flash (Nand controller)MPX
10: Serial flash (SPI controller)SPI
11: ReservedNAND
Reset: value sampled on MODE[17:16]
[2:1] RESERVEDCLOCK_SELECT:
These pins identify which clock is bristled on to the flash clock out pin of EMISS.
00: Flash clock on clock out
01: MPX clock on clock out pin
10: PCI clock on clock out pin
11: Reserved
Confidential
Reset: 0x01value of CLOCK_SELECT[1:0]

[0] RESERVEDPCI_CLOCK_MASTER:
The configuration of EMISS as a PCI clock master or clock slave is inferred from this bit. The
appropriate logic to select the internal or external clock to be PCI clock is expected to be
instantiated within the EMISS.
0: PCI Clock slave
1: PCI Clock master
Reset: 0x0value of PCI_CLOCK_MASTERNOTSLAVE
3.3
EMI register descriptions
EMI_STA_CFG
EMI status configuration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CFG_UPDATED
Address:
EMIConfigBaseAddress + 0x0010
Type:
Read
Reset:
Undefined
Description:
If bit n is set, then all configuration registers associated with bank n have been written
to at least once.
[31:5] RESERVED
[4:0] CFG_UPDATED: EMI status configuration
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[5] PCI_HOST_NOT_DEVICE:
The PCI mode supported by EMISS is inferred by this bit.
0: Device
1: Host
Reset: 1(Host)
EMI registers
STi7105
EMI_STA_LCK
EMI status configuration lock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CFG_LCK
Address:
Type:
Read
Reset:
Undefined
Description:
If bit n is set, then all configuration registers associated with bank n are locked and
further write accesses are ignored.
[31:5] RESERVED
[4:0] CFG_LCK: EMI status configuration lock
EMI_LCK
EMI lock
9
RESERVED
PROTECT
Address:
Type:
R/W
Reset:
Undefined
Description:
If bit n is set, then the registers EMI_BANKn.EMI_CFG_DATA[0:3] may only be read.

Subsequent writes to these registers are ignored.
[31:5] RESERVED
[4:0] PROTECT: EMI lock
EMI general purpose
Address:
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8137791 RevA
CSD_EN
CSD_EN
RESERVED
RESERVED
RESERVED
RESERVED
PC_CARD_EN_C
PC_CARD_EN_D
PC_CARD_EN_C
PC_CARD_EN_D
RETIMING_STAGES
MPX_CS_MUX_SEL
MPX_CLK
ENABLE_DACK
RESERVED
VERIFY_MPX
STROBE_ON_FALLING
DISABLE_PULLDOWN DISABLE_PULLDOWN
ADD_DELAY
ADD_DELAY
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RETIMING_STAGES
EMI_GEN_CFG
RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
STi7105
EMI registers
Type:
R/W
Reset:
0x00
Description:
Used to propagate general purpose outputs.
[31:16] RESERVED
[15] ADD_DELAY: add extra delay on EMI clock
In dual STi7105 configuration allows a better MPX clock balancing,
[13] VERIFY_MPX: MPX in loopback mode.

Verifies EMI EMPI connection on same device.
[12] STROBE_ON_FALLING: strobe on falling for MPX bank.
To be set if an EMI bank, configured as MPX, has got the strobes on falling feature activated.
[11] MPX_CLK: MPX clock on flash clock
When an EMI bank is configured in MPX mode inside the device generating the MPX clock,
this bit must be set to map MPX clock on EMIFLASHCLK pad
Confidential
[10] ENABLE_DACK: must be set to enable DACK signals generation on EMI side during an MPX
transaction.
[9:7] MPX_CS_MUX_SEL:
001: CSA
010: CSB
---101: CSE
[13:7] RESERVED
[6:5] RETIMING_STAGES: number of synchronization stages on the wait signal.
00: single retiming stages (this config is mandatory when at least an EMI bank in MPX mode)
01: double retiming stage
10: no retiming stage
[4] PC_CARD_EN_D: enable PC card on bank D
[3] PC_CARD_EN_C: enable PC card on bank C
[2:1] RESERVED
[0] CSD_EN:
0: CSD pad is reconfigured as address EMIADD[25] if MODE pin[9] is set to 1
1: CSD pad retains its CSD functionality
EMI_FLASH_CLK_SEL
7
EMI flash burst clock select

5
RESERVED
FLASH_CLK_SEL
Address:
Type:
WO
Reset:
Undefined
8137791 RevA
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[14] DISABLE_PULLDOWN: disable pull down on ewait pad.

Disables the default pull down on EMITREADYORWAIT pad
EMI registers
STi7105
Description:
[7:2] RESERVED
[1:0] FLASH_CLK_SEL: Set clock ratio for burst flash clock.
00: 1:1 flash operates at CLK_EMI
01: 1:2 flash operates at 1/2 of CLK_EMI
10: 1:3 flash operates at 1/3 of CLK_EMI 11: Reserved
EMI MPX clock select

5
RESERVED
0
MPX_CLK_SEL
Address:
Type:
WO
Reset:
10
Description:
Set clock ratio for MPX
Confidential
[7:2] RESERVED
[1:0] MPX_CLK_SEL: Set clock ratio for MPX
00: 1:1 MPX operates at CLK_EMI
01: 1:2 MPX operates at 1/2 of CLK_EMI
10: 1:3 MPX operates at 1/3 of CLK_EMI 11: Reserved
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8137791 RevA
EMI_MPX_CLK_SEL
STi7105
EMI registers
EMI_CLK_EN
7
EMI clock enable

6
RESERVED
Address:
Type:
WO
Reset:
0x00
Description:
A write of 1 to this bit causes the flash clocks to be updated.
0
CLK_EN
This operation can only occur once, further writes to this register may lead to
undefined behavior.
[31:5] RESERVED
Confidential
[4:0] CLK_EN: EMI lock enable
8137791 RevA
47/454
EMI registers
3.3.1
STi7105
Configuration register formats for peripherals

The following is a summary of the configuration register formats for peripherals.
EMI configuration data 0
Type:
R/W
Reset:
0x00
1
DEVICETYPE
PORTSIZE
BEACTIVE
CSACTIVE
Confidential
Description:
[31:27] RESERVED
[26] WE_USE_OE_CFG: This bit must be set to one in case the SFlash bank (such as
STM58LW064A/B) requires a configurable EMIRDNOTWR signal for async write operation.
When this bit is set to one the WE becomes low following the same timing defined for
OEE1TIMEWRITE and OEE2TIMEWRITE
Otherwise (bit set to 0) the EMIRDNOTWR becomes low at the start of the access and is
deactivated at the end of the access
[25] WAITPOLARITY: Set the wait signal polarity:
0: Wait active high
1: Wait active low
[24:20] LATCHPOINT: Number of EMI subsystem clock cycles before end of access cycle.
0 0000: End of access cycle0 0001: 1 cycle
0 0010: 2 cycles
0 0011: 3 cycles
0 0100: 4 cycles
0 0101: 5 cycles
0 0110: 6 cycles
0 0111: 7 cycles
0 1000: 8 cycles
0 1001: 9 cycles
0 1010: 10 cycles
0 1011: 11 cycles
0 1100: 12 cycles
0 1101: 13 cycles
0 1110: 14 cycles
0 1111: 15 cycles
1 0000: 16 cycles
Other: Reserved
[19:15] DATADRIVEDELAY: 0 to 31 phases
[14:11] BUSRELEASETIME: 0 to15 cycles
[10:9] CSACTIVE:
[8:7] OEACTIVE:
48/454
8137791 RevA
Address:
BUSRELEASETIME
DATADRIVEDELAY
LATCHPOINT
WAITPOLARITY
RESERVED
WE_USE_OE_CFG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OEACTIVE
EMI_CFG_DATA0
STi7105
EMI registers
[6:5] BEACTIVE:
[4:3] PORTSIZE:
00: Reserved
10: 16-bit
01: Reserved
11: 8-bit
[2:0] DEVICETYPE:
001: Normal peripheral or 100: Burst flash
31
30
29

28
CYCLE
NOT
PHRD
27
25
24
23
ACCESSTIMEREAD
15
14
13
12
11
OEE1TIMEREAD
Confidential
26
10
22
21
20
19
CSE1TIMEREAD
9
OEE2TIMEREAD
Address:
Type:
RO
Reset:
0x00
18
17
16
CSE2TIMEREAD
4
BEE1TIMEREAD
BEE2TIMEREAD
Description:
[31] CYCLENOTPHRD: Change measure unit for e1/e2 time accesses from phases to cycles:
0: The e1(e2) write times for CS, BE and OE are expressed in EMI system clock phases.
1: Write times are expressed in cycles.
[30:24] ACCESSTIMEREAD: 2 to 127 EMI subsystem clock cycles: value 0 and 1 are reserved.
[23:20] CSE1TIMEREAD: Falling edge of CS. 0 to 15 phases/cycles after start of access cycle.
[19:16] CSE2TIMEREAD: Rising edge of CS. 0 to 15 phases/cycles before end of access cycle.
[15:12] OEE1TIMEREAD: Falling edge of OE. 0 to 15 phases/cycles after start of access cycle.
[11:8] OEE2TIMEREAD: Rising edge of OE. 0 to 15 phases/cycles before end of access cycle.
[7:4] BEE1TIMEREAD: Falling edge of BE. 0 to 15 phases/cycles after start of access cycle.
[3:0] BEE2TIMEREAD: Rising edge of BE. 0 to 15 phases/cycles before end of access cycle.
EMI_CFG_DATA2
31
30
29
28
CYCLE
_NOT_
PHWR
27
26
25
24
23
ACCESS_TIME_WRITE
15
14
13
12
OEE1_TIME_WRITE
11
10
22
21
20
CSE1_TIME_WRITE
9
OEE2_TIME_WRITE
Address:
Type:
R/W
Reset:
0x00
8137791 RevA
BEE1_TIME_WRITE
19
18
17
16
CSE2_TIME_WRITE
4
BEE2_TIME_WRITE
49/454
EMI_CFG_DATA1
EMI registers
STi7105
Description:
[31] CYCLE_NOT_PHWR: Change measure unit for e1/e2 time accesses from phases to cycles:
0: The e1(e2) write times for CS, BE, OE are expressed in EMI system clock phases.
1: Write times are expressed in cycles.
[30:24] ACCESS_TIME_WRITE: 2 to 127 cycles: value 0 and 1 are reserved
[23:20] CSE1_TIME_WRITE: Falling edge of CS. 0 to 15 phases/cycles after start of access cycle
[15:12] OEE1_TIME_WRITE (WEE1TIMEWRITE): Falling edge of OE. 0 to 15 phases/cycles after

start of access cycle. Also used for falling edge of WE if bit WE_USE_OE_CFG (reg0, bit 26) is
set to one.
[11:8] OEE2_TIME_WRITE (WEE2TIMEWRITE): Rising edge of OE. 0 to 15 phases/cycles before
end of access cycle. Also used for rising edge of WE if bit WE_USE_OE_CFG (reg0, bit 26) is
set to 1.
[7:4] BEE1_TIME_WRITE: Rising edge of BE. 0 to 15 phases/cycles after start of access cycle
0
BURSTMODE
DATALATENCY
RESERVED
STROBEONFALLING
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATAHOLDDELAY
BURST_SIZE
EMI_CFG_DATA3
RESERVED
Confidential
[3:0] BEE2_TIME_WRITE: Falling edge of BE. 0 to 15 phases/cycles before end of access cycle
Address:
Type:
R/W
Reset:
0x00
Description:
Configuration of EMI_CFG_DATA0, EMI_CFG_DATA1, EMI_CFG_DATA2 relates only

to the asynchronous behavior (normal peripheral and normal asynchronous behavior
of flash). These registers must be programmed in terms of CLK_EMI clock cycle.
EMI_CFG_DATA3 must be configured only if there is burst flash and refers to the
synchronous behavior of flash. It does not need to be configured for a normal
asynchronous peripheral. The parameters in this register must be programmed in
terms of flash clock cycles.
[31:27] RESERVED: must be set to 0.

[26] STROBEONFALLING: Flash clock edge for burst strobe generation.
0: rising edge1: falling edge
The strobe on falling feature of EMI means only that strobes, data and address are generated
on the falling edge of the SFlash clock. This does not imply that the same signals are sampled
on the falling edge by the memories. The EMI assumes memory always samples on the rising
edge. The strobes on falling feature has been implemented only to extend the hold time of half
a cycle to help padlogic implementation.
50/454
8137791 RevA
[19:16] CSE2_TIME_WRITE: Rising edge of CS. 0 to 15 phases/cycles before end of access cycle
STi7105
EMI registers
[9:7] BURST_SIZE: The number of bytes which map onto the devices burst mode (only valid in burst
mode).
000: 2
001: 4
010: 8
011: 16
100: 32
101: 64
110: 128
111: Reserved
The 64/128 byte burst mode is due to the possible usage of the AMD device that has a fixed 32word burst length. STBus interface max transfer is 32 bytes on EMI, so in these cases the burst
on flash is always interrupted.
Confidential
[6:2] DATALATENCY: The number of SFlash clock cycles between the address valid and the first
data valid.
00010: 2 cycles
00011: 3 cycles
00100: 4 cycles....
01001: 17 cycles
Others: Reserved
[1] DATAHOLDDELAY: Extra delay when accessing same bank consecutively when in cycles
between words in burst mode.
0: one flash clock cycle
1: two flash clock cycles
[0] BURSTMODE: Select synchronous flash burst mode. If this bit is set, only ACCESSTIMEREAD
and DATAHOLDDELAY are relevant for strobe generation timing during read operations
8137791 RevA
51/454
EMI registers
3.4
STi7105
EMI buffer register descriptions

All the registers described in this section define the base address of each EMI bank and are
nonvolatile.
After reset each EMI bank has a size of 16 Mbyte.
The relationship between each EMI bank reset value and EMI memory space is shown in
Table 14.
EMI bank memory space
EMI memory space
EMI bank
Reset value
address bits
[27:22]
Page
0x0000 0000 to 00FF FFFF
0000 00
on page 52
0x0100 0000 to 01FF FFFF
0001 00
on page 53
0x0200 0000 to 02FF FFFF
0010 00
on page 53
0x0300 0000 to 03FF FFFF
0011 00
on page 53
0x0300 0000 to 03FF FFFF
0100 00
on page 54
0101 00
on page 54
External memory bank 0 base address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BANK0_BASE_ADDR
Address:
BANK0_BASE_ADDR
Type:
R/W
Reset:
0000 00
Description:
Contains the base address bits [27:22] of external memory bank 0. Accesses to this
address space cause transfer on EMI bank 0.
[31:6] RESERVED
[5:0] BANK0_BASE_ADDR: External memory bank 0 base address
52/454
8137791 RevA
Confidential
Table 14.
STi7105
EMI registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BANK1_BASE_ADDR
Address:
BANK1_BASE_ADDR
Type:
R/W
Reset:
0001 00
Description:
[31:6] RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BANK2_BASE_ADDR
Address:
BANK2_BASE_ADDR
Type:
R/W
Reset:
0010 00
Description:
[31:6] RESERVED
[5:0] BANK2_BASE_ADDR: External memory bank 2base address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BANK3_BASE_ADDR
Address:
BANK3_BASE_ADDR
Type:
R/W
Reset:
0011 00
Description:
[31:6] RESERVED
8137791 RevA
53/454
EMI registers
STi7105
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BANK4_BASE_ADDR
Address:
BANK4_BASE_ADDR
Type:
R/W
Reset:
0100 00
Description:
[31:6] RESERVED
Virtual memory bank 5 base address
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BANK5_BASE_ADDR
Address:
BANK5_BASE_ADDR
Type:
R/W
Reset:
0101 00
Description:
This is a virtual bank; its associated ChipSelect signal is not brought out of the
chip so cannot be used. Be aware of this when programming register
EMIB_BANK_EN.
[31:6] RESERVED
54/454
8137791 RevA
STi7105
EMI registers
EMIB_BANK_EN
Enabled bank register
RESERVED
BANKS_EN
Address:
EMIConfigBaseAddress + 860
Type:
R/W
Reset:
110
Description:
Contains the total number of bank registers enabled. When the number of banks is
reduced by register EMIB_BANK_EN, the last bank (that is, the top bank) takes its
own area plus the remaining area of the banks disabled. For example, if only five
banks are enabled, BANK5 is disabled, then BANK4 region contains its own area
plus the BANK5 area. At reset all the banks are enabled.
Confidential
[31:3] RESERVED
[2:0] BANKS_EN: Banks enabled
001: Bank 0 only enabled
010: Banks 0 to 1 enabled
101: All banks with associated ChipSelect enabled (0 to 4)
110: All banks enabled - including shadow bank 5 which has no associated ChipSelect.
8137791 RevA
55/454
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EMI registers
STi7105
EMI MPX configuration
Type:
R/W
Reset:
0x00
DEVICETYPE
WAITSTATESWRITE
WAITSTATEFRAME
Description:
[31:27] RESERVED
Confidential
[26] STROBEONFALLING:
0: Strobes/Data/Address for MPX generated on rising edge of the MPX clock
1: Strobes/Data/Address for MPX generated on falling edge of the MPX clock
[25] WAITPOLARITY: Set the Wait input pin polarity:
0: wait active high
1: wait active low
[24:14] RESERVED
[13] EXTENDEDMPX: When this bit is set, the MPX i/f will use ST MPX super-set opcodes (1X0 =
16 bytes transfer), otherwise the standard set is used.
[12:11] BUSRELEASETIME: Specifies time needed to release the bus for MPX agent:
00: 1MPX clock cycle
01: 2 cycles
10: 3 cycles
11: 4cycles
[10:9] WAITSTATEFRAME: Specifies internal wait to be inserted for accesses (read or write) after
the first:
00: No wait states
01: 1 wait state
10: 2 wait states
11: 3 wait states
[8:6] WAITSTATESREAD: Specifies internal wait to be inserted for first read:
000: 0 wait state
001: 1 wait state
010: 2 wait states
011: 3 wait states
111: 7 wait states
[5:3] WAITSTATESWRITE: Specifies internal wait to be inserted for first read:
000: 0 wait state
001: 1 wait state
010: 2 wait states
011: 3 wait states
111: 7 wait states
[2:0] DEVICETYPE:
001: 011 = MPX. Sets the format of the config register
Note:
56/454
All the configuration values must relate to the MPX clock. The strobe on falling feature of
EMI means only that strobes/data/address are generated on falling edge of the MPX clock.
This DOES NOT imply that the same signal are sampled on the falling edge by the
memories. The EMI assume that the target will always sample on rising edge anyway. The
8137791 RevA
Address:
BUSRELEASETIME
EXTENDEDMPX
RESERVED
WAITPOLARITY
RESERVED
STROBEONFALLING
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WAITSTATESREAD
EMI_MPX_CFG
STi7105
EMI registers
Confidential
STROBES_ON_FALLING feature has been implemented only to possibly extend the HOLD
time of half a cycle to help padlogic implementation.
8137791 RevA
57/454
EMI NAND flash support registers
STi7105

Refer to the STi7105 datasheet for a description of the NAND flash support.
4.1
EMI NAND flash addressing

Configuration register addresses are provided as
EMINANDConfigBaseAddress + offset
EMINAND base address is:
4.2
EMI NAND flash register summary

Table 15.
Confidential
Offset
58/454
EMIBank register list

Register name
Description
Page
0x00
EMINAND_BOOTBANK_CFG
EMI bootbank configuration
59
0x04
EMINAND_RBn_STA
EMI RN status
60
0x10
EMINAND_INT_EN
EMI interrupt enable
61
0x14
EMINAND_INT_STA
EMI interrupt status
62
0x18
EMINAND_INT_CLR
EMI interrupt clear
62
0x1C
EMINAND_INT_EDGE_CFG
EMI interrupt edge config
63
0x40
EMINAND_CTL_TIMING
EMI control timing
63
0x44
EMINAND_WEN_TIMING
EMI WEN timing
64
0x48
EMINAND_REN_TIMING
EMI REN timing
65
0x4C
EMINAND_BLOCK_ZERO_REMAP
EMI block zero remapper
65
0x100
EMINAND_FLEXMODE_CFG
EMI flexmode config
66
0x104
EMINAND_FLEX_MUXCTRL
EMI flex muxcontrol
67
0x108
EMINAND_FLEX_CS_ALT
EMI flex CS alternate
68
0x10C
EMINAND_FLEX_DATAWRT_CFG
EMI flex datawrite config
68
0x110
EMINAND_FLEX_DATA_RD_CFG
EMI flex dataread config
69
0x114
EMINAND_CMD
EMI command
69
0x118
EMINAND_FLEX_ADD_REG
EMI flex address
71
0x120
EMINAND_FLEX_DATA
EMI flex data
72
0x144
EMINAND_VERSION
EMI nand version
72
0x1E0
EMINAND_ADDR_REG1
EMI Nand address register1 73
0x1E4
EMINAND_ADDR_REG2
0x1E8
EMINAND_ADDR_REG3
8137791 RevA
0xFE700000 + 0x1000
STi7105

EMIBank register list (continued)
Description
Page
01EC
EMINAND_MULTI_CS_CFG
EMi Nand multi CS

configuration
74
0x200
EMINAND_SEQ_REG1
EMI sequence reg1
75
0x204
EMINAND_SEQ_REG2
EMI sequence reg2
76
0x208
EMINAND_SEQ_REG3
EMI sequence reg3
76
0x20C
EMINAND_SEQ_REG4
EMI sequence reg4
77
0x210
EMINAND_ADD
EMI address
78
0x214
EMINAND_EXTRA_REG
EMI extra reg
78
0x218
EMINAND_CMND
EMI command
78
0x21C
EMINAND_SEQ_CFG
EMI sequence config reg
79
0x220
EMINAND_GEN_CFG
EMI generic config
80
0x240
EMINAND_SEQ_STA
EMI sequence status
81
EMIBank register descriptions
ENABLE
DATA_8_NOT_16
SW_RESET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS_SHORT_NOT_LONG
EMI bootbank configuration

5
NANDREMAP_OFFSET_NOT_BLOCK
EMINAND_BOOTBANK_CFG
PAGE_LARGE_NOT_SMALL
4.3
Register name
RESERVED
Confidential
Offset
R/
W
R/
W
Address:
EMINANDBaseAddress + 0x00
Type:
R/W
Reset:
0x0
Description:
This register contains default settings on reset. These default settings are inferred
from the static input pins. At boot, the external nand flash is accessed with these
default settings. Some of these default settings can be changed after boot. A soft
reset can be also executed to the boot control logic, by setting the appropriate bit in
this register. The nand flash on boot bank can be read at any time, even after reset,
by executing reads to the boot bank. Other functionality such as erase, program etc.
are supported only through flex mode.
8137791 RevA
59/454
Table 15.
STi7105
The reset value for bits [2:0] is consistent with the value of the input signals, namely
enable = NAND_NOT_ROM, DATA8_NOT_16 = NANDDATA_8_NOT_16 and
ADDRESS_SHORT_NOT_LONG = NANDADD_SHORT_NOT_LONG and
PAGE_LARGE_NOT_SMALL = NANDPAGE_LARGE_NOT_SMALL
[5] NANDREMAP_OFFSET_NOT_BLOCK:
1: Offset remapping
0: Fixed 1 block remapping
[4] PAGE_LARGE_NOT_SMALL:
1: Large page device (page size 2048)
0: Small page device (page size 512)
[2] ADDRESS_SHORT_NOT_LONG:
1: No Extra Address cycle
0: Extra Address cycle
[1] DATA_8_NOT_16:
1: Data width of nand flash is 8 bits
0: Data width of nand flash is 16 bits
[0] ENABLE:
1: Enables the controller
RBN_BOOT
RESERVED
EMI RN status
RBN_FLEX
EMINAND_RBn_STA
RESERVED
Confidential
[3] SW_RESET:
1: resets the boot control logic,
bit needs to be cleared to de-assert soft reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0
Description:
The status of the RBn of the boot bank and flex bank nand flashes can be inferred by
reading this register. If the RBn of a bank is 0 then it has to be inferred that the
external nand flash corresponding to the bank is busy. In the case of multiple banks
supported in flex mode, the RBn status corresponds to the RBn pin status of the
selected bank.
[31:3] RESERVED
[2] RBN_FLEX: Status of RBn pin on flex bank
[1] RBN_BOOT: Status of RBn pin on boot bank
[0] RESERVED
60/454
8137791 RevA
[31:6] RESERVED
STi7105
R/
W
R/
W
R/
W
R/
W
R/
W
R/
W
Address:
Type:
R/W
Reset:
0x0
Description:
An interrupt can be asserted on different conditions by writing 1 into appropriate bits

of the interrupt enable register.
Confidential
[31:7] RESERVED
[6] ECC_FIX_REQD:
0: No interrupt generated
1: Interrupt generated when calculated_ECC XOR read_ECC != 0
[5 SEQUENCE_CHECK:
1: Interrupt generated when a CHECK instruction detects an error bit set
[4] SEQ_DREQ_INT:
1- Interrupt generated on rising edge of seq_Dreq
[3] DATA_DREQ_INT:
1: Interrupt generated on rising edge of data_Dreq
[2] INT_ENB_RBN_FLEX:
1: Enables interrupt on programmed edge of flex bank RBn
[1] RESERVED
[0] ENABLE:
0: Disables all interrupts
8137791 RevA
61/454
ENABLE
DATA_DREQ_INT
INT_ENB_RBN_FLEX
SEQ_DREQ_INT
ECC_FIX_REQD
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
EMI interrupt enable

SEQUENCE_CHECK
EMINAND_INT_EN
STi7105
INT_SEQ_CHECK
INT_SEQ_DREQ
INT_DATA_DREQ
INT_RBN_BANK1
RESERVED
INTERRUPT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0
Description:
The cause of an interrupt can be read by reading into this register.
[31:7] RESERVED
Confidential
[6] INT_ECC_FIX_REQD:
1: Interrput due to ECC_fix_reqd
[5] INT_SEQ_CHECK:
1: Interrupt due to sequence_check
[4] INT_SEQ_DREQ:
1: Interrupt due to seq_Dreq
[3] INT_DATA_DREQ:
1: Interrupt due to data_DReq
[2] INT_RBN_BANK1:
1: Interrupt due to programmed edge of flex bank RBn
[1] RESERVED:
[0] INTERRUPT:
1: Interrupt is pending
EMI interrupt clear
Address:
Type:
R/W
Reset:
0x0
62/454
8137791 RevA
RESERVED
INT_CLR_SEQ_CHK
INT_CLR_RBN_BANK1
INT_ECC_FIX_REQD
INT_SEQ_DREQ
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_DATA_DREQ
EMINAND_INT_CLR
6
INT_ECC_FIX_REQD
EMI interrupt status
RESERVED
EMINAND_INT_STA
STi7105
Description:
An interrupt can be cleared by writing a 1 into appropriate bits of this register.
[31:7] RESERVED
[6] INT_SEQ_DREQ
1: Clears interrupt due to SEQ_DREQ
[5] INT_DATA_DREQ
1: Clears interrupt due to DATA_DREQ
[4] INT_ECC_FIX_REQD:
1: Clears Interrupt ECC_fix_reqd
[2] INT_CLR_RBN_BANK1:
1: Clears Interrupt due to programmed edge of flex bank RBn
[1:0] RESERVED
EMI interrupt edge config

9
0
RBN_EDGECONFIG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Confidential
EMINAND_INT_EDGE_CFG
R/W
Address:
EMINANDBaseAddress + 0x1C
Type:
R/W
Reset:
0x0
Description:
An interrupt can be enabled on a programmed edge of the RBn on flex bank by

writing into this register.
[31:2] RESERVED
[1:0] RBN_EDGECONFIG:
Configures the Edge of RBn on which interrupt has to be generated.
00: Reserved
01: Rising Edge
10: Falling Edge
11: Any Edge
EMINAND_CTL_TIMING
EMI control timing
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WE_HIGH_TO_RBN_LOW_TIME
CE_DEASSERT_HOLD
HOLD
SETUP
R?W
R/W
R/W
R/W
Address:
Type:
R/W
8137791 RevA
63/454
[3] INT_CLR_SEQ_CHK:
1: Clears Interrupt sequence_check
STi7105
Reset:
0x19
Description:
The values mentioned in the timing registers are the fmi clock counts that the
controller waits before asserting or de-asserting a signal. The reset values have been
calculated assuming the freq. of operation on reset to be 200 MHz. For applications
that have a different frequency of operation on reset, these values have to be
changed.
For bits [7:0], the reset value of setup and hold are passed by generics. The values
mentioned in the table are for a boot frequency of 200 MHz.
[23:16] CE_DEASSERT_HOLD: CE de-assertion time

[15:8] HOLD: Hold time for control signal de-assertion wrt WEn or Z on data
[7:0] SETUP: Setup time for assertion control signal assertion wrt WEn(1)
Confidential
1. Value of setup and hold are passed by generics. The values mentioned in the table are for a boot frequency of 200MHz.
EMINAND_WEN_TIMING
EMI WEN timing
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
OFFTIME
ONTIME
R/W
R/W
Address:
Type:
R/W
Reset:
0xE
Description:
The on time and off time of the WEn (Write Enable) signal are held in this register. It is
expected that the data is asserted on the output always on the falling edge of the
WEn signal. It has to be ensured that the off time is more than the data setup time
and on time is more than data hold.
mentioned in the table are for a boot frequency of 200 MHz
[31:16] RESERVED
[15:8] OFFTIME: Off time of WEn pulse
[7:0] ONTIME: On time of WEn pulse
64/454
8137791 RevA
[31:24] WE_HIGH_TO_RBN_LOW_TIME: Time that the Flash device RBn takes to go low after
accepting a command
STi7105
EMI REN timing
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
OFFTIME
ONTIME
R/W
R/W
Address:
Type:
R/W
Reset:
0xE
Description:
The on time and off time of the REn (Read Enable) pulse are held in this register.
While programming this register it has to be ensured that the minimum pulse width
and the cycle time are respected.
mentioned in the table are for a boot frequency of 200 MHz
[31:16] RESERVED
Confidential
[15:8] OFFTIME: Offtime of REn pulse

[7:0] ONTIME: Ontime of REn pulse
EMINAND_BLOCK_ZERO_REMAP
EMI block zero remapper
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BLOCK_ZERO_REMAP_ADD
RESERVED
Address:
Type:
Reset:
0x00
Description:
This
Description:
This is a read only register. This address is used to remap the uppper bits of the
incoming boot address to the first good block address. The first good block found after
the block scanning is written into this register by the controller.
[31:14] BLOCK_ZERO_REMAP_ADD: First good block address.

[13:0] RESERVED
8137791 RevA
65/454
EMINAND_REN_TIMING
STi7105
EMINAND_FLEXMODE_CFG
EMI flexmode config

2
R/
W
R/
W
R/
W
R/W
Address:
Type:
R/W
Reset:
0x10
Description:
Flex mode access can be enabled by setting the FLEX_ENABLE bit in this register.
Confidential
[31:7] RESERVED
[6] RESET_ECC_COUNTER:
1: Resets the ECC counter and ECC_CHECKCODE registers
[5] DATA_LATCHING_TIME:
0: Latch data on the rising edge of REn
1: Latch data one clock cycle after the rising edge of REn(1)
[4] CSN_STATUS:
1: De-asserts CSn of flex bank(2)
Resets to 1
[3] SW_RESET:
1: Soft resets flex control logic of flex banks(3)
[2] RESERVED
[1:0] FLEX_ENABLE:
00: Neither flex nor Advance flex mode enabled
01: Enables Flex mode operations
10: Enables Advance Flex mode operations
11: Illegal
1. For some flash devices where the read_access time is more than the REn_low time, the data can be latched one clock
cycle after the REn is deasserted. However, the DATA_HOLD time should be more than one system clock cycle
2. Read value will be the value of CSn of the current flex bank.
3. The soft reset bit has to be reset to 0 to de-assert the soft reset.The soft reset bit is expected to be asserted for at least
one clock cycle for proper reset
Note:
66/454
Writing 00 into FLEX_ENABLE bit de-asserts all the control signals. Writes or reads to the
flex control registers do not generate any activity on the external nand flash. The transaction
however will be granted. The writes to the configuration bits however update the values of
the configuration
8137791 RevA
FLEX_ENABLE
RESERVED
SW_RESET
CSN_STATUS
DATA_LATCHING_TIME
RESET_ECC_COUNTER
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STi7105
EMINAND_FLEX_MUXCTRL
EMI flex muxcontrol
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VARIABE_M_0_MUXCONTROL
R/W
Type:
R/W
Reset:
0x0
Description:
The contents of this register are directly bristled out on the

BANK_MUXCONTROL[M:0] pins. Flex mode control signals are routed to a bank
depending on the contents of this register.
Address:
Confidential
[31:0] VARIABE_M_0_MUXCONTROL: Mux control bits
8137791 RevA
67/454
STi7105
EMINAND_FLEX_CS_ALT
EMI flex CS alternate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
ALT_CS_BITS
Address:
Type:
R/W
Reset:
0x0
Description:
The contents of this register are directly bristled out on the CS_ALTERNATEL[M:0]
pins. These pins are used to drive the CS pin of the external nand flash when the
bank corresponding to the nand flash is not active on flex mode.
[31:5] RESERVED
1: Bank 0 selected
100: Bank 2 selected
EMINAND_FLEX_DATAWRT_CFG
EMI flex datawrite config
CSN_STATUS
BEAT_COUNT
WAIT_RBN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BYTES_PERBEAT
Confidential
[4:0] ALT_CS_BITS:
0: No bank selection
10: Bank 1 selected
R/
W
R/
W
R/W
R/
W
Address:
Type:
R/W
Reset:
0x0
Description:
The number of beats that have to be generated for each write operation on
FLEX_DATA register are specified in this register. Bytes per beat, dependency on
external RBn, and status of the CSn after the transfer, are all configured in this
register. If the beat count corresponds to four beats, then bytes per beat has to be
zero (one byte per beat). If the beat count is two then beats per byte is either one or
two bytes. It is the responsibility of software to ensure the setting. Hardware provides
no protection. An unjustified beat and beats per byte combination may result in
unknown data being written.
[31] CSN_STATUS:
1: De-asserts CSn after current transfer completion
[30] BYTES_PERBEAT:
0: One byte per beat
68/454
1: Two bytes per beat
8137791 RevA
R/W
STi7105
[29:28] BEAT_COUNT:
00: Four Beats
10: Two beats
01: One Beat

11: Three Beats
[27] WAIT_RBN:
1: Writes data to nand flash only when RBn is at 1
[26:0] RESERVED
EMI flex dataread config
CSN_STATUS
BYTES_PERBEAT
BEAT_COUNT
WAIT_RBN
RESERVED
R/
W
R/
W
R/W
R/
W
Address:
Type:
R/W
Reset:
0x0
Description:
The number of beats that have to be generated for each read operation on
FLEX_DATA register are specified in this register. Bytes per beat, dependency on
RBn, and the status of CSn after the transfer, are all configured in this register.
[31] CSN_STATUS:
1: De-asserts CSn after current transfer completion
[30] BYTES_PERBEAT:
0: One byte per beat
1: Two bytes per beat
[29:28] BEAT_COUNT:
00: Four Beats
10: Two beats
01: One Beat

11: Three Beats
[27] WAIT_RBN:
1: Reads data from external nand only when RBn is at 1
[26:0] RESERVED
EMINAND_FLEXCMD
EMI flex command
RESERVED
BEAT_COUNT
WAIT_RBN
RESERVED
COMMAND
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CSN_STATUS
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EMINAND_FLEX_DATA_RD_CFG
R/
W
R/W
R/
W
R/W
Address:
8137791 RevA
69/454
STi7105
Type:
R/W
Reset:
0x1000 0000
Description:
The programmed command is executed to the external nand flash by writing into this
register. If the CSn of the bank is HIGH, it will be first asserted, then the CLE is
asserted. The WEn will be toggled, with the contents of the field command on I/O
bus to write the command. All the setup and hold timings of the control and data
signals (as held the registers) will be met while the command is executed. The CLE
pin is de-asserted after execution of the command.
In most nand flashes, only one byte of command is written. It is possible to write
commands of multiple bytes using the flex mode, by writing the command which is
more than one byte, and programming the beats appropriately. The functioning of
multiple byte command is as follows. If the beat count is 10 then there will be two
command cycles (CLE asserted and WEn toggled twice). For the first beat,
COMMAND[7:0] will be output on NAND_O[7:0] while for the second beat,
COMMAND[15:8] will be output. If the beat count is 00 (four beats), COMMAND[7:0],
COMMAND[15:8], and COMMAND[23:16] will be written on the first three cycles. For
the fourth cycle 0x00 will be written.
Confidential
If the WAIT_RBN bit is set then the command cycle is executed only when
NAND_RBN_FLEX is at 1.
If CSN_STATUS is 1 then the NAND_CSN_FLEX will be de-asserted after writing
the programmed command.
NOTE: If the CSN_STATUS bit is set in FLEX_COMMAND_REG and
FLEX_ADDRESS_REG the NAND_CSN_FLEX will be de-asserted after the current
command or address execution.
If the bit WAIT_RBN is set then command, address, read or write cycles will be
executed only when NAND_RBN_FLEX pin is at logic 1. No hardware protection is
provided if the RBn is held at 0 for a very long time.
[31] CSN_STATUS:
1: De-asserts CSn after current command
[30] RESERVED
[29:28] BEAT_COUNT: Note: these bits reset to 10. All other bits reset to o
00: Four Beats
01: One Beat
10: Two Beats
11: Three Beats
[27] WAIT_RBN:
1: Wait for RBn to be 1 to execute command
[26:24] RESERVED
[23:0] COMMAND: Command to be written to the external Nand flash
70/454
8137791 RevA
STi7105
EMI flex address
Confidential
CSN_STATUS
ADD8_VALID
BEAT_COUNT
WAIT_RBN
ADDRESS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/W
R/
W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
The programmed address cycle is executed to the external nand flash by writing into
this register. The ALE is asserted. The address bits are output and WEn toggled. The
number of beats is inferred by the BEAT_COUNT bits. The bit8 of the register is either
given out or not, during the address phase, if the ADD8_VALID is 1. All the setup
and hold timings of the control and data signals (as held the registers) will be met
while the address cycles are executed.
If the bit CSN_STATUS is set to 1, the CSn to the external nand flash will be deasserted (to 1) else it is kept asserted.
If the BEAT_COUNT is 00 then for the first three beats the contents of address are
given. For the fourth bit, the most significant nibble (bits 29 to 31) is set to all zeros.
If the ADD8_VALID is 1, the first address beat will have contents ADDRESS[7:0]
second ADDRESS[15:8], third ADDRESS[23:16] and fourth 0b00000 &
ADDRESS[26:24].
If the ADD8_VALID is 0, the first address beat will have contents ADDRESS[7:0]
second ADDRESS[16:9], third ADDRESS[24:17] and fourth 0b000000 &
ADDRESS[26:25].
If the bit WAIT_RBN is 1, then the address cycles will be only executed when the
RBn pin is ready (at 1), else the controller waits till the RBn returns to ready.
[31] CSN_STATUS:
1: De-asserts CSn current Address cycle
[30] ADD8_VALID:
1: Address bit 8 valid
[29:28] BEAT_COUNT:
00: Four Beats
10: Two Beats
01: One Beat

11: Three Beats
[27] WAIT_RBN:
1: Waits till RBn to be 1 to execute address cycles
[26:0] ADDRESS: Address during the address cycles
8137791 RevA
71/454
EMINAND_FLEX_ADD_REG
STi7105
EMINAND_FLEX_DATA
EMI flex data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
Address:
Type:
R/W
Reset:
0x0
Description:
Writing into this register executes writes to the external nand flash with the
configuration held in the register FLEX_DATAWRITE_CONFIG register. It is expected
that the least significant byte/word is written. This register is aliased from 0x120 to
0x13C locations. This facilitates execution of ST32 opcode for writes (in which case
the LSB address bits are toggled).
[31:0] DATA: Data to be written or read into or from external nand flash
EMI NAND version register

7
TERTIARY_BRANCH_VERSION_NO
SECONDARY_BRANCH_VERSION_NO
9
PRIMARY_BRANCH_VERSION_NO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Confidential
EMINAND_VERSION
Address:
Type:
Reset:
0x0
Description:
The register can be read by software to determine the current version of NAND
controller IP. Four bits are defined for primary, secondary and tertiary branch numbers
each.
[31:12] RESERVED
[11:8] PRIMARY_BRANCH_VERSION_NO:
This value represents the primary branch version number of nand contoller IP.
[7:4] SECONDARY_BRANCH_VERSION_NO:
This value represents the secondary branch version number of nand contoller IP.
[3:0] TERTIARY_BRANCH_VERSION_NO:
This value represents the tertiary branch version number of nand contoller IP.
72/454
8137791 RevA
RW
STi7105
EMI NAND address register 1

6
3
ADDR1[0]
ADDR1[1]
ADDR1[2]
ADDR1[3]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
Address:
EMINANDBaseAddress + 0x1E0
Type:
R/W
Reset:
0x0
Description:
The address register provides four address bytes for the CMD instructions for the
second deivce in multi CS setup. The addresses programmed in this register are the
actual addresses that are provided to the NAND flash through the CMD or ADDR
instructions. This register corresponds to the device connected on CSn1 and RBn1
pins.
[23:16] ADDR1[2]: third address byte

[15:8] ADDR1[1]: second address byte
[7:0] ADDR1[0]: first address byte
EMINAND_ADDR_REG2

7
3
ADDR1[0]
ADDR1[1]
ADDR1[2]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR1[3]
Confidential
[31:24] ADDR1[3]: fourth address byte
R/W
R/W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
third deivce in multi CS setup. The addresses programmed in this register are the
pins.

8137791 RevA
73/454
EMINAND_ADDR_REG1
STi7105

6
3
ADDR1[0]
ADDR1[1]
ADDR1[2]
ADDR1[3]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
second deivce in multi CS setup. The addresses programmed in this register are the
pins.

EMINAND_MULTI_CS_CFG
EMI NAND multi CS configuration

5
0
RPT_COUNTER_MCS
RESERVED
NUM_CHIPS
INIT_CHIP
NO_WAIT_RBN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Confidential
R/
W
R/W
R/W
R/W
Address:
EMINANDBaseAddress + 0x1EC
Type:
R/W
Reset:
0x0
Description:
This configuration register is only used when multi CS devices are used.This register
is used to support multi Chip Select devices or a configuration in which multiple FMI
banks have nand flashes connected on them. The NUM_CHIPS bit field defines the
total number of chips connected to the NAND controller. The INIT_CHIP bit field
defines the initial bank number or chip number for the NAND controller to start
operating on.
[31:13] RESERVED
[12] NO_WAIT_RBN
0: Always wait for RBn to be high
74/454
1: Do not wait on RBn
8137791 RevA
EMINAND_ADDR_REG3
STi7105
[11:10] INIT_CHIP: Selects the initial bank/chips for the sequence to operate on. Allowed values are 0
to NUM_CHIPS.
[9:8] NUM_CHIPS: Defines the number_of_chips -1 that are active in the NAND Flash device
connected. By default this number of 0. In case of multi-CS devices or while using multiple
banks for NAND devices this number should represent the number of chips/banks.
[7:2] RESERVED
[1:0] RPT_COUNTER_MCS: Repeat counter for the instruction DEC_JMP_MCS.
EMI sequence reg1
Confidential
1
INSTRUCTION_0
OPERAND_0
INSTRUCTION_1
OPERAND_1
INSTRUCTION_2
OPERAND_2
INSTRUCTION_3
OPERAND_3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
The sequence registers contains the program for 16 instructions that will be executed
by the controller. There are four sequence registers of 32 bit each. The instructions
are executed from 0 to 15. Each complete instruction can be specified in eight bits,
with four bits to specify the instruction and other four bits to specify the operand.
[31:28] OPERAND_3: 4th Operand

[27:24] INSTRUCTION_3: 4th Instruction
[23:20] OPERAND_2: 3rd Operand
[19:16] INSTRUCTION_2: 3rd Instruction
[15:12] OPERAND_1: 2nd Operand
[11:8] INSTRUCTION_1: 2nd instruction
[7:4] OPERAND_0:
First Operand
value: 0 to 15
[3:0] INSTRUCTION_0:
First Instruction
0000: CMD
0010: DEC_JUMP
0100: DATA
0110: CHECK
1000: 1111 : Reserved
0001: INC
0011: STOP
0101: SPARE
0111: ADDR
8137791 RevA
75/454
EMINAND_SEQ_REG1
STi7105
EMI sequence reg2

2
1
INSTRUCTION_4
OPERAND_4
INSTRUCTION_5
OPERAND_5
INSTRUCTION_6
OPERAND_6
INSTRUCTION_7
OPERAND_7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:

EMINAND_SEQ_REG3
EMI sequence reg3

3
1
INSTRUCTION_8
OPERAND_8
INSTRUCTION_9
OPERAND_9
INSTRUCTION_10
OPERAND_10
INSTRUCTION_11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OPERAND_11
Confidential
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
with four bits to specify the instruction and the other four bits to specify the operand.
76/454
8137791 RevA
EMINAND_SEQ_REG2
STi7105

EMINAND_SEQ_REG4
EMI sequence reg4

2
1
INSTRUCTION_12
OPERAND_12
INSTRUCTION_13
OPERAND_13
INSTRUCTION_14
OPERAND_14
INSTRUCTION_15
OPERAND_15
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:

8137791 RevA
77/454
STi7105
EMINAND_ADD
EMI address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
Address:
Type:
R/W
Reset:
0x0
Description:
The address register provides four address bytes for the CMD instructions. The
addresses programmed in this register are the actual addresses that are provided to
the NAND flash through the CMD or ADDR instructions.
[31:0] ADDR[3]: 4th address byte

[23:16] ADDR[2]: 3rd address byte
[15:8] ADDR[1]: 2nd address byte
Confidential
[7:0] ADDR[0]: 1st address byte
EMINAND_EXTRA_REG
EMI extra reg
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EX[3]
EX[2]
EX[1]
EX[0]
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
The extra register provides four extra bytes for CMD and ADDR instructions. The
bytes may be the actual addresses or commands that are to be given to the NAND
Flash through the CMD or ADDR instructions.
[31:0] EX[3]: 4th extra byte

[23:16] EX[2]: 3rd extra byte
[15:8] EX[1]: 2nd extra byte
[7:0] EX[0]: 1st extra byte
EMINAND_CMD
EMI command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMD[3]
CMD[2]
CMD[1]
R/W
Address:
Type:
R/W
Reset:
0x0
78/454
8137791 RevA
CMD[0]
R/W
STi7105
Description:
The commands to be given to nand flash are provided through the four bytes of this
register. Four different commands can be programmed by the user and can be used
by giving CMD instructions. These commands are actual NAND flash commands.
[31:0] CMD[3]: 4th command byte

[23:16] CMD[2]: 3rd command byte
[15:8] CMD[1]: 2nd command byte
[7:0] CMD[0]: 1st command byte
EMI sequence config reg
SEQUENCE_IDENT
REPEAT_COUNTER_RPT
DATA_DIRECTION
GO_STOP
DREQ_HALF_OR_FULL
RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
R/W
R/W
Address:
Type:
R/W
Reset:
0x0
Description:
The sequence configuration register specifies the configuration values of the

sequence. The repeat count field specifies the number of times the DEC_JUMP
instruction is to be repeated. The repeat count register is decremented each time the
JUMP is repeated. When it is zero, the controller moves to the next sequence
programmed. The sequence ident bit field allows the FDMA to keep a track of the
sequences that are being programmed into the controller. A maximum of 256
sequences are supported without overlap. The direction field specifies the direction of
the transfer for the DATA instruction.
[31:27 RESERVED:
[26] GO_STOP:
Starts or stops the execution of the sequence
0: stop
1: go
[25] DREQ_HALF_OR_FULL:
0: Dreq generated when data fifo is half_full or half_empty
1: Dreq generated when the data fifo is full or empty
[24] DATA_DIRECTION:
specifies direction of data transfer
0: Read
1: Write
[23:16] SEQUENCE_IDENT: sequence number
8137791 RevA
79/454
EMINAND_SEQ_CFG
STi7105
[15:0] REPEAT_COUNTER_RPT:
Number of times the JUMP instr is to be repeated
EMI generic config
Confidential
RESERVED
DATA_8_NOT_16
PAGE_SIZE
EXTRA_ADD_CYCLE
RESERVED
MODE_ENABLE_2X8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R/
W
R/
W
R/
W
Address:
Type:
R/W
Reset:
0x0
Description:
The generic configuration register specifies information about the memory that is
being accessed, and also enables the rate control. When the rate control field has a
non zero value written on it, the rate control feature is enabled. The value of the rate
control field specifies the number of STBus cycles that must elapse between two
consecutive DReqs that are issued by the controller.
[31:20] RESERVED
[19] MODE_ENABLE_2X8:
1: Enables the 2X8 mode for advance flex mode
[18] EXTRA_ADD_CYCLE:
0: No extra cycle
1: Extra cycle required
[17] PAGE_SIZE:
0: Small page
1: Large page
[16] DATA_8_NOT_16:
1: data bus size 8
0: data bus size 16
[15:0] RESERVED
80/454
8137791 RevA
EMINAND_GEN_CFG
STi7105
EMI sequence status
Confidential
1
SEQUENCE_COUNT
RUN_STATUS
SEQ_CHK_BITS
CURRENT_CHIP_ACTIVE
RESERVED
SEQ_CHK_BITS_2X8
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0
Description:
The sequence status register is a read only register which specifies the status of the
execution of the sequence. The sequence count specifies the instruction count of the
sequence being executed. The RUN_STATUS field specifies whether the sequence is
running or is paused.
[31:13] RESERVED
[12:11] SEQ_CHK_BITS_2X8: Bit[1:0] of the memory status register bits of the device connected on
the MSB bits in 2X8 mode.
[10:9] RESERVED
[8:7] CURRENT_CHIP_ACTIVE
00: Chip A active
01: Chip B active
10: Chip C active
11: Chip D active
(Valid only till NUM_ACTIVE_CHIPS. So, if NUM_ACTIVE_CHIPS is 01 then only 00 and 01
values are valid)
[6:5] SEQ_CHK_BITS:
Bit[1:0] of the memory status register bits generated during SEQ_CHK instr
[4] RUN_STATUS:
Status of the execution of the sequence
0: paused
1: running
[3:0] SEQUENCE_COUNT: Instruction count of the sequence being executed
8137791 RevA
81/454
EMINAND_SEQ_STA
PCI registers
STi7105
PCI registers
Caution:
5.1
Overview
PCI register addresses are provided as:
PCIBridgeBaseAddress + offset
Table 16 lists the PCI registers
PCI Host Function registers are provided as:

PCIHostBaseAddress + offset
Confidential
where PCIHostBaseAddress is: 0xFE56 0000

Table 17 lists the Host Function registers
PCI Configuration registers are accessed through CRP registers

Table 18 lists the PCI Configuration registers
Table 16.
PCI registers summary
Offset
Register
Description
Page
0x000
PCI_BRIDGE_CONFIG
PCI bridge configuration
on page 84
0x004
PCI_BRIDGE_INT_DMA_ENABLE
PCI bridge DMA interrupt enable
on page 85
0x008
PCI_BRIDGE_INT_DMA_STATUS
PCI bridge DMA interrupt status
on page 86
0x00C
PCI_BRIDGE_INT_DMA_CLEAR
PCI bridge DMA interrupt clear
on page 86
0x010
PCI_TARGID_BARHIT
PCI target function ID and BAR hit

information
on page 87
0x014:
0x03C
RESERVED
0x040
PCI_INTERRUPT_OUT
PCI interrupts to host
on page 88
0x044
PCI_DEVICEINTMASK_INT_ENABLE
PCI device interrupt enable
on page 89
0x048
PCI_DEVICEINTMASK_INT_STATUS
PCI device interrupt status
on page 90
0x4C
PCI_DEVICEINTMASK_INT_CLEAR
PCI device interrupt clear
on page 92
0x050:
0x0FC
RESERVED
0x100:
0x1E4
PCI_BUFFADD0_FUNCn
PCI slave buffer addresses
on page 93
82/454
8137791 RevA
where PCIBridgeBaseAddress is: 0xFE40 1400
STi7105
PCI registers summary (continued)
Offset
Register
Description
Page
0x108:
0x1E8
PCI_FUNCn_BUFF_CONFIG
PCI function buffer configuration
on page 94
0x10C:
0x1EC
PCI_FUNCn_BUFF_DEPTH
PCI function buffer depth
on page 94
0x110:
0x1F0
PCI_CURRADDPTR_FUNCn
PCI function current buffer address pointer
on page 95
0x1F4:
0x1FC
RESERVED
0x200
PCI_FRAME_ADD
PCI frame address
on page 95
0x204
PCI_FRAME_ADD_MASK
PCI frame address mask
on page 96
0x208:
0x2FC
RESERVED
0x300
PCI_BOOTCFG_ADD
PCI boot configuration address
on page 96
0x304
PCI_BOOTCFG_DATA
PCI boot configuration data
on page 97
0x308:
0x3FC
RESERVED
Table 17.
PCI Host Function registers summary
Offset
Register
Description
Page
0x000
PCI_CRP_ADD
PCI CRP address
on page 98
0x004
PCI_CRP_WR_DATA
PCI CRP write data
on page 99
0x008
PCI_CRP_RD_DATA
PCI CRP read data
on page 99
0x00C
PCI_CSR_ADDRESS
PCI CSR address
on page 99
0x010
PCI_CSR_BE_CMD
PCI CSR byte enables and command
on page 100
0x014
PCI_CSR_WR_DATA
PCI CSR write data
on page 100
0x018
PCI_CSR_RD_DATA
PCI CSR read data
on page 100
0x01C:
0x0FC
RESERVED
Table 18.
PCI Configuration registers summary
Offset
Register
Description
Page
0x00
PCI_CCR_ID
PCI CCR vendor and device ID
on page 101
0x04
PCI_CCR_STS_CMD
PCI CCR command and status
on page 101
0x08
PCI_CCR_CODE_REV
PCI CCR class code and revision

identification
on page 102
8137791 RevA
83/454
Confidential
Table 16.
PCI registers
PCI registers
Offset
Register
Description
Page
0x0C
PCI_CCR_LAT_CACHSIZ
PCI CCR cache line size and master

latency
on page 102
0x10
PCI_CCR_MEM_ADD
PCI CCR memory transaction base

address
on page 103
0x14
PCI_CCR_IO_ADD
PCI CCR IO transaction base address
on page 103
0x18
PCI_CCR_NP_MEM_ADD
PCI CCR NonPrefetchable Mem base

address
on page 103
0x1C:
0x28
RESERVED
0x2C
PCI_CCR_SUBSYS_ID
PCI CCR sub-system IDs
on page 104
0x30
RESERVED
0x34
PCI_CCR_CAP_PTR
PCI CCR capability pointer
on page 104
0x38
RESERVED
0x3C
PCI_CCR_INT
PCI CCR interrupt information
on page 104
0x40
PCI_CCR_TIMEOUT
PCI CCR timeout values
on page 105
0x44:
0xD8
RESERVED
0xDC
PCI_CCR_PMC
PCI CCR power management capabilities
on page 105
0xE0
PCI_CCR_PMC_CSR
PCI CCR power management control and

status
on page 105
0xE4:
0xFF
RESERVED
PCI registers
PCI bridge configuration
RESERVED
Address:
PCIBridgeBaseAddress + 0x000
Type:
R/W
Reset:
84/454
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8137791 RevA
RESERVED
PCI_BRIDGE_CONFIG
PCI_RESET
5.2
PCI Configuration registers summary (continued)
WRAP_ENABLE[7:0]
Confidential
Table 18.
STi7105
STi7105
PCI registers
Description:
The PCI bridge is configured by writing to this register. The status of the bridge can
be inferred by reading from this register.
[31:24] WRAP_ENABLE[7:0]: Enable buffer wrapping for the function

[23:16] RESERVED
[15:2] RESERVED
[1] PCI_RESET:
0: PCI block is reset
On power on reset, the PCI interface is held at reset. The reset is de-asserted when a
1 is written to PCI_RESET bit.
PCI bridge DMA interrupt enable
Address:
Type:
R/W
Reset:
INTERRUPT_ENABLE
RESERVED
RESERVED
INT_BRIDGE_UNDEF_FUNC_ENB
RESERVED
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_FUNC_ENB[7:0]
PCI_BRIDGE_INT_DMA_ENABLE
Description:
[31:25] RESERVED
[24] INT_BRIDGE_UNDEF_FUNC_ENB:
1: Enables interrupt when an PCI frame to an unassociated bridge function is received.
[23:16] RESERVED
[15:9] RESERVED
[8:1] INT_FUNC-ENB[7:0]:
1: Enables the corresponding function interrupt
[0] INTERRUPT_ENABLE:
0: Disables interrupt generation globally
The interrupt corresponding to the function n is enabled when the corresponding bit
INT_FUNC_ENB[n] (n is in range 0 to 7) is set to 1. The interrupt is generated when
the bit is set to 1 and the PCI frame fills the buffer depth which is defined in the
register PCI_FUNCn_BUFF_DEPTH for the given function. When the bit
8137791 RevA
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[0] RESERVED
PCI registers
STi7105
INT_BRIDGE_UNDEF_FUNC_ENB is set to 1 an interrupt is asserted if a PCI frame
is received to a function with which a buffer is not associated.
PCI bridge DMA interrupt status

6
Type:
Reset:
Description:
This register shows the DMA interrupt status of the pci bridge. If the interrupt is
asserted then the corresponding bit is set to 1. This register is read only, any writes
to this location will be ignored.
[31:25] RESERVED
[24] INT_BRIDGE_UNDEF_FUNC_STS:
1: Interrupt due to un-associated PCI target function
[23:16] RESERVED
[15:9] RESERVED
[8:1] INT_FUNC-STS[7:0]:
1: Interrupt asserted for the corresponding function
[0] RESERVED
PCI bridge DMA interrupt clear
86/454
8137791 RevA
RESERVED
RESERVED
RESERVED
INT_BRIDGE_UNDEF_FUNC_CLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_FUNC_CLR[7:0]
PCI_BRIDGE_INT_DMA_CLEAR
INT_FUNC_STS[7:0]
RESERVED
RESERVED
Address:
RESERVED
Confidential
RESERVED
INT_BRIDGE_UNDEF_FUNC_STS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PCI_BRIDGE_INT_DMA_STATUS
STi7105
PCI registers
Address:
PCIBridgeBaseAddress + 0x00C
Type:
Reset:
Description:
The PCI bridge DMA interrupt is cleared by writing to this register. The asserted
interrupt is cleared by writing a 1 into the corresponding location. Writing 0 doesnt
clear the interrupt. This register is write only, any reads will return zeros.
[31:25] RESERVED
[23:16] RESERVED
[15:9] RESERVED
[8:1] INT_FUNC-CLR[7:0]:
1: Clears corresponding interrupt
PCI target function ID and BAR hit information

8
PCI_TAR_ID[2:0]
9
PCI_BASE_HITS[2:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PCI_TARGID_BARHIT
RESERVED
Confidential
[0] RESERVED
Address:
Type:
Reset:
Description:
The target function ID (function space addressed by the PCI frame) and the
information if the PCI frame received was IO, memory or dual address cycle is
inferred by reading this register. When the interrupt is asserted due to un-associated
function, reading this register helps in inferring the function space addressed and the
type of PCI frame received. Software can associate any of the buffers from which data
can be accessed by the received PCI frame.
[31:11] RESERVED
8137791 RevA
87/454
[24] INT_BRIDGE_UNDEF_FUNC_CLR:
1: Clear interrupt due to un-associated function
PCI registers
STi7105
[10:8] PCI_BASE_HITS[2:0]:
Target BAR hit information
0: Memory frame
2: Dual address cycle Frame
1: IO frame
3: Reserved
[7:3] RESERVED
[2:0 PCI_TAR_ID[2:0]: Function ID of the PCI frame received
Confidential
Address:
Type:
R/W
Reset:
Description:
The PCI interrupts to the host is driven by writing into this register. This register is
valid in device mode only. The status of the interrupt pins PCI_INT_TO_HOST are
masked however by the contents of 10th bit of command register of the individual
functions. The masking pins are bristled as INTR_DISABLE[7:0] pins from the
STBus-PCI bridge.
[31:29] RESERVED: must be set to 001

[28] PCI_INT[7]: PCI interrupt from function[7]
88/454
8137791 RevA
0
PCI_INT[0]
RESERVED
PCI_INT[1]
RESERVED
RESERVED
PCI_INT[3]
RESERVED
PCI_INT[4]
RESERVED
PCI_INT[5]
RESERVED
PCI_INT[6]
RESERVED
PCI_INT[7]
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PCI interrupts to host
PCI_INT[2]
PCI_INTERRUPT_OUT
STi7105
PCI registers
Interrupt is asserted for the function n when the bit PCI_INTn is set to 1. This pin
also drives the interrupt status bit of the device status register in the PCI functions
configuration space.
0
INT_ENABLE[0]
EDGE_ENABLE[0]
RESERVED
INT_ENABLE[1]
EDGE_ENABLE[1]
EDGE_ENABLE[2]
RESERVED
INT_ENABLE[3]
EDGE_ENABLE[3]
RESERVED
INT_ENABLE[4]
EDGE_ENABLE[4]
RESERVED
INT_ENABLE[5]
EDGE_ENABLE[5]
RESERVED
INT_ENABLE[6]
EDGE_ENABLE[6]
RESERVED
INT_ENABLE[7]
EDGE_ENABLE[7]
Address:
Type:
R/W
Reset:
Description:
The STBus-PCI bridge can be programmed to assert an interrupt on pin

PCI_INT_TO_HOST when the status of the interrupt disable bit changes. This bit is
bit10 of the control register within the PCI configuration space of the function. When
the interrupt is disabled for the function, the function doesnt assert the interrupt on
the corresponding pci interrupts going to host (PCI_INT_TO_HOST).
Software can program the bridge to assert an interrupt on PCI_INT_TO_HOST when
a rising edge occurs or falling edge occurs or any edge occurs on interrupt disable.
The pci function interrupt PCI_INTn bit in PCI_INTERRUPT_OUT register (which is
bit 3 of status register of PCI configuration space) has to be cleared by software.
[31] RESERVED
[30:29] EDGE_ENABLE[7]:
00: Reserved (interrupt not enabled)
10: Interrupt asserted on falling edge
01: Interrupt asserted on rising edge

11: Interrupt asserted on both the edges
[28] INT_ENABLE[7]:
1: Enables interrupt on change in status of interrupt disable bit, bit10 of command register
[27] RESERVED

[24] INT_ENABLE[6]:
[23] RESERVED

[20] INT_ENABLE[5]:
[19] RESERVED
8137791 RevA
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Confidential
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PCI device interrupt enable
INT_ENABLE[2]
PCI_DEVICEINTMASK_INT_ENABLE
PCI registers
STi7105
00: Reserved (interrupt not enabled

[16] INT_ENABLE[4]:
[15] RESERVED
[12] INT_ENABLE[3]:
[11] RESERVED

Confidential
[8] INT_ENABLE[2]:
[7] RESERVED

[4] INT_ENABLE[1]:
[3] RESERVED

[0] INT_ENABLE[3]:
Address:
90/454
8137791 RevA
INT_STATUS[0]
EDGE_STATUS[0]
INTERRUPT_DISABLE[0]
INT_STATUS[1]
EDGE_STATUS[1]
9
EDGE_STATUS[2]
INT_STATUS[3]
EDGE_STATUS[3]
INT_STATUS[4]
EDGE_STATUS[4]
INT_STATUS[5]
EDGE_STATUS[5]
INT_STATUS[6]
EDGE_STATUS[6]
INT_STATUS[7]
EDGE_STATUS[7]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_STATUS[2]
PCI device interrupt status
PCI_DEVICEINTMASK_INT_STATUS

STi7105
PCI registers
Type:
Reset:
Description:
The cause of the interrupt due to change in the value of interrupt disable bit can be
inferred by reading this register.
The bit int_status bit would be set if the interrupt is asserted due to the programmed
edge on the interrupt disable.The last transition on the interrupt disable bit can be
inferred by reading the bits EDGE_STATUS. The status of the interrupt disable bit of
the function can be inferred from the bit INTERRUPT_DISABLE. It is expected that
the status of the pin INT_DISABLE_n_o is connected from the bit
INTERRUPT_DISABLE
[30:29] EDGE_STATUS[7]:
00: Reserved
10: Falling edge occurred last
[31] INTERRUPT_DISABLE[7]: Interrupt disable

01: Rising edge occurred last
11: Reserved
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[28] INT_STATUS[7]:
1: Interrupt asserted
00: Reserved

11: Reserved
[24] INT_STATUS[6]:
00: Reserved

11: Reserved
[20] INT_STATUS[5]:
00: Reserved

11: Reserved
[16] INT_STATUS[4]:
00: Reserved

11: Reserved
[12] INT_STATUS[2]:
8137791 RevA
91/454
PCI registers
STi7105
00: Reserved

11: Reserved
[8] INT_STATUS[2]:
00: Reserved
[4] INT_STATUS[1]:
11: Reserved
[0] INT_STATUS[0]:
PCI device interrupt clear

6
Address:
PCIBridgeBaseAddress + 0x04C
Type:
Reset:
Description:
The cause of the interrupt due to change in the interrupt disable pin status can be
cleared by writing 1 into the appropriate bit in this register.
[31:29] RESERVED
[28] INT_CLEAR[7]:
[27:25] RESERVED
[24] INT_CLEAR[6]:
[23:21] RESERVED
[20] INT_CLEAR[5]:
92/454
8137791 RevA
0
INT_CLEAR[0]
RESERVED
INT_CLEAR[1]
RESERVED
RESERVED
INT_CLEAR[3]
RESERVED
INT_CLEAR[4]
RESERVED
INT_CLEAR[5]
RESERVED
INT_CLEAR[6]
RESERVED
INT_CLEAR[7]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_CLEAR[2]
PCI_DEVICEINTMASK_INT_CLEAR
RESERVED
Confidential
00: Reserved

11: Reserved
STi7105
PCI registers
[19:17] RESERVED
[16] INT_CLEAR[4]:
[15:13] RESERVED
[12] INT_CLEAR[3]:
[11:9] RESERVED
[8] INT_CLEAR[2]:
[4] INT_CLEAR[1]:
[3:1] RESERVED
PCI slave buffer addresses
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
PCIBridgeBaseAddress + 0x100 + 0x20*n (where n= 0 to 7)
Type:
R/W
Reset:
RESERVED
PCI_BUFFADD0_FUNCn
BUFFER_ADDRESS
Confidential
[0] INT_CLEAR[0]:
Description:
[31:2] BUFFER_ADDRESS: Address translation for target transaction between PCI memory space
and physical memory space
[1:0] RESERVED: Buffer address always word aligned
When the PCI interface is acting as target, it receives PCI frames. The received PCI
frames can be programmed to fill or empty a buffer. A maximum of 8 such buffer
spaces can be supported, which are referred to as buffer functions. These are
represented as n.
A buffer is are allocated for each buffer function in the slave mode. When a PCI frame
is received for a buffer function, the starting address of the buffer where the data has
to be stored or retrieved from is inferred from the corresponding buffer address,
denoted by this register.
8137791 RevA
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[7:5] RESERVED
PCI registers
STi7105
1
BAR_HIT
PCIBridgeBaseAddress + 0x100 + 0x20*n + 0x08 (where n= 0 to 7)
Type:
R/W
Reset:
Description:
The configuration of the buffer is inferred from this register. The content of the bits
BAR_HIT associate the buffer with the memory or IO (DAC Frames are currently not
supported by STBus-PCI bridge) frame received. Each buffer is associated with a
unique target function on PCI. The association of the buffer with the function space of
PCI is inferred from FUNC_ID. The combination of BAR_HIT and FUNC_ID uniquely
associate a buffer (buffer function) with the frame received. The buffer association
with the PCI frame received is active only when bit FUNC_ENABLE is set to 1.
Confidential
Address:
[31] FUNC_ENABLE:
1: Function of association of buffer is active
[30:11] RESERVED
[10:8] FUNC_ID: Relates the PCI function association with buffer
[3:2] RESERVED
[1:0] BAR_HIT:
0: Memory transaction
2: IO transaction
1: NON Prefetchable Mem transaction

3: Reserved
PCI function current buffer depth

9
BUFFER_DEPTH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
PCIBridgeBaseAddress + 0x100 + 0x20*n + 0x0C (where n= 0 to 7)
Type:
R/W
Reset:
94/454
8137791 RevA
0
RESERVED
PCI_FUNCn_BUFF_DEPTH
RESERVED
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FUNC_ID
PCI function buffer configuration
FUNC_ENABLE
PCI_FUNCn_BUFF_CONFIG
STi7105
PCI registers
Description:
The buffer depth for the buffer function n, is inferred from this registers.
Note: The buffer depth has always to be 2k aligned, where k is an integer.

[31:2] BUFFER_DEPTH: Current buffer depth
[1:0] RESERVED
PCI function current buffer address pointer

9
Confidential
0
RESERVED
CURR_ADDRESS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
PCIBridgeBaseAddress + 0x100 + 0x20*n + 0x10 (where n= 0 to 7)
Type:
Reset:
Description:
The current buffers address pointer for the buffer function n, is inferred by reading
these registers. The address is always 32-bit word aligned. Software may use this
register to infer if a buffer is not updated after elapse of a time.
[31:2] CURR_ADDRESS: Current address pointer

[1:0] RESERVED
PCI_FRAME_ADD
PCI frame address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PCI_BASE_ADDRESS
RESERVED
Address:
Type:
R/W
Reset:
Description:
The current buffers address pointer for the buffer function n, is inferred by reading
this register. The address is always 32-bit word aligned. Software may use this
register to infer if a buffer is not updated after elapse of a time.
[31:10] PCI_BASE_ADDRESS: Base address with which the PCI frame is to be generated
[9:0] RESERVED
8137791 RevA
95/454
PCI_CURRADDPTR_FUNCn
PCI registers
STi7105
PCI_FRAME_ADD_MASK
PCI frame address mask

9
Type:
R/W
Reset:
0x3FF
Description:
The amount of STBus address space mapped onto PCI memory space can be
configured by writing to this register. The address translation for the PCI is performed
with the contents of this register and the register PCI_FRAME_ADD. The address
translation is performed on the STBus address bus connected to the STBus-PCI
bridge. The PCI generates the frames with the address received on the STBus, hence
it is sufficient to manipulate the address on the STBus. The lower 10 bits of the
STBus address will be always passed through to STBus bus (and so to PCI) and the
bits 30 and 31 would always be inferred from the register PCI_FRAME_ADD. If the bit
MASK_DISABLE[m] is set to 1, then the STBus address would be passed instead of
the bit PCI_BASE_ADDRESS[m]. If the mask disable bit is 0, then the STBus
transaction would have the address bit PCI_BASE_ADDRESS[m]. If all the bits in the
MASK_DISABLE fields are set to 1, then 1GB of the system space would be
mapped on to the PCI. It is the responsibility of the software to program these bits
depending on the system configuration.
Confidential
Address:
[31:30] MASK_DISABLE[31:30]: Read only, cannot be written

[29:10] MASK_DISABLE[29:10]:
1: Propagates the STBus LSB address to the PCI
[9:0] MASK_DISABLE[9:0]: Read only, cannot be written
PCI_BOOTCFG_ADD
PCI boot configuration address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CFG_OFFSET_ADD
Address:
Type:
R/W
Reset:
Description:
When the reset is de-asserted the STBus-PCI bridge reads default data from a
register bank and configures some of the registers in the PCI configuration space. In
the current implementation, this data is written into a set of memory elements by the
CPU, which acts as the register bank.
96/454
8137791 RevA
MASK_DISABLE[9:0]
MASK_DISABLE[31:30]
MASK_DISABLE[31:30]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STi7105
PCI registers
The CPU writes to these registers and de-assers the reset by writing a 1 into
PCI_RESET bit of the PCI_BRIDGE_CONFIG registers.
The data is written into the locations by the CPU using the PCI_BOOTCFG_ADD and
PCI_BOOTCFG_DATA registers.
The offset address of the configuration buffer has to be written into the register
PCI_BOOTCFG_ADD. Then writing data into PCI_BOOTCFG_DATA writes into the
corresponding memory. A next write will then write the data into the next memory
location. For example, if the data corresponding to all locations has to be written,
write 0x00 into the PCI_BOOTCFG_ADD register. Then the data may be written into
the register PCI_BOOTCFG_DATA.
[7:0] CFG_OFFSET_ADD: Configuration offset address
Confidential
PCI_BOOTCFG_DATA
PCI boot configuration data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CFG_DATA
Address:
Type:
R/W
Reset:
0x0000104A
Description:
Writing into this register results in the write into the boot configuration memory. The
address pointer is automatically updated after read or write to facilitate reading or
writing the consecutive locations.
[31:0] CFG_DATA: Configuration data
8137791 RevA
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[31:8] RESERVED
PCI registers
PCI Host Function registers

PCI CRP address
9
CRP_FUNCTION
RESERVED
CRP_COMMAND
RESERVED
CRP_BYTEENABLE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
PCIHostBaseAddress + 0x000
Type:
R/W
Reset:
Description:
The configuration registers in the PCI space can be accessed by writing the address,
function number, command and byte enables into this register and performing a read
or write from PCI_CRP_RD_DATA or PCI_CRP_WR_DATA registers.
Confidential
Note: This register is accessible only when the bridge is configured as host.
[31:24] RESERVED
[23:20] CRP_BYTEENABLE:
1: Read ahead turned on
[19:16] CRP_COMMAND: Specifies the opcode for the STBus packet
[15:11] RESERVED
[10:8] CRP_FUNCTION
0: Cell based
1: threshold based
[7:0] CRP_ADDRESS:
Specifies number of bytes written before initiating a transaction on STBus for STBus writes.
Specifies number of bytes read by STBus on a STBus read transaction
98/454
8137791 RevA
PCI_CRP_ADD
CRP_ADDRESS
5.3
STi7105
STi7105
PCI registers
PCI_CRP_WR_DATA
PCI CRP write data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WRITE_DATA
Address:
Type:
R/W
Reset:
Description:
[31:0] WRITE_DATA: Write data
Confidential
PCI_CRP_RD_DATA
PCI CRP read data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
READ_DATA
Address:
Type:
R/W
Reset:
Description:
[31:0] READ_DATA: Read data
PCI_CSR_ADDRESS
PCI CSR address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDRESS
Address:
PCIHostBaseAddress + 0x00C
Type:
R/W
Reset:
Description:
This register holds the address for PCI I/O or configuration cycles.
[31:0] ADDRESS: PCI address for I/O and config transactions
8137791 RevA
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PCI registers
STi7105
PCI CSR byte enables and command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
BYTE_ENABLE
COMMAND
Address:
Type:
R/W
Reset:
Description:
This register holds the Byte enables and command for the PCI I/O and configuration
cycles.
[31:8] RESERVED
[7:4] BYTE_ENABLE: Byte enables for I/O and config transactions
Confidential
[3:0] COMMAND: Command for I/O and config transactions
PCI_CSR_WR_DATA
PCI CSR write data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WRITE_DATA
Address:
Type:
Reset:
Description:
The write data for the PCI I/O and command cycles is written into this register. The
PCI cycle is generated once data is written into this register. The PCI address,
command and byte enables are inferred from the contents of the registers
PCI_CSR_ADDRESS and PCI_CSR_BE_CMD. The configuration and IO write
frames are of one data cycle.
[31:0] WRITE_DATA: Write data, reads ignored
PCI_CSR_RD_DATA
PCI CSR read data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
READ_DATA
Address:
Type:
Reset:
Description:
The read data for the PCI I/O and command cycles can be read from this register.
The PCI cycle is generated once data is read from this register. The PCI address,
command and byte enables are inferred from the contents of the registers
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8137791 RevA
PCI_CSR_BE_CMD
STi7105
PCI registers
PCI_CSR_ADDRESS and PCI_CSR_BE_CMD. The configuration and IO read
frames are of one data cycle.
[31:0] READ_DATA: Read data, writes ignored
PCI Configuration registers
PCI_CCR_ID
PCI CCR vendor and device ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
DEVICE_ID
VENDOR_ID
Address:
0x00
Type:
Reset:
Reset value read by config memory.
Description:
The Device and vendor ID can be inferred by reading this register.
[31:16] DEVICE_ID: Device ID

Reset: 0x7105
[15:0] VENDOR_ID: Vendor ID
Reset: 0x104A
PCI_CCR_STS_CMD
PCI CCR command and status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STATUS
COMMAND
Address:
0x04
Type:
R/W
Reset:
Application dependant, defined by the Host at system boot.
Description:
The command and status register in the PCI configuration register space is shown
below.
[31:16] STATUS: Status can be read from this field

[15:0] COMMAND: Command can be read or written into this field
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5.4
PCI registers
STi7105
PCI_CCR_CODE_REV
PCI CCR class code and revision identification
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CLASS_CODE
REVISION_ID
Address:
0x08
Type:
Reset:
Description:
The class code and revision identification register format is shown below.
[15:0] REVISION_ID: Class code identifies the generic function of device
PCI CCR cache line size and master latency

8
CACHELINE_SIZE
RESERVED
HEADER_TYPE
MASTER_LATENCY
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BIST
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PCI_CCR_LAT_CACHSIZ
Address:
0x0C
Type:
R/W
Reset:
Description:
The cache line size, master latency, header type and BIST are inferred by reading this
registers.
[31:24] BIST: BIST Register as per PCI standard

[23:16] HEADER_TYPE: Header type
[15:10] MASTER_LATENCY: Master Latency in terms of four clocks (since two LSBs are 0) when
other master is requesting
[9:8] RESERVED
[7:0] CACHELINE_SIZE: Cache line size
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[31:16] CLASS_CODE: Status cam be read from this field
STi7105
PCI registers
PCI_CCR_MEM_ADD
PCI CCR memory transaction base address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
0x10
Type:
R/W
Reset:
0x00000008
Description:
The base address for the memory transactions for the function in the device is written
into this register.
[31:0] ADDRESS: Base Address for PCI memory transactions
PCI_CCR_IO_ADD
PCI CCR IO transaction base address
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IO_ADDRESS
Address:
0x14
Type:
R/W
Reset:
0x00000001
Description:
The base address for the IO transactions for the function in the device is written into
this register.
[31:0] IO_ADDRESS: Base Address for PCI IO transactions
PCI_CCR_NP_MEM_ADD
PCI CCR NonPrefetchable Mem base address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NP_MEM_ADDRESS
Address:
0x18
Type:
R/W
Reset:
0x00000000
Description:
The base address for the NonPrefetchable Mem transactions for the function in the
device is written into this register.
[31:0] NP_MEM_ADDRESS: Base Address for PCI NonPrefetchable MEM transactions
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ADDRESS
PCI registers
STi7105
PCI_CCR_SUBSYS_ID
PCI CCR sub-system IDs
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BIST
MASTER_LATENCY
Address:
0x2C
Type:
Reset:
Description:
The sub-system ID and sub-system vendor ID can be inferred by reading this register.
[15:0] SUBSYS_VENDOR_ID: Sub-system Vendor ID
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PCI_CCR_CAP_PTR
PCI CCR capability pointer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CAP_PTR
Address:
0x34
Type:
Reset:
Description:
The capability pointer register provides an offset into the PCI configuration space for
location of first item into capabilities linked list.
[31:8] RESERVED
[7:0] CAP_PTR: Capabilities linked list pointer
PCI_CCR_INT
PCI CCR interrupt information
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MAX_LAT
MIN_GNT
Address:
0x3C
Type:
R/W
INT_PIN
INT_LINE
Reset:
Description:
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The minimum, maximum latency and information on the interrupt can be inferred by
reading this register.
8137791 RevA
[31:16] SUBSYS_ID: Sub-system ID
STi7105
PCI registers
[31:24] MAX_LAT: (RO) Identifies maximum latency value

[23:16] MIN_GNT: (RO) Identifies the minimum length of the burst
[15:8] INT_PIN: (RO) Identifies pin to which controller is connected
PCI_CCR_TIMEOUT
PCI CCR timeout values
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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RESERVED
RETRY_TIMEOUT
TRDY_TIMEOUT
Address:
0x40
Type:
R/W
Reset:
0x80
Description:
TRDY timeout and retry timeout values are inferred by reading this register.
[31:16] RESERVED
[15:8] RETRY_TIMEOUT: Retry time out in PCI clocks
[7:0] TRDY_TIMEOUT: TRDY time out in PCI clocks
PCI_CCR_PMC
PCI CCR power management capabilities
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PMC
Address:
0xDC
Type:
R/W
NEXT_PTR
CAPABILITY_ID
Reset:
Description:
Power management capabilities of the PCI controller can be inferred by reading this
register.
[31:16] PMC: Power management capabilities

Reset value is device specific
[15:8] NEXT_PTR: Points to the next element in power management capabilities
Reset: 0x00
[7:0] CAPABILITY_ID: When 01 identifies linked list has power management registers
Reset: 0x01
PCI_CCR_PMC_CSR
PCI CCR power management control and status

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[7:0] INT_LINE: Identifies the Interrupt line register to which controller is connected
Reset: 0x00
PCI registers
STi7105
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DATA
BUS_STATUS
Address:
0xE0
Type:
R/W
CONTROL_STATUS
Reset:
Description:
The power management control and status is inferred from this register.
[31:24] DATA: Power state dependent data
[23:16] BUS_STATUS: Power management Bus status

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[15:0] CONTROL_STATUS: Power Management Control and Status bits

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Reset: 0x00
STi7105
USB 2.0 host (USBH)
USB 2.0 host (USBH)
6.1
Overview
This chapter describes the functional operation of the universal serial bus host (USBH)
interface module implemented on the STi7105.
The interface works with an embedded microcore. It is compliant with both the EHCI and
OHCI (USB 2.0 and USB 1.1) bus control standards, supporting low, full and high speed,
isochronous, bulk, interrupt and control transfers.
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A typical USB system consists of:
the client software and USB driver
host controller driver (HCD)
host controller (HC)
USB device
The client software, USB driver and host controller driver are implemented in software. The
host controller and USB device are implemented in hardware.
6.1.1
References
For further details of USB functionality the references below can be downloaded from
www.usb.org.
6.2
Universal Serial Bus Specification, revision 2.0
Enhanced Host Controller Interface Specification for Universal Serial Bus, revision 1.0
Universal Serial Bus Specification, revision 1.1
OpenHCI Open Host Controller Interface Specification for USB, revision 1.0a
Operation
The USB 2.0 Host consists of two major blocks: the digital host controller and the PHY
analog physical interface to the bus. These two blocks communicate with each other via the
USB Transceiver Macro Cell Interface (UTMI) and transfer data via an 8-bit/16-bit bus at
60/30 MHz, shown in Figure 14.
The digital host controller includes one USB 2.0 high-speed mode host controller and one
USB 1.1 host controller (see Figure 15).
The high-speed host controller implements an EHCI interface. It is used for all high-speed
communications to high-speed mode devices connected to the root ports of the USB 2.0
host controller. This allows the companion USB 1.1 host controller to communicate with fullspeed and low-speed devices connected to the root ports of the USB 2.0 host controller.
Note:
The USB 2.0 EHCI Host Controller for the STi7105 is set to the CONFIG2 mode of
operation, and incorporates a 32-bit Type 3 initiator interface. CONFIG2 is an always active
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The STi7105 integrates two industry-standard USB2.0 host controllers, and their associated
USB transceivers, to allow connection of external devices to the host. The USB 2.0 Host
Controller (HC) is backward compatible with USB1.1 and supports bus speeds of
1.5/12/480 Mbits/s.
USB 2.0 host (USBH)
STi7105
feature that provides data prefetch to improve throughput, and is fully transparent to
application software.
Each USB host controller shares a PHY and a dedicated PLL.

Figure 14. USB host controller
30 MHz
PLL
USB host controller

USB 1.1
OHCI
Bus
interface
USB 2.0
EHCI
USB0
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STBus
DP
PHY
Alt function
MUXing
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DM
USB device
USB0_PRT_OVRCUR
USB0_PRT_PWR
60 MHz
STi7105
USB 2.0 host (USBH)

Figure 15. USB 2.0 subsystem block diagram
USB 2.0 Host Controller
OHCI_IRQ
EHCI_IRQ
12 MHz
APP_PRT_OVRCUR_I
48 MHz
PHY CLK
T3 Initiator
32-bits
STBus
Interface
EHCI
UMTI
PHY CLK
UTMI
8/16-bits@
60/30 MHz
STBus
60 MHz
48 MHz
Clock
Div
PHY CLK
60 MHz
UTMI
Interface
UTMI PHY CLK

60 MHz
PHY UTMI
EHCI_PRT_PWR_O
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D+
PLL
1.44 GHz
30 MHz
XTAL
D-
Filter &
Data Line
Protection
Port Power
Control
OSC
Gnd
Vcc
Current
Sense
Circuitry
USB device
6.2.1
STBus interface
The block has a 32-bit Type 1 target interface for configuration registers access, and a 32-bit
Type 3 initiator interface. This Type 3 interface is arbitrated between three internal initiators:
one for data transfer from memory to either the EHCI or the OHCI, one for data transfer from
EHCI to memory and one for data transfer from OHCI to memory. The STBus clock is
100 MHz and can be fully asynchronous from the other clocks (EHCI and OHCI clocks).
6.2.2
Interrupts
The interrupts associated with the USB 2.0 host are OHCI_IRQ and EHCI_IRQ. The pins
are outputs from the USB 2.0 host and have active high signal levels. They must be
connected to the STBus interrupt sub-system. When an OHCI or EHCI interrupt occurs it
triggers an interrupt on the STBus and the interrupt handling application responds to this
request. Register OHCI_HC_INT_STA provides status information for interrupt OHCI_IRQ
and register EHCI_USBSTS provides status information for interrupt EHCI_IRQ.
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OHCI
T1 Target
32-bits
USB 2.0 host (USBH)
6.2.3
STi7105
System Configuration
The following STi7105 system configuration registers (as detailed in STi7105 Volume 1,
ADCS 8065507 Rev A) affect the operation of the USB 2.0 host:
USB 2.0 System Configuration registers
Register
Purpose
Status
SYSTEM_STATUS15
Power down acknowledge
SYSTEM_CONFIG4
Current sensing polarity

selection and soft reset
SYSTEM_CONFIG32
Power down request
SYSTEM_CONFIG33
Test
SYSTEM_CONFIG40
Clock selection
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SYSTEM_STATUS0
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Comments
Table 19.
STi7105
USB 2.0 host (USBH) registers
7.1
Base Addresses and Offsets

There are four sets of registers to configure the OHCI (USB 1.1), EHCI (USB 2), AHB bus
(AHB) and the AHB to STBus Protocol Converter (AHBPC).
Register addresses are provided as
AHBBAseAddress + offset, or
OHCIBaseAddress + offset, or
AHBPCBAseAddress + offset
Where :
The AHBBaseAddress is: USBnBaseAddress + 0x00000
The OHCIBaseAddress is: USBnBaseAddress + 0xFFD00
The EHCIBaseAddress is: USBnBaseAddress + 0xFFE00
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The AHBPCBaseAddress is: USBnBaseAddress + 0xFFF00

and where:
USB0BaseAddress is 0xFE10 0000
USB1BaseAddress is 0xFEA0 0000
Registers in Table 20: USB 1.1 host register summary are detailed in the OpenHCI (Open
Host Controller Interface Specification for USB, revision 1.0a.
Registers in Table 21: USB 2.0 host register summary. are detailed in the Enhanced Host
Controller Interface Specification for Universal Serial Bus, revision 1.0.
There are a few additional USB registers described in System configuration registers.
All registers are 32-bits.
Table 20.
USB 1.1 host register summary
Address
offset
Register
Description
Type
(HCD)
Type
(HCD)
0x00
OHCI_HC_REV
Version number of HC
0x04
OHCI_HC_CTRL
Operating modes for HC
R/W
R/W
0x08
OHCI_HC_CMD_STA
Shows status and receives commands from

R/W
HCD
R/W
0x0C
OHCI_HC_INT_STA
Status of events causing interrupts
R/W
R/W
0x10
OHCI_HC_INT_EN
Enables interrupt generation for various

events
R/W
0x14
OHCI_HC_INT_DISABLE
Enables interrupt generation for various

events
R/W
0x18
OHCI_HC_HCCA
HC communication area
R/W
0x1C
OHCI_HC_PER_CURRENTED
Current endpoint descriptor
R/W
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EHCIBaseAddress + offset, or

Table 20.
Address
offset
STi7105
USB 1.1 host register summary

Register
Description
Type
(HCD)
Type
(HCD)
R/W
0x20
OHCI_HC_CTRL_HEADED
0x24
OHCI_HC_CTRL_CURRENTED Current endpoint descriptor of control list
R/W
R/W
0x28
OHCI_HC_BULK_HEADED
R/W
0x2C
OHCI_HC_BULK_CURRENTED Current endpoint descriptor of bulk list
R/W
R/W
0x30
OHCI_HC_DONE_HEAD
Last completed transfer descriptor
R/W
0x34
OHCI_HC_FM_INTERVAL
Frame time interval
R/W
0x38
OHCI_HC_FM_REMAINING
Time remaining in the frame
R/W
0x3C
OHCI_HC_FM_NUMBER
Frame number
R/W
0x40
OHCI_HC_PERIC_START
Earliest time HC can process periodic list
R/W
0x44
OHCI_HC_LS_THOLD
Packet transfer threshold
R/W
0x48
OHCI_HC_RHDESCRIPTORA
Description A of root hub
R/W
0x4C
OHCI_HC_RHDESCRIPTORB
Description B of root hub
R/W
0x50
OHCI_HC_RH_STA
Hub status/change
R/W, R, W
R/W, R
0x54
OHCI_HC_RHPRT_STA_1
Control and report port events
R/W
R/W
Table 21.
Address
offset
First endpoint descriptor of control list
First endpoint descriptor of bulk list
USB 2.0 host register summary.

Register
Description
Type
See Enhanced Host Controller Interface Specification for Universal Serial Bus, revision 1.0
0x00
EHCI_HCAPBASE
Capability register
0x04
EHCI_HCSPARAMS
Host controller structural parameters
R(1)
0x08
EHCI_HCCPARAMS
Host controller capability parameters
0x10
EHCI_USBCMD
USB EHCI command
R/W, R
0x14
EHCI_USBSTS
USB EHCI status
R/WC, R
0x18
EHCI_USB_INT_EN
USB EHCI interrupt enable
R/W
0x1C
EHCI_FRINDEX
USB EHCI frame index
R/W
0x20
EHCI_CTRLDS_SEG
Control data structure segment
R/W
0x24
EHCI_PER_ICLISTBASE
Periodic frame list base address
R/W
0x28
EHCI_ASYNCLIST_ADDR
Next asynchronous list address
R/W
0x50
EHCI_CFG_FLAG
Configure flag register
R/WC, R/W, R
0x54
EHCI_PORTSC_0
Port 0 status and control
R/W
0x90
EHCI_INSNREG00
Programmable microframe base value
R/W
0x94
EHCI_INSNREG01
Programmable packet buffer out/in threshold
R/W
0x98
EHCI_INSNREG02
Programmable packet buffer length (reserved)
R/W
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See OpenHCI Open Host Controller Interface Specification for USB, revision 1.0a
STi7105
Table 21.

USB 2.0 host register summary.
Address
offset
Register
Description
Type
0x9C
EHCI_INSNREG03
Break memory transfer
R/W
0xA0
EHCI_INSNREG04
Debug - reserved
R/W
0xA4
EHCI_INSNREG05
UTMI control and status
R/W
1. May be written when the WRT_RDONLY bit is set.
AHB register summary
Address
offset
Register
Description
Page
0x0000
AHBn_FL_ADJ
Frame length adjustment register
on page 114
0x0008
AHBn_OHCI_INT_STS
Interrupt status register
on page 114
0x0010
AHBn_EHCI_INT_STS
EHCI interrupt status register
on page 115
0x0014
AHBn_STRAP
Strap options register
on page 115
0x0018
AHBn_OHCI
Status register
on page 116
0x001C
AHBn_POWER_STATE
Power management state register
on page 117
0x0020
AHBn_NEXT_POWER_STATE
Next power management state register
on page 117
0x0024
AHBn_SIMULATION_MODE
Simulation mode register
on page 117
0x0028
AHBn_OHCI_0_APP_IO_HIT
Application I/O register
on page 118
0x002C
AHBn_OHCI_0_APP_IRQ1
External interrupt 1 register
on page 118
0x0030
on page 119
0x0034
AHBn_SS_PME_ENABLE
Power management enable register
on page 119
0x0038
AHBn_OHCI_0_LGCY_IRQ
Legacy interrupt request register
on page 120
0x003C
AHBn_EHCI_PME_STATUS_ACK
Power management status ACK register
on page 120
Register address is:

AHBBaseAddress + offset
Where the AHBPCBaseAddress is: USBnBaseAddress + 0x00000
Table 23.
AHBPC summary table : AHB to STBus protocol converter
Address
offset
Register
Description
Page
0x0000
AHBnPC_OPC
Transaction op codes
on page 121
0x0004
AHBnPC_MSG_CFG
Message size
on page 121
0x0008
AHBnPC_CHUNK_CFG
Chunk size
on page 122
0x000C
AHBnPC_SW_RESET
Software reset
on page 122
0x0010
AHBnPC_STATUS
Protocol converter status
on page 122
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Table 22.
STi7105
Register address is:

AHBPCBaseAddress + offset
Where the AHBPCBaseAddress is: USBnBaseAddress + 0xFFF00
AHB Registers
AHBn_FL_ADJ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Address:
AHBBaseAddress + 0x0000
Type:
RW
Reset:
Description:
FL_TIMING
[31:6] RESERVED
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[5:0] FL_TIMING:
R/W. Each decimal value change to this register corresponds to 16 high-speed bit times. The
SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length)
is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF
cycle time of 60000.
FLADJ Value : Frame Length (number of 480 MHz clock periods)
0x00
0x01
0x02
and so on...
0x1F
0x20
and so on..
0x3E
0x3F
59984
60000
60480
60496
Address:
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OHCI_MRMTWKP
OHCI_MBUFFERACCESS
OHCI_SMI
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OHCI_MIRQN
Interrupt status register
OHCI_MSOFN
AHBn_OHCI_INT_STS
59488
59504
59520
7.2
STi7105
Type:
Reset:
Description:
This register implements interrupt states for the OHCI controller.
[31:11] RESERVED
[4] OHCI_SMI: OHCI legacy system management interrupt
[3] OHCI_MIRQN: HCI-Bus General Interrupt
[2] OHCI_MSOFN: OHCI New Frame: Triggered whenever the HC internal frame counter
(HcFmRemaining) reaches "0" and it is in operational state.
[0] OHCI_MRMTWKP: OHCI Remote wake up: Indicates that a remote wakeup event occurred on
one of the down stream ports of the root hub. This is triggered when HC transits from suspend
to resume state.
EHCI interrupt status register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
EHCI_USBSTS
Address:
Type:
Reset:
Description:
This register indicates interrupt states for the EHCI controller.
RESERVED
[31:10] RESERVED
[9:4] EHCI_USBSTS: The bits indicate pending interrupts and various host controller states. These
6 bits indicate the value of the EHCI_USBSTS_O[5:0] pins from the UHOST2C, which in turn
indicate the USBSTS[5:0] register within EHCI.
[3:0] RESERVED
Address:
Type:
R/W
Reset:
0x8
0
RESERVED
OHCI_CNTSEL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SS_WORD_IF
Strap options register

PLL_PWR_DWN
AHBn_STRAP
RESERVED
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AHBn_EHCI_INT_STS
Description:
[31:4] RESERVED
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[1] OHCI_MBUFFERACCESS: OHCI Host Controller Buffer Access Indication: Triggered when
HC is accessing the data buffer indicated by the TD.
STi7105
[3] PLL_PWR_DWN:
Controls the power down of the PLL inside PHY. Must be cleared after 10 s (minimum delay),
to enable the clock outputs from PHY.
All the reads and writes to other registers must be delayed by 250 s after writing a zero.
[2] SS_WORD_IF:
Select the data width of the parallel Interface. 1 = 16-bit, 0 = 8-bit.
[1] OHCI_CNTSEL:
Count select for 1 ms. 1 = real timings (1 ms), 0 = simulation timings
[0] RESERVED
0
OHCI_SPEED
OHCI_SUSPEND
OHCI_RWE
OHCI_GLSUSPEND
Address:
Type:
Reset:
Description:
This is status only register implementation. Please refer to USB 1.1 OHCI Host
Controller Core User Manual (Core Version 2.2, Oct. 2.2 for more information on
these signals).
[31:6] RESERVED
[5] OHCI_CCS: When active this bit indicates the current connect status of the port.
[4] OHCI_DRWE: (Device remote wakeup enable) This bit reflects the HCRHSTATUS DRWE bit.
[3] OHCI_RWE: (Remote wake-up enabled) This bit reflects the RWE bit of HCCONTROL.
[2] OHCI_GLSUSPEND: (Host controller is in global suspend) This bit is active after 5 ms of HC
USB suspend state.
[1] OHCI_SUSPEND: When active, this bit indicates that the port is suspended.
[0] OHCI_SPEED: (Transmit speed to USB port transreceiver) This signal indicates whether it is a
high (12 Mb/s) or low speed (1.5 Mb/s) operation.
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RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
OHCI_DRWE
Status register
OHCI_CCS
AHBn_OHCI
STi7105
Power management state register

9
RESERVED
AHB_PWR_STATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
AHBBaseAddress + 0x001C
Type:
R/W
Reset:
Description:
This register controls the power management for the current state output.
[31:2] RESERVED
[1:0] AHB_PWR_STATE: Power management for the current state input bits from PCI (unused
here).
Next power management state register

9
RESERVED
AHB_NEXT_PWR_STATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
Description:
This register controls the power management for the current state output.
[31:2] RESERVED
[1:0] AHB_NEXT_PWR_STATE: Power management for the next state input bits from PCI (unused
here).
Simulation mode register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
0
AHB_SIMULATION_MODE
AHBn_SIMULATION_MODE
RESERVED
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AHBn_NEXT_POWER_STATE
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AHBn_POWER_STATE

Type:
RW
Reset:
STi7105
Description:
[31:1] RESERVED
[0] AHB_SIMULATION_MODE:
When active this bit sets the PHY in a non-driving mode and enables EHCI in simulation mode.
AHBn_OHCI_0_APP_IO_HIT Application I/O register

7
Type:
RW
Reset:
Description:
[31:1] RESERVED
[0] AHB_OHCI_0_APP_IO_HIT: used for OHCI legacy devices, when active it indicates I/O
access to HC.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
0
AHB_OHCI_0_APP_IRQ1
RESERVED
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Address:
Description:
[31:1] RESERVED
[0] AHB_OHCI_0_APP_IRQ1: External Interrupt 1
Used to indicate external keyboard controller interrupt 1 in case of a mixed environment. When
active this bit causes an emulation interrupt.
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AHB_OHCI_0_APP_IO_HIT
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STi7105

9
Address:
Type:
RW
Reset:
Description:
[0] AHB_OHCI_0_APP_IRQ12: External Interrupt 12

Used to indicate external keyboard controller interrupt 12 in case of a mixed environment.
When active this bit causes an emulation interrupt.
Power management enable register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
0
AHB_SS_PME_EN
AHBn_SS_PME_ENABLE
RESERVED
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[31:1] RESERVED
Description:
[31:1] RESERVED
[0] AHB_SS_PME_EN:
Power management enable: when active this bit indicates the software's power management
ability
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RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AHB_OHCI_0_APP_IRQ12
Address:
Type:
Reset:
Description:
[1] AHB_OHCI_LGCY_IRQ_12_O: (OHCI Legacy IRQ1) This bit is set to 1 when an emulation
interrupt condition exists and OUTPUTFULL, IRQEn and AUXOUTFULL are set.
[0] AHB_OHCI_LGCY_IRQ_1_O: (OHCI Legacy IRQ12) This bit is set to 1 when an emulation
interrupt condition exists and OUTPUTFULL and IRQEn are set and AUXOUTFULL is clear.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0
AHB_EHCI_PME_STATUS
Power management status ACK register

AHB_EHCI_PWR_STATE_ACK
AHBn_EHCI_PME_STATUS_ACK
RESERVED
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[31:2] RESERVED
Description:
[31:2] RESERVED
[1] AHB_EHCI_PWR_STATE_ACK:
This signal indicates the power state change acknowledge from EHCI to the PCI for PCI power
management.
[0] AHB_EHCI_PME_STATUS:
This bit indicates the PME status.
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RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AHB_OHCI_LGCY_IRQ_1_O
Legacy interrupt request register

AHB_OHCI_LGCY_IRQ_12_O
AHBn_OHCI_0_LGCY_IRQ
STi7105
STi7105
7.3
AHBPC Registers
AHB Protocol to STBus.
Address:
AHBPCBaseAddress + 0x0000
Type:
RW
Reset:
Description:
[31:5] RESERVED
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[4] WRITE_EN:
Enable write posting
[3] RESERVED
[2:0] OPCODE
000 = Store4/Load4
001 = Store8/Load8
010 = Store16/Load16
AHBnPC_MSG_CFG
Message size
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
MSG_SIZE
Address:
Type:
RW
Reset:
Description:
The message length in number of packets is programmed in this register.
[31:3] RESERVED
[2:0] MSG_SIZE:
000 = Disable messaging
010 = 4 packet
100 = 16 packet
110 = 64 packet
001 = 2 packet
011 = 8 packet
101 = 32 packet
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OPCODE
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
WRITE_EN
AHBnPC_OPC
AHBnPC_CHUNK_CFG
STi7105
Chunk size
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CH_SIZE
Address:
Type:
RW
Reset:
Description:
The chunk size in number of packets is programmed in this register.
Software reset
9
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
SOFT_RESET
AHBnPC_SW_RESET
001 = 2 packet
011 = 8 packet
101 = 32 packet
Address:
AHBPCBaseAddress + 0x000C
Type:
RW
Reset:
Description:
This register implements the software reset for the protocol converter.
[31:1] RESERVED
[0] SOFT_RESET:
1 has to be written into bit 0 of this register to enable the software reset. The bit has to be reset
to 0 to disable the softreset. When softreset is active the state machines are initialized to the
reset state on rising system clock edge.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
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PC_STATUS
AHBnPC_STATUS
RESERVED
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[2:0] CH_SIZE:
000 = Disable chunk
010 = 4 packet
100 = 16 packet
110 = 64 packet
[31:3] RESERVED
STi7105
Reset:
Description:
This register indicates the state of the protocol converter. It can be used by the
software to ensure that configuration registers are written only when STBus idle.
[31:1] RESERVED
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[0] PC_STATUS:
Indicates the state of the protocol converter
0 = Busy
1 = Idle
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Serial ATA (SATA) subsystem
STi7105

Portions of this chapter Copyright Synopsys 2007 Synopsys, Inc. All rights reserved.
Used with permission.
8.1
Introduction to the SATA subsystem

HDD (hard disk drive) support is provided by an embedded SATA subsystem.
an integrated PHY with 20-bit encoded data interface to the SATA controller
a 3 GHz PLL
SATA host controllers with integrated DMA engine
SSC (spread spectrum clocking) support
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Figure 16. SATA subsystem block diagram
STBus
SATA Controller
intrq_hostc
SATA host controller

TXP
intrq_dmac
TXN
host controller
PHY
STBus
Interface
RXP
DMA
rst_stbus_n
RXN
phy_reset_n
PLL
3 GHz
30 MHz to USB
8.2
References
The SATA interface is based on a host controller block from Synopsys, Inc. For full details,
see the following Synopsys documents:
DesignWare SATA Host Core Databook
DesignWare DW_ahb_dmac Databook
The interface is compliant with the Serial ATA Revision 2.6 specification.
This specification is available from www.serialata.org.
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The SATA subsystem includes:
STi7105
8.3
Key Features
8.3.1
PHY feature list
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8.3.2
Implementation of the Serial ATA PHY layers
Support for 1.5Gbaud Serial ATA
20-bit wide parallel transmit and receive words (STMA interface)
75MHz controller interface clocks
single clock input of 30MHz required for PHY operation
Spread Spectrum Clocking (SSC) supported
Integrated I/O Impedance Adaption with compensation to 100Ohm +/- 10Ohm
Programmable driver and receiver
Hard/Soft macro separation for optimal integration
Multiple lane assembly supported
SATA Controller feature list

The STi7105 incorporates a SATA Controller, providing the following features:
8.4
Compliant with Serial ATA Revision 2.6 specification
Supports 1.5 Gbps
Supports Native Command Queuing (NCQ)
Integrated SATA link layer and transport layer logic
STBus Type1 interface as target for register access
STBus Type2 interface as initiator for DMA
Supports PIO, first party and legacy DMA modes
Supports legacy command queuing
Supports ATA and ATAPI master-only emulation mode (i.e., register and command
compatible with these standards)
Partial and slumber power management modes
8b10b encoding/decoding
OOB sequence generation and detection
Far end loop-back re-timed
DMA supports linked lists
System overview
The SATA subsystem integrates a SATA controller and SATA PHY. The SATA lane consists
of an interface to the device bus, a host controller, a DMA controller and PHY lane.
8.4.1

The SATA host controller operates in three modes.
Transmit: the DMA writes to the host controller when the host controllers transmit
FIFO has space available. After receiving a write request from the DMA controller, the
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The STi7105 incorporates a SATA PHY, providing the following features:
STi7105
SATA host controller receives data from the STBus in one block chunks. While a data
block is being received the SATA host controller is in a BUSY state.
8.4.2
Receive: The DMA reads from the host controller when the host controllers receive
FIFO starts to fill. The STBus is requested and the DMA controller transfers data from
the SATA host controller to the STBus in one block chunks. While a data block is being
received the SATA host controller is in a BUSY state.
PIO mode: in SATA PIO mode data is read from and written to the STBus.
DMA data transfers
8.4.3
1.
The SATA host initializes and enables the DMA controller for a given transfer.
2.
The SATA host issues a bulk transfer command to the DMA controller.
3.
The command is executed and SATA host is notified that data is ready to be sent or
received.
4.
During a read operation, data is read from the external HDD and written to the external
DDR memory via the host controller.
5.
During a write operation, a DMA activate or a DMA setup, the SATA host sends data to
the external HDD.
6.
During such a transfer the host controller is in a BUSY state
7.
The host controller returns to IDLE when all of the data block has been transmitted or
received.
SATA PHY
The PHY handles the low-level SATA protocols and signalling, including the parallel data
serialization and de-serialization, clock recovery and synchronization. It is clocked by an
internal PLL.
8.5
Functional description
8.5.1
Low power management

Power states are controlled by the host driver and the STi7105. The SATA host interface
supports the following three power states.
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PHY ready: the PHY and the main PLL are both active. The interface is synchronized
and ready to receive and send data.
Partial: the PHY is powered but is in a reduced power state. Both signals on the
interface are in a neutral state. The exit latency from this state is not longer than 10 s.
High selects partial power management mode. The cable interface is quiet (no
differential transitions). The SATA clock is running at 30 MHz.
Slumber: the PHY is powered but in a reduced power state. Both signals on the
interface are in a neutral state. The exit latency from this state is not longer than 10 ms.
High selects low power management mode. The cable interface is quiet (no differential
transitions) and the PHY is shut down. The SATA clock runs at 30 MHz.
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The embedded host controller is coupled to the STBus via a local DMA controller that
provides bulk data transfers between the SATA host and the external DDR memory. The
data transfer sequence is listed below.
STi7105
8.5.2
Interrupt management
The SATA subsytem generates the following interrupts:
8.5.3
DMA interrupt request (intrq_dmac): This signal is asserted when any unmasked
DMA interrupt status register is set.
Host controller interrupt request (intrq_hostc): This signal is asserted when any
unmasked SATA host interrupt pending register is set
Reset management
System Reset
rst_stbus_n (STBus reset)
This reset, which is active low, is internally synchronized on each clock domain to generate
synchronously releasing resets. The internal reset is bypassed when tst_reset_mux = 1.
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PHY Reset
The lane reset output (to PHY) from the controller is phy_reset. The lane reset for the PHY
is generated by the link layer, and is also active low. This reset is applied asynchronously
along with the rst_stbus_n reset. This internal reset is also bypassed with the rst_stbus_n
primary reset when tst_reset_mux = 1.
The release is synchronous to the clk_asic coming from the PHY block.
8.6
Clocking
The PHY macrocell provides three clocks which are clk_rbc0, clk_asic and clk_rxoob.
clk_rbc0 is the 75 MHz recovery clock used to strobe reveived data. The 75 MHz clk_asic
clock is used into the link and the transport layer of the host controller. These two clocks are
asynchronous. clk_rxoob is a 30 MHz clock used to detect special character such as
COMINIT, COMWAKE and COMRESET. The SATA PHY macro-cell generates this clock. In
the STi7105, this detection is carried out in the host controller.
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A global system reset is provided by an asychronous reset signal:
Serial ATA (SATA) host
STi7105

9.1
Introduction
Interface layer
Transport layer
Link layer
Figure 17 shows how the SATA host fits into the SATA system.
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Figure 17. SATA system block diagram
9.1.1
References
The SATA host complies with the Serial ATA II specification. Information about Serial ATA
can be found at www.serialata.org.
The SATA specification can be found in the ANSI T13 Committee document 1532D Volume
3 (ATA/ATAPI-7 V3) at http://www.t13.org.
The Serial ATA Specification describes the following:
Defines how a disk drive communicates with a disk controller
Describes how a cable should plug into a connector
Shows connector pin assignments as well as other similar interoperability points
The Serial ATA II Specification does not discuss system design.
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The STi7105 has an embedded SATA subsystem. This provides independent control for an
internal SATA HDD or external eSATA HDD. This chapter describes the host controller of the
SATA subsystem. The host controller provides three functional layers:
STi7105
9.2
Host overview
The SATA host operates primarily in three clock domains: receive (Rx), transmit (Tx), and
application. However, in some systems, an additional clock is supported for Rx OOB signal
detection. The application clock is provided by the system bus; its frequency is applicationspecific. Rx and Tx clocks are generated in the PHY and are 150, 75, or 37.5 MHz for Gen1
(300, 150, or 75 MHz for Gen2), depending on the PHY data width. Most of the link layer
(both receive and transmit data paths) and part of the transport layer operates in the Tx
clock domain. Rx clock is a recovered clock from the PHY and is used for clocking data into
the SATA host and for performing optional 8b/10b decoding, dropping ALIGNs and aligning
data. Finally, the optional Rx OOB clock can be set by the user. See Section 9.3.3: Link layer
on page 131 for more details.
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Note:
All SATA host clocks are asynchronous to each other in general, but the Rx clock cannot
exceed the Tx clock by more than 350 ppm.
The Bus Interface block provides a configurable AHB slave interface, which is used to
connect to the system bus. Host application software (driver) accesses SATA host using a
set of ATA, SATA and SATA host-specific registers. DMA flow control is implemented with
several handshaking signals compatible with the DMA controller.
9.2.1
Internal communication paths

The following subsections describe the basic SATA host functionality in terms of Rx/Tx data,
control paths and layers.
Receive path
The following list highlights the receive path functionality:
Link layer optionally detects Rx OOB signalling sequences from the device and
initializes the system.
Link layer receives SATA frames and primitives from the PHY sent by the device.
Link layer transmits primitives using backchannel to control the data flow.
Link layer optionally performs 10B/8B decoding, data alignment, descrambling,

deframing and CRC checking on the frame FIS (frame payload), stripping SOF, EOF
and other control primitives. A data-stream FIFO (DS FIFO) is used to cross data from
the Rx to the Tx clock domain.
Link layer passes FIS to the transport layer Rx FIFO. The Rx FIFO is a two-clock 33-bit
wide FIFO. Data is written in the Tx clock domain and is read in the application clock
domain, thus providing clock-crossing function for receive data. The Rx FIFO depth is a
configurable parameter.
Transport layer decodes FIS type from the least-significant byte of the FIS first
DWORD.
Transport layer updates ATA/SATA registers if it is a register type FIS. Some FIS types
are used for control only (example: DMA activate FIS).
Transport layer passes data from the Rx FIFO to the system bus using DMA or PIO
modes using the Bus Interface (example: Data FIS). In PIO mode, application software
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SATA is a half-duplex system for data transfers. Either a receive or transmit operation is
performed between the two agents (host and device) at any given time, but not both. Control
traffic (primitives) is full duplex to maintain receiver synchronization. For example, SYNC
primitives are sent continuously while both host and device sides are in their idle states.
STi7105
performs series of reads from the Data register. In DMA mode, Bus Interface requests
transaction from the DMA controller, which in turn generates read access to the
RxFIFO.
Transmit path
Link layer optionally generates Tx OOB signalling sequences to the device and
initializes the system.
Transport layer receives data from the system bus either via DMA channel or from the
ATA/SATA registers after application software writes to them. In PIO mode, application
software performs series of writes to the Data register. In DMA mode, Bus Interface
requests transaction from the DMA controller, which in turn generates write access to
the TxFIFO.
Transport layer constructs the appropriate FIS and passes it to the link layer via Tx
FIFO. The Tx FIFO is a two-clock 33-bit wide FIFO. Data is written in the application
clock domain and read in the Tx clock domain, thus providing clock-crossing function
for transmit data.
Link layer receives FIS from the Tx FIFO, calculates CRC, frames the data by inserting
SOF, EOF and other flow control primitives, scrambles Repeat Primitives and data,
optionally performs 8B10B encoding and multiplexes the data out to the PHY at the
correct data width.
Link layer receives flow control and status primitives from the device on the
backchannel and passes relevant information and status to the transport layer.
Control path
The following list highlights the Control Path functionality:
Link control implements link layer and initialization state machines and interfaces to the
PHY and to the transport layer, as well as controls data movement in both directions.
Link detects all the PHY and link layer errors and passes them to the transport layer. In
addition, the link layer controls PHY interface power management.
Transport control implements SATA transport layer state machine and interfaces to the
link layer and to the bus interface. Various synchronizing modules provides clockcrossing functionality for all control signals and data. The transport layer detects all the
PHY/link layer/transport layer errors and passes them to the Bus Interface.
Bus Interface control (not shown in the block diagram) provides Rx/Tx FIFO control
functions, error handling, ATA/SATA register control, power management, DMA flow
control, PHY control/status, interrupt control.
9.3
Host functional description
9.3.1
STBus Interface
The interface layer is provided by the STBus interface, linking the transport layer and the
system bus through the AHB slave interface. It has a 32-bit target interface for register
configuration and system control, and a 32-bit initiator interface for data transfer. The
initiator interface is used to move data between the system memory and device storage via
DMA transfers. The associated STBus clock is 100MHz and can be fully asynchronous from
the other SATA clocks.
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The following list highlights the Transmit Path functionality:
STi7105
9.3.2
FIS decomposition/construction - these are transport layer functions, which include

reception of the FIS from the RxFIFO and placing the contents into the ATA registers;
forming the FIS from the ATA registers for transmission via TxFIFO.
Interrupt control - ATA master (Device 0) emulation and other SATA host-specific
interrupts.
DMA control - provides DMA controller external handshaking signals and FIFOs flow
control.
Error control - gathers errors from the PHY, link layer, and transport layer and updates
corresponding ATA and SATA error registers.
Host power management control and status.
PHY/link layer status/control - monitors interface state and provides PHY
Register control - implements ATA/ATAPI, SATA and SATA host registers.
Transport layer
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The Transport layer constructs Frame Information Structures (FIS) for transmission and
decomposes received FIS. The following paragraphs outline the transport layer functions.
Transport layer FIS construction

The following list describes how an FIS is constructed:
Gathers FIS content based on the type of FIS requested by the host application layer
software.
Places FIS content in the proper order.
Notifies the link layer of required frame transmission and passes FIS to Link.
Manages TxFIFO flow, notifies Link of required flow control via TxFIFO flags.
Receives frame receipt acknowledge from Link.
Reports good transmission or errors to requesting higher layer.
Transport layer FIS decomposition

The following list describes how an FIS is decomposed:
9.3.3
Receives the FIS from the link layer.
Determines FIS type.
Distributes the FIS content to the locations indicated by the FIS type.
Reports good reception or errors to the application layer.
Link layer
The link layer controls initialization between the link layer, PHY and a connected device. In
addition, the link layer optionally generates and detects OOB signalling, transmits and
receives frames, transmits primitives based on control signals from the transport layer and
PHY, and receives primitives from the PHY layer that are used to control the Transport and
link layers. The link layer also controls power management via control of the PHY and PHY
interface. A summary of the main link layer features are described in the following sections.
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The Bus Interface provides the following functions:
STi7105
Initialization
Negotiates with its peer link layer and PHY to bring the system to an initialized state
ready to transmit and receive data.
Optionally transmits OOB sequences to the PHY, or instructs the PHY to generate
them. These sequences are then forwarded to the remote device PHY per SATA
specifications, causing device PHY initialization.
Optionally receives OOB sequences or condition detection signals from the PHY,
causing advancement in the initialization routine. When OOB detection is performed by
the PHY, the link layer detects these conditions via phy_cominit and phy_comwake
signals from the PHY.
Once it has been determined that the remote device is ready, the link layer transitions
to normal operation.
Power management
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The following list describes the link layer power management process:
Monitors power management signals from the transport layer and PHY.
When power modes are enabled, disables normal data transmission on the Tx interface
and prevents internal Rx data reception until a wake-up request from the transport layer
or a remote device via the PHY is seen. Re-enables PHY interface when transport layer
or remote device request wake-up.
Frame transmission
The following list describes the link layer frame transmission process:
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Negotiates with its peer link layer to transmit a frame, resolves arbitration conflicts if
both host and device request transmission.
Inserts frame envelope around transport layer data (i.e. SOF, CRC, EOF).
Receives data in the form of DWORDs from the transport layer.
Calculates CRC on transport layer data.
Transforms (scrambles) data and Repeat Primitive DWORDs in such a way to distribute
the potential EMI emissions over a broader range.
Optionally performs 8b/10b encoding.
Transmits frame.
Provides frame flow control in response to status from the TxFIFO or the peer link layer.
Receives frame receipt acknowledge from peer link layer.
Reports good transmission or Link/PHY Layer errors to transport layer.
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The following list describes the link layer initialization process:
STi7105
Frame receipt
Acknowledges to the peer link layer readiness to receive a frame.
Receives data in the form of optionally encoded characters from the PHY layer.
Optional decodes the encoded 8b/10b character stream into aligned DWORDs of data.
Performs data alignment/realignment.
Drops Repeat Primitive Data.
De-scrambles the control and data DWORDs received from a peer link layer.
Removes the envelope around frames (i.e. SOF, CRC, EOF Primitives).
Calculates CRC on the received DWORDs.
Compares the calculated CRC to the received CRC.
Provides frame flow control in response to the status from the Rx FIFO or the peer link
layer.
Reports good reception status or Link/PHY Layer errors to transport layer and the peer
link layer.
9.3.4
Physical layer overview
Note:
Physical layer (PHY) is not part of the SATA host. However, the PHY/Link interface has been
designed to be configurable to control and function with almost any PHY. (Some glue logic
might be required for some PHYs).
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The following list describes the link layer frame receipt process:
Serial ATA (SATA) DMA
10
STi7105

There are references to both software and hardware parameters throughout this chapter.
The software parameters are the field names in each register description table and are
prefixed by the register name; for example, the Block Transfer Size field in the control
register is designated as SADMAn_CTRL0.BLOCK_TS.
10.1
SATA DMA transfer types
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A DMA transfer may consist of single or multi-block transfers. On successive blocks of a

multi-block transfer, the SAR0/DAR0 register in the SATA DMA is reprogrammed using
either of the following methods:
Block chaining using linked lists
Auto-reloading
Contiguous address between blocks
On successive blocks of a multi-block transfer, the SADMAn_CTRL0 register is

reprogrammed using either of the following methods:
Auto-reloading
When block chaining, using linked lists is the multi-block method of choice. On successive
blocks, the SADMAn_LLP0 register in the SATA DMA is re-programmed using block
chaining with linked lists.
A block descriptor consists of six registers: SADMAn_... SAR0, DAR0, LLP0, CTRL0,
SSTAT0, and DSTAT0. The first four registers, along with the SADMAn_CFG0 register, are
used by the SATA DMA to set up and describe the block transfer.
Note:
The term Link List Item (LLI) and block descriptor are synonymous.
10.1.1
Multi-block transfers
Multi-block transfers are enabled by setting the configuration parameter,
DMAH_CH0_MULTI_BLK_EN to True.

To enable multi-block transfers using block chaining, you must set the configuration
parameter DMAH_CH0_MULTI_BLK_EN to True and the DMAH_CH0_HC_LLP parameter
to False.
In this case, the SATA DMA re-programs the channel registers prior to the start of each
block by fetching the block descriptor for that block from system memory. This is known as
an LLI update.
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This section includes information on how to program the SATA DMA for a single SATA
interface, but is applicable to either interface in a dual SATA system. An n is used in the
register names to identify which interface is being referred to; for example, the DMA
controller registers are identified by the prefix SADMAn_, where n is the interface number.
STi7105

SATA DMA block chaining uses a linked lists pointer register (SADMAn_LLP0) that stores
the address in memory of the next linked list item. Each LLI contains the corresponding
block descriptors:
1.
SADMAn_SAR0
2.
SADMAn_DAR0
3.
SADMAn_LLP0
4.
SADMAn_CTRL0
5.
SADMAn_SSTATx
6.
SADMAn_DSTATx
The SADMAn_... SAR0, DAR0, LLPx, and CTRL0 registers are fetched from system
memory on an LLI update. If configuration parameter DMAH_CH0_CTL_WB_EN = True,
then the updated contents of the SADMAn_... CTRL0, SSTAT0, and DSTAT0 regregisters
are written back to memory on block completion. Figure 18 and Figure 19 show how to use
chained linked lists in memory to define multi-block transfers using block chaining.
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Figure 18. Multi-block transfer using linked lists when DMAH_CH0_STAT_SRC set to
true
System
Memory
LLI(0)
LLI(1)
Write-back for DSTAT0
Write-back for SSTAT0
Write-back for SSTAT0
CTL0[63:32]
CTL0[63:32]
CTL0[31:0]
CTL0[31:0]
LLP0(1)
LLP0(2)
DAR0
DAR0
SAR0
SAR0
LLP0(0)
LLP0(1)
LLP0(2)
It is assumed that no allocation is made in system memory for the source status when the
configuration parameter DMAH_CH0_STAT_SRC is set to False. If this parameter is False,
then the order of a linked list item is as follows:
1.
SAR0
2.
DAR0
3.
LLP0
4.
CTRL0
5.
DSTAT0
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To set up block chaining, you program a sequence of linked lists in memory.
STi7105
Figure 19. Multi-block transfer using linked lists when DMAH_CH0_STAT_SRC set to
false
System
Memory
LLI(0)
LLI(1)
CTL0[63:32]
CTL0[63:32]
CTL0[31:0]
CTL0[31:0]
LLP0(1)
LLP0(2)
DAR0
DAR0
SAR0
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Note:
LLP0(1)
LLP0(2)
So as not to confuse the SADMAn_... SAR0, DAR0, LLP0, CTRL0, STAT0, and DSTAT0
register locations of the LLI with the corresponding SATA DMA memory mapped register
locations, the LLI register locations are prefixed with LLI; that is, LLI.SAR0, LLI.DAR0,
LLI.LLP0, LLI.SADMAn_CTRL0, LLI.SSTAT0, and LLI.DSTAT0.
Figure 18 and Figure 19 show the mapping of a linked list Item stored in memory to the
channel registers block descriptor.
Rows 6 through 10 of Table 24: Programming of transfer types and channel register update
method on page 137 show the required values of LLP0, SADMAn_CTRL0, and
SADMAn_CFG0 for multi-block DMA transfers using block chaining.
Note:
136/454
For rows 6 through 10 of Table 24, the LLI.SADMAn_CTRL0, LLI.LLP0, LLI.SAR0, and
LLI.DAR0 register locations of the LLI are always affected at the start of every block transfer.
The LLI.LLP0 and LLI.SADMAn_CTRL0 are always used to reprogram the SATA DMA LLP0
and SADMAn_CTRL0 registers. However, depending on the Table 24 row number, the
LLI.SAR0/LLI.DAR0 address may or may not be used to reprogram the SATA DMA
SAR0/DAR0 registers.
8137791 RevA
SAR0
LLP0(0)
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Programming of transfer types and channel register update method
Transfer Type
LLP LOC
=0
LLP_
SRC_EN
(SADMAn
_CTRL0)
RELOAD
_SRC
(SADMAn
_CFG0)
LLP_
DST_EN
(SADMAn
_CTRL0)
RELOAD
_DST
(SADMAn
_CFG0)
SADMAn_C
SAR0
TRL0, LLP0
Update
Update
Method
Method
1. Single-block
Yes
None, user None

reprogram (single)
s
None
(single)
No
2. Auto-reload
Yes
SADMAn_ ConCTRL0,
tiguous
LLP0 are
reloaded
from initial
values
Auto
reload
No
3. Auto-reload
Yes
SADMAn_ Auto
CTRL0,
reload
LLP0 are
reloaded
from initial
values
Contiguous
No
4. Auto-reload
Yes
SADMAn_ Auto
CTRL0,
reload
LLP0 are
reloaded
from initial
values
Auto
reload
No
5. Single-block
No
None, user None

reprogram (single)
s
None
(single)
Yes
6. Linked list
No
SADMAn_ ConCTRL0,
tiguous
LLP0 are
loaded
from next
linked list
item
Linked
list
Yes
7. Linked list
No
SADMAn_ Auto
CTRL0,
reload
LLP0 are
loaded
from next
linked list
item
Linked
list
Yes
8. Linked list
No
SADMAn_ Linked
CTRL0,
list
LLP0 are
loaded
from next
linked list
item
Contiguous
Yes
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Update
Method
Write
Back
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Table 24.

Programming of transfer types and channel register update method
Transfer Type
LLP LOC
=0
LLP_
SRC_EN
(SADMAn
_CTRL0)
RELOAD
_SRC
(SADMAn
_CFG0)
LLP_
DST_EN
(SADMAn
_CTRL0)
RELOAD
_DST
(SADMAn
_CFG0)
SADMAn_C
SAR0
TRL0, LLP0
Update
Update
Method
Method
9. Linked list
No
SADMAn_ Linked
CTRL0,
list
LLP0 are
loaded
from next
linked list
item
Auto
reload
Yes
10. Linked list.
No
SADMAn_ Linked
CTRL0,
list
LLP0 are
loaded
from next
linked list
item
Linked
list
Yes
Note:
DAR0
Update
Method
Write
Back
Write back: This column assumes that the configuration parameter

DMAH_CH0_CTL_WB_EN = True. If DMAH_CH0_CTL_WB_EN = False, then there is
never writeback of the control and status registers regardless of transfer type, and all rows of
this column are No.
Figure 20. Mapping of block descriptor (LLI) in memory to channel registers when
DMAH_CH0_STAT_SRC is set to true
hsize = 32
LLI.DSTAT0
{LLP0[31:2],2b00} + 0x18
LLI.SSTAT0
{LLP0[31:2],2b00} + 0x14
LLI.CTL0[63:32]
{LLP0[31:2],2b00} + 0x10
LLI.CTL0[31:0]
{LLP0[31:2],2b00} + 0xc
LLI.LLP0(1)
{LLP0[31:2],2b00} + 0x8
LLI.DAR0
{LLP0[31:2],2b00} + 0x4
LLI.SAR0
{LLP0[31:2],2b00}
Fixed offsets
32
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base address of LLI

(LLP0.LOC)
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Table 24.
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Figure 21. Mapping of block descriptor (LLI) in memory to channel registers when
DMAH_CH0_STAT_SRC is set to false
hsize = 32
LLI.DSTAT0
{LLP0[31:2],2b00} + 0x14
LLI.CTL0[63:32]
{LLP0[31:2],2b00} + 0x10
LLI.CTL0[31:0]
{LLP0[31:2],2b00} + 0xc
LLI.LLP0(1)
{LLP0[31:2],2b00} + 0x8
LLI.DAR0
{LLP0[31:2],2b00} + 0x4
LLI.SAR0
{LLP0[31:2],2b00}
Fixed offsets
base address of LLI

(LLP0.LOC)
Note:
Throughout this datasheet, there are descriptions about fetching the LLI.SADMAn_CTRL0
register from the location pointed to by the LLP0 register. This exact location is the LLI base
address (stored in LLP0 register) plus the fixed offset. For example, in Figure 20, the
location of the LLI.SADMAn_CTRL0 register is LLP0.LOC + 0xc.
Note:
Referring to Table 24: Programming of transfer types and channel register update method
on page 137, if the Write Back column entry is Yes and the configuration parameter
DMAH_CH0_CTL_WB_EN = True, then the SADMAn_CTRL0[63:32] register is always
written to system memory (to LLI.SADMAn_CTRL0[63:32]) at the end of every block
transfer.
The source status is fetched and written to system memory at the end of every block
transfer if the Write Back column entry is Yes, DMAH_CH0_CTL_WB_EN = True,
DMAH_CH0_STAT_SRC = True, and SADMAn_CFG0.SS_UPD_EN is enabled.
The destination status is fetched and written to system memory at the end of every block
transfer if the Write Back column entry is Yes, DMAH_CH0_CTL_WB_EN = True,
DMAH_CH0_STAT_DST = True, and SADMAn_CFG0.DS_UPD_EN is enabled.
10.1.2
Auto-reloading of channel registers

During auto-reloading, the channel registers are reloaded with their initial values at the
completion of each block and the new values used for the new block. Depending on the row
number in Table 24: Programming of transfer types and channel register update method on
page 137, some or all of the SAR0, DAR0, and SADMAn_CTRL0 channel registers are
reloaded from their initial value at the start of a block transfer.
10.1.3
Contiguous address between blocks

In this case, the address between successive blocks is selected as a continuation from the
end of the previous block.
Enabling the source or destination address to be contiguous between blocks is a function of
the SADMAn_CTRL0.LLP_SRC_EN, SADMAn_CFG0.RELOAD_SRC,
SADMAn_CTRL0.LLP_DST_EN, and SADMAn_CFG0.RELOAD_DST registers (see
Table 24).
Note:
You cannot select both SAR0 and DAR0 updates to be contiguous. If you want this
functionality, you should increase the size of the Block Transfer
(SADMAn_CTRL0.BLOCK_TS), or if this is at the maximum value, use Row 10 of Table 24
and set up the LLI.SAR0 address of the block descriptor to be equal to the end SAR0
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address of the previous block. Similarly, set up the LLI.DAR0 address of the block descriptor
to be equal to the end DAR0 address of the previous block. For more information, refer to
Multi-block transfer with linked list for source and linked list for destination (row 10) on
page 143.
10.1.4
Suspension of transfers between blocks

At the end of every block transfer, an end-of-block interrupt is asserted if:
Interrupts are enabled, SADMAn_CTRL0.INT_EN = 1, and
2.
The channel block interrupt is unmasked, MaskBlock[0] = 1.
The block-complete interrupt is generated at the completion of the block transfer to the
destination.
For rows 6, 8, and 10 of Table 24: Programming of transfer types and channel register
update method on page 137, the DMA transfer does not stall between block transfers. For
example, at the end-of-block N, the SATA DMA automatically proceeds to block N +1.
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For rows 2, 3, 4, 7, and 9 of Table 24 (SAR0 and/or DAR0 auto-reloaded between block
transfers), the DMA transfer automatically stalls after the end-of-block interrupt is asserted,
if the end-of-block interrupt is enabled and unmasked.
The SATA DMA does not proceed to the next block transfer until a write to the ClearBlock[0]
block interrupt clear register, done by software to clear the channel block-complete interrupt,
is detected by hardware.
For rows 2, 3, 4, 7, and 9 of Table 24 (SAR0 and/or DAR0 auto-reloaded between block
transfers), the DMA transfer does not stall if either:
Interrupts are disabled, SADMAn_CTRL0.INT_EN = 0, or
The channel block interrupt is masked, MaskBlock[0] = 0.
Channel suspension between blocks is used to ensure that the end-of-block ISR (interrupt
service routine) of the next-to-last block is serviced before the start of the final block
commences. This ensures that the ISR has cleared the SADMAn_CFG0.RELOAD_SRC
and/or SADMAn_CFG0.RELOAD_DST bits before completion of the final block. The reload
bits SADMAn_CFG0.RELOAD_SRC and/or SADMA_CFG0.RELOAD_DST should be
cleared in the end-of-block ISR for the next-to-last block transfer.
10.1.5
Ending multi-block transfers

All multi-block transfers must end as shown in either Row 1 or Row 5 of Table 24. At the end
of every block transfer, the SATA DMA samples the row number, and if the SATA DMA is in
the Row 1 or Row 5 state, then the previous block transferred was the last block and the
DMA transfer is terminated.
Note:
Row 1 and Row 5 are used for single-block transfers or terminating multi-block transfers.
Ending in the Row 5 state enables status fetch and write-back for the last block. Ending in
the Row 1 state disables status fetch and write-back for the last block.
For rows 2, 3, and 4 of Table 24, (LLP0 = 0 and SADMAn_CFG0.RELOAD_SRC and/or
SADMAn_CFG0.RELOAD_DST is set), multi-block DMA transfers continue until both the
SADMAn_CFG0.RELOAD_SRC and SADMAn_CFG0.RELOAD_DST registers are cleared
by software. They should be programmed to zero in the end-of-block interrupt service
routine that services the next-to-last block transfer; this puts the SATA DMA into the Row 1
state.
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1.
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For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last
block transfer should clear the SADMAn_CFG0.RELOAD_SRC and
SADMAn_CFG0.RELOAD_DST reload bits. The last block descriptor in memory should be
set up so that both the LLI.SADMAn_CTRL0.LLP_SRC_EN and
LLI.SADMAn_CTRL0.LLP_DST_EN registers are zero. If the LLI.LLPx register of the last
block descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the
LLI.LLPx register of the last block descriptor in memory is zero, then the DMA transfer is
terminated in Row 1.
Note:
The only allowed transitions between the rows of Table 24 are from any row into Row 1 or
Row 5. As already stated, a transition into row 1 or row 5 is used to terminate the DMA
transfer; all other transitions between rows are not allowed. Software must ensure that
illegal transitions between rows do not occur between blocks of a multi-block transfer. For
example, if block N is in row 10, then the only allowed rows for block N +1 are rows 10, 5, or
1.
10.2
Programming a channel
Three registers LLP0, SADMAn_CTRL0, and SADMAn_CFG0 need to be programmed
to determine whether single- or multi-block transfers occur, and which type of multi-block
transfer is used. The different transfer types are shown in Table 24.
The SATA DMA can be programmed to fetch status from the source or destination
peripheral; this status is stored in the SSTAT0 and DSTAT0 registers. When the SATA DMA
is programmed to fetch this status from the source or destination peripheral, it writes this
status and the contents of the SADMAn_CTRL0 register back to memory at the end of a
block transfer. The Write Back column of Table 24 shows when this occurs.
The Update Method columns indicate where the values of SAR0, DAR0,
SADMAn_CTRL0, and LLP0 are obtained for the next block transfer when multi-block SATA
DMA transfers are enabled.
Note:
In Table 24, all other combinations of LLP0.LOC = 0, SADMAn_CTRL0.LLP_SRC_EN,

SADMAn_CFG0.RELOAD_SRC, SADMAn_CTRL0.LLP_DST_EN, and
SADMAn_CFG0.RELOAD_DST are illegal, and will cause indeterminate or erroneous
behavior.
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For rows 6, 8, and 10 of Table 24: Programming of transfer types and channel register
update method on page 137 (both SADMAn_CFG0.RELOAD_SRC and
SADMAn_CFG0.RELOAD_DST cleared), the user must set up the last block descriptor in
memory so that both LLI.SADMAn_CTRL0.LLP_SRC_EN and
LLI.SADMAn_CTRL0.LLP_DST_EN are zero. If the LLI.LLP0 register of the last block
descriptor in memory is non-zero, then the DMA transfer is terminated in Row 5. If the
LLI.LLP0 register of the last block descriptor in memory is zero, then the DMA transfer is
terminated in Row 1.
Programming examples
Single-block Transfer (Row 1)
Multi-block transfer with linked list for source and linked list for destination (row 10)
Multi-block transfer with source address auto-reloaded and destination address autoreloaded (row 4)
Multi-block transfer with source address auto-reloaded and linked list destination
address (row 7)
Multi-block transfer with source address auto-reloaded and contiguous destination

address (row 3)
Multi-block dma transfer with linked list for source and contiguous destination address
(row 8)
Single-block transfer (row 1)

This section describes a single-block transfer, Row 1 in Table 24.
Confidential
Note:
Row 5 in Table 24 is also a single-block transfer with write-back of control and status
information enabled at the end of the single-block transfer.
1.
Read the Channel Enable register to choose a free (disabled) channel; refer to
SATAn_DMA_CH_EN.
2.
Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: SATAn_DMA_CLEAR_TFR,
SATAn_DMA_CLEAR_BLOCK, SATAn_DMA_CLEAR_SRC_TRAN,
SATAn_DMA_CLEAR_DST_TRAN, and SATAn_DMA_CLEAR_ERR. Reading the
Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have
been cleared.
3.
Program the following channel registers:

a)
Write the starting source address in the SATAn_DMA_SAR0 register.
b)
Write the starting destination address in the SATAn_DMA_DAR0 register.
c)
Program SADMAn_CTRL0 and SADMAn_CFG0 according to Row 1, as shown in

Table 24.
d)
Write the control information for the DMA transfer in the SADMAn_CTRL0 register
(see page 170). For example, in the register, you can program the following:
i.
Set up the transfer type (memory or non-memory peripheral for source

and destination) and flow control device by programming the TT_FC of the
SADMAn_CTRL0 register.
ii.
Set up the transfer characteristics, such as:

Transfer width for the source in the SRC_TR_WIDTH field.
Transfer width for the destination in the DST_TR_WIDTH field.
Source master layer in the SMS field where the source resides.
Destination master layer in the DMS field where the destination resides.
Incrementing/decrementing or fixed address for the source in the SINC field.
Incrementing/decrementing or fixed address for the destination in the DINC
field.
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10.2.1
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e)
Write the channel configuration information into the SADMAn_CFG0 register (see
page 175).
i.
Designate the handshaking interface type (hardware or software) for the

source and destination peripherals; this is not required for memory.
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits,
respectively. Writing a 0 activates the hardware handshaking interface to
handle source/destination requests. Writing a 1 activates the software
handshaking interface to handle source and destination requests.
2.
After the SATA DMA-selected channel has been programmed, enable the channel by
writing a 1 to the ChEnReg.CH_EN bit. Ensure that bit 0 of the DmaCfgReg register is
enabled.
3.
Source and destination request single and burst DMA transactions to transfer the block
of data (assuming non-memory peripherals). The SATA DMA acknowledges at the
completion of every transaction (burst and single) in the block and carries out the block
transfer.
4.
Once the transfer completes, hardware sets the interrupts and disables the channel. At
this time, you can respond to either the Block Complete or Transfer Complete
interrupts, or poll for the transfer complete raw interrupt status register (RawTfr[n], n =
channel number) until it is set by hardware, to detect when the transfer is complete.
Note that if this polling is used, the software must ensure that the transfer complete
interrupt is cleared by writing to the Interrupt Clear register, ClearTfr[n], before the
channel is enabled.
Multi-block transfer with linked list for source and linked list for destination
(row 10)
Note:
This type of multi-block transfer can only be enabled when the either of the following
parameters is set:
DMAH_CH0_MULTI_BLK_TYPE = NO_HARDCODE
or
DMAH_CH0_MULTI_BLK_TYPE = LLP_LLP
1.
Read the Channel Enable register (see SATAn_DMA_CH_EN on page 191) to choose
a free (disabled) channel.
2.
Set up the chain of linked list Items (otherwise known as block descriptors) in memory.
Write the control information in the LLI.SADMAn_CTRL0 register location of the block
descriptor for each LLI in memory (see Figure 18: Multi-block transfer using linked lists
when DMAH_CH0_STAT_SRC set to true on page 135). For example, in the register,
you can program the following:
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If the hardware handshaking interface is activated for the source or

destination peripheral, assign a handshaking interface to the source and
destination peripheral; this requires programming the SRC_PER and
DEST_PER bits, respectively.
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7.
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a)
Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow control device by programming the TT_FC of the
b)

i.
ii.
iii.
iv.
Destination master layer in the DMS field where the destination resides.
v.
Incrementing/decrementing or fixed address for the source in the SINC

field.
vi.
Incrementing/decrementing or fixed address for the destination in the

DINC field.
Write the channel configuration information into the SADMAn_CFG0 register.

a)
Designate the handshaking interface type (hardware or software) for the source
and destination peripherals; this is not required for memory.
respectively. Writing a 0 activates the hardware handshaking interface to handle
source/destination requests for the specific channel. Writing a 1 activates the
software handshaking interface to handle source/destination requests.
b)
If the hardware handshaking interface is activated for the source or destination

peripheral, assign the handshaking interface to the source and destination
peripheral. This requires programming the SRC_PER and DEST_PER bits,
respectively.
8.
Make sure that the LLI.SADMAn_CTRL0 register locations of all LLI entries in memory
(except the last) are set as shown in Row 10 of Table 24. The LLI.SADMAn_CTRL0
register of the last linked list Item must be set as described in Row 1 or Row 5 of
Table 24: Programming of transfer types and channel register update method on
page 137. Table 18: Multi-block transfer using linked lists when
DMAH_CH0_STAT_SRC set to true on page 135 shows a linked list example with two
list items.
9.
Make sure that the LLI.SAR0/LLI.DAR0 register locations of all LLI entries in memory
point to the start source/destination block address preceding that LLI fetch.
10. If parameter DMAH_CH0_CTL_WB_EN = True, ensure that the

LLI.SADMAn_CTRL0.DONE field of the LLI.SADMAn_CTRL0 register locations of all
LLI entries in memory is cleared.
11. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: SADMAn_... CLEAR_TFR, CLEAR_BLOCK,
CLEAR_SRC_TRAN, CLEAR_DST_TRAN, and CLEAR_ERR. Reading the Interrupt
Raw Status and Interrupt Status registers confirms that all interrupts have been
cleared.
12. Program the SADMAn_CTRL0 and SADMAn_CFG0 registers according to Row 10, as
shown in Table 24: Programming of transfer types and channel register update method
on page 137.
13. Finally, enable the channel by writing a 1 to the ChEnReg.CH_EN bit; the transfer is
performed.
14. The SATA DMA fetches the first LLI from the location pointed to by LLPx(0).
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Note:

The LLI.SAR0, LLI. DAR0, LLI.LLPx, and LLI.SADMAn_CTRL0 registers are fetched. The
SATA DMA automatically reprograms the SADMAn_SAR0, SADMAn_DAR0,
SADMAn_LLP0, and SADMAn_CTRL0 channel registers from the SADMAn_LLPx(0).
15. Source and destination request single and burst DMA transactions to transfer the block
of data (assuming non-memory peripheral). The SATA DMA acknowledges at the
completion of every transaction (burst and single) in the block and carries out the block
transfer.
Confidential
The destination status information is fetched from the location pointed to by the
DSTATARx register and stored in the DSTATx register if DMAH_CH0_CTL_WB_EN =
True, DMAH_CH0_STAT_DST = True and SADMAn_CFG0.DS_UPD_EN is enabled.
For conditions under which the destination status information is fetched from system
memory, refer to the Write Back column of Table 24.
17. If DMAH_CH0_CTL_WB_EN = True, then the SADMAn_CTRL0[63:32] register is
written out to system memory. For conditions under which the SADMAn_CTRL0[63:32]
register is written out to system memory, refer to the Write Back column of Table 24.
The SADMAn_CTRL0[63:32] register is written out to the same location on the same
layer (SADMAn_LLP0.LMS) where it was originally fetched; that is, the location of the
SADMAn_CTRL0 register of the linked list item fetched prior to the start of the block
transfer. Only the second word of the SADMAn_CTRL0 register is written out
SADMAn_CTRL0[63:32] because only the SADMAn_CTRL0.BLOCK_TS and
SADMAn_CTRL0.DONE fields have been updated by the SATA DMA hardware.
Additionally, the SADMAn_CTRL0.DONE bit is asserted to indicate block completion.
Therefore, software can poll the LLI.SADMAn_CTRL0.DONE bit of the
SADMAn_CTRL0 register in the LLI to ascertain when a block transfer has completed.
Note:
Do not poll the SADMAn_CTRL0.DONE bit in the SATA DMA memory map; instead, poll the
LLI.SADMAn_CTRL0.DONE bit in the LLI for that block. If the polled
LLI.SADMAn_CTRL0.DONE bit is asserted, then this block transfer has completed. This
LLI.SADMAn_CTRL0.DONE bit was cleared at the start of the transfer (Step 7).
18. The SSTATx register is now written out to system memory if
DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_SRC = True, and
SADMAn_CFG0.SS_UPD_EN is enabled. It is written to the SSTATx register location
of the LLI pointed to by the previously saved SADMAn_LLP0.LOC register.
The DSTATx register is now written out to system memory if
DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_DST = True, and
SADMAn_CFG0.DS_UPD_EN is enabled. It is written to the DSTATx register location
of the LLI pointed to by the previously saved LLPx.LOC register.
The end-of-block interrupt, int_block, is generated after the write-back of the control
and status registers has completed.
Note:
The write-back location for the control and status registers is the LLIpointed to by the
previous value of the LLPx.LOC register, not the LLI pointed to by the current value of the
LLPx.LOC register.
19. The SATA DMA does not wait for the block interrupt to be cleared, but continues
fetching the next LLI from the memory location pointed to by the current LLPx register
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16. Once the block of data is transferred, the source status information is fetched from the
location pointed to by the SSTATAR0 register and stored in the SSTATx register if
DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_SRC = True and
SADMAn_CFG0.SS_UPD_EN is enabled. For conditions under which the source
status information is fetched from system memory, refer to the Write Back column of
Table 24.
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and automatically reprograms the SAR0, DAR0, LLPx, and SADMAn_CTRL0 channel
registers. The DMA transfer continues until the SATA DMA determines that the
SADMAn_CTRL0 and LLPx registers at the end of a block transfer match the ones
described in Row 1 or Row 5 of Table 24 (as discussed earlier). The SATA DMA then
knows that the previously transferred block was the last block in the DMA transfer.
The DMA transfer might look like that shown in Figure 22.
If the user needs to execute a DMA transfer where the source and destination address are
contiguous, but where the amount of data to be transferred is greater than the maximum
block size SADMAn_CTRL0.BLOCK_TS, then this can be achieved using the type of multiblock transfer shown in Figure 23.
Figure 23. Multi-block with linked address for source and destination where SAR0
and DAR0 between successive blocks are contiguous
The DMA transfer flow is shown in Figure 24.
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Figure 22. Multi-block with linked address for source and destination
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Figure 24. DMA transfer flow for source and destination linked list address
Channel enabled
by software
LLI fetch
Hardware reprograms
SARx, DARx, CTRLx and LLPx
Source/destination status fetch
Write-back of control and

source/destination status to LLI
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Block-complete interrupt
generated here
Is DMA in
Row 1 or Row 5
of Table 40?
DMA transfer-complete
interrupt generated here
No
Yes
Channel disabled
by hardware
Multi-block transfer with source address auto-reloaded and destination

address auto-reloaded (row 4)
Note:
This type of multi-block transfer can only be enabled when either of the following parameters
is set:
DMAH_CH0_MULTI_BLK_TYPE = NO_HARDCODE
or
DMAH_CH0_MULTI_BLK_TYPE = RELOAD_RELOAD
1.
Read the Channel Enable register to choose an available (disabled) channel.
2.
CLEAR_SRC_TRAN, CLEAR_DST_TRAN, AND CLEAR_ERR. Reading the Interrupt
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DMA block transfer
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cleared.
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a)
Write the starting source address in the SADMAn_SAR0 register
b)
Write the starting destination address in the SADMAn_DAR0 register.
c)
Program SADMAn_CTRL0 and SADMAn_CFG0 according to Row 4, as shown in

page 137.
d)
Write the control information for the DMA transfer in the SADMAn_CTRL0 register.
For example, in the register, you can program the following:
i
ii
Transfer width for the source in the SRC_TR_WIDTH field;
Transfer width for the destination in the DST_TR_WIDTH field;
Destination master layer in the DMS field where the destination
resides.
Incrementing/decrementing or fixed address for the source in the
SINC field.
DINC field.
e)

Ensure that the reload bits, SADMAn_CFG0.RELOAD_SRC and
SADMAn_CFG0.RELOAD_DST, are enabled.
i
handle source/destination requests for the specific channel. Writing a 1
activates the software handshaking interface to handle source/destination
requests.
ii
destination peripheral, assign the handshaking interface to the source and
destination peripheral. This requires programming the SRC_PER and
4.
After the SATA DMA selected channel has been programmed, enable the channel by
writing a 1 to the ChEnReg.CH_EN bit. Ensure that bit 0 of the DmaCfgReg register is
enabled.
5.
Source and destination request single and burst SATA DMA transactions to transfer the
block of data (assuming non-memory peripherals). The SATA DMA acknowledges on
completion of each burst/single transaction and carries out the block transfer.
6.
When the block transfer has completed, the SATA DMA reloads the SAR0, DAR0, and
SADMAn_CTRL0 registers. Hardware sets the block-complete interrupt. The SATA
DMA then samples the row number, as shown in Table 24: Programming of transfer
types and channel register update method on page 137. If the SATA DMA is in Row 1,
then the DMA transfer has completed. Hardware sets the transfer complete interrupt
and disables the channel. You can either respond to the Block Complete or Transfer
8137791 RevA
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3.
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Complete interrupts, or poll for the transfer complete raw interrupt status register
(RawTfr[n], where n is the channel number) until it is set by hardware, to detect when
the transfer is complete. Note that if this polling is used, software must ensure that the
transfer complete interrupt is cleared by writing to the Interrupt Clear register,
ClearTfr[n], before the channel is enabled. If the SATA DMA is not in Row 1, the next
step is performed.
The DMA transfer proceeds as follows:
a)
If interrupts are enabled (SADMAn_CTRL0x.INT_EN = 1) and the block-complete

interrupt is un-masked (MaskBlock[x] = 1b1, where x is the channel number)
hardware sets the block-complete interrupt when the block transfer has
completed. It then stalls until the block-complete interrupt is cleared by software. If
the next block is to be the last block in the DMA transfer, then the block-complete
ISR (interrupt service routine) should clear the reload bits in the
SADMAn_CFG0.RELOAD_SRC and SADMAn_CFG0.RELOAD_DST registers.
This puts the SATA DMA into Row 1, as shown in Table 24. If the next block is not
the last block in the DMA transfer, then the reload bits should remain enabled to
keep the SATA DMA in Row 4.
b)
If interrupts are disabled (SADMAn_CTRL0.INT_EN = 0) or the block-complete

interrupt is masked (MaskBlock[x] = 1b0, where x is the channel number), then
hardware does not stall until it detects a write to the block-complete interrupt clear
register; instead, it immediately starts the next block transfer. In this case, software
must clear the reload bits in the SADMAn_CFG0.RELOAD_SRC and
SADMAn_CFG0.RELOAD_DST registers to put the SATA DMA into Row 1 of
Table 24 before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 25.
Figure 25. Multi-block DMA transfer with source and destination address autoreloaded
The DMA transfer is shown in Figure 26.
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7.
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Figure 26. DMA transfer flow for source and destination address auto-reloaded
Channel enabled
by software
Block transfer
Reload SARx, DARx and CTRLx
Yes
Is DMA in
Row 1 of
Table 40?
Channel disabled
by hardware
No
Confidential
CTRLx.INT_EN=1
&
MASKBLOCK[x]=1?
No
Yes
Stall until block interrupt
cleared by software
Note:
is set:
DMAH_CH0_MULTI_BLK_TYPE = 0
or
DMAH_CH0_MULTI_BLK_TYPE = RELOAD_LLP
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1.
Read the Channel Enable register to choose a free (disabled) channel.
2.
Set up the chain of linked list items (otherwise known as block descriptors) in memory.
Write the control information in the LLI.SADMAn_CTRL0 register location of the block
descriptor for each LLI in memory (see Figure 18: Multi-block transfer using linked lists
8137791 RevA
generated here
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3.
Note:
destination) and flow control peripheral by programming the TT_FC of the
b)

i
ii
iii Source master layer in the SMS field where the source resides.
iv Destination master layer in the DMS field where the destination resides.
v
field.
vi Incrementing/decrementing or fixed address for the destination in the
DINC field.
Write the starting source address in the SADMAn_SAR0 register.
The values in the LLI.SAR0 register locations of each of the linked list Items (LLIs) set up in
memory, although fetched during an LLI fetch, are not used.
4.
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a)

a)
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits. Writing a 0
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a 1 activates the software handshaking
interface source/destination requests.
b)

peripheral; this requires programming the SRC_PER and DEST_PER bits,
respectively.
5.
Make sure that the LLI.SADMAn_CTRL0 register locations of all LLIs in memory
(except the last) are set as shown in Row 7 of Table 24: Programming of transfer types
and channel register update method on page 137, while the LLI.SADMAn_CTRL0
register of the last linked list item must be set as described in Row 1 or Row 5.
Table 18: Multi-block transfer using linked lists when DMAH_CH0_STAT_SRC set to
true on page 135 shows a linked list example with two list items.
6.
Ensure that the LLI.LLPx register locations of all LLIs in memory (except the last) are
non-zero and point to the next linked list Item.
7.
Ensure that the LLI.DAR0 register location of all LLIs in memory point to the start
destination block address preceding that LLI fetch.
8.
If DMAH_CH0_CTL_WB_EN = True, ensure that the LLI.SADMAn_CTRL0.DONE

fields of the LLI.SADMAn_CTRL0 register locations of all LLIs in memory are cleared.
9.
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when DMAH_CH0_STAT_SRC set to true on page 135). For example, in the register
you can program the following:
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cleared.
on page 137.
11. Finally, enable the channel by writing a 1 to the CH_EN.CH_EN bit; the transfer is
performed. Ensure that bit 0 of the SADMAn_DMA_CFG register is enabled.
12. The SATA DMA fetches the first LLI from the location pointed to by LLPx(0).
The LLI.SAR0, LLI.DAR0, LLI. LLPx, and LLI.SADMAn_CTRL0 registers are fetched.
The LLI.SAR0 register although fetched is not used.
13. Source and destination request single and burst SATA DMA transactions to transfer the
block of data (assuming non-memory peripherals). The SATA DMA acknowledges at
the completion of every transaction (burst and single) in the block and carries out the
block transfer.
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location pointed to by the SSTATAR0 register and stored in the SSTATx register if
SADMAn_CFG0.SS_UPD_EN is enabled. For conditions under which the source
status information is fetched from system memory, refer to the Write Back column of
Table 24.
True, DMAH_CH0_STAT_DST = True, and SADMAn_CFG0.DS_UPD_EN is enabled.
For conditions under which the destination status information is fetched from system
memory, refer to the Write Back column of Table 24.
15. If DMAH_CH0_CTL_WB_EN = True, then the SADMAn_CTRL0[63:32] register is
written out to system memory. For conditions under which the SADMAn_CTRL0[63:32]
register is written out to system memory, refer to the Write Back column of Table 24.
The SADMAn_CTRL0[63:32] register is written out to the same location on the same
layer (SADMAn_LLP0.LMS) where it was originally fetched; that is, the location of the
SADMAn_CTRL0 register of the linked list item fetched prior to the start of the block
transfer. Only the second word of the SADMAn_CTRL0 register is written out
SADMAn_CTRL0[63:32] because only the SADMAn_CTRL0.BLOCK_TS and
SADMAn_CTRL0.DONE fields have been updated by hardware within the SATA DMA.
The LLI.SADMAn_CTRL0.DONE bit is asserted to indicate block completion.
Therefore, software can poll the LLI.SADMAn_CTRL0.DONE bit field of the
SADMAn_CTRL0 register in the LLI to ascertain when a block transfer has completed.
Note:
Do not poll the SADMAn_CTRL0.DONE bit in the SATA DMA memory map. Instead, poll the
SADMAn_CFG0.SS_UPD_EN is enabled. It is written to the SSTATx register location
of the LLI pointed to by the previously saved SADMAn_LLP0.LOC register.
DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_DST = True, and
SADMAn_CFG0.DS_UPD_EN is enabled. It is written to the DSTATx register location
of the LLI pointed to by the previously saved SADMAn_LLPx.LOC register.
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The write-back location for the control and status registers is the LLIpointed to by the
previous value of the SADMAn_LLP0.LOC register, not the LLI pointed to by the current
value of the SADMAn_LLP0.LOC register.
17. The SATA DMA reloads the SAR0 register from the initial value. Hardware sets the
block-complete interrupt. The SATA DMA samples the row number, as shown in
page 137. If the SATA DMA is in Row 1 or Row 5, then the DMA transfer has
completed. Hardware sets the transfer complete interrupt and disables the channel.
You can either respond to the Block Complete or Transfer Complete interrupts, or poll
for the transfer complete raw interrupt status register (RawTfr[n], n = channel number)
until it is set by hardware, to detect when the transfer is complete. Note that if this
polling is used, software must ensure that the transfer complete interrupt is cleared by
writing to the Interrupt Clear register, ClearTfr[n], before the channel is enabled. If the
SATA DMA is not in Row 1 or Row 5 as shown in Table 24, the following steps are
performed.
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18. The DMA transfer proceeds as follows:

a)
If interrupts are enabled (SADMAn_CTRL0.INT_EN = 1) and the block-complete

interrupt is unmasked (MaskBlock[x] = 1b1, where x is the channel number),
hardware sets the block-complete interrupt when the block transfer has
ISR (interrupt service routine) should clear the SADMAn_CFG0.RELOAD_SRC
source reload bit. This puts the SATA DMA into Row 1, as shown in Table 24 If the
next block is not the last block in the DMA transfer, then the source reload bit
should remain enabled to keep the SATA DMA in Row 7, as shown in
page 137.
b)
interrupts are disabled (SADMAn_CTRL0.INT_EN = 0) or the block-complete

interrupt is masked (MaskBlock[x] = 1b0, where x is the channel number), then
hardware does not stall until it detects a write to the block-complete interrupt clear
register; instead, it immediately starts the next block transfer. In this case, software
must clear the source reload bit, SADMAn_CFG0.RELOAD_SRC to put the
device into Row 1 of Table 24 before the last block of the DMA transfer has
completed.
19. The SATA DMA fetches the next LLI from memory location pointed to by the
SADMAn_LLP0 register and automatically reprograms the SADMAn_DAR0,
SADMAn_CTRL0, and SADMAn_LLP0 channel registers.
Note:
The SAR0 is not re-programmed, since the reloaded value is used for the next DMA block
transfer. If the next block is the last block of the DMA transfer, then the SADMAn_CTRL0
and SADMAn_LLP0 registers just fetched from the LLI should match Row 1 or Row 5 of
Table 24
The DMA transfer might look like that shown in Figure 27.
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Note:
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Figure 27. Multi-block DMA transfer with source address auto-reloaded and linked
list destination address
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Figure 28. DMA transfer flow for source address auto-reloaded and linked list
destination address
Channel enabled
by software
LLI fetch
Hardware reprograms
DARx, CTRLx and LLPx
DMA block transfer
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Reload SARx
generated here
Yes
Channel disabled
by hardware
Is DMA in
Row 1 or Row 5
of Table 40?
No
CTRLx.INT_EN=1
&
MASKBLOCK[x]=1?
No
Yes
cleared by software
Multi-block transfer with source address auto-reloaded and contiguous

destination address (row 3)
Note:
is set:
or
DMAH_CH0_MULTI_BLK_TYPE = RELOAD_CONT
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1.
2.
CLEAR_SRC_TRAN, CLEAR_DST_TRAN, AND CLEAR_ERR. Reading the Interrupt
cleared.
3.
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a)
Write the starting source address in the SADMAn_SAR0 register for channel
b)
Write the starting destination address in the SADMAn_DAR0 register.
c)
Program SADMAn_CTRL0 and SADMAn_CFG0 according to Row 3, shown in

Table 24.
d)
Write the control information for the DMA transfer in the SADMAn_CTRL0 register.
For example, in the register, you can program the following:
i
ii
Destination master layer in the DMS field where the destination
resides.
Incrementing/decrementing or fixed address for the source in the
SINC field.
DINC field.
e)

i
handle source/destination requests for the specific channel. Writing a 1
activates the software handshaking interface to handle source/destination
requests.
ii
destination peripheral, assign the handshaking interface to the source and
destination peripheral. This requires programming the SRC_PER and
4.
After the SATA DMA channel has been programmed, enable the channel by writing a 1
to the SATAn_DMA_CH_EN.CH_EN bit. Ensure that bit 0 of the SATAn_DMA_CFG
register is enabled.
5.
Source and destination request single and burst SATA DMA transactions to transfer the
block transfer.
6.
When the block transfer has completed, the SATA DMA reloads the SAR0 register; the
DAR0 register remains unchanged. Hardware sets the block-complete interrupt. The
SATA DMA then samples the row number, as shown in Table 24: Programming of
transfer types and channel register update method on page 137. If the SATA DMA is in
8137791 RevA
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Row 1, then the DMA transfer has completed. Hardware sets the transfer-complete
interrupt and disables the channel. You can either respond to the Block Complete or
Transfer Complete interrupts, or poll for the transfer complete raw interrupt status
register (RawTfr[n], n = channel number) until it is set by hardware, to detect when the
transfer is complete. Note that if this polling is used, software must ensure that the
transfer complete interrupt is cleared by writing to the Interrupt Clear register,
ClearTfr[n], before the channel is enabled. If the SATA DMA is not in Row 1, the next
step is performed.
The DMA transfer proceeds as follows:
a)
If interrupts are enabled (SATAn_DMA_CTRL0_LSB.INT_EN = 1) and the blockcomplete interrupt is un-masked (MaskBlock[x] = 1b1, where x is the channel
number), hardware sets the block-complete interrupt when the block transfer has
ISR (interrupt service routine) should clear the source reload bit,
SATAn_DMA_CFG0_LSB.RELOAD_SRC. This puts the SATA DMA into Row 1,
as shown in Table 24: Programming of transfer types and channel register update
method on page 137. If the next block is not the last block in the DMA transfer,
then the source reload bit should remain enabled to keep the SATA DMA in Row 4.
b)
If interrupts are disabled (SATAn_DMA_CTRL0_LSB.INT_EN = 0) or the blockcomplete interrupt is masked (MaskBlock[x] = 1b0, where x is the channel
number), then hardware does not stall until it detects a write to the block-complete
interrupt clear register; instead, it starts the next block transfer immediately. In this
case, software must clear the source reload bit,
SATAn_DMA_CFG0_LSB.RELOAD_SRC, to put the device into Row 1 of Table 24
before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 29.

Figure 29. Multi-block dma transfer with source address auto-reloaded and
contiguous destination address
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7.
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Figure 30. DMA transfer flow for source address auto-reloaded and contiguous
destination address
Channel enabled
by software
Block transfer
Reload SARx and CTRLx
Is DMA in
Row 1 of
Table 40?
Yes
Confidential
Channel disabled
by hardware
No
CTRLx.INT_EN=1
&
MASKBLOCK[x]=1?
No
Yes
cleared by software
Multi-block DMA transfer with linked list for source and contiguous
destination address (row 8)
Note:
is set:
or
DMAH_CH0_MULTI_BLK_TYPE = LLP_CONT
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1.
2.
Set up the linked list in memory. Write the control information in the LLI.
SADMAn_CTRL0 register location of the block descriptor for each LLI in memory (see
8137791 RevA
generated here
STi7105
3.
Note:
destination) and flow control device by programming the TT_FC of the
b)

i
ii
iii Source master layer in the SMS field where the source resides.
iv Destination master layer in the DMS field where the destination resides.
v
field.
vi Incrementing/decrementing or fixed address for the destination in the
DINC field.
Write the starting destination address in the SATAn_DMA_DAR0 register.
The values in the LLI.DAR0 register location of each linked list Item (LLI) in memory,
although fetched during an LLI fetch, are not used.
4.
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a)

a)
This step requires programming the HS_SEL_SRC/HS_SEL_DST bits. Writing a 0
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a 1 activates the software handshaking
interface to handle source/destination requests.
b)

peripherals. This requires programming the SRC_PER and DEST_PER bits,
respectively.
5.
Ensure that all LLI.SADMAn_CTRL0 register locations of the LLI (except the last) are
set as shown in Row 8 of Table 24: Programming of transfer types and channel register
update method on page 137, while the LLI.SADMAn_CTRL0 register of the last linked
list item must be set as described in Row 1 or Row 5 of Table 24. Figure 18: Multi-block
transfer using linked lists when DMAH_CH0_STAT_SRC set to true on page 135 shows
a linked list example with two list items.
6.
Ensure that the LLI.LLPx register locations of all LLIs in memory (except the last) are
non-zero and point to the next linked list Item.
7.
Ensure that the LLI.SAR0 register location of all LLIs in memory point to the start
source block address preceding that LLI fetch.
8.
If DMAH_CH0_CTL_WB_EN = True, ensure that the LLI.SADMAn_CTRL0.DONE

fields of the LLI.SADMAn_CTRL0 register locations of all LLIs in memory are cleared.
9.
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Figure 18: Multi-block transfer using linked lists when DMAH_CH0_STAT_SRC set to
true on page 135). For example, in the register, you can program the following:
STi7105
Raw Status and interrupt Status registers confirms that all interrupts have been
cleared.
on page 137.
11. Finally, enable the channel by writing a 1 to the SATAn_DMA_CH_EN.CH_EN bit; the
transfer is performed. Ensure that bit 0 of the SATAn_DMA_CFG register is enabled.
12. The SATA DMA fetches the first LLI from the location pointed to by SADMAn_LLP0(0).
Note:
The SADMAn_... LLI.SAR0, LLI.DAR0, LLI.LLPx, and LLI.SADMAn_CTRL0 registers are

fetched.
The DAR0 register in the SATA DMA remains unchanged.
13. Source and destination request single and burst SATA DMA transactions to transfer the
block transfer.
Confidential
location pointed to by the SSTATAR0 register and stored in the SADMAn_SSTAT0
register if DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_SRC = True and
SATAn_DMA_CFG0_MSB.SS_UPD_EN is enabled. For conditions under which the
source status information is fetched from system memory, refer to the Write Back
column of Table 24: Programming of transfer types and channel register update
method on page 137.
True, DMAH_CH0_STAT_DST = True and SATAn_DMA_CFG0_MSB.DS_UPD_EN is
enabled. For conditions under which the destination status information is fetched from
system memory, refer to the Write Back column of Table 24.
15. If DMAH_CH0_CTL_WB_EN = True then the SATAn_DMA_CTRL0_MSB register is
written out to system memory. For conditions under which the
SATAn_DMA_CTRL0_MSB register is written out to system memory, refer to the Write
Back column of Table 24.
The SATAn_DMA_CTRL0_MSB register is written out to the same location on the
same layer (SATAn_DMA_LLP0.LMS) where it was originally fetched; that is, the
location of the SADMAn_CTRL0 register of the linked list item fetched prior to the start
of the block transfer. Only the second word of the SADMAn_CTRL0 register is written
out, SATAn_DMA_CTRL0_MSB, because only the SADMAn_CTRL0.BLOCK_TS and
SADMAn_CTRL0.DONE fields have been updated by hardware within the SATA DMA.
Additionally, the SADMAn_CTRL0.DONE bit is asserted to indicate block completion.
Therefore, software can poll the LLI.SADMAn_CTRL0.DONE bit field of the
SATAn_DMA_CTRL0_MSB register in the LLI to ascertain when a block transfer has
completed.
Note:
Do not poll the SADMAn_CTRL0.DONE bit in the SATA DMA memory map. Instead, poll the
DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_SRC = True and
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The LLI.DAR0 register location of the LLI although fetched is not used.
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SATAn_DMA_CFG0_MSB.SS_UPD_EN is enabled. It is written to the SSTATx register
location of the LLI pointed to by the previously saved SATAn_DMA_LLP0.LOC register.
DMAH_CH0_CTL_WB_EN = True, DMAH_CH0_STAT_DST = True and
SATAn_DMA_CFG0_MSB.DS_UPD_EN is enabled. It is written to the DSTATx register
location of the LLI pointed to by the previously saved SATAn_DMA_LLP0.LOC register.
The write-back location for the control and status registers is the LLI pointed to by the
previous value of the LLPx.LOC register, not the LLI pointed to by the current value of the
LLPx.LOC register.
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17. The SATA DMA does not wait for the block interrupt to be cleared, but continues and
fetches the next LLI from the memory location pointed to by current LLPx register and
automatically reprograms the SADMAn_... SAR0, SADMAn_CTRL0, and LLP0
channel registers. The DAR0 register is left unchanged. The DMA transfer continues
until the SATA DMA samples that the SADMAn_CTRL0 and LLPx registers at the end
of a block transfer match. The SATA DMA then knows that the previously transferred
block was the last block in the DMA transfer.
The SATA DMA transfer might look like that shown in Figure 31. Note that the destination
address is decrementing.
Figure 31. Multi-block dma transfer with linked list source address and contiguous
destination address
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Note:
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Figure 32. DMA transfer flow for source address auto-reloaded and contiguous
destination address
Channel enabled
by software
LLI fetch
DMA block transfer
Confidential

generated here
Is DMA in
Row 1 or Row 5
of Table 40?
No
Yes
Channel disabled
by hardware
10.3
Disabling a channel prior to transfer completion

Under normal operation, software enables a channel by writing a 1 to the channel enable
register, SATAn_DMA_CH_EN.CH_EN, and hardware disables a channel on transfer
completion by clearing the SATAn_DMA_CH_EN.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the
CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration
Register (SATAn_DMA_CFG0_LSB).
1.
If software wishes to disable a channel prior to the DMA transfer completion, then it can
set the SATAn_DMA_CFG0_LSB.CH_SUSP bit to tell the SATA DMA to halt all
transfers from the source peripheral. Therefore, the channel FIFO receives no new
data.
2.
Software can now poll the SATAn_DMA_CFG0_LSB.FIFO_EMPTY bit until it indicates

that the channel FIFO is empty.
3.
The SATAn_DMA_CH_EN.CH_EN bit can then be cleared by software once the

channel FIFO is empty.
When SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH <

SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH and the SATAn_DMA_CFG0_LSB.CH_SUSP
bit is high, the SATAn_DMA_CFG0_LSB.FIFO_EMPTY is asserted once the contents of the
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Hardware reprograms
SARx, CTRLx and LLPx
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FIFO do not permit a single word of SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH to be
formed. However, there may still be data in the channel FIFO, but not enough to form a
single transfer of SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH. In this scenario, once the
channel is disabled, the remaining data in the channel FIFO is not transferred to the
destination peripheral.
Note:
If a channel is disabled by software, an active single or burst transaction is not guaranteed to

receive an acknowledgement.
10.3.1
Abnormal transfer termination

A SATA DMA transfer may be terminated abruptly in software by clearing the channel enable
bit, SATAn_DMA_CH_EN.CH_EN. The CH_EN bit is cleared over the AHB slave interface,
however you cannot assume that the channel is disabled immediately after the
SATAn_DMA_CH_EN. To confirm the channel is disabled, poll
SATAn_DMA_CH_EN.CH_EN and read back 0. If the channel is not disabled after a
channel disable request then either the source or destination has received a split or retry
response. The SATA DMA must keep re-attempting the transfer to the system HADDR that
originally received the split or retry response until an OKAY response is returned; to do
otherwise is a bus protocol violation.
Software may terminate all channels abruptly by clearing the global enable bit in the SATA
DMA Configuration Register (SATAn_DMA_CFG[0]). Again, you must not assume that all
channels are disabled immediately after the SATAn_DMA_CFG[0] is cleared over the AHB
slave interface. Congirm all channels are disabled by polling SATAn_DMA_CH_EN and
reading back 0.
Note:
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not
sent to the destination peripheral and is not present when the channel is re-enabled. For
read-sensitive source peripherals, such as a source FIFO, this data is therefore lost. When
the source is not a read-sensitive device (such as memory), disabling a channel without
waiting for the channel FIFO to empty may be acceptable, since the data is available from
the source peripheral upon request and is not lost.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to

receive an acknowledgement.
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It is permissible to remove the channel from the suspension state by writing a 0 to the
SATAn_DMA_CFG0_LSB.CH_SUSP register. The DMA transfer completes in the normal
manner.
Serial ATA (SATA) host registers
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11
Note:
There are three sets of registers to configure the DMA controller, the host controller and the
protocol converter.
Register addresses are provided as:
SATAnBaseAddress + offset
The SATAnBaseAddress is:
Note:
The areas not allocated are reserved and must not be accessed.
There are a few additional SATA registers described in the System configuration chapter.
Table 25.
SATA_DMA controller register summary.
Confidential
Address offset Register
Description
Page
Channel
0x400
SATAn_DMA_SAR0
Channel 0 source address
page 167
0x408
SATAn_DMA_DAR0
Channel 0 destination address
page 168
0x410
SATAn_DMA_LLP0
Channel 0 linked list pointer address
page 169
0x418
SATAn_DMA_CTRL0_LSB
Channel 0 control LSB
page 170
0x41C
SATAn_DMA_CTRL0_MSB
Channel 0 control MSB
page 173
0x420 - 0x43F
Reserved
0x440
SATAn_DMA_CFG0_LSB
Channel 0 configuration LSB
page 175
0x444
SATAn_DMA_CFG0_MSB
Channel 0 configuration MSB
page 177
0x448 - 0x6BF
Reserved
Interrupt
0x6C0
SATAn_DMA_RAW_TFR
Raw status for INTTFR interrupt
page 180
0x6C8
SATAn_DMA_RAW_BLOCK
Raw status for INTBLOCK interrupt
page 181
0x6D0
SATAn_DMA_RAW_SRC_TRAN
Raw status for INTSRCTRAN interrupt
page 181
0x6D8
SATAn_DMA_RAW_DST_TRAN
Raw status for INTDSTTRAN interrupt
page 182
0x6E0
SATAn_DMA_RAW_ERR
Raw status for INTERR interrupt
page 182
0x6E8
SATAn_DMA_TFR_STA
Status for INTTFR interrupt
page 183
0x6F0
SATAn_DMA_BLOCK_STA
Status for INTBLOCK interrupt
page 183
0x6F8
SATAn_DMA_SRC_TRAN_STA
Status for INTSRCTRAN interrupt
page 184
0x700
SATAn_DMA_DST_TRAN_STA
Status for INTDSTTRAN interrupt
page 184
0x708
SATAn_DMA_ERR_STA
Status for INTERR interrupt
page 185
0x710
SATAn_DMA_MASK_TFR
Mask for INTTFR interrupt
page 186
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8137791 RevA
SATABaseAddress - FD52 0000
STi7105
SATA_DMA controller register summary.
Description
Page
0x718
SATAn_DMA_MASK_BLK
Mask for INTBLOCK interrupt
page 186
0x720
SATAn_DMA_CLEAR_SRC_TRAN
Mask for INTSRCTRAN interrupt
page 189
0x728
SATAn_DMA_CLEAR_DST_TRAN
Mask for INTDSTTRAN interrupt
page 190
0x730
SATAn_DMA_MASK_ERR
Mask for INTERR interrupt
page 188
0x738
SATAn_DMA_CLEAR_TFR
Clear for INTTFR interrupt
page 188
0x740
SATAn_DMA_CLEAR_BLOCK
Clear for INTBLOCK interrupt
page 189
0x748
Clear for INTSRCTRAN interrupt
page 189
0x750
Clear for INTDSTTRAN interrupt
page 190
0x758
SATAn_DMA_CLEAR_ERR
Clear for INTERR interrupt
page 190
0x760
SATAn_DMA_STATUS_INT
Status for each interrupt type
page 190
0x798
SATAn_DMA_CFG
DMAC configuration
page 191
0x7A0
SATAn_DMA_CH_EN
DMAC channel enable
page 191
0x7A8
SATAn_DMA_ID
DMAC ID
page 192
0x7B0
SATAn_DMA_TEST
DMA test register
page 192
0x7F8
SATAn_DMA_COMP_TYPE
DMA component type number register
page 193
0x7FC
SATAn_DMA_COMP_VERSION
DMA component version register
page 193
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Miscellaneous
For more details on programming these registers, seeChapter 9: Serial ATA (SATA) host on
page 128, and the Synopsys documentation listed in Section 8.2: References on page 124.
Table 26.
SATA host controller register summary.
Description
Page
Shadow ATA/ATAPI: CDR - command block, CLR - control block

PIO mode: data
Read only for PIO read/receive operation,
write only for PIO write/transmit operation.
0x800
SATAn_CDR0
DMA mode: FIFO location

Read only for DMA read/receive
operation, write only for DMA
write/transmit operation.
page 194
Error
0x804
SATAn_CDR1
Feature (current value)
page 195
Feature expanded (previous value)

Sector count (current value)
0x808
SATAn_CDR2
page 195
Sector count expanded (previous value)
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Table 25.

Table 26.
STi7105
SATA host controller register summary.
Description
Page
Sector number (current value)

0x80C
SATAn_CDR3
page 196
Sector number expanded (previous value)
Cylinder low (current value)
0x810
SATAn_CDR4
page 196
Cylinder low expanded (previous value)
Cylinder high (current value)
0x814
SATAn_CDR5
page 197
Cylinder high expanded (previous value)
SATAn_CDR6
0x81C
SATAn_CDR7
Device/head
page 197
Status
page 198
Command
Alternative status
0x820
SATAn_CLR0
page 199
Device control
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SATA
0x824
SATAn_SCR0
SStatus
page 201
0x828
SATAn_SCR1
SError
page 202
0x82C
SATAn_SCR2
SControl
page 204
0x830
SATAn_SCR3
SActive
page 206
0x834
SATAn_SCR4
SNotification
page 207
0x864
SATAn_FPTAGR
First party DMA tag
page 207
0x868
SATAn_FPBOR
First party DMA buffer offset
page 208
0x86C
SATAn_FPTCR
First party DMA transfer count
page 208
0x870
SATAn_DMACR
DMA control
page 209
0x874
SATAn_DBTSR
DMA burst transaction size
page 210
0x878
SATAn_INTPR
Interrupt pending
page 211
0x87C
SATAn_INTMR
Interrupt mask
page 211
0x880
SATAn_ERRMR
Error mask
page 212
0x884
SATAn_LLCR
Link layer control
page 212
0x888
SATAn_PHYCR
PHY control
page 213
0x88C
SATAn_PHYSR
PHY status
page 213
0x8F8
SATAn_VERSIONR
SATA host version
page 214
0x8FC
SATAn_IDR
SATA host ID
page 214
SATA host
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8137791 RevA
0x818
STi7105
AHB to STBus protocol converter registers
Address offset
Register
Description
Page
0x0000
SATAn_AHB_OPC
STBus opcode configuration
page 214
0x0004
SATA_AHB_MSG_CFG
STBus message size configuration
page 215
0x0008
SATA_AHB_CHUNK_CFG
STBus chunk size configuration
page 215
0x000C
SATA_AHB_SW_RESET
Soft reset
page 216
0x0010
SATA_AHB_STATUS
page 216
0x0014
SATA_AHB_PC_GLUE_LOGIC
Protocol converter timeout
page 217
11.1
DMA controller
11.1.1
Channel
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SATAn_DMA_SAR0
Channel 0 source address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SAR
Address:
SATAnBaseAddress + 0x400
Type:
RW
Reset:
0x0000 0000
Description:
The starting bus source address is programmed by software before the DMA channel
is enabled, or by an LLI update before the start of the DMA transfer. While the DMA
transfer is in progress, this register is updated to reflect the source address of the
current bus transfer. If this is not already the case, hardware aligns this address to the
source transfer width, SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH field. Refer to
Hardware re-alignment of SAR/DAR registers on page 168.
For information on how the SAR0 is updated at the start of each SATA DMA block for
multi-block transfers.
[31:0] SAR: Current Source Address of DMA transfer

Updated after each source bus transfer. The SINC field in the SATAn_DMA_CTRL0_LSB
register determines whether the address increments, decrements, or is left unchanged on
every source bus transfer throughout the block transfer.
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Table 27.
STi7105
SATAn_DMA_DAR0
Channel 0 destination address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
0x0000 0000
Description:
The starting bus destination address is programmed by software before the DMA
channel is enabled, or by an LLI update before the start of the DMA transfer. While
the DMA transfer is in progress, this register is updated to reflect the destination
address of the current bus transfer. If this is not already the case, hardware aligns this
address to the destination transfer width,
SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH field. Refer to Hardware re-alignment of
SAR/DAR registers on page 168.
For information on how the DAR0 is updated at the start of each SATA DMA block for
multi-block transfers, refer to Section 10.2.1: Programming examples on page 142.
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[31:0] DAR: Current Destination address of DMA transfer

Updated after each destination bus transfer. The DINC field in the SATAn_DMA_CTRL0_LSB
register determines whether the address increments, decrements or is left unchanged on every
destination bus transfer throughout the block transfer.
Hardware re-alignment of SAR/DAR registers

Hardware aligns the value of the SATAn_DMA_SAR0 and SATAn_DMA_DAR0 registers in
the direction of the address control field SATAn_DMA_CTRL0.SINC and
SATAn_DMA_CTRL0.DINC when the current values of SAR0 and DAR0 are not aligned
to the programmed transfer width, SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH and
SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH.
The SATAn_DMA_SAR0 and SATAn_DMA_DAR0 registers are aligned upwards for an
incrementing address control and downwards for a decrementing address control.
If the SATAn_DMA_CTRL0_LSB.SINC and SATAn_DMA_CTRL0_LSB.DINC fields indicate
a fixed FIFO mode addressing scheme _CTRL0.SINC/_CTRL0.DINC = 2'b1x then the
_CTRL0.SINC[0] and _CTRL0.DINC[0] registers control the direction of the address
alignment if the current SAR0 and DAR0 addresses are not aligned to the transfer width.
SATA_CTRL0.SINC[1:0]/SATA_CTRL0.DINC[1:0] = 10 : Align SARx/DARx
upwards
SATA_CTRL0.SINC[1:0]/SATA_CTRL0.DINC[1:0] = 11 : Align SARx/DARx
downwards
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8137791 RevA
DAR
STi7105
SATAn_DMA_LLP0
Channel 0 linked list pointer address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LLP0
Address:
Type:
RW
Reset:
0x0000 0000
Description:
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[31:0] LLP0 :
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STi7105
Channel 0 control LSB
Type:
RW
Reset:
0x0030 4825
Description:
This register contains fields that control the DMA transfer.
INT_EN
The _CTRL0 register is part of the block descriptor (linked list item LLI) when block
chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer
when block chaining is enabled. For information about the behavior of this register
between blocks, refer to Section 10.1.1: Multi-block transfers on page 134.
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If status write-back is enabled, the upper word of the control register, _CTRL0[63:32],
is written to the control register location of the LLI in system memory at the end of the
block transfer.
Note: This register must be programmed before enabling the channel.
[31:29] RESERVED
[28] LLP_SRC_EN:
Block chaining is enabled on the source side only if the LLP_SRC_EN field is high and
LLP0.LOC is non-zero; for more information.
This field does not exist if the configuration parameter DMAH_CH0_MULTI_BLK_EN is not
selected or if DMAH_CH0_HC_LLP is selected. In this case the read-back value is always 0.
[27] LLP_DST_EN:
Block chaining is enabled on the destination side only if the LLP_DST_EN field is high and
LLP0.LOC is non-zero. For more information.
selected or if DMAH_CH0_HC_LLP is selected. In this case, the read-back value is always 0.
[26:25] SMS: Source master select
Identifies the Master Interface layer from which the source device (peripheral or memory) is
accessed.
00: AHB master 1
10: AHB master 3
01: AHB master 2
11: AHB master 4
The maximum value of this field that can be read back is DMAH_NUM_MASTER_INT 1. This
field does not exist if the configuration parameter DMAH_CH0_SMS is hardcoded; in this case,
the read-back value is always the hardcoded value.
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8137791 RevA
Address:
DST_TR_WIDTH
SRC_TR_WIDTH
SINC
DEST_MSIZE
SRC_MSIZE
SRC_GATHER_EN
DST_SCATTER_EN
RESERVED
TT_FC
DMS
SMS
LLP_DST_EN
LLP_SRC_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DINC
SATAn_DMA_CTRL0_LSB
STi7105
[22:20] TT_FC: Transfer type and flow control

The following transfer types are supported:
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Flow control can be assigned to the SATA DMA block, the source peripheral, or the destination
peripheral. Table 30: SATAn_DMA_CTRL0_LSB.TT_FC field decoding on page 174 lists the
decoding for this field. For more information on transfer types and flow control.
If the configuration parameter DMAH_CH0_FC is set to DMA_FC_ONLY, then TT_FC[2] does
not exist and TT_FC[2] always reads back 0. If DMAH_CH0_FC is set to SRC_FC_ONLY, then
TT_FC[2:1] does not exist and TT_FC[2:1] always reads back 2b10. If DMAH_CH0_FC is set
to DST_FC_ONLY, then TT_FC[2:1] does not exist and TT_FC[2:1] always reads back 2b11.
The reset value is configuration-dependent:
TT_FC[0] = 1b0
TT_FC[1] = DMAH_CH0_FC[1] and (!DMAH_CH0_FC[0])
TT_FC[2] = DMAH_CH0_FC[1] ^ DMAH_CH0_FC[0]
[19] RESERVED
[18] DST_SCATTER_EN: Destination scatter enable
0: Scatter disabled
1: Scatter enabled
Scatter on the destination side is applicable only when the SATA_CTRL0.DINC bit indicates an
incrementing or decrementing address control.
This field does not exist if DMAH_CH0_DST_SCA_EN is not selected; in this case, the readback value is always 0.
[17] SRC_GATHER_EN: Source gather enable
0: Gather disabled
1: Gather enabled
Gather on the source side is applicable only when the SATA_CTRL0.SINC bit indicates an
incrementing or decrementing address control.
This field does not exist if DMAH_CH0_SRC_GAT_EN is not selected; in this case, the readback value is always 0.
[16:14] SRC_MSIZE: Source burst transaction length
Number of data items, each of width SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH, to be read
from the source every time a source burst transaction request is made from either the
corresponding hardware or software handshaking interface. Table 28: SATAn_...
CTRL0.SRC_MSIZE, DEST_MSIZE decoding on page 174 lists the decoding for this field.
All remaining bits in this field do not exist and read back as 0.
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[24:23] DMS: Destination master select

Identifies the Master Interface layer where the destination device (peripheral or memory)
resides.
00: AHB master 1
10: AHB master 3
01: AHB master 2
11: AHB master 4
The maximum value of this field that can be read back is DMAH_NUM_MASTER_INT 1. This
field does not exist if the configuration parameter DMAH_CH0_DMS is hardcoded; in this case,
the read-back value is always the hardcoded value.
STi7105
[10:9] SINC: Source address Increment

Indicates whether to increment or decrement the source address on every source bus transfer.
If the device is fetching data from a source peripheral FIFO with a fixed address, then set this
field to No change.
00: Increment
1x = No change
01: Decrement
Note: Incrementing or decrementing is done for alignment to the next
SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH boundary.
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[8:7] DINC: Destination address increment

Indicates whether to increment or decrement the destination address on every destination bus
transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then
set this field to No change.
00: Increment
1x = No change
01: Decrement
Note: Incrementing or decrementing is done for alignment to the next
SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH boundary.
[6:4] SRC_TR_WIDTH: Source transfer width
Table 29: SATAn_... CTRL0.SRC_TR_WIDTH, CTRL0.DST_TR_WIDTH decoding on
page 174 lists the decoding for this field. Mapped to AHB bus hsize. For a nonmemory
peripheral, typically the peripheral (source) FIFO width.
This value must be less than or equal to DMAH_Mx_HDATA_WIDTH, where x is the bus layer 1
to 4 where the source resides.
This field does not exist if the parameter DMAH_CH0_STW is hardcoded. In this case, the
read-back value is always the hardcoded source transfer width, DMAH_CH0_STW.
[3:1] DST_TR_WIDTH: Destination transfer width
Table 29: SATAn_... CTRL0.SRC_TR_WIDTH, CTRL0.DST_TR_WIDTH decoding on
page 174 lists the decoding for this field. Mapped to AHB bus hsize. For a non-memory
peripheral, typically rgw peripheral (destination) FIFO width.
This value must be less than or equal to DMAH_Mk_HDATA_WIDTH, where k
is the bus layer 1 to 4 where the destination resides.
This field does not exist if DMAH_CH0_DTW is hardcoded. In this case, the read-back value is
always the hardcoded destination transfer width, DMAH_CH0_DTW.
[0] INT_EN: Interrupt enable
1: All interrupt-generating sources are enabled.
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8137791 RevA
[13:11] DEST_MSIZE: Destination burst transaction length

Number of data items, each of width SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH, to be
written to the destination every time a destination burst transaction request is made from either
the corresponding hardware or software handshaking interface. Table 28: SATAn_...
CTRL0.SRC_MSIZE, DEST_MSIZE decoding on page 174 lists the decoding for this field;
All surplus bits in this field do not exist and read back as 0.
STi7105
Channel 0 control MSB
DONE
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SATAnBaseAddress + 0x41C
Type:
RW
Reset:
0x0000 0002
BLOCK_TS
SATAn_DMA_CTRL0_MSB
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[31:13] RESERVED
[12] DONE:
If status write-back is enabled, the upper word of the control register, _CTRL0_MSB[31:0], is
written to the control register location of the Linked List Item (LLI) in system memory at the end
of the block transfer with the done bit set.
Software can poll the LLI _CTRL0.DONE bit to see when a block transfer is complete. The LLI
_CTRL0.DONE bit should be cleared when the linked lists are set up in memory prior to
enabling the channel.
For more information, refer to Section 10.1.1: Multi-block transfers on

page 134.
[11:0] BLOCK_TS: Block transfer size
b = log2(DMAH_CH0_MAX_BLK_SIZE + 1) + 31
[11:b] : RESERVED - Returns 0 on a read
[b:0] : BLOCK_TS
When the SATA DMA block is the flow controller, the user writes this field before the channel is
enabled in order to indicate the block size.
The number programmed into BLOCK_TS indicates the total number of single transactions to
perform for every block transfer; a single transaction is mapped to a single bus beat.
The width of the single transaction is determined by _CTRL0_LSB.SRC_TR_WIDTH. For
further information on setting this field, refer to Table 29: SATAn_... CTRL0.SRC_TR_WIDTH,
CTRL0.DST_TR_WIDTH decoding on page 174.
Once the transfer starts, the read-back value is the total number of data items already read
from the source peripheral, regardless of what is the flow controller. When the source or
destination peripheral
is assigned as the flow controller, then the maximum block size that can be read back saturates
at DMAH_CH0_MAX_BLK_SIZE, but the actual block size can be greater.
b = log2(DMAH_CH0_MAX_BLK_SIZE + 1) + 31
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Description:
SATAn_DMA_CTRL0_LSB.SRC_MSIZE /
SATAn_DMA_CTRL0_LSB.DEST_MSIZE
Number of data items to be transferred

(of width
SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH
or
SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH)
000
001
010
011
16
100
32
101
64
110
128
111
256
Table 29.
Confidential
SATAn_... CTRL0.SRC_MSIZE, DEST_MSIZE decoding
SATAn_... CTRL0.SRC_TR_WIDTH, CTRL0.DST_TR_WIDTH

decoding
SATAn_DMA_CTRL0_LSB.SRC_TR_WIDTH
Size (bits)
/SATAn_DMA_CTRL0_LSB.DST_TR_WIDTH
000
001
16
010
32
011
64
100
128
101
256
11x
256
Table 30.
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SATAn_DMA_CTRL0_LSB.TT_FC field decoding
SATA_CTRL0.TT_FC Field
Transfer type
Flow controller
000
Memory to memory
SATA DMA block
001
Memory to peripheral
SATA DMA block
010
Peripheral to memory
SATA DMA block
011
Peripheral to peripheral
SATA DMA block
100
Peripheral to memory
Peripheral
101
Source peripheral
110
Memory to peripheral
Peripheral
111
Destination peripheral
8137791 RevA
Table 28.
STi7105
STi7105
Address:
Type:
RW
Reset:
0x0000 0C00
Description:
This register contains fields that configure the DMA transfer. The channel
configuration register remains fixed for all blocks of a multi-block transfer.
Confidential
Note: This register must be programmed before enabling the channel.

[31] RELOAD_DST: Automatic destination reload
The DAR0 register can be automatically reloaded from its initial value at the end of every block
for multiblock transfers. A new block transfer is then initiated. Refer to Table 24: Programming
of transfer types and channel register update method on page 137 for conditions under which
this occurs.
This register does not exist if the configuration parameter DMAH_CH0_MULTI_BLK_EN is not
selected. In this case, the readback value is always zero.
[30] RELOAD_SRC: Automatic source reload
The SAR0 register can be automatically reloaded from its initial value at the end of every block
for multi-block transfers. A new block transfer is then initiated. Refer to Table 24: Programming
of transfer types and channel register update method on page 137 for conditions under which
this occurs.
selected. In this case, the readback value is always zero.
[29:20] MAX_ABRST: Maximum bus burst length
Maximum bus burst length that is used for DMA transfers on this channel.
A value of 0 indicates that software is not limiting the maximum bus burst length for DMA
transfers on this channel.
This field does not exist if the configuration parameter DMAH_MABRST is not selected. In this
case, the read-back value is always zero, and the maximum bus burst length cannot be limited
by software.
[19] SRC_HS_POL: Source handshaking interface polarity
0: Active high
1: Active low
[18] DST_HS_POL: Destination handshaking interface polarity
0: Active high
1: Active low
[17] LOCK_B: Bus lock
When active, the bus master signal hlock is asserted for the duration specified in
SATAn_DMA_CFG0_LSB.LOCK_B_L.
This field does not exist if the configuration parameter DMAH_CH0_LOCK_EN is set to False.
In this case, the read-back value is always zero.
8137791 RevA
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RESERVED
CH_PRIOR
HS_SEL_DST
HS_SEL_SRC
LOCK_CH_L
LOCK_B_L
LOCK_CH
LOCK_B
DST_HS_POL
SRC_HS_POL
MAX_ABRST
RELOAD_DST
RELOAD_SRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CH_SUSP
Channel 0 configuration LSB

FIFO_EMPTY
SATAn_DMA_CFG0_LSB
STi7105
[15:14] LOCK_B_L: Bus lock level

Indicates the duration over which SATAn_DMA_CFG0_LSB.LOCK_B bit applies.
00: Over complete DMA transfer
01: Over complete SATA DMA block transfer
1x = Over complete DMA transaction
This field does not exist if the parameter DMAH_CH0_LOCK_EN is set to False. In this case,
the read-back value is always zero.
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[13:12] LOCK_CH_L: Channel lock level

Indicates the duration over which SATAn_DMA_CFG0_LSB.LOCK_CH bit applies.
00: Over complete DMA transfer
01: Over complete SATA DMA block transfer
1x = Over complete DMA transaction
[11] HS_SEL_SRC: Source software or hardware handshaking
Select. This register selects which of the handshaking interfaces, hardware or software,
is active for source requests on this channel.
0: Hardware handshaking interface. Software-initiated transaction requests are ignored.
1: Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
[10] HS_SEL_DST: Destination software or hardware handshaking select
This register selects which of the handshaking interfaces, hardware or software, is active for
destination requests on this channel.
0: Hardware handshaking interface. Software-initiated transaction requests are ignored.
1: Software handshaking interface. Hardware Initiated transaction requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
[9] FIFO_EMPTY
Indicates if there is data left in the channel's FIFO. Can be used in conjunction with
SATAn_DMA_CFG0_LSB.CH_SUSP to cleanly disable a channel. For more information, refer
to Section 10.3: Disabling a channel prior to transfer completion on page 162.
0: Channel's FIFO not empty
1: Channel's FIFO empty
[8] CH_SUSP: Channel suspend
Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee
that the current transaction will complete. Can also be used in conjunction with
SATAn_DMA_CFG0_LSB.FIFO_EMPTY to cleanly disable a channel without losing any data.
0: Not Suspended
1: Suspend. Suspend DMA transfer from the source.
For more information, refer to Section 10.3: Disabling a channel prior to transfer completion on
page 162
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8137791 RevA
[16] LOCK_CH: Channel lock

When the channel is granted control of the master bus interface and if the
SATAn_DMA_CFG0_LSB.LOCK_CH bit is asserted, then no other channels are granted
control of the master bus interface for the duration specified in
SATAn_DMA_CFG0_LSB.LOCK_CH_L. Indicates to the master bus interface arbiter that this
channel wants exclusive access to the master bus interface for the duration specified in
SATAn_DMA_CFG0_LSB.LOCK_CH_L.
STi7105
[7:5] CH_PRIOR: Channel priority

A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within
the range: 0 to (DMAH_NUM_CHANNELS 1)
A programmed value outside this range will cause erroneous behavior.
[4:0] RESERVED
Type:
R/W
0
FCMODE
FIFO_MODE
PROT_CTRL
Confidential
Buffer:
Reset:
0x0000 0004
Applicability:
UNRESTRICTED
Description:
[31:15] RESERVED
[14:11] DEST_PER
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of
channel 0 if the SATAn_DMA_CFG0_LSB.HS_SEL_DST field is 0. Otherwise, this field is
ignored. The channel can then communicate with the destination peripheral connected to that
interface via the assigned hardware handshaking interface.
Note: For correct DMA operation, only one peripheral (source or destination) should be
assigned to the same handshaking interface.
[10:7] SRC_PER
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of
channel 0 if the SATAn_DMA_CFG0_LSB.HS_SEL_SRC field is 0. Otherwise, this field is
ignored. The channel can then communicate with the source peripheral connected to that
interface via the assigned hardware handshaking interface.
Note: For correct SATA DMA block operation, only one peripheral (source or destination)
should be assigned to the same handshaking interface.
[6] SS_UPD_EN: Source status update enable
Source status information is only fetched from the location pointed to by the SSTATAR0
register, stored in the SSTAT0 register and written out to the SSTAT0 location of the LLI (refer to
Figure 32: Mapping of block descriptor (LLI) in memory to channel registers when
DMAH_CHx_STAT_SRC is set to true on page 204) if SS_UPD_EN is high.
Note: This enable is only applicable if DMAH_CH0_STAT_SRC is set to True.
This field does not exist if the configuration parameter DMAH_CH0_STAT_SRC is set to False.
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Address:
SS_UPD_EN
DEST_PER
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DS_UPD_EN
Channel 0 configuration MSB

SRC_PER
SATAn_DMA_CFG0_MSB
STi7105
[4:2] PROT_CTRL: Protection control

The default value of HPROT indicates a non-cached, nonbuffered, privileged data access. The
reset value is used to indicate such an access.
HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches.
There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface
signals. Table 31: PROT_CTRL field to HPROT mapping on page 178 shows the mapping of
bits in this field to the HPROT[3:1] bus.
Confidential
[1] FIFO_MODE: FIFO mode select

Determines how much space or data needs to be available in the FIFO before a burst
transaction request is serviced.
0: Space/data available for single bus transfer of the specified transfer width.
1: Space/data available is greater than or equal to half the FIFO depth for destination transfers
and less than half the FIFO depth for source transfers. The exceptions are at the end of a burst
transaction request or at the end of a block transfer.
[0] FCMODE: Flow control mode
Determines when source transaction requests are serviced when the Destination Peripheral is
the flow controller.
0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled.
1: Source transaction requests are not serviced until a destination transaction request occurs.
In this mode the amount of data transferred from the source is limited such that it is guaranteed
to be transferred to the destination prior to block termination by the destination. Data prefetching is disabled.
Table 31.
178/454
PROT_CTRL field to HPROT mapping
PROT_CTRL
HPROT
HPROT[0]
SATAn_DMA_CFG0_MSB.PROT_CTRL[1]
HPROT[1]
HPROT[2]
HPROT[3]
8137791 RevA
[5] DS_UPD_EN: Destination status update enable

Destination status information is only fetched from the location pointed to by the DSTATAR0
register, stored in the DSTAT0 register and written out to the DSTAT0 location of the LLI (refer
to Figure 32: Mapping of block descriptor (LLI) in memory to channel registers when
DMAH_CHx_STAT_SRC is set to true on page 204) if DS_UPD_EN is high.
This field does not exist if the configuration parameter DMAH_CH0_STAT_DST is set to False.
STi7105
11.1.2
Interrupts
The following sections describe the registers pertaining to interrupts, their status, and how to
clear them. For each channel, there are five types of interrupt sources:
INT_TFR: DMA transfer complete interrupt

This interrupt is generated on DMA transfer completion to the destination peripheral.
INT_BLOCK: Block transfer complete interrupt

This interrupt is generated on SATA DMA block transfer completion to the destination
peripheral.
INT_SRC_TRAN: Source transaction complete interrupt
This interrupt is generated after completion of the last bus transfer of the requested
single/burst transaction from the handshaking interface (either the hardware or
software handshaking interface) on the source side
Note:
If the source for a channel is memory, then that channel will never generate a IntSrcTran
interrupt and hence the corresponding bit in this field will not be set.
Confidential
INT_DST_TRAN: Destination transaction complete interrupt

This interrupt is generated after completion of the last bus transfer of the requested
single/burst transaction from the handshaking interface (either the hardware or
software handshaking interface) on the destination side
Note:
If the destination for a channel is memory, then that channel will never generate the
IntDstTran interrupt and hence the corresponding bit in this field will not be set.
INT_ERR: Error interrupt

This interrupt is generated when an ERROR response is received from an AHB slave
on the HRESP bus during a DMA transfer. In addition, the DMA transfer is cancelled
and the channel is disabled.
There are several groups of interrupt-related registers:
RAW_TFR, RAW_BLOCK, RAW_SRC_TRAN, RAW_DST_TRAN, RAW_ERR
STATUS_TFR, STATUS_BLOCK, STATUS_SRC_TRAN, STATUS_DST_TRAN,

STATUS_ERR
MASK_TFR, MASK_BLOCK, MASK_SRC_TRAN, MASK_DST_TRAN, MASK_ERR
CLEAR_TFR, CLEAR_BLOCK, CLEAR_SRC_TRAN, CLEAR_DST_TRAN,

CLEAR_ERR
STATUS_INT
When a channel has been enabled to generate interrupts, the following is true:
Interrupt events are stored in the raw status registers.
The contents of the raw status registers are masked with the contents of the mask
registers.
The masked interrupts are stored in the status registers.
The contents of the status registers are used to drive the INT_* port signals.
Writing to the appropriate bit in the clear registers clears an interrupt in the raw status
registers and the status registers on the same clock cycle.
The contents of each of the five status registers is ORed to produce a single bit for each
interrupt type in the Combined Status Register: STATUS_INT.
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Note:
STi7105
The SATAn_DMA_CTRL0_LSB.INT_EN bit must be set for the enabled channel to generate
any interrupts.
RAW_TFR, RAW_BLOCK, RAW_SRC_TRAN, RAW_DST_TRAN, RAW_ERR

Interrupt events are stored in these raw interrupt status registers before masking:
RAW_TFR, RAW_BLOCK, RAW_SRC_TRAN, RAW_DST_TRAN,
RAW_ERR.
Raw status for INTTFR interrupt
Confidential
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SATAnBaseAddress + 0x6C0
Type:
R/W
Reset:
0x0000 0000
Description:
[31:1] RESERVED
[0] RAW: Raw interrupt status
Raw transfer complete
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8137791 RevA
0
RAW
SATAn_DMA_RAW_TFR
Each bit in these registers is cleared by writing a 1 to the corresponding location in

the CLEAR_TFR, CLEAR_BLOCK, CLEAR_SRC_TRAN,
CLEAR_DST_TRAN, CLEAR_ERR registers.
STi7105
SATAn_DMA_RAW_BLOCK
Raw status for INTBLOCK interrupt

9
Address:
SATAnBaseAddress + 0x6C8
Type:
R/W
Reset:
0x0000 0000
0
RAW
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
Raw status for INTSRCTRAN interrupt
Address:
SATAnBaseAddress + 0x6D0
Type:
R/W
0
RAW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Confidential
SATAn_DMA_RAW_SRC_TRAN
Buffer:
Reset:
0x0000 0000
Description:
[31:1] RESERVED
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Description:
STi7105
SATAn_DMA_RAW_DST_TRAN
Raw status for INTDSTTRAN interrupt

9
Address:
SATAnBaseAddress + 0x6D8
Type:
R/W
Reset:
0x0000 0000
0
RAW
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
Raw status for INTERR interrupt

9
Address:
SATAnBaseAddress + 0x6E0
Type:
R/W
Reset:
0x0000 0000
0
RAW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Confidential
SATAn_DMA_RAW_ERR
Description:
[31:1] RESERVED
STATUS_TFR, STATUS_BLOCK, STATUS_SRC_TRAN, STATUS_DST_TRAN,

STATUS_ERR
All interrupt events from all channels are stored in these interrupt status registers after
masking: STATUS_TFR, STATUS_BLOCK, STATUS_SRC_TRAN,
STATUS_DST_TRAN, and STATUS_ERR.The contents of these register are
used to generate the interrupt signals leaving the SATA DMA block.
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8137791 RevA
Description:
STi7105
SATAn_DMA_TFR_STA
Status for INTTFR interrupt

9
Address:
SATAnBaseAddress + 0x6E8
Type:
Reset:
0x0000 0000
0
STATUS
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
[0] STATUS: Interrupt status
Status for INTBLOCK interrupt

RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SATAnBaseAddress + 0x6F0
Type:
Reset:
0x0000 0000
0
STATUS
SATAn_DMA_BLOCK_STA
Description:
[31:1] RESERVED
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Description:
STi7105
SATAn_DMA_SRC_TRAN_STA
Status for INTSRCTRAN interrupt

9
Address:
Type:
Reset:
0x0000 0000
0
STATUS
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
Status for INTDSTTRAN interrupt

RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0000 0000
Description:
[31:1] RESERVED
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8137791 RevA
0
STATUS
SATAn_DMA_DST_TRAN_STA
Description:
STi7105
SATAn_DMA_ERR_STA
Status for INTERR interrupt

9
Address:
Type:
Reset:
0x0000 0000
0
STATUS
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
Confidential
MASK_TFR, MASK_BLOCK, MASK_SRC_TRAN, MASK_DST_TRAN,

MASK_ERR
The contents of the raw status registers are masked with the contents of the mask
registers: MASK_TFR, MASK_BLOCK, MASK_SRC_TRAN,
MASK_DST_TRAN, MASK_ERR.
A channels INT_MASK bit will only be written if the corresponding mask write enable
bit in the INT_MASK_WE field is asserted on the same bus write transfer. This allows
software to set a mask bit without performing a read-modified write operation.
For example, writing hex 01x1 to the MASK_TFR register writes a 1 into
MASK_TFR[0], while MASK_TFR[7:1] remains unchanged. Writing 0x00xx leaves
MASK_TFR[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus
allowing the SATA DMA block to set the appropriate bit in the status registers and
INT_* port signals.
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Description:
STi7105
Mask for INTTFR interrupt

8
Type:
RW
Reset:
0x0000 0000
RESERVED
RESERVED
Address:
Description:
[31:9] RESERVED
[8] INT_MASK_WE: Interrupt mask write enable (W)
0: Write disabled
1: Write enabled
[0] INT_MASK: Interrupt mask (R/W)

0: Masked
Mask for INTBLOCK interrupt

8
Address:
Type:
RW
Buffer:
Reset:
0x0000 0000
Description:
[31:9] RESERVED
0: Write disabled
1: Write enabled
[7:1] RESERVED
0: Masked
186/454
8137791 RevA
1: Unmasked
0
INT_MASK
INT_MASK_WE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SATAn_DMA_MASK_BLK
1: Unmasked
RESERVED
Confidential
[7:1] RESERVED
INT_MASK_WE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_MASK
SATAn_DMA_MASK_TFR
STi7105
Mask for INTSRCTRAN interrupt

8
Type:
RW
Reset:
0x0000 0000
RESERVED
RESERVED
Address:
Description:
[31:9] RESERVED
0: Write disabled
1: Write enabled

0: Masked
Mask for INTDSTTRAN interrupt

8
Address:
Type:
RW
Reset:
0x0000 0000
0
INT_MASK
INT_MASK_WE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SATAn_DMA_DST_TRAN
1: Unmasked
RESERVED
Confidential
[7:1] RESERVED
Description:
[31:9] RESERVED
0: Write disabled
1: Write enabled
[7:1] RESERVED
0: Masked
8137791 RevA
1: Unmasked
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INT_MASK_WE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_MASK
SATAn_DMA_SRC_TRAN
STi7105
Mask for INTERR interrupt

8
Type:
RW
Reset:
0x0000 0000
RESERVED
RESERVED
Address:
Description:
[31:9] RESERVED
0: Write disabled
1: Write enabled

0: Masked
1: Unmasked
CLEAR_TFR, CLEAR_BLOCK, CLEAR_SRC_TRAN, CLEAR_DST_TRAN,

CLEAR_ERR
Each bit in the raw status and status registers is cleared on the same cycle by writing
a 1 to the corresponding location in the clear registers: CLEAR_TFR,
CLEAR_BLOCK, CLEAR_SRC_TRAN, CLEAR_DST_TRAN, CLEAR_ERR.
Writing a 0 has no effect. These registers are not readable.
SATAn_DMA_CLEAR_TFR
Clear for INTTFR interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0000 0000
Description:
[31:1] RESERVED
[0] CLEAR: Interrupt clear.
0: No effect
188/454
1: Clear interrupt
8137791 RevA
0
CLEAR
RESERVED
Confidential
[7:1] RESERVED
INT_MASK_WE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
INT_MASK
SATAn_DMA_MASK_ERR
STi7105
SATAn_DMA_CLEAR_BLOCK
Clear for INTBLOCK interrupt

9
Address:
Type:
Reset:
0x0000 0000
0
CLEAR
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
0: No effect
1: Clear interrupt
Clear for INTSRCTRAN interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0000 0000
0
CLEAR
RESERVED
Confidential
Description:
[31:1] RESERVED
0: No effect
1: Clear interrupt
8137791 RevA
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Description:
STi7105
Clear for INTDSTTRAN interrupt

9
Address:
Type:
Reset:
0x0000 0000
0
CLEAR
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[31:1] RESERVED
0: No effect
1: Clear interrupt
Clear for INTERR interrupt

9
Address:
Type:
Reset:
0x0000 0000
0
CLEAR
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Description:
[31:1] RESERVED
0: No effect
1: Clear interrupt
TFR
ERR
BLOCK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DSTT
Status for each interrupt type
SRCT
SATAn_DMA_STATUS_INT
RESERVED
Confidential
SATAn_DMA_CLEAR_ERR
Address:
Type:
Reset:
0x0000 0000
Description:
The contents of each of the five Status Registers (STATUS_TFR, STATUS_BLOCK,

STATUS_SRC_TRAN, STATUS_DST_TRAN, STATUS_ERR) are ORed to produce
a single bit per interrupt type in the combined status register (STATUS_INT).
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8137791 RevA
Description:
STi7105
[31:5] RESERVED
[4] ERR: OR of the contents of STATUS_ERR register
[3] DSTT: OR of the contents of STATUS_DST register
[2] SRCT: OR of the contents of STATUS_SRC_TRAN register
[1] BLOCK: OR of the contents of STATUS_BLOCK register
[0] TFR: OR of the contents of STATUS_TFR register
Miscellaneous
SATAn_DMA_CFG
DMAC configuration
9
DMA_EN
Address:
Type:
RW
Reset:
0x0000 0000
Description:
Used to enable the SATA DMA block, which must be done before any channel activity
can begin.
[31:1] RESERVED
[0] DMA_EN: SATA DMA block enable
0: SATA DMA block disabled
1: SATA DMA block enabled
DMAC channel enable

8
0
CH_EN
CH_EN_WE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SATAn_DMA_CH_EN
RESERVED
Confidential
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SATAnBaseAddress + 0x7A0
Type:
RW
Reset:
0x0000 0000
Description:
If software needs to set up a new channel, then it can read this register in order to find
out which channels are currently inactive; it can then enable an inactive channel with
the required priority.
8137791 RevA
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11.1.3
STi7105
[31:9] RESERVED
[8] CH_EN_WE: Channel enable write enable
[7:1] RESERVED
Confidential
All bits of this register are cleared to 0 when the global SATA DMA block channel
enable bit, DMA_CFG_REG[0], is 0. When the global channel enable bit is 0, then a
write to the CH_EN_REG register is ignored and a read will always read back 0.
The channel enable bit, SATAn_DMA_CH_EN.CH_EN, is written only if the
corresponding channel write enable bit, SATAN_DMA_CH_EN.CH_EN_WE, is
asserted on the same bus write transfer. For example, writing hex 01x1 writes a 1 into
CH_EN_REG[0], while CH_EN_REG[7:1] remains unchanged. Writing 0x00xx leaves
CH_EN_REG[7:0] unchanged. Note that a read-modified write is not required.
For information on software disabling a channel by writing 0 to
SATAn_DMA_CH_EN.CH_EN, refer to Section 10.3: Disabling a channel prior to
transfer completion on page 162.
SATAn_DMA_ID
DMA ID register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMA_ID
Address:
SATAnBaseAddress + 0x07A8
Type:
Reset:
0x0000 202A
Description:
[31:0] DMA_ID: DMAC ID register which is a read-only register that specifies the component ID
SATAn_DMA_TEST
DMA test register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMA_TEST
Address:
SATAnBaseAddress + 0x07B0
Type:
R/W
Reset:
0x0000 0000
Description:
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8137791 RevA
[0] CH_EN: Enables/disables the channel

Setting this bit enables a channel, clearing this bit disables the channel.
0: Disable the Channel
1: Enable the Channel
The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the
last bus transfer of the DMA transfer to the destination has completed. Software can therefore
poll this bit to determine when this channel is free for a new DMA transfer.
STi7105
SATAn_DMA_COMP_TYPE
DMA component type number register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SATA_COMP_TYPE
Address:
Type:
Reset:
0x4457 1110
[31:0] SATA_COMP_TYPE: DMAC component type register

which is a read-only register that specifies the component type. Designware component type
number = 0x44_57_11_10. This assigned unique hex value is constant and is derived from the
two ASCII letters DW followed by a 32-bit unsigned number.
SATAn_DMA_COMP_VERSION
DMA component version register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
SATA_COMP_VERSION
Address:
SATAnBaseAddress + 0x7FC
Type:
Reset:
0x3231 302A
Description:
[31:0] SATA_COMP_VERSION : This is the DMAC component version register
specifies the version of the packaged component, for example version 2.02a is given as
0x3230 322A
8137791 RevA
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Description:
11.2
11.2.1
Shadow ATA/ATAPI
STi7105
SATAn_CDR0
PIO data/DMA location
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DMA
DMA_LOC
RESERVED
PIO_DATA
Address:
Type:
RW
Reset:
Undefined
Description:
Used to transfer data from host-to-device and from device-tohost in PIO or DMA
modes. Read-only during read/receive operation, and write-only during write/transmit
operation.
DMA:
Confidential
[31:0]DMA_LOC:
This location can only be accessed by the host software or DMA controller when the SATA host
is in the corresponding DMA mode:
- read (when the Data FIS is being received) or
- write (when the DMA Activate or DMA Setup FIS is received),
and the corresponding DMA handshake signal is asserted (dma_req or dma_single).
Both single and burst 32-bit or 16-bit bus transfers are supported in this mode.
NOTE: the same transfer size (either 16 or 32 bits) should be maintained during the whole DMA
transfer.
PIO:
[31:16]RESERVED
[15:0]PIO_DATA:
This register can only be accessed by the host software when the SATA host is in the
corresponding PIO mode:
- read, when the PIO Setup FIS with D=1 is followed by the Data FIS, or
- write, when the PIO Setup FIS with D=0 is received.
During PIO read, the software performs a series of reads from this location, during PIO write - a
series of writes to this location.
Only single 16-bit bus transfers are supported in this mode.
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8137791 RevA
PIO
STi7105
SATAn_CDR1
Error/feature
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Address:
Type:
RW
Reset:
0xFF (error), 0x00 (feature)
Description:
This location is used as one of the following:
error register when read;
feature/ feature expanded registers when written. Implemented as two-byte

FIFO.
Confidential
[31:8] RESERVED
[7:0] ERROR_FEATURE_FEATURE_EXP :
ERROR
Error/diagnostic information from the device.
FEATURE
Current value of the Feature register. Determines the specific function of the SET FEATURES
commands.
FEATURE_EXP: Feature expanded
Previous value of the Feature register (used for 48-bit addressing). It is pushed from the
Feature register every time CDR1 is written.
SATAn_CDR2
Sector count
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SEC_CNT/SEC_CNT_EXP
Address:
Type:
RW
Reset:
0xFF
Description:
These two 8-bit registers contain the number of sectors for read/write AT/ATAPI
commands or command-specific parameters on some non-read/write commands.
Implemented as two-byte FIFO.
[31:8] RESERVED
[7:0] SEC_CNT/SEC_CNT_EXP:
SEC_CNT:
Current value of the CDR2 register when written. Can be read when Device Control register
HOB bit is cleared (SATAn_CLR0.HOB=0).
SEC_CNT_EXP:
Previous value of the CDR2 register (used for 48-bit addressing) pushed from the SEC_CNT
register every time CDR2 is written. This value can be read when Device Control register HOB
bit is set (SATAn_CLR0.HOB=1).
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ERROR_FEATURE_
FEATURE_EXP
STi7105
SATAn_CDR3
Sector number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SEC_NUM/SEC_NUM_EXP
Address:
Type:
RW
Reset:
0xFF
Description:
These two 8-bit registers contain starting sector number (CHS mode) or LBA low
value (LBA mode bits [7:0], [31:24]). Implemented as two-byte FIFO.
[7:0] SEC_NUM:
Current value of the CDR3 when written. Can be read when SATAn_CLR0.HOB=0. Contains
LBA [7:0] bits.
Confidential
SEC_NUM_EXP:
Previous value of the CDR3 pushed from the Secnum every time CDR3 is written. Can be read
when SATAn_CLR0.HOB=1. Contains LBA [31:24] bits. Used for 48-bit addressing.
SATAn_CDR4
Cylinder low
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CYLLOW_EXP/CYLLOW
Address:
Type:
RW
Reset:
0xFF
Description:
These two 8-bit registers contain cylinder number low byte (CHS mode) or LBA mid
value (LBA mode bits [15:8], [39:32]). Implemented as two-byte FIFO.
[31:8] RESERVED
[7:0] CYLLOW:
LBA [15:8] bits.
CYLLOW_EXP:
Previous value of the CDR4 pushed from the Cyllow every time CDR4 is written. Can be read
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8137791 RevA
[31:8] RESERVED
STi7105
SATAn_CDR5
Cylinder high
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CYLHIGH/CYLHIGH_EXP
Address:
Type:
RW
Reset:
0xFF
Description:
These two 8-bit registers contain the cylinder-number high byte (CHS mode) or the
LBA high value (LBA mode bits [23:16], [47:40]). Implemented as two-byte FIFO.
[7:0] CYLHIGH:
LBA [23:16] bits.
4
DEV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LBA
Device/head
RESERVED
SATAn_CDR6
RESERVED
Confidential
CYLHIGH_EXP:
Previous value of the CDR5 pushed from the Cylhigh every time CDR5 is written. Can be read
HEAD
Address:
Type:
RW
Reset:
0xEF
Description:
This read/write 8-bit register selects the device and contains command-dependent
information.
[31:7] RESERVED
[6] LBA: Logical Block Addressing:
0: CHS Mode
1: LBA Mode
[5] RESERVED
8137791 RevA
197/454
[31:8] RESERVED
STi7105
[4] DEV: Device select

0: Device 0 (Master)
1: Device 1 (Slave)
This bit should always be cleared (Dev=0) since SATA host implements Master-only emulation.
If this bit is set, any access to Command or Control register is ignored.
NOTE: this bit is not updated when Register FIS is received from the device, i.e. device can not
change the state of this bit.
This bit is cleared by one of the following conditions:
power-up;
SControl[0]=1 (COMRESET);
device signals COMINIT;
SRST bit set in the Device Control register;
EXECUTE DEVICE DIAGNOSTIC command written to the Command register.
[3:0] HEAD: Head number or other command-dependent information.
4
SERV
0
ERR
RESERVED
DRQ
COMMAND STATUS
DWF
RESERVED
RESERVED
Read
Write
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DRDY
Status/command
BSY
SATAn_CDR7
Address:
Type:
RW
Reset:
0x7F(a) (status)/0x00 (command)
Description:
Command register when written,
Status register when read.
[31:8] RESERVED
[7:0] COMMAND: (write)
Contains command code for device to execute. A write to this register sets the BSY bit in the
Status register (BSY=1). This register is written last to initiate command execution.
Command Register FIS is sent to the device every time this register is written and both BSY
and DRQ bits of the Status register are cleared.
[7:0] STATUS: (read)
Status is a read-only 8-bit register and can be written only by the device with either the
Register or the Set Device Bits FIS. Read access to the Status register clears the IPF, which
negates the ATA interrupt request signal (intrq) to the system bus. Reset occurs on power-on.
a. Set to 0x7F on power-up, then 0x80 when device presence is detected via PHY READY condition.
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8137791 RevA
[7] BSY: Busy

Indicates the device is busy when set. All other Command Block registers are invalid. When
BSY and DRQ bits are cleared by the device, the host software can access any of the
Command Block registers. This bit is cleared on power-on and set in the following cases:
- Device presence is detected via PHY READY
- signal assertion;
- SControl[0]=1 (COMRESET condition);
-Device signals COMINIT;
-A new command is written to the Command
-register when BSY=0;
-DEVICE RESET command is written to the
-Command register;
-SRST bit is set in the Device Control register.
[6] DRDY: Device ready
Device is ready when high and is able to execute a command.
Stays high once set unless catastrophic error.
[4] SERV: Service

Used in overlap and queued commands (command dependent in AT/ATAPI-4).
[3] DRQ: Data Request
Asserted when device is ready to transfer data.
[2:1] RESERVED
[0] ERR: Error when high (ERROR register contains further information).
Address:
Type:
RW
Reset:
0x7F(b) (alt status)/0x00 (device control)
Description:
device control register when written,
alternative status register when read.
NIEN
HOB
SRST
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Alternative status/device control

RESERVED
SATAn_CLR0
RESERVED
Confidential
[5] DWF: Drive write fault (command dependent in AT/ATAPI-4)
Contains the same value as the Status register (CDR7), except the IPF is not cleared
when the CLR0 is read.
b. Set to 0x7F on power-up, then 0x80 when device presence is detected via PHY READY condition.
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STi7105
STi7105
[31:8] RESERVED
[7] HOB
Used to read expanded registers (CDR2 - CDR5) when set. For example:
0: CDR2 Seccnt register is read.
1: CDR2 Seccnt_exp register is read
[6:3] RESERVED
[1] NIEN: Interrupt enable

0: Enable (intrq is asserted if IPF=1);
1: Disable (intrq is negated).
Confidential
[0] RESERVED
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8137791 RevA
[2] SRST: Soft reset

0: Device is not reset
1: Device is reset
Control register FIS is transmitted to the device every time the state of this bit is changed.
STi7105
SATA
SATAn_SCR0
SStatus
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
IPM
SPD
DET
Address:
Type:
Reset:
0x0000 0000
Description:
Contains the current state of the interface and host adapter. Updated continuously
and asynchronously by the host adapter. Writes to this register result in bus error
response. Resets on power-on.
Confidential
[31:12] RESERVED
[11:8] IPM: Current interface owner management state
0000: Device not present or communication not established
0001: Interface in active state
0010: Interface in PARTIAL power management state
0110: Interface in SLUMBER power management state
All other values: Reserved.
[7:4] SPD: Negotiated interface communication speed established
0000: No negotiated speed (device not present or communication not established)
0001: Generation 1 communication rate negotiated
0010: Generation 2 communication rate negotiated
All other values: Reserved.
[3:0] DET: Interface device detection and Phy state
0000: No device detected and PHY communication is not established
0001: Device presence detected but PHY communication not established (PHY COMWAKE
signal is detected).
0011: Device presence detected and PHY communication established (PHY READY signal is
detected).
0100: Phy in offline mode as a result of the interface being disabled.
8137791 RevA
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11.2.2
Type:
RW
Reset:
0x0000 0000
Description:
This register contains supplemental SATA interface error information to complement

the error information available in the Shadow Error register. The register represents
all the detected errors accumulated since the last time the SError register was
cleared. See Transport Layer chapter for more details. The set bits in the SError
register indicate that the corresponding error condition became true one or more
times since the last time this bit was cleared. The set bits in the SError register are
explicitly cleared by a write operation to the register, or a reset operation (power-on or
COMRESET). The value written to clear the set error bits should have ones encoded
in the bit positions corresponding to the bits that are to be cleared.
Confidential
Address:
[31:28] RESERVED
[27] DIAG_A: Port Selector Presence detected
This bit is set when the Phy PORTSELECT signal is detected.
[26] DIAG_X: Exchanged error
This bit is set when the Phy COMINIT signal is detected.
[25] DIAG_F: Unrecognized FIS type
This bit is set when the Transport Layer receives a FIS with good CRC, but unrecognized FIS
type.
[24] DIAG_T: Transport state transition error
This bit is set when the Transport Layer detects one of the following conditions:
Wrong sequence of received FISes,
PIO count mismatch between the PIO Setup FIS and the following Data FIS,
Odd PIO/DMA byte count or DMA buffer offset,
Wrong non-data FIS length (Received Data FIS length is not checked),
RxFIFO overrun as a result of the 20 dword latency violation by the device.
[23] DIAG_S: Link sequence (illegal transition) error
This bit is set when the Link Layer detects an erroneous Link state machine transition.
[22] DIAG_H: Handshake error
This bit is set when the Link Layer receives one or more R_ERRp handshake responses form
the device after frame transmission.
[21] DIAG_C: CRC error
This bit is set when the Link Layer detects CRC error in the received frame.
[20] DIAG_D: Disparity error
This bit is set when the Link Layer detects incorrect disparity in the received data or primitives.
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8137791 RevA
RESERVED
ERR_P
ERR_E
RESERVED
DIAG_N
DIAG_I
DIAG_W
DIAG_B
DIAG_D
DIAG_C
DIAG_S
DIAG_H
DIAG_T
DIAG_F
DIAG_X
DIAG_A
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERR_I
SError
ERR_M
SATAn_SCR1
ERR_T
STi7105
ERR_C
STi7105
[19] DIAG_B: 10b to 8b decoder error

This bit is set when the Link Layer detects 10b to 8b decoder error in the received data or
primitives.
[18] DIAG_W: Comm Wake
This bit is set when Phy COMWAKE signal is detected.
[17] DIAG_I: Phy internal error
This bit is set when Phy internal error condition is detected.
[16] DIAG_N: PhyRdy change
This bit is set when Phy READY signal state is changed.
[11] ERR_E: Internal host adapter error

This bit is set when ERROR response is generated on the AHB bus, or DMA_FINISH_TX is
asserted, but no data had been written during DMA write operation.
Confidential
[10] ERR_P: Protocol error

This bit is set when any of the following error conditions is detected: Transport state transition
error (DIAG_T), Unrecognized FIS type (DIAG_F), or Link sequence error (DIAG_S).
[9] ERR_C: Non-recovered persistent communication or data integrity error
This bit is set when PHY READY signal is negated (Phy Not Ready condition) due to the loss of
communication with the device or problems with interface, but not after the transition from
active to PARTIAL or SLUMBER power management state.
[8] ERR_T: Non-recovered transient data integrity error
This bit is set if any of the 10b to 8b decoder error (DIAG_B), CRC error (DIAG_C), Disparity
error (DIAG_D), Handshake error (DIAG_H), or Transport transition error (DIAG_T) is detected
in the Data FIS, or non-data FIS transmission was not recovered after 3 retries.
[7:2] RESERVED
[1] ERR_M: Recovered communication error
This bit is set when PHY READY condition is detected after interface initialization, but not after
transition from PARTIAL or SLUMBER power management state to active state.
[0] ERR_I: Recovered data integrity error
This bit is set when nondata FIS transmission was unsuccessful (i.e. DIAG_H error was
detected), but was recovered after 1 to 3 retries.
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[15:12] RESERVED
STi7105
SATAn_SCR2
SControl
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PMP
Address:
Type:
RW
SPM
IPM
SPD
DET
Reset:
0x0000 0000
Applicability:
UNRESTRICTED
Description:
Provides control for the SATA interface. Write operations to the SControl register
result in an action being taken by the host adapter or interface. Read operations from
the register return the last value written to it.
[31:20] RESERVED
[19:16] PMP: Port Multiplier Port
Represents the 4-bit value that will be placed in the PM Port field of all transmitted FISes.
Confidential
[15:12] SPM: Select power management

Selects a power management state. A non-zero value written to this field will cause the power
management state specified to be initiated. A value written to this field is treated as a one-shot.
It is read as 0000.
0000 - No power management state transition requested.
0001 - Transition to PARTIAL power management state initiated.
0010 - Transition to SLUMBER power management state initiated.
0100 - Transition to the active power management state initiated.
All other values reserved.
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8137791 RevA
Buffer:
STi7105
Confidential
[7:4] SPD:
This field represents the highest-allowed communication speed that the interface is allowed to
negotiate when the speed is established:
0000 - No speed negotiation restrictions
0001 - Limit speed negotiation to a rate not greater than Generation 1 communication rate
0010 - Limit speed negotiation to a rate not greater than Generation 2 communication rate
[3:0] DET:
This field controls the host adapter device detection and interface initialization:
0000 - No device detection or initialization action requested
0001 - Perform interface communication initialization sequence to establish communication.
This is functionally equivalent to a hard reset and results in the interface being reset and
communication reinitialized (COMRESET condition). Upon a write to the SControl register that
sets DET to 0001, the host interface shall transition to a HP1:HR_Reset state and shall remain
in that state until DET field bit 0 is cleared by a subsequent write to the SControl register.
0100 - Disable SATA interface and put Phy in offline mode.
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[11:8] IPM:
This field represents the enabled interface power management states that can be invoked with
the SATA interface power management capabilities:
0000 - No interface power management state restrictions
0001 - Transitions to the PARTIAL state disabled
0010 - Transitions to the SLUMBER state disabled
0011 - Transitions to both the PARTIAL and SLUMBER states disabled
STi7105
SATAn_SCR3
SActive
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SCR3
Address:
Type:
RW
Reset:
0x0000 0000
Confidential
[31:0] SCR3 :
Used for native SATA command queuing; contains the information returned in the SActive field
of the set device bits FIS.
The host software can set bits in the SActive register by a write operation to this register. The
value written to the set bits should have ones encoded in the bit positions corresponding to the
bits that are to be set. Bits in the SActive register can not be cleared as a result of a register
write operation by the host, and host software cannot clear bits in the SActive register.
Set bits in the SActive register are cleared as a result of data returned by the device in the
SActive field of the Set Device Bits FIS. The value returned in this field will have ones encoded
in the bit positions corresponding to the bits that are to be cleared. The device cannot set bits in
this register.
All bits in the SActive register are cleared upon issuing a hard reset (COMRESET) signal or as
a result of issuing a software reset by setting SRST bit of the Device Control register.
For the native command queuing protocol, the SActive value represents the set of outstanding
queued commands that have not completed successfully yet. The value is bit-significant and
each bit position represents the status of a pending queued command with a corresponding
TAG value.
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8137791 RevA
Description:
STi7105
SATAn_SCR4
SNotification
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NOTIFY
Address:
Type:
R/W
Reset:
0x0000 0000
Description:
Used to notify host software which devices have sent a set device bits FIS with
notification bit set. When a set device bits FIS with notification bit set to 1 is received,
the bit corresponding to the value of the PM port field in the FIS is set, and an
interrupt is generated if the I bit in the FIS is set and interrupt is enabled.
Set bits in the SNotification register are explicitly cleared by a write operation to the
SNotification register, or a power-on reset. The register is not cleared due to a
COMRESET condition. The value written to clear set bits should have ones encoded
in the bit positions corresponding to the bits that are to be cleared.
Confidential
[31:16] RESERVED
[15:0] NOTIFY:
This field represents whether a particular device with the corresponding PM Port number has
sent a Set Device Bits FIS to the host with the Notification bit set.
11.2.3
SATA host
SATAn_FPTAGR
First party DMA tag
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
TAG
Address:
Type:
Reset:
0x0000 0000
Description:
Contains the command 5-bit TAG value, which is updated every time a new DMA
Setup FIS is received. The DMA controller uses this value to identify the buffer region
in the host system memory selected for the data transfer. Write access to this location
results in the bus error response.
[31:5] RESERVED
[4:0] TAG: First-party DMA TAG value
Updated every time a new DMA Setup FIS is received from the device.
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RESERVED
STi7105
SATAn_FPBOR
First party DMA buffer offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FPBOR
Address:
Type:
Reset:
0x0000 0000
[31:0] FPBOR :
Contains the DMA buffer offset value, which is updated every time a new DMA Setup FIS is
received. The device uses the offset to transfer DMA data out of order. Bits 1 and 0 should
always be cleared (32-bit-aligned offset). A write access to this location results in the bus error
response.
SATAn_FPTCR
First party DMA transfer count
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
FPTCR
Address:
Type:
Reset:
0x0000 0000
Description:
[31:0] FPTCR :
Contains the number of bytes that will be transferred. It is updated every time a new DMA
Setup FIS is received. Bit 0 should always be cleared (even number of bytes). A write access to
this location results in the bus error response.
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8137791 RevA
Description:
STi7105
Address:
Type:
RW
Reset:
0x0000 0000
Description:
Status of the DMA transmit or receive channel. Application software must set either of
these bits prior to issuing a corresponding DMA command to the device. Power-on or
COMRESET condition clears this register.
[31:2] RESERVED
Confidential
[1] RXCHEN:
0: DMA receive channel is disabled
1: DMA receive channel is enabled and ready for transfer
[0] TXCHEN:
0: DMA transmit channel is disabled
1: DMA transmit channel is enabled and ready for transfer
8137791 RevA
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RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXCHEN
DMA control
RXCHEN
SATAn_DMACR
STi7105
DMA burst tranaction size
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
MRD
RESERVED
MWR
Address:
Type:
RW
Reset:
0x0014 0010
Description:
Used to set RxFIFO pop almost empty and TxFIFO push almost full thresholds to
the burst transaction size (in dwords) for a DMA read or write operation. The SATA
host generates corresponding request signals (DMA_REQ_RX or DMA_REQ_TX) to
the DMA controller as follows:
DMA_REQ_RX is asserted when RxFIFO contains enough data for the burst
transaction of MRD size;
DMA_REQ_TX is asserted when TxFIFO contains enough free space for the
burst transaction of MWR size.
Power-up or COMRESET condition initializes this register to the value shown below.
Confidential
The MRD/ MWR field can only be written if the corresponding RXCHEN/ TXCHEN bit
of the DMACR register is cleared.
Note: The DMA burst transaction size must never exceed these values, otherwise an
ERROR response is generated by the slave interface if either the RxFIFO empty or
the TxFIFO full condition is detected during a DMA bus transfer. Host software must
ensure that the DMA controller is programmed with the same values prior to enabling
a channel for transfer.
Note: For 16-bit DMA transfers, MRD and MWR values should be adjusted by dividing the
burst size (number of beats in the burst) by 2 and rounding up if the value is odd. For
example, if the read burst size is 7 words, then the MRD value should be 4.
[31:22] RESERVED
[21:16] MRD:
This field is used to set the RxFIFO pop almost empty flag to the maximum burst size in
dwords for the DMA read operation. Can be written if DMACR.RXCHEN=0, otherwise, the write
to this field is ignored.
Valid range: 1 to (RXFIFO_DEPTHraf-1)
Note: MRD=0 might result in a bus error response during DMA read transaction. Upper
boundary is derived from the fact that the device will stop sending data when the host
generates HOLDp raf dwords from the RxFIFO full condition. This might result in possible lock
condition (dma_req_rx is never generated) if this value is exceeded.
Defaults to 8 dwords on reset (32-23-1=8).
[15:5] RESERVED
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8137791 RevA
SATAn_DBTSR
STi7105
[4:0] MWR:
This field is used to set the TxFIFO push almost full flag to the maximum burst size in dwords
for the DMA write operation. Can be written if DMACR.TXCHEN=0, otherwise, the write to this
field is ignored.
Valid range: 1 to (TXFIFO_DEPTH1)
Note: MWR=0 might result in bus error response during DMA write transaction. Upper
boundary is determined by the TxFIFO address width.
Defaults to 16 dwords on reset (32/2=16).
Address:
Type:
RW
Reset:
0x0000 0000
Description:
Contains all SATA host interrupt events before masking. The bits are set by an
interrupt event. All the interrupt bits together with the IPF ATA interrupt flag are ORed
to generate the SATA host intrq output. The set bits in the INTPR register can be
cleared by a write operation to the register, or a reset operation (power-on or
COMRESET). The value written to clear set bits should have ones encoded in the bit
positions corresponding to the bits that are to be cleared.
[31:4] RESERVED
[3] ERR:
Set when any of the bits in the SError register is set and the corresponding bit in the ERRMR
register is set.
[2] PMABORT:
Set when the link layer detects a power mode abort condition (power mode is aborted by the
device requesting a frame transmission).
Note: this bit must be cleared explicitly by software before issuing a power management
request to the interface.
[1] NEWFP:
Set when a DMA Setup FIS is received from the device without errors.
[0] DMAT:
Set when DMATp is received from the device during Data FIS transmission.
Address:
0
DMATM
NEWFPM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERRM
Interrupt mask
PMABORTM
SATAn_INTMR
RESERVED
Confidential
8137791 RevA
211/454
DMAT
NEWFP
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERR
Interrupt pending
PMABORT
SATAn_INTPR
STi7105
Type:
RW
Reset:
0x0000 0000
Description:
Used to mask or enable corresponding interrupt events in the INTPR register. An

interrupt event is masked if the bit is cleared and is enabled if set. If any of the INTPR
bits are set or if IPF is set and enabled (unmasked), the INTRQ output is asserted. A
COMRESET condition clears this register.
1: ERR interrupt is enabled
[2] PMABORTM:
0: PMABORT interrupt is masked
1: PMABORT interrupt is enabled
[1] NEWFPM:
0: NEWFP interrupt is masked
1: NEWFP interrupt is enabled
[0] DMATM:
0: DMAT interrupt is masked
1: DMAT interrupt is enabled
SATAn_ERRMR
Error mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ERRMR
Address:
Type:
RW
Reset:
0x0000 0000
Description:
[31:0] ERRMR:
Used to mask or enable corresponding bits of the SError register prior to setting the ERR bit of
the INTPR. This allows driver software to select the SError bits that can cause the interrupt
output intrq to be asserted. The INTPR ERR bit is set if any of the SError bits are set and the
corresponding ERRMR bit is set. Clearing the ERRMR bit would mask the corresponding
SError bit from setting the INTRP ERR bit. COMRESET condition clears this register.
Address:
Type:
RW
Reset:
0x0000 0007
Description:
Provides Link Layer (LL) control capability for the host software. Power-on or
COMRESET condition sets these bits.
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8137791 RevA
0
SCRAM
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DESCRAM
Link layer control
RPD
SATAn_LLCR
[3] ERRM:
0: ERR interrupt is masked
RESERVED
Confidential
[31:4] RESERVED
STi7105
[31:3] RESERVED
[2] RPD:
0: Repeat primitive drop function disabled
1: Repeat primitive drop function enabled
[1] DESCRAM:
0: Descrambler disabled
1: Descrambler enabled
[0] SCRAM:
0: Scrambler disabled
1: Scrambler enabled
PHY control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
PHYCR
Address:
Type:
RW
Reset:
0x1901 00C3
Description:
[31:0] PHYCR :
Bits of this register are connected to the corresponding bits of the phy_control output port. The
width is set by the PHY_CTRL_W parameter (valid range: 0 to 32). The remaining bits are
reserved: reads return zeros, writes have no effect. If the width is set to zero, then this location
is reserved
Note: This location supports only 16 or 32-bit transfer sizes for write accesses; 8- bit write
accesses are ignored.
SATAn_PHYSR
PHY status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PHYSR
Address:
Type:
Reset:
0x0000 0000
Description:
[31:0] PHYSR :
Used to monitor Phy status. The bits of this register reflect the state of the
corresponding bits of the phy_status input port. The width is set by the PHY_STAT_W
parameter (valid range: 0 to 32). The remaining bits are reserved: reads return zeros,
writes have no effect. If the width is set to zero, then this location is reserved.
8137791 RevA
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SATAn_PHYCR
STi7105
SATAn_VERSIONR
SATA host version
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VERSIONR
Address:
Type:
Reset:
0x3138 332A(c)
[31:0] VERSIONR :
Contains the hard-coded SATA host component version value set by the
HSATA_VERSION_NUM parameter. The value represents an ASCII code of the version
number. For example, version 1.00* is coded as 0x3130 302A. Writing to this register results in
a bus error response.
SATAn_IDR
SATA host ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
SATAnBaseAddress + 0x8FC
Type:
Reset:
0x100A 020A(c)
[31:0] IDR :
Contains the hard-coded SATA host identification value set by the HSATA_ID_NUM parameter.
Writing to this register results in a bus error response.
AHB to STBus protocol converter registers

Address:
Type:
RW
Reset:
Description:
[31:5] RESERVED
[4] WRITE_EN:
Enable write posting
c.
Fixed value which must not be changed.
214/454
8137791 RevA
1
OPCODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
SATAn_AHB_OPC
WRITE_EN
11.3
RESERVED
Confidential
IDR
Description:
STi7105
[3] RESERVED
[2:0] OPCODE:
000: Store4/Load4
010: Store16/Load16
100: Store64/Load64
others: Store4/Load4
001: Store8/Load8
011: Store32/Load32
101: Store128/Load128
SATA_AHB_MSG_CFG
Message size
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MSG_SIZE
Address:
Type:
RW
Reset:
Description:
The message length in number of packets is programmed in this register.
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[31:4] RESERVED
[3:0] MSG_SIZE:
0000: Disable chunk
0001: 2 packet
0011: 8 packet
0101: 32 packet
0111: 128 packet
0010: 4 packet
0100: 16 packet
0110: 64 packet
Others: Disable chunk
SATA_AHB_CHUNK_CFG
Chunk size
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
CH_SIZE
Address:
AHBBaseAddress+ 0x0008
Type:
R/W
Reset:
Description:
The chunk size in number of packets is programmed in this register.
[31:4] RESERVED
[3:0] CH_SIZE:
0000 = Disable chunk
0001 = 2 packet
0011 = 8 packet
0101 = 32 packet
0111 = 128 packet
0010 = 4 packet
0100 = 16 packet
0110 = 64 packet
Others = Disable chunk
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RESERVED
STi7105
SATA_AHB_SW_RESET
Software reset
9
Address:
Type:
RW
Reset:
Description:
This register implements the software reset for the protocol converter.
[31:1] RESERVED
SATA_AHB_STATUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
Description:
This register indicates the state of the protocol converter. It can be used by the
software to ensure that configuration registers are written only when STBus idle.
[31:1] RESERVED
[0] STATUS:
Indicates the state of the protocol converter
0: busy
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8137791 RevA
0
STATUS
RESERVED
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[0] SOFT_RESET:
1 has to be written into bit 0 of this register to enable the software reset. The bit has to be reset
to 0 to disable the softreset. When softreset is active the state machines are initialized to the
reset state on rising system clock edge.
1: idle
RESERVED
SOFT_RESET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STi7105
SATA_AHB_PC_GLUE_LOGIC
Protocol converter timeout

RESERVED
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
TIMEOUT_COUNT
TIMEOUT_EN
BLOCK_EN
Address:
Type:
R/W
Reset:
0xFFFF FFFF FFFD 00FF
Description:
This register holds the time-out value in number of AHB IDLEs.
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RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
[63:18] RESERVED
[17] BLOCK_EN:
0: disable the termination of AHB burst after transferring an amount of data equal to
BLOCK_TS (default).
1: enable the termination of AHB burst after transferring an amount of data equal to
BLOCK_TS.
[16] TIMEOUT_EN:
1: enabled
0: disabled
[15:0] TIMEOUT_COUNT:
Holds timeout value for number of IDLEs
Default = 255 consecutive IDLEs on the AHB interface.
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Ethernet subsystem
12
STi7105
Ethernet subsystem
12.1
Introduction
PHY layer technologies that can be connected to GMAC controllers include 802.11 WLAN,
HomePlug AV, MOCA and standard ethernet 802.3.
Note:
SYS_CFG7 must be configured appropriately before using the Ethernet GMAC subsystem,
to enable ethernet functionalities and clock schemes.
12.1.1
PHY connections
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The ethernet controller supports a direct interface with STE100P/STE101P and similar
PHYs via MII or RMII. The STi7105 has on chip clock generation for GMAC and external
Ethernet PHY in MII/RMII modes. It can also be clocked from external PHY/Home network
devices in RMII mode.
The controller can be used to interface, through an overclocked MII interface (up to 300
Mbit/s), to an external non-ethernet Phy, such as a Moca PHY.
There is also support for the GMII interface supporting a 1000Mbps transfer rate using an
external 125Mhz clock. The STi7105 can be configured to output a GTX_CLK, which is a
delayed version of the incoming RX_CLK aligned with the TXD signals. This can be used by
the companion chip to capture the TX signals synchronously.
The STi7105 also supports also the REV MII feature that allows to connect to Ethernet MAC
without using a physical layer device, used for on-pcb backplane connection cost reduction.
Only MII type interface is supported at 100Mbps in REV MII mode.
12.1.2
Interface support
Each GMAC supports the the interface standards and interface frequencies detailed in Table
32.
Table 32.
STi7105 ethernet MAC interface standards
Interface
Frequencies
No. Pins
RMII
50MHz
MII(1)
25MHz, 75MHz
19
RevMII
25MHz, 75MHz
19
GMII
125MHz
27
1. Overclocked MII at 300Mbit/s essential for Moca support
PHY clock support is selectable between an internal clock and external input. The external
clock input may not be multiples of 25MHz, but will provide a total bit rate of up to 300Mbit/s.
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8137791 RevA
The STi7105 integrates a gigabit ethernet MAC controller (GMAC) to support delivery of IP
based A/Vstreams in IP-TV applications.
STi7105
12.2
Ethernet subsystem
Ethernet subsystem features(a)

The following is a list of features supported by the Synopsys GMAC.
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12.2.1
10 / 100 / 1000-Mbps data transfer rates with the following PHY interfaces:
IEEE 802.3-compliant GMII / MII(default) interface to communicatenwith an

external Gigabit / Fast Ethernet PHY
SGMII interface
Full-duplex and half-duplex operation:
CSMA/CD Protocol for half-duplex operation
Packet bursting and frame extension in 1000 MBps half-duplex operation
IEEE 802.3x flow control for full-duplex operation
Optional fowarding of received pause control frames in full-duplex operation
Back pressure support for half-duplex operation
Automatic transmission of zero-quanta pause frame on deassertion of flow control

input in full-diplex operaiton
Preamble and SFD insertion in Transmit and deletion in Receive paths
Automatic CRC and pad generation controllable on a per-frame basis
Options for Automatic Pad/CRC Stripping on receive frames
Programmable frame length to support Standard or Jumbo Ethernet frames with sizes
up to 16kB
Programmable InterFrameGap (40-96 bit times in steps of 8)
A variety of flexible address filtering modes:
Up to 31 additional 48-bit perfect (DA) address filters with masks for each byte
Up to 31 48-bit SA address comparison check with masks for each byte
64-bit hash filter (optional) for multicast and uni-cast (DA) addresses
Option to pass all multicast address frames
Promiscuous mode support to pass all frames without any filtering for network
monitoring
Passes all incoming packets (as per filter) with a status report
Separate 32-bit status returned for transmission and reception packets
Supports 32/64/128-bit data transfer on the system-side
Complete network statistics (optional) for PHY device configuration and management
Optional module for detection of LAN wake-up frames and AMD Magic Packet Frames
Optional Receive module for checksum off-load for received IPv4 and TCP packets
encapsulated by the Ethernet frame.
System Configuration Registers

Table 33. contains a list of signals which can be configured using the system configuration
registers.
Note:
SYS_CFG7 must be configured appropriately before using the Ethernet GMAC subsystem,
to enable ethernet functions and clock schemes.
a. From Synopsys Designware Cores Ethernet MAC Universal Databook - Databook Version 3.3 - August 2006
8137791 RevA
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Ethernet subsystem
System Configuration
Configuration Register
Comment
PHY Interface Selection
00 : GMII/MII (default)
01 : RGMII (not used)
10 : SGMII
system_config7[26:25]
RMII Mode Selection

0: RMII interface activated
1: MII interface activated
system_config[18]
Interface Speed
0 : 10Mbps (divide by 20)
1 : 100MBps (divide by 2)
system_config7[20]
Interface Type
0 - revMII Enabled
1 - MII Enabled
system_config7[27]
Interface On
0: Ethernet interface off
1: Ethernet interface on
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system_config7[16]
system_config7[19]
PHY Clock Selection

0: PHY clock provided by STi7105
1: PHY clock is external
system_config[17]
MIIM Selection
0: MIIM_DIO from GMAC
1: MIIM_DIO from external input
Clock Selection
0 : Use divided phyclk_in
1 : Use rxclk/txclk
NOT system_config7[26]
12.3
Ethernet I/O Modes

Table 34.
GMAC PADs Required
PAD
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Comment
ETHMII_PHYCLK
PHY clock in MII mode

Reference clock in RMII mode
ETHMII_COL
i
o
Collision: it is asserted by the PHY when detecting a collision on the

medium in half duplex mode
ETHMII_CRS
i
o
Carrier Sense: it is asserted by the PHY in half duplex mode when

either the transmit or the receive medium is not idle or during a
collision
ETHMII_MDC
i
o
Management Data Clock for MDIO serial data channel
8137791 RevA
Table 33.
STi7105
STi7105
Ethernet subsystem
Table 34.
GMAC PADs Required (continued)
PAD
Comment
Management Data Interrupt from PHY which is an input to the
interrupt controller.
ETHMII_MDINT
ETHMII_MDIO
i
o
Management Data I/O bidirectional channel for PHY communications
Management data output enable (active low)
ETHMII_RXCLK
Receive clock: Timing reference for RX_DV, RX_ER, RXD
ETHMII_RXD[n:0]
Recive Data from the PHY synchronous to RXCLK
ETHMII_RXDV
Receive data valid
ETHMII_RXER
Receive error
ETHMII_TXCLK
ETHMII_TXD[n:0]
ETHMII_TXEN
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ETHMII_TXER
Transmit Clock: timing reference for TX_EN and TXD

Transmit Data driven by the MAC
indicated the MAC is presenting nibbles on the MII for transmission

Transmit error
Note:
phy_tx_clk_ps and phy_rx_clk_ps only connected if GRMII modes required
12.3.1
MII Mode
Table 35.
MII PADs Mapping
PAD
Mapping
Dir
PAD
Mapping
(1)
PHYCLK
Out
ETHMII_RXCLK
RXCLK
ETHMII_COL
COL
In
ETHMII_RXD[3:0]
RXD
ETHMII_CRS
CRS
ETHMII_RXDV
RXDV
ETHMII_MDC
MDC
Out
ETHMII_RXER
RXER
ETHMII_MDINT
MDINT
In
ETHMII_TXCLK
TXCLK
ETHMII_TXD[3:0]
TXD
ETHMII_TXER
TXER
ETHMII_TXEN
TXEN
ETHMII_PHYCLK
ETHMII_MDIO
MDI/MDO
MDO_enN
Dir
In
Out
1. Not used for the GMAC in MII mode, This is a STi7105 ethernet output unless an external clock option is
selected.
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Ethernet subsystem
STi7105
Figure 33. Ethernet MII Mode
system_config7[19]
B
clk_ethernet
Ext Osc
D
phy_rmii_clk
25Mhz xtal
TX_clk
phy_tx_clk
RX_clk
phy_rx_clk
enmii = 1
sclk x1
tx_clk
mdc
MDC
x2
rx_clk
mdc
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PHY (STE101P)
Table 36.
MII and MII overdrive configuration

Clock Source and Rate (Mhz)
Mode
clk_
ethernet
Ext Osc
MII external clock

MII internal clock
12.3.2
STe101P
Osc
25
25-75
25-75
drv_clk_
ethernet
no
25
MII overdrive external clock

MII overdrive internal clock
Routing (c = closed)
yes
no
yes
RMII (Reduced MII) Mode

The ethernet controller subsystem also supports an RMII protocol to interface an RMIIbased PHY.
The RMII specification has been optimized for use in high port density interconnect devices
which require independent treatment of the data paths. The primary motivator is a switch
ASIC which requires independent data streams between the MAC and PHY.
In choosing the signaling for the RMII specification, the following criteria was applied:
Clock frequency of 50 MHz or less to minimize ASIC I/O requirements
Pin count independent of port density of the PHY
Single synchronous clocking
Reduction of required control pins
By doubling the clock frequency 4 pins are saved on the data path alone without
substantially impacting ASIC I/O capabilities.
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8137791 RevA
GMAC
STi7105
Ethernet subsystem
A single synchronous reference clock for transmit, receive, and control is used. This
corresponds to one output from the switch ASIC. Alternatively, the clock reference could be
sourced from an external device and may correspond to one input to the switch ASIC. Each
PHY provides a clock reference input. However, only one input is required for multiple PHYs
on a single IC.
Table 37.
RMII PADs mapping
PAD
Mapping
Dir
PAD
Mapping
ETHMII_PHYCLK
PHYCLK
Out
ETHMII_RXCLK
RXCLK
ETHMII_COL
COL
ETHMII_RXD[1:0]
RXD
ETHMII_RXDV
RXDV
Dir
In
CRS
ETHMII_MDC
MDC
Out
ETHMII_RXER
RXER
ETHMII_MDINT
MDINT
In
ETHMII_TXCLK
TXCLK
ETHMII_TXD[1:0]
TXD
ETHMII_TXER
TXER
ETHMII_TXEN
TXEN
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ETHMII_MDIO
MDI/MDO
MDO_enN
In
Out
Figure 34. Ethernet RMII mode

sysytem_config7[19]
clk_ethernet
B
D
mac_speed
/2
25/2.5 MHz
/20
GMAC
50 MHz
phy_tx_clk
N/C
tx_clk
phy_rx_clk
N/C
rx_clk
MDC
mdc
A
25 MHz xtal
sclk x1
phy_rmii_clk
Ext Osc
x2
PHY (STE101P)
mdc
enmii = 1
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ETHMII_CRS
Ethernet subsystem
Table 38.
STi7105
RMII configuration
Clock source and rate
Mode
clk_ethernet Ext Osc
RMII external clock
RMII internal clock
STe101P
drv_clk_
A B C D
Osc
ethernet
50 MHz
50 MHz
no
yes
Comment
phy_rmii_clk is at
50 MHz use SCLK
input
RevMII Mode
Table 39.
REV.MII PAD mapping
PAD
Mapping
Dir
PAD
Mapping
ETHMII_PHYCLK
PHYCLK
Out
ETHMII_RXCLK
RXCLK
ETHMII_COL
COL
ETHMII_RXD[3:0]
RXD
ETHMII_RXDV
RXDV
Dir
Confidential
Out
ETHMII_CRS
CRS
ETHMII_MDC
MDC
In
ETHMII_RXER
RXER
ETHMII_MDINT
MDINT
In
ETHMII_TXCLK
TXCLK
ETHMII_TXD[3:0]
TXD
ETHMII_TXER
TXER
ETHMII_TXEN
TXEN
ETHMII_MDIO
MDI/MDO
MDO_enN
In
Out
Rev MII mode allows two Ethernet MACs to connect without using a PHY layer. It is used for
on-PCB backplane connection and can be used in 100 Mbps mode only.
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8137791 RevA
12.3.3
Routing (c = closed)
STi7105
Ethernet subsystem
Figure 35. Ethernet Rev.MII mode
sysytem_config7[19]
A
clk_ethernet
B
Ext Osc
phy_rmii_clk
TX_clk
phy_tx_clk
RX_clk
phy_rx_clk
mdc
exmdc
Other MAC
tx_clk
rx_clk
MDC
enmii = 0
CRS, COL
Confidential
excrs, excol
TX
TX
RX
enmii = 0
revMii enabled
Table 40.
RX
change from
normal
connectivity
Rev.MII configuration
Routing (c =
closed)
Clock Source and Rate

Mode
Comment
clk_ethernet
Rev.MII external clock
Rev.MII internal clock
12.3.4
revMii disabled
enmii = 1
Ext Osc
A B
25 MHz
2.5 MHz
25 MHz or
2.5 MHz
drv_clk_
ethernet
no
External 25 MHz
could come from the
other GMAC
yes
GMII Mode
GMII mode always uses an external clock supplied by an oscillator or the gigabit-PHY.
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GMAC
Ethernet subsystem
STi7105
Figure 36. Ethernet GMII mode
Ext Osc
125Mhz
SM7745DV
GMAC
RX_clk
phy_rx_clk
mdc
MDC
Confidential
enmii = 1
tx_clk
rx_clk
mdc
Gigabit-PHY
Figure 37. Ethernet GMII mode using GTX_Clk
125Mhz
Ext Osc
SM7745DV
PHYCLK
GTX_clk
TX_clk
phy_tx_clk
RX_clk
GMAC
phy_rx_clk
MDC
enmii = 1
Note:
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mdc
gtx_clk
tx_clk
rx_clk
mdc
Gigabit-PHY
GTX_CLK is a delayed version of TX_CLK which is aligned to TX_DATA signals.This is

added to ease the board level requirements to meet the setup/hold requirements on the TX
interface.
8137791 RevA
TX_clk
phy_tx_clk
STi7105
Ethernet subsystem
Figure 38. Ethernet GMII mode connecting to EN2210
RF
EN1010
xtal
PHYCLK
phy_tx_clk
GMAC
emac_txclk
PLL
TX_clk
RX_clk
phy_rx_clk
mdc
MDC
emac_rxclk_mii
mdc
Confidential
enmii = 1
EN2210
The Entropic EN2210 c.LINK Coaxial Network Controller supports a GMII interface at
125Mhz.
It receives a 25MHz input clock from the EN1010 device which feeds an internal PLL which
outputs a 125Mhz clock to drive the EMAC_RXCLK_MII pin.
This clock can be used by the STi7105 as a 125Mhz input clock to drive the TX interface.
This can then be used to generate an output clock (GTX_clk) which is aligned to the TXD
interface. Section 35.2.2.2 of the IEEE Std 802.3-2005 describes RX_CLK as continuous,
and so it should be able to be used instead of a clock from an external PLL if it meets the
timing specifications.
The EN2210 datasheet acknowledges that it does not meet the GMII specification in all
process and temperature corners. It is therefore important to ensure that the STi7105
ensures that there is very good alignment of the TX signals with the GTX_clk.
12.4
Ethernet Subsystem Architecture

The ethernet subsystem consists of the following functional blocks:
Figure 39. Ethernet subsystem block diagram
AMBA bus
STbus
bridge
DMA
MTL
GMAC
XMII
STBus
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GTX_clk
Ethernet subsystem
12.4.1
STi7105
STBus bridge
The STBus Bridge performs the protocol conversion between the AHB-type data traffic
inside the Subsystem and the STBus-type data traffic used in the STi7105 central
interconnect network. It has configuration registers located at the following base address:
0xFD11 7000
DMA block
The DMA has independent Transmit and Receive engines, and a CSR space. The Transmit
Engine transfers data from system memory to the device port (MTL), while the Receive
Engine transfers data from the device port to system memory. The controller utilizes
descriptors to efficiently move data from source to destination with minimal Host CPU
intervention. It has configuration registers located at the following base address:
0xFD11 1000
12.4.3
MTL block
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The MAC Transaction Layer provides FIFO memory to buffer and regulate the frames
between the application system memory and the GMAC core.
12.4.4
GMAC block
The Ethernet Media Access Controller (MAC) incorporates the essential protocol
requirements for operating an Ethernet/IEEE 802.3-compliant node, and provides an
interface between the host subsystem and the Media Independent Interface (MII). The MAC
operates in either the 100-Mbps or 10-Mbps mode, based on the MII (25/2.5 MHz) clock or
overclocked MII (up to 75 MHz) for Home Networking applications.
12.4.5
XMII block
The XMII block controls the GMAC data traffic to and from the MII/RMII external interface.
12.5
DMA block
12.5.1
Overview
The DMA has independent Transmit and Receive engines, and a CSR space. The Transmit
Engine transfers data from system memory to the device port (MTL), while the Receive
Engine transfers data from the device port to system memory. The controller utilizes
descriptors to efficiently move data from source to destination with minimal Host CPU
intervention. The DMA is designed for packet-oriented data transfers such as frames in
Ethernet. The controller can be programmed to interrupt the Host CPU for situations such as
Frame Transmit and Receive transfer completion, and other normal/error conditions.
The DMA and the Host driver communicate through two data structures:
Control and Status registers (CSR)
Descriptor lists and data buffers
Control and Status registers are described in detail in Chapter 13: Ethernet registers.
Descriptors are described in detail in Section 12.6
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8137791 RevA
12.4.2
STi7105
Ethernet subsystem
The DMA transfers data frames received by the core to the Receive Buffer in the Host
memory, and Transmit data frames from the Transmit Buffer in the Host memory. Descriptors
that reside in the Host memory act as pointers to these buffers.
A data buffer resides in the Host physical memory space, and consists of an entire frame or
part of a frame, but cannot exceed a single frame. Buffers contain only data, buffer status is
maintained in the descriptor. Data chaining refers to frames that span multiple data buffers.
However, a single descriptor cannot span multiple frames. The DMA will skip to the next
frame buffer when end-of-frame is detected. Data chaining can be enabled or disabled.
Confidential
Figure 40 shows the descriptor organization.

Figure 40. Descriptor ring and chain structure examples
Buffer 1
Descriptor 0
Buffer 1
Buffer 2
Descriptor 0
Buffer 1
Descriptor 1
Buffer 2
Buffer 1
Buffer 2
Descriptor 1
Descriptor 2
Buffer 2
Next descriptor
Buffer 1
Descriptor n
Buffer 2
Each descriptor contains two buffers, two byte-count buffers, and two address pointers,
which enable the adapter port to be compatible with various types of memory management
schemes. The descriptor addresses must be aligned to the bus width used
(Word/Dword/Lword for 32/64/128- bit buses).
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There are two descriptor lists; one for reception, and one for transmission. The base
address of each list is written into GMAC_RCV_BASE_ADDR and
GMAC_XMT_BASE_ADDR, respectively. A descriptor list is forward linked (either implicitly
or explicitly). The last descriptor may point back to the first entry to create a ring structure.
Explicit chaining of descriptors is accomplished by setting the second address chained in
both Receive and Transmit descriptors (RDES1[24] and TDES1[24]). The descriptor lists
resides in the Host physical memory address space. Each descriptor can point to a
maximum of two buffers. This enables two buffers to be used, physically addressed, rather
than contiguous buffers in memory.
Ethernet subsystem
12.5.2
STi7105
Initialization
1.
Write to GMAC_BUS_MODE to set Host bus access parameters.
2.
Write to GMAC_DMA_INT_EN to mask unnecessary interrupt causes.
3.
The software driver creates the Transmit and Receive descriptor lists. Then it writes to
both GMAC_RCV_BASE_ADDR and GMAC_XMT_BASE_ADDR, providing the DMA
with the starting address of each list.
4.
Write to GMAC_FRAME, GMAC_HASH_TBL_HI and GMAC_HASH_TBL_LO for

desired filtering options.
5.
Write to GMAC_CFG to configure and enable the Transmit and Receive operating
modes. The PS and DM bits are set based on the auto-negotiation result (read from the
PHY).
6.
Write to GMAC_DMA_CTRL to set bits 13 and 1 to start transmission and reception.
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The Transmit and Receive engines enter the Running state and attempt to acquire
descriptors from the respective descriptor lists. The Receive and Transmit engines then
begin processing Receive and Transmit operations. The Transmit and Receive processes
are independent of each other and can be started or stopped separately.
12.5.3
Transmission
Default Mode
The Transmit DMA engine in default mode proceeds in the following sequence:
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1.
The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame
data.
2.
Once the ST bit (GMAC_DMA_CTRL[13]) is set, the DMA enters the Run state.
3.
While in the Run state, the DMA polls the Transmit Descriptor list for frames requiring
transmission. After polling starts, it continues in either sequential descriptor ring order
or chained order. If the DMA detects a descriptor flagged as owned by the Host, or if an
error condition occurs, transmission is suspended and both the Transmit Buffer
Unavailable (GMAC_DMA_STA[2]) and Normal Interrupt Summary
(GMAC_DMA_STA[16]) bits are set. The Transmit Engine proceeds to Step 9..
4.
If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1b1), the DMA
decodes theTransmit Data Buffer address from the acquired descriptor.
5.
The DMA fetches the Transmit data from the Host memory and transfers the data to the
MTL for transmission.
6.
If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes
the intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5 are
repeated until the end-of-Ethernet frame data is transferred to the MTL.
7.
When frame transmission is complete, status information is written into Transmit

Descriptor 0 (TDES0) which has the end-of frame buffer.
8.
Transmit Interrupt (GMAC_DMA_STA[0]) is set after completing transmission of a

frame that has Interrupt on Completion (TDES1[31]) set in its Last Descriptor. The
DMA engine then returns to Step 3..
9.
In Suspend state, the DMA tries to re-acquire the descriptor (jump to Step 3.) when it
receives a Transmit Poll demand and the Underflow Interrupt Status bit is cleared.
8137791 RevA
Initialization for the GMAC is as follows;
STi7105
Ethernet subsystem
Figure 41 shows the default transmission flow.
Figure 41. Normal TxDMA operation
Reset
TXDMA
START
(Re-)Fetch next
descriptor
Tx poll
demand
TXDMA
SUSPEND
Yes
TXDMA
STOP
(AHB)
Error?
No
No
OWN bit = 1?
Confidential
Yes
Transfer data
from buffer(s)
(AHB)
Error?
Yes
No
No
Frame transfer
complete?
Yes
Wait for
Tx status
Close
descriptor
No
(AHB)
Error?
Yes
While in the Run state, the transmit process can simultaneously acquire two frames without
closing the Status descriptor of the first (if the OSF bit is set in GMAC_DMA_CTRL[2]). As
the transmit process finishes transferring the first frame, it immediately polls the Transmit
Descriptor list for the second frame. If the second frame is valid, the transmit process
transfers this frame before writing the status information of the first frame.
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Ethernet subsystem
STi7105
OSF Mode
In OSF mode, the sequence of Transmit DMA operation in the Run state is as follows:
The DMA operates as described in steps 1-6 of the Transmission process.
2.
Without closing the previous frames descriptor, the DMA fetches the next descriptor.
3.
If the acquired descriptor is owned by DMA, the DMA decodes the Transmit Buffer
address in this descriptor. If the descriptor is not owned by DMA, the sequence DMA
goes into SUSPEND mode and the sequence skips to Step 9.
4.
The DMA fetches the Transmit frame from the Host memory and transfers the frame to
the MTL until the End-of-Frame data is transferred.
5.
The DMA waits for the previous frames frame transmission status and writes the status
to its corresponding TDES0 when it receives it.
6.
If enabled, the Transmit interrupt is set, the DMA fetches the next descriptor, then
proceeds to Step 3. (when Status is normal). If the transmission status shows errors
such as Underflow, the DMA goes into Suspend mode (Step 9.).
7.
The DMA waits for the current frames frame transmission status and, when it received
it, writes the status to the corresponding TDES0.
8.
If enabled, the Transmit interrupt is set and the DMA goes into Suspend mode.
9.
In Suspend mode, if any pending status is received from MTL, that status is written to
the corresponding TDES0, relevant interrupts are set, and the DMA returns to Suspend
mode.
10. The DMA can exit Suspend mode and enter the Run state (go to Step 1. or Step 2.
depending on pending status) only after receiving a Transmit Poll demand
(GMAC_XMT_POLL_DEMAND).
Figure 42 shows the basic flow in OSF mode.
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1.
STi7105
Ethernet subsystem
Figure 42. TxDMA operation in OSF mode
Reset
TXDMA
START
Tx poll
demand?
Yes
(AHB)
Error?
First frames
Tx status or
Tx poll demand
TXDMA
SUSPEND
(Re-)Fetch next
descriptor
Yes
TXDMA
STOP
No
No
No
OWN bit = 1?
Yes
Confidential
Close first
frames last
descriptor
(AHB)
Error?
Transfer data
from buffer(s)
(AHB)
Error?
No
Yes
No
Yes
Frame transfer
complete?
No
Yes
No
Second
frame?
Yes
Close
descriptor
Wait for previous

frames Tx status
Close previous
frames last
descriptor
No
(AHB)
Error?
8137791 RevA
Yes
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Ethernet subsystem
12.5.4
STi7105
Reception
1.
The host sets up Receive descriptors (RDES0-RDES3) and sets the Own bit
(RDES0[31]).
2.
Once the SR (GMAC_DMA_CTRL[1]) bit is set, the DMA enters the Run state. While in
the Run state, the DMA polls the Receive Descriptor list, attempting to acquire free
descriptors.
3.
The DMA decodes the receive data buffer address from the acquired descriptors.
4.
Incoming frames are processed and placed in the acquired descriptors data buffers.
5.
When the buffer is full or the frame transfer is complete, the Receive engine fetches the
next descriptor.
6.
The status information is written to RDES0 of the previous Receive descriptor with the
frames Own bit reset to 1b0. If the frame transfer is not complete, the Descriptor Error
bit is set and the DMA does not own the next descriptor.
7.
The Receive engine checks the latest descriptors Own bit. When the host owns a
descriptor, the Own bit is 1b0, the Receive Buffer Unavailable bit
(GMAC_DMA_STA[7]) is set and the Receive Engine enters the Suspended state. If
the DMA owns the descriptor, the engine jumps to Step 4 and awaits the next frame.
8.
Before the Receive engine enters the Suspend state, partial frames are flushed from
the Receive FIFO (user-controllable).
9.
The Receive DMA exits the Suspend state when a Receive Poll demand is given or the
start of next frame is available from the MTLs Receive FIFO. The engine proceeds to
Step 2 and fetches the next descriptor.
Figure 43 shows the default receive flow.
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The general reception sequence proceeds as follows:
STi7105
Ethernet subsystem
Figure 43. RxDMA operation
Reset
RXDMA
START
RXDMA
SUSPEND
Rx poll demand/
Frame in Rx FIFO
Flush rest
of frame
(AHB)
Error?
No
Yes
RXDMA
STOP
No
Flush
disabled?
Yes
(Re-)Fetch next
descriptor
No
Yes
Frame transfer
complete?
No
OWN bit = 1?
Confidential
Yes
Frame transfer
complete?
No
Yes
Wait for
RxFrame
Transfer data to buffers

until buffer is full or
frame transfer over
(AHB)
Error?
Yes
No
Fetch next
descriptor
(AHB)
Error?
Yes
No
Close previous
descriptor
No
(AHB)
Error?
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Yes
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Ethernet subsystem
12.5.5
STi7105
Interrupts
Interrupts can be generated as a result of various events. GMAC_DMA_STA contains all the
bits that might cause an interrupt. GMAC_DMA_INT_EN contains an Enable bit for each of
the events that can cause an interrupt.
Confidential
Interrupts are not queued and if the interrupt event occurs before the driver has responded
to it, no additional interrupts are generated. For example, Receive Interrupt
(GMAC_DMA_STA[6]) indicates that one or more frames was transferred to the Host buffer.
The driver must scan all descriptors, from the last recorded position to the first one owned
by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan
GMAC_DMA_STA for the interrupt cause. The interrupt is not generated again, unless a
new interrupting event occurs after the driver has cleared the appropriate GMAC_DMA_STA
bit. For example, the controller generates a Receive Interrupt (GMAC_DMA_STA[6]) and the
driver begins reading GMAC_DMA_STA. Next, Receive Buffer Unavailable
(GMAC_DMA_STA[7]) occurs. The driver clears the Receive Interrupt. sbd_intr_o is
deasserted for at least one cycle and then asserted again for the Receive Buffer Unavailable
Interrupt.
12.6
Descriptors
12.6.1
Format
The DMA in the Ethernet subsystem transfers data based on a linked list of descriptors.
Each descriptor, transmit or receive, contains two buffers, two byte-count buffers, and two
address pointers, which enable the adapter port to be compatible with various types of
memory management schemes.
12.6.2
Receive descriptors
The GMAC Subsystem requires at least two descriptors when receiving a frame. The
Receive state machine of the DMA (in the GMAC Subsystem) always attempts to acquire an
extra descriptor in anticipation of an incoming frame. (The size of the incoming frame is
unknown). Before the RxDMA closes a descriptor, it will attempt to acquire the next
descriptor even if no frames are received.
In a single descriptor (receive) system, the subsystem will generate a descriptor error if the
receive buffer is unable to accommodate the incoming frame and the next descriptor is not
owned by the DMA. Thus, the Host is forced to increase either its descriptor pool or the
buffer size. Otherwise, the subsystem starts dropping all incoming frames. Figure 44 shows
the Receive Descriptor format.
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There are two groups of interrupts, Normal and Abnormal, as described in

GMAC_DMA_STA. Interrupts are cleared by writing a 1b1 to the corresponding bit position.
When all the enabled interrupts within a group are cleared, the corresponding summary bit
is cleared. If the GMAC core is the cause for assertion of the interrupt, then any of the GLI,
GMI, or GPI bits of GMAC_DMA_STA will be set high.
STi7105
Ethernet subsystem
Figure 44. Receive descriptor format in Little-Endian Mode with a 32-bit data bus
31
O
RDES0
Status [30:0]
Confidential
Note:
Control bits [9:0]
Byte Count Buffer 2 [10:0]
RDES2
Buffer 1 address pointer [31:0]
RDES3
Buffer 2 address pointer [31:0]/

Next descriptor address pointer [31:0])
If only a single Receive Descriptor is used, the buffer size should be sufficiently large to hold
the incoming Ethernet frame.
RDES0 contains the received frame status, the frame length, and the descriptor ownership
information. Table 41 describes the bit fields of the RDES0. All bits fields except Bits 31 and
Bit 9 are valid only when the LS bit (RDES0[8]) is set.
Table 41.
Field
Receive descriptor 0 description (RDES0)
Description
31
OWN: Own bit

When set, this bit indicates that the descriptor is owned by the DMA of the GMAC
Subsystem. When this bit is reset, this bit indicates that the descriptor is owned by the Host.
The DMA clears this bit either when it completes the frame reception or when the buffers that
are associated with this descriptor are full.
30
AFM: Destination Address Filter Fail

When set, this bit indicates that the frame failed the destination address filtering in the GMAC
core.
FL: Frame Length

Indicates the byte length of the received frame transferred to host memory (including CRC).
This field is valid only when Last Descriptor (RDES0[8]) is set and Descriptor Error
(RDES0[14]) is reset. The frame length also includes the two bytes appended to the Ethernet
29:16 frame when IP checksum calculation (Type 1) is enabled and the received frame is not a
MAC control frame.
This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and
Error Summary bits are not set, this field indicates the accumulated number of bytes that
have been transferred for the current frame.
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RDES1
Ethernet subsystem
Table 41.
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Receive descriptor 0 description (RDES0) (continued)
Description
15
ES: Error Summary

Indicates the logical OR of the following bits:
RDES0[1]: CRC Error
RDES0[3]: Receive Error
RDES0[4]: Watchdog Timeout
RDES0[6]: Late Collision
RDES0[7]: Giant Frame (This is not applicable when RDES0[7] indicates an IPV4 header
Checksum error.)
RDES0[11]: Overflow Error
RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
14
DE: Descriptor Error

When set, this bit indicates a frame truncation caused by a frame that does not fit within the
current descriptor buffers, and that the DMA does not own the Next Descriptor. The frame is
truncated. This field is valid only when the Last Descriptor (RDES0[8]) is set.
13
SAF: Source Address Filter Fail

When set, this bit indicates that the SA field of frame failed the SA Filter in the GMAC Core.
12
LE: Length Error

When set, this bit indicates that the actual length of the frame received and that the Length/
Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset.
11
OE: Overflow Error

When set, this bit indicates that the received frame was damaged due to buffer overflow in
MTL.
10
VLAN: VLAN Tag

When set, this bit indicates that the frame pointed to by this descriptor is a VLAN frame
tagged by the GMAC Core.
FS-First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size
of the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the
second buffer is also 0, the next Descriptor contains the beginning of the frame.
LS-Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of
the frame.
IPC Checksum Error/Giant Frame

When set, this bit indicates that the 16-bit IPv4 Header checksum calculated by the core did
not match the received checksum bytes. If this bit is set when Full Checksum Offload Engine
(Type 2) is enabled, it indicates an error in the IPv4 or IPv6 header. This error can be due to
inconsistent Ethernet Type field and IP header Version field values, a header checksum
mismatch in IPv4, or an Ethernet frame lacking the expected number of IP header bytes.
If IP Checksum Module is not selected during core configuration, this bit, when set, indicates
that the received frame was a Giant Frame. Giant frames are larger-than-1,518-byte (or
1,522-byte for VLAN) normal frames and larger-than-9,018-byte (9,022-byte for VLAN) frame
when Jumbo Frame processing is enabled.
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Field
STi7105
STi7105
Ethernet subsystem
Table 41.
Description
LC: Late Collision

When set, this bit indicates that a late collision has occurred while receiving the frame in HalfDuplex mode.
FT: Frame Type

When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is
greater than or equal to 16h0600). When this bit is reset, it indicates that the received frame
is an IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes.
RWT: Receive Watchdog Timeout

When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the
current frame and the current frame is truncated after the Watchdog Timeout.
RE: Receive Error

When set, this bit indicates that the ETHMII_RXER signal is asserted while ETHMII_RXDV is
asserted during frame reception. Error can be of less/no extension, or error (rxd != 0f) during
extension.
DE: Dribble Bit Error

When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd
nibbles). This bit is valid only in MII Mode.
CE: CRC Error

When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the
received frame. This field is valid only when the Last Descriptor (RDES0[8]) is set.
Rx MAC Address/Payload Checksum Error

When set, this bit indicates that the Rx MAC Address registers value (1 to 15) matched the
frames DA field. When reset, this bit indicates that the Rx MAC Address Register0 value
matched the DA field. If Full Checksum Offload Engine is enabled, this bit, when set,
indicates the TCP, UDP, or ICMP checksum the core calculated does not match the received
encapsulated TCP, UDP, or ICMP segments Checksum field. This bit is also set when the
received number of payload bytes does not match the value indicated in the Length field of
the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame.
Receive descriptor 1 (RDES1)

RDES1 contains the buffer sizes and other bits that control the descriptor chain/ring.
Table 42 describes the bit fields of the RDES1.
Table 42.
Field
31
Description
Disable Interrupt on Completion
When set, this bit will prevent the setting of the RI (CSR5[6]) bit of the Status Register for the
received frame that ends in the buffer pointed to by this descriptor. This, in turn, will disable
the assertion of the interrupt to Host due to RI for that frame.
30:26 Reserved (default:0h)

25
RER: Receive End of Ring

When set, this bit indicates that the descriptor list reached its final descriptor. The DMA
returns to the base address of the list, creating a Descriptor Ring.
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Field
Ethernet subsystem
Table 42.
Field
24
STi7105
Description
RCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor
address rather than the second buffer address. When RDES1[24] is set, RBS2 (RDES1[2111]) is a dont care value. RDES1[25] takes precedence over RDES1[24].
RBS2: Receive Buffer 2 Size

These bits indicate the second data buffer size in bytes. The buffer size must be a multiple of
21:11 4/8/16 depending upon the bus widths (32/64/128), even if the value of RDES3 (buffer2
address pointer) is not aligned to bus width. In the case where the buffer size is not a
multiple of 4/8/16, the resulting behavior is undefined. This field is not valid if RDES1[24] is
set.
Confidential
10:0

Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4/8/16
depending upon the bus widths (32/64/128), even if the value of RDES2 (buffer1 address
pointer) is not aligned. In the case where the buffer size is not a multiple of 4/8/16, the
resulting behavior is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer
2 or next descriptor depending on the value of RCH (bit 24).

RDES2 contains the address pointer to the first data buffer in the descriptor. Table 43
describes the bit fields of the RDES2.
Table 43.
Field
31:0
Description
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There are no limitations on the buffer
address alignment except for the following condition: The DMA uses the configured value for
its address generation when the RDES2 value is used to store the start of frame. Note that
the DMA performs a write operation with the RDES2[3/2/1:0] bits as 0 during the transfer of
the start of frame but the frame data is shifted as per the actual Buffer address pointer. The
DMA ignores RDES2[3/2/1:0] (corresponding to bus width of 128/64/32) if the address
pointer is to a buffer where the middle or last part of the frame is stored.

RDES3 contains the address pointer either to the second data buffer in the descriptor or the
next descriptor. Table 44 describes the bit fields of the RDES3.
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Ethernet subsystem
Table 44.
31:0
Confidential
12.6.3
Description
Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when descriptor chaining is used. If the
Second Address Chained (RDES1[24]) bit is set, then this address contains the pointer to
the physical memory where the Next Descriptor is present.
If RDES1[24] is set, the buffer (Next Descriptor) address pointer must be bus width-aligned
(RDES3[3, 2, or 1:0] = 0, corresponding to a bus width of 128, 64, or 32. LSBs are ignored
internally.) However, when RDES1[24] is reset, there are no limitations on the RDES3 value,
except for the following condition: The DMA uses the configured value for its buffer address
generation when the RDES3 value is used to store the start of frame. The DMA ignores
RDES3[3, 2, or 1:0] (corresponding to a bus width of 128, 64, or 32) if the address pointer is
to a buffer where the middle or last part of the frame is stored.
Transmit descriptors
The descriptor addresses must be aligned to the bus width used (32/64/128). Figure 45
shows the transmit descriptor format in Little-Endian mode with a 32-bit data bus.
Figure 45. Transmit descriptor format in Little-Endian Mode with a 32-bit data bus
31
TDES0
O
W
Status [30:0]
TDES1
Control bits [9:0]
TDES2
Buffer 1 address pointer [31:0]
TDES3
Buffer 2 address pointer [31:0]/

Next descriptor address pointer [31:0])
Transmit descriptor 0 (TDES0)

TDES0 contains the transmitted frame status and the descriptor ownership information. All
the bits except TDES0[31] are valid only if the LS bit (TDES1 [30]) of the descriptor is set.
Table 45 describes the bit fields of the TDES0.
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Field
Ethernet subsystem
Table 45.
Field
31
STi7105
Transmit descriptor 0 description (TDES0)
Description
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset,
this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either
when it completes the frame transmission or when the buffers allocated in the descriptor are
empty. The ownership bit of the First Descriptor of the frame should be set after all
subsequent descriptors belonging to the same frame have been set. This avoids a possible
race condition between fetching a descriptor and the driver setting an ownership bit.
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16
IHE: IP Header Error

When set, this bit indicates that the Checksum Offload engine detected an IP header error
and consequently did not modify the transmitted frame for any checksum insertion. This bit is
valid only when Full Checksum Offload is enabled; otherwise, it is reserved.
15
ES: Error Summary

Indicates the logical OR of the following bits:
TDES0[14]: Jabber Timeout
TDES0[13]: Frame Flush
TDES0[11]: Loss of Carrier
TDES0[10]: No Carrier
TDES0[9]: Late Collision
TDES0[8]: Excessive Collision
TDES0[2]: Excessive Deferral
TDES0[1]: Underflow Error
14
JT: Jabber Timeout

When set, this bit indicates the GMAC transmitter has experienced a jabber time-out. This bit
is only set when the GMAC configuration registers JD bit is not set.
13
FF: Frame Flushed

When set, this bit indicates that the DMA/MTL flushed the frame due to a SW flush command
given by the CPU.
12
PCE: Payload Checksum Error

This bit, when set, indicates that the Checksum Offload engine had a failure and did not
insert any checksum into the encapsulated TCP, UDP, or ICMP payload. This failure can be
either due to insufficient bytes, as indicated by the IP Headers Payload Length field, or the
MTL starting to forward the frame to the MAC transmitter in Store-and-Forward mode without
the checksum having been calculated yet. This second error condition only occurs when the
Transmit FIFO depth is less than the length of the Ethernet frame being transmitted: to avoid
deadlock, the MTL starts forwarding the frame when the FIFO is full, even in Store-andForward mode.
11
LC: Loss of Carrier

When set, this bit indicates that Loss of Carrier occurred during frame transmission (that is,
the ETHMII_CRS signal was inactive for one or more transmit clock periods during frame
transmission). This is valid only for the frames transmitted without collision and when the
GMAC operates in Half-Duplex Mode.
10
NC: No Carrier
When set, this bit indicates that the carrier sense signal form the PHY was not asserted
during transmission.
8137791 RevA
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30:17 Reserved (default: 0x0)
STi7105
Ethernet subsystem
Table 45.
LC: Late Collision

When set, this bit indicates that frame transmission was aborted due to a collision occurring
after the collision window (64 byte times including Preamble in MII Mode). Not valid if
Underflow Error is set.
EC: Excessive Collision

When set, this bit indicates that the transmission was aborted after 16 successive collisions
while attempting to transmit the current frame. If the DR (Disable Retry) bit in the GMAC
Configuration Register is set, this bit is set after the first collision and the transmission of the
frame is aborted.
VF: VLAN Frame

When set, this bit indicates that the transmitted frame was a VLAN-type frame.
6:3
Confidential
Description
CC: Collision Count

This 4-bit counter value indicates the number of collisions occurring before the frame was
transmitted. The count is not valid when the Excessive Collisions bit (TDES0[8]) is set.
ED: Excessive Deferral

When set, this bit indicates that the transmission has ended because of excessive deferral of
over 24,288 bit times (155,680 bits times in 1000-Mbps mode, or in Jumbo Frame enabled
mode) if the Deferral Check (DC) bit is set high in the GMAC Control Register.
UF: Underflow Error

When set, this bit indicates that the GMAC aborted the frame because data arrived late from
the Host memory. Underflow Error indicates that the DMA encountered an empty Transmit
Buffer while transmitting the frame. The transmission process enters the suspended state
and sets both Transmit Underflow (GMAC_DMA_STA[5]) and Transmit Interrupt
(GMAC_DMA_STA[0]).
DB: Deferred Bit

When set, this bit indicates that the GMAC defers before transmission because of the
presence of carrier. This bit is valid only in Half-Duplex mode.

TDES1 contains the buffer sizes and other bits which control the descriptor chain/ring and
the frame being transferred. Table 46 describes the bit fields of the TDES1.
Table 46.
Field
Description
31
IC-Interrupt on Completion
When set, the DMA Controller sets Transmit Interrupt bit CSB5[0] after the present frame has
been transmitted.
30
LS-Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame.
29
FS-First: Segment
When set, this bit indicates that the buffer contains the first segment of the frame.
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Field
Transmit descriptor 0 description (TDES0) (continued)
Ethernet subsystem
Table 46.
Transmit descriptor 1 description (TDES1) (continued)
Description
Confidential
CIC: Checksum Insertion Control

These bits control the insertion of checksums in Ethernet frames that encapsulate TCP, UDP,
or ICMP over IPv4 or IPv6 as described below:
2'b00: Do nothing. Checksum Engine is bypassed.
2'b01: Insert IPv4 header checksum. Use this value to insert IPv4 header checksum when
the frame encapsulates an IPv4 datagram.
2'b10: Insert TCP/UDP/ICMP checksum. The checksum is calculated over the TCP, UDP,
or ICMP segment only and the TCP, UDP, or ICMP pseudo-header checksum is assumed
28:27
to be present in the corresponding input frames Checksum field. An IPv4 header
checksum is also inserted if the encapsulated datagram conforms to IPv4.
2'b11: Insert a TCP/UDP/ICMP checksum that is fully calculated in this engine. In other
words, the TCP, UDP, or ICMP pseudo-header is included in the checksum calculation, and
the input frames corresponding Checksum field has an all-zero value. An IPv4 Header
checksum is also inserted if the encapsulated datagram conforms to IPv4.
The Checksum engine detects whether the TCP, UDP, or ICMP segment is encapsulated in
IPv4 or IPv6 and processes its data accordingly.
26
DC: Disable CRC

When set, the GMAC does not append the Cyclic Redundancy Check (CRC) to the end of
the transmitted frame. This is valid only when the first segment (TDES1[29]).
25
TER: Transmit End of Ring

When set, this bit indicates that the descriptor list reached its final descriptor. The returns to
the base address of the list, creating a descriptor ring.
24
TCH: Second Address Chained

address rather than the second buffer address. When TDES1[24] is set, TBS2 (TDES1[21
11]) are dont care values. TDES1[25] takes precedence over TDES1[24].
23
DP: Disable Padding

When set, the GMAC does not automatically add padding to a frame shorter than 64 bytes.
When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than
64 bytes and the CRC field is added despite the state of the DC (TDES1[26]) bit. This is valid
only when the first segment (TDES1[29]) is set.
22
Reserved (default: 0x0)
TBS2-Transmit Buffer 2 Length

21:11 These bits indicates the size, in bytes, of the second data buffer. This field is not valid if
TDES1[24] is set.
10:0
TBS1: Transmit Buffer 1 Size

These bits indicate the First Data Buffer byte size. If this field is 0, the DMA ignores this buffer
and uses Buffer 2 or next descriptor depending on the value of TCH (bit 24).

TDES2 contains the address pointer to the first buffer of the descriptor. Table 47 describes
the bit fields of the TDES2.
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Field
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STi7105
Ethernet subsystem
Table 47.
Field
Description
31:0
Buffer 1 Address Pointer

This is the physical address of Buffer 1. There are no limitations on the buffer address
alignment.
Confidential
Table 48.
12.6.4
Field
Description
31:0
Buffer 2 Address Pointer (Next Descriptor Address)

Indicates the physical address of Buffer 2 when the descriptor chaining is used. If the
Second Address Chained (TDES1[24]) bit is set, then this address contains the pointer to the
physical memory where the Next Descriptor is present. The buffer address pointer must be
aligned to the bus width only when TDES1[24] is set. (LSBs are ignored internally.)
Alternate (Enhanced) Descriptor Structure

The default descriptor structure allows data buffers of up to 2,048 bytes. An alternative
descriptor structure has been implemented to support buffers of up to 8 KB (useful for
Jumbo frames). This descriptor structure also consists of four 32-bit words, as in the default
Receive and Transmit Descriptors. Figure 46. shows the alternate transmit descriptor format
and Figure 47. the alternate receive descriptor fortmat.
The main difference from the default is the re-assignment of the Control and Status bits in
TDES0, TDES1 and RDES1. Hence, only the description or bit-mapping of TDES0, TDES1,
and RDES1 in the alternate descriptor structure (in Little Endian mode) is given in Table 49.
(TDES0), Table 50. (TDES1) and Table 51. (RDES1).
Figure 46. Transmit descriptor format in Little-Endian Mode
31
TDES0
O
W
N
TDES1
Reserved
[31:29]
Ctrl
[30:26]
Reserved
[25:24]
Ctrl
[23:20]
Reserved
[17:17]
Buffer 2 Byte Count [23:16]
Reserved
[15:13]
Status [16:0]
TDES2
Buffer 1 address [31:0]
TDES3
Buffer 2 address [31:0] or

Next descriptor address [31:0])
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TDES3 contains the address pointer either to the second buffer of the descriptor or the next
descriptor. Table 48 describes the bit fields of the TDES3
Ethernet subsystem
STi7105
Figure 47. Receive descriptor format in Little-Endian Mode

31
O
RDES0
0
Ctrl
[30:26]
Reserved
[25:24]
Ctrl
[23:20]
Reserved
[17:17]
Status [16:0]
N
Ctrl
[15:14]
RDES2
Buffer 1 address [31:0]
RDES3
Buffer 2 address [31:0] or

Next descriptor address [31:0])
TDES0 in Enhanced Descriptor Structure
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The application software must program control bits 31:20 during descriptor initialization.
When the DMA updates the descriptor (or writes it back), it resets all the control bits
(including the Own bit) and reports only the status bits.
Table 49.
Field
Transmit descriptor word 0 (TDES0)
Description
31
OWN: Own Bit

When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it
indicates that the descriptor is owned by the Host. The DMA clears this bit either when it
completes the frame transmission or when the buffers allocated in the descriptor are read
completely. The ownership bit of the frames first descriptor must be set after all subsequent
descriptors belonging to the same frame have been set. This avoids a possible race
condition between fetching a descriptor and the driver setting an ownership bit.
30
IC: Interrupt on Completion

When set, this bit sets the Transmit Interrupt (Register5[0]) after the present frame has been
transmitted.
29
LS: Last Segment

When set, this bit indicates that the buffer contains the last segment of the frame.
28
FS: First Segment

When set, this bit indicates that the buffer contains the first segment of a frame.
27
DC: Disable CRC

When set, the GMAC does not append the Cyclic Redundancy Check (CRC) to the end of
the transmitted frame. This is valid only when the first segment (TDES1[28]).
26
DP: Disable Pad

When set, the GMAC does not automatically add padding to a frame shorter than 64 bytes.
When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than
64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is
valid only when the first segment (TDES0[28]) is set.
25:24 Reserved
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Reserved
[30:29] Buffer 2 Byte Count [28:16]
Reserved
Ctrl
RDES1
STi7105
Ethernet subsystem
Table 49.
Field
Transmit descriptor word 0 (TDES0) (continued)
Description
21
TER: Transmit End of Ring

returns to the base address of the list, creating a descriptor ring.
20
TCH: Second Address Chained

address rather than the second buffer address. When TDES0[20] is set, TBS2
(TDES1[28:16]) is a dont care value.
TDES0[21] takes precedence over TDES0[20].
19:17 Reserved
16
IHE: IP Header Error

When set, this bit indicates that the GMAC transmitter detected an error in the IP datagram
header. The transmitter checks the header length in the IPv4 packet against the number of
header bytes received from the application and indicates an error status if there is a
mismatch. For IPv6 frames, a header error is reported if the main header length is not 40
bytes. Furthermore, the Ethernet Length/Type field value for an IPv4 or IPv6 frame must
match the IP header version received with the packet. For IPv4 frames, an error status is also
indicated if the Header Length field has a value less than 0x5.
15
ES: Error Summary Indicates the logical OR of the following bits:

TDES0[14]: Jabber Timeout
TDES0[13]: Frame Flush
TDES0[11]: Loss of Carrier
TDES0[10]: No Carrier
TDES0[9]: Late Collision
TDES0[8]: Excessive Collision
TDES0[2]: Excessive Deferral
TDES0[1]: Underflow Error
TDES0[16]: IP Header Error
TDES0[12]: IP Payload Error
14
JT: Jabber Timeout

When set, this bit indicates the GMAC transmitter has experienced a jabber time-out. This bit
is only set when the GMAC configuration registers JD bit is not set.
13
FF: Frame Flushed

When set, this bit indicates that the DMA/MTL flushed the frame due to a software Flush
command given by the CPU.
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CIC: Checksum Insertion Control

These bits control the checksum calculation and insertion. Bit encodings are as shown
below:
2b00: Checksum Insertion Disabled.
23:22 2b01: Only IP header checksum calculation and insertion are enabled.
2b10: IP header checksum and payload checksum calculation and insertion are enabled,
but pseudo-header checksum is not calculated in hardware.
2b11: IP Header checksum and payload checksum calculation and insertion are enabled,
and pseudo-header checksum is calculated in hardware.
Ethernet subsystem
Table 49.
Description
12
IPE: IP Payload Error

When set, this bit indicates that GMAC transmitter detected an error in the TCP, UDP, or
ICMP IP datagram payload.
The transmitter checks the payload length received in the IPv4 or IPv6 header against the
actual number of TCP, UDP, or ICMP packet bytes received from the application and issues
an error status in case of a mismatch.
11
LC: Loss of Carrier

When set, this bit indicates that a loss of carrier occurred during frame transmission (that is,
the gmii_crs_i signal was inactive for one or more transmit clock periods during frame
transmission). This is valid only for the frames transmitted without collision when the GMAC
operates in Half-Duplex mode.
10
NC: No Carrier When set, this bit indicates that the Carrier Sense signal form the PHY was
not asserted during transmission.
LC: Late Collision

When set, this bit indicates that frame transmission was aborted due to a collision occurring
after the collision window (64 byte-times, including preamble, in MII mode and 512 bytetimes, including preamble and carrier extension, in GMII mode). This bit is not valid if the
Underflow Error bit is set.
EC: Excessive Collision

When set, this bit indicates that the transmission was aborted after 16 successive collisions
while attempting to transmit the current frame. If the DR (Disable Retry) bit in the GMAC
Configuration register is set, this bit is set after the first collision, and the transmission of the
frame is aborted.
VF: VLAN Frame

When set, this bit indicates that the transmitted frame was a VLAN-type frame.
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Transmit descriptor word 0 (TDES0) (continued)
CC: Collision Count

This 4-bit counter value indicates the number of collisions occurring before the frame was
transmitted. The count is not valid when the Excessive Collisions bit (TDES0[8]) is set.
ED: Excessive Deferral

When set, this bit indicates that the transmission has ended because of excessive deferral of
over 24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo Frame is enabled)
if the Deferral Check (DC) bit in the GMAC Control register is set high.
UF: Underflow Error

When set, this bit indicates that the GMAC aborted the frame because data arrived late from
the Host memory. Underflow Error indicates that the DMA encountered an empty transmit
buffer while transmitting the frame. The transmission process enters the Suspended state
and sets both Transmit Underflow (Register5[5]) and Transmit Interrupt (Register5[0]).
DB: Deferred Bit

When set, this bit indicates that the GMAC defers before transmission because of the
presence of carrier. This bit is valid only in Half-Duplex mode.
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Field
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Ethernet subsystem
TDES1 in Enhanced Descriptor Structure

Table 50.
Field
Transmit descriptor word 1 (TDES1)
Description
31:29 Reserved
28:16 These bits indicate the second data buffer size in bytes. This field is not valid if TDES0[20] is
set.
12:0

These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores
this buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH
(TDES0[20]).
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RDES1 in Enhanced Descriptor Structure

Table 51.
Field
31
Receive descriptor word 1 (RDES1)
Description
DIC: Disable Interrupt on Completion
When set, this bit prevents setting the Status Registers RI bit (CSR5[6]) for the received
frame ending in the buffer indicated by this descriptor. This, in turn, disables the assertion of
the interrupt to Host due to RI for that frame.
30:29 Reserved
RBS2: Receive Buffer 2 Size These bits indicate the second data buffer size, in bytes. The
buffer size must be a multiple of 4, 8, or 16, depending on the bus widths (32, 64, or 128,
28:16 respectively), even if the value of RDES3 (buffer2 address pointer) is not aligned to bus
width. If the buffer size is not an appropriate multiple of 4, 8, or 16, the resulting behavior is
undefined. This field is not valid if RDES1[14] is set.
15
RER: Receive End of Ring

returns to the base address of the list, creating a descriptor ring.
14
RCH: Second Address Chained

address rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is
a dont care value. RDES1[15] takes precedence over RDES1[14].
13
Reserved
12:0

Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16,
depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address
pointer) is not aligned. When the buffer size is not a multiple of 4, 8, or 16, the resulting
behavior is undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next
descriptor depending on the value of RCH (bit 14).
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15:13 Reserved
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STi7105
12.7
MAC
12.7.1
General Description
The MAC operates in both Half-Duplex and Full-Duplex modes. When operating in HalfDuplex mode, the MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE
standard) and ANSI/IEEE 802.3. When operating in Full-Duplex mode, the MAC complies
with the IEEE 802.3x Full-Duplex operation.
The MAC provides programmable enhanced features designed to minimize host
supervision, bus utilization, and pre- or post-message processing. These features include
the ability to disable retries after a collision, dynamic FCS generation on a frame-by-frame
basis, automatic pad field insertion and deletion to enforce minimum frame size attributes,
and automatic retransmission and detection of collision frames.
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The primary attributes of the MAC block are:
Transmit and receive message data encapsulation
Framing (frame boundary delimitation, frame synchronization)
Error detection (physical medium transmission errors)
Media access management
Medium allocation (collision detection, except in Full-Duplex operation)
Contention resolution (collision handling, except in Full-Duplex operation)
Flow control during Full-Duplex mode
Decoding of Control frames (PAUSE command) and disabling the transmitter
Generation of Control frames
Interface to the PHY
Support of MII protocol to interface with an MII-based PHY
Support of RMII protocol to interface with an RMII-based PHY
Management Interface support on MII
12.7.2
Generation of PHY Management frames on MDC/MDI/MDO
Transmission
Transmit CRC Generator Module
The Transmit CRC Generator (CTX) module generates CRC for the FCS field of the
Ethernet frame. The encoding is defined by the following generating polynomial.
G (x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Transmit Checksum Offload Engine

The GMAC includes an Checksum Offload Engine (COE) to support checksum calculation
and insertion in the transmit path.
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TThe Ethernet Media Access Controller (MAC) incorporates the essential protocol
requirements for operating an Ethernet/IEEE 802.3-compliant node, and provides an
interface between the host subsystem and the Media Independent Interface (MII). The MAC
operates in either the 100-Mbps or 10-Mbps mode, based on the MII (25/2.5 MHz) clock or
overclocked MII (up to 75 MHz) for Home Networking applications.
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Ethernet subsystem
This module supports two types of checksum calculation and insertion. This checksum
engine can be controlled for each frame by setting the CIC bits (Bits 23:22 of TDES0).
Note:
The checksum for TCP, UDP, or ICMP is calculated over a complete frame, then inserted
into its corresponding header field. Due to this requirement, this function is enabled only
when the Transmit FIFO is configured for Store-and-Forward mode (that is, when the TSF bit
is set in GMAC_DMA_CTRL). If the core is configured for Threshold (cut-through) mode, the
Transmit COE is bypassed.
In IPv4 datagrams, the integrity of the header fields is indicated by the 16-bit Header
Checksum field (the eleventh and twelfth bytes of the IPv4 datagram). The COE detects an
IPv4 datagram when the Ethernet frames Type field has the value 0x0800 and the IP
datagrams Version field has the value 0x4. The input frames checksum field is ignored
during calculation and replaced with the calculated value. IPv6 headers do not have a
checksum field; thus, the COE does not modify IPv6 header fields.
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The result of this IP header checksum calculation is indicated by the IP Header Error status
bit in the Transmit status (Bit 16)..This status bit is also set whenever the values of the
Ethernet Type field and the IP header Version field are not consistent, or when the Ethernet
frame does not have enough data, as indicated by the IP header Length field. field. When
the COE detects this IP header error, it inserts an IPv4 Header checksum only if the
Ethernet Type field indicates an IPv4 payload.
TCP/UDP/ICMP Checksum Engine

The TCP/UDP/ICMP Checksum Engine processes the IPv4 or IPv6 header (including
extension headers) and determines whether the encapsulated payload is TCP, UDP, or
ICMP.
The checksum is calculated for the TCP, UDP, or ICMP payload and inserted into its
corresponding field in the header. This engine can work in the following two modes:
In the first mode, the TCP, UDP, or ICMPv6 pseudo-header is not included in the checksum
calculation and is assumed to be present in the input frames Checksum field. This engine
include the Checksum field in the checksum calculation, then replaces the Checksum field
with the final calculated checksum.
In the second mode, the engine ignores the Checksum field, includes the TCP, UDP, or
ICMPv6 pseudo-header data into the checksum calculation, and overwrites the checksum
field with the final calculated value.
The result of this operation is indicated by the Payload Checksum Error status bit in the
Transmit Status vector (Bit 12). When this engine detects the first type of error, it does not
modify the TCP, UDP, or ICMP header. For the second error type, it still inserts the
calculated checksum into the corresponding header field.
Note:
For non-TCP, -UDP, or -ICMP/ICMPv6 payloads, this checksum engine is bypassed and
nothing further is modified in the frame.
Fragmented IP frames (IPv4 or IPv6), IP frames with security features (such as an
authentication header or encapsulated security payload), and IPv6 frames with routing
headers are bypassed and not processed by this engine.
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IP Header Checksum Engine
Ethernet subsystem
12.7.3
STi7105
Reception
Receive CRC Module
The Receive CRC (CRX) interfaces to the RPE module to check for any CRC error in the
receiving frame.
This module calculates the 32-bit CRC for the received frame that includes the Destination
address field through the FCS field. The encoding is defined by the following generating
polynomial.
G (x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Two types of Receive Checksum Offload engine are available. Selecting only Enable IP
Checksum for Received frames instantiates the Type 1 engine, selecting Full Checksum
Offload instantiates the Type 2 engine. Type 2 is the recommended configuration, Type 1 is
retained for backward compatibility.
Type 1
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The application can enable IP header checksum checking and TCP/UDP checksum
offload by setting the GMAC Configuration registers IPC bit. This module calculates
the 16-bit ones complement of the Ethernet frames payload datas (DATA field) ones
complement sum. The payload data is assumed to start from byte 15 (19 for a VLANtagged frame) of the received Ethernet frame. This module only processes IPv4
datagrams, bypassing and not processing all other types (such as IPv6).
This module also compares the calculated IP checksum with the received frames IPv4
header checksum. Bytes 25 and 26 of the received Ethernet frame (29 and 30 for a
VLAN-tagged frame) are taken as the IP header checksum. The header checksum is
calculated against the header length field (20 bytes minimum). The result of the
comparison (pass or fail) is given to the RFC, which sets the appropriate bit in the
receive status word. If the Header Length field value is less than 5 or if the IP Version
field does not equal 4, an error is indicated for the IP header checksum.
The ones complement sum of the IP datagrams 16-bit payload is also calculated. The
start of the payload is considered to be the data after the IP header. If the data payload
ends with a non-aligned halfword, then a pad byte is added for the sum calculation. The
16-bit ones complement of the resultant sum is forwarded to the RFC module, which
inserts it into the data stream (towards the application) right after the FCS bytes (MS
byte first) of the Ethernet payload. This 16-bit sum helps the software check the
TCP/UDP header checksums faster. Note that this 16-bit sum (which is always
appended to the Ethernet frame in this mode) is invalid when the IP header checksum
bit shows an Error status.
Type 2
In this mode, both IPv4 and IPv6 frames in the received Ethernet frames are detected
and processed for data integrity. As with Type 1, you can enable this module by setting
the IPC bit in the GMAC Configuration register. The GMAC receiver identifies IPv4 or
IPv6 frames by checking for value 0x0800 or 0x86DD, respectively, in the received
Ethernet frames Type field. This identification applies to VLAN-tagged frames as well.
The Receive Checksum Offload engine calculates IPv4 header checksums and checks
that they match the received IPv4 header checksums. The result of this operation (pass
or fail) is given to the RFC module for insertion into the receive status word. The IP
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Ethernet subsystem
Header Error bit is set for any mismatch between the indicated payload type (Ethernet
Type field) and the IP header version, or when the received frame does not have
enough bytes, as indicated by the IPv4 headers Length field (or when fewer than 20
bytes are available in an IPv4 or IPv6 header).
This engine bypasses the payload of fragmented IP datagrams, IP datagrams with

security features, IPv6 routing headers, and payloads other than TCP, UDP or ICMP,
and resets the corresponding status.
In this configuration, the core does not append any payload checksum bytes to the
received Ethernet frames (as the Type 1 engine does).
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Address Filtering Module

The Address Filtering (AFM) module performs the destination and source address checking
function on all received frames and reports the address filtering status to the RFC module.
The address checking is based on different parameters (Frame Filter register) chosen by the
Application. These parameters are inputs to the AFM module as control signals, and the
AFM module reports the status of the address filtering based on the combination of these
inputs. The AFM module does not filter the receive frames by itself, but reports the status of
the address filtering (whether to drop the frame or not) to the RFC module. The AFM module
also reports whether the receiving frame is a multicast frame or a broadcast frame, as well
as the address filter status.
The AFM module probes the 8-bit receive data path between the RPE module and the RFC
module and checks the destination and source address field of each incoming packet. In MII
mode the module takes 14/26 clocks (from the start of frame) to compare the destination/
source address of the receiving frame. The AFM module gets the stations physical (MAC)
address and the Multicast Hash table from CSR module for address checking. The CSR
module provides the Frame Filter register parameters to AFM.
Unicast Destination Address Filter
The AFM supports up to 32 MAC addresses for unicast perfect filtering. If perfect
filtering is selected (HUC bit of Frame Filter register is reset), the AFM compares all 48
bits of the received unicast address with the programmed MAC address for any match.
Default MacAddr0 is always enabled, other addresses MacAddr1MacAddr31 are
selected with an individual enable bit. Each byte of these other addresses (MacAddr1
MacAddr31) can be masked during comparison with the corresponding received DA
byte by setting the corresponding Mask Byte Control bit in the register. This helps
group address filtering for the DA.
In Hash filtering mode (when HUC bit is set), the AFM performs imperfect filtering for
unicast addresses using a 64-bit Hash table. For hash filtering, the AFM uses the upper
6 bits CRC of the received destination address to index the content of the Hash table. A
value of 000000 selects bit 0 of the selected register, and a value of 111111 selects bit
63 of the Hash Table register. If the corresponding bit (indicated by the 6-bit CRC) is set
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This engine also identifies a TCP, UDP or ICMP payload in the received IP datagrams
(IPv4 or IPv6) and calculates the checksum of such payloads properly, as defined in the
TCP, UDP, or ICMP specifications. This engine includes the TCP/UDP/ICMPv6 pseudoheader bytes for checksum calculation and checks whether the received checksum
field matches the calculated value. The result of this operation is given as a Payload
Checksum Error bit in the receive status word. This status bit is also set if the length of
the TCP, UDP, or ICMP payload does not tally to the expected payload length given in
the IP header.
Ethernet subsystem
STi7105
to 1, the unicast frame is said to have passed the Hash filter; otherwise, the frame has
failed the Hash filter.
Multicast Destination Address Filter
In Hash filtering mode, the AFM performs imperfect filtering using a 64-bit Hash table.
For hash filtering, the AFM uses the upper 6 bits CRC of the received multicast address
to index the content of the Hash table. A value of 000000 selects bit 0 of the selected
register and a value of 111111 selects bit 63 of the Hash Table register.
If the corresponding bit is set to 1, then the multicast frame is said to have passed the
Hash filter; otherwise, the frame has failed the Hash filter.
Hash or Perfect Address Filter
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The DA filter can be configured to pass a frame when its DA matches either the Hash
filter or the Perfect filter by setting the HPF bit of the Frame Filter register and setting
the corresponding HUC or HMC bits. This configuration applies to both unicast and
multicast frames. If the HPF bit is reset, only one of the filters (Hash or Perfect) is
applied to the received frame.
Broadcast Address Filter
The AFM doesnt filter any broadcast frames in the default mode. However, if the
GMAC is programmed to reject all broadcast frames by setting the DBF bit in the Frame
Filter register, the DAF module asserts the Filter fail signal to RFC, whenever a
broadcast frame is received. This will tell the RFC module to drop the frame.
Unicast Source Address Filter
The GMAC can also perform a perfect filtering based on the source address field of the
received frames. By default, the AFM compares the SA field with the values
programmed in the SA registers. The MAC Address registers [1:31] can be configured
to contain SA instead of DA for comparison, by setting bit 30 of the corresponding
Register. Group filtering with SA is also supported. The frames that fail the SA Filter are
dropped by the GMAC if the SAF bit of Frame Filter register is set. Otherwise, the result
of the SA filter is given as a status bit in the Receive Status word.
When SAF bit is set, the result of SA Filter and DA filter is ANDed to decide whether
the frame needs to be forwarded. This means that either of the filter fail result will drop
the frame and both filters have to pass in-order to forward the frame to the application.
Inverse Filtering Operation
For both Destination and Source address filtering, there is an option to invert the filtermatch result at the final output. These are controlled by the DAIF and SAIF bits of the
Frame Filter register respectively. The DAIF bit is applicable for both Unicast and
Multicast DA frames. The result of the unicast/multicast destination address filter is
inverted in this mode. Similarly, when the SAIF bit is set, the result of unicast SA filter is
reversed.
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The GMAC can be programmed to pass all multicast frames by setting the PM bit in the
Frame Filter register. If the PM bit is reset, the AFM performs the filtering for multicast
addresses based on the HMC bit of Frame Filter register. In Perfect Filtering mode, the
multicast address is compared with the programmed MAC Destination Address
registers (131). Group address filtering is also supported.
STi7105
Ethernet subsystem
Table 52. and Table 53. summarize the Destination and Source Address filtering based
on the type of frames received.
Frame
type
PR
HPF
Broadcast
Unicast
Confidential
Destination address filtering
Multicast
HUC DAIF HMC
PM
DB
Pass
Pass
Fail
Pass all frames
Pass on Perfect/Group filter match
Fail on Perfect/Group filter match
Pass on Hash filter match
Fail on Hash filter match
Pass on Hash or Perfect/Group filter

match
Fail on Hash or Perfect/Group filter

match
Pass all frames
Pass all frames
Pass on Perfect/Group filter match

and drop PAUSE control frames if
PCF = 0x
Pass on Hash filter match and drop

PAUSE control frames if PCF = 0x
Pass on Hash or Perfect/Group filter

match and drop PAUSE control
frames if PCF = 0x
Fail on Perfect/Group filter match and

drop PAUSE control frames if PCF =
0x
Fail on Hash filter match and drop

PAUSE control frames if PCF = 0x
Fail on Hash or Perfect/Group filter

match and drop PAUSE control
frames if PCF = 0x
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Table 52.
Ethernet subsystem
Frame
type
Source address filtering

PR
SAIF
SAF
Pass all frames
Pass status on Perfect/Group filter match but do not drop frames

that fail.
Fail status on Perfect/Group filter match but do not drop frame
Pass on Perfect/Group filter match and drop frames that fail
Fail on Perfect/Group filter match and drop frames that fail
Unicast
12.7.4
SA filter operation
RMII Block
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The Reduced Media Independent Interface (RMII) specification is intended to reduce the pin
count between Ethernet PHYs and Ethernet MACs. According to the IEEE 802.3u standard,
an MII contains 16 pins for data and control. In devices incorporating multiple MAC or PHY
interfaces (such as switches), the number of pins adds significant cost by increasing the port
count. The RMII specification addresses the above problem by reducing the pin count to 7
per port, a 62.5% decrease in pin count.
The RMII module is instantiated between the MAC and the PHY. This helps translate the
MAC'S MI interface into the RMI interface.
The RMII block has the following characteristics:
It is capable of supporting 10 Mbps and 100 Mbps rates
Three clock references are sourced from an external source
It provides independent two-bit wide transmit and receive paths
Figure 48 shows the position of the RMII block relative to the MAC and RMII PHY. The RMII
block is placed in front of MAC to translate the MII signals to RMII signals. This RMII block
contains the MII signals on one side and RMII signals on the PHY side.
Figure 48. RMII Block Diagram
MAC
block
12.7.5
RMII
block
MII
RMII
RMII PHY
block
MAC management counters

The MMC module maintains a set of registers for gathering statistics on the received and
transmitted frames. These include a control register for controlling the behavior of the
registers, two 32-bit registers containing interrupts generated (receive and transmit), and
two 32-bit registers containing masks for the Interrupt register (receive and transmit).
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Table 53.
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Ethernet subsystem
The Receive MMC counters are updated for frames that are passed by the Address Filter
(AFM) block. Statistics of frames that are dropped by the AFM module are not updated
unless they are runt frames of less than 6 bytes (DA bytes are not received fully).
The MMC module gathers statistics on encapsulated IPv4, IPv6, TCP, UDP, or ICMP
payloads in received Ethernet frames.
Address Assignments
tx as a prefix or suffix indicates counters associated with transmission
rx as a prefix or suffix indicates counters associated with reception
_g as a suffix indicates registers that count good frames only
_gb as a suffix indicates registers that count frames regardless of whether they are
good or bad
Confidential
Transmitted frames are considered Bad (and are thus aborted) if one or more of the
following conditions exists:
Jabber Timeout
No Carrier/Loss of Carrier
Late Collision
Frame Underflow error
Received frames are considered Bad if one of the following conditions exists:
CRC error
Length error
Watchdog timeout
Missed frame error
Maximum frame size is dependent on the frame type, as follows;
12.7.6
Untagged frame maxsize = 1518
VLAN Frame maxsize = 1522
Jumbo Frame maxsize = 9018
JumboVLAN Frame maxsize = 9022
Power Management block

The power management (PMT) mechanisms support the reception of network (remote)
wake-up frames and Magic Packet frames. PMT does not perform the clock gate function,
but generates interrupts for wake-up frames and Magic Packets received by the GMAC. The
PMT block sits on the receiver path of the GMAC and is enabled with remote wake-up frame
enable and Magic Packet enable. These enables are in the PMT Control and Status register
and are programmed by the Application.
When the power down mode is enabled in the PMT, then all received frames are dropped by
the core and they are not forwarded to the application. The core comes out of the power
down mode only when either a Magic Packet or a Remote Wake-up frame is received and
the corresponding detection is enabled.
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The MMC register naming convention is as follows:
Ethernet subsystem
STi7105
Remote Wake-Up Frame Filter Register

The register wkupfmfilter_reg, address (028H), loads the Wake-up Frame Filter register. To
load values in a Wake-up Frame Filter register, the entire register (wkupfmfilter_reg) must be
written. The wkupfmfilter_reg register is loaded by sequentially loading the eight register
values in address (028) for wkupfmfilter_reg0, wkupfmfilter_reg1, ... wkupfmfilter_reg7,
respectively. wkupfmfilter_reg is read in the same way.
wkupfmfilter_reg0
Filter 0 Byte Mask
wkupfmfilter_reg1
Filter 1 Byte Mask
wkupfmfilter_reg2
Filter 2 Byte Mask
wkupfmfilter_reg3
Filter 3 Byte Mask
wkupfmfilter_reg4
RSVD
Confidential
wkupfmfilter_reg5
Filter 3
Command
Filter 3 Offset
RSVD
Filter 2
Command
Filter 2 Offset
RSVD
Filter 1
Command
Filter 1 Offset
RSVD
Filter 0
Command
Filter 0 Offset
wkupfmfilter_reg6
Filter 1 CRC - 16
Filter 0 CRC - 16
wkupfmfilter_reg7
Filter 3 CRC - 16
Filter 2 CRC - 16
Filter i Byte Mask

This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in
order to determine whether or not the frame is a wake-up frame. The MSB (thirty-first
bit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is
set, then Filter i Offset + j of the incoming frame is processed by the CRC block;
otherwise Filter i Offset + j is ignored.
Filter i Command
This 4-bit command controls the filter i operation. Bit 3 specifies the address type,
defining the patterns destination address type. When the bit is set, the pattern applies
to only multicast frames; when the bit is reset, the pattern applies only to unicast frame.
Bit 2 and Bit 1 are reserved. Bit 0 is the enable for filter i; if Bit 0 is not set, filter i is
disabled.
Filter i Offset
This register defines the offset (within the frame) from which the frames are examined
by filter i. This 8-bit pattern-offset is the offset for the filter i first byte to examined. The
minimum allowed is 12.
Filter i CRC-16
This register contains the CRC_16 value calculated from the pattern, as well as the
byte mask programmed to the wake-up filter register block.
258/454
8137791 RevA
Figure 49. Wake-Up frame filter register
STi7105
Ethernet subsystem
Remote Wake-Up Frame Detection

When the GMAC is in sleep mode and the remote wake-up bit is enabled in PMT Control
and Status register (002C), normal operation is resumed after receiving a remote wake-up
frame. The Application writes all eight wake-up filter registers, by performing a sequential
Write to address (0028). The Application enables remote wake-up by writing a 1 to bit 2 of
the PMT Control and Status register.
Confidential
Filter_offset (minimum value 12) determines the offset from which the frame is to be
examined. Filter Byte Mask determines which bytes of the frame must be examined. The
thirty-first bit of Byte Mask must be set to zero.
The remote wake-up CRC block determines the CRC value that is compared with Filter
CRC-16. The wake-up frame is checked only for length error, FCS error, dribble bit error,
collision, and to ensure that it is not a runt frame. Even if the wake-up frame is more than
512 bytes long, if the frame has a valid CRC value, it is considered valid. Wake-up frame
detection is updated in the PMT Control and Status register for every remote Wake-up frame
received. A PMT interrupt to the Application triggers a Read to the PMT Control and Status
register to determine reception of a wake-up frame.
Magic Packet Detection

The Magic Packet frame is based on a method that uses Advanced Micro Devices Magic
Packet technology to power up the sleeping device on the network. The GMAC receives a
specific packet of information, called a Magic Packet, addressed to the node on the network.
Only Magic Packets that are addressed to the device or a broadcast address will be checked
to determine whether they meet the wake-up requirements. Magic Packets that pass the
address filtering (unicast or broadcast) will be checked to determine whether they meet the
remote Wake-on-LAN data format of 6 bytes of all ones followed by a GMAC Address
appearing 16 times.
The Application enables Magic Packet wake-up by writing a 1 to Bit 3 of the PMT Control
and Status register. The PMT block constantly monitors each frame addressed to the node
for a specific Magic Packet pattern. Each frame received is checked for a
48hFF_FF_FF_FF_FF_FF pattern following the destination and source address field. The
PMT block then checks the frame for 16 repetitions of the GMAC address without any
breaks or interruptions. In case of a break in the 16 repetitions of the address, the
48hFF_FF_FF_FF_FF_FF pattern is scanned for again in the incoming frame. The 16
repetitions can be anywhere in the frame, but must be preceded by the synchronization
stream (48hFF_FF_FF_FF_FF_FF). The device will also accept a multicast frame, as long
as the 16 duplications of the GMAC address are detected.
For example, if the MAC address of a node is 48'h00_11_22_33_44_55, then the GMAC
scans for the data sequence:
Destination Address Source Address .. FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
8137791 RevA
259/454
PMT supports four programmable filters that allow support of different receive frame
patterns. If the incoming frame passes the address filtering of Filter Command, and if Filter
CRC-16 matches the incoming examined pattern, then the wake-up frame is received.
Ethernet subsystem
STi7105
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
CRC
Magic Packet detection is updated in the PMT Control and Status register for Magic Packet
received. A PMT interrupt to the Application triggers a read to the PMT CSR to determine
whether a Magic Packet frame has been received.
Power-Down and Wake-up sequence
12.7.7
1.
Disable the Transmit DMA (if applicable) and wait for any previous frame transmissions
to complete. These transmissions can be detected when Transmit Interrupt
(GMAC_DMA_STA[0]) is received.
2.
Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the
MAC Configuration register.
3.
Wait until the Receive DMA empties all the frames from the Rx FIFO (a software timer
may be required).
4.
Enable Power-Down mode by appropriately configuring the PMT registers.
5.
Enable the MAC Receiver and enter Power-Down mode.
6.
On receiving a valid wake-up frame, the GMAC exits Power-Down mode.
7.
On receiving the interrupt, the system enables the application.
8.
Read the PMT Status register to clear the interrupt, then enable the other modules in
the system and resume normal operation.
Station Management Agent

The Station Management Agent module allows the Application to access any PHY registers
through a 2-wire Station Management interface (MIM). The interface supports accessing up
to 32 PHYs.
The Application can select one of the 32 PHYs and one of the 32 registers within any PHY
and send control data or receive status information. Only one register in one PHY can be
addressed at any given time. For more details on the communication from the Application to
the PHYs, refer to the Reconciliation Sublayer and Media Independent Interface
Specifications section of the IEEE 802.3z specification, 1000BASE Ethernet. The
Application sends the control data to the PHY and receives status information from the PHY
through the SMA module.
Functions
The GMAC initiates the Management Write/Read operation. The clock ETHMII_PHY is a
divided clock from the Application clock CLK_ETHERNET_PHY.
The frame structure on the MDIO line is shown below.
IDLE
PREAMBLE
START
OPCODE
PHY
ADDR
REG
ADDR
TA
DATA
where:
260/454
IDLE:
PREAMBLE: 32 continuous bits of value 1
The mdio line is three-state; there is no clock on ETHMII_MDC
8137791 RevA
IDLE
Confidential
The recommended power-down and wake-up sequence is as follows:
STi7105
Ethernet subsystem
START:
Start-of-frame is 201
OPCODE:
2b10 for Read and 2b01 for Write
PHY ADDR: 5-bit address select for one of 32 PHYs
REG ADDR: Register address in the selected PHY
TA:
Turnaround is 2bZ0 for Read and 2b10 for Write
DATA:
Any 16-bit value. In a Write operation, the GMAC drives mdio; in a

Read operation, PHY drives it.
Confidential
When the user sets the MII Write and Busy bits (see MII Address Register,
GMAC_MII_ADDR), the GMAC CSR module transfers the PHY address, the register
address in PHY, and the write data (GMAC_MII_DATA) to the SMA to initiate a Write
operation into the PHY registers. At this point, the SMA module starts a Write operation on
the MII Management Interface using the Management Frame Format. The application
should not change the MII Address register contents or the MII Data register while the
transaction is ongoing. Write operations to the MII Address register or the MII Data Register
during this period are ignored (the Busy bit is high), and the transaction is completed without
any error on the MCI interface.
After the Write operation has completed, the SMA indicates this to the CSR which then
resets the Busy bit. The SMA module divides the CSR (Application) clock with the clock
divider programmed (CR bits of MII Address Register) to generate the MDC clock for this
interface. The GMAC drives the MDIO line for the complete duration of the frame. The frame
format for the Write operation is as follows:
IDLE
PREAMBLE
START
OPCODE
PHY
ADDR
REG
ADDR
TA
DATA
IDLE
1111...11
01
01
AAAAA
RRRRR
10
DDD...DDD
MII Management Read Operation

When the user sets the MII Busy bit (see MII Address Register, GMAC_MII_ADDR) with the
MII Write bit as 0, the GMAC CSR module transfers the PHY address and the register
address in PHY to the SMA to initiate a Read operation in the PHY registers. At this point,
the SMA module starts a Read operation on the MII Management Interface using the
Management Frame Format. The application should not change the MII Address register
contents or the MII Data register while the transaction is ongoing. Write operations to the MII
Address register or MII Data Register during this period are ignored (the Busy bit is high)
and the transaction completed without any error on the MCI interface.
After the Read operation has completed, the SMA indicates this to the CSR, which then
resets the Busy bit and updates the MII Data register with the data read from the PHY. The
SMA module divides the CSR (Application) clock with the clock divider programmed (CR
bits of MII Address Register) to generate the MDC clock for this interface. The GMAC drives
the MDIO line for the complete duration of the frame except during the Data Fields when the
PHY is driving the MDIO line. The frame format for the Read operation is as follows:
IDLE
PREAMBLE
START
OPCODE
PHY
ADDR
REG
ADDR
TA
DATA
IDLE
1111...11
01
10
AAAAA
RRRRR
Z0
DDD...DDD
8137791 RevA
261/454
MII Management Write Operation
Ethernet registers
STi7105
13
Ethernet registers
13.1
Register addresses
Caution:
Register addresses are provided as:
The ETHBaseAddress is: 0xFD11 0000
Confidential
The GMAC has the ability to have 32 MAC addresses, with each address requiring two
registers (Hi and Lo). The registers for the addresses are located in two blocks within the
memory map . The registers for MAC address0 has a unique set of characteristics, the
remaining registers (1-31) have identical characteristics. For simplicity, and to ensure Spirit
Compliance, these registers are described once within each address block, with an equation
used to calculate the address for each register:
<Base address> + base offset + (<iterator> - <first value>) * <step> (where <iterator> =
<first value> to <last value>)
where:
<Base address> = base address of IP block
base offset = offset sub-block being mapped
(<iterator> - <first value>) * <step> = step calculation for each register in the block, with
<iterator> being the range of register name values of the block and <step> being the
offset to the next register of the same type.
To ensure the correct incremental steps for the address of each register, the base offset of
the first register provides the datum and therefore has no step.
Note: There is no step offset from the base offset for the first address, hence the overall
iterator for that address must be 0. Similarly, there is a single step from the base
offset to arrive at the second address, so the overall iterator must 1.
The (<iterator> ) calculation provides the decrement of the register name value to
produce the correct multiplier for the <step>.
As examples, the equation for the registers for Hi addresses 1 to 15 is:
ETHBaseAddress + 0x004C + (one - 1) * 0x8 (where one = 1 to 15)
and the equation for the registers for Lo addresses 16 to 31 is:
ETHBaseAddress + 0x0804 + (sixteen - 16) * 0x8 (where sixteen = 16 to 31)
where:
262/454
0x004C is the base address offset for the high register for address 1, and 0x0804 is the
base address offset for the low register for address 16.
the string iterator one identifies addresses 1 to 15, the string iterator sixteen identifies
addresses 16 to 31.
8137791 RevA
ETHBaseAddress + offset.
STi7105
Ethernet registers
Table 54.
Address
offset
Register summary table

Register
Description
Page
0x0000
GMAC_CFG
GMAC configuration register

Operation mode register for the GMAC
page 268
0x0004
GMAC_FRAME
GMAC frame filter

Contains the frame filtering controls
page 270
0x0008
GMAC_HASH_TBL_HI
Multicast hash table high register

Contains the upper 32 bits of the Multicast
hash table
page 272
0x000C
GMAC_HASH_TBL_LO
Multicast hash table low register

Contains the lower 32 bits of the Multicast
hash table
page 273
GMAC_MII_ADDR
MII Address register

Controls the management cycles to the
external PHY through the management
interface
page 273
0x0014
GMAC_MII_DATA
The MII Data register stores Write data to

be written to the PHY register located at the
page 274
address specified in register
GMAC_MII_ADDR.
0x0018
GMAC_FLOW_CTRL
Flow control register

Controls the generation of control frames
page 275
0x001C
GMAC_VLAN_TAG
VLAN1 tag register

Length/type field register to identify VLAN
type frames
page 276
0x0020
GMAC_VERSION
Version register
Identifies the version of the Core
page 277
0x0024
RESERVED
RESERVED
0x0028
GMAC_CSR_WAKE_UP
Wake up control and status register

Contains data pertaining to the GMACs
remote wake-up status and capabilities
0x002C
GMAC_PMT_CTRL
PMT control and status register

page 279
Available when the PMT module is selected
Confidential
0x0010
page 277
0x0030 to
RESERVED
0x0034
RESERVED
0x0038
GMAC_INT_STA
Interrupt register
Contains the interrupt status
page 280
0x003C
GMAC_INT_MASK
Interrupt mask register

Contains the masks for generating
interrupts
page 281
GMAC address registers (0-15)
8137791 RevA
263/454
GMAC control and status registers
Ethernet registers
Address
offset
Register
Description
Page
0x0040
GMAC_ADDR0_HI
MAC address0 high register

Contains the upper 16 bits of the MAC
address
page 282
0x0044
GMAC_ADDR0_LO
MAC address0 low register

Contains the lower 32 bits of the MAC
address
page 282
0x0048,
0x0050,
0x0058,
...
0x00B8
GMAC_ADDRone_HI
MAC address high registers

These contain the upper 16 bits of the MAC page 283
addresses 1 to 15
0x004C,
0x0054,
0x005C,
...
0x00BC
GMAC_ADDRone_LO
MAC address low registers

These contain the lower 32 bits of the MAC page 283
addresses 1 to 15
0x00C0
to
0x00FC
RESERVED
RESERVED
MMC registers
264/454
0x0100
GMMC_CTRL
GMAC MC control register
page 284
0x0104
GMMC_INTR_RX
GMAC MC receive interrupt
page 284
0x0108
GMMC_INTR_TX
GMAC MC transmit interrupt
page 286
0x010C
GMMC_INTR_MSK_RX
GMAC MC receive interrupt mask
page 288
0x0110
GMMC_INTR_MSK_TX
GMAC MC transmit interrupt mask
page 290
0x0114
TXOCTETCOUNT_GB
Number of bytes transmitted
page 291
0x0118
TXFRAMECOUNT_GB
Number of good and bad frames

transmitted
page 292
0x011C
TXBROADCASTFRAMES_G
Number of good broadcast frames

transmitted
page 292
0x0120
TXMULTICASTFRAMES_G
Number of good multicast frames

transmitted
page 292
0x0124
TX64OCTETS_GB

transmitted with length 64 bytes
page 293
0x0128
TX65TO127OCTETS_GB

transmitted with length between 65 and 127 page 293
(inclusive) bytes
0x012C
TX128TO255OCTETS_GB

transmitted with length between 128 and
255 (inclusive) bytes
8137791 RevA
page 293
Confidential
Table 54.
STi7105
STi7105
Ethernet registers
Address
offset
Register
Description
Page
0x0130
TX256TO511OCTETS_GB

511 (inclusive) bytes
page 294
0x0134
TX512TO1023OCTETS_GB

1,023 (inclusive) bytes
page 294
0x0138
TX1024TOMAXOCTETS_GB

transmitted with length between 1,024 and
maxsize (inclusive) bytes
page 294
0x013C
TXUNICASTFRAMES_GB
Number of good and bad unicast frames

transmitted
page 295
0x0140
TXMULTICASTFRAMES_GB
Number of good and bad multicast frames

transmitted
page 295
0x0144
TXBROADCASTFRAMES_GB
Number of good and bad broadcast frames

page 295
transmitted
0x0148
TXUNDERFLOWERROR
Number of frames aborted due to frame

underflow error
page 296
0x014C
TXSINGLECOL_G
Number of successfully transmitted frames

after a single collision in Half-duplex mode
page 296
0x0150
TXMULTICOL_G

after more than a single collision in Halfduplex mode
page 296
0x0154
TXDEFERRED

after a deferral in Half-duplex mode
page 297
0x0158
TXLATECOL
Number of frames aborted due to late

collision error
page 297
0x015C
TXEXCESSCOL
Number of frames aborted due to excessive

page 297
(16) collision errors
0x0160
TXCARRIERERROR
Number of frames aborted due to carrier

sense error
0x0164
TXOCTETCOUNT_G
Number of bytes transmitted in good frames

page 298
only
0x0168
TXFRAMECOUNT_G
Number of good frames transmitted
0x016C
TXEXCESSDEF

page 298
deferral error
0x0170
TXPAUSEFRAMES
Number of good PAUSE frames transmitted page 298
0x0174
TXVLANFRAMES_G
Number of good VLAN frames transmitted
0x0178 to
RESERVED
0x017C
RESERVED
0x0180
Number of good and bad frames received
RXFRAMECOUNT_GB
8137791 RevA
page 297
page 298
page 299
page 299
265/454
Confidential
Table 54.
Ethernet registers
266/454
Address
offset
Register
Description
Page
0x0184
RXOCTETCOUNT_GB
Number of bytes received in good and bad

frames
page 299
0x0188
RXOCTETCOUNT_G
Number of bytes received only in good

frames
page 299
0x018C
RXBROADCASTFRAMES_G
Number of good broadcast frames received page 300
0x0190
RXMULTICASTFRAMES_G
Number of good multicast frames received
page 300
0x0194
RXCRCERROR
Number of frames received with CRC error
page 300
0x0198
RXALIGNMENTERROR
Number of frames received with alignment

(dribble) error
page 300
0x019C
RXRUNTERROR
Number of frames received with runt (<64

bytes and CRC error) error
page 301
0x01A0
RXJABBERERROR
Number of giant frames received with length

greater than 1,518 bytes and with CRC
page 301
error
0x01A4
RXUNDERSIZE_G
Number of frames received, with length less

page 301
than 64 bytes, without any errors
0x01A8
RXOVERSIZE_G
Number of frames received, with length

greater than the maxsize, without errors
page 302
0x01AC
RX64OCTETS_GB

with length 64 bytes
page 302
0x01B0
RX65TO127OCTETS_GB

with length between 65 and 127 (inclusive)
bytes
page 302
0x01B4
RX128TO255OCTETS_GB

with length between 128 and 255 (inclusive) page 303
bytes
0x01B8
RX256TO511OCTETS_GB

with length between 256 and 511 (inclusive) page 303
bytes
0x01BC
RX512TO1023OCTETS_GB

with length between 512 and 1,023
(inclusive) bytes
page 303
0x01C0
RX1024TOMAXOCTETS_GB

with length between 1,024 and maxsize
(inclusive) bytes
page 304
0x01C4
RXUNICASTFRAMES_G
Number of good unicast frames received
page 304
0x01C8
RXLENGTHERROR
Number of frames received with length

error, for all frames with valid length field
page 304
0x01CC
RXOUTOFRANGETYPE
Number of frames received with length field

page 305
not equal to the valid frame size
0x01D0
RXPAUSEFRAMES
Number of good and valid PAUSE frames

received
8137791 RevA
page 305
Confidential
Table 54.
STi7105
STi7105
Ethernet registers
Address
offset
Register
Description
Page
0x01D4
RXFIFOOVERFLOW
Number of missed received frames due to

FIFO overflow
page 305
0x01D8
RXVLANFRAMES_GB
Number of good and bad VLAN frames

received
page 306
0x01DC
RXWATCHDOGERROR
Number of frames received with error due to

page 306
watchdog timeout error
0x01E0
to
0x01FC
RESERVED
RESERVED
0x0200
GMMC_IPC_INTR_MSK_RX
GMAC MC receive checksum offload

interrupt mask
0x0204
RESERVED
RESERVED
0x0208
GMMC_IPC_INTR_RX
GMAC MC receive checksum offload

interrupt
0x020C
to
0x07FC
RESERVED
RESERVED
page 306
page 309
GMAC address registers (16-31)

0x0800,
0x0808,
0x0810,
...
0x0878
GMAC_ADDRsixteen_HI
MAC address high registers

These contain the upper 16 bits of the MAC page 310
addresses 16 to 31
0x0804,
0x080C,
0x0814,
...
0x087C
GMAC_ADDRsixteen_LO
MAC address low registers

These contain the lower 32 bits of the MAC page 311
addresses 16 to 31
0x0880 to
RESERVED
0x0FFC
RESERVED
DMA registers
0x1000
GMAC_BUS_MODE
Bus mode register
page 312
0x1004
GMAC_XMT_POLL_DEMAND
Transmit poll demand register
page 314
0x1008
GMAC_RCV_POLL_DEMAND
Receive poll demand register
page 314
0x100C
GMAC_RCV_BASE_ADDR
Receive descriptor list address register
page 315
0x1010
GMAC_XMT_BASE_ADDR
Transmit descriptor list address register
page 315
0x1014
GMAC_DMA_STA
Status register
page 316
0x1018
GMAC_DMA_CTRL
Control (operation mode register
page 320
0x101C
GMAC_DMA_INT_EN
(CSR7). Interrupt enable register
page 323
8137791 RevA
267/454
Confidential
Table 54.
Ethernet registers
Register
Description
Page
0x1020
GMAC_MISSED_FRAME_CTR
(CSR8). Missed frame counter (receive

only)
page 325
0x1024 to
RESERVED
0x1044
RESERVED
0x1048
GMAC_CUR_TX_DESC
(CSR20). Current host transmit buffer

address
page 326
0x104C
GMAC_CUR_RX_DESC
(CSR21). Current host receive buffer

address
page 327
0x1050
GMAC_CUR_TX_BUF_ADDR
(CSR20). Current host transmit buffer

address
page 327
0x1054
GMAC_CUR_RX_BUF_ADDR
(CSR21). Current host receive buffer

address
page 327
GMAC control and status registers
Address:
ETHBaseAddress + 0x0000
Type:
RW
Reset:
0x0000
Description:
The GMAC Configuration register establishes Rx and Tx operating modes.
0
RESERVED
TE
RE
DC
BL
DM
IPC
LM
RESERVED
RESERVED
PS
DCRS
IFG
JE
RESERVED
WD
JD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ACS
GMAC configuration register

RESERVED
GMAC_CFG
[31:24] RESERVED
[23] WD: Watchdog Disable
When this bit is set, the GMAC disables the watchdog timer on the receiver, and can receive
frames of up to 16,384 bytes.
When this bit is reset, the GMAC allows no more than 2,048 bytes (10,240 if JE is set high) of the
frame being received and cuts off any bytes received after that.
[22] JD: Jabber Disable
When this bit is set, the GMAC disables the jabber timer on the transmitter, and can transfer
frames of up to 16,384 bytes.
When this bit is reset, the GMAC cuts off the transmitter if the application sends out more than
2,048 bytes of data (10,240 if JE is set high) during transmission.
[21] RESERVED
268/454
8137791 RevA
Address
offset
DR
13.2
RESERVED
Confidential
Table 54.
STi7105
STi7105
Ethernet registers
Confidential
[19:17] IFG: Inter-Frame Gap

These bits control the minimum IFG between frames during transmission:
000: 96 bit times
001: 88 bit times
010: 80 bit times
.
111: 40 bit times
In Half-Duplex mode, the minimum IFG that can be configured is for 64 bit times (IFG = 100) only.
Lower values are not considered. In 1000-Mbps mode, the minimum IFG supported is 64 bit
times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other
system configurations.
[16] DCRS: Disable Carrier Sense During Transmission
When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame
transmission in Half-Duplex mode. This request results in no errors generated due to Loss of
Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter
generates such errors due to Carrier Sense and will even abort the transmissions.
This bit is reserved (and RO) when the core is selected for Full-Duplex-only operation during core
configuration.
[15] PS: Port Select
Preset to 1 for MII mode during core configuration.
[14] RESERVED
[13] RESERVED
[12] LM: Loop-back Mode
When this bit is set, the GMAC operates in loop-back mode at MII. The MII Receive clock input
(clk_rx_i) is required for the loopback to work properly, as the Transmit clock is not looped-back
internally.
[11] DM: Duplex Mode
When this bit is set, the GMAC operates in a Full-Duplex mode where it can transmit and receive
simultaneously. This bit is RO with default value of 1'b1 in Full- Duplex-only configuration.
[10] IPC: Checksum Offload
When this bit is set, the GMAC calculates the 16-bit 1s complement of the 1s complement sum
of all received Ethernet frame payloads (16-bit). It also checks whether the IPv4 Header
checksum (assumed to be bytes 25-26 or 29-30 (VLAN-tagged) of Received Ethernet frame) is
correct for the received frame and gives the status in the Receive Status Word. The GMAC Core
also appends the 16-bit Checksum calculated for the payload of the IP header datagram (bytes
after the IPv4 header) and appends it to the Ethernet frame transferred to the application.
When this bit is reset, then this function is disabled. This bit is reserved (RO with default value) if
IP Checksum Offload feature is not enabled during coreKit configuration. .
[9] DR: Disable Retry
When this bit is set, the GMAC will attempt only 1 transmission. When a collision occurs on the
MII, the GMAC will ignore the current frame transmission and report a Frame Abort with
excessive collision error in the transmit frame status.
When this bit is reset, the GMAC will attempt retries based on the settings of BL. This bit is
applicable only to Half-Duplex mode and is reserved (RO with default value) in Full-Duplex-only
configuration.
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[20] JE: Jumbo Frame Enable

When this bit is set, GMAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged
frames) without reporting a giant frame error in the receive frame status.
Ethernet registers
STi7105
[8] RESERVED
[7] ACS: Automatic Pad/CRC Stripping
When this bit is set, the GMAC strips the Pad/FCS field on incoming frames only if the lengths
field value is less than or equal to 1,500 bytes. All received frames with length field greater than
or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.
When this bit is reset, the GMAC will pass all incoming frames to the Host unmodified.
Confidential
The Back-Off limit determines the random integer number (r) of slot time delays (4,096
bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the GMAC waits before
rescheduling a transmission attempt during retries after a collision. This bit is
applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only
configuration:
00: k = min (n, 10)
01: k = min (n, 8)
10: k = min (n, 4)
11: k = min (n, 1),
where n = retransmission attempt.
The random integer r takes the value in the range 0 r < 2k.
[4] DC: Deferral Check
When this bit is set, the deferral check function is enabled in the GMAC. The GMAC will issue a
Frame Abort status, along with the excessive deferral error bit set in the transmit frame status
when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps
mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled
in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the
transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal
on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then
transmits, collides, backs off, and then has to defer again after completion of back-off, the
deferral timer resets to 0 and restarts.
When this bit is reset, the deferral check function is disabled and the GMAC defers until the CRS
signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in FullDuplex-only configuration.
[3] TE: Transmitter Enable
When this bit is set, the transmit state machine of the GMAC is enabled for transmission on the
MII. When this bit is reset, the GMAC transmit state machine is disabled after the completion of
the transmission of the current frame, and will not transmit any further frames.
[2] RE: Receiver Enable
When this bit is set, the receiver state machine of the GMAC is enabled for receiving frames from
the MII. When this bit is reset, the GMAC receive state machine is disabled after the completion
of the reception of the current frame, and will not receive any further frames from the MII.
[1:0] RESERVED
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8137791 RevA
0
RESERVED
TE
RE
RESERVED
DC
ASTP
Address:
7
BOLMT
DRTY
RA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
GMAC frame filter register description

RESERVED
GMAC_FRAME
[6:5] BL: Back-Off Limit
Ethernet registers
Type:
RW
Reset:
0x0000
Description:
The GMAC Frame Filter register contains the filter controls for receiving frames.
Some of the controls from this register go to the address check block of the GMAC,
which performs the first level of address filtering. The second level of filtering is
performed on the incoming frame, based on other controls such as Pass Bad Frames
and Pass Control Frames.
[31] RA: Receive All

When this bit is set, the GMAC Receiver module passes to the Application all frames received
irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated
(pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the
Receiver module passes to the Application only those frames that pass the SA/DA address filter.
Confidential
[30:11] RESERVED
[10] HPF: Hash or Perfect Filter
When set, this bit configures the address filter to pass a frame if it matches either the perfect
filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set,
the frame is passed only if it matches the Hash filter.
This bit is reserved (and RO) if the Hash filter is not selected during core configuration.
[9] SAF: Source Address Filter Enable
The GMAC core compares the SA field of the received frames with the values programmed in the
enabled SA registers. If the comparison matches, then the SAMatch bit of RxStatus Word is set
high. When this bit is set high and the SA filter fails, the GMAC drops the frame.
When this bit is reset, then the GMAC Core forwards the received frame to the application and
with the updated SA Match bit of the RxStatus depending on the SA address comparison.
[8] SAIF: SA Inverse Filtering
When this bit is set, the Address Check block operates in inverse filtering mode for the SA
address comparison. The frames whose SA matches the SA registers will be marked as failing
the SA Address filter.
When this bit is reset, frames whose SA does not match the SA registers will be marked as failing
the SA Address filter.
[7:6] PCF: Pass Control Frames
These bits control the forwarding of all control frames (including unicast and multicast PAUSE
frames). Note that the processing of PAUSE control frames depends only on RFE of Flow Control
Register[2]:
0x: GMAC filters all control frames from reaching the application
10: GMAC forwards all control frames to application even if they fail the Address Filter
11: GMAC forwards control frames that pass the Address Filter.
[5] DBF: Disable Broadcast Frames
When this bit is set, the AFM module filters all incoming broadcast frames.
When this bit is reset, the AFM module passes all received broadcast frames.
[4] PM: Pass All Multicast
When set, this bit indicates that all received frames with a multicast destination address (first bit
in the destination address field is '1') are passed.
When reset, filtering of multicast frame depends on HMC bit.
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STi7105
Ethernet registers
STi7105
[3] DAIF: DA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the DA
address comparison for both unicast and multicast frames.
When reset, normal filtering of frames is performed.
Confidential
[1] HUC: Hash Unicast

When set, MAC performs destination address filtering of unicast frames according to the hash
table
When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it
compares the DA field with the values programmed in DA registers.
If Hash Filter is not selected during coreKit configuration, this bit is reserved (and RO).
[0] PR: Promiscuous Mode
When this bit is set, the Address Filter module passes all incoming frames regardless of its
destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will
always be cleared when PR is set.
GMAC_HASH_TBL_HI
Hash table high register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
HTH
Address:
Type:
RW
Reset:
0x0000
Description:
The 64-bit Hash table is used for group address filtering. For hash filtering, the
contents of the destination address in the incoming frame is passed through the CRC
logic, and the upper 6 bits of the CRC register are used to index the contents of the
Hash table. The most significant bit determines the register to be used (Hash Table
High/Hash Table Low), and the other 5 bits determine which bit within the register. A
hash value of 5b'00000 selects bit 0 of the selected register, and a value of 5b'11111
selects bit 31 of the selected register.
For example, if the DA of the incoming frame is received as 0x1F52419CB6AF (0x1F
is the first byte received), then the internally calculated 6-bit Hash value is 0x2C and
the HTH register bit[12] is checked for filtering. If the DA of the incoming frame is
received as 0xA00A98000045, then the calculated 6-bit Hash value is 0x07 and the
HTL register bit[7] is checked for filtering.
If the corresponding bit value of the register is 1b1, the frame is accepted. Otherwise,
it is rejected. If the PM (Pass All Multicast) bit is set in Register1, then all multicast
frames are accepted regardless of the multicast hash values.
If the Hash Table register is configured to be double-synchronized to the MII clock
domain, the synchronization is triggered only when Bits[31:24] (in Little-Endian mode)
or Bits[7:0] (in Big-Endian mode) of the Hash Table High/Low registers are written to.
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8137791 RevA
[2] HMC: Hash Multicast

When set, MAC performs destination address filtering of received multicast frames according to
the hash table.
When reset, the MAC performs a perfect destination address filtering for multicast frames, that is,
it compares the DA field with the values programmed in DA registers.
If Hash Filter is not selected during coreKit configuration, this bit is reserved (and RO).
STi7105
Ethernet registers
Please note that consecutive writes to these register should be performed only after
at least 4 clock cycles in the destination clock domain when double-synchronization is
enabled.
The Hash Table Hi register contains the higher 32 bits of the Hash table.
[31:0] HTH: Hash Table High
This field contains the upper 32 bits of the Hash table.
GMAC_HASH_TBL_LO
Hash table low register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ETHBaseAddress + 0x000C
Type:
RW
Reset:
0x0000
Description:
The Hash Table Low register contains the lower 32 bits of the Hash table. Both
GMAC_HASH_TBL_HI and GMAC_HASH_TBL_LO and corresponding HMC and
HUC bits in Filter Register are reserved if the Hash Filter Function is disabled during
coreKit configuration.
[31:0] HTL: Hash Table Low
This field contains the lower 32 bits of the Hash table.
Address:
Type:
RW
Reset:
0x0000
Description:
The MII Address register controls the management cycles to the external PHY
through the management interface.
GB
CR
PA
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
GW
MII address register
GR
GMAC_MII_ADDR
[31:16] RESERVED
[15:11] PA: Physical Layer Address
These bits indicate which of the 32 possible PHY devices are accessed.
[10:6] GR: MII Register
These bits select the desired Mll register in the selected PHY device.l
[5] RESERVED
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Address:
RESERVED
Confidential
HTL
Ethernet registers
STi7105
Selection
CLK_ETHERNET_PHY
MDC Clock
000
60-100 MHz
CLK_ETHERNET_PHY/42
001
100-150 MHz
CLK_ETHERNET_PHY/62
010
20-35 MHz
CLK_ETHERNET_PHY/16
011
35-60 MHz
CLK_ETHERNET_PHY/26
100
150-250 MHz
CLK_ETHERNET_PHY/102
101
50-300 MHz
CLK_ETHERNET_PHY/122
110,111
Reserved
Confidential
[1] GW: MII Write

When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If
this bit is not set, this will be a Read operation, placing the data in the MII Data register.
[0] GB: MII_BUSY
This bit is Read, Write Set, and Self Clear (R_WS_SC); the bit can be read by the application
(Read), can be set to 1b1 by the application with a register write of 1b1 (Write Set), and is
cleared to 1b0 by the core (Self Clear). The application cannot clear this type of bit, and a
register write of 1b0 to this bit has no effect.
This bit should read a logic 0 before writing to GMAC_MII_ADDR and GMAC_MII_DATA. This
bit must also be set to 0 during a Write to GMAC_MII_ADDR. During a PHY register access,
this bit will be set to 1b1 by the Application to indicate that a Read or Write access is in
progress. Register GMAC_MII_DATA should be kept valid until this bit is cleared by the GMAC
during a PHY Write operation. The GMAC_MII_DATA register is invalid until this bit is cleared by
the GMAC during a PHY Read operation. The GMAC_MII_ADDR register should not be written
to until this bit is cleared.
GMAC_MII_DATA
MII data register description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
GD
Address:
Type:
RW
Reset:
0x0000
Description:
The MII Data register stores Write data to be written to the PHY register located at the
address specified in register GMAC_MII_ADDR. The MII Data register also stores
Read data from the PHY register located at the address specified by register
GMAC_MII_ADDR.
[31:16] RESERVED
[15:0] GD: MII_DATA
This contains the 16-bit data value read from the PHY after a Management Read operation or the
16-bit data value to be written to the PHY before a Management Write operation.
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8137791 RevA
[4:2] CR: CSR Clock Range

The CSR Clock Range selection determines the CLK_ETHERNET_PHY frequency and is used
to decide the frequency of the MDC clock:
STi7105
Ethernet registers
TFE
FCB/BPA
UP
PLT
Address:
Type:
RW
Reset:
0x0000
Description:
The Flow Control register controls the generation and reception of the Control (Pause
Command) frames by the GMAC's Flow control module. A Write to a register with the
Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame.
The fields of the control frame are selected as specified in the 802.3x specification,
and the Pause Time value from this register is used in the Pause Time field of the
control frame. The Busy bit remains set until the control frame is transferred onto the
cable. The Host must make sure that the Busy bit is cleared before writing to the
register.
[31:16] PT: Pause Time

This field holds the value to be used in the Pause Time field in the transmit control frame. If the
Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then
consecutive writes to this register should be performed only after at least 4 clock cycles in the
destination clock domain.
[15:7] RESERVED
[6] DZPQ: Disable Zero-Quanta Pause
When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the
deassertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control
signal sbd_flowctrl_i/mti_flowctrl_i).
When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame
generation is enabled.
[5:4] PLT: Pause Low Threshold
This field configures the threshold of the PAUSE timer at which the input flow control signal
mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of PAUSE Frame. The
threshold values should be always greater than the Pause Time configured in Bits[31:16]. For
example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is
automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256-28) slot-times after
the first Pause-frame is transmitted.
00: Pause time 4 slot times
Slot time is defined as time taken to transmit 512 bits (64 bytes) on the MII interface.
[3] UP: Unicast Pause Frame Detect
When this bit is set, the GMAC will detect the Pause frames with the stations unicast address
specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the
detecting Pause frames with the unique multicast address. When this bit is reset, the GMAC will
detect only a Pause frame with the unique multicast address specified in the 802.3x standard.
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Confidential
PT
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RFE
Flow control register description
DZPQ
GMAC_FLOW_CTRL
Ethernet registers
STi7105
[2] RFE: Receive Flow Control Enable

When this bit is set, the GMAC will decode the received Pause frame and disable its transmitter
for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame
is disabled.
[0] FCB/BPA: Flow Control Busy/Backpressure Activate

This bit initiates a Pause Control frame in Full-Duplex mode and activates the backpressure
function in Half-Duplex mode if TFE bit is set.
This bit is Read, Write Set, and Self Clear (R_WS_SC) in FCB mode; the bit can be read by the
application (Read), can be set to 1b1 by the application with a register write of 1b1 (Write Set),
and is cleared to 1b0 by the core (Self Clear). The application cannot clear this type of bit, and a
register write of 1b0 to this bit has no effect. The bit is Read/Write (RW) in BPA mode.
In Full-Duplex mode, this bit should be read as 1b0 before writing to the Flow Control register. To
initiate a Pause control frame, the Application must set this bit to 1b1. During a transfer of the
Control Frame, this bit will continue to be set to signify that a frame transmission is in progress.
After the completion of Pause control frame transmission, the GMAC will reset this bit to 1b0. The
Flow Control register should not be written to until this bit is cleared.
In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the
GMAC Core. During backpressure, when the GMAC receives a new frame, the transmitter starts
sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the
mti_flowctrl_i input signal for the backpressure function. When the GMAC is configured to FullDuplex mode, the BPA is automatically disabled.
GMAC_VLAN_TAG
VLAN tag identifier register description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
VL
Address:
Type:
RW
Reset:
0x0000
Description:
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the
VLAN frames. The GMAC compares the 13th and 14th bytes of the receiving
frame (Length/Type) with 16h8100, and the following 2 bytes are compared
with the VLAN tag; if a match occurs, it sets the received VLAN bit in the
receive frame status. The legal length of the frame is increased from 1518
bytes to 1522 bytes.
If the VLAN Tag register is configured to be double-synchronized to the (G)MII
clock domain, then consecutive writes to these register should be performed
only after at least 4 clock cycles in the destination clock domain.
[31:16] RESERVED
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8137791 RevA
Confidential
[1] TFE: Transmit Flow Control Enable

In Full-Duplex mode, when this bit is set, the GMAC enables the flow control operation to transmit
Pause frames. When this bit is reset, the flow control operation in the GMAC is disabled, and the
GMAC will not transmit any Pause frames.
In Half-Duplex mode, when this bit is set, the GMAC enables the back-pressure operation. When
this bit is reset, the backpressure feature is disabled.
STi7105
Ethernet registers
[15:0] VL: VLAN tag identifier

This contains the 802.1Q VLAN Tag to identify the VLAN frames, and is used to compare with the
15th and 16th bytes of the receiving frames for VLAN frames. If the VL is all-zeros, then the
GMAC does not check the 15th and 16th bytes for VLAN tag comparison.
Core version identifier register description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RESERVED
USER_ID
SYNOP_ID
Address:
Type:
Reset:
0xnnss
where:
nn is user defined version number
ss is the Synopsys version number
Description:
The Version registers contents identify the version of the core. This register contains
two bytes, one of which Synopsys uses to identify the core release number, and the
other of which you set during coreKit configuration.
[31:16] RESERVED
[15:8] USER_ID:
User-defined version, configured with coreKit (reads as 0x10H for version 1.0).
[7:0] SYNOP_ID:
Synopsys-defined version (reads as 0x33H for version 3.3).
GMAC_CSR_WAKE_UP
Wake-up control and status register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
WKUPFMFILTER_REG
Address:
Type:
Reset:
0x0000
Description:
This is the address through which the remote Wake-up Frame Filter registers
(wkupfmfilter_reg) are written/read by the Application. wkupfmfilter_reg is actually a
pointer to eight (not transparent) such wkupfmfilter_reg registers. Eight sequential
Writes to this address (028) will write all wkupfmfilter_reg registers. Eight sequential
Reads from this address (028) will read all wkupfmfilter_reg registers.
This register contains the higher 16 bits of the 7th MAC address.
This register is present only when the PMT module Remote Wake-up feature is
selected in coreConsultant.
[31:0] WKUPFMFILTER_REG
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GMAC_VERSION
Ethernet registers
STi7105
The sequentional values for WKUPFMFILTER_REG are:

wkupfmfilter_reg0
Filter 0 Byte Mask
wkupfmfilter_reg1
Filter 1 Byte Mask
wkupfmfilter_reg2
Filter 2 Byte Mask
wkupfmfilter_reg3
Filter 3 Byte Mask
wkupfmfilter_reg4 RESERVED
wkupfmfilter_reg5
Filter 3
Command
Filter 3 Offset
RESERVED
Filter 2
Command
Filter 2 Offset
RESERVED
Filter 1
Command
Filter 1 Offset
RESERVED
Filter 0
Command
Filter 0 Offset
wkupfmfilter_reg6
Filter 1 CRC - 16
Filter 0 CRC - 16
wkupfmfilter_reg7
Filter 3 CRC - 16
Filter 2 CRC - 16
Filter i Byte Mask
Confidential
This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3)
in order to determine whether or not the frame is a wake-up frame. The MSB (thirtyfirst bit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte
Mask is set, then Filter i Offset + j of the incoming frame is processed by the CRC
block; otherwise Filter i Offset + j is ignored.
Filter i Command
This 4-bit command controls the filter i operation. Bit 3 specifies the address type,
defining the patterns destination address type. When the bit is set, the pattern
applies to only multicast frames; when the bit is reset, the pattern applies only to
unicast frame. Bit 2 and Bit 1 are reserved. Bit 0 is the enable for filter i; if Bit 0 is not
set, filter i is disabled.
Filter i Offset
This register defines the offset (within the frame) from which the frames are examined
by filter i. This 8- bit pattern-offset is the offset for the filter i first byte to examined. The
minimum allowed is 12.
Filter i CRC-16
This register contains the CRC_16 value calculated from the pattern, as well as the
byte mask programmed to the wake-up filter register block.
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8137791 RevA
where:
STi7105
Ethernet registers
PWR_DOWN
MAGIC_PACKET_EN
MAGIC_PACKET
WAKEUP_FRAME_EN
RESERVED
WAKEUP_FRAME
Confidential
Type:
Reset:
0x0000
Description:
The PMT CSR program the request wake-up events and monitor the wake-up events.
This register is present only when the PMT module is selected in coreConsultant.
[31] WAKEUP_FRAME_PTR_RESET: Wake-Up Frame Filter Register Pointer Reset

When set, resets the Remote Wake-up Frame Filter register pointer to 3b000. It is automatically
cleared after 1 clock cycle.
[30:10] RESERVED
[9] UNICAST_EN: Global Unicast Enable
When set, enables any unicast packet filtered by the GMAC (DAF) address recognition to be a
wake-up frame.
[8:7] RESERVED
[6] WAKEUP_FRAME: Wake-Up Frame Received
This bit is Read, Self Set, and Read Clear (R_SS_RC); the bit can be read by the application
(Read), can be set to 1b1 by the core on a certain internal event (Self Set), and is automatically
cleared to 1b0 on a register read. A register write of 1b0 has no effect on this bit.
When set, this bit indicates the power management event was generated due to reception of a
wake-up frame. This bit is cleared by a Read into this register.
[5] MAGIC_PACKET: Magic Packet Received
When set, this bit indicates the power management event was generated by the reception of a
Magic Packet. This bit is cleared by a Read into this register.
[4:3] RESERVED
[2] WAKEUP_FRAME_EN: Wake-Up Frame Enable
When set, enables generation of a power management event due to wake-up frame reception.
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Address:
RESERVED
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
UNICAST_EN
PMT control and status register description
WAKEUP_FRAME_PTR_RESET
GMAC_PMT_CTRL
Ethernet registers
STi7105
[1] MAGIC_PACKET_EN: Magic Packet Enable

When set, enables generation of a power management event due to Magic Packet reception.
RESERVED
RESERVED
RESERVED
PMT_INTR_STA
MMC_INTR_STA
MMC_IPC_INTR_RX_STA
RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MMC_INTR_TX_STA
Interrupt status register description
MMC_INTR_RX_STA
GMAC_INT_STA
Address:
Type:
Reset:
0x0000
Description:
The Interrupt Status register contents identify the events in the GMAC-CORE that can
generate interrupt. Note that all the interrupt events are generated only when the
corresponding optional feature is selected during coreKit configuration and enabled
during operation. Hence, these bits are reserved when the corresponding features is
not present in the core.
[31:8] RESERVED
[7] MMC_IPC_INTR_RX_STA: MMC Receive Checksum Offload Interrupt Status
This bit is set high whenever an interrupt is generated in the MMC Receive Checksum Offload
Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.
This bit is only valid when the optional MMC module and Checksum Offload Engine (Type 2) are
selected during configuration.
[6] MMC_INTR_TX_STA: MMC Transmit Interrupt Status
This bit is set high whenever an interrupt is generated in the MMC Transmit Interrupt Register.
This bit is cleared when all the bits in this interrupt register are cleared.
This bit is only valid when the optional MMC module is selected during configuration.
[5] MMC_INTR_RX_STA: MMC Receive Interrupt Status
This bit is set high whenever an interrupt is generated in the MMC Receive Interrupt Register.
This bit is cleared when all the bits in this interrupt register are cleared. This bit is only valid when
the optional MMC module is selected during configuration.
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8137791 RevA
[0] PWR_DOWN: Power Down

When set, all received frames will be dropped. This bit is cleared automatically when a magic
packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after
this bit is cleared are forwarded to the application.This bit must only be set when either the Magic
Packet Enable or Wake-Up Frame Enable bit is set high.
STi7105
Ethernet registers
[4] MMC_INTR_STA: MMC Interrupt Status

This bit is set high whenever any of bits 7:5 is set high and cleared only when all of these bits are
low. This bit is valid only when the optional MMC module is selected during configuration.
[3] PMT_INTR_STA: PMT Interrupt Status
This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power-Down mode
(See bits 5 and 6 in the PMT Control and Status register PMT Control and Status Register on
page 116). This bit is cleared when both bits[6:5] are cleared due to a read operation to the PMT
Control and Status register.
This bit is valid only when the optional PMT module is selected during configuration
[2] RESERVED
[0] RESERVED
RESERVED
PCS_LINK_INTR_MASK
RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PMT_INTR_MASK
Interrupt mask register description

PCS_AN_INTR_MASK
GMAC_INT_MASK
Address:
Type:
RW
Reset:
0x0000
Description:
The Interrupt Mask Register bits enables the user to mask the interrupt signal due to
the corresponding event in the Interrupt Status Register. The interrupt signal is
sbd_intr_o in GMAC-AHB and GMACDMA configuration while the interrupt signal is
mci_intr_o in the GMAC-MTL and GMAC-CORE configuration.
[31:4] RESERVED
[3] PMT_INTR_MASK: PMT Interrupt Mask
This bit, when set, will disable the assertion of the interrupt signal due to the setting of PMT
Interrupt Status bit in the Interrupt Status Register.
[2] PCS_AN_INTR_MASK: PCS AN Completion Interrupt Mask
This bit, when set, will disable the assertion of the interrupt signal due to the setting of PCS Autonegotiation complete bit in the Interrupt Status Register caused due to the completion of Autonegotiation event.
[1] PCS_LINK_INTR_MASK: PCS Link Status Interrupt Mask
This bit, when set, will disable the assertion of the interrupt signal due to the setting of PCS Linkstatus changed bit in the Interrupt Status Register caused due to change in link-status event.
[0] RESERVED
8137791 RevA
281/454
[1] RESERVED
Ethernet registers
STi7105
GMAC_ADDR0_HI
GMAC address0 high register

7
A[47:32]
RESERVED
MO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
Address:
Reset:
0x8000 FFFF
Description:
The MAC Address0 High register holds the upper 16 bits of the 6-byte first MAC
address of the station. Note that the first DA byte that is received on the (G)MII
interface corresponds to the LS Byte (Bits [7:0]) of the MAC Address Low register. For
example, if 0x112233445566 is received (0x11 is the first byte) on the (G)MII as the
destination address, then the MacAddress0 Register [47:0] is compared with
0x665544332211.
Confidential
If the MAC address registers are configured to be double-synchronized to the (G)MII

clock domains, then the synchronization is triggered only when Bits[31:24] (in LittleEndian mode) or Bits[7:0] (in Big- Endian mode) of the MAC Address Low Register
(Register17) are written to. Please note that consecutive writes to this Address Low
Register should be performed only after at least 4 clock cycles in the destination clock
domain for proper synchronization updates.
[31] MO: Always 1.
[30:16] RESERVED
[15:0] A[47:32]: MAC Address0 [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the
MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow
Control (PAUSE) Frames.
GMAC_ADDR0_LO
GMAC address0 low register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A[31:0]
Address:
Type:
RW
Reset:
0xFFFF FFFF
Description:
The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC
address of the station.
[31:0] PADR[31:0]: MAC Address0 [31:0]

This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for
filtering for received frames and for inserting the MAC address in the Transmit Flow Control
(PAUSE) Frames.
282/454
8137791 RevA
Type:
STi7105
Ethernet registers
GMAC address high registers (1-15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA
MBC
RESERVED
A[47:32]
Address:
ETHBaseAddress + 0x0048 + (one - 1) * 0x8 (where one = 1 to 15)
Type:
RW
Reset:
0xFFFF
Description:
The MAC Address High registers hold the upper 16 bits of the 6-byte MAC addresses
1 to 15 of the station.
clock domains, then the synchronization is triggered only when Bits[31:24] (in Little
Endian mode) or Bits[7:0] (in Big Endian mode) of the MAC Address Low Register
(Register19) are written to. Consecutive writes to this Address Low Register must be
performed only after at least 4 clock cycles in the destination clock domain for proper
synchronization updates.
Confidential
[31] AE: Address Enable

When this bit is set, the Address filter module uses the second MAC address for perfect filtering.
When reset, the address filter module will ignore the address for filtering.
[30] SA: Source Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the
received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA
fields of the received frame.
[29:24] MBC: Mask Byte Control
These bits are mask control bits for comparison of each of the MAC Address bytes. When set
high, the GMAC core does not compare the corresponding byte of received DA/SA with the
contents of Mac Address1 registers. Each bit controls the masking of the bytes as follows:
Bit 29: Register18[15:8]

[23:16] RESERVED
[15:0] A[47:32]: MAC Address1 [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte MAC addresses.
GMAC_ADDRone_LO
GMAC address low registers (1-15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A[31:0]
Address:
ETHBaseAddress + 0x004C + (one - 1) * 0x8 (where one = 1 to 15)
Address:
Type:
RW
Reset:
0xFFFF FFFF
8137791 RevA
283/454
GMAC_ADDRone_HI
Ethernet registers
Description:
STi7105
The MAC Address Low registers hold the lower 32 bits of the 6-byte MAC addresses
[31:0] A[31:0]: MAC Address1 [31:0]

This field contains the lower 32 bits of the 6-byte MAC addresses. The content of this field is
undefined until loaded by the Application after the initialization process.
GMAC management counters
Confidential
Address:
Type:
RW
Reset:
0x0000
Description:
The MMC control register establishes the operating mode of the management
counters.
[31:14] RESERVED
[3] FREEZE: MMC Counter Freeze
When set, this bit freezes all the MMC counters to their current value. (None of the MMC
counters are updated due to any transmitted or received frame until this bit is reset to 0. If any
MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this
mode.)
[2] RESET: Reset on Read
When set, the MMC counters will be reset to zero after Read (self-clearing after reset). The
counters are cleared when the least significant byte lane (bits[7:0]) is read.
[1] ROLLOVER: Counter Stop Rollover
When set, counter after reaching maximum value will not roll over to zero.
[0] COUNTERS_RESET:
This bit is Read, Write, and Self Clear (R_W_SC); the bit can be read and written by the
application (Read and Write), and is cleared to 1b0 by the core (Self Clear).
When set, all counters will be reset. This bit will be cleared automatically after 1 clock cycle .
GMMC_INTR_RX
GMAC MC receive interrupt register description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Address:
284/454
RX_INT[23:0]
8137791 RevA
ROLLOVER
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
COUNTERS_RESET
GMAC MC control register description
RESET
GMMC_CTRL
FREEZE
13.3
STi7105
Ethernet registers
Type:
Reset:
0x0000
Description:
The MMC Receive Interrupt register maintains the interrupts generated when receive
statistic counters reach half their maximum values. (MSB of the counter is set.) It is a
32-bit wide register. An interrupt bit is cleared when the respective MMC counter that
caused the interrupt is read. The least significant byte lane (bits[7:0]) of the respective
counter must be read in order to clear the interrupt bit.
Note: These register bits are Read, Self Set, and Read Clear (R_SS_RC); the bits are set
internally and are cleared when the appropriate counter is read.
[31:24] RESERVED
[23] RX_INT[23]:
The bit is set when the rxwatchdogerror counter reaches half the maximum value.
[22] RX_INT[22]:
The bit is set when the rxvlanframes_gb counter reaches half the maximum value.
Confidential
[21] RX_INT[21]:
The bit is set when the rxfifooverflow counter reaches half the maximum value.
[20] RX_INT[20]:
The bit is set when the rxpauseframes counter reaches half the maximum value.
[19] RX_INT[19]:
The bit is set when the rxoutofrangetype counter reaches half the maximum value.
[18] RX_INT[18]:
The bit is set when the rxlengtherror counter reaches half the maximum value.
[17] RX_INT[17]:
The bit is set when the rxunicastframes_gb counter reaches half the maximum value.
[16] RX_INT[16]:
The bit is set when the rx1024tomaxoctets_gb counter reaches half the maximum value.
[15] RX_INT[15]:
The bit is set when the rx512to1023octets_gb counter reaches half the maximum value.
[14] RX_INT[14]:
[13] RX_INT[13]:
[12] RX_INT[12]:
[11] RX_INT[11]:
The bit is set when the rx64octets_gb counter reaches half the maximum value.
[10] RX_INT[10]:
The bit is set when the rxoversize_g counter reaches half the maximum value.
[9] RX_INT[9]:
The bit is set when the rxundersize_g counter reaches half the maximum value.
8137791 RevA
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Ethernet registers
STi7105
[8] RX_INT[8]:
The bit is set when the rxjabbererror counter reaches half the maximum value.
[7] RX_INT[7]:
The bit is set when the rxrunterror counter reaches half the maximum value.
[6] RX_INT[6]:
The bit is set when the rxalignmenterror counter reaches half the maximum value.
[5] RX_INT[5]:
The bit is set when the rxcrcerror counter reaches half the maximum value.
[3] RX_INT[3]:
The bit is set when the rxbroadcastframes_g counter reaches half the maximum value.
[2] RX_INT[2]:
The bit is set when the rxoctetcount_g counter reaches half the maximum value.
Confidential
[1] RX_INT[1]:
The bit is set when the rxoctetcount_gb counter reaches half the maximum value.
[0] RX_INT[0]:
The bit is set when the rxframecount_gb counter reaches half the maximum value.
GMMC_INTR_TX
GMAC MC transmit interrupt register description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
TX_INT[24:0]
Address:
Type:
Reset:
0x0000
Description:
The MMC Transmit Interrupt register maintains the interrupts generated when
transmit statistic counters reach half their maximum values. (MSB of the counter is
set.) It is a 32-bit wide register. An interrupt bit is cleared when the respective MMC
counter that caused the interrupt is read. The least significant byte lane (bits[7:0]) of
the respective counter must be read in order to clear the interrupt bit.
[31:25] RESERVED
[24] TX_INT[24]:
The bit is set when the txvlanframes_g counter reaches half the maximum value.
[23] TX_INT[23]:
The bit is set when the txpauseframes error counter reaches half the maximum value.
[22] TX_INT[22]:
The bit is set when the txoexcessdef counter reaches half the maximum value.
286/454
8137791 RevA
[4] RX_INT[4]:
The bit is set when the rxmulticastframes_g counter reaches half the maximum value.
STi7105
Ethernet registers
[21] TX_INT[21]:
The bit is set when the txframecount_g counter reaches half the maximum value.
[20] TX_INT[20]:
The bit is set when the txoctetcount_g counter reaches half the maximum value.
[19] TX_INT[19]:
The bit is set when the txcarriererror counter reaches half the maximum value.
[18] TX_INT[18]:
The bit is set when the txexesscol counter reaches half the maximum value.
[16] TX_INT[16]:
The bit is set when the txdeferred counter reaches half the maximum value.
[15] TX_INT[15]:
The bit is set when the txmulticol_g counter reaches half the maximum value.
Confidential
[14] TX_INT[14]:
The bit is set when the txsinglecol_g counter reaches half the maximum value.
[13] TX_INT[13]:
The bit is set when the txunderflowerror counter reaches half the maximum value.
[12] TX_INT[12]:
The bit is set when the txbroadcastframes_gb counter reaches half the maximum value.
[11] TX_INT[11]:
The bit is set when the txmulticastframes_gb counter reaches half the maximum value.
[10] TX_INT[10]:
The bit is set when the txunicastframes_gb counter reaches half the maximum value.
[9] TX_INT[9]:
The bit is set when the tx1024tomaxoctets_gb counter reaches half the maximum value.
[8] TX_INT[8]:
The bit is set when the tx512to1023octets_gb counter reaches half the maximum value.
[7] TX_INT[7]:
[6] TX_INT[6]:
[5] TX_INT[5]:
[4] TX_INT[4]:
[3] TX_INT[3]:
The bit is set when the txmulticastframes_g counter reaches half the maximum value.
[2] TX_INT[2]:
The bit is set when the txbroadcastframes_g counter reaches half the maximum value.
[1] TX_INT[1]:
The bit is set when the txframecount_gb counter reaches half the maximum value.
8137791 RevA
287/454
[17] TX_INT[17]:
The bit is set when the txlatecol counter reaches half the maximum value.
Ethernet registers
STi7105
[0] TX_INT[0]:
The bit is set when the txoctetcount_gb counter reaches half the maximum value.
GMMC_INTR_MSK_RX
GMAC MC receive interrupt mask register

description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_INT_MSK[23:0]
Address:
Type:
RW
Reset:
0x0000
Description:
The MMC Receive Interrupt Mask register maintains the masks for the interrupts
generated when receive statistic counters reach half their maximum value. (MSB of
the counter is set.) It is a 32-bit wide register.
[31:24] RESERVED
Confidential
[23] RX_INT_MSK[23]:
Setting this bit masks the interrupt when the rxwatchdogerror counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxfifooverflow counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxpauseframes counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxlengtherror counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxunicastframes_gb counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half the
maximum value.
288/454
8137791 RevA
RESERVED
STi7105
Ethernet registers
maximum value.
maximum value.
Setting this bit masks the interrupt when the rx64octets_gb counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxoversize_g counter reaches half the maximum
value.
Confidential
[9] RX_INT_MSK[9]:
Setting this bit masks the interrupt when the rxundersize_g counter reaches half the maximum
value.
[8] RX_INT_MSK[8]:
Setting this bit masks the interrupt when the rxjabbererror counter reaches half the maximum
value.
[7] RX_INT_MSK[7]:
Setting this bit masks the interrupt when the rxrunterror counter reaches half the maximum value.
[6] RX_INT_MSK[6]:
Setting this bit masks the interrupt when the rxalignmenterror counter reaches half the maximum
value.
[5] RX_INT_MSK[5]:
Setting this bit masks the interrupt when the rxcrcerror counter reaches half the maximum value.
[4] RX_INT_MSK[4]:
Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half the
maximum value.
[3] RX_INT_MSK[3]:
Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half the
maximum value.
[2] RX_INT_MSK[2]:
Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half the maximum
value.
[1] RX_INT_MSK[1]:
Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half the maximum
value.
[0] RX_INT_MSK[0]:
Setting this bit masks the interrupt when the rxframecount_gb counter reaches half the maximum
value.
8137791 RevA
289/454
maximum value.
Ethernet registers
GMMC_INTR_MSK_TX
STi7105
GMAC MC transmit interrupt mask register

description
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TX_INT_MSK[24:0]
Address:
Type:
RW
Reset:
0x0000
Description:
The MMC Transmit Interrupt Mask register maintains the masks for the interrupts
generated when transmit statistic counters reach half their maximum value. (MSB of
the counter is set). It is a 32-bit wide register.
[31:25] RESERVED
[24] TX_INT_MSK[24]:
Setting this bit masks the interrupt when the txvlanframes_g counter reaches half the maximum
value.
Confidential
Setting this bit masks the interrupt when the txpauseframes error counter reaches half the
maximum value.
Setting this bit masks the interrupt when the txoexcessdef counter reaches half the maximum
value.
Setting this bit masks the interrupt when the txframecount_g counter reaches half the maximum
value.
Setting this bit masks the interrupt when the txoctetcount_g counter reaches half the maximum
value.
Setting this bit masks the interrupt when the txcarriererror counter reaches half the maximum
value.
Setting this bit masks the interrupt when the txexesscol counter reaches half the maximum value.
Setting this bit masks the interrupt when the txlatecol counter reaches half the maximum value.
Setting this bit masks the interrupt when the txdeferred counter reaches half the maximum value.
Setting this bit masks the interrupt when the txmulticol_g counter reaches half the maximum
value.
Setting this bit masks the interrupt when the txsinglecol_g counter reaches half the maximum
value.
290/454
8137791 RevA
RESERVED
STi7105
Ethernet registers
Setting this bit masks the interrupt when the txunderflowerror counter reaches half the maximum
value.
Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half the
maximum value.
Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half the
maximum value.
[9] TX_INT_MSK[9]:
Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half the
maximum value.
Confidential
[8] TX_INT_MSK[8]:
Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half the
maximum value.
[7] TX_INT_MSK[7]:
maximum value.
[6] TX_INT_MSK[6]:
maximum value.
[5] TX_INT_MSK[5]:
maximum value.
[4] TX_INT_MSK[4]:
maximum value.
[3] TX_INT_MSK[3]:
Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half the
maximum value.
[2] TX_INT_MSK[2]:
Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half the
maximum value.
[1] TX_INT_MSK[1]:
Setting this bit masks the interrupt when the txframecount_gb counter reaches half the maximum
value.
[0] TX_INT_MSK[0]:
Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half the maximum
value.
8137791 RevA
291/454
Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half the
maximum value.
Ethernet registers
TXOCTETCOUNT_GB
STi7105
Number of bytes transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXOCTETCOUNT_GB
Address:
Type:
Reset:
Number of bytes transmitted, exclusive of preamble and retried bytes, in good and
bad frames.
TXFRAMECOUNT_GB
Number of good and bad frames transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
TXFRAMECOUNT_GB
Address:
Type:
Reset:
Description:
Number of good and bad frames transmitted, exclusive of retried frames.
TXBROADCASTFRAMES_G
Number of good broadcast frames transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXBROADCASTFRAMES_G
Address:
Type:
Reset:
Description:
Number of good broadcast frames transmitted.
TXMULTICASTFRAMES_G
Number of good multicast frames transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXMULTICASTFRAMES_G
Address:
Type:
Reset:
Description:
292/454
Number of good multicast frames transmitted.
8137791 RevA
Description:
STi7105
Ethernet registers
TX64OCTETS_GB
Number of good and bad frames transmitted with

length 64 bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TX64OCTETS_GB
Address:
Type:
Reset:
Number of good and bad frames transmitted with length 64 bytes, exclusive of
preamble and retried frames.
TX65TO127OCTETS_GB

length between 65 and 127 (inclusive) bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
TX65TO127OCTETS_GB
Address:
Type:
Reset:
Description:
Number of good and bad frames transmitted with length between 65 and 127
(inclusive) bytes, exclusive of preamble and retried frames.
TX128TO255OCTETS_GB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TX128TO255OCTETS_GB
Address:
Type:
Reset:
Description:
8137791 RevA
293/454
Description:
Ethernet registers
TX256TO511OCTETS_GB
STi7105

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TX256TO511OCTETS_GB
Address:
Type:
Reset:

length between 512 and 1,023 (inclusive) bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
Address:
Type:
Reset:
Description:
Number of good and bad frames transmitted with length between 512 and 1,023
TX1024TOMAXOCTETS_GB Number of good and bad frames transmitted with

length between 1,024 and maxsize (inclusive) bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TX1024TOMAXOCTETS_GB
Address:
Type:
Reset:
Description:
294/454
Number of good and bad frames transmitted with length between 1,024 and maxsize
8137791 RevA
Description:
STi7105
Ethernet registers
TXUNICASTFRAMES_GB
Number of good and bad unicast frames

transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXUNICASTFRAMES_GB
Address:
Type:
Reset:
Number of good and bad unicast frames transmitted.
TXMULTICASTFRAMES_GB Number of good and bad multicast frames

transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
TXMULTICASTFRAMES_GB
Address:
Type:
Reset:
Description:
Number of good and bad multicast frames transmitted.
TXBROADCASTFRAMES_GB Number of good and bad broadcast frames

transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXBROADCASTFRAMES_GB
Address:
Type:
Reset:
Description:
Number of good and bad broadcast frames transmitted.
8137791 RevA
295/454
Description:
Ethernet registers
TXUNDERFLOWERROR
STi7105
Number of frames aborted due to frame underflow

error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXUNDERFLOWERROR
Address:
Type:
Reset:
Number of frames aborted due to frame underflow error.
TXSINGLECOL_G
Number of successfully transmitted frames after a

single collision in Half-duplex mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
TXSINGLECOL_G
Address:
Type:
Reset:
Description:
Number of successfully transmitted frames after a single collision in Half-duplex

mode.
TXMULTICOL_G
Number of successfully transmitted frames after

more than a single collision in Half-duplex mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXMULTICOL_G
Address:
Type:
Reset:
Description:
296/454
Number of successfully transmitted frames after more than a single collision in Halfduplex mode.
8137791 RevA
Description:
STi7105
Ethernet registers
TXDEFERRED
Number of successfully transmitted frames after a

deferral in Half-duplex mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXDEFERRED
Address:
Type:
Reset:
Number of successfully transmitted frames after a deferral in Half-duplex mode.
TXLATECOL
Number of frames aborted due to late collision

error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
TXLATECOL
Address:
Type:
Description:
Number of frames aborted due to late collision error.
TXEXCESSCOL
Number of frames aborted due to excessive (16)

collision errors
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXEXCESSCOL
Address:
Type:
Reset:
Description:
Number of frames aborted due to excessive (16) collision errors.
TXCARRIERERROR
Number of frames aborted due to carrier sense

error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXCARRIERERROR
Address:
Type:
Reset:
Description:
Number of frames aborted due to carrier sense error (no carrier or loss of carrier).
8137791 RevA
297/454
Description:
Ethernet registers
TXOCTETCOUNT_G
STi7105
Number of bytes transmitted in good frames only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXOCTETCOUNT_G
Address:
Type:
Reset:
Number of bytes transmitted, exclusive of preamble, in good frames only.
TXFRAMECOUNT_G
Number of good frames transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
TXFRAMECOUNT_G
Address:
Type:
Reset:
Description:
Number of good frames transmitted.
TXEXCESSDEF

deferral error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXEXCESSDEF
Address:
Type:
Reset:
Description:
Number of frames aborted due to excessive deferral error (deferred for more than two
max-sized frame times).
TXPAUSEFRAMES
Number of good PAUSE frames transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXPAUSEFRAMES
Address:
Type:
Reset:
Description:
298/454
Number of good PAUSE frames transmitted
8137791 RevA
Description:
STi7105
Ethernet registers
TXVLANFRAMES_G
Number of good VLAN frames transmitted
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TXVLANFRAMES_G
Address:
Type:
Reset:
Number of good VLAN frames transmitted, exclusive of retried frames.
RXFRAMECOUNT_GB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RXFRAMECOUNT_GB
Address:
Type:
Reset:
Description:
Number of good and bad frames received.
RXOCTETCOUNT_GB
Number of bytes received in good and bad frames
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXOCTETCOUNT_GB
Address:
Type:
Reset:
Description:
Number of bytes received, exclusive of preamble, in good and bad frames.
RXOCTETCOUNT_G
Number of bytes received only in good frames
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXOCTETCOUNT_G
Address:
Type:
Reset:
Description:
Number of bytes received, exclusive of preamble, only in good frames.
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Description:
Ethernet registers
STi7105
RXBROADCASTFRAMES_G Number of good broadcast frames received

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXBROADCASTFRAMES_G
Address:
Type:
Reset:
Number of good broadcast frames received.
RXMULTICASTFRAMES_G
Number of good multicast frames received
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RXMULTICASTFRAMES_G
Address:
Type:
Reset:
Description:
Number of good multicast frames received.
RXCRCERROR
Number of frames received with CRC error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXCRCERROR
Address:
Type:
Reset:
Description:
Number of frames received with CRC error.
RXALIGNMENTERROR
Number of frames received with alignment

(dribble) error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXALIGNMENTERROR
Address:
Type:
Reset:
Description:
300/454
Number of frames received with alignment (dribble) error. Valid only in 10/100 mode.
8137791 RevA
Description:
STi7105
Ethernet registers
RXRUNTERROR
Number of frames received with runt (<64 bytes

and CRC error) error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXRUNTERROR
Address:
Type:
Reset:
Number of frames received with runt (<64 bytes and CRC error) error.
RXJABBERERROR
Number of giant frames received with length

greater than 1,518 bytes and with CRC error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RXJABBERERROR
Address:
ETHBaseAddress + 0x01A0
Type:
Reset:
Description:
Number of giant frames received with length (including CRC) greater than 1,518
bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is
enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are
considered as giant frames.
RXUNDERSIZE_G
Number of frames received, with length less than

64 bytes, without any errors
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXUNDERSIZE_G
Address:
Type:
Reset:
Description:
Number of frames received with length less than 64 bytes, without any errors.
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Description:
Ethernet registers
RXOVERSIZE_G
STi7105
Number of frames received, with length greater

than the maxsize, without errors
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXOVERSIZE_G
Address:
Type:
Reset:
Number of frames received with length greater than the maxsize (1,518 or 1,522 for
VLAN tagged frames), without errors.
RX64OCTETS_GB
Number of good and bad frames received with

length 64 bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RX64OCTETS_GB
Address:
ETHBaseAddress + 0x01AC
Type:
Reset:
Description:
Number of good and bad frames received with length 64 bytes, exclusive of preamble.
RX65TO127OCTETS_GB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX65TO127OCTETS_GB
Address:
ETHBaseAddress + 0x01B0
Type:
Reset:
Description:
302/454
Number of good and bad frames received with length between 65 and 127 (inclusive)
bytes, exclusive of preamble.
8137791 RevA
Description:
STi7105
Ethernet registers
RX128TO255OCTETS_GB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX128TO255OCTETS_GB
Address:
Type:
Reset:
Number of good and bad frames received with length between 128 and 255
(inclusive) bytes, exclusive of preamble.
RX256TO511OCTETS_GB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RX256TO511OCTETS_GB
Address:
Type:
Reset:
Description:
Number of good and bad frames received with length between 256 and 511

length between 512 and 1,023 (inclusive) bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
ETHBaseAddress + 0x01BC
Type:
Reset:
Description:
Number of good and bad frames received with length between 512 and 1,023
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Description:
Ethernet registers
STi7105
RX1024TOMAXOCTETS_GB Number of good and bad frames received with

length between 1,024 and maxsize (inclusive) bytes
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX1024TOMAXOCTETS_GB
Address:
ETHBaseAddress + 0x01C0
Type:
Reset:
Number of good and bad frames received with length between 1,024 and maxsize
RXUNICASTFRAMES_G
Number of good unicast frames received
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RXUNICASTFRAMES_G
Address:
Type:
Reset:
Description:
Number of good unicast frames received.
RXLENGTHERROR
Number of frames received with length error, for all

frames with valid length field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXLENGTHERROR
Address:
Type:
Reset:
Description:
304/454
Number of frames received with length error (Length type field frame size), for all
frames with valid length field.
8137791 RevA
Description:
STi7105
Ethernet registers
RXOUTOFRANGETYPE
Number of frames received with length field not

equal to the valid frame size
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXOUTOFRANGETYPE
Address:
ETHBaseAddress + 0x01CC
Type:
Reset:
Number of frames received with length field not equal to the valid frame size (greater
than 1,500 but less than 1,536).
RXPAUSEFRAMES
Number of good and valid PAUSE frames received
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RXPAUSEFRAMES
Address:
ETHBaseAddress + 0x01D0
Type:
Reset:
Description:
Number of good and valid PAUSE frames received.
RXFIFOOVERFLOW
Number of missed received frames due to FIFO

overflow
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXFIFOOVERFLOW
Address:
Type:
Reset:
Description:
Number of missed received frames due to FIFO overflow. This counter is not present
in the GMAC-CORE configuration.
8137791 RevA
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Description:
Ethernet registers
STi7105
RXVLANFRAMES_GB
Number of good and bad VLAN frames received
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RXVLANFRAMES_GB
Address:
Type:
Reset:
Number of good and bad VLAN frames received.
RXWATCHDOGERROR
Number of frames received with error due to

watchdog timeout error
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
ETHBaseAddress + 0x01DC
Type:
Reset:
Number of frames received with error due to watchdog timeout error (frames with a
data load larger than 2,048 bytes).
GMMC_IPC_INTR_MSK_RX
GMAC MC receive checksum offload interrupt

mask register description
RESERVED
RX_IPC_INT_MSK[29:16]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_IPC_INT_MSK[13:0]
Description:
RESERVED
Confidential
RXWATCHDOGERROR
Address:
Type:
RW
Reset:
0x0000
Description:
The MMC Receive Checksum Offload Interrupt Mask register maintains the masks for
the interrupts generated when the receive IPC (Checksum Offload) statistic counters
reach half their maximum value. (the counters MSB is set.) This register is 32 bits
wide.
[31:30] RESERVED
306/454
8137791 RevA
Description:
STi7105
Ethernet registers
[29] RX_IPC_INT_MSK[29]:
Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half the maximum
value.
Confidential
Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half the maximum
value.
[15:14] RESERVED
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Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half the maximum
value.
Ethernet registers
STi7105
Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half the maximum
value.
Confidential
Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half the maximum
value.
Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half the
maximum value.
Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half the maximum
value.
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8137791 RevA
Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half the maximum
value.
STi7105
Ethernet registers
GMAC MC receive checksum offload interrupt

register description
RESERVED
Address:
Type:
Reset:
0x0000
Description:
The MMC Receive Checksum Offload Interrupt register maintains the interrupts
generated when receive IPC statistic counters reach half their maximum values (the
counters MSB is set). This register is 32 bits wide. When the MMC IPC counter that
caused the interrupt is read, its corresponding interrupt bit is cleared. The counters
least-significant byte lane (bits[7:0]) must be read to clear the interrupt bit.
[31:30] RESERVED
[29] RX_IPC_INT[29]:
The bit is set when the rxicmp_err_octets counter reaches half the maximum value.
The bit is set when the rxicmp_gd_octets counter reaches half the maximum value.
The bit is set when the rxtcp_err_octets counter reaches half the maximum value.
The bit is set when the rxtcp_gd_octets counter reaches half the maximum value.
The bit is set when the rxudp_err_octets counter reaches half the maximum value.
The bit is set when the rxudp_gd_octets counter reaches half the maximum value.
The bit is set when the rxipv6_nopay_octets counter reaches half the maximum value.
The bit is set when the rxipv6_hdrerr_octets counter reaches half the maximum value.
The bit is set when the rxipv6_gd_octets counter reaches half the maximum value.
The bit is set when the rxipv4_udsbl_octets counter reaches half the maximum value.
The bit is set when the rxipv4_frag_octets counter reaches half the maximum value.
8137791 RevA
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Confidential
RESERVED
RX_IPC_INT[29:16]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_IPC_INT[13:0]
GMMC_IPC_INTR_RX
Ethernet registers
STi7105
The bit is set when the rxipv4_nopay_octets counter reaches half the maximum value.
The bit is set when the rxipv4_hdrerr_octets counter reaches half the maximum value.
The bit is set when the rxipv4_gd_octets counter reaches half the maximum value.
[15:14] RESERVED
The bit is set when the rxicmp_err_frms counter reaches half the maximum value.
The bit is set when the rxicmp_gd_frms counter reaches half the maximum value.
The bit is set when the rxtcp_err_frms counter reaches half the maximum value.
The bit is set when the rxtcp_gd_frms counter reaches half the maximum value.
Confidential
[9] RX_IPC_INT[9]:
The bit is set when the rxudp_err_frms counter reaches half the maximum value.
[8] RX_IPC_INT[8]:
The bit is set when the rxudp_gd_frms counter reaches half the maximum value.
[7] RX_IPC_INT[7]:
The bit is set when the rxipv6_nopay_frms counter reaches half the maximum value.
[6] RX_IPC_INT[6]:
The bit is set when the rxipv6_hdrerr_frms counter reaches half the maximum value.
[5] RX_IPC_INT[5]:
The bit is set when the rxipv6_gd_frms counter reaches half the maximum value.
[4] RX_IPC_INT[4]:
The bit is set when the rxipv4_udsbl_frms counter reaches half the maximum value.
[3] RX_IPC_INT[3]:
The bit is set when the rxipv4_frag_frms counter reaches half the maximum value.
[2] RX_IPC_INT[2]:
The bit is set when the rxipv4_nopay_frms counter reaches half the maximum value.
[1] RX_IPC_INT[1]:
The bit is set when the rxipv4_hdrerr_frms counter reaches half the maximum value.
[0] RX_IPC_INT[0]:
The bit is set when the rxipv4_gd_frms counter reaches half the maximum value.
GMAC_ADDRsixteen_HI
GMAC address high registers (16-31)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AE SA
MBC
RESERVED
A[47:32]
Address:
Type:
RW
310/454
8137791 RevA
STi7105
Ethernet registers
Reset:
0xFFFF
Description:
The MAC Address High registers hold the upper 16 bits of the 6-byte MAC addresses
[31] AE: Address Enable

When this bit is set, the Address filter module uses the second MAC address for perfect filtering.
When reset, the address filter module will ignore the address for filtering.
[30] SA: Source Address
When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the
received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA
fields of the received frame.
Confidential
[29:24] MBC: Mask Byte Control

These bits are mask control bits for comparison of each of the MAC Address bytes. When set
high, the GMAC core does not compare the corresponding byte of received DA/SA with the
contents of Mac Address1 registers. Each bit controls the masking of the bytes as follows:

[23:16] RESERVED
[15:0] A[47:32]: MAC Address1 [47:32]
This field contains the upper 16 bits (47:32) of the 6-byte second MAC address.
GMAC_ADDRsixteen_LO
GMAC address low registers (16-31)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A[31:0]
Address:
Address:
Type:
RW
Reset:
0xFFFF FFFF
Description:
The MAC Address Low registers hold the lower 32 bits of the 6-byte MAC addresses
[31:0] A[31:0]: MAC Address1 [31:0]

This field contains the lower 32 bits of the 6-byte second MAC address. The content of this field is
undefined until loaded by the Application after the initialization process.
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clock domains, then the synchronization is triggered only when Bits[31:24] (in Little
Endian mode) or Bits[7:0] (in Big Endian mode) of the MAC Address Low Register
(Register19) are written to. Consecutive writes to this Address Low Register must be
performed only after at least 4 clock cycles in the destination clock domain for proper
synchronization updates.
Ethernet registers
DMA control and status registers
Address:
Type:
RW
Reset:
0x0002 0101
Description:
The Bus Mode register establishes the bus operating modes for the DMA.
[31:26] RESERVED
Confidential
[25] AAL: Address-Aligned Beats

When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned
to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffers start
address) is not aligned, but subsequent bursts are aligned to the address.
This bit is valid only in GMAC-AHB configuration, and reserved (RO with default value 0) in all
other configurations.
[24] 4xPBL Mode
When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) four
times. Thus the DMA will transfer data in to a maximum of 4, 8, 16, 32, 64 and 128 beats
depending on the PBL value.
[23] USP: Use Separate PBL
When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while
the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL
value in bits [13:8] is applicable for both DMA engines.
[22:17] RPBL: RxDMA PBL
These bits indicate the maximum number of beats to be transferred in one RxDMA transaction.
This will be the maximum value that is used in a single block Read/Write. The RxDMA will
always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus.
RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will
result in undefined behavior.
These bits are valid and applicable only when USP is set high.
[16] FB: Fixed Burst
This bit controls whether the AHB Master interface performs fixed burst transfers or not. When
set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst
transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations.
[15:14] PR: Rx:Tx priority ratio
RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only
when the DA bit is reset:
00: 1:1
01: 2:1
10: 3:1
11: 4:1
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8137791 RevA
DA
PBL
PR
FB
RPBL
USP
4xPBL
AAL
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SWR
Bus mode register
DSL
GMAC_BUS_MODE
RESERVED
13.4
STi7105
Ethernet registers
Confidential
[13:8] PBL: Programmable Burst Length

These bits indicate the maximum number of beats to be transferred in one DMA transaction.
This will be the maximum value that is used in a single block Read/ Write. The DMA will always
attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can
be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in
undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions
only.
The PBL values have the following limitations.
The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO
in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the
maximum beat supported is half the depth of the FIFO. For different data bus widths and FIFO
sizes, the valid PBL range (including x4 mode) is provided in the following table. If the PBL is
common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be
considered. Do not program out-of-range PBL values, because the system may not behave
properly.
Data Bus Width
FIFO Depth
Valid PBL Range
32
128 bytes
16 or less
256 bytes
32 or less
512 bytes
64 or less
1 KB and above
All
128 bytes
8 or less
256 bytes
16 or less
512 bytes
32 or less
1 KB
64 or less
2 KB and above
All
128 bytes
4 or less
256 bytes
8 or less
512 bytes
16 or less
1 KB
32 or less
2 KB
64 or less
4 KB and above
All
64
128
[7] RESERVED
[6:2] DSL: Descriptor Skip Length
This bit specifies the number of Word/Dword/Lword (depending on 32/64/128-bit bus) to skip
between two unchained descriptors. The address skipping starts from the end of current
descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table
is taken as contiguous by the DMA, in Ring mode.
[1] DA: DMA Arbitration scheme
0: Round-robin with Rx:Tx priority given in bits [15:14]
1: Rx has priority over Tx
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STi7105
Ethernet registers
STi7105
[0] SWR: Software Reset

This bit is Read, Write Set, and Self Clear (R_W_SC); the bit can be read by the application
When this bit is set, the MAC DMA Controller resets all GMAC Subsystem internal registers and
logic. It is cleared automatically after the reset operation has completed in all of the core clock
domains. Read a 0 value in this bit before re-programming any register of the core.
GMAC_XMT_POLL_DEMAND Transmit poll demand register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Type:
Reset:
0x0000
Description:
The Transmit Poll Demand register enables the Transmit DMA to check whether or not
the current descriptor is owned by DMA. The Transmit Poll Demand command is
given to wake up the TxDMA if it is in Suspend mode. The TxDMA can go into
Suspend mode due to an Underflow error in a transmitted frame or due to the
unavailability of descriptors owned by Transmit DMA. You can give this command
anytime and the TxDMA will reset this command once it starts re-fetching the current
descriptor from host memory.
Confidential
Address:
[31:0] TPD: Transmit Poll Demand

This bit is Read Only and Write Trigger (RO_WT); the bit can be read by the application, and
when a write operation is performed with any data value, an event is triggered.
When these bits are written with any value, the DMA reads the current descriptor pointed to by
register GMAC_CUR_TX_DESC. If that descriptor is not available (owned by Host), transmission
returns to the Suspend state and DMA register GMAC_DMA_STA [2] is asserted. If the
descriptor is available, transmission resumes.
GMAC_RCV_POLL_DEMAND Receive poll demand register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RPD
Address:
Type:
Reset:
0x0000
Description:
The Receive Poll Demand register enables the receive DMA to check for new
descriptors. This command is given to wake up the RxDMA from SUSPEND state.
The RxDMA can go into SUSPEND state only due to the unavailability of descriptors
owned by it.
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8137791 RevA
TPD
STi7105
Ethernet registers
[31:0] RPD: Receive Poll Demand

This bit is Read Only and Write Trigger (RO_WT); the bit can be read by the application, and
when a write operation is performed with any data value, an event is triggered.
When these bits are written with any value, the DMA reads the current descriptor pointed to by
register GMAC_CUR_RX_DESC. If that descriptor is not available (owned by Host), reception
returns to the Suspended state and register GMAC_DMA_STA[7] is not asserted. If the
descriptor is available, the Receive DMA returns to active state.
GMAC_RCV_BASE_ADDR
Receive descriptor list base address register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
0x0000
Description:
The Receive Descriptor List Address register points to the start of the Receive
Descriptor List. The descriptor lists reside in the host's physical memory space and
must be Word/Dword/Lword-aligned (for 32/64/128-bit data bus). The DMA internally
converts it to bus width aligned address by making the corresponding LS bits low.
Writing to this register is permitted only when reception is stopped. When stopped,
this register must be written to before the receive Start command is given.
[31:0] START_RX_LIST: Start of receive descriptor list

This field contains the base address of the First Descriptor in the Receive Descriptor list. The
LSB bits [1/2/3:0] (for 32/64/128-bit bus width) will be ignored and taken as all-zero by the DMA
internally. Hence these LSB bits are Read Only.
GMAC_XMT_BASE_ADDR
Transmit descriptor list base address register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
START_TX_LIST
Address:
Type:
RW
Reset:
0x0000
Description:
The Transmit Descriptor List Address register points to the start of the Transmit
Descriptor List. The descriptor lists reside in the host's physical memory space and
must be Word/DWORD/LWORDaligned (for 32/64/128-bit data bus). The DMA
internally converts it to bus width aligned address by making the corresponding LSB
to low. Writing to this register is permitted only when transmission has stopped. When
stopped, this register can be written before the transmission Start command is given.
[31:0] START_TX_LIST: Start of transmi descriptor list

This field contains the base address of the First Descriptor in the Transmit Descriptor list. The
LSB bits [1/2/3:0] (for 32/64/128-bit bus width) will be ignored and taken as all-zero by the DMA
internally. Hence these LSB bits are Read Only.
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Confidential
START_RX_LIST
Ethernet registers
STi7105
RI
UNF
OVF
TJT
TU
TPS
TI
Address:
Type:
Reset:
0x0000
Description:
The Status register contains all the status bits that the DMA reports to the host Status
register and is usually read by the Software driver during an interrupt service routine
or polling. Most of the fields in this register cause the host to be interrupted. Status
register bits are not cleared when read. Writing 1b1 to (unreserved) bits in Status
register[16:0] clears them and writing 1b0 has no effect. Each field (bits[16:0]) can be
masked by masking the appropriate bit in the Interrupt Enable register.
Confidential
[31:29] RESERVED
[28] GPI: GMAC PMT Interrupt
This bit indicates an interrupt event in the GMAC cores PMT module. The software must read the
corresponding registers in the GMAC core to get the exact cause of interrupt and clear its source
to reset this bit to 1b0. The interrupt signal from the GMAC subsystem (sbd_intr_o) is high when
this bit is high.
[27] GMI: GMAC MMC Interrupt
This bit reflects an interrupt event in the MMC module of the GMAC core. The software must read
the corresponding registers in the GMAC core to get the exact cause of interrupt and clear the
source of interrupt to make this bit as 1b0. The interrupt signal from the GMAC subsystem
(sbd_intr_o) is high when this bit is high.
[26] GLI: GMAC Line interface Interrupt
This bit reflects an interrupt event in the GMAC Cores PCS interface block. The software must
read the corresponding registers in the GMAC core to get the exact cause of interrupt and clear
the source of interrupt to make this bit as 1b0. The interrupt signal from the GMAC subsystem
(sbd_intr_o) is high when this bit is high.
[25:23] EB: Error bits.
These bits indicate the type of error that caused a Bus Error (error response on the AHB
interface). Valid only with Fatal Bus Error bit (Status register[13]) set. This field does not generate
an interrupt.
Bit 25 1b1 Error during descriptor access Error during data buffer access
Bit 23
Bit 24
Bit 25
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1b1
Error during data transfer by TxDMA
1b0
Error during data transfer by RxDMA
1b1
Error during read transfer
1b0
Error during write transfer
1b1
Error during descriptor access
1b0
Error during data buffer access
8137791 RevA
RU
ETI
RESERVED
FBI
ERI
AIS
NIS
20 19 18 17 16 15 14 13 12 11 10
RS
21
TS
EB
GLI
GMI
GPI
RESERVED
31 30 29 28 27 26 25 24 23 22
RPS
Status register
RWT
GMAC_DMA_STA
STi7105
Ethernet registers
[19:17] RS: Receive process state

These bits indicate the Receive DMA FSM state. This field does not generate an interrupt.
3b000: Stopped: Reset or Stop Receive Command issued.
3b001: Running: Fetching Receive Transfer Descriptor.
3b010: Reserved for future use.
3b011: Running: Waiting for receive packet.
3b100: Suspended: Receive Descriptor Unavailable.
3b101: Running: Closing Receive Descriptor.
3b110: Reserved for future use.
3b111: Running: Transferring the receive packet data from receive buffer to host memory.
[16] NIS: Normal interrupt summary
This bit is Read, Write Set, and Self Clear (R_SS_WC); the bit can be read by the application
(Read), can be set to 1b1 by the core on a certain internal event (Self Set), and can be cleared to
1b0 by the application with a register write of 1b1 (Write Clear). A register write of 1b0 has no
effect on this bit.
Normal Interrupt Summary bit value is the logical OR of the following when the corresponding
interrupt bits are enabled in the DMA Interrupt Enable register:
Status register[0]: Transmit Interrupt
Status register[2]: Transmit Buffer Unavailable
Status register[6]: Receive Interrupt
Status register[14]: Early Receive Interrupt
Only unmasked bits affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit
that causes NIS to be set is cleared.
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[22:20] TS: Transmit process state

These bits indicate the Transmit DMA FSM state. This field does not generate an interrupt.
3b000: Stopped; Reset or Stop Transmit Command issued.
3b001: Running; Fetching Transmit Transfer Descriptor.
3b010: Running; Waiting for status.
3b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx
FIFO).
3b100, 3b101: Reserved for future use.
3b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.
3b111: Running; Closing Transmit Descriptor
STi7105
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[15] AIS : Abnormal interrupt summary.

effect on this bit.
Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding
interrupt bits are enabled in the DMA Interrupt Enable register:
Status register[1]: Transmit Process Stopped
Status register[3]: Transmit Jabber Timeout
Status register[4]: Receive FIFO Overflow
Status register[5]: Transmit Underflow
Status register[7]: Receive Buffer Unavailable
Status register[8]: Receive Process Stopped
Status register[9]: Receive Watchdog Timeout
Status register[10]: Early Transmit Interrupt
Status register[13]: Fatal Bus Error.
Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is
cleared.
[14] ERI : early receive interrupt
This bit is Read, Self Set, and Self Clear or Write Clear (R_SS_SC_WC) ; the bit can be read by
the application (Read), can be set to 1b1 by the core on a certain internal event (Self Set), and
can be cleared to 1b0 either by the core itself (Self Clear) or by the application with a register
write of 1b0 (Write Clear). A register write of 1b1 to this bit has to no effect.
This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt,
Status register[6], automatically clears this bit.
[13] FBI: Fatal Bus Error Interrupt
effect on this bit.
This bit indicates that a Bus Error occurred (Status register[25:23]). When this bit is set, the
corresponding DMA engine disables all its bus accesses.
[12:11] RESERVED
[10] ETI: Early Transmit Interrupt
effect on this bit.
This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO.
[9] RWT: Receive Watchdog Timeout
effect on this bit.
This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when
Jumbo Frame mode is enabled).
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Ethernet registers
STi7105
Ethernet registers
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[7] RU: Receive Buffer Unavailable

effect on this bit.
This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be
acquired by the DMA. Receive Process is suspended. To resume processing Receive
descriptors, the host should change the ownership of the descriptor and issue a Receive Poll
Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the
next recognized incoming frame is received. Status register[7] is set only when the previous
Receive Descriptor was owned by the DMA.
[6] RI: Receive interrupt
effect on this bit.
This bit indicates the completion of frame reception. Specific frame status information has been
posted in the descriptor. Reception remains in the Running state.
[5] UNF : Transmit Underflow
effect on this bit.
This bit indicates that the Transmit Buffer had an Underflow during frame transmission.
Transmission is suspended and an Underflow Error TDES0[1] is set.
[4] OVF: Receive Overflow
effect on this bit.
This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial
frame is transferred to application, the overflow status is set in RDES0[11].
[3] TJ : Transmit Jabber Timeout
effect on this bit.
This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been
excessively active. The transmission process is aborted and placed in the Stopped state. This
causes the Transmit Jabber Timeout TDES0[14] flag to assert. .
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[8] RPS: Receive Process Stopped

effect on this bit.
This bit is asserted when the Receive Process enters the Stopped state.
Ethernet registers
STi7105
[0] TI: Transmit Interrupt.

effect on this bit.
This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor.
SR
RESERVED
OSF
RTC
FUF
RESERVED
RFA
RFD
ST
TTC
RESERVED
FTF
TSF
RFD[2]
DFF
RFA[2]
DT
RSF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FEF
Control (operation mode) register
EFC
GMAC_DMA_CTRL
RESERVED
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[1] TPS: Transmit Process Stopped

effect on this bit.
This bit is set when the transmission is stopped.
Address:
Type:
RW
Reset:
0x0000
Description:
The Operation Mode register establishes the Transmit and Receive operating modes
and commands. This register should be the last control register to be written as part
of DMA initialization. This register is also present in the GMAC-MTL configuration
with Bits 13, 2, and 1 unused and reserved.
[31:27] RESERVED
[26] DT: Disable Dropping of TCP/IP Checksum Error Frame
When this bit is set, the core does not drop frames that only have errors detected by the Receive
Checksum Offload engine. Such frames do not have any errors (including FCS error) in the
Ethernet frame received by the MAC but have errors in the encapsulated payload only. When this
bit is reset, all error frames are dropped if the FEF bit is reset.
If the Full Checksum Offload engine (Type 2) is disabled, this bit is reserved (RO with value
1'b0).
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[2] TU: Transmit Buffer Unavailable

effect on this bit.
This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be
acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state
transitions. To resume processing transmit descriptors, the host should change the ownership of
the bit of the descriptor and then issue a Transmit Poll Demand command.
STi7105
Ethernet registers
[25] RSF: Receive Store and Forward

When this bit is set, the MTL only reads a frame from the Rx FIFO after the complete frame has
been written to it, ignoring RTC bits. When this bit is reset, the Rx FIFO operates in Cut-Through
mode, subject to the threshold specified by the RTC bits.
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[23] RFA[2]: MSB of Threshold for Activating Flow Control

If the GMAC-UNIV is configured for an Rx FIFO depth of 8 KB or more, this bit (when set)
provides additional threshold levels for activating the Flow Control in both Half-Duplex and FullDuplex modes. This bit (as Most Significant Bit) along with the RFA (bits [10:9]) give the following
thresholds for activating flow control.
100: Full 5 KB
101: Full 6 KB
110: Full 7 KB
111: Reserved
This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.
[22] RFD[2]: MSB of Threshold for Deactivating Flow Control
If the GMAC-UNIV is configured for an Rx FIFO depth of 8 KB or more, this bit (when set)
provides additional threshold levels for deactivating the Flow Control in both Half-Duplex and
Full-Duplex modes. This bit (as Most Significant Bit) along with the RFD (bits [12:11]) give the
following thresholds for deactivating flow control.
100: Full 5 KB
101: Full 6 KB
110: Full 7 KB
111: Reserved
This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.
[21] TSF: Transmit Store and Forward
When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO.
When this bit is set, the TTC values specified in the Operation Mode register[16:14] are ignored.
This bit should be changed only when transmission is stopped.
[20] FTF: Flush Transmit FIFO
When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all
data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is
completed fully. The Operation Mode register should not be written to until this bit is cleared.
[19:17] RESERVED
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[24] DFF: Disable Flushing of Received Frames

When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive
descriptors/buffers as it does normally when this bit is reset.
This bit is reserved (and RO) in GMAC-MTL configuration.
STi7105
[16:14] TTC: Transmit Threshold Control

These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when
the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames
with a length less than the threshold are also transmitted. These bits are used only when the
TSF bit (Bit 21) is reset.
000: 64
001: 128
010: 192
011: 256
100: 40
101: 32
110: 24
111: 16
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[13] ST: Start/Stop Transmission Command

When this bit is set, transmission is placed in the Running state, and the DMA checks the
Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is
attempted either from the current position in the list, which is the Transmit List Base Address set
by GMAC_XMT_BASE_ADDR, or from the position retained when transmission was stopped
previously. If the current descriptor is not owned by the DMA, transmission enters the
Suspended state and Transmit Buffer Unavailable (Status register[2]) is set. The Start
Transmission command is effective only when transmission is stopped. If the command is issued
before setting DMA Transmit descriptor list base address register, then the DMA behavior is
unpredictable
When this bit is reset, the transmission process is placed in the Stopped state after completing
the transmission of the current frame. The Next Descriptor position in the Transmit List is saved,
and becomes the current position when transmission is restarted. The stop transmission
command is effective only the transmission of the current frame is complete or when the
transmission is in the Suspended state.
[12:11] RFD: Threshold for deactivating flow control (in both HD and FD)
These bits control the threshold (Fill-level of Rx FIFO) at which the flow-control is deasserted
after activation.
00: Full 1 KB
01: Full 2 KB
10: Full 3 KB
11: Full 4 KB
Note that the deassertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or
more, an additional bit (RFD[2]) is used for more threshold levels as described in bit [22].
[10:9] RFA: Threshold for activating flow control (in both HD and FD)
These bits control the threshold (Fill level of Rx FIFO) at which flow control is activated.
00: Full 1 KB
01: Full 2 KB
10: Full 3 KB
11: Full 4 KB
Note that the above only applies to Rx FIFOs of 4 KB or more when the EFC bit is set high. If the
Rx FIFO is 8 KB or more, an additional bit (RFA[2]) is used for more threshold levels as
described in bit [23].
[8] EFC: Enable HW flow control
When this bit is set, the flow control signal operation based on fill-level of Rx FIFO is enabled.
When reset, the flow control operation is disabled. This bit is not used (reserved and always
reset) when the Rx FIFO is less than 4 KB.
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STi7105
Ethernet registers
[7] FEF: Forward Error Frames

When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error,
giant frame, watchdog timeout, overflow). However, if the frames start byte (write) pointer is
already transferred to the read controller side (in Threshold mode), then the frames are not
dropped. Note that in GMAC-MTL configuration in which the Frame Length FIFO is also enabled
during coreKit configuration, the Rx FIFO drops the error frames if that frame's start byte is not
transferred (output) on the ARI bus. When FEF is set, all frames except runt error frames are
forwarded to the DMA.
[5] RESERVED
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[4:3] RTC: Receive Threshold Control

These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA
starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition,
full frames with a length less than the threshold are transferred automatically. Note that value of
11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only
when the RSF bit is zero, and are ignored when the RSF bit is set to 1.
00: 64
01: 32
10: 96
11: 128
[2] OSF: Operate on Second Frame
When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even
before status for first frame is obtained.
[1] SR: Start/Stop Receive
When this bit is set, the Receive process is placed in the Running state. The DMA attempts to
acquire the descriptor from the Receive list and processes incoming frames. Descriptor
acquisition is attempted from the current position in the list, which is the address set by DMA
Receive Descriptor List Address register or the position retained when the Receive process was
previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive
Buffer Unavailable (Status GMAC_DMA_STA[7]) is set. The Start Receive command is effective
only when reception has stopped. If the command was issued before setting DMA Receive
Descriptor List Address, DMA behavior is unpredictable.
When this bit is cleared, RxDMA operation is stopped after the transfer of the current frame. The
next descriptor position in the Receive list is saved and becomes the current position after the
Receive process is restarted. The Stop Receive command is effective only when the Receive
process is in either the Running (waiting for receive packet) or in the Suspended state.
[0] RESERVED
Address:
TIE
TSE
TJE
TUE
OVE
RIE
UNE
RSE
ETE
RESERVED
FBE
ERE
AIE
NIE
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RUE
Interrupt enable register
RWE
GMAC_DMA_INT_EN
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[6] FUF: Forward Undersized Good Frames

When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less
than 64 bytes) including pad-bytes and CRC).
When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already
transferred due to lower value of Receive Threshold (e.g., RTC = 01).
Ethernet registers
STi7105
Type:
RW
Reset:
0x0000
Description:
The Interrupt Enable register enables the interrupts reported by the Status register.
Setting a bit to 1b1 enables a corresponding interrupt. After a hardware or software
reset, all interrupts are disabled.
[16] NIE : Normal Interrupt Summary Enable

When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is
disabled. This bit enables the following bits:
Status register[0]: Transmit Interrupt
Status register[2]: Transmit Buffer Unavailable
Status GMAC_DMA_STA[6]: Receive Interrupt
Status GMAC_DMA_STA[14]: Early Receive Interrupt
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[15] AIE: Abnormal Interrupt Summary Enable

When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal
Interrupt is disabled. This bit enables the following bits
Status register[1]: Transmit Process Stopped
Status register[3]: Transmit Jabber Timeout
Status register[4]: Receive Overflow
Status register[5]: Transmit Underflow
Status register[7]: Receive Buffer Unavailable
Status register[8]: Receive Process Stopped
Status register[9]: Receive Watchdog Timeout
Status register[10]: Early Transmit Interrupt
Status register[13]: Fatal Bus Error
[14] ERE: Early Receive Interrupt Enable
When this bit is set with Normal Interrupt Summary Enable (Interrupt Enable register[16]), Early
Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled.
[13] FBE: Fatal Bus Error Enable
When this bit is set with Abnormal Interrupt Summary Enable (Interrupt Enable register[15]), the
Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is
disabled.
[12:11] RESERVED
[10] ETE: Early Transmit Interrupt Enable
When this bit is set with an Abnormal Interrupt Summary Enable (Interrupt Enable register[15]),
Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled.
[9] RWE: Receive Watchdog Timeout Enable
When this bit is set with Abnormal Interrupt Summary Enable (Interrupt Enable register[15]), the
Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog
Timeout Interrupt is disabled.
[8] RSE: Receive Stopped Enable
When this bit is set with Abnormal Interrupt Summary Enable (Interrupt Enable register[15]),
Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is
disabled.
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[31:17] RESERVED
STi7105
Ethernet registers
[7] RUE: Receive Buffer Unavailable Enable

Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer
Unavailable Interrupt is disabled.
[6] RIE: Receive Interrupt Enable
When this bit is set with Normal Interrupt Summary Enable (Interrupt Enable register[16]),
Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled.
[4] OVE: Overflow Interrupt Enable

Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled.
[2] TUE: Transmit Buffer Unavailable Enable

Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer
Unavailable Interrupt is disabled.
[1] TSE: Transmit Stopped Enable
Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt
is disabled.
[0] TIE: Transmit Interrupt Enable
Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled.
Missed frame and buffer overflow counter

register
FIFO
FRAME
MISSED_FRAME
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MISSED_FRAME_CTR
GMAC_MISSED_FRAME_CTR
RESERVED
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[3] TJE: Transmit Jabber Timeout Enable

Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout
Interrupt is disabled.
Address:
Type:
Reset:
0x0000
Description:
The DMA maintains two counters to track the number of missed frames during
reception. This register reports the current value of the counter. The counter is used
for diagnostic purposes. Bits[15:0] indicate missed frames due to the host buffer
being unavailable. Bits[27:17] indicate missed frames due to buffer overflow
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[5] UNE: Underflow Interrupt Enable

Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled.
Ethernet registers
STi7105
conditions (MTL and GMAC) and runt frames (good frames of less than 64 bytes)
dropped by the MTL.
[31:29] RESERVED
[27:17] FRAME: Overflow Frame Counter

Indicates the number of frames missed by the application. This counter is incremented each time
the MTL asserts the sideband signal mtl_rxoverflow_o. The counter is cleared when this register
is read with mci_be_i[2] at 1b1.
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[16] MISSED_FRAME: Overflow bit for Missed Frame Counter

This bit is set when the Missed Frame Counter (bits 15:0) overflows from all-ones to all-zeros.
This bit is reset when this register is read.
[15:0] MISSED_FRAME_CTR: Missed Frame Counter
lndicates the number of frames missed by the controller due to the Host Receive Buffer being
unavailable. This counter is incremented each time the DMA discards an incoming frame. The
counter is cleared when this register is read with mci_be_i[0] at 1b1.
GMAC_CUR_TX_DESC
Current host transmit descriptor register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_POINTER
Address:
Type:
Reset:
0x0000
Description:
The Current Host Transmit Descriptor register points to the start address of the
current Transmit Descriptor read by the DMA.
[31:0] ADDR_POINTER: Host Transmit Descriptor Address Pointer

Cleared on Reset. Pointer updated by DMA during operation.
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[28] FIFO: Overflow bit for FIFO Overflow Counter

This bit is set when the Overflow Counter (bits 27:17) overflows from all-ones to all-zeros. This bit
is reset when this register is read.
STi7105
Ethernet registers
GMAC_CUR_RX_DESC
Current host receive descriptor register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
0x0000
Description:
The Current Host Receive Descriptor register points to the start address of the
current Receive Descriptor read by the DMA.
[31:0] ADDR_POINTER: Host Receive Descriptor Address Pointer

GMAC_CUR_TX_BUF_ADDR Current host transmit buffer address register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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ADDR_POINTER
Address:
Type:
Reset:
0x0000
Description:
The Current Host Transmit Buffer Address register points to the current Transmit
Buffer Address being read by the DMA.
[31:0] ADDR_POINTER: Host Transmit Buffer Address Pointer

GMAC_CUR_RX_BUF_ADDR Current host receive buffer address register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ADDR_POINTER
Address:
Type:
Reset:
0x0000
Description:
The Current Host Receive Buffer Address register points to the current Receive Buffer
address being read by the DMA.
[31:0] ADDR_POINTER: Host Receive Buffer Address Pointer

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ADDR_POINTER
Programmable I/O port
STi7105
14
14.1
Overview
The STi7105 has two separate Programmable Input/Output (PIO) blocks:
The comms block contains one block of PIO. This supports 10 banks, of which 7 are
connected to PADS. These are identified as PIO[6:0].
A standalone PIO block supports a further 10 banks, these are identified as PIO[16:7].
PIO[6:0]
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Comms block
Standalone
PIO block
14.1.1
Comms
PIO mux
PIO[9:7]
PIO[6:0]
PIO[16:7]
PIO[8:0]
Standalone
PIO mux
Functional Description
Each PIO bank allows direct control of 8 pads. The STi7105 has 17 banks of PIO connected
to pads, giving a total of 136 controlled pads.
Any of the pads can be configured as input, output or bidirectional. The output drivers can
be setup as push-pull, open drain or weak pull-up.
The pad input can also be compared to a stored value to produce an interrupt if it is not
equal.
All PIO pins are rated at 4 mA sink/source. The input compare logic can generate an
interrupt on any change of any input bit.
The PIO ports can be controlled by registers, mapped into the device address space. The
registers for each port are grouped in a 4 Kbyte block, with the base of the block for port n at
the address PIOnBaseAddress. At reset, all of the registers are reset to zero and all PIO
pads put in input mode with internal pull-up.
Each 8-bit PIO port has a set of eight-bit registers. Each of the eight bits of each register
refers to the corresponding pin in the corresponding port. These registers hold:
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the output data for the port (PIOn_POUT)
the input data read from the pin (PIOn_PIN)
PIO bit configuration registers (PIOn_PCx)
the two input compare function registers (PIOn_PCOMP and PIOn_PMASK)
8137791 RevA
Figure 50. PIO pins muxing
STi7105

Each of the registers, except PIOn_PIN, is mapped on to two additional addresses so that
bits can be set or cleared individually.
14.1.2
The PIO_SET_x registers set bits individually. Writing 1 in these registers sets a
corresponding bit in the associated register x; 0 leaves the bit unchanged.
The PIO_CLR_x registers clear bits individually. Writing 1 in these registers resets a
corresponding bit in the associated register x; 0 leaves the bit unchanged.
Alternate functions
Confidential
Each PIO bit inside the COMMs block can be assigned an alternate function both in input
and output mode.
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The PIOs also have alternate functions. Refer to Chapter 7, Alternate functions on PIO in
the STi7105 data sheet for full details of the alternate functions.
Programmable I/O port registers
STi7105
15
Caution:
Register bits that are shown as reserved must not be modified by software because this will
cause unpredictable behavior.
The STi7105 has 17 PIO ports, in two banks (PIO0 - PIO6, and PIO7 - PIO16). Each 8-bit
PIO port has a set of eight-bit registers. Each of the eight bits of each register refers to the
corresponding pin in the corresponding port.
Register addresses are provided as PIOnBaseAddress + offset.
Bank 1:
PIO1BaseAddress: 0xFD02 1000
Confidential

Bank 2:
PIO7BaseAddress: 0xFE01 0000
Table 55.
Programmable I/O ports register summary
Offset
Register
Description
Page
0x00
PIOn_POUT
PIO output
on page 331
0x04
PIOn_SET_POUT
Set bits of POUT
on page 331
0x08
PIOn_CLR_POUT
Clear bits of POUT
on page 332
0x10
PIOn_PIN
PIO input
on page 332
0x20, 30, 40
PIOn_PCx
PIO configuration
on page 332
0x24, 34, 44
PIOn_SET_PCx
Set bits of PCx
on page 333
0x28, 38, 48
PIOn_CLR_PCx
Clear bits of PCx
on page 333
0x50
PIOn_PCOMP
PIO input comparison
on page 334
0x54
PIOn_SET_PCOMP
Set bits of PCOMP
on page 334
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8137791 RevA
STi7105
Table 55.

Programmable I/O ports register summary
Offset
Register
Description
Page
0x58
PIOn_CLR_PCOMP
Clear bits of PCOMP
on page 335
0x60
PIOn_PMASK
PIO input comparison mask
on page 335
0x64
PIOn_SET_PMASK
Set bits of PMASK
on page 335
0x68
PIOn_CLR_PMASK
Clear bits of PMASK
on page 336
There is an additional comms register described in the System configuration chapter of

Volume 1.
PIO output
6
Confidential
POUT[7:0]
Address:
PIOnBaseAddress + 0x00
Type:
RW
Reset:
Description:
Holds output data for the port. Each bit defines the output value of the corresponding
bit of the port.The PIOn_POUT register is mapped on to two additional addresses,
PIOn_SET_POUT and PIOn_CLR_POUT, so that bits can be set or cleared
individually.
[7:0] POUT[7:0]: Bit 7 to 0 of output data for port.
PIOn_SET_POUT
7
Set bits of POUT

5
SET_POUT[7:0]
Address:
Type:
Description:
PIOn_SET_POUT allows bits of PIOn_POUT to be set individually.
[7:0] SET_POUT[7:0]:
1: Sets the corresponding bit in PIOn_POUT.
0: Leaves the corresponding bit unchanged.
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PIOn_POUT
STi7105
PIOn_CLR_POUT
7
Clear bits of POUT
CLR_POUT[7:0]
Address:
Type:
Description:
PIOn_CLR_POUT allows bits of PIOn_POUT to be cleared individually.
PIOn_PIN
PIO input
Confidential
PIN[7:0]
Address:
Type:
Reset:
Description:
The data read from this register gives the logic level present on the input pins of the
port at the start of the read cycle to this register. Each bit reflects the input value of
the corresponding bit of the port. The read data is the last value written to the register
regardless of the pin configuration selected.
[7:0] PIN[7:0]: Bit 7 to 0 of input data for port.
PIOn_PCx
PIO configuration
0x20
CONFIGDATA0[7:0]
0x30
CONFIGDATA1[7:0]
0x40
CONFIGDATA2[7:0]
Address:
PIOnBaseAddress + 0x20 (PIOn_PC0), 0x30 (PIOn_PC1), 0x40 (PIOn_PC2)
Type:
RW
Reset:
Description:
There are three configuration registers (PIOn_PC0, PIOn_PC1 and PIOn_PC2) for
each port. These are used to configure the PIO port pins. Each pin can be configured
as an input, output, bidirectional, or alternative function pin (if any), with options for
the output driver configuration.
Three bits, one bit from each of the three registers, configure the corresponding bit of
the port. The configuration of the corresponding I/O pin for each valid bit setting is
given in Table 56..
[7:0] CONFIGDATAx[7:0]: PIO configuration data x bits 7 to 0.
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8137791 RevA
[7:0] CLR_POUT[7:0]:
1: Clears the corresponding bit in PIOn_POUT.
STi7105

PIO bit configuration encoding
PC2[y]
PC1[y]
PC0[y]
Bit y configuration
Bit y output
Input
Weak pull up (default)
0 or 1
Bidirectional
Open drain
Output
Push-pull
0 or 1
Input
High impedance
Alternative function output
Push-pull
Alternative function bidirectional
Open drain
The PIOn_PC[2:0] registers are each mapped onto two additional addresses,
PIOn_SET_PCx and PIOn_CLR_PCx, so that bits can be set or cleared individually.
PIOn_SET_PCx
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Set bits of PCx

6
0x24
SET_PC0[7:0]
0x34
SET_PC1[7:0]
0x44
SET_PC2[7:0]
Address:
PIOnBaseAddress + 0x24 (PIOn_SET_PC0), 0x34 (PIOn_SET_PC1),

0x44 (PIOn_SET_PC2)
Type:
Description:
PIOn_SET_PCx allow the bits of registers PIOn_PCx to be set individually.
[7:0] SET_PC0[7:0]:
1: Sets the corresponding bit in PIOn_PCx.
PIOn_CLR_PCx
7
Clear bits of PCx

6
0x28
CLR_PC0[7:0]
0x38
CLR_PC1[7:0]
0x48
CLR_PC2[7:0]
Address:
PIOnBaseAddress + 0x28 (PIOn_CLR_PC0), 0x38 (PIOn_CLR_PC1),

0x48 (PIOn_CLR_PC2)
Type:
Description:
PIOn_CLR_PCx allows the bits of registers PIOn_PCx to be cleared individually.
[7:0] CLR_PC0[7:0]:
1: Clears the corresponding bit in PIOn_PCx.
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Table 56.
PIOn_PCOMP
7
STi7105
PIO input comparison

6
Address:
Type:
RW
Reset:
Description:
The input compare register PIOn_PCOMP can be used to cause an interrupt if the
input value differs from a fixed value.
The input data from the PIO ports pins are compared with the value held in
PIOn_PCOMP. If any of the input bits is different from the corresponding bit in the
PIOn_PCOMP register and the corresponding bit position in PIOn_PMASK is set to 1,
then the internal interrupt signal for the port is set to 1.
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The compare function is sensitive to changes in levels on the pins. For the
comparison to be seen as a valid interrupt by an interrupt handler, the change in state
on the input pin must be longer in duration than the interrupt response time.
The compare function is operational in all configurations for each PIO bit, including
the alternative function modes.
The PIOn_PCOMP register is mapped onto two additional addresses,
PIOn_SET_PCOMP and PIOn_CLR_PCOMP, so that bits can be set or cleared
individually..
[7:0] PCOMP[7:0]: 8-bit value to which PIn is compared.
PIOn_SET_PCOMP
7
Set bits of PCOMP

5
SET_PCOMP[7:0]
Address:
Type:
Description:
PIOn_SET_PCOMP allows bits of PIOn_PCOMP to be set individually.
[7:0] SET_PCOMP[7:0]:
1: Sets the corresponding bit in PIOn_PCOMP.
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8137791 RevA
PCOMP[7:0]
STi7105
PIOn_CLR_PCOMP
7
Clear bits of PCOMP

5
CLR_PCOMP[7:0]
Address:
Type:
Description:
PIOn_CLR_PCOMP allows bits of PIOn_PCOMP to be cleared individually.
PIOn_PMASK
7
PIO input comparison mask

6
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PMASK[7:0]
Address:
Type:
RW
Reset:
Description:
When a bit is set to 1, the compare function for the internal interrupt for the port is
enabled for that bit. If the respective bit ([7:0]) of the input is different from the
corresponding bit in the PIOn_PCOMP register, then an interrupt is generated.
The PIOn_PMASK register is mapped on to two additional addresses,
PIOn_SET_PMASK and PIOn_CLR_PMASK, so that bits can be set or cleared
individually..
[7:0] PMASK[7:0]:
When set to 1, interrupt generated when difference between PCompBitn and PInBitn detected.
PIOn_SET_PMASK
7
Set bits of PMASK

5
SET_PMASK[7:0]
Address:
Type:
Description:
PIOn_SET_PMASK allows bits of PIOn_PMASK to be set individually.
[7:0] SET_PMASK[7:0]:
1: Sets the corresponding bit in PIOn_PMASK.
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[7:0] CLR_PCOMP[7:0]:
1: Clears the corresponding bit in PIOn_PCOMP.
PIOn_CLR_PMASK
7
STi7105
Clear bits of PMASK

5
CLR_PMASK[7:0]
Address:
Type:
Description:
PIOn_CLR_PMASK allows bits of PIOn_PMASK to be cleared individually.
Confidential
[7:0] CLR_PMASK[7:0]:
1: Clears the corresponding bit in PIOn_PMASK.
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8137791 RevA
STi7105
Synchronous serial controller (SSC)
16
16.1
Overview
The SSC shares pins with the parallel input/output (PIO) ports. It supports full-duplex(a) and
half-duplex synchronous communication when used in conjunction with the PIO
configuration.
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The SSC uses three signals:
serial clock SCL
serial data in/out MRST
serial data out/in MTSR(a)
To set the SSC PIOs to their alternate functions, follow this sequence:
1.
Set SCL and MTSR as open drain bidirectional.
2.
Set MRST as input(a).
3.
Set SCL and MTSR to logic high.
4.
Set all SSC registers to slave mode.
5.
Only now, when the software is ready to accept data from the master, reprogram the
PIO pins to their alternative output functions.
For IC operation, MRST and MTSR can either be externally wired together, or just the
MTSR pin can be used(a). These pins are connected to the SSC clock and data interface
pins in a configuration which allows their direction to be changed when in master or slave
mode (see Section 16.2.1: Pin connection and control on page 340). The serial clock signal
is either generated by the SSC (in master mode) or received from an external master (in
slave mode). The input and output data are synchronized to the serial clock.
The following features are programmable: baudrate, data width, shift direction (heading
control), clock polarity and clock phase. These features allow communications with SPI
compatible devices.
In the SPI standard, the device can be used as a bus master, a bus slave, or can arbitrate in
a multi-master environment for control of the bus. Many of these features require software
support.
a. On the STi7105, by default the two serial data in/out signals are multiplexed on to a single pin for IC mode (fullduplex mode is not supported).
8137791 RevA
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The synchronous serial controller (SSC) is a high-speed interface, which can be used to
communicate with a wide variety of serial memories, remote control receivers and other
microcontrollers. There are a number of serial interface standards for these. Four external
SSCs are provided on the STi7105 for IC/SPI master/slave interfaces. The SSC supports
all the features of the serial peripheral interface (SPI) bus and also includes additional
functions for the full support of the IC bus. The general programmable features should also
allow interface with other serial bus standards.
STi7105
The SSC also fully supports the IC bus standard and contains additional hardware (beyond
the SPI standard) to achieve this. The extra IC features include:
multi-master arbitration
acknowledge generation
start and stop condition generation and detection
clock stretching
These allow software to fully implement all aspects of the standard, such as master and
slave mode, multi-master mode, 10-bit addressing and fast mode.
Basic operation
Control of the direction (as input, output or bi-directional) of the SCL, MTSR and MRST
pins(b) is performed in software by configuring the PIO.
The serial clock output signal is programmable in master mode for baudrate, polarity and
phase. This is described in Section 16.2.2: Clock generation on page 341.
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The SSC works by taking the data frame (2 to 16 bits) from a transmission buffer and
placing it into a shift register. It then shifts the data at the serial clock frequency out of the
output pin and synchronously shifts in data coming from the input pin. The number of bits
and the direction of shifting (MSB or LSB first) are programmable. This is described in
Section 16.2.4: Shift register on page 343.
b. On the STi7105, by default the two serial data in/out signals can be multiplexed on to a single pin for IC mode
(full-duplex mode is not supported).
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8137791 RevA
16.2
STi7105

Figure 51. SSC architecture
Serial clock in
Clock edge
detector
Serial clock out
Clock
generator
Master/slave
select
Shift register
and control
Serial data out
Loopback
control
Serial data out
Enable
control
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Interrupt, error
Receive
buffer
Transmit
buffer
Peripheral interface
After the data frame has been completely shifted out of the shift register, it transfers the
received data frame into the receive buffer. The transmit and receive buffers are described in
Section 16.2.7: Transmit and receive buffers on page 344. The SSC is therefore double
buffered. This allows back-to-back transmission and reception of data frames up to the
speed that interrupts can be serviced.
The SSC can also be configured to loop the serial data output back to serial data input to
test the device without any external connections. This is described in Section
16.2.8: Loopback mode on page 345.
The SSC can be turned on and off by setting the enable control. This is described in Section
16.2.9: Enabling operation on page 345. It can be also be set to operate as a bus master or
as a bus slave device. This is described in Section 16.2.10: Master/slave operation on
page 345.
The SSC generates interrupts in a variety of situations:
when the transmission buffer is empty
when the receive buffer is full, and
when an error occurs. A number of error conditions are detected. These are described
in Section 16.2.11: Error detection on page 345.
There are additional hardware features that can be independently enabled to fully support
the IC bus standard when used in conjunction with a suitable software driver. The additional
IC hardware is described in Section 16.3: IC operation on page 347.
8137791 RevA
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Serial data in
Pin
control
16.2.1
STi7105
Pin connection and control

To fully support the SPI standard, the interface presented at the pins is:
a single clock pin, SCL, which is both an input and an output
two data pins, MTSR, and MRST, which are either inputs or outputs depending on
whether the SSC is in slave or master mode(c)
These pads are provided by three bits of a standard PIO block. Their directions (input,
output or bi-directional) can therefore be configured in software using the appropriate PIO
settings. Consequently the SSC does not need to provide automatic control of data pad
directions and does not need to provide a bi-directional clock port.
Figure 52. SSC port to PIO pin connections
OUT_ENn
Confidential
SSCn_SCLOUT
SSCn_SCLKIN
ALT_DATA_OUTn
SCL
SSC clock
DATA_FROM_PADSn
OUT_ENm
SSCn_MTSR_DOUT
SSCn_MTSR_DIN
ALT_DATA_OUTm
MTSR
DATA_FROM_PADSm
SSC data
OUT_ENp
SSCn_MRST_DOUT
SSCn_MRST_DIN
SSC
ALT_DATA_OUTp
MRST
DATA_FROM_PADSp
PIO
The pad control block inside the SSC determines which of the serial data input ports is used
to read data from (depending on the master or slave mode). It also determines which of the
serial data output ports to write data to (depending on the master or slave mode).
The deselected serial data output port is driven to ground (except in IC mode when it is
driven high). Therefore the user must ensure that the relevant PIO pad output enable is
turned off depending on the master/slave status of the SSC.
It is up to the user to ensure that the PIO pads are configured correctly for direction and
output driver type (for example, push/pull or open drain).
Throughout the rest of this document, the data out and in ports are referred to as
SERIAL_DATA_OUT and SERIAL_DATA_IN, where this is assumed to be the correct pair of
pins dependent on the master or slave mode of the SSC.
c.
340/454
On the STi7105, by default the two serial data in/out signals can be multiplexed on to a single pin (full-duplex
mode is not supported) for IC mode.
8137791 RevA
In IC mode only, the MTSR pin is used as an input and output. This means only the MTSR
pad needs to be used on the IC data line. However, for backward compatibility, it is still
possible to short MTSR and MRST data pins externally and achieve the same function (the
MRST data output is permanently driven to a high logic value and its input is ignored(c).
STi7105
16.2.2
Clock generation
If the SSC is configured to be the bus master, then it generates a serial clock signal on the
serial clock output port.
The clock signal can be controlled for polarity and phase and its period (baudrate) can be
set to a variety of frequencies.
For IC operation there are a number of additional clocking features. These are described in
Section 16.3: IC operation on page 347.
Clock control
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The polarity bit PO defines the logic level the clock idles at, that is, when the SSC is in
master mode but is between transactions. A polarity bit of 1 indicates an idle level of logic 1;
0 indicates idle of logic 0.
The phase bit PH indicates whether a pulse is generated in the first or second half of the
cycle. This is a pulse relative to the idle state of the clock line; so if the polarity is 0 then the
pulse is positive going; if the polarity is 1 then the pulse is negative going. A phase setting of
0 causes the pulse to be in the second half of the cycle while a setting of 1 causes the pulse
to occur in the first half of the cycle.
The different combinations of polarity and phase are shown in Figure 53.
Figure 53. Polarity and phase combinations
PO
PH
Pins
MTSR and MRST
Load Latch Shift Latch Shift Latch Unload
8137791 RevA
Load Latch Shift Latch Shift Latch Unload
341/454
In master mode, the serial clock SCL, is generated by the SSC according to the setting of
the phase bit PH and polarity bit PO in the control register SSCn_CTRL.
STi7105
The SSC always latches incoming data in the middle of the clock period at the point shown
in the diagram. With the different combinations of polarity and phase it is possible to
generate or not generate a clock pulse before the first data bit is latched.
Shifting out of data occurs at the end of the clock period. At the start of the first clock period
the shift register is loaded. At the end of the last clock period, the shift register is unloaded
into the receive buffer.
16.2.3
Baudrate generation
In write mode these registers are set up to program the baudrate as defined by the following
formulae:
f comms
Baudrate = -------------------------------2 S SCBR
f comms
SSCBR = ------------------------------------2 B audrate
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where SSCBR represents the content of the baudrate generator register SSCn_BRG, as an
unsigned 16-bit integer, multiplied by the baudrate prescaler register SSCn_PRE_BRG, and
fcomms represents the comms clock frequency.
At a comms clock (CLK_IC_IF_100) frequency of 100 MHz and with SSCn_PRE_BRG
programmed to 0x0001, the baudrates generated are shown in Table 57.
Table 57.
Baudrates and bit times for different SSCn_BRG reload values

Baudrate
Bit time
Reload value
Reserved. Use a reload value > 0
0x0000
5 MBaud
200 ns
0x000A
3.3 MBaud
300 ns
0x000F
2.5 MBaud
400 ns
0x0014
2.0 MBaud
500 ns
0x0019
1.0 MBaud
1 s
0x0032
100 KBaud
10 s
0x01F4
10 KBaud
100 s
0x1388
1.0 KBaud
1 ms
0xC350
The value in SSCn_BRG is used to load a counter at the start of each clock cycle. The
counter counts down until it reaches 1 and then flips the clock to the opposite logic value.
Consequently, the clock produced is twice the SSCn_BRG number of comms clock cycles.
In read mode the SSCn_BRG register returns the current count value. This can be used to
determine how far into each half cycle the counter is.
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8137791 RevA
The SSC can generate a range of different baudrate clocks in master mode. These are set
up by programming the baudrate generator register SSCn_BRG and the baudrate prescaler
register SSCn_PRE_BRG.
STi7105
16.2.4
Shift register
The shift register is loaded using the data in the transmit buffer at the start of a data frame. It
then shifts data out of the serial output port and data in from the serial input port.
The shift register can shift out LSB first or MSB first. This is programmed by the heading
control bit HB in the control register SSCn_CTRL. A logic 1 indicates that the MSB is shifted
out first and a logic 0 that the LSB shifts first.
The width of a data frame is also programmable from 2 to 16 bits. This is set by the BM bit
field of the control register SSCn_CTRL. A value of 0000 is not allowed. Subsequent values
set the bit width to the value plus one; for example 0001 sets the frame width to 2 bits and
1111 sets it to 16 bits.
For IC, bit SSCn_CTRL.BM must be programmed for a 9-bit data width.
When shifting LSB first, data comes into the shift register at the MSB of the programmed
frame width and is taken out of the LSB of the register. When shifting in MSB first, data is
placed into the LSB of the register and taken out of the MSB of the programmed data width.
This is shown for a 9-bit data frame in Figure 54.
Figure 54. 9-bit data frame shifting
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MSB
15
LSB
14
13
12
11
10
Shift direction
Data in
Data out
LSB first direction (HB = 0)
LSB
MSB
15
14
13
12
11
10
Shift direction
Data in
MSB first direction (HB = 1)
Data out
The shift register shifts at the end of each clock cycle. The clock pulse for shifting is
presented to it from the clock generator (see Section 16.2.2: Clock generation on page 341).
This is regardless of the polarity or phase of the clock.
When a complete data frame has been shifted, the contents of the shift register (that is, all
bits shifted into the register) is loaded into the receive buffer.
There are some additional controls required on the shifting operation to allow full support of
the IC bus standard. These are described in Section 16.3: IC operation on page 347.
16.2.5
Receive data sampling

The data received by the SSC is sampled after the latching edge of the input clock, the
latching edge being determined by the programming of the polarity and phase bits.
8137791 RevA
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Note:
STi7105
The data value that is finally latched is determined by taking three data samples at the third,
fourth and fifth comms clock periods after the latching data edge. The data value is
determined from the predominant data value in the three samples. This gives an element of
spike suppression.
16.2.6
Antiglitch filter
The antiglitch filter suppresses any pulses that have a value in microseconds of less than a
programmed width. Such signals may be either high or low. The filter has two registers,
SSCn_NOISE_SUPP_WID and SSCn_PRESCALER.
The comms clock is divided by a prescaler factor equivalent to 10 MHz, before being fed to
the antiglitch filter. For example, if the comms clock is 100 MHz the prescaler division factor
is 10, the value programmed in SSCn_PRESCALER register.
16.2.7
Transmit and receive buffers
Confidential
The transmit and receive buffers are used to allow the SSC to do back-to-back transfers;
that is, continuous clock and data transmission.
The transmit buffer SSCn_TBUFF is written with the data to be sent out of the SSC. This is
loaded into the shift register for transmission. Once this has been performed, the
SSCn_TBUFF is available to be loaded again with a new data frame. This is indicated by the
assertion of the status bit SSCn_STA.TIR, which indicates that the transmit buffer is empty.
This causes an interrupt if the transmit buffer empty interrupt is enabled, by setting the
SSCn_INT_EN.TI_EN bit in the interrupt enable register.
A transmission is started in master mode by a write to the transmit buffer. This starts the
clock generation circuit and loads the shift register with the new data.
Continuous transfers of data are therefore possible by reloading the transmit buffer
whenever the interrupt is received. The software interrupt routine has the length of time for a
complete data frame to refill the buffer before it is next emptied. If the transmit buffer is not
reloaded in time when in slave mode, a transmit error condition (see Section 16.2.11: Error
detection) is generated and flagged by the SSCn_STA.TE bit.
The number of bits to be loaded into the transmit buffer is determined by the frame data
width selected in the control register bit SSCn_CTRL.BM. The unused bits are ignored.
The receive buffer SSCn_RBUFF is loaded from the shift register when a complete data
frame has been shifted in. This is indicated by the assertion of the status bit
SSCn_STA.RIR, which indicates that the receive buffer is full. This causes an interrupt if the
receive buffer full interrupt is enabled, by setting the SSCn_INT_EN.RI_EN bit in the
interrupt enable register.
The CPU should then read out the contents of this register before the next data frame has
been received, otherwise the buffer is reloaded from the shift register over the top of the
previous data. This is indicated as a receive error condition at SSCn_STA.RE. See Section
16.2.11: Error detection.
The number of bits loaded into the receive buffer is determined by the frame data width
selected in the control register SSCn_CTRL.BM. The unused bits are not valid and should
be ignored.
344/454
8137791 RevA
SSCn_NOISE_SUPP_WID holds the value of maximum glitch width. To suppress glitches of

n microseconds or less, the value n + 1 is written into the register. Writing 0x00 bypasses
the antiglitch filter.
STi7105
16.2.8
Loopback mode
A loopback mode is provided that connects the SERIAL_DATA_OUT to SERIAL_DATA_IN.
This allows software testing to be performed without the need for an external bus device.
This mode is enabled by setting the control register bit SSCn_CTRL.LPB. A setting of logic
1 enables loopback; logic 0 puts the SSC into normal operation.
16.2.9
Enabling operation
16.2.10
Master/slave operation
Confidential
The control of a number of the features of the SSC depends on whether the block is in
master or slave mode. For example, in master mode the SSC generates the serial clock
signal according to the setting of baudrate, polarity and phase. In slave mode, no clock is
generated and instead the assumption is made that an external device is generating the
serial clock.
Master or slave mode is set by the control register bit SSCn_CTRL.MS. A setting of logic 0
means the SSC is in slave mode, a setting of logic 1 puts the device into master mode.
16.2.11
Error detection
A number of different error conditions can be detected by the SSC. These are related to the
mode of operation (master or slave, or both).
On detection of any of these error conditions a status flag is set in the status register,
SSCn_STA. Also, if the relevant enable bit is set in the interrupt enables register
SSCn_INT_EN, then an error interrupt is generated from the SSC.
The different error conditions are described as follows.
Transmit error
A transmit error can be generated both in master and in slave mode. It indicates that a
transfer has been initiated by a remote master device before a new transmit data buffer
value has been written into the SSC.
In other words, the error occurs when old transmit data is going to be transmitted. This could
cause data corruption in the half-duplex open drain configuration.
The error condition is indicated by the setting of the SSCn_STA.TE bit in the status register.
An interrupt is generated if the SSCn_INT_EN.TE_EN bit is set in the interrupt enable
register.
The transmit error status bit (and the interrupt, if enabled) is cleared by the next write to the
transmit buffer.
Receive error
A receive error can be generated in both master and slave modes. It indicates that a new
data frame has been completely received into the shift register and has been loaded into the
8137791 RevA
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The transmission and reception of data by the SSC block can be enabled or disabled by
setting the control register bit SSCn_CTRL.EN. A setting of logic 1 turns on the SSC block
for transmission and reception. Logic 0 prevents the block from reading or writing data to the
serial data input and output ports.
STi7105
receive buffer before the existing receive buffer contents have been read out. Consequently,
the receive buffer has been overwritten with new data and the old data is lost.
The error condition is indicated by the setting of the SSCn_STA.RE bit in the status register.
An interrupt is generated if the SSCn_INT_EN.RE_EN bit is set in the interrupt enable
register.
The receive error status bit (and the interrupt, if enabled) is cleared by the next read from the
receive buffer.
A phase error can be generated in master and slave modes. This indicates that the data
received at the incoming data pin (MRST in master mode or MTSR in slave mode) has
changed during the time from one sample before the latching clock edge and two samples
after the edge.
The data at the incoming data pin is supposed to be stable around the time of the latching
clock edge, hence the error condition. Each sample occurs at the comms clock frequency.
The sampling scheme is shown in Figure 55.
Confidential
Figure 55. Sampling scheme
Comms clock
Serial clock in
SERIAL_DATA_IN
Sampling points
Phase error?
No
No
Yes
The error condition is indicated by the setting of the SSCn_STA.PE bit in the status register.
An interrupt is generated if the SSCn_INT_EN.PE_EN bit is set in the interrupt enable
register. The phase error status bit (and the interrupt, if enabled) is cleared by the next read
from the receive buffer.
16.2.12
Interrupt mechanism
The SSC can generate a variety of different interrupts. They can all be enabled or disabled
independently of each other. All the enabled interrupt conditions are ORed together to
generate a global interrupt signal.
To determine which interrupt condition has occurred, a status register SSCn_STA is
provided which includes a bit for each condition. This is independent of the interrupt enables
346/454
8137791 RevA
Phase error
STi7105

register SSCn_INT_EN, and determines whether the condition asserts one or more of the
interrupt signals.
16.3
IC operation
This section describes the additional hardware features, which are implemented to allow full
support for the IC bus standard.
The architecture of the IC, including all the IC hardware additions is shown in Figure 56.
Serial clock in
Clock
generator
Clock stretcher
START/STOP
generator
IC control
Confidential
Serial clock out
START/STOP
detect
Acknowledge
generator
Slave address
comparison
Arbitration
checker
Shift register
Serial data in
Serial data out
Transmit buffer
Receive buffer
Peripheral interface
8137791 RevA
347/454
Figure 56. IC architecture
16.3.1
STi7105
IC control
To allow slow slave devices to be accessed and to allow multiple master devices to
generate a consistent clock signal, a clock synchronization mechanism is specified.
START and STOP conditions must be recognized when in slave mode or multi-master
mode. A START condition initiates the address comparison phase. A STOP condition
indicates that a master has completed transmission and that the bus is now free.
In slave mode (and in multi-master configurations), it is necessary to determine if the

first byte received after a START condition is the address of the SSC. If it is, then an
acknowledge must be generated in the ninth bit position.
Subsequently, an interrupt must be generated to inform the software that the SSC has been
addressed as a slave device and therefore that it needs to either send data to the
addressing master or to receive data from it.
In addition to normal 7-bit addressing, there is an extended 10-bit addressing mode where
the address is spread over two bytes. In this mode, the SSC must compare two consecutive
bytes with the incoming data after a START condition. It must also generate acknowledge
bits for the first and second bytes automatically if the address matches.
Confidential
The 10-bit addressing mode is further complicated by the fact that if the slave has been
previously addressed for writing with the full two-byte address, the master can issue a
repeated START condition and then transmit just the first address byte for a read. The slave
therefore must remember that it has already been addressed and must respond.
For the software interrupt handler to have time to service interrupts, the SSC can hold
the clock line low until the software releases it. This is called clock stretching.
In master mode the SSC must begin a transmission by generating a START condition
and must end transmission by generating a STOP condition. In multi-master
configurations a START condition should not be generated if the bus is already busy;
that is, a START condition has already been received.
When the SSC is receiving data from another device, it must generate acknowledge
bits in the ninth bit position. However, when receiving data as a master, the last byte
received must not be acknowledged. This applies only to data bytes: when operating as
a slave device the SSC should always acknowledge a matching address byte; that is,
the first byte after a START condition.
In multi-master configurations, arbitration must take place because it is not possible to

determine if another master is also trying to transmit to the bus; that is, the START
conditions were generated within the allowed time frame.
Arbitration involves checking that the data being transmitted is the same as the data
received. If this is not the case, then we have lost arbitration. The SSC must then continue to
transmit a high logic level for the rest of the byte to avoid corrupting the bus.
It is also possible that, having lost arbitration, it is addressed as a slave device. So the SSC
must then go into slave mode and compare the address in the normal fashion (and generate
an acknowledge if it was addressed).
After the byte plus acknowledge the SSC must indicate to the software that we have lost
arbitration by setting a flag.
All of these features are provided in the SSC block. They are controlled by the IC control
block, which interacts with various other modules to perform the protocols.
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8137791 RevA
There are a number of features of the IC-bus protocol that require special control.
STi7105
To program the slave address of the SSC the slave address register, SSCn_SLA_ADDR
must be written to with the address value. In the case of 7-bit addresses, only 7 bits should
be written. For 10-bit addressing, the full 10 bits are written. The SSC then uses this register
to compare the slave address transmitted after a START condition (see Section
16.3.4: Slave address comparison on page 352). To perform 10-bit address comparison and
address acknowledge generation, the 10-bit addressing mode register bit
SSCn_I2C_CTRL.AD10 must be set (see Section 16.3.4: Slave address comparison).
Confidential
The clock stretching mechanism is enabled for various interrupt conditions when the IC
control enable register bit SSCn_I2C_CTRL.I2CM is set (see Section 16.3.5: Clock
stretching on page 352).
To generate a START condition, the IC START condition generate bit
SSCn_I2C_CTRL.STRTG must be set (see Section 16.3.6: START/STOP condition
generation on page 353). To generate a STOP condition, the IC STOP condition generate
bit SSCn_I2C_CTRL.STOPG must be set (see Section 16.3.6: START/STOP condition
generation).
To generate acknowledge bits (that is, a low data bit) after each 8-bit data byte when
receiving data, the acknowledge generation bit SSCn_I2C_CTRL.ACKG must be set. When
receiving data as a master, this bit must be reset to 0 before the final data byte is received,
thereby signalling to the slave to stop transmitting (see Section 16.3.7: Acknowledge bit
generation on page 354).
To indicate to the software that various situations have arisen on the IC bus, a number of
status bits are provided in the status register SSCn_STA. In addition, some of these bits can
generate interrupts if corresponding bits are set in the interrupt enable register
SSCn_INT_EN.
To indicate that the SSC has been accessed as a slave device, the addressed as slave
register bit SSCn_STA.AAS is set. This also causes an interrupt if the register bit
SSCn_INT_EN.AAS_EN is set.
The interrupt occurs after the SSC has generated the address acknowledge bit. In 10-bit
addressing mode, where two bytes of address are sent, the interrupt occurs after the
second byte acknowledge bit; it occurs after the first byte acknowledge where only one byte
is required.
Until the status bit is reset, the SSC holds the clock line low (see Section 16.3.5: Clock
stretching on page 352). This forces the master device to wait until the software has
processed the interrupt.
The status bit and the interrupt are reset by reading from the receive buffer SSCn_RBUFF,
when the slave is being sent data, and by writing to the transmit buffer SSCn_TBUFF, when
the SSC needs to send data.
To indicate that a STOP condition has been received, when in slave mode, the STOP
condition detected bit SSCn_STA.STOP is set. This also causes an interrupt if the
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To program for IC mode, a separate control register SSCn_I2C_CTRL is provided. To

perform any of the IC hardware features, the IC control bit, SSCn_I2C_CTRL.I2CM, must
be set in this register. When the IC control bit is set, the clock synchronization mechanism
is always enabled (see Section 16.3.2: Clock synchronization on page 350). When the IC
control bit is set, the START and STOP condition detection is performed. Fast mode is
supported by bit 12 SSCn_I2C_CTRL.I2CFSMODE of the control register. In addition,
register bits SSCn_CTRL.PH and SSCn_CTRL.PO must be set to 1.
STi7105
SSCn_INT_EN.STOP_EN bit is set in the interrupt enable register. The STOP interrupt and
status bit is reset by a read of the status register SSCn_STA.
To indicate that the SSC has lost the arbitration process, when in a multi-master
configuration, the arbitration lost bit SSCn_STA.ARBL in the status register is set. This also
results in an interrupt if the SSCn_INT_EN.ARBL_EN bit is set in the interrupt enable
register. The interrupt occurs immediately after the arbitration is lost.
Until the status bit is reset, the SSC holds the clock line low at the end of the current data
frame, (see Section 16.3.5: Clock stretching). This forces the winning master device to wait
until the software has processed the interrupt.
To indicate that the IC bus is busy (that is, between a START and a STOP condition), the
IC bus busy bit SSCn_STA.BUSY in the status register is set. This does not generate an
interrupt.
16.3.2
Clock synchronization
Confidential
The IC standard defines how the serial clock signal can be stretched by slow slave devices
and how a single synchronized clock is generated in a multi-master environment. The clock
synchronization of all the devices is performed as follows.
All master devices start generating their low clock pulse when the external clock line goes
low (this may or may not correspond with their own generated high-to-low transition).
They count out their low clock period and when finished attempt to pull the clock line high.
However, if another master device is attempting to use a slower clock frequency, then it is
holding the clock line low; or if a slave device wants to, it can extend the clock period by
deliberately holding the clock low.
Because the output drive is open-drain, the slower clock wins and the external clock line
remains low until this device has finished counting its slow clock pulse, or until the slave
device is ready to proceed. Meanwhile, the quicker master device has detected a
contradiction and goes into a wait state until the clock signal goes high again.
After the external clock signal goes high, all the master devices begin counting off their high
clock pulse. In this case the first master to finish counting attempts to pull the external clock
line low and wins (because of the open drain line). The other master devices detect this and
abort their high pulse count and switch to counting out their low clock pulse.
Consequently, the quicker master device determines the length of the high clock pulse and
the slowest master or slave device determines the length of the low clock pulse.
This results in a single synchronized clock signal which all master and slave devices then
use to clock their shift registers.
The synchronization and stretching mechanism is shown in Figure 57.
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8137791 RevA
The interrupt and status bit is reset by a read of the status register SSCn_STA.
STi7105

Figure 57. Synchronization and stretching
Master 1
Master 2
Master 2
high period
Slave
stretch
Confidential
Slave
stretched
The SSC implements this clock synchronization mechanism when the IC control bit
SSCn_I2C_CTRL.I2CM, is enabled.
16.3.3
START/STOP condition detection

START/STOP conditions are generated only by a master device. A slave device must detect
the START condition and expect the next byte (or two bytes in 10-bit addressing) to be a
slave address. A STOP condition is used to signal when the bus is free.
A START condition occurs when the transmit/receive data line changes from high to low
during the high period of the clock line. It indicates that a master device wants control of the
bus. In a single master configuration, it automatically gets control. In a multi-master
configuration, it begins to transmit as part of the arbitration procedure, and may or may not
get control (see Section 16.3.8: Arbitration checking on page 354).
A STOP condition occurs when the transmit/receive data line changes from low to high
during the high period of the clock line. It indicates that a master device has relinquished
control of the bus (the bus is made free a specified time after the stop condition).
An additional piece of hardware is provided on the SSC to detect START and STOP
conditions. This is necessary in slave mode because detection cannot be performed in time
merely by programming the PIO pads. This is because there is not sufficient time for a
software interrupt between the end of the START condition and the beginning of the data
transmitted by a remote master.
START and STOP conditions are detected by sampling the data line continuously when the
clock line is high. Minimum set up and hold times are measured by the counters.
The START condition is detected when data goes low (and the clock is high) and remains
low for the minimum time specified by the IC standard.
The STOP condition is detected when data goes high (and the clock is high) and remains
high for the minimum time specified by the IC standard.
START and STOP condition detection is enabled when the IC control bit I2CM is set in the
IC control register.
8137791 RevA
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Master 1
low period
Resultant
clock
STi7105
When a START condition is triggered, the SSC informs the IC control block, which then
initiates the address comparison phase.
When a STOP condition is triggered, the SSC sets the STOP bit in the status register. It also
generates an interrupt if the SSCn_INT_EN.STOP_EN bit is set in the interrupt enable
register.
The interrupt and the status bit are cleared when the status register is read.
16.3.4
Slave address comparison
It receives the first eight bits of the next byte transmitted and compares the first seven bits
against the address stored in the slave address register SSCn_SLA_ADDR. If they match,
the address comparison block indicates this to the IC control block.
Confidential
This generates an acknowledge bit in the next bit position and sets the addressed as slave
bit AAS in the status register. An interrupt is then generated after the acknowledge bit if the
addressed as slave enable bit SSCn_INT_EN.AAS_EN is set in the interrupt enable
register.
The eighth bit of the first byte indicates whether the SSC is written to (low) or read from
(high). This is used by the control block to determine if it needs to acknowledge the following
data bytes (that is, when receiving data).
When 10-bit addressing mode is selected by setting the 10-bit addressing
SSCn_I2C_CTRL.AD10 register bit, the first seven bits of the first data byte is compared
against 11110nn, where nn is the two most significant bits of the 10-bit address stored in the
slave address register.
The read/write bit then determines what to do next.
If the read/write bit is low, indicating a write, an acknowledge must be generated for the byte.
The addressed as slave status bit and interrupt however are not yet asserted so, instead,
the address comparator waits for the next data byte and compares this against the eight
least significant bits of the slave address register.
If this matches, then the SSC is being addressed, therefore the second byte is
acknowledged and the addressed as slave bit is set. An interrupt also occurs after the
acknowledge bit if the addressed as slave interrupt enable is set.
On the other hand if the first byte sent has the read/write bit high, then the SSC
acknowledges it only if it has previously been addressed and a STOP condition has not yet
occurred (that is, the master has generated a repeated START condition). In this case the
addressed as slave bit is set after the first byte plus acknowledge and an interrupt is
generated if the interrupt enable is set. The second byte in this case is sent by the SSC
because this is a read operation.
In all cases if the address does not match, then the SSC ignores further data until a STOP
condition is detected.
16.3.5
Clock stretching
The IC standard allows slave devices to hold the clock line low if they need more time to
process the data being received (see Section 16.3.2: Clock synchronization on page 350).
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8137791 RevA
After a START condition has been detected, the SSC goes into the address comparison
phase.
STi7105

The SSC takes advantage of this by inserting extended clock low periods. This is done to
allow a software device driver to process the interrupt conditions when in slave mode.
When the SSC has been addressed as a slave device and the interrupt has been
enabled. The clock stretch occurs immediately after the first byte with acknowledge,
after a START condition has occurred (or in the case of 1-bit addressing this might
occur after the second byte plus acknowledge). This gives the software interrupt routine
time to initialize for transmission or reception of data. The clock stretch is cleared by
writing 0x1FF to the transmit buffer register.
When the SSC is in slave mode and is transmitting or receiving. The clock stretch
occurs immediately after each data byte plus acknowledge. When transmitting, this
allows the software interrupt routine to check that the master has acknowledged before
writing the next data byte into the transmit buffer. If no acknowledge is received, then
the software must stop transmitting bytes. When receiving, it allows the software to
read the next data byte before the master starts to send the next one. The clock stretch
is cleared by a write to the transmit buffer when transmitting and by a read from the
receive buffer when receiving.
When the SSC loses arbitration. The clock stretch occurs immediately after the current
data byte and acknowledge have been performed only if the master that has lost
arbitration has been addressed. This gives the software time to abort its current
transmission and to prepare to retry after the next STOP condition. The clock stretch is
not performed if the master which has lost arbitration has not been addressed.
If a clock stretching event occurs but no relevant interrupt is enabled then the clock is
stretched indefinitely. Hence it is important that the correct interrupts are always enabled.
16.3.6
START/STOP condition generation

As a master device the SSC must generate a START condition before transmission of the
first byte can start. It may also generate repeated START conditions. It must complete its
access to the bus with a STOP condition.
Between STOP and START conditions, the bus is free and the clock and data lines must be
held high. The IC control block determines this and instructs the START/STOP generator to
hold the lines high between transactions.
The START/STOP generator is controlled by the START condition generate bit STRTG and
the STOP condition generate bit STOPG in register SSCn_I2C_CTRL.
The generator pulls the SERIAL_DATA_OUT line low during the high period of the clock to
produce a START condition. In the case of a STOP condition it pulls the data line high.
However, a START condition is generated only if the bus is currently free (that is, the BUSY
bit in the status register is low). This is to prevent the SSC from generating a START
condition when another master has just generated one.
If a START condition cannot be generated because the bus is busy, then the generator
forces the arbitration checker to generate an arbitration lost interrupt and prevent data from
being transmitted for the next byte. The software interrupt handler is therefore informed of
the aborted transmission when servicing the interrupt. Bit 11 (REPSTRT) of register
SSCn_STA shows that a repeated start condition has occurred.
To properly generate the timing waveforms of the START and STOP conditions, the SSC
contains a timing counter. This ensures the minimum setup and hold times are met with
some additional margin.
8137791 RevA
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Confidential
The clock stretching mechanism is used in the situations listed below.
16.3.7
STi7105
Acknowledge bit generation

For IC operation, it is required both to detect acknowledge bits when transmitting data, and
to generate them when receiving data.
An acknowledge bit must be transmitted by the receiver at the end of every 8-bit data frame.
The transmitter must verify that an acknowledge bit has been received before continuing.
The acknowledge bit is generated by the receiver after the eight data bits have been
transferred to it. In the ninth clock pulse, the transmitter holds the data line high and the
receiver must pull the line low to acknowledge receipt. If the receiver is unable to
acknowledge receipt, then the master generates a stop condition to abort the transfer.
Confidential
Acknowledge bits are generated by the SSC when the acknowledge generation bit,
SSCn_I2C_CTRL.ACKG, is set in the IC control register. They are generated only when
receiving data.
When in master mode and receiving data the ACKG bit should be set to 0 before the last
byte to be received. The SSC automatically generates acknowledge bits when addressed as
a slave device.
Bit 10 SSCn_INT_EN.NACK_EN of the interrupt enable register permits the setting of an
interrupt on a NACK condition.
16.3.8
Arbitration checking
This situation arises only when two or more master devices generate a START condition
within the minimum hold time of the bus standard. This generates a valid start condition on
the bus with more than one master valid.
However, a master device cannot determine if two or more masters have generated a
START condition, so arbitration is always enabled. The arbitration for which device wins
control of the bus is determined by which master is the first to transmit a low data bit on the
data line when the other master wants to send a high bit. This master wins control of the
bus. Therefore a master that detects a different data bit on its input to that which it
transmitted must switch off its output stage for the rest of the eight bit data byte, because it
has lost the arbitration.
The arbitration scheme does not affect the data transmitted by the winning master.
Consequently, arbitration proceeds concurrently with data transmission and the data
received by the selected slave during the arbitration process. It is valid that the winning
master is actually addressing the losing master and hence this device must respond as if it
were a slave device.
Arbitration is implemented in hardware by comparing the transmitted and received data bits
every cycle. Loss of arbitration is indicated by the setting of the SSCn_STA.ARBL arbitration
lost error flag in the status register. An interrupt also occurs if the SSCn_INT_EN.ARBL_EN
bit is set in the interrupt enables register.
Loss of arbitration also causes a clock stretch to be inserted if the master that has lost
arbitration has been addressed. The interrupt and the clock stretch occurs immediately after
the eight bits plus acknowledge. The clock stretch is cleared when the software reads the
receive buffer.
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8137791 RevA
An acknowledge bit is not generated by a master receiver for the last byte it wishes to
receive. This not acknowledge is used by the slave device to determine when to stop
transmission.
STi7105
Synchronous serial controller (SSC) registers
17
Caution:
Register addresses are provided as SSCnBaseAddress + offset.
The SSCnBaseAddresses are:
SSC0BaseAddress: 0xFD04 0000
Confidential
Table 58.
SSC register summary
Offset
Register
Description
Page
0x000
SSCn_BRG
SSCn baudrate generation
page 356
0x004
SSCn_TBUFF
SSCn transmit buffer
page 356
0x008
SSCn_RBUFF
SSCn receive buffer
page 356
0x00C
SSCn_CTRL
SSCn control
page 357
0x010
SSCn_INT_EN
SSCn interrupt enable
page 358
0x014
SSCn_STA
SSCn status
page 359
0x018
SSCn_I2C_CTRL
SSCn IC control
page 360
0x01C
SSCn_SLA_ADDR
SSCn slave address
page 360
0x020
SSCn_REP_START_HOLD_TIME
Programming repeated start hold time

count value
page 361
0x024
SSCn_START_HOLD_TIME
Programming start hold time count value page 361
0x028
SSCn_REP_START_SETUP_TIME
Programming repeated start setup time

count value
page 361
0x02C
SSCn_DATA_SETUP_TIME
Programming data setup time count

value
page 361
0x030
SSCn_STOP_SETUP_TIME
Programming stop setup time count

value
page 362
0x034
SSCn_BUS_FREE_TIME
Programming bus free time count value
page 362
0x038
SSCn_TX_FSTAT
Transmitter FIFO status
page 362
0x03C
SSCn_RX_FSTAT
Receiver FIFO status
page 363
0x040
SSCn_PRE_BRG
Programming prescaler value for clock
page 363
0x080
SSCn_CLR_STA
Clear status bits
page 363
0x100
SSCn_NOISE_SUPP_WID
Noise suppression width
page 364
0x104
SSCn_PRESCALER
Clock prescaler for glitch suppression
page 364
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Table 58.
SSC register summary
Offset
Register
Description
0x108
SSCn_NOISE_SUPP_WID_DOUT
Noise suppression max output data delay

page 365
width
0x10C
SSCn_PRE_SCALER_DATAOUT
Prescaler data out
SSCn_BRG
15
14
STi7105
Page
page 365
SSCn baudrate generation

13
12
11
10
Address:
SSCnBaseAddress + 0x000
Type:
RW
Reset:
0x01
Description:
This register is dual purpose. When reading, the current 16-bit counter value is
returned. When a value is written to this address, the 16-bit reload register is loaded
with that value.
When in slave mode, BRG must be zero.
BRG is changed only when initialization of the master is performed for a master
transaction. When the SSC is master and either the addressed as slave or arbitration
lost interrupts are fired, then BRG must be reset to 0.
SSCn_TBUFF
15
14
SSCn transmit buffer
13
12
11
10
TD[15:0]
Address:
Type:
Reset:
0x00
Description:
Transmit buffer data.
[15:0] TD[15:0]: Transmit buffer data D15:D0.
SSCn_RBUFF
15
14
SSCn receive buffer
13
12
11
10
RD[15:0]
Address:
Type:
Reset:
0x00
Description:
Receive buffer data.
[15:0] RD[15:0]: Receive buffer data D15:D0.
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8137791 RevA
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BRG
STi7105
10
LPB
EN
MS
SR
PO
PH
HB
Address:
SSCnBaseAddress + 0x00C
Type:
RW
Reset:
0x00
Description:
[15:14] RESERVED
Confidential
[13] CLKST_RX_EN: Enable clock strech mechanism for receiving devices.

0: Mechanism disabled.
1: Mechanism enabled.
[12] RX_FIFO_EN: Enable Rx side FIFO
0 FIFO bypassed
1 FIFO enabled
[11] TX_FIFO_EN: Enable Tx side FIFO

0 FIFO bypassed
1 FIFO enabled
[10] LPB: SSC loopback

0: Disabled
1: Shift register output is connected to shift register input
[9] EN: SSC enable
0: Transmission and reception disabled
1: Transmission and reception enabled
[8] MS: SSC master select

0: Slave mode
1: Master mode
[7] SR: SSC software reset

0: Device is not reset
1: All functions are reset while this bit is set
[6] PO: SSC clock polarity control

0: Clock idles at logic 0
Must be set in IC mode.
1: Clock idles at logic 1
[5] PH: SSC clock phase control

0: Pulse in second half cycle
Must be set in IC mode.
1: Pulse in first half cycle
[4] HB: SSC heading control

0: LSB first
1: MSB first
[3:0] BM: SSC data width selection (reset value is illegal)

0000: Reserved, do not use this combination 0001: 2 bits
0010: 3 bits
up to
1111: 16 bits
8137791 RevA
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11
BM
12
RESERVED
13
CLKST_RX_EN
14
RESERVED
15
SSCn control
RX_FIFO_EN
SSCn_CTRL
RE_EN
TE_EN
TI_EN
RI_EN
Address:
Type:
RW
Reset:
0x00
Description:
This register holds the interrupt enable bits, which can be used to mask the interrupts.
[31:15] RESERVED
[14] RHFI_EN: Receiver FIFO half full interrupt enable
1: Interrupt enabled
[13] TFI_EN: Transmit FIFO full interrupt enable.
1: Interrupt enabled.
Confidential
[12] THEI_EN: Transmit FIFO half empty interrupt enable.

[11] REPSTRT_EN: I2C repeated start condition interrupt enable
1: Repeated condition interrupt enabled
[10] NACK_EN: I2C NACK condition interrupt enable
1: NACK condition interrupt enabled
[9] RESERVED
[8] ARBL_EN: I2C arbitration lost interrupt enable
1: Arbitration lost interrupt enabled
[7] STOP_EN: I2C stop condition interrupt enable
1: Stop condition interrupt enabled
[6] AAS_EN: I2C addressed as slave interrupt enable
1: Addressed as slave interrupt enabled
[5] RESERVED
[4] PE_EN: Phase error interrupt enable
1: Phase error interrupt enabled
[3] RE_EN: Receive error interrupt enable
1: Receive error interrupt enabled
[2] TE_EN: Transmit error interrupt enable
1: Transmit error interrupt enabled
[1] TI_EN: Transmitter buffer empty interrupt enable
1: Transmitter buffer empty interrupt enabled
[0] RI_EN: Receiver buffer full interrupt enable
1: Receiver buffer interrupt enabled
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8137791 RevA
PE_EN
AAS_EN
RESERVED
ARBL_EN
NACK_EN
REPSTRT_EN
TFI_EN
THEI_EN
RHFI_EN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STOP_EN
SSCn interrupt enable

RESERVED
SSCn_INT_EN
STi7105
STi7105
CLST
PE
RE
TE
TIR
Address:
Type:
Reset:
0x02 (all active bits clear except TIR)
RIR
AAS
STOP
10
ARBL
11
BUSY
TXF
12
NACK
13
REPSTRT
14
TXHE
15
RXHF
SSCn status
RESERVED
SSCn_STA
Description:
[15] RESERVED
[14] RXHF: Receive FIFO half full bag.
1: Receive FIFO is half full.
Confidential
[13] TXF: Transmit FIFO full flag.

1: Transmit FIFO is full.
[12] TXHE: Transmit FIFO half empty flag.
1: TX FIFO is half empty.
[11] REPSTRT: I2C repeated start flag
1: I2C repeated start condition detected
[10] NACK: I2C NACK flag
1: NACK received
[9] BUSY: I2C bus busy flag
1: I2C bus busy
[8] ARBL: I2C arbitration lost flag
1: Arbitration lost
[7] STOP: I2C stop condition flag
1: Stop condition detected
[6] AAS: I2C addressed as slave flag
1: Addressed as slave device
[5] CLST: I2C clock stretch flag
1: Clock stretching in operation
[4] PE: Phase error flag
1: Phase error set
[3] RE: Receive error flag
1: Receive error set
[2] TE: Transmit error flag
1: Transmit error set
[1] TIR: Transmitter buffer empty flag
1: Transmitter buffer empty
[0] RIR: Receiver buffer full flag
1: Receiver buffer full
8137791 RevA
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STi7105
Address:
Type:
RW
Reset:
0x00
Description:
To suit I2C specifications, bits PH and PO of register SSCn_CTRL must also be set to
1.
[31:12] RESERVED
[11] REPSTRTG: SSC I2C generate repeated START condition
0: Disabled
1: Enabled
[10:6] RESERVED
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[5] TX_EN: SSC I2C transaction enable control

0: Disabled
2C
[4] AD10: SSC I

0: Disabled
10-bit addressing control

1: Use 10 bit addressing
2C
[3] ACKG: SSC I

0: Disabled
generate acknowledge bits

1: Generate acknowledge bits when receiving
[2] STOPG: SSC I

0: Disabled
2C
[1] STRTG: SSC I

0: Disabled
2C
generate STOP condition

1: Generate a STOP condition
2C
[0] I2CM: SSC I

0: Disabled
1: Enabled
generate START condition

1: Generate a START condition
control
1: Enable I2C features
[31:12] RESERVED
SSCn_SLA_ADDR
15
14
13
12
RESERVED
SSCn slave address

11
10
SL[9:7]
SL[6:0]
Address:
Type:
Reset:
0x00
Description:
The slave address is written into this register. If the address is a 10-bit address it is
written into bits [9:0]. If the address is a 7-bit address then it is written into bits [6:0].
360/454
8137791 RevA
I2CM
TX_EN
STRTG
ACKG
STOPG
8
RESERVED
REPSTRTG
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
AD10
SSCn I2C control
SSCn_I2C_CTRL
STi7105
SSCn_REP_START_HOLD_TIME
15
14
13
12
11
10
Programming repeated start hold time count

value
9
Address:
Type:
RW
Reset:
0x01
Description:
The value in this register corresponds to the IC repeated start hold time requirement.
[15:0] REP_START_HOLD_TIME:
time = clock_period * (value in register)
SSCn_START_HOLD_TIME
15
14
13
12
11
Programming start hold time count value

10
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START_HOLD_TIME
Address:
Type:
RW
Reset:
0x01
Description:
The value in this register corresponds to the IC start hold time requirement.
[15:0] START_HOLD_TIME:
SSCn_REP_START_SETUP_TIME
15
14
13
12
11
10
Programming repeated start setup time

count value
REP_START_SETUP_TIME
Address:
Type:
RW
Reset:
0x01
Description:
The value in this register corresponds to the IC repeated start setup time
requirement.
[15:0] REP_START_SETUP_TIME:
SSCn_DATA_SETUP_TIME
15
14
13
12
11
Programming data setup time count value

10
DATA_SETUP_TIME
Address:
Type:
RW
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REP_START_HOLD_TIME

Reset:
STi7105
0x01
Description:
The value in this register corresponds to the IC data setup time requirement.
[15:0] DATA_SETUP_TIME:
SSCn_STOP_SETUP_TIME
15
14
13
12
11
Programming stop setup time count value

10
Address:
Type:
RW
Reset:
0x01
Description:
The value in this register corresponds to the IC stop setup time requirement.
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[15:0] STOP_SETUP_TIME:
SSCn_BUS_FREE_TIME
15
14
13
12
11
Programming bus free time count value

10
BUS_FREE_TIME
Address:
Type:
RW
Reset:
0x01
Description:
The value in this register corresponds to the IC bus free time requirement.
[15:0] BUS_FREE_TIME:
SSCn_TX_FSTAT
15
14
13
12
Transmitter FIFO status

11
10
RESERVED
Address:
Type:
Reset:
0x00
Description:
This register depicts the Tx FIFO status.
[15:3] RESERVED
[2:0] SSCTXF_STA: Tx FIFO status - number of words in the Tx FIFO:
000: 0 (empty)
100: 4
001: 1
101: 5
010: 2
110: 6
011: 3
111: 7 (full)
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8137791 RevA
SSCTXF_STA
STOP_SETUP_TIME
STi7105
SSCn_RX_FSTAT
15
14
13
12
Receiver FIFO status

11
10
RESERVED
SSCRXF_STA
Address:
Type:
Reset:
0x00
Description:
This register depicts the Rx FIFO status.

[2:0] SSCRXF_STA: Rx FIFO status
Register contains the number of words in the Rx FIFO:
000: 0 (empty)
100: 4
001: 1
101: 5
010: 2
110: 6
011: 3
111: 7 (full)
15
14
13
12
Programming prescaler value for clock

11
10
PRE_SCALER_BRG
Address:
Type:
RW
Reset:
0x01
Description:
The value in this register is used to further pre-scale the clock generated according to
the programming of the baud rate. It can be used in conjunction with the programming
in register SSCn_BRG to slow down the serial clock generated to operate at lower
frequencies.
[15:0] PRE_SCALER_BRG: Pre-scaling the BRG clock
Address:
Type:
RW
Reset:
0x00
Description:
Clear bits in SSCn_STA.
RESERVED
CLR_SSCAAS
CLR_SSCARBL
CLR_NACK
CLR_REPSTRT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CLR_SSCSTOP
Clear status bits

RESERVED
SSCn_CLR_STA
RESERVED
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SSCn_PRE_BRG
[31:12] RESERVED
[11] CLR_REPSTRT:
1: Clear REPSTRT
8137791 RevA
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[15:13] RESERVED
STi7105
[10] CLR_NACK:
1: Clear SCCNACK
[9] RESERVED
[8] CLR_SSCARBL:
1: Clear SSC_ARBL
[7] CLR_SSCSTOP:
1: Clear SSC_STOP
[6] CLR_SSCAAS:
1: Clear SSC_AAS
SSCn_NOISE_SUPP_WID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NOISE_SUPP_WID
Address:
Type:
RW
Reset:
0x00
Description:
The value, in microseconds, in this register determines the maximum width of noise
pulses which the filter suppresses. To suppress glitches of n width, load n+1 in this
register. All signal transitions whose width is less than the value in
SSCn_NOISE_SUPP_WID are suppressed. Writing 0x00 into this register bypasses
the antiglitch filter.
[31:8] RESERVED
[7:0] NOISE_SUPP_WID: Holda the value of maximum glitch to be suppressed.
Clock prescaler for glitch suppression
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1
PRESCALE_VAL
SSCn_PRESCALER
RESERVED
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RESERVED
Address:
Type:
RW
Reset:
0x00
Description:
This register holds the prescaler division factor for glitch suppression, equivalent to
10 MHz. For example if the comms clock is 100 MHz the prescaler division factor
should be 10.
[31:4] RESERVED
[3:0] PRESCALE_VAL: Holds the pre-scaler division value for glitch suppression.
364/454
8137791 RevA
[5:0] RESERVED
STi7105
SSCn_NOISE_SUPP_WID_DOUT
Noise suppression max output data delay

width
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
NSWD
Address:
Type:
RW
Reset:
Description:
Holds the maximum delay width by which output data has to be delayed.
[7:0] NSWD: Holds the value of maximum delay.
SSCn_PRE_SCALER_DATAOUT
Prescaler data out
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
RESERVED
PSDO
Address:
Type:
RW
Reset:
Description:
Pre-scaler division factor of input comms clock. The output of this section is fed to the
baud rate generator to generate the serial clock.
[31:4] RESERVED
[3:0] PSDO: Holds the pre-scaler division value.
8137791 RevA
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[31:8] RESERVED
Asynchronous serial controller (ASC)
18
STi7105
Parity generation, selection of 8-bit or 9-bit data transfer, and the number of stop bits are
programmable. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. The transmission and reception of data can simply be doublebuffered, or 16-deep FIFOs may be used. Handshaking is supported both for transmission
and for reception. For multiprocessor communication, a mechanism to distinguish the
address from the data bytes is included. Testing is supported by a loop-back option. A dualmode 16-bit baudrate generator provides the ASC with a separate serial clock signal.
Confidential
Each ASC supports full duplex, asynchronous communication, where both the transmitter
and the receiver use the same data frame format and the same baudrate. Data is
transmitted on the transmit data output pin TXD and received on the receive data input pin
RXD.
Each ASC can be set to operate in smart card mode for use when interfacing with a
smart card.
18.1
Control
Register ASCn_CTRL controls the operating mode of the ASC. It contains control and
enable bits, error check selection bits, and status flags for error identification.
Serial data transmission or reception is possible only when the baudrate generator run bit
(ASCn_CTRL.RUN) is set to 1. When the RUN bit is set to 0, TXD is 1. Setting the RUN bit
to 0 immediately freezes the state of the transmitter and receiver and should be done only
when the ASC is idle.
Note:
Programming the mode control field (ASCn_CTRL.MODE) to one of the reserved

combinations results in unpredictable behavior.
The ASC can be set to use either double-buffering or a 16-deep FIFO on transmission and
reception.
18.1.1
Resetting the FIFOs

Registers ASCn_TX_RST and ASCn_RX_RST have no actual storage associated with
them. A write of any value to one of these registers resets the corresponding FIFO.
18.1.2
Transmission and reception

Serial data transmission or reception is possible only when the baudrate generator run bit
(ASCn_CTRL.RUN) is set to 1. A handshaking protocol is supported on both transmission
and reception, using CTS and RTS signals.
A transmission is started by writing to the transmit buffer register ASCn_TX_BUF. Data
transmission is either double buffered or uses a FIFO (selectable in register ASCn_CTRL),
therefore a new character may be written to the transmit buffer register before the
366/454
8137791 RevA
The asynchronous serial controller, also referred to as the UART interface, provides serial
communication between the STi7105 and other microcontrollers, microprocessors or
external peripherals. The STi7105 provides four ASCs, two of which are generally used by
the smart card controllers.
STi7105

transmission of the previous character is complete. This allows characters to be sent backto-back without gaps.
Data reception is enabled by the receiver enable bit ASCn_CTRL.RX_EN. After reception of
a character has been completed, the received data and, if provided by the selected
operating mode, the parity error bit, can be read from the receive buffer register,
ASCn_RX_BUF.
Confidential
The loop back option (selected by the ASCn_STA.LOOPBACK bit) connects the output of
the transmitter shift register internally to the input of the receiver shift register. This may be
used to test serial communication routines at an early stage without having to provide an
external network.
18.2
Data frames
Data frames may be 8-bit or 9-bit, with or without parity and with or without a wake-up bit.
The data frame type is selected by setting the ASCn_CTRL.MODE bit field in the control
register.
The transmitted data frame consists of three basic elements:
18.2.1
start bit
data field (8 or 9 bits, least significant bit (LSB) first, including a parity bit or wake-up bit,
if selected)
stop bits (0.5, 1, 1.5 or 2 stop bits)
8-bit data frames

Figure 58 shows an 8-bit transmitted data frame. 8-bit frames may use one of the following
formats:
eight data bits D[0:7] (MODE set to 001)
seven data bits D[0:6] plus an automatically generated parity bit (MODE set to 011)
Parity may be odd or even, depending on the bit ASCn_CTRL.PARITYODD. If the modulo 2
sum of the seven data bits is 1, then the even parity bit is set and the odd parity bit is
cleared.
In receive mode the parity error flag (ASCn_STA.PARITY_ERR) is set if a wrong parity bit is
received. The parity error flag is stored in the 8th bit (D7) of the ASCn_RX_BUF register.
The parity error bit is set high if there is a parity error.
8137791 RevA
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Reception of a second character may begin before the received character has been read out
of the receive buffer register. The overrun error status flag in the status register
(ASCn_STA.OVERRUN_ERR) is set when the receive buffer register has not been read by
the time the reception of a second character is completed. The previously received
character in the receive buffer is overwritten, and the ASCn_STA register is updated to
reflect the reception of the new character.
STi7105
Figure 58. 8-bit Tx data frame format
Start
bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
8th
bit
1st
stop
bit
2nd
stop
bit
Data bit (D7)

or Parity bit
9-bit data frames

Figure 59 shows a 9-bit transmitted data frame. 9-bit data frames use of one of the following
formats:
nine data bits D[0:8] (MODE set to 100)
eight data bits D[0:7] plus an automatically generated parity bit (MODE set to 111)
eight data bits D[0:7] plus a wake-up bit (MODE set to 101)
Confidential
Figure 59. 9-bit Tx data frame format

Start
bit
D0
(LSB)
D1
D2
D3
D4
D5
D6
D7
9th
bit
1st
stop
bit
2nd
stop
bit
Data bit (D8)

or Parity bit
or wake-up bit
Parity may be odd or even, depending on bit ASCn_CTRL.PARITYODD. If the modulo 2

sum of the eight data bits is 1, then the even parity bit is set and the odd parity bit is cleared.
The parity error flag (ASCn_STA.PARITY_ERR) is set if a wrong parity bit is received. The
parity error flag is stored in the ninth bit (D8) of the ASCn_RX_BUF register. The parity error
bit is set high if there is a parity error.
In wake-up mode (MODE = 101), received frames are transferred to the receive buffer
register only if the ninth bit (the wake-up bit) is 1. If this bit is 0, no receive interrupt request
is activated and no data is transferred.
This feature may be used to control communication in multiprocessor systems. When the
master processor wants to transmit a block of data to one of several slaves, it first sends out
an address byte that identifies the target slave. An address byte differs from a data byte in
that the additional ninth bit is 1 for an address byte and 0 for a data byte, so no slave is
interrupted by a data byte. An address byte interrupts all slaves (operating in 8-bit data plus
wake-up bit mode), so each slave can examine the eight least significant bits (LSBs) of the
received character, which is the address. The addressed slave switches to 9-bit data mode,
which enables it to receive the data bytes that are coming (with the wake-up bit cleared).
The slaves that are not being addressed remain in 8-bit data plus wake-up bit mode,
ignoring the data bytes that follow.
368/454
8137791 RevA
18.2.2
STi7105
18.3
Transmission
Transmission begins at the next baudrate clock tick, provided that the RUN bit is set and
data has been loaded into the ASCn_TX_BUF. If bit ASCn_CTRL.CTS_EN is set, then
transmission occurs only when CTS is low.
The loop back option (selected by bit ASCn_CTRL.LOOPBACK) internally connects the
output of the transmitter shift register to the input of the receiver shift register. This may be
used to test serial communication routines at an early stage without having to provide an
external network.
Confidential
A transmission ends with stop bits (1 is output on TXD). When bit ASCn_CTRL.SC_EN is 0,
the length of these stop bits is determined by the setting of field ASCn_CTRL.STOPBITS.
This can be for 0.5, 1, 1.5 or 2 periods of the baud clock. In smart card mode, when bit
ASCn_CTRL.SC_EN is 1, the number of stop bits is determined by the value in
ASCn_GUARDTIME register.
18.3.1
Transmission with FIFOs enabled

The FIFOs are enabled by setting bit ASCn_CTRL.FIFO_EN. The output FIFO is
implemented as a 16-deep array of 9-bit vectors. Values to be transmitted are written to the
output FIFO by writing to ASCn_TX_BUF.
Bit ASCn_STA.TX_FULL is set when the transmit FIFO is considered full, that is, when it
contains 16 characters. Further writes to ASCn_TX_BUF fail to overwrite the most recent
entry in the output FIFO. Bit ASCn_STA.TX_HALFEMPTY is set when the output FIFO
contains eight or fewer characters.
Values are shifted out of the bottom of the output FIFO into a 9-bit output shift register in
order to be transmitted. If the transmitter is idle (that is, the output shift register is empty)
and something is written to the ASCn_TX_BUF so that the output FIFO becomes nonempty, the output shift register is immediately loaded from the output FIFO and transmission
of the data in the output shift register begins at the next baudrate tick.
When the transmitter is just about to transmit the stop bits, and if the output FIFO is nonempty, the output shift register is immediately loaded from the output FIFO, and the
transmission of this new data begins as soon as the current stop bit period is over (that is,
the next start bit is transmitted immediately following the current stop bit period). If the
output FIFO is empty at this point, the output shift register becomes empty. Thus, back-toback transmission of data can take place. Writing anything to ASCn_TX_RST empties the
output FIFO.
After changing the ASCn_CTRL.FIFO_EN bit, it is important to reset the FIFO to empty (by
writing to the ASCn_TX_RST register), or garbage may be transmitted.
18.3.2
Double buffered transmission

Double buffering is enabled and the FIFOs disabled by writing 0 to bit
ASCn_CTRL.FIFO_EN. When the transmitter is idle, the transmit data written into the
transmit buffer ASCn_TX_BUF is immediately moved to the transmit shift register, thus
freeing the transmit buffer for the next data to be sent. This is indicated by the transmit buffer
8137791 RevA
369/454
The transmitter empty flag (ASCn_STA.TX_EMPTY) indicates whether the output shift
register is empty. It is set at the beginning of the last data frame bit that is transmitted, that
is, during the first comms clock cycle of the first stop bit shifted out of the transmit shift
register.
STi7105
empty flag (TX_HALFEMPTY) being set. The transmit buffer can be loaded with the next
data while transmission of the previous data is still occurring.
When the FIFOs are disabled, the ASCn_STA.TX_FULL bit is set when the buffer contains
one character, and a write to ASCn_TX_BUF in this situation overwrites the contents. The
TX_HALFEMPTY bit of the ASCn_STA register is set when the output buffer is empty.
18.3.3
ASC_n_DIR
18.4
Reception
Reception is initiated by a falling edge on the data input pin RXD, provided that the RUN and
RX_EN bits of the ASCn_CTRL register are set.
Confidential
Controlled data transfer can be achieved using the RTS handshaking signal provided by the
ASC. Normally the RTS output of the ASC transmitter is connected to the CTS input of the
ASC receiver. The sender checks the RTS to ensure the ASC is ready to receive data. In
double buffered reception RTS goes high when ASCn_RX_BUF is full. In FIFO controller
operation RTS goes high when RX_HALFFULL bit is 1.
The RXD pin is sampled at 16 times the rate of the selected baudrate. A majority decision of
the first, second and third samples of the start bit determines the effective bit value. This
avoids erroneous results that may be caused by noise.
If the detected value of the first bit of a frame is not 0, then the receive circuit is reset and
waits for the next falling edge transition at the RXD pin. If the start bit is valid, that is 0, the
receive circuit continues sampling and shifts the incoming data frame into the receive shift
register. For subsequent data and parity bits, the majority decision of the seventh, eighth
and ninth samples in each bit time is used to determine the effective bit value. The effective
values received on RXD are shifted into a 10-bit input shift register.
For 0.5 stop bits, the majority decision of the third, fourth, and fifth samples during the stop
bit is used to determine the effective stop bit value. For 1 and 2 stop bits, the majority
decision of the seventh, eighth, and ninth samples during the stop bits is used to determine
the effective stop bit values. For 1.5 stop bits, the majority decision of the 15th, 16th, and
17th samples during the stop bits is used to determine the effective stop bit value.
Reception is stopped by clearing bit ASCn_CTRL.RX_EN. Any currently received frame is
completed, including the generation of the receive status flags. Start bits that follow this
frame are not recognized.
370/454
8137791 RevA
To allow control of the ASC exchange between transmitter and receiver by external signals,
the ASC_n_DIR level indicates the direction of data at the TXD data output pins. When
ASC_n_DIR is low, TXD is in output mode. When ASC_n_DIR is high, TXD is in tri-state
mode.
STi7105
18.4.1
Hardware error detection

To improve the safety of serial data exchange, the ASC provides three error status flags in
the ASCn_STA register, which indicate if an error has been detected during reception of the
last data frame and associated stop bits.
The parity error bit (PARITY_ERR) in the ASCn_STA register is set when the parity
check on the received data is incorrect.
In FIFO operation parity errors on the buffers are ORed to yield a single parity error bit.
The framing error bit (FRAME_ERR) in the ASCn_STA register is set when the RXD
pin is not 1 during the programmed number of stop bit times.
The overrun error bit (OVERRUN_ERR) in the ASCn_STA register is set when the input
buffer is full and a character has not been read out of the ASCn_RX_BUF register
before reception of a new frame is complete.
These flags are updated simultaneously with the transfer of data to the receive input buffer.
Frame and parity errors
Confidential
For each input entry, the frame error information is recorded. Bit ASCn_STA.FRAME_ERR
is set when the input buffer (double buffered operation), or at least one of the valid entries in
the input buffering (FIFO controlled operation) has its most significant bit set.
If the mode is one where a parity bit is expected, for each input entry the parity error is
recorded in the ASCn_RX_BUF register, in bit 7 for 7-bit data mode or in bit 8 for 8-bit data
mode. It does not contain the parity bit that was received. For 7-bit + parity data frames the
parity error bit is set in both the eighth (bit 7 of 0 to 9) and the ninth (bit 8 of 0 to 9) bits. The
PARITY_ERR bit of ASCn_STA is set when the input buffer (double buffered operation), or
at least one of the valid entries in the input buffering (FIFO controlled operation), has bit 8
set.
When receiving 8-bit data frames without parity, the ninth bit of each input entry (bit 8 of 0 to
9) is undefined.
18.4.2
Input buffering modes

FIFO enabled reception
The FIFOs are enabled by setting bit ASCn_CTRL.FIFO_EN. The input FIFO is
implemented as a 16-deep array of 10-bit vectors (each 9 down to 0). If the input FIFO is
empty, that is, no entries are present, bit ASCn_STA.RX_BUFFULL is set to 0. If one or
more FIFO entries are present, bit ASCn_STA.RX_BUFFULL register is set to 1. If the input
FIFO is not empty, a read from ASCn_RX_BUF gets the oldest entry in the input FIFO.
Bit ASCn_STA.RX_HALFFULL is set when the input FIFO contains more than eight
characters. Writing anything to ASCn_RX_RST empties the input FIFO. As soon as the
effective value of the last stop bit has been determined, the content of the input shift register
is transferred to the input FIFO (except during wake-up mode, in which case this happens
only if the wake-up bit, bit 8, is 1). The receive circuit then waits for the next falling edge
transition at the RXD pin.
Bit ASCn_STA.OVERRUN_ERR is set when the input FIFO is full and a character is loaded
from the input shift register into the input FIFO. It is cleared when the ASCn_RX_BUF
register is read.
8137791 RevA
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In FIFO operation the bit remains set while at least one of the entries has a frame error.
STi7105
After changing the ASCn_CTRL.FIFO_EN bit, it is important to reset the FIFO to empty by
writing to the ASCn_RX_RST register; otherwise the state of the FIFO pointers may be
garbage.
Double buffered operation is enabled and the FIFOs disabled by writing 0 to bit
ASCn_CTRL.FIFO_EN. This mode can be seen as equivalent to a FIFO controlled
operation with a FIFO of length 1 (the first FIFO vector is in fact used as the buffer). When
the last stop bit has been received (at the end of the last programmed stop bit period) the
content of the receive shift register is transferred to the receive data buffer register
(ASCn_RX_BUF). The receive buffer full flag (RX_BUFFULL) is set, and the parity error
(PARITY_ERR) and framing error (FRAME_ERR) flags are updated at the same time, after
the last stop bit has been received (that is, at the end of the last stop bit programmed
period), the flags are updated even if no valid stop bits have been received. The receive
circuit then waits for the next falling edge transition at the RXD pin.
18.4.3
Time out mechanism
Confidential
The ASC contains an 8-bit time-out counter. This reloads from ASCn_TIMEOUT whenever
one or more of the following is true:
ASCn_RX_BUF is read
the ASC is in the middle of receiving a character
ASCn_TIMEOUT is written to
If none of these conditions holds, the counter decrements towards 0 at every baudrate tick.
The TIMEOUT_NOTEMPTY bit of the ASCn_INT_EN register is 1 when the input FIFO is
not empty and the time-out counter is zero.
The TIMEOUT_IDLE bit of the ASCn_INT_EN register is 1 when the input FIFO is empty
and the time-out counter is zero.
The effect of this is that whenever the input FIFO has got something in it, the time-out
counter decrements until something happens to the input FIFO. If nothing happens, and the
time-out counter reaches zero, the TIMEOUT_NOTEMPTY bit of the ASCn_INT_EN
register is set.
When the software has emptied the input FIFO, the time-out counter resets and starts
decrementing. If no more characters arrive, when the counter reaches zero the
TIMEOUT_IDLE bit of the ASCn_INT_EN register is set.
18.5
Baudrate generation
Each ASC has its own dedicated 16-bit baudrate generator with 16-bit reload capability. The
baudrate generator has two possible modes of operation.
The ASCn_BAUDRATE register is the dual-function baudrate generator and reload value
register. A read from this register returns the content of the counter or accumulator
(depending on the mode of operation); writing to it updates the reload register.
If bit ASCn_CTRL.RUN register is 1, then any value written in register ASCn_BAUDRATE is
immediately copied to the counter/accumulator. However, if the RUN bit is 0 when the
register is written, then the counter/accumulator is not reloaded until the first comms clock
cycle after the RUN bit is 1.
372/454
8137791 RevA
Double buffered reception
STi7105

The baudrate generator supports two modes of operation, offering a wide range of possible
values. The mode is set via bit ASCn_CTRL.BAUDMODE. Mode 0 is a simple counter
driven by the comms clock whereas mode 1 uses a loop-back accumulator. Mode 0 is
recommended for low baudrates (below 19.2 Kbaud), where its error deviation is low, and
mode 1 is recommended for baudrates above 19.2 Kbytes.
18.5.1
Baudrates
The baudrate generator provides an internal oversampling clock at 16 times the external
baudrate. This clock ticks only if the bit ASCn_CTRL.RUN is set to 1. Setting this bit to 0
immediately freezes the state of the ASCs transmitter and receiver.
When bit ASCn_CTRL.BAUDMODE is set to 0, the baudrate and the required reload value
for a given baudrate can be determined by the following formulae:
Confidential
BaudRate =
ASCBaudRate =
fcomms
16 ASCBaudRate
fcomms
16 BaudRate
where:
ASCBaudRate represents the content of the ASCn_BAUDRATE reload value register,

taken as an unsigned 16-bit integer
fcomms is the frequency of the comms clock (clock channel CLK_IC_IF_100)
The baudrate counter is clocked by the comms clock. It counts downwards and can be
started or stopped by bit ASCn_CTRL.RUN. Each underflow of the timer provides one
oversampling baudrate clock pulse. The counter is reloaded with the value stored in its
16-bit reload register each time it underflows.
Writes to register ASCn_BAUDRATE update the reload register value. Reads from the
ASCn_BAUDRATE register return the current value of the counter.
Mode 1
When bit ASCn_CTRL.BAUDMODE is set to 1, the baudrate is controlled by the circuit in
Figure 60.
8137791 RevA
373/454
Mode 0
STi7105
Figure 60. Baudrate in mode 1
ASCBaudRate
(accumulator)
ASCBaudRate
(Reload)
Carry-out
Oversampling clock
The CPU writes go to ASCn_BAUDRATE to the reload register. The CPU then reads from
ASCn_BAUDRATE and returns the value in the accumulator register. Both registers are 16
bits wide and are clocked by the comms clock (CLK_IC_IF_100).
Writing a value of ASCBaudRate to the ASCn_BAUDRATE register results in an average
oversampling clock frequency of:
Confidential
ASCBaudRate fcomms
216
So the baudrate is given by:
BaudRate =
ASCBaudRate fcomms
16 216
This gives good granularity, and hence low baudrate deviation errors, at high baudrate
frequencies.
18.6
Interrupt control
Each ASC contains two registers that are used to control interrupts, the status register
(ASCn_STA) and the interrupt enable register (ASCn_INT_EN). The status bits in the
ASCn_STA register show the cause of any interrupt. The interrupt enable register allows
certain interrupt causes to be masked. Interrupts occur when a status bit is 1 (high) and the
corresponding bit in the ASCn_INT_EN register is 1.
The ASC interrupt signal is generated from the OR of all status bits after they have been
ANDed with the corresponding enable bits in the ASCn_INT_EN register, as shown in
Figure 61.
374/454
8137791 RevA
Comms clock
STi7105

The status bits cannot be reset by software because the ASCn_STA register cannot be
written to directly. Status bits are reset by operations performed by the interrupt handler:
transmitter status bits (TX_EMPTY and TX_HALFEMPTY) are reset when a character
is written to the transmitter buffer
receiver status bit (RX_BUFFULL) is reset when a character is read from the receive
buffer
PARITY_ERR and FRAME_ERR status bits are reset when all characters containing
errors have been read from the receive input buffer
the OVERRUN_ERR status bit is reset when a character is read from ASCn_RX_BUF
Using the ASC interrupts when FIFOs are disabled (double buffered
operation)
Confidential
The transmitter generates two interrupts; this provides advantages for the servicing
software. For normal operation (that is, other than the error interrupt) when FIFOs are
disabled the ASC provides three interrupt requests to control data exchange via the serial
channel:
TX_HALFEMPTY is activated when data is moved from ASCn_TX_BUF to the transmit

shift register
TX_EMPTY is activated before the last bit of a frame is transmitted
RX_BUFFULL is activated when the received frame is moved to ASCn_RX_BUF
8137791 RevA
375/454
18.6.1
STi7105
Figure 61. ASC status and interrupt registers

RX_BUFFULL
RX_BUFFULL_IE
TX_EMPTY
TX_EMPTY_IE
TX_HALFEMPTY
TX_HALFEMPTY_IE
PARITY_ERR
PARITY_ERR_IE
AND
AND
AND
AND
ASC
interrupt
FRAME_ERR_IE
OVERRUN_ERR
OVERRUN_ERR_IE
TIMEOUT_NOTEMPTY
TIMEOUT_NOTEMPTY_IE
TIMEOUT_IDLE
TIMEOUT_IDLE_IE
RX_HALFFULL
RX_HALFFULL_IE
AND
OR
Confidential
AND
AND
AND
AND
TX_FULL
NKD
ASCn_STA
register
ASCn_INT_EN
register
As shown in Figure 62, TX_HALFEMPTY is an early trigger for the reload routine, and
TX_EMPTY indicates the completed transmission of the data field of the frame. Therefore,
software using handshake should rely on TX_EMPTY at the end of a data block to make
sure that all data has really been transmitted.
For single transfers it is sufficient to use the transmitter interrupt (TX_EMPTY), which
indicates that the previously loaded data has been transmitted, except for the last bit of a
frame.
For multiple back-to-back transfers it is necessary to load the next data before the last bit of
the previous frame has been transmitted. The use of TX_EMPTY alone would leave just one
stop bit time for the handler to respond to the interrupt and initiate another transmission.
Using the output buffer interrupt (TX_HALFEMPTY) to signal for more data allows the
service routine to load a complete frame, as ASCn_TX_BUF may be reloaded while the
previous data is still being transmitted.
376/454
8137791 RevA
FRAME_ERR
STi7105
18.6.2
Using the ASC interrupts when FIFOs are enabled

To transmit a large number of characters back to back, the driver routine initially writes 16
characters to ASCn_TX_BUF. Then, every time a TX_HALFEMPTY interrupt fires, it writes
eight more. When there is nothing more to send, a TX_EMPTY interrupt tells the driver that
everything has been transmitted.
Figure 62. ASC transmission
Write char1 Write char2
Write char3
Char 3
Char 2
Char 1
Output shift register
Char 3
Char 2
TX_HALFEMPTY
Char 3
Stop
Char 2
Start
Start
Char 1
Stop
Confidential
Transmission Idle
Stop
Start
TX_EMPTY interrupt
Idle
When receiving, the driver can use RX_BUFFULL to interrupt every time a character
arrives. Alternatively, if data is coming in back to back, it can use RX_HALFFULL to interrupt
it when there are more than eight characters in the input FIFO to read. It has as long as it
takes to receive eight characters to respond to this interrupt before data overruns. If less
than eight characters stream in, and no more are received for at least a time-out period, the
driver can be woken up by one of the two time-out interrupts, TIMEOUT_NOTEMPTY or
TIMEOUT_IDLE.
Input shift register
Char 1
Stop
Char 3
Char 2
Char 1
ASCn_RX_BUF register
Start
Char 2
Stop
Start
Char 1
Stop
Receive Idle
Start
Figure 63. ASC reception
Idle
Char 3
Char 2
Char 3
RX_BUFFULL
18.7
Smart card operation

Smart card mode is selected by setting bit ASCn_CTRL.SC_EN to 1. In smart card mode
the RXD and TXD ports of the ASC are both connected externally via a single bi-directional
line to a smart card I/O port. Characters are transferred to and from the smart card as 8-bit
8137791 RevA
377/454
ASCn_TX_BUF register
STi7105
data frames with parity (see Section 18.2 on page 367). Handshaking between the ASC and
the smart card ensures secure data transfer.
The ASC supports both T=0 and T=1 protocol. In T=0 protocol, the reception of parity errors
by either the ASC or the smart card is signalled by the automatic transmission of a NACK,
where the receiver pulls the data line low, 0.5 baudrate clock periods after the end of the
parity bit. The ASC supports the reception and transmission of such NACKs. In T=1
protocol, this NACK behavior is not required, and any such behavior on the part of the UART
can be disabled by setting the ASCn_CTRL bit NACK_DISABLE.
When bit ASCn_CTRL.SC_EN is set to 0, normal UART operation occurs.
18.7.1
Control registers
Confidential
ASCn_GUARDTIME
The programmable 9-bit register ASCn_GUARDTIME controls the time between
transmitting the parity bit of a character and the start bit of any further bytes, or transmitting
a NACK (no acknowledge signal, see Handshaking). During the guardtime period the ASC
receiver is insensitive to possible start bits and the smart card is free to send NACKs.
The guardtime is effectively the number of stop bits to use when transmitting in smart card
mode. Programming a value of 0 is undefined. Any positive value < 512 is possible.
The guardtime mentioned here is different from the guardtime mentioned in ISO7816. In fact
to achieve a particular guardtime value, the guardtime should be programmed with the
following value:
Guardtime = guardtime + 2 (mod 256)
In particular, this applies to the special case of guardtime = 255, where effectively, the
number of stop bits is 1.
Note:
If guardtime = 255 then any NACKs from the smart card might conflict with subsequent
transmitted start bits, so it is assumed that the smart card is not sending NACKs in this case
(T=1 protocol is being used for example). It is also important that the ASC should be
programmed in 0.5 stop bit mode, so that it does not see a subsequent start bit as a frame
error (that is a NACK). So when guardtime = 255, the ASC should be programmed in
0.5 stop bit mode.
Guardtime should always be set to at least two.
18.7.2
Transmission
In smart card mode FIFOs can be either enabled or disabled. If FIFOs are disabled, the
ASC transmission behaves according to NDC requirements.
Handshaking
When the ASC is transmitting data to the smart card, the smart card can NACK (not
acknowledge) the transmission by pulling the line low 0.5 baud clock periods into the
guardtime period, and holding it low for at least 1 baud clock period. The ASC should also
be programmed in 1.5 stop bit mode, and because it receives what it transmits, NACKs is
detected as receive framing errors.
378/454
8137791 RevA
Smart card operation complies with the ISO smart card specification except where noted
(see Section 18.7.4).
STi7105
Behavior with FIFOs enabled

At about 1 baud clock period into the guardtime period, the ASC knows whether or not the
transmitted character has been NACKed. If no NACK has been received and the Tx FIFO is
not empty, the next character is transmitted after the guardtime period.
If a transmitted character is NACKed by the receiving ASC, the character is retransmitted as
soon as the guardtime period expires (or if guardtime is two, an extra baud clock period
later), and retransmission is attempted up to the number of retries set in the
ASCn_RETRIES register. If the last retry is also NACKed the Tx FIFO is emptied, putting
the transmitter into an idle state, and the NKD bit is set in the ASCn_STA register.
All unNACKed (successfully transmitted) data is looped back into the receive FIFO. This
FIFO can be read by software to determine the status of the data transmission.
Behavior with FIFOs disabled
Confidential
When the smart card mode bit is set to 1, the following operation occurs.
Transmission of data from the transmit shift register is guaranteed to be delayed by a

minimum of 1/2 baud clock. In normal operation a full transmit shift register starts
shifting on the next baud clock edge. In smart card mode this transmission is further
delayed by a guaranteed 1/2 baud clock.
If a parity error is detected during reception of a frame programmed with a 1/2 stop bit
period, the transmit line is pulled low for a baud clock period after the completion of the
receive frame, that is, at the end of the 1/2 stop bit period. This is to indicate to the
smart card that the data transmitted to the ASC has not been correctly received.
The assertion of the TX_EMPTY interrupt can be delayed by programming the

ASCn_GUARDTIME register. In normal operation, TX_EMPTY is asserted when the
transmit shift register is empty and no further transmit requests are outstanding.
The receiver enable bit in the ASCn_CTRL register is automatically reset after a
character has been transmitted. This avoids the receiver detecting a NACK from the
smart card as a start bit.
In smart card mode an empty transmit shift register triggers the guardtime counter to count
up to the programmed value in the ASCn_GUARDTIME register. TX_EMPTY is forced low
during this time. When the guardtime counter reaches the programmed value TX_EMPTY is
asserted high.
The de-assertion of TX_EMPTY is unaffected by smart card mode.
18.7.3
Reception
Reception can be done with FIFOs either enabled or disabled. The behavior is the same as
in normal (nonsmart card) mode except that if a parity error occurs then, providing the
transmitter is idle, and bit ASCn_CTRL.NACK_DISABLE is 0, the UART transmits a NACK
on the TXD for one baud clock period from the end of the received stop bit. RXD is masked
when transmitting a NACK, since TXD is tied to RXD and a NACK must not be seen as a
start bit.
If bit ASCn_CTRL.NACK_DISABLE is 1 then no automatic NACK generation takes place.
8137791 RevA
379/454
Emptying the FIFO causes an interrupt, which can be handled by software. The NKD bit in
the ASCn_STA register can be reset by writing to the ASCn_TX_RST register.
18.7.4
STi7105
Divergence from ISO smart card specification
Confidential
This ASC does not support guardtimes of 0 or 1, and does not have any special behavior for
a guardtime of 255.
380/454
8137791 RevA
STi7105
Asynchronous serial controller (ASC) registers
19
Caution:
The registers for each ASC are grouped in 4 Kbyte blocks, with the base of the block for
ASC number n at the address ASCnBaseAddress.
Register addresses are provided as ASCnBaseAddress + offset.
ASC0BaseAddress: 0xFD03 0000
(UART 0)
(UART 1)
(UART 2)
(UART 3)
Confidential
Table 59.
ASC register summary
Offset
Register
Description
Page
0x000
ASCn_BAUDRATE
ASCn baudrate generator
on page 381
0x004
ASCn_TX_BUF
ASCn transmit buffer
on page 384
0x008
ASCn_RX_BUF
ASCn receive buffer
on page 385
0x00C
ASCn_CTRL
ASCn control
on page 385
0x010
ASCn_INT_EN
ASCn interrupt enable
on page 386
0x014
ASCn_STA
ASCn interrupt status
on page 387
0x018
ASCn_GUARDTIME
ASCn guard time
on page 388
0x01C
ASCn_TIMEOUT
ASCn time out
on page 389
0x020
ASCn_TX_RST
ASCn transmit FIFO reset
on page 389
0x024
ASCn_RX_RST
ASCn receive FIFO reset
on page 389
0x028
ASCn_RETRIES
ASCn number of retries on transmission
on page 390
ASCn_BAUDRATE
ASCn baudrate generator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
RELOAD_VAL
Address:
ASCnBaseAddress + 0x000
Type:
RW
Reset:
Description:
This register is the dual function baudrate generator and reload value register. A read
from this register returns the content of the 16-bit counter/accumulator; writing to it
updates the 16-bit reload register.
If bit ASCn_CTRL.RUN is 1, then any value written in the ASCn_BAUDRATE register
is immediately copied to the timer. However, if the RUN bit is 0 when the register is
8137791 RevA
381/454
The ASCnBaseAddresses are:
STi7105
written, then the timer is not reloaded until the first comms clock cycle after the RUN
bit is 1.
The mode of operation of the baudrate generator depends on the setting of bit
ASCn_CTRL.BAUDMODE.
Mode 0
When bit ASCn_CTRL.BAUDMODE is set to 0, the baudrate and the required reload
value for a given baudrate can be determined by the following formulae:
fcomms
BaudRate =
fcomms
16 BaudRate
ASCBaudRate =
where: ASCBaudRate represents the content of the ASCn_BAUDRATE register,

taken as an unsigned 16-bit integer.
fcomms is the frequency of the comms clock (clock channel CLK_IC_IF_100).
Confidential
Mode 0 should be used for all baudrates below 19.2 Kbaud.

Table 60 lists commonly used baudrates with the required reload values and the
approximate deviation errors for an example baudrate with a comms clock of
100 MHz.
Table 60.
Baudrate
Mode 0 baudrates
Reload value
(exact)
Reload value
(integer)
Reload value
(hex)
Approximate
deviation error (%)
38.4 K
162.76
163
0x00A3
0.15
19.2 K
325.52
326
0x0146
0.15
9600
651.04
651
0x028B
0.01
4800
1302.08
1302
0x0516
0.01
2400
2604.17
2604
0x0A2C
0.01
1200
5208.33
5208
0x1458
0.01
600
10416.67
10417
0x28B1
0.01
300
20833.33
20833
0x5161
150
41666.67
41667
0xA2C3
Mode 1
When bit ASCn_CTRL.BAUDMODE is set to 1, the baudrate is given by:
BaudRate =
382/454
ASCBaudRate fcomms
16 216
8137791 RevA
16 ASCBaudRate
STi7105

where: fcomms is the comms clock frequency and ASCBaudRate is the value written to
the ASCn_BAUDRATE register. Mode 1 should be used for baudrates of 19.2 Kbytes
and above because it has a lower deviation error than mode 0 at higher frequencies.
Table 61.
Mode 1 baudrates fcomms = 100 MHz

Reload value
(exact)
Reload value
(integer)
Reload value
(hex)
Approximate
deviation error (%)
115200
1207.96
1208
0x04B8
0.00
96000
1006.63
1007
0x03EF
0.04
38400
402.65
403
0x0193
0.09
19200
201.33
201
0x00C9
0.16
Confidential
Baudrate
8137791 RevA
383/454
Address:
Type:
Reset:
Description:
A transmission is started by writing to the transmit buffer register ASCn_TX_BUF.

Serial data transmission is possible only when the baudrate generator bit
ASCn_CTRL.RUN is set to 1.
Data transmission is double buffered or uses a FIFO, so a new character may be
written to the transmit buffer register before the transmission of the previous character
is complete. This allows characters to be sent back-to-back without gaps.
[31:9] RESERVED
Confidential
[8] TD8:
Transmit buffer data D8, or parity bit, or wake up bit or undefined depending on the operating
mode (the setting of field ASCn_CTRL.MODE).
If the MODE field selects an 8-bit frame then this bit should be written as 0.
[7] TD7:
Transmit buffer data D7, or parity bit depending on the operating mode (the setting of field
ASCn_CTRL.MODE).
[6:0] TD[6:0]: Transmit buffer data D6 to D0
384/454
8137791 RevA
TD[6:0]
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TD8
ASCn transmit buffer
TD7
ASCn_TX_BUF
STi7105
STi7105
Address:
Type:
Reset:
Serial data reception is possible only when the baudrate generator bit
ASCn_CTRL.RUN is set to 1.
[31:9] RESERVED
[7] RD7:
Receive buffer data D7, or parity error bit depending on the operating mode (the setting of field
ASCn_CTRL.MODE)
[6:0] RD[6:0]:
Receive buffer data D6 to D0
MODE
STOPBITS
LOOPBACK
PARITYODD
RUN
CTS_EN
FIFO_EN
BAUDMODE
NACK_DISABLE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_EN
ASCn control
SC_EN
ASCn_CTRL
RESERVED
Confidential
[8] RD8:
Receive buffer data D8, or parity error bit, or wake up bit depending on the operating mode (the
setting of field ASCn_CTRL.MODE)
If the MODE field selects an 8-bit frame then this bit is undefined. Software should ignore this
bit when reading 8-bit frames
Address:
ASCnBaseAddress + 0x00C
Type:
RW
Reset:
Description:
This register controls the operating mode of the ASC and contains control bits for
mode and error check selection, and status flags for error identification.
Programming the mode control field (MODE) to one of the reserved combinations
may result in unpredictable behavior. Serial data transmission or reception is possible
only when the baudrate generator run bit (RUN) is set to 1. When the RUN bit is set to
0, TXD is 1. Setting the RUN bit to 0 immediately freezes the state of the transmitter
and receiver. This should be done only when the ASC is idle.
8137791 RevA
385/454
Description:
RD[6:0]
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RD8
ASCn receive buffer
RD7
ASCn_RX_BUF
STi7105
Serial data transmission or reception is possible only when the baudrate generator
RUN bit is set to 1. A transmission is started by writing to the transmit buffer register
ASCn_TX_BUF.
[31:14] RESERVED
[13] NACK_DISABLE: NACKing behavior control
0: NACKing behavior in smartcard mode
1: No NACKing behavior in smartcard mode
[11] CTS_EN: CTS enable

0: CTS ignored
1: CTS enabled
[10] FIFO_EN: FIFO enable:

0: FIFO disabled
1: FIFO enabled
[9] SC_EN: Smartcard enable

0: Smartcard mode disabled
1: Smartcard mode enabled
[8] RX_EN: Receiver enable bit

0: Receiver disabled
1: Receiver enabled
Confidential
[12] BAUDMODE: Baudrate generation mode

0: Baud counter decrements, ticks when it reaches 1
1: Baud counter added to itself, ticks when there is a carry
[7] RUN: Baudrate generator run bit

0: Baudrate generator disabled (ASC inactive)
1: Baudrate generator enabled
[6] LOOPBACK: Loopback mode enable bit
0: Standard transmit/receive mode
1: Loopback mode enabled
[5] PARITYODD: Parity selection

0: Even parity (parity bit set on odd number of 1s in data)
1: Odd parity (parity bit set on even number of 1s in data)
[4:3] STOPBITS: Number of stop bits selection
00: 0.5 stop bits
10: 1.5 stop bits
01: 1 stop bits

11: 2 stop bits
[2:0] MODE: ASC mode control

000: Reserved
010: Reserved
100: 9-bit data
110: Reserved
001: 8-bit data

011: 7-bit data + parity
101: 8-bit data + wake up bit
111: 8-bit data + parity
Address:
Type:
RW
386/454
8137791 RevA
FRAME_ERR
RX_BUFFULL
TX_EMPTY
PARITY_ERR
TX_HALFEMPTY
OVERRUN_ERR
TIMEOUT_NOTEMPTY
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_HALFFULL
ASCn interrupt enable
TIMEOUT_IDLE
ASCn_INT_EN
STi7105
Reset:
Description:
[31:9] RESERVED
[8] RX_HALFFULL: Receiver FIFO is half full interrupt enable
0: Receiver FIFO is half full interrupt disable 1: Receiver FIFO is half full interrupt enable
[7] TIMEOUT_IDLE: Time out when the receiver FIFO is empty interrupt enable
0: Time out when the input FIFO or buffer is empty interrupt disable
1: Time out when the input FIFO or buffer is empty interrupt enable
[5] OVERRUN_ERR: Overrun error interrupt enable

0: Overrun error interrupt disable
1: Overrun error interrupt enable
[4] FRAME_ERR: Framing error interrupt enable
0: Framing error interrupt disable
1: Framing error interrupt enable
1: Parity error interrupt enable
[2] TX_HALFEMPTY: Transmitter buffer half empty interrupt enable

0: Transmitter buffer half empty interrupt disable
1: Transmitter buffer half empty interrupt enable
[1] TX_EMPTY: Transmitter empty interrupt enable
0: Transmitter empty interrupt disable
1: Transmitter empty interrupt enable
[0] RX_BUFFULL: Receiver buffer full interrupt enable
0: Receiver buffer full interrupt disable
1: Receiver buffer full interrupt enable
Type:
Reset:
3 (Rx buffer full and Tx buffer empty)
0
RX_BUFFULL
TX_EMPTY
PARITY_ERR
TX_HALFEMPTY
FRAME_ERR
TONE
OVERRUN_ERR
NKD
Address:
TOE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_HALFFULL
ASCn interrupt status
TX_FULL
ASCn_STA
RESERVED
Confidential
[3] PARITY_ERR: Parity error interrupt enable:

0: Parity error interrupt disable
Description:
[31:11] RESERVED
[10] NKD: Transmission failure acknowledgement by receiver in smartcard mode.
0: Data transmitted successfully
1: Data transmission unsuccessful (data NACKed by smartcard)
8137791 RevA
387/454
[6] TIMEOUT_NOTEMPTY: Time out when not empty interrupt enable

0: Time out when input FIFO or buffer not empty interrupt disable
1: Time out when input FIFO or buffer not empty interrupt enable
STi7105
[9] TX_FULL: Transmitter FIFO or buffer is full

0: The FIFOs are enabled and the transmitter FIFO is empty or contains less than 16
characters, or the FIFOs are disabled and the transmit buffer is empty
1: The FIFOs are enabled and the transmitter FIFO contains 16 characters, or the FIFOs are
disabled and the transmit buffer is full
[8] RX_HALFFULL: Receiver FIFO is half full
0: The receiver FIFO contains eight characters or less
1: The receiver FIFO contains more than eight characters
[6] TONE: Time out when the receiver FIFO or buffer is not empty
0: No time out or the receiver FIFO or buffer is empty
1: Time out when the receiver FIFO or buffer is not empty
Confidential
[5] OVERRUN_ERR: Overrun error flag

0: No overrun error
1: Overrun error, that is, data received when the input buffer is full
[4] FRAME_ERR: Input frame error flag
0: No framing error
1: Framing error (stop bits not found)
[3] PARITY_ERR: Input parity error flag:

0: No parity error
1: Parity error
[2] TX_HALFEMPTY: Transmitter FIFO at least half empty flag or buffer empty
0: The FIFOs are enabled and the transmitter FIFO is more than half full (more than eight
characters) or the FIFOs are disabled and the transmit buffer is not empty.
1: The FIFOs are enabled and the transmitter FIFO is at least half empty (eight or less
characters) or the FIFOs are disabled and the transmit buffer is empty
[1] TX_EMPTY: Transmitter empty flag
0: Transmitter is not empty
1: Transmitter is empty
[0] RX_BUFFULL: Receiver FIFO not empty (FIFO operation) or buffer full (double buffered
operation)
0: Receiver FIFO is empty or buffer is not full 1: Receiver FIFO is not empty or buffer is full
ASCn_GUARDTIME
ASCn guard time
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
GUARDTIME
Address:
Type:
RW
Reset:
Description:
This register defines the number of stop bits and the delay of the assertion of the
interrupt TX_EMPTY by a programmable number of baud clock ticks. The value in the
register is the number of baud clock ticks to delay assertion of TX_EMPTY. This value
must be in the range 0 to 511.
388/454
8137791 RevA
[7] TOE: Time out when the receiver FIFO or buffer is empty
0: No time out or the receiver FIFO or buffer is not empty
1: Time out when the receiver FIFO or buffer is empty
STi7105
ASCn time out
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
TIMEOUT
Address:
ASCnBaseAddress + 0x01C
Type:
RW
Reset:
Description:
The time out period in baudrate ticks. The ASC contains an 8-bit time out counter,
which reloads from ASCn_TIMEOUT when one or more of the following is true:
ASCn_RX_BUF is read
the ASC is in the middle of receiving a character
ASCn_TIMEOUT is written to
Confidential
If none of these conditions hold, the counter decrements to 0 at every baudrate tick.
The TONE (time out when not empty) bit of the ASCn_STA register is 1 when the
input FIFO is not empty and the time out counter is zero. The TIMEOUT_IDLE bit of
the ASCn_STA register is 1 when the input FIFO is empty and the time-out counter is
zero.
When the software has emptied the input FIFO, the time out counter resets and starts
decrementing. If no more characters arrive, when the counter reaches zero the
TIMEOUT_IDLE bit of the ASCn_STA register is set.
ASCn_TX_RST
ASCn transmit FIFO reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TX_RST
Address:
Type:
Description:
Reset the transmit FIFO. Registers ASCn_TX_RST have no storage associated with
them. A write of any value to these registers resets the corresponding transmitter
FIFO.
ASCn_RX_RST
ASCn receive FIFO reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RX_RST
Address:
Type:
Description:
Reset the receiver FIFO. The registers ASCn_RX_RST have no actual storage
associated with them. A write of any value to one of these registers resets the
corresponding receiver FIFO.
8137791 RevA
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ASCn_TIMEOUT
ASCn_RETRIES
STi7105
ASCn number of retries on transmission
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
NUM_RETRIES
Type:
RW
Reset:
Description:
Defines the number of transmissions attempted on a piece of data before the UART
discards the data. If a transmission still fails after NUM_RETRIES, the NKD bit is set
in the ASCn_STA register where it can be read and acted on by software. This
register does not have to be reinitialized after a NACK error.
Confidential
Address:
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8137791 RevA
STi7105
20
PWM and counter module

The STi7105 includes an independent PWM four-channel timer module. Channels 0 and 1
are used by the STi7105; the channels are identical, with each containing one
programmable timer.
generates very low PWM frequencies (typically 411 Hz to 105 kHz for a 27 MHz PWM
clock)
enables generation of PWM waveforms
enables generation of an interrupt on a periodic basis with little software intervention,

with a wide periodic range - from a few microseconds to over 100 ms
capture and compare of PWM inputs
There are two completely independent counters, with associated prescalers and duty cycle
control, each able to generate an interrupt or a PWM waveform (or both if desired - interrupt
and PWM periods are identical).
Confidential
Figure 64. PWM function block diagram

PWM comp reg
D[7:0]
PWM_VALx[7:0]
LOAD
A
= EQ
B
Sync
PWM_EN
Blocks above dotted line are

duplicated for each PWM output
PWM_EN
PWM_CLK_VAL[7:0]
8
Sync
D
EN
8
Prescaler
DIVRATIO[7:0]
DIVCLK
PWMCOUNT
EN
COUNT
RESET
SET Q
OVERFLOW
Q[7:0]
PWM_OUTx
PWMCLK
27 MHZ
SET
Sync
D
SET
Q
RESET
PWM_INT
CPUCLK
100 MHZ
PWM_INT_ACK
PWM_INT_EN
The PWM capture (decoder) inputs are PWM_CAPTUREIN0 and PWM_CAPTUREIN1.

The encoder outputs are PWM_OUT0, PWM_OUT1, PWM_COMPAREOUT0 and
PWM_COMPAREOUT1 (see the Alternative functions chapter in the STi7105 Data Sheet);
the interrupt requests (routed to the ILC) are all made through a single signal. Register
PWM_INT_STA indicates which event which caused the interrupt. The module is clocked by
8137791 RevA
391/454
The module includes the following functions:
STi7105
two independent clocks, one for capture inputs/timers and one for PWM outputs, with two
different prescalers (see PWM_CTRL register description).
Each capture input can be programmed to detect rising-edge, falling-edge, both edges or
neither edge (disabled) using register PWM_CPT_EDGEx.
Figure 65. PWM - Capture and compare function block diagram
Sync
Edge select
CAPTURE_INx
Interrupt status reg bit
SET
CPUCLK
Q
RESET
CPT_INTx
CPUCLK
CPT_EN
CPT_INT_ENx
CPT_INT_ACKx
Prescaler
Capture count
EN
32
EN
CPT_CLK_VAL[4:0]
DIVRATIO[7:0]
DIVCLK
LOAD
32
D[31:0]
COUNT
PWM_CPT_VALx
Confidential
Capture valx
CPUCLK
Compare Regn
Interrupt status reg bit

A
D[31:0]
Q[31:0]
= EQ
32
PWM_CMP_VALx
SET
CMP_INTx
Q
RESET
Blocks outside dotted line are

duplicated for each PWM input and output
CMP_INT_ENx
CMP_INT_ACKx
LOAD
PWM_CMP_OUT_VALx
D
COMPAREOUTx
20.1
Programmable PWM function

The PWM clock (27 MHz nominal) is first prescaled (divided) by a factor of 1 to 256
according to control bits PWM_CLK_VAL, and triggers an 8-bit counter (from 0 to 255). The
counter and prescaler may be stopped by writing 0 to PWM_CTRL.PWM_EN. While
disabled, the value in the counter may be read or written from register PWM_CNT. Every
256 counts, the counter triggers the output block to start new pulses. Register
PWM_CPT_VALx is used to define the duty cycle of the PWM clock output, PWM_OUTx.
The prescaler consists of a modulo counter counting from 0 to
PWM_CTRL.PWM_CLK_VAL[7:0] and then rolling over to zero (see Figure 64).
For example:
CLK_VAL =
0x00: divide by 1 (that is, generated clock = PWM clock),

0x02: divide by 3 (modulo-3 count, from 0 to 2),
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8137791 RevA
PWM_CPT_EDGEx[1:0]
STi7105
0x0F: divide by 16 (modulo-16 count, from 0 to 15)

0xFF: divide by 256 (modulo-256 count, from 0 to 255)
When PWM_CTRL.PWM_EN is low, the prescaler is disabled and reset. It starts upon the
next rising edge following the setting of the enable bit.
Figure 66 below shows the generated waveforms.
Confidential
20.2
Periodic interrupt generation

Similarly, an interrupt request is raised (PWM_TMR_INTx goes high) when the 0-to-255
rolls over, provided bit PWM_INT_EN.EN is set. The interrupt request remains active until
cleared by a write access to the corresponding bit in register PWM_INT_ACK (or the
interrupt gets disabled). The status of the interrupt is available to software via register
PWM_INT_STA.
Figure 66. PWM-timer periodic interrupt generation waveforms
PWM clock
Prescaled clock
1 local (prescaled) clock period =
PWM_CLK_VAL_X PWM clock cycles
PWM_OUTn
(PWM_VALx +1) local clock period
256 local clock periods
PWM_INT
(if enabled via
PWM_INT_EN register)
Interrupt cleared here through PWM_INT_ACK register
8137791 RevA
393/454
A new PWM pulse is started (PWM_OUTx rises to logic 1) every time the 0-to-255 counter
rolls over. It returns to logic 0 after the number of cycles programmed in register
PWM_VALx + 1. Therefore PWM_VALx controls the duty cycle of the PWM signal. For
example, if the value programmed is 127 (that is, half the maximum possible), the resulting
output is a 50% duty cycle waveform; if the value programmed is the maximum (255) the
pulse will last for all the 256 cycles and the resulting output is constantly high. The length of
the pulse is updated only upon the last count, so that the pulse currently executing always
finishes before a pulse of different width is output. Following reset, PWM_OUTx is low.
20.3
STi7105
Capture and compare

The Capture and compare module contains a 32-bit counter, CaptureCount, and four 32-bit
registers: two (PWM_CPT_VALx) to capture the value of the counter CaptureValx and two,
PWM_CMP_VALx, to compare with PWM_CPT_VALx, causing an interrupt when the two
values are equal. The capture and compare module shares the PWM clock source, which
can be prescaled using the CPT_CLK_VAL bits of register PWM_CTRL. The PWM_CTRL
register also contains the capture enable bit, CPT_EN, which is used to enable the counter.
Capture function
Confidential
It is possible to select which edge to trigger on (a capture event) by setting

PWM_CPT_EDGEx. The detection of a capture event for capture register x results in the
current value of CaptureCount being loaded into PWM_CPT_VALx, and the CPT_INTx bit
being set in register PWM_INT_STA. Interrupts are enabled through register
PWM_INT_EN. Bits PWM_INT_ACK.CPT_INT_ACKx are used to reset
PWM_INT_STA.CPTn_INT.
Note:
The capture signals are synchronized to the CPU clock domain.
20.3.2
Compare function
There are two compare registers, PWM_CMP_VALx, each of which can generate an
interrupt when the values of CaptureCount and PWM_CMP_VALx are equal.
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8137791 RevA
20.3.1
STi7105
PWM and counter module registers
21
Caution:
The base address for the PWM-timer, referred to as PWMTimerBaseAddress, is:
0xFD01 0000.
The PWM-timer is software compatible with PWM modules present on earlier ST MPEG
decoders. A routine running on such PWM modules, and exploiting only PWM features (not
capture of interrupts), should be transposable to this PWM-timer.
Confidential
Table 62.
PWM-timer register summary
Offset
Register
Description
Page
0x00 0x0C
PWM_VALx
PWM reload value x
on page 396
0x10 0x1C
PWM_CPT_VALx
PWM capture value x
on page 396
0x20 0x2C
PWM_CMP_VALx
PWM compare value x
on page 396
0x30 0x3C
PWM_CPT_EDGEx
PWM capture edge control x
0x40 0x4C
PWM_CMP_OUT_VALx
PWM compare output value x
0x50
PWM_CTRL
PWM control
on page 397
0x54
PWM_INT_EN
PWM interrupt enable
on page 399
0x58
PWM_INT_STA
PWM interrupt status
on page 399
0x5C
PWM_INT_ACK
PWM interrupt acknowledge
on page 400
0x60
PWM_CNT
PWM count
on page 401
0x64
PWM_CPT_CMP_CNT
PWM capture/compare counter
on page 401
8137791 RevA
on page 397
on page 397
395/454
Note:
PWM_VALx
7
STi7105
PWM reload value x

6
PWM_VAL
Address:
PWMTimerBaseAddress + 0x00 + x * 0x4 (where x = 0 to 3)
Type:
RW
Reset:
Undefined
Description:
PWM reload value.
[7:0] PWM_VAL: PWM reload value, define duty cycle of output PWM_OUTx.
PWM_CPT_VALx
PWM capture value x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Confidential
CPT_VAL
Address:
Type:
Reset:
Undefined
Description:
PWM capture value.
[31:0] CPT_VAL: Value of capture counter when a capture event occurs.
PWM_CMP_VALx
PWM compare value x
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CMP_VAL
Address:
Type:
RW
Reset:
Undefined
Description:
PWM compare value..
[31:0] CMP_VAL: When value of PWM_CPT_VALx and this register are equal, an interrupt is
triggered.
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8137791 RevA
PWM_VAL + 1 is the number of local (prescaled) clock cycles for which PWM_OUTx
is high in a period of 256 local (prescaled) clock cycles.
STi7105
PWM_CPT_EDGEx
7
PWM capture edge control x
RESERVED
CE
Address:
Type:
RW
Reset:
Undefined
Description:
Controls the edge used for the capture of the timer in register PWM_CPT_VALx.
[7:2] RESERVED
00: Disabled
10: Falling edge
PWM_CMP_OUT_VALx
PWM compare output value x

4
CPT_OUT_VAL
RESERVED
Address:
Type:
RW
Reset:
Undefined
Description:
PWM compare output value.

[7:1] RESERVED
[0] CPT_OUT_VAL: On the next compare output, this value is output on the COMPAREOUTx
signal.
11
10
Address:
PWMTimerBaseAddress + 0x50
Type:
RW
Reset:
Undefined
PWM_CLK_VAL[3:0]
12
CPT_CLK_VAL[4:0]
13
PWM_EN
14
PWM_CLK_VAL[7:4]
15
PWM control
CPT_EN
PWM_CTRL
RESERVED
Confidential
01: Rising edge

11: Rising or falling edge
Description:
[15] RESERVED
8137791 RevA
397/454
[1:0] CE:
STi7105
[14:11] PWM_CLK_VAL[7:4]:
High order bits of the parameter that defines the period of the local prescaled clock for the
PWM-timer. The local clock enable signal is generated upon the prescale counter reaching
PWM_CLK_VAL[7:0].
[10] CPT_EN:
0: Disable capture
1: Enable capture
[9] PWM_EN:
0: Prescale counter is cleared and PWM counter is stopped
1: Prescale counter and PWM counter are enabled
[8:4] CPT_CLK_VAL[4:0]: Capture counter clock prescale value
Confidential
[3:0] PWM_CLK_VAL[3:0]: PWM counter clock prescale value.
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8137791 RevA
STi7105
CPT0_INT_EN
PWM_INT_EN
CPT0_INT
CPT1_INT_EN
CPT1_INT
3
CPT2_INT_EN
CPT2_INT
CPT3_INT_EN
CPT3_INT
CMP0_INT_EN
CMP0_INT
CMP1_INT_EN
10
CMP1_INT
11
CMP2_INT_EN
12
CMP2_INT
13
CMP3_INT_EN
14
RESERVED
15
PWM interrupt enable
CMP3_INT
PWM_INT_EN
Address:
Type:
RW
Reset:
Undefined
Description:
[15:9] RESERVED
[8] CMP3_INT_EN: Enable compare 3 interrupt
Confidential

[4] CPT3_INT_EN: Enable capture 3 interrupt
[3] CPT2_INT_EN: Enable capture 2interrupt
[0] PWM_INT_EN: PWM-timer interrupt enable
14
13
12
11
RESERVED
15
PWM interrupt status

10
Address:
Type:
Reset:
Undefined
8137791 RevA
PWM_INT
PWM_INT_STA
399/454
STi7105
Description:
[15:9] RESERVED
[8] CMP3_INT: Compare 3 interrupt
1: Interrupt.
1: Interrupt.
1: Interrupt.
[4] CPT3_INT: Capture 3 interrupt

1: Interrupt.
1: Interrupt.

1: Interrupt.
[0] PWM_INT: PWM counter interrupt
1: Interrupt.
CPT0_INT_ACK
PWM_INT_ACK
CPT1_INT_ACK
10
CPT2_INT_ACK
11
CPT3_INT_ACK
12
CMP0_INT_ACK
13
CMP1_INT_ACK
14
CMP2_INT_ACK
15
PWM interrupt acknowledge

CMP3_INT_ACK
PWM_INT_ACK
RESERVED
Confidential

1: Interrupt.
Address:
PWMTimerBaseAddress + 0x5C
Type:
Reset:
Undefined
Description:
[15:9] RESERVED
[8] CMP3_INT_ACK: Compare 3 interrupt acknowledge
1: Clear interrupt.
1: Clear interrupt.
1: Clear interrupt.
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8137791 RevA

1: Interrupt.
STi7105

1: Clear interrupt.
[4] CPT3_INT_ACK: Capture 3 interrupt acknowledge
1: Clear interrupt.
1: Clear interrupt.
1: Clear interrupt.
[0] PWM_INT_ACK: PWM counter interrupt acknowledge

1: Clear interrupt.
PWM_CNT
7
PWM count
6
Confidential
PWM_CNT
Address:
Type:
RW
Reset:
Undefined
Description:
[7:0] PWM_CNT: Direct access to the PWM counter
Write access (to preset a value for example) is only possible when the PWM-timer is disabled
(PWM_CTRL.PWM_EN = 0).
PWM_CPT_CMP_CNT
PWM capture/compare counter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CPT_CMP_CNT
Address:
Type:
RW
Reset:
Undefined
Description:
Counter used in capture and compare mode. Unlike the PWM counter, this can be
accessed when the counter is enabled.
[31:0] CPT_CMP_CNT: Compare and capture counter value.
8137791 RevA
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1: Clear interrupt.
Modem analog front end (MAFE) interfaces
STi7105
22
22.1
Overview
The modem analog front end interface (MAFE) is an interface to an analog front end (AFE)
for a modem such as the STLC7550.
The MAFE transmits samples simultaneously into and out of the AFE. Typically, it operates
at a rate of 9600 samples/second, giving a typical sample period of 100 s. That is, every
100 s, one sample is transmitted and another received through the MAFE.
The MAFE receives its system clock signal (SCLK) from the AFE. The SCLK frequency is
typically 256 ticks/sample period, or 2.56 MHz. The first 16 ticks of the 256 tick sample
period are used to exchange a 16-bit sample pair (1 bit per tick).
Confidential
The MAFE uses one DMA to transfer samples from a transmit memory buffer to the AFE,
and simultaneously uses a second DMA to receive samples from the AFE and write them
into the receive memory buffer. The software driver is woken up every time a simultaneous
transfer is completed, that is, every time a transmit memory buffer has been emptied and a
receive memory buffer has been filled. For example, if each memory buffer contains
100 samples, the software is woken up every 10 ms (100 100 s). This is more stringent
for handshake signals, where the buffer size could be as low as a few samples, for example,
four.
The software modem has two pairs of pointers (that is, four pointers) that point to two pairs
of transmit/receive buffers. The modem and the MAFE alternately switch between the two
pairs of pointers. While the MAFE transmits and receives using one pair of buffers, the
software modem processes the information in the other pair. Using the above example for a
buffer containing 100 samples, the software has 10 ms to wake up and then process one
pair of transmit/receive buffers before they are required again by the MAFE.
22.2
Using the MAFE to connect to a modem

The following table lists the pins that are used by the MAFE to connect a modem:
Table 63.
402/454
MAFE pins
Name
Type
Function name
(alternative)
Function description
PIO1[2]
MAFE_HC1
Indicates to the AFE that a control/status exchange is to

take place.
PIO1[3]
MAFE_DOUT
Line for serially transmitting samples to the AFE.
PIO1[0]
MAFE_DIN
Line for serially receiving samples from the AFE.
8137791 RevA
In this chapter, the term sample refers to a 16-bit data object that is transferred to or from
the modem through the MAFE, and the term sample period refers to the time from the start
of one sample to the start of the next.
STi7105
Name
22.3
MAFE pins (continued)

Type
Function name
(alternative)
Function description
PIO1[5]
MAFE_FS
Signal from the AFE indicating the start of a sampling

period. This is latched on falling edges of SCLK. For normal
operation it should not remain high for more than 16 SCLK
cycles, and there should be at least 20 SCLK ticks between
consecutive rising edges of FS.
PIO1[1]
MAFE_SCLK
Modem system clock. The frequency should be less than

50 MHz.
Software
The MAFE software manages the data exchange between the software modem and the
MAFE, and handles the control/status exchange.
22.3.1
Data exchange
Confidential
When the MAFE exchanges data, the software:

1.
disables all interrupts
2.
programs the clock path by setting bit DAA_SCLK_CTRL of SYS_CFG33
3.
sets the buffer size, for example, 100 samples (for handshake response times, the
buffer size could be as low as a few samples, for example 4)
4.
sets up both pairs of memory pointers in the MAFE (this is probably not changed again)
5.
enables status (complete) interrupt
6.
sets the control (run) bit
7.
deschedules
The MAFE then processes a buffer load of samples (that is, it transmits 100 samples and
receives 100 samples). When this is complete, the MAFE sets the status (complete) bit,
causing the software to be woken up. The software then:
8.
processes the receive memory buffer and fills the next transmit memory
9.
confirms that there has been no overflow (that is, failure to finish the software
processing of a buffer before that buffer has started to be overwritten again)
10. confirms that there have been no memory latency problems during the exchange of the
previous buffer, by reading the status (missed) bit
11. if there are no problems, the software writes to the MOD_ACK register and
deschedules
22.3.2
Control/status exchange
For a control/status exchange, the software writes to register MOD_INT_EN to enable the
status interrupt (CTRL_EMPTY), and then deschedules.
When the software wakes up, it reads the modem status and disables the status interrupt
(CTRL_EMPTY) again.
8137791 RevA
403/454
Table 63.
Modem analog front end (MAFE) interface registers
STi7105
23
Caution:
Register addresses are provided as ModemBaseAddress + offset.
The ModemBaseAddress is 0xFD05 8000
MAFE interface register summary
Offset
Register
Description
Page
0x00
MOD_CTRL_1
Control 1
on page 404
0x04
MOD_STA_1
Status 1
on page 405
0x08
MOD_INT_EN
Interrupt enable
on page 405
0x0C
MOD_ACK
Acknowledge
on page 406
0x10
MOD_BUFF_SIZE
Buffer size
on page 406
0x14
MOD_CTRL_2
Control 2
on page 406
0x18
MOD_STA_2
Status 2
on page 407
0x20
MOD_RECEIVE0_PTR
Receive memory buffer 0 start address
on page 407
0x24
MOD_RECEIVE1_PTR
on page 407
0x28
MOD_TX0_PTR
Transmit memory buffer 0 start address
on page 408
0x2C
MOD_TX1_PTR
on page 408
MOD_CTRL_1
7
Control 1
6
RESERVED
Address:
ModemBaseAddress + 0x00
Type:
RW
Reset:
Undefined
START
RUN
Description:
[7:2] RESERVED
[1] START:
Indicates which of the two pairs of memory buffer pointers it should start off using:
0: Indicates MOD_RECEIVE0_PTR and MOD_TX0_PTR.
1: Indicates MOD_RECEIVE1_PTR and MOD_TX1_PTR.
[0] RUN:
1: The MAFE interface is to start exchanging data with the AFE.
0: The MAFE interface stops after completing the exchange of the current buffer load of
samples.
404/454
8137791 RevA
Confidential
Table 64.
STi7105
MOD_STA_1
7
Status 1
6
RESERVED
MISSED
OVERFLOW
LAST
CTRL_EMPTY
COMPLETE
IDLE
Address:
Type:
Reset:
Undefined
Description:
[5] MISSED:
1: Indicates that the memory latency is too high, causing a sample to be missed (the MAFE
interface is exchanging samples faster than they can be read from or written to the memory
buffers).
Cleared by writing to MOD_ACK.
Confidential
[4] OVERFLOW:
1: Indicates that overflow has occurred (the MAFE interface has completed the exchange of
another buffer load of samples before the software has acknowledged the previous buffer load).
[3] LAST: Indicates the last pair of buffer pointers used by the DMA.
[2] CTRL_EMPTY:
Set to 0 by writing to MOD_CTRL_1.
Set to 1 when the MAFE interface has completed the control/status exchange.
[1] COMPLETE:
Set to 1 when a buffer load of samples has been exchanged.
[0] IDLE:
0: The MAFE interface is exchanging data with the AFE.
1: The MOD_CTRL_1.RUN bit is low and the MAFE interface is not exchanging data. After the
software clears the RUN bit, the MAFE interface goes idle only when it has finished exchanging
the current buffer load of samples.
Address:
Type:
RW
Reset:
Undefined
INT_IDLE
INT_COMPLETE
RESERVED
Interrupt enable
INT_CTRL_EMPTY
MOD_INT_EN
Description:
[7:3] RESERVED
8137791 RevA
405/454
[7:6] RESERVED
STi7105
[2] INT_CTRL_EMPTY:
Enables the MOD_STA_1.CTRL_EMPTY interrupt.
1: Indicates the interrupt is enabled.
0: Indicates the interrupt is disabled.
[1] INT_COMPLETE:
Enables the MOD_STA_1.COMPLETE interrupt.
MOD_ACK
Acknowledge
Confidential
ACK
Address:
ModemBaseAddress + 0x0C
Type:
Reset:
Undefined
Description:
[7:0] ACK: Acknowledge
Clears the overflow, missed and complete flags in register MOD_STA_1.
MOD_BUFF_SIZE
7
Buffer size
SIZE
Address:
Type:
RW
Reset:
Undefined
RESERVED
Description:
[7:1] SIZE: Buffer size (the number of 16-bit samples in a buffer).
This value must be a multiple of two.
[0] RESERVED
MOD_CTRL_2
15
14
Control 2
13
12
11
10
CTRL_VAL
Address:
Type:
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8137791 RevA
[0] INT_IDLE:
Enables the MOD_STA_1.IDLE interrupt.
STi7105
Reset:
Undefined
Description:
[15:0] CTRL_VAL: Control value to send out to the MAFE interface
MOD_STA_2
15
14
Status 2
13
12
11
10
Address:
Type:
Reset:
Undefined
Description:
[15:0] STATUS: Status value received from the MAFE interface.

9
ADDR
Address:
Type:
RW
Reset:
Undefined
Description:
Start address of RECEIVE_MEM_BUFF_0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
Undefined
Description:
Start address of RECEIVE_MEM_BUFF_1.
8137791 RevA
0
RESERVED
MOD_RECEIVE1_PTR
ADDR
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
MOD_RECEIVE0_PTR
407/454
STATUS

8
Type:
R/W
Reset:
Undefined
Description:
Start address of TX_MEM_BUFF_0
MOD_TX1_PTR
Confidential
ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
ModemBaseAddress + 0x2C
Type:
R/W
Reset:
Undefined
Description:
Start address of TX_MEM_BUFF_1.
408/454
8137791 RevA
Address:
0
RESERVED
ADDR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
MOD_TX0_PTR
STi7105
STi7105
24
Direct access arrangement (DAA)
Direct access arrangement (DAA)

The direct access arrangement provides a programmable line interface to communicate with
a telephone line.
Confidential
See Silicon Laboratories Inc. document 32 4 MHz Differential-Link Interface DAA Embedded System-Side DAA Module Specification.
8137791 RevA
409/454
Integrated modem codec
25
STi7105
Integrated modem codec

The modem codec sub-system consist of a single-channel mono voice codec IP and the
existing PCM player and reader. The I/O interfaces are between the codec ADC on the input
side and the DAC on the output side.
GPFifo size is tbd kBytes.
fS = 7.2, 8, 9.6 kHz
Figure 67. Modem codec block diagram

0 (for slave mode)
SET_MASTER
PCMR_M_SCLK PCMR_M_LRClk
Validation use
Dangle
Dangle
(64xFs)
ADC
INP
(Fs)
PCM READER
PCM_CLKL
SCLK
OUTP
(Fs)
FSYNC_IN
OUTM
SCLK_IN
DAC
(64xFs)
Data
GPFIFO
FSYNC
Dangle
PCM PLAYER
CLK_APPL
MCLK
1-channel voice codec
Boundary of Modem Codec
MCLK 512xFs
410/454
8137791 RevA
STBus 32-bit 100/133 MHz
Confidential
INM
GPFIFO
Data
When in slave mode, fSync and Sclk are generated by the PCM player. The DAC also
generates data for the reader, which is also in slave mode, synchronous to these signals.
Data format between ADC-Reader/Player-DAC will be I2S (one skipped Sclk), MSB First.
STi7105
Remote controller interface
26
26.1
Overview
The infrared (IR) transmitter/receiver is an ST40 peripheral that supports RC5, RC6 and
RECS80, RC-MM 1.5, and DIRECTV. For each symbol transmitted, the software driver
determines the symbol period and the symbol on-time of the IR pulse, and transfers these
parameters into an eight-word deep FIFO. The IR transmitter/receiver then generates coded
symbols using an internally-generated subcarrier clock.
The incoming signal must be detected, and the subcarrier must be suppressed, externally.
Only the symbol envelope can be used by the IR and UHF processors. It is sampled at
10 MHz and the sample values are transferred into the input buffer in microseconds.
Figure 68. IR transmitter/receiver symbol
Confidential
Symbol on time
Symbol period
26.2
Functional description
The IR transmitter/receiver transmits infrared data and receives both IR and UHF data. The
IR and UHF receivers are independent and identical, except that the IR receiver does not
use the noise filter. Both receivers are simultaneously active. The IR transmitter/receiver
supports RC (remote control) codes only.
Figure 69 shows the IR transmitter/receiver block diagram in a typical circuit configuration
with input demodulating and output buffering (open drain).
In the transmitter there are two programmable dividers to generate the prescaled clock and
the subcarrier clock. The subcarrier clock sets the resolution for the transmitted data. Both
receivers contain a sampling rate clock, which samples the incoming data and is
programmed to 10 MHz.
FIFOs buffer both the transmitter output and the receivers inputs to avoid timing problems
with the CPU. Interrupts can be set on the FIFOs levels to prevent input data overrun and
output data underrun.
The two receivers each have one input pin (IRB_IR_IN and IR_UHF_IN), and the transmitter
has two output pins (IRB_IR_DATAOUT driven directly and IRB_IR_DATAOUT_OD
inverted as open drain).
There are six 8-word FIFOs: two in the RC transmitter and two in each RC receiver. The
eighth word in each FIFO is used internally and is not accessible. Therefore a FIFO is empty
when there are seven empty words and full when it contains seven words. At all times, the
fullness level of the FIFO is given in its corresponding status register.
8137791 RevA
411/454
The parameters symbol period and symbol on-time are shown in Figure 68.
STi7105
Each submodule pair of FIFOs, for symbol period and symbol on-time, should be treated as
a set and must be consecutively accessed for read or for write. They share a common
pointer, which is incremented only when they have been accessed correctly. Repeated
reads on one FIFO always give the same data, and repeated writes always overwrite the
previous data.
Figure 69 shows the complete system, and Figure 70, the receiver subsystem.
UHF data in
RC receive
code processor
PIO3[4]
Demod and
carrier suppress
Input
signal
Confidential
Bus interface
UHF processor
RC transmit
code processor
IR data out
PIO3[5]
PIO3[6]
RC receive
code processor
IR data in
PIO3[3]
IR module
Demod and
carrier suppress
IR processor
Input
signal
Note: PIO3[6] must be programmed in open drain mode
STBus
POLINV_REG
Noise
suppression
filter
(UHF only)
Polarity
inversion
logic
IRB_IR_IN and
IR_UHF_IN
Retime
26.2.1
SCD
SCD_UHF/IR_OUT
Mux
UHF/IR_WAKEUP
Figure 70. IR/UHF receiver block diagram
SCD_DETECTED
SYMBOL_TIME_OUT
Symbol time
count logic
RC transmit code processor

Remote control codes are generated by programming the transmit frequency and writing the
symbol information into a FIFO, which is then read internally and the data processed to
provide a serial PWM data stream. The transmit interrupt is set on a preselected FIFO level.
412/454
8137791 RevA
Figure 69. IR/UHF transmitter/receiver block diagram and implementation
STi7105

An interrupt and a flag in the status register indicate an underrun condition (that is, an empty
FIFO). RC data transmission is disabled by setting bit IRB_TX_EN.TX_EN to 0.
The transmit interrupt is set by register IRB_TX_EN, on one of three FIFO levels:
when seven words are empty (buffer is empty)
when four words are empty (buffer is half full)
when at least one word is empty
The transmit interrupt is cleared automatically when new data is written to registers
IRB_TX_SYMB_PER and IRB_TX_ON_TIME. Register bits IRB_TX_INT_STA [4:1] give
the FIFOs fullness status.
The symbol period, in subcarrier cycles, is programmed in register IRB_TX_SYMB_PER

and the on time of the IR pulse is written to register IRB_TX_ON_TIME. These two registers
are eight-word FIFOs. They must be programmed sequentially as a pair to increment the
write pointer and be ready for the next data. Transmission is enabled by setting bit
IRB_TX_EN.TX_EN to 1. If new data is not written before the last symbol in the buffer is
transmitted, no RC codes are generated. The output is driven to logic 0 and bit
IRB_TX_INT_STA.UNDERRUN: is set.
Before data can be transmitted, the underrun condition must be cleared as follows:
1.
Disable the transmission by writing 0 to register IRB_TX_EN.TX_EN_IR.
2.
Load at least one block of data into IRB_RX_ON_TIME_UHF_IR and

IRB_TX_ON_TIME_IR.
3.
Clear the TX_UNDERRUN status bit by writing 1 to register

IRB_TX_INT_CLR_IR.UNDERRUN.
Transmission is resumed by writing 1 to register IRB_TX_EN.TX_EN_IR.
26.2.2
RC receive code processor

This section describes the UHF data and the IR data receivers. They are independent and
identical except that the noise suppression filter is programmable in the UHF receiver, and is
not used in the IR receiver. The 10 MHz sampling clock is common to both receivers and is
set by register IRB_RX_STA_UHF. This register is programmed with the value 10 for a
100 MHz infrared transmitter/receiver system clock.
Each receiver processes the incoming RC code symbol envelope and stores the values
symbol period and symbol on-time (in s) in an eight-word FIFO buffer, until the data can be
read by the microcontroller.
The receive interrupt is set by register IRB_RX_SYMB_PER_UHF to one of the following
three FIFO levels:
at least one word is available to be read
four or more words are available to be read (FIFO half full)
seven words are available to be read (FIFO full)
The interrupt is cleared when registers IRB_RX_ON_TIME_UHF and

IRB_RX_ON_TIME_IR have been read. They must be read consecutively, as a pair, to
increment the FIFO read pointer. Bits 4 and 5 of register IRB_RX_INT_EN_UHF give the
fullness level of the FIFO.
8137791 RevA
413/454
Confidential
The frequency of the subcarrier is set by programming registers IRB_TX_PRESCALER and

IRB_TX_SUBCARR.
STi7105
If the FIFO is full and has not been read before the arrival of new data, then this data is lost
and a receive overrun flag is set in the status register IRB_RX_INT_EN_UHF. No new data
is written to the FIFO while this condition exists.
1.
Read at least one word from each of the receive FIFO registers,
IRB_RX_ON_TIME_UHF and IRB_RX_ON_TIME_IR.
2.
Clear the overrun flag by writing 0x01 to register IRB_RX_MAX_SMB_PER_UHF.
The last symbol is detected using a time-out condition whose value is stored (in s) in
register IRB_IRDA_RX_MAX_SYMB_PER. If no pulse has been received during this time
then the last word in the FIFO IRB_RX_MAX_SYMB_PER has a value 0xFFFF. If the value
of bit IRB_RX_SYMB_PER_UHF.LAST_SYMB_INT_EN is 1, then an interrupt is triggered
and the status register IRB_RX_INT_EN_UHF.LAST_SYMB_INT is set. The interrupt and
its status bit are cleared automatically when the last value in the FIFO has been read.
When IRB_RX_SYMB_PER_UHF.INT_EN is set to 0 then both the FIFO level interrupt and
the last symbol interrupt are inhibited.
Confidential
Remote control data reception can be disabled by setting

IRB_RX_SYMB_PER_UHF.INT_EN to 0. However, both receivers are normally always
enabled.
The polarity of input IRB_UHF_IN or IRB_IR_IN can be inverted by setting bit 0 in one of the
polarity invert registers IRB_POL_INV_IR.
26.2.3
Noise suppression filter

This filter is turned off in the IR receiver and is programmable in the UHF receiver by using
register IRB_RX_NOISE_SUPP_WID_IR_UHF. Any pulses, either high or low, having a
value in microseconds of less than the programmed width, are assumed to be noise and,
therefore, suppressed.
The noise suppression filter can be disabled by writing 0x00 to register
IRB_RX_NOISE_SUPP_WID_IR_UHF.
26.3
Start code detector

The start code detector detects any programmable start code on the RC-Rx input. The
length of the start code (number of bits), the minimum, nominal and maximum time of the
input signal, and the start code are all programmable.
The start code detector works on a time unit called symbol time. The value of the input is
expected to be constant during the symbol period. If the value of the input violates the
symbol period, then the start code detector resets the start code detection process and
begins searching for start codes again.
The minimum and nominal symbol periods are programmed in two different registers,
IRB_SCD_SYMB_MIN_TIME and IRB_SCD_SYMB_NOM_TIME. For the symbol to be
valid, it has to be constant for at least the minimum symbol period. The symbol is registered
as 0 or 1 only after expiry of the nominal symbol time. The registering of the symbol is done
by the clock, which aligns itself to changes in the input data. This periodic phase alignment
ensures that wrong start codes are not detected and that valid start codes do not go
undetected.
414/454
8137791 RevA
To reset the overrun flag:
STi7105

The maximum number of symbols in a start code sequence is 32. The start code detector
can be programmed to detect a start code that is smaller than 32 symbols.
26.3.1
Generation of subcarrier
The methodology of subcarrier generation is documented in this section. Configuration of
different registers to generate subcarrier is discussed with an example. The prescaler
divides the comms clock (100 MHz) to get the required granularity.
For example, assume a 40 kHz clock with 50% duty cycle is to be generated.
Confidential
To achieve the above time period the prescaler can be configured for divide-by-10. The
output of the prescaler will be 100/10 = 10 MHz. This clock gives a granularity of 0.1 s in
subcarrier generation. To configure the prescaler in divide-by-10 mode, write 10 in the
prescaler register.
Register IRB_TX_SUBCARR_IR must be programmed with an appropriate value so that the
required time period for the subcarrier clock cycle is achieved. To generate a clock period of
25 s, write 250 to IRB_TX_SUBCARR_IR. This generates a clock of period 25 s, or
40 kHz.
To generate a 50% duty cycle, the subcarrier must be high for 12.5 s, by writing 125 to
IRB_TX_SUBCARR_WID_IR.
26.3.2
Signalling rates and pulse duration specification for IrDA

Table 65.
Signalling rate and pulse duration specification

Pulse duration (s)
Signalling rate (kb/s) Tolerance % of rate (+/-)

Min.
26.3.3
Nom.
Max.
9.6
0.87
1.41
19.53
22.13
19.2
0.87
1.41
9.77
11.07
38.4
0.87
1.41
4.88
5.96
57.6
0.87
1.41
3.26
4.34
115.2
0.87
1.41
1.63
2.23
Start code detection example

As an example, suppose the start code detector is programmed with the start code as
shown in Figure 71.
8137791 RevA
415/454
To generate the 40 kHz clock, the programmable counters must be programmed to generate
a clock of 25 s clock period and 12.5 s on-time. This is done because the time period and
on-time of the subcarrier are now programmable.
STi7105
Figure 71. Start code example
11
10
1 ms
2 ms
1 ms
2 ms
Confidential
Here, the nominal symbol duration is 500 s and there are 13 symbols (denoted as 12 to 0).
Because the data is shifted through the shift register, the data bit first received is the MSB.
1.
Because the SCD operates on a 100 MHz clock, program the prescaler to 100 (0x64).
The sampling clock is 1 MHz, and sampling resolution is 1 s.
2.
Program registers as follows:
450 (s) in register IRB_SCD_SYMB_MIN_TIME
500 (s) in IRB_SCD_SYMB_NOM_TIME, and
550 (s) in IRB_SCD_SYMB_MAX_TIME
3.
Program IRB_SCD_CODE with 0b1 0011 1100 1111 and IRB_SCD_CODE_LEN with
13 (0x0E) corresponding to 13 symbols to be detected.
4.
Start the start code detection by setting the EN and RE_SEARCH bits in
IRB_SCD_CFG to 1.
The start code detector checks for the minimum symbol time of each register and the
sequence in which symbols are received. If the symbol time is not respected by the input
UHF (if noisy) the start code detection is re-initialized.
Constraints on SCD registers

The following relationships need to be respected:
IRB_SCD_SYMB_MAX_TIME <= (IRB_SCD_SYMB_NOM_TIME * 1.5)
IRB_SCD_SYMB_MIN_TIME >= (IRB_SCD_SYMB_NOM_TIME * 0.5)
(IRB_SCD_SYMB_MAX_TIME - IRB_SCD_SYMB_NOM_TIME) >= 4
(IRB_SCD_SYMB_NOM_TIME - IRB_SCD_SYMB_MIN_TIME) >= 4
Start code should not be equal to the reset value (all zeros).
IRB_SCD_CODE_LEN 0x00 corresponds to 32-bit standard and alternative start

codes.
If there is only one start code to be detected, the registers for normal and alternative
start codes must be programmed with identical values, as do the
IRB_SCD_CODE_LEN values.
Noise recovery
416/454
IRB_SCD_NOISE_RECOV is provided to overcome possible issues in detecting

a valid start code in cases where noise preceding the start code has the same
logic level as that of a start code LSB; in such cases the SCD logic may fail to
detect a valid start if this register is not enabled. For example, considering the
8137791 RevA
500 s
12
STi7105

start code of Figure 71 (0b1 0011 1100 1111) noise at logic level 1 must be
ignored.
Example: Start code is 13-bit, 0b1 0011 1100 1111:
IRB_SCD_NOISE_RECOV
.EN = 1: The noise recovery feature is enabled.
.LOGIC_LEV = 1: The logical value of first symbol in start code is 1.
Confidential
.NCSSLV = 00001 because there is change in logic value after the first symbol of
the start code.
8137791 RevA
417/454
Remote controller interface registers
STi7105
27
Caution:
This section describes the RC transmitter and receiver registers, the RC and UHF receiver
and control registers and the noise suppression registers of the IR transmitter/receiver.
Although the IR RC receiver and UHF RC receiver registers are held at different addresses,
their register descriptions are identical and are only given once for each pair of registers.
Registers are suffixed with _IR and _UHF as appropriate.
Register addresses are provided as IRBBaseAddress + offset.

The IRBBaseAddress is: 0xFD01 8000
.
Table 66.
Infrared transmitter/receiver register summary
Offset
Register
Confidential
IR
Description
Page
UHF
RC transmitter
0x00
IRB_TX_PRESCALER
Clock prescaler.
page 420
0x04
IRB_TX_SUBCARR
Subcarrier frequency
programming.
page 420
0x08
IRB_TX_SYMB_PER
Symbol time programming.
page 421
0x0C
IRB_TX_ON_TIME
Symbol on time programming.
page 421
0x10
IRB_TX_INT_EN
Transmit interrupt enable.
page 421
0x14
IRB_TX_INT_STA
Transmit interrupt status.
page 422
0x18
IRB_TX_EN
RC transmit enable.
page 422
0x1C
IRB_TX_INT_CLR
Transmit interrupt clear.
page 423
0x20
IRB_TX_SUBCARR_WID
Subcarrier frequency
programming.
page 423
0x24
IRB_TX_STA
Transmit status.
page 424
RC receiver
418/454
0x40
0x80
IRB_RX_ON_TIME_IR,
IRB_RX_ON_TIME_UHF
Received pulse time capture.
page 425
0x44
0x84
IRB_RX_SYMB_PER_IR,
IRB_RX_SYMB_PER_UHF
Received symbol period capture.
page 425
0x48
0x88
IRB_RX_INT_EN_IR,
IRB_RX_INT_EN_UHF
Receive interrupt enable.
page 426
0x4C
0x8C
IRB_RX_INT_STA_IR,
IRB_RX_INT_STA_UHF
Receive interrupt status.
page 428
0x50
0x90
IRB_RX_EN_IR,
IRB_RX_EN_UHF
RC receive enable.
page 429
8137791 RevA
The STi7105 has one independent remote controller module, referred to as IRB.
STi7105

Table 66.
Offset
Register
Description
Page
0x94
IRB_RX_MAX_SMB_PER_IR,
IRB_RX_MAX_SMB_PER_UHF
Maximum RC symbol period.
page 430
0x98
IRB_RX_INT_CLR_IR,
IRB_RX_INT_CLR_UHF
Receive interrupt clear.
page 430
IRB_RX_NOISE_SUPP_WID_IR,
IRB_RX_NOISE_SUPP_WID_UHF
Noise suppression width.
page 432
IRB_RC_IO_SEL
I/O select RC or IrDA.
page 432
Reverse polarity data.
page 433
IRB_RX_STA_IR,
IRB_RX_STA_UHF
Receive status and interrupt

clear.
page 434
0x64
IRB_SAMPLE_RATE_COMM
Sampling frequency division.
page 435
0x70
IRB_CLK_SEL
Clock select configuration.
page 436
0x74
IRB_CLK_SEL_STA
Clock select status.
page 436
IR
UHF
0x54
0x58
0x5C
0x9C
I/O control
0x60
Reverse polarity
Confidential
0x68
0xA8
IRB_POL_INV_IR,
IRB_POL_INV_UHF
Receive status and clock

0x6C
0xAC
IrDA Interface
0xC0
IRB_IRDA_BAUD_RATE_GEN
Baud rate generation for IR.
page 436
0xC4
IRB_IRDA_BAUD_GEN_EN
Baud rate generation enable for

IR.
page 437
0xC8
IRB_IRDA_TX_EN
Transmit enable for IR.
page 437
0xCC -
IRB_IRDA_RX_EN
Receive enable for IR.
page 437
0xD0
IRB_IRDA_ASC_CTRL
Asynchronous data control.
page 438
0xD4
IRB_IRDA_RX_PULSE_STA
Receive pulse status for IR.
page 438
0xD8
IRB_IRDA_RX_SAMPLE_RATE
Receive sampling rate for IR.
page 438
IRB_IRDA_RX_MAX_SYMB_PER
Receive maximum symbol period page 439

for IR.
0xDC -
Start code detector

0x200 IRB_SCD_CFG
SCD configuration.
page 439
0x204 IRB_SCD_STA
SCD status.
page 440
0x208 IRB_SCD_CODE
Start code to be detected.
page 440
0x20
C
Start code length.
page 440
SCD minimum symbol time.
page 441
IRB_SCD_CODE_LEN
0x210 IRB_SCD_SYMB_MIN_TIME
8137791 RevA
419/454
Noise suppression

Table 66.
STi7105
Offset
Register
27.1
Description
Page
0x214 IRB_SCD_SYMB_MAX_TIME
SCD maximum symbol time.
page 441
0x218 IRB_SCD_SYMB_NOM_TIME
SCD nominal symbol time.
page 441
0x21
C
SCD prescaler value.
page 442
0x220 IRB_SCD_INT_EN
SCD detect interrupt enable.
page 442
0x224 IRB_SCD_INT_CLR
SCD detect interrupt clear.
page 442
0x22
C
SCD detect interrupt status.
page 443
0x228 IRB_SCD_NOISE_RECOV
SCD noise recovery

configuration.
page 443
0x230 IRB_SCD_ALT_CODE
Alternative start code to be

detected.
page 444
UHF
IRB_SCD_PRESCALER
IRB_SCD_INT_STA
RC transmitter registers
IRB_TX_PRESCALER
7
Clock prescaler
PRESCALE_VAL
Address:
IRBBaseAddress + 0x00
Type:
RW
Reset:
Description:
Selects the value of the prescaler for clock division. The prescaled clock frequency is
obtained by dividing the comms clock frequency by PRESCALE_VAL. It determines
the transmit subcarrier resolution, see IRB_TX_SUBCARR_IR.
IRB_TX_SUBCARR
15
14
13
12
Subcarrier frequency programming

11
10
SUBCARR_VAL
Address:
Type:
RW
Reset:
Description:
Determines the RC transmit subcarrier frequency. The prescaled clock frequency

divided by (SUBCARR_VAL x 2) gives the subcarrier frequency, which has a 50%
duty cycle.
420/454
8137791 RevA
Confidential
IR
STi7105
IRB_TX_SYMB_PER
15
14
13
12
Symbol time programming

11
10
Address:
Type:
Buffer:
8-word buffered
Reset:
Description:
Gives the symbol time (symbol period) in periods of the subcarrier clock. It must be
programmed sequentially with register IRB_TX_ON_TIME.
IRB_TX_ON_TIME
15
14
13
12
Symbol on time programming

11
10
Address:
IRBBaseAddress + 0x0C
Type:
Buffer:
8-word buffered
Reset:
Description:
Gives the symbol on time (pulse duration) in periods of the subcarrier clock.
Note: Registers IRB_TX_SYMB_PER and IRB_TX_ON_TIME act as a single register set.

They must be programmed sequentially as a pair to latch in the data.
11
10
Address:
Type:
RW
Reset:
0
INT_EN
12
UNDERRUN
13
EMPTY
14
HALF_EMPTY
15
Transmit interrupt enable
F_1WD
IRB_TX_INT_EN
RESERVED
Confidential
TX_ON_TIME_VAL
Description:
[15:5] RESERVED
[4] F_1WD:
1: Interrupt enable on at least one word empty in FIFO
[3] HALF_EMPTY:
1: Interrupt enable on FIFO half empty
[2] EMPTY:
1: Interrupt enable on FIFO empty
8137791 RevA
421/454
TX_SYMB_TIME_VAL
STi7105
[1] UNDERRUN:
1: Enable interrupt on underrun
[0] INT_EN: Interrupt enable
1: Global transmit interrupt enable
Type:
Reset:
Description:
This register is also updated when data is written into registers IRB_TX_SYMB_PER
and IRB_TX_IR_ON_TIME.
Confidential
Address:
[15:5] RESERVED
[4] F_1WD:
1: At least one word empty interrupt pending
[3] HALF_EMPTY:
1: FIFO half empty interrupt pending
[2] EMPTY:
1: FIFO Empty interrupt pending
[1] UNDERRUN:
1: Underrun interrupt pending
[0] INT_PEND: Interrupt pending
1: Global interrupt pending
IRB_TX_EN
7
RC transmit enable
6
RESERVED
Address:
Type:
RW
Reset:
0
TX_EN
Description:
[7:1] RESERVED
[0] TX_EN:
Enables the RC transmit processor. When it is set to 1 and there is data in the transmit FIFO,
then the RC processor is transmitting
422/454
8137791 RevA
10
INT_PEND
11
UNDERRUN
12
EMPTY
13
HALF_EMPTY
14
RESERVED
15
Transmit interrupt status
F_1WD
IRB_TX_INT_STA
STi7105
10
Address:
Type:
Reset:
0
RESERVED
11
UNDERRUN
12
EMPTY
13
HALF_EMPTY
14
RESERVED
15
Transmit interrupt clear
F_1WD
IRB_TX_INT_CLR
[31:29] RESERVED
[4] F_1WD:
1: Clear interrupt: at least one word empty in FIFO
Confidential
[3] HALF_EMPTY:
1: Clear interrupt: FIFO half-empty
[2] EMPTY:
1: Clear interrupt: FIFO empty
[1] UNDERRUN:
1: Clear interrupt: underrun
[0] RESERVED
IRB_TX_SUBCARR_WID
15
14
13
12
11
Subcarrier frequency programming

10
SUBCARR_WID_VAL
Address:
Type:
RW
Reset:
Description:
The pulse width of the subcarrier generated is programmed into this register. Loading
a value k into this register keeps the subcarrier high for n * k comms clock cycles.
Where n is the value loaded into the IRB_TX_PRESCALER register. Software has to
ensure that the value written in this register is less than that written in register
IRB_TX_SUBCARR. If the condition is not met, the subcarrier is not generated.
8137791 RevA
423/454
Description:
Address:
Type:
Reset:
0x1C
RESERVED
Description:
[11:15] RESERVED
Confidential
[10:8] TX_FIFO_LEVEL:
000: FIFO empty
010: 2 blocks in FIFO
001: 1 block in FIFO

111: 7 blocks in FIFO (full)
[7:5] RESERVED
[4] F_1WD:
1: At least one word empty in FIFO
[3] HALF_EMPTY:
1: FIFO half empty
[2] EMPTY:
1: FIFO empty
[1] UNDERRUN:
1: FIFO underrun
[0] RESERVED
Clearing an interrupt does not clear the corresponding status flag. The status reflects
the true transmit status.
424/454
8137791 RevA
RESERVED
10
UNDERRUN
11
EMPTY
12
HALF_EMPTY
13
TX_FIFO_LEVEL
14
RESERVED
15
Transmit status
F_1WD
IRB_TX_STA
STi7105
STi7105
27.2
RC receiver registers
If not explicitly stated the following registers are common to both the RC IR receiver and the
RC UHF receiver. The first address given is the RC IR receiver (IR). The registers are
distinguished by the suffix _IR for the IR receiver and _UHF for the UHF receiver.
IRB_RX_ON_TIME_IR
15
14
13
12
Received pulse time capture

11
10
Address:
Type:
Buffer:
8-word buffered
Reset:
Description:
Detected duration of the received RC pulse in microseconds. Must be read

sequentially with register IRB_RX_SYMB_PER.
IRB_RX_ON_TIME_UHF
15
14
13
12
11
Received pulse time capture

10
RX_ONTIME_VAL
Address:
Type:
Buffer:
8-word buffered
Reset:
Description:
Detected duration of the received RC pulse in microseconds. Must be read

sequentially with register IRB_RX_SYMB_PER.
IRB_RX_SYMB_PER_IR
15
14
13
12
11
Received symbol period capture

10
RX_SYMB_TIME_VAL
Address:
Type:
Buffer:
8-word buffered
Reset:
Description:
Detected time between the start of two successive received RC pulses, in

microseconds.
Note:
Registers IRB_RX_SYMB_PER and IRB_RX_IR_ON_TIME act as a register set. A new

value can only be read after reading both registers sequentially.
8137791 RevA
425/454
Confidential
RX_ONTIME_VAL
IRB_RX_SYMB_PER_UHF
15
14
13
12
11
STi7105
Received symbol period capture

10
Address:
Type:
Buffer:
8-word buffered
Reset:
Description:
Detected time between the start of two successive received RC pulses, in

microseconds.
Registers IRB_RX_SYMB_PER and IRB_RX_IR_ON_TIME act as a register set. A new

value can only be read after reading both registers sequentially.
10
Address:
Type:
RW
Reset:
Description:
[15:6] RESERVED
[5] ATLEAST_1WD:
1: Enable interrupt on at least one word in FIFO
[4] HALF_FULL:
1: Enable interrupt on FIFO half-full
[3] FULL:
1: Enable interrupt on FIFO full
[2] OVERRUN:
1: Enable interrupt on overrun
[1] LAST_SYMB_INT_EN:
1: Enable interrupt on last symbol receive
[0] INT_EN:
1: Enable global receive interrupt
426/454
8137791 RevA
INT_EN
11
LAST_SYMB_INT_EN
12
OVERRUN
13
FULL
14
RESERVED
Confidential
15
Receive interrupt enable
HALF_FULL
IRB_RX_INT_EN_IR
ATLEAST_1WD
Note:
RX_SYMB_TIME_VAL
STi7105
Address:
Type:
RW
Reset:
INT_EN
10
LAST_SYMB_INT_EN
11
OVERRUN
12
FULL
13
HALF_FULL
14
RESERVED
15
Receive interrupt enable
ATLEAST_1WD
IRB_RX_INT_EN_UHF
Description:
[15:6] RESERVED
Confidential
[5] ATLEAST_1WD:
1: Enable interrupt on at least one word in FIFO
[4] HALF_FULL:
1: Enable interrupt on FIFO half-full
[3] FULL:
1: Enable interrupt on FIFO full
[2] OVERRUN:
1: Enable interrupt on overrun
[1] LAST_SYMB_INT_EN:
1: Enable interrupt on last symbol receive
[0] INT_EN:
1: Enable global receive interrupt
8137791 RevA
427/454
Address:
Type:
Reset:
Description:
[15:6] RESERVED
[5] ATLEAST_1WD:
1: At least one word in FIFO interrupt pending
Confidential
[4] HALF_FULL:
1: Half-full interrupt pending
[3] FULL:
1: FIFO full interrupt pending
[2] OVERRUN:
1: FIFO overrun pending
[1] LAST_SYMB_INT:
1: Last symbol receive interrupt pending
[0] INT:
Global receive interrupt pending
428/454
8137791 RevA
INT
10
LAST_SYMB_INT
11
OVERRUN
12
FULL
13
HALF_FULL
14
RESERVED
15
Receive interrupt status

ATLEAST_1WD
IRB_RX_INT_STA_IR
STi7105
STi7105
Address:
Type:
Reset:
Description:
[15:6] RESERVED
[5] ATLEAST_1WD:
1: At least one word in FIFO interrupt pending
Confidential
[4] HALF_FULL:
1: Half-full interrupt pending
[3] FULL:
1: FIFO full interrupt pending
[2] OVERRUN:
1: FIFO overrun pending
[1] LAST_SYMB_INT:
1: Last symbol receive interrupt pending
[0] INT:
Global receive interrupt pending
IRB_RX_EN_IR
7
RC receive enable
5
RESERVED
Address:
Type:
RW
Reset:
0
RX_EN
Description:
[7:1] RESERVED
[0] RX_EN:
1: The RC receive section is enabled to read incoming data.
8137791 RevA
429/454
INT
10
LAST_SYMB_INT
11
OVERRUN
12
FULL
13
ATLEAST_1WD
14
RESERVED
15
Receive interrupt status
HALF_FULL
IRB_RX_INT_STA_UHF
IRB_RX_EN_UHF
7
STi7105
RC receive enable
RESERVED
Address:
Type:
RW
Reset:
RX_EN
Description:
[7:1] RESERVED
1: The RC receive section is enabled to read incoming data.
IRB_RX_MAX_SMB_PER_IR
15
14
13
12
11
Maximum RC symbol period
10
Address:
Type:
RW
Reset:
Description:
Sets the maximum symbol period (in microseconds) which is necessary to define the
time out for recognizing the end of the symbol stream.
IRB_RX_MAX_SMB_PER_UHF
15
14
13
12
11
10
Maximum RC symbol period

9
RX_MAX_SYMB_TIME
Address:
Type:
RW
Reset:
Description:
Sets the maximum symbol period (in microseconds) which is necessary to define the
time out for recognizing the end of the symbol stream.
10
Address:
Type:
430/454
8137791 RevA
0
RESERVED
11
LAST_SYMB_INT
12
OVERRUN
13
FULL
14
HALF_FULL
15
Receive interrupt clear

ATLEAST_1WD
IRB_RX_INT_CLR_IR
RESERVED
Confidential
RX_MAX_SYMB_TIME
[0] RX_EN:
STi7105
Reset:
Description:
Set to 1 as part of the procedure for clearing flags in register IRB_RX_INT_EN_UHF.

No new data is written into the receive FIFO while these bits are set.
[15:6] RESERVED
[5] ATLEAST_1WD:
1: Clear interrupt: at least one word in FIFO
[4] HALF_FULL:
1: Clear interrupt: FIFO half-full
[2] OVERRUN:
1: Clear interrupt: FIFO overrun
[1] LAST_SYMB_INT:
1: Clear interrupt: last symbol receive
10
0
RESERVED
11
LAST_SYMB_INT
12
OVERRUN
13
FULL
14
HALF_FULL
15
Receive interrupt clear

ATLEAST_1WD
IRB_RX_INT_CLR_UHF
RESERVED
Confidential
[0] RESERVED
Address:
Type:
Reset:
Description:
Set to 1 as part of the procedure for clearing flags in register IRB_RX_INT_EN_UHF.

No new data is written into the receive FIFO while these bits are set.
[15:6] RESERVED
[5] ATLEAST_1WD:
[4] HALF_FULL:
1: Clear interrupt: FIFO half-full
[3] FULL:
1: Clear interrupt: FIFO full
[2] OVERRUN:
[1] LAST_SYMB_INT:
[0] RESERVED
8137791 RevA
431/454
[3] FULL:
1: Clear interrupt: FIFO full
27.3
STi7105
Noise suppression
IRB_RX_NOISE_SUPP_WID_IR
15
14
13
12
11
10

9
Address:
Type:
RW
Reset:
Description:
Determines the maximum width of noise pulses, in microseconds, which the filter
suppresses.
IRB_RX_NOISE_SUPP_WID_UHF
15
14
13
12
11
10
Confidential
NOISE_SUPP_WID
Address:
Type:
RW
Reset:
Description:
Determines the maximum width of noise pulses, in microseconds, which the filter
suppresses.
27.4
I/O control
IRB_RC_IO_SEL
7
I/O select RC or IrDA

5
RESERVED
0
IO_SEL
Address:
Type:
RW
Reset:
Description:
Selects the data type on IRBn_IR_DATAOUT and IRBn_IR_IN pins.This register is

present only in the receive interface for IR signals.
[7:1] RESERVED
[0] IO_SEL:
0: RC data
1: IrDA data
432/454
8137791 RevA
NOISE_SUPP_WID
STi7105
27.5
Reverse polarity
The two IRB input pins (IRB_IR_IN {PIO3 bit 3} and IRB_UHF_IN {PIO3 bit 4}) are inverted
internally from high to low. To account for this, IRB_IR_IN and IRB_UHF_IN should be
configured as PIO inputs and the bits in the POLINV registers set to 1.
Reverse polarity data

5
RESERVED
Address:
Type:
RW
Reset:
0
POLARITY
Description:
Confidential
[7:1] RESERVED
[0] POLARITY:
0: No polarity inversion
This bit should always be set to 1
IRB_POL_INV_UHF
7
1: Polarity of IR data inverted
Reverse polarity data

5
RESERVED
Address:
IRBBaseAddress + 0xA8
Type:
RW
Reset:
0
POLARITY
Description:
[7:1] RESERVED
[0] POLARITY:
0: No polarity inversion
This bit should always be set to 1
8137791 RevA
1: Polarity of IR data inverted
433/454
IRB_POL_INV_IR
Receive status and clock
Address:
Type:
Reset:
RESERVED
LAST_SYMB
10
OVERRUN
11
FULL
12
HALF_FULL
13
RX_FIFO_LEVEL
14
RESERVED
15
Receive status and interrupt clear

AT_LEAST_1WD
IRB_RX_STA_IR
RESERVED
27.6
STi7105
Description:
[15:11] RESERVED
Confidential
[10:8] RX_FIFO_LEVEL:
000: FIFO empty
001: 1 block FIFO

[7:6] RESERVED
[5] AT_LEAST_1WD:: At least one word
[4] HALF_FULL:
1: Clear interrupt: FIFO half full
[3] FULL:
1: Clear interrupt FIFO full
[2] OVERRUN:
[1] LAST_SYMB: Last symbol
[0] RESERVED
Note: Clearing the interrupt does not clear the status. To clear the status, appropriate
actions (such as reading the data from the FIFO) have to be performed.
Address:
434/454
IRBBaseAddress + 0xAC
8137791 RevA
0
RESERVED
LAST_SYMB
OVERRUN
10
FULL
11
HALF_FULL
12
AT_LEAST_1WD
13
RX_FIFO_LEVEL
14
RESERVED
15
Receive status and interrupt clear
RESERVED
IRB_RX_STA_UHF
STi7105
Type:
Reset:
Description:
[15:11] RESERVED
[10:8] RX_FIFO_LEVEL:
000: FIFO empty
001: 1 block FIFO

[5] AT_LEAST_1WD:: At least one word

[4] HALF_FULL:
1: Clear interrupt: FIFO half full
Confidential
[3] FULL:
1: Clear interrupt FIFO full
[2] OVERRUN:
[1] LAST_SYMB: Last symbol
[0] RESERVED
Note: Clearing the interrupt does not clear the status. To clear the status, appropriate
actions (such as reading the data from the FIFO) have to be performed.
IRB_SAMPLE_RATE_COMM
7
Sampling frequency division

4
RESERVED
Address:
Type:
RW
Reset:
Description:
Programs the sampling rate for the RC codes receive section. A 4-bit counter with
auto reload feature generates the sampling frequency. This counter is configured
such that the output of this counter is 10 MHz.
The clock is divided by N.
This is a common register for both IR and UHF receivers.
8137791 RevA
435/454
[7:6] RESERVED
Clock select configuration

6
RESERVED
CLK_SEL
Address:
Type:
RW
Reset:
Description:
Used to select if the receive sections (both RC and UHF) are clocked by the
CLK_IC_DIV2 system clock or the 27 MHz clock. In low power mode it is expected
that the system clock is switched off. The noise suppression filter is clocked by
27 MHz clock to ensure the filtering takes place on the received signal even in the low
power mode.
[7:1] RESERVED: Set to 0
[0] CLK_SEL:
0: System clock
1: 27 MHz clock
Confidential
IRB_CLK_SEL_STA
7
Clock select status
RESERVED
CLK_STA
Address:
Type:
Reset:
Description:
Used to infer if the receive section is clocked by the system clock or the 27 MHz clock.
After changing the clocking mode by programming register IRB_CLK_SEL, software
has to read this register to see if the programmed clock change has happened.
[7:1] RESERVED
[0] CLK_STA:
0: System clock
27.7
1: 27 MHz clock
IrDA Interface
IRB_IRDA_BAUD_RATE_GEN
15
14
13
12
11
10
Baud rate generation for IR

9
ASCBAUD
Address:
IRBBaseAddress + 0xC0
Type:
RW
Reset:
Undefined
Description:
The baud rate generation is exactly same as in ASC. It has a 16-bit counter with autoreload capability. This register holds the value ASCBAUD to be loaded into the
counter.
436/454
8137791 RevA
IRB_CLK_SEL
STi7105
STi7105

ASCBAUD can be calculated by the formula:
ASCBAUD = fCOMMS/ (16* baudrate)
Baud rate
Reload value
(to 3 dec places)
Reload value
(Integer)
Reload value
(Hex)
Approximate
deviation
9600
651.042
651
0x28B
0.01%
19200
325.521
326
0x146
0.15%
34.8 k
179.600
180
0x0B4
0.22%
57.6 k
108.507
109
0x06D
0.45%
115.2 k
54.250
54
0x036
0.46%
IRB_IRDA_BAUD_GEN_EN
7
Baud rate generation enable for IR
Confidential
RESERVED
Address:
Type:
RW
Reset:
Description:
1: The baud rate generator is enabled.
IRB_IRDA_TX_EN
7
Transmit enable for IR

5
RESERVED
Type:
RW
Reset:
Description:
1: The IrDA transmit section is enabled.
IRB_IRDA_RX_EN
6
0
IRTX_EN
Address:
0
BRG_EN
Receive enable for IR

5
RESERVED
Address:
IRBBaseAddress + 0xCC
Type:
RW
Reset:
Description:
1: The IrDA receive section is enabled.
8137791 RevA
0
IRRX_EN
437/454
Table 67.
where fCOMMS is the CPU clock frequency. For a comms clock frequency of 100 MHz,
the values to be loaded into BAUD_RATE_GEN_IRDA are shown in Table 67 below.
Bit fields in interrupt enable register
IRB_IRDA_ASC_CTRL
7
STi7105
Asynchronous data control

5
RESERVED
0
ASC_CTRL
Address:
IRBBaseAddress + 0xD0
Type:
RW
Reset:
Description:
Controls the data on pins IRB_IR_DATAOUT_OD and IR_UHF_IN.

0: IrDA data is available on pins IRB_IR_DATAOUT_OD and IR_UHF_IN.
IRB_IRDA_RX_PULSE_STA
7
Receive pulse status for IR
Confidential
RESERVED
0
P_STA
Address:
Type:
Reset:
Description:
Set to one if there is pulse width violation of IrDA input signal from the infrared
detector. This bit is set to 0 when it is read.
IRB_IRDA_RX_SAMPLE_RATE
7
Receive sampling rate for IR
RESERVED
0
N
Address:
Type:
Reset:
Undefined
Description:
The sampling frequency of the IrDA receive signal is selected by programming this
register. If fIRB is the module clock frequency, then this register must be programmed
with a value N such that fIRB/N = 10 MHz.
438/454
8137791 RevA
1: Asynchronous data is available on pins IRB_IR_DATAOUT_OD and IR_UHF_IN.
STi7105
IRB_IRDA_RX_MAX_SYMB_PER
15
14
13
12
11
10
Receive maximum symbol period for IR
Address:
IRBBaseAddress + 0xDC
Type:
Reset:
Undefined
Description:
The maximum symbol time for which the IR pulse should be high is programmed in
this register. If a value M is written in this register, then the maximum pulse duration is
M/10 s. If an IR pulse greater than this time is detected then the IR pulse is
neglected.
SCD
Address:
Type:
RW
Reset:
EN
RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RE_SEARCH
SCD configuration
SW_RST
IRB_SCD_CFG
RST_SFT
27.8
Description:
[31:4] RESERVED
[3] RST_SFT:
Reset shift register only. SCD_STA is not affected.
[2] SW_RST:
Reset all counters and shift register.
[1] RE_SEARCH:
1: Start a new search
Asserting RE_SEARCH while start code detection is in progress has no effect. The purpose of
this bit is to provide software a capability to force a restart when SCD has already detected a
start code and symbol-time-out does not occur.
[0] EN:
0: Bypass SCD, UHF sent to UHF_OUT
8137791 RevA
1: Enable start code detection
439/454
Address:
Type:
Reset:
Description:
SCD status.
[31:2] RESERVED
[1] ALT:
1: Alternative code detected
Confidential
[0] DETECT:
1: Start code detected, UHF sent to UHF_OUT
IRB_SCD_CODE
Start code to be detected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CODE
Address:
Type:
RW
Reset:
Description:
Start code to be detected.
[31:0] CODE: Start code to be detected.
IRB_SCD_CODE_LEN
Start code length
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
ALT_CODE_LEN
Address:
Type:
RW
Reset:
Description:
Length of the start code in symbols.
[31:13] RESERVED
[12:8] ALT_CODE_LEN: Alternative start code length
[7:5] RESERVED
[4:0] CODE_LEN: Start code lengtth
440/454
8137791 RevA
RESERVED
CODE_LEN
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DETECT
SCD status
ALT
IRB_SCD_STA
STi7105
STi7105
IRB_SCD_SYMB_MIN_TIME
SCD minimum symbol time
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
Description:
Minimum time of a symbol. If any symbol is shorter than this value, the SCD process
is re-initialized. The symbol time counting is done by a clock (enable pulse) output
from the pre-scaler. If the minimum time of the symbol is n pre-scaler clock periods,
the SCD_SYMB_MIN_TIME register should be programmed with a value of (n-1). For
example, if a value 0xF is written into this register, the symbol minimum time is 16
pre-scaler clock periods.
[31:0] MIN_SYMB_TIME: Minimum symbol time.
IRB_SCD_SYMB_MAX_TIME
SCD maximum symbol time
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
MAX_SYMB_TIME
Address:
Type:
RW
Reset:
Description:
Maximum time of a symbol. Any changes in the input data are allowed only between
symbol minimum time and symbol maximum time. The symbol time counting is done
by a clock (enable pulse) output from the pre-scaler. If the maximum time of the
symbol is n pre-scaler clock periods, the SCD_SYMB_MAX_TIME register should be
programmed with a value of (n-1). For example, if a value 0xF is written into this
register, the symbol maximum time is 16 pre-scaler clock periods.
[31:0] MAX_SYMB_TIME: Maximum symbol time.
IRB_SCD_SYMB_NOM_TIME
SCD nominal symbol time
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NOM_TIME
Address:
Type:
RW
Reset:
Description:
Nominal time for a symbol. This value is used by SCD to register a new symbol for
when consecutive identical symbols are received. The symbol time counting is done
by a clock (enable pulse) output from the pre-scaler. If the SCD nominal time is n prescaler clock periods, the SCD_SYMB_NOM_TIME register should be programmed
with a value of (n-1).For example, if a value 0xF is written into this register, the symbol
nominal time is 16 pre-scaler clock periods.
[31:0] NOM_TIME: Normal symbol time.
8137791 RevA
441/454
MIN_SYMB_TIME
IRB_SCD_PRESCALER
STi7105
SCD prescaler value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
PRE_SCALER
Address:
Type:
RW
Reset:
0x01
Description:
Prescaler division value.
[31:16] RESERVED
IRB_SCD_INT_EN
SCD detect interrupt enable

8
RESERVED
SCD_DETECTED
Address:
Type:
RW
Reset:
Description:
Enable interrupt on SCD detected.
[31:1] RESERVED
[0] SCD_DETECTED:
0: Disable interrupt
IRB_SCD_INT_CLR
1: Enable interrupt
SCD detect interrupt clear

9
0
SCD_INT_CLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
Reset:
Description:
Clear SCD-detected interrupt. This register clears the interrupt only when the SCD is
functioning on the interconnect clock.
[31:1] RESERVED
[0] SCD_INT_CLR:
0: No change on interrupt
442/454
1: Clear interrupt
8137791 RevA
[15:0] PRE_SCALER: Pre scaler division value is stored in this register.
STi7105
Type:
Reset:
Description:
Status of SCD detected interrupt.
[31:1] RESERVED
1: Pending interrupt
SCD noise recovery configuration
Address:
Type:
R/W
Reset:
Description:
NCSSLV
RESERVED
ALT_EN
ALT_LOGIC_LEV
RESERVED
ALT_NCSSLV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
IRB_SCD_NOISE_RECOV
RESERVED
Confidential
[0] SCD_DETECTED_STA:
0: No pending interrupt
[31:29] RESERVED
[28:24] ALT_NCSSLV: Number of contiguous symbols at same logical value as first symbol, for
alternate code
0x00: Noise recovery disabled
0x01
0x02
...
0x1E
0x1F
[23:18] RESERVED
[17] ALT_LOGIC_LEV: Logic level for alternative code
0: Alt code starts with 0
1: Alt code starts with 1
[16] ALT_EN: Enable noise recovery for alternative code
0: Noise recovery disabled
1: Noise recovery enabled
[15:13] RESERVED
8137791 RevA
443/454
RESERVED
Address:
0
SCD_DETECTED_STA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
EN
SCD detect interrupt status
LOGIC_LEV
IRB_SCD_INT_STA
STi7105
[12:8] NCSSLV: Number of contiguous symbols at same logical value as first symbol
[7:2] RESERVED
[1] LOGIC_LEV: Logic level
0: Code starts with 0
1: Code starts with 1
[0] EN: Enable noise recovery

0: Noise recovery disabled
1: Noise recovery enabled
IRB_SCD_ALT_CODE
Alternative start code to be detected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
Confidential
Description:
[31:0] ALT_CODE: Start code to be detected.
444/454
8137791 RevA
ALT_CODE
STi7105
28
Key scanner
Key scanner
The STi7105 key scanner (KS) module provides a front panel switch interface managed as a
matrix of rows and columns.
An embedded finite state machine runs a scanning algorithm, detects switch toggles and
generates interrupts to the CPU. A double buffering mechanism is used to store the
configuration of the switches.
The parameters are:
matrix size
1 to 4 rows, set by Y_DIM of KS_MATRIX_X_Y_DIM
1 to 4 columns, set by X_DIM of KS_MATRIX_X_Y_DIM
switch debounce duration
scanning duration (max period is 40ms)
Confidential
The CPU detects the valid configuration of switches.
28.1
Debounce
The key scanner module incorporates a programmable counter as a debounce timer to
allow for the different properties of switches. This counter is initialized to the programmed
value in the register KS_DEBOUNCE_TIME as soon one the KeyScanOut[i] output is set to
1 to scan the row i.
Glitch inputs are filtered by the timer re-initializing to the programmed value if at least one bit
of the scanned row KeyScanIn[j] changes while the timer is counting.
The programmable debounce time is also the period a key must remain pressed before an
interrupt to the CPU is generated.
A nominal 100 MHz clock is used by the key scanner module to set the debounce time and
scanning duration. The scanning duration is independent of the matrix size; the complete
4x4 matrix is scanned and unwanted keys filtered according to the programmed matrix
configuration. The effective scan duration is therefore 4 x the programmed debounce time.
With a maximum programmable debounce time of 10.4 ms, the CPU has a maximum of
41 ms (scan time = 10.4 ms per row x 4 rows) before a detected state is overwritten.
28.2
Operation
Scanning
The key scanner sequentially scans each row of the matrix. For each row it:
debounces the row
identifies the status of each switch on the row
stores the row data
If a button is accidently pressed or released during a row scan the timer is re-initialized and
the scan sequence repeats.
8137791 RevA
445/454
Key scanner
STi7105
Detection
If, during the scan sequence, the row data does not match that stored by the matrix state
register (KS_MATRIX_STATE) the new data overwrites the old data and an interrupt is
generated.
Note:
The interrupt is cleared as soon the CPU performs a read operation on the matrix state
register.
28.3
Key scanner pads

KS pins
Signal
I/O
Voltage
Description
KEY_SCANOUT[0]
PIO7[0], PIO5[0]
KEY_SCANOUT[1]
PIO7[1], PIO5[1]
Confidential
3.3
Key Scanner outputs
KEY_SCANOUT[2]
PIO7[2], PIO5[2]
KEY_SCANOUT[3]
PIO7[3], PIO5[3]
KEY_SCANIN[0]
PIO5[4]
KEY_SCANIN[1]
PIO5[5]
I
446/454
Comments
3.3
Key Scanner inputs
KEY_SCANIN[2]
PIO5[6]
KEY_SCANIN[3]
PIO5[7]
8137791 RevA
Table 68.
STi7105
Key scanner registers
29
Caution:
Register bits that are shown as reserved must not be modified by software because this will
cause unpredictable behavior.
Register addresses are provided as KeyScanBaseAddress + offset.
The KeyScanBaseAddress is:
KeyScanBaseAddress: 0xFE02 0000
Offset
Register
Description
Page
0x00
KS_CONFIG
Key scanner configuration
on page 447
0x04
KS_DEBOUNCE_TIME
Key scanner de-bounce timer
on page 447
0x08
KS_MATRIX_STATE
Key scanner matrix_state
on page 448
0x18
KS_MATRIX_X_Y_DIM
Key scanner matrix dimension

configuration
on page 448
KS_CONFIG
Key scanner configuration

9
Address:
KeyScanBaseAddress + 0x00
Type:
RW
Reset:
ENABLE
RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Description:
[31:1] RESERVED
[0] ENABLE: Key Scanner enable
0: Scanner off
Key scanner de-bounce timer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
DB_TIMER
0
RESERVED
KS_DEBOUNCE_TIME
1: Scanner on
8137791 RevA
447/454
Key scanner register summary
RESERVED
Confidential
Table 69.

Type:
RW
Reset:
STi7105
Description:
[31:20] RESERVED
[19:1] DB_TIMER: programmable de-bounce time (up to ~10ms)
[0] RESERVED
Key scanner matrix_state
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
STATE
Address:
Type:
RW
Reset:
Description:
[31:16] RESERVED
[15:0] STATE: registers valid switch states (R3, R2, R1, R0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address:
Type:
RW
Reset:
Description:
[31:4] RESERVED
[3:2] Y_DIM: matrix row size 1:4 -> defines the number of rows
[1:0] X_DIM: matrix column size 1:4 -> defines the number of columns
448/454
8137791 RevA
X_DIM
Key scanner matrix dimension configuration
Y_DIM
KS_MATRIX_X_Y_DIM
RESERVED
Confidential
RESERVED
KS_MATRIX_STATE
STi7105
List of registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
AHBn_EHCI_INT_STS . . . . . . . . . . . . . . . . . .115
AHBn_EHCI_PME_STATUS_ACK . . . . . . . . .120
AHBn_FL_ADJ . . . . . . . . . . . . . . . . . . . . . . . .114
AHBn_NEXT_POWER_STATE . . . . . . . . . . .117
AHBn_OHCI . . . . . . . . . . . . . . . . . . . . . . . . . .116
AHBn_OHCI_0_APP_IO_HIT . . . . . . . . . . . . .118
AHBn_OHCI_0_APP_IRQ1 . . . . . . . . . . . . . .118
AHBn_OHCI_0_APP_IRQ12 . . . . . . . . . . . . .119
AHBn_OHCI_0_LGCY_IRQ . . . . . . . . . . . . . .120
AHBn_OHCI_INT_STS . . . . . . . . . . . . . . . . . .114
AHBn_POWER_STATE . . . . . . . . . . . . . . . . .117
AHBn_SIMULATION_MODE . . . . . . . . . . . . .117
AHBn_SS_PME_ENABLE . . . . . . . . . . . . . . .119
AHBn_STRAP . . . . . . . . . . . . . . . . . . . . . . . . .115
AHBnPC_CHUNK_CFG . . . . . . . . . . . . . . . . .122
AHBnPC_MSG_CFG . . . . . . . . . . . . . . . . . . .121
AHBnPC_OPC . . . . . . . . . . . . . . . . . . . . . . . .121
AHBnPC_STATUS . . . . . . . . . . . . . . . . . . . . .122
AHBnPC_SW_RESET . . . . . . . . . . . . . . . . . .122
ASCn_BAUDRATE . . . . . . . . . . . . . . . . . . . . .381
ASCn_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . .385
ASCn_GUARDTIME . . . . . . . . . . . . . . . . . . . .388
ASCn_INT_EN . . . . . . . . . . . . . . . . . . . . . . . .386
ASCn_RETRIES . . . . . . . . . . . . . . . . . . . . . . .390
ASCn_RX_BUF. . . . . . . . . . . . . . . . . . . . . . . .385
ASCn_RX_RST. . . . . . . . . . . . . . . . . . . . . . . .389
ASCn_STA . . . . . . . . . . . . . . . . . . . . . . . . . . .387
ASCn_TIMEOUT. . . . . . . . . . . . . . . . . . . . . . .389
ASCn_TX_BUF . . . . . . . . . . . . . . . . . . . . . . . .384
ASCn_TX_RST . . . . . . . . . . . . . . . . . . . . . . . .389
EMI_CFG_DATA0. . . . . . . . . . . . . . . . . . . . . . .48
EMI_CFG_DATA1. . . . . . . . . . . . . . . . . . . . . . .49
EMI_CFG_DATA2. . . . . . . . . . . . . . . . . . . . . . .49
EMI_CFG_DATA3. . . . . . . . . . . . . . . . . . . . . . .50
EMI_CLK_EN . . . . . . . . . . . . . . . . . . . . . . . . . .47
EMI_FLASH_CLK_SEL . . . . . . . . . . . . . . . . . .45
EMI_GEN_CFG . . . . . . . . . . . . . . . . . . . . . . . .44
EMI_LCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
EMI_MPX_CFG . . . . . . . . . . . . . . . . . . . . . . . .56
EMI_MPX_CLK_SEL . . . . . . . . . . . . . . . . . . . .46
EMI_STA_CFG . . . . . . . . . . . . . . . . . . . . . . . . .43
EMI_STA_LCK . . . . . . . . . . . . . . . . . . . . . . . . .44
EMIB_BANK_EN. . . . . . . . . . . . . . . . . . . . . . . .55
EMIB_BANK0_BASE_ADDR . . . . . . . . . . . . . .52
EMIB_BANK5_BASE_ADDR . . . . . . . . . . . . . . 54
EMINAND_ADD . . . . . . . . . . . . . . . . . . . . . . . . 78
EMINAND_ADDR_REG1 . . . . . . . . . . . . . . . . . 73
EMINAND_ADDR_REG2 . . . . . . . . . . . . . . . . . 73
EMINAND_ADDR_REG3 . . . . . . . . . . . . . . . . . 74
EMINAND_BLOCK_ZERO_REMAP . . . . . . . . 65
EMINAND_BOOTBANK_CFG . . . . . . . . . . . . . 59
EMINAND_CMD. . . . . . . . . . . . . . . . . . . . . . . . 78
EMINAND_CTL_TIMING . . . . . . . . . . . . . . . . . 63
EMINAND_EXTRA_REG . . . . . . . . . . . . . . . . . 78
EMINAND_FLEX_ADD_REG. . . . . . . . . . . . . . 71
EMINAND_FLEX_CS_ALT . . . . . . . . . . . . . . . 68
EMINAND_FLEX_DATA . . . . . . . . . . . . . . . . . 72
EMINAND_FLEX_DATA_RD_CFG . . . . . . . . . 69
EMINAND_FLEX_DATAWRT_CFG. . . . . . . . . 68
EMINAND_FLEX_MUXCTRL. . . . . . . . . . . . . . 67
EMINAND_FLEXCMD . . . . . . . . . . . . . . . . . . . 69
EMINAND_FLEXMODE_CFG . . . . . . . . . . . . . 66
EMINAND_GEN_CFG . . . . . . . . . . . . . . . . . . . 80
EMINAND_INT_CLR . . . . . . . . . . . . . . . . . . . . 62
EMINAND_INT_EDGE_CFG . . . . . . . . . . . . . . 63
EMINAND_INT_EN . . . . . . . . . . . . . . . . . . . . . 61
EMINAND_INT_STA . . . . . . . . . . . . . . . . . . . . 62
EMINAND_MULTI_CS_CFG . . . . . . . . . . . . . . 74
EMINAND_RBn_STA . . . . . . . . . . . . . . . . . . . . 60
EMINAND_REN_TIMING. . . . . . . . . . . . . . . . . 65
EMINAND_SEQ_CFG . . . . . . . . . . . . . . . . . . . 79
EMINAND_SEQ_REG1 . . . . . . . . . . . . . . . . . . 75
EMINAND_SEQ_REG2 . . . . . . . . . . . . . . . . . . 76
EMINAND_SEQ_REG3 . . . . . . . . . . . . . . . . . . 76
EMINAND_SEQ_REG4 . . . . . . . . . . . . . . . . . . 77
EMINAND_SEQ_STA . . . . . . . . . . . . . . . . . . . 81
EMINAND_VERSION. . . . . . . . . . . . . . . . . . . . 72
EMINAND_WEN_TIMING . . . . . . . . . . . . . . . . 64
EMISS_CONFIG . . . . . . . . . . . . . . . . . . . . . . . 42
GMAC_ADDR0_HI . . . . . . . . . . . . . . . . . . . . . 282
GMAC_ADDR0_LO . . . . . . . . . . . . . . . . . . . . 282
GMAC_ADDRone_HI . . . . . . . . . . . . . . . . . . . 283
GMAC_ADDRone_LO . . . . . . . . . . . . . . . . . . 283
GMAC_ADDRsixteen_HI . . . . . . . . . . . . . . . . 310
GMAC_ADDRsixteen_LO . . . . . . . . . . . . . . . 311
GMAC_BUS_MODE. . . . . . . . . . . . . . . . . . . . 312
GMAC_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 268
GMAC_CSR_WAKE_UP . . . . . . . . . . . . . . . . 277
GMAC_CUR_RX_BUF_ADDR. . . . . . . . . . . . 327
GMAC_CUR_RX_DESC . . . . . . . . . . . . . . . . 327
GMAC_CUR_TX_BUF_ADDR . . . . . . . . . . . . 327
GMAC_CUR_TX_DESC . . . . . . . . . . . . . . . . 326
GMAC_DMA_CTRL . . . . . . . . . . . . . . . . . . . . 320
8137791 RevA
449/454
Confidential
List of registers
STi7105
GMAC_DMA_INT_EN. . . . . . . . . . . . . . . . . . .323
GMAC_DMA_STA . . . . . . . . . . . . . . . . . . . . .316
GMAC_FLOW_CTRL . . . . . . . . . . . . . . . . . . .275
GMAC_FRAME . . . . . . . . . . . . . . . . . . . . . . . .270
GMAC_HASH_TBL_HI . . . . . . . . . . . . . . . . . .272
GMAC_HASH_TBL_LO . . . . . . . . . . . . . . . . .273
GMAC_INT_MASK . . . . . . . . . . . . . . . . . . . . .281
GMAC_INT_STA. . . . . . . . . . . . . . . . . . . . . . .280
GMAC_MII_ADDR . . . . . . . . . . . . . . . . . . . . .273
GMAC_MII_DATA . . . . . . . . . . . . . . . . . . . . . .274
GMAC_MISSED_FRAME_CTR . . . . . . . . . . .325
GMAC_PMT_CTRL . . . . . . . . . . . . . . . . . . . .279
GMAC_RCV_BASE_ADDR . . . . . . . . . . . . . .315
GMAC_RCV_POLL_DEMAND . . . . . . . . . . . .314
GMAC_VERSION . . . . . . . . . . . . . . . . . . . . . .277
GMAC_VLAN_TAG. . . . . . . . . . . . . . . . . . . . .276
GMAC_XMT_BASE_ADDR . . . . . . . . . . . . . .315
GMAC_XMT_POLL_DEMAND . . . . . . . . . . . .314
GMMC_CTRL . . . . . . . . . . . . . . . . . . . . . . . . .284
GMMC_INTR_MSK_RX . . . . . . . . . . . . . . . . .288
GMMC_INTR_MSK_TX . . . . . . . . . . . . . . . . .290
GMMC_INTR_RX . . . . . . . . . . . . . . . . . . . . . .284
GMMC_INTR_TX . . . . . . . . . . . . . . . . . . . . . .286
GMMC_IPC_INTR_MSK_RX . . . . . . . . . . . . .306
GMMC_IPC_INTR_RX . . . . . . . . . . . . . . . . . .309
IRB_CLK_SEL . . . . . . . . . . . . . . . . . . . . . . . .436
IRB_CLK_SEL_STA . . . . . . . . . . . . . . . . . . . .436
IRB_IRDA_ASC_CTRL . . . . . . . . . . . . . . . . . .438
IRB_IRDA_BAUD_GEN_EN . . . . . . . . . . . . . .437
IRB_IRDA_BAUD_RATE_GEN . . . . . . . . . . .436
IRB_IRDA_RX_EN . . . . . . . . . . . . . . . . . . . . .437
IRB_IRDA_RX_MAX_SYMB_PER . . . . . . . . .439
IRB_IRDA_RX_PULSE_STA . . . . . . . . . . . . .438
IRB_IRDA_RX_SAMPLE_RATE . . . . . . . . . .438
IRB_IRDA_TX_EN . . . . . . . . . . . . . . . . . . . . .437
IRB_POL_INV_IR . . . . . . . . . . . . . . . . . . . . . .433
IRB_POL_INV_UHF . . . . . . . . . . . . . . . . . . . .433
IRB_RC_IO_SEL . . . . . . . . . . . . . . . . . . . . . .432
IRB_RX_EN_IR. . . . . . . . . . . . . . . . . . . . . . . .429
IRB_RX_EN_UHF . . . . . . . . . . . . . . . . . . . . . .430
IRB_RX_INT_CLR_IR. . . . . . . . . . . . . . . . . . .430
IRB_RX_INT_CLR_UHF . . . . . . . . . . . . . . . . .431
IRB_RX_INT_EN_IR . . . . . . . . . . . . . . . . . . . .426
IRB_RX_INT_EN_UHF . . . . . . . . . . . . . . . . . .427
IRB_RX_INT_STA_IR . . . . . . . . . . . . . . . . . . .428
IRB_RX_INT_STA_UHF . . . . . . . . . . . . . . . . .429
IRB_RX_MAX_SMB_PER_IR. . . . . . . . . . . . .430
IRB_RX_MAX_SMB_PER_UHF . . . . . . . . . . .430
IRB_RX_NOISE_SUPP_WID_IR . . . . . . . . . .432
IRB_RX_NOISE_SUPP_WID_UHF . . . . . . . .432
IRB_RX_ON_TIME_IR . . . . . . . . . . . . . . . . . .425
IRB_RX_ON_TIME_UHF . . . . . . . . . . . . . . . .425
450/454
IRB_RX_STA_IR . . . . . . . . . . . . . . . . . . . . . . 434
IRB_RX_STA_UHF . . . . . . . . . . . . . . . . . . . . 434
IRB_RX_SYMB_PER_IR . . . . . . . . . . . . . . . . 425
IRB_RX_SYMB_PER_UHF . . . . . . . . . . . . . . 426
IRB_SAMPLE_RATE_COMM . . . . . . . . . . . . 435
IRB_SCD_ALT_CODE . . . . . . . . . . . . . . . . . . 444
IRB_SCD_CFG . . . . . . . . . . . . . . . . . . . . . . . 439
IRB_SCD_CODE . . . . . . . . . . . . . . . . . . . . . . 440
IRB_SCD_CODE_LEN. . . . . . . . . . . . . . . . . . 440
IRB_SCD_INT_CLR . . . . . . . . . . . . . . . . . . . . 442
IRB_SCD_INT_EN . . . . . . . . . . . . . . . . . . . . . 442
IRB_SCD_INT_STA . . . . . . . . . . . . . . . . . . . . 443
IRB_SCD_NOISE_RECOV . . . . . . . . . . . . . . 443
IRB_SCD_PRESCALER . . . . . . . . . . . . . . . . 442
IRB_SCD_STA . . . . . . . . . . . . . . . . . . . . . . . . 440
IRB_SCD_SYMB_MAX_TIME . . . . . . . . . . . . 441
IRB_SCD_SYMB_MIN_TIME. . . . . . . . . . . . . 441
IRB_SCD_SYMB_NOM_TIME. . . . . . . . . . . . 441
IRB_TX_EN . . . . . . . . . . . . . . . . . . . . . . . . . . 422
IRB_TX_INT_CLR . . . . . . . . . . . . . . . . . . . . . 423
IRB_TX_INT_EN . . . . . . . . . . . . . . . . . . . . . . 421
IRB_TX_INT_STA . . . . . . . . . . . . . . . . . . . . . 422
IRB_TX_ON_TIME . . . . . . . . . . . . . . . . . . . . . 421
IRB_TX_PRESCALER . . . . . . . . . . . . . . . . . . 420
IRB_TX_STA . . . . . . . . . . . . . . . . . . . . . . . . . 424
IRB_TX_SUBCARR . . . . . . . . . . . . . . . . . . . . 420
IRB_TX_SUBCARR_WID . . . . . . . . . . . . . . . 423
IRB_TX_SYMB_PER . . . . . . . . . . . . . . . . . . . 421
KS_CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . 447
KS_DEBOUNCE_TIME . . . . . . . . . . . . . . . . . 447
KS_MATRIX_STATE . . . . . . . . . . . . . . . . . . . 448
KS_MATRIX_X_Y_DIM . . . . . . . . . . . . . . . . . 448
MOD_ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
MOD_BUFF_SIZE . . . . . . . . . . . . . . . . . . . . . 406
MOD_CTRL_1 . . . . . . . . . . . . . . . . . . . . . . . . 404
MOD_CTRL_2 . . . . . . . . . . . . . . . . . . . . . . . . 406
MOD_INT_EN . . . . . . . . . . . . . . . . . . . . . . . . 405
MOD_RECEIVE0_PTR . . . . . . . . . . . . . . . . . 407
MOD_RECEIVE1_PTR . . . . . . . . . . . . . . . . . 407
MOD_STA_1 . . . . . . . . . . . . . . . . . . . . . . . . . 405
MOD_STA_2 . . . . . . . . . . . . . . . . . . . . . . . . . 407
MOD_TX0_PTR . . . . . . . . . . . . . . . . . . . . . . . 408
MOD_TX1_PTR . . . . . . . . . . . . . . . . . . . . . . . 408
PCI_BOOTCFG_ADD . . . . . . . . . . . . . . . . . . . 96
PCI_BOOTCFG_DATA . . . . . . . . . . . . . . . . . . 97
PCI_BRIDGE_CONFIG . . . . . . . . . . . . . . . . . . 84
PCI_BRIDGE_INT_DMA_CLEAR . . . . . . . . . . 86
PCI_BRIDGE_INT_DMA_ENABLE . . . . . . . . . 85
PCI_BRIDGE_INT_DMA_STATUS . . . . . . . . . 86
PCI_BUFFADD0_FUNCn. . . . . . . . . . . . . . . . . 93
PCI_CCR_CAP_PTR . . . . . . . . . . . . . . . . . . . 104
PCI_CCR_CODE_REV . . . . . . . . . . . . . . . . . 102
8137791 RevA
Confidential
List of registers
List of registers
PCI_CCR_ID . . . . . . . . . . . . . . . . . . . . . . . . . .101
PCI_CCR_INT. . . . . . . . . . . . . . . . . . . . . . . . .104
PCI_CCR_IO_ADD . . . . . . . . . . . . . . . . . . . . .103
PCI_CCR_LAT_CACHSIZ . . . . . . . . . . . . . . .102
PCI_CCR_MEM_ADD . . . . . . . . . . . . . . . . . .103
PCI_CCR_NP_MEM_ADD . . . . . . . . . . . . . . .103
PCI_CCR_PMC . . . . . . . . . . . . . . . . . . . . . . .105
PCI_CCR_PMC_CSR . . . . . . . . . . . . . . . . . . .105
PCI_CCR_STS_CMD . . . . . . . . . . . . . . . . . . .101
PCI_CCR_SUBSYS_ID . . . . . . . . . . . . . . . . .104
PCI_CCR_TIMEOUT . . . . . . . . . . . . . . . . . . .105
PCI_CRP_ADD . . . . . . . . . . . . . . . . . . . . . . . . .98
PCI_CRP_RD_DATA . . . . . . . . . . . . . . . . . . . .99
PCI_CRP_WR_DATA . . . . . . . . . . . . . . . . . . . .99
PCI_CSR_ADDRESS . . . . . . . . . . . . . . . . . . . .99
PCI_CSR_BE_CMD . . . . . . . . . . . . . . . . . . . .100
PCI_CSR_RD_DATA . . . . . . . . . . . . . . . . . . .100
PCI_CSR_WR_DATA . . . . . . . . . . . . . . . . . . .100
PCI_CURRADDPTR_FUNCn . . . . . . . . . . . . . .95
PCI_DEVICEINTMASK_INT_CLEAR . . . . . . . .92
PCI_DEVICEINTMASK_INT_ENABLE . . . . . . .89
PCI_DEVICEINTMASK_INT_STATUS . . . . . . .90
PCI_FRAME_ADD . . . . . . . . . . . . . . . . . . . . . .95
PCI_FRAME_ADD_MASK . . . . . . . . . . . . . . . .96
PCI_FUNCn_BUFF_CONFIG . . . . . . . . . . . . . .94
PCI_FUNCn_BUFF_DEPTH. . . . . . . . . . . . . . .94
PCI_INTERRUPT_OUT . . . . . . . . . . . . . . . . . .88
PCI_TARGID_BARHIT . . . . . . . . . . . . . . . . . . .87
PIOn_CLR_PCOMP . . . . . . . . . . . . . . . . . . . .335
PIOn_CLR_PCx . . . . . . . . . . . . . . . . . . . . . . .333
PIOn_CLR_PMASK . . . . . . . . . . . . . . . . . . . .336
PIOn_CLR_POUT . . . . . . . . . . . . . . . . . . . . . .332
PIOn_PCOMP . . . . . . . . . . . . . . . . . . . . . . . . .334
PIOn_PCx . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
PIOn_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
PIOn_PMASK . . . . . . . . . . . . . . . . . . . . . . . . .335
PIOn_POUT . . . . . . . . . . . . . . . . . . . . . . . . . .331
PIOn_SET_PCOMP . . . . . . . . . . . . . . . . . . . .334
PIOn_SET_PCx . . . . . . . . . . . . . . . . . . . . . . .333
PIOn_SET_PMASK . . . . . . . . . . . . . . . . . . . .335
PIOn_SET_POUT . . . . . . . . . . . . . . . . . . . . . .331
PWM_CMP_OUT_VALx . . . . . . . . . . . . . . . . .397
PWM_CMP_VALx . . . . . . . . . . . . . . . . . . . . . .396
PWM_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . .401
PWM_CPT_CMP_CNT . . . . . . . . . . . . . . . . . .401
PWM_CPT_EDGEx . . . . . . . . . . . . . . . . . . . .397
PWM_CPT_VALx . . . . . . . . . . . . . . . . . . . . . .396
PWM_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . .397
PWM_INT_ACK . . . . . . . . . . . . . . . . . . . . . . .400
PWM_INT_EN. . . . . . . . . . . . . . . . . . . . . . . . .399
PWM_INT_STA. . . . . . . . . . . . . . . . . . . . . . . .399
PWM_VALx . . . . . . . . . . . . . . . . . . . . . . . . . . .396
RX1024TOMAXOCTETS_GB . . . . . . . . . . . . 304
RX128TO255OCTETS_GB . . . . . . . . . . . . . . 303
RX256TO511OCTETS_GB . . . . . . . . . . . . . . 303
RX512TO1023OCTETS_GB . . . . . . . . . . . . . 303
RX64OCTETS_GB. . . . . . . . . . . . . . . . . . . . . 302
RX65TO127OCTETS_GB . . . . . . . . . . . . . . . 302
RXALIGNMENTERROR. . . . . . . . . . . . . . . . . 300
RXBROADCASTFRAMES_G . . . . . . . . . . . . 300
RXCRCERROR . . . . . . . . . . . . . . . . . . . . . . . 300
RXFIFOOVERFLOW . . . . . . . . . . . . . . . . . . . 305
RXFRAMECOUNT_GB . . . . . . . . . . . . . . . . . 299
RXJABBERERROR . . . . . . . . . . . . . . . . . . . . 301
RXLENGTHERROR . . . . . . . . . . . . . . . . . . . . 304
RXMULTICASTFRAMES_G . . . . . . . . . . . . . 300
RXOCTETCOUNT_G. . . . . . . . . . . . . . . . . . . 299
RXOCTETCOUNT_GB . . . . . . . . . . . . . . . . . 299
RXOUTOFRANGETYPE . . . . . . . . . . . . . . . . 305
RXOVERSIZE_G . . . . . . . . . . . . . . . . . . . . . . 302
RXPAUSEFRAMES . . . . . . . . . . . . . . . . . . . . 305
RXRUNTERROR . . . . . . . . . . . . . . . . . . . . . . 301
RXUNDERSIZE_G . . . . . . . . . . . . . . . . . . . . . 301
RXUNICASTFRAMES_G . . . . . . . . . . . . . . . . 304
RXVLANFRAMES_GB . . . . . . . . . . . . . . . . . . 306
RXWATCHDOGERROR . . . . . . . . . . . . . . . . 306
SATA_AHB_CHUNK_CFG . . . . . . . . . . . . . . 215
SATA_AHB_MSG_CFG . . . . . . . . . . . . . . . . . 215
SATA_AHB_PC_GLUE_LOGIC. . . . . . . . . . . 217
SATA_AHB_STATUS. . . . . . . . . . . . . . . . . . . 216
SATA_AHB_SW_RESET . . . . . . . . . . . . . . . . 216
SATAn_AHB_OPC . . . . . . . . . . . . . . . . . . . . . 214
SATAn_CDR0 . . . . . . . . . . . . . . . . . . . . . . . . 194
SATAn_CDR1 . . . . . . . . . . . . . . . . . . . . . . . . 195
SATAn_CDR2 . . . . . . . . . . . . . . . . . . . . . . . . 195
SATAn_CDR3 . . . . . . . . . . . . . . . . . . . . . . . . 196
SATAn_CDR4 . . . . . . . . . . . . . . . . . . . . . . . . 196
SATAn_CDR5 . . . . . . . . . . . . . . . . . . . . . . . . 197
SATAn_CDR6 . . . . . . . . . . . . . . . . . . . . . . . . 197
SATAn_CDR7 . . . . . . . . . . . . . . . . . . . . . . . . 198
SATAn_CLR0 . . . . . . . . . . . . . . . . . . . . . . . . . 199
SATAn_DBTSR . . . . . . . . . . . . . . . . . . . . . . . 210
SATAn_DMA_BLOCK_STA . . . . . . . . . . . . . . 183
SATAn_DMA_CFG. . . . . . . . . . . . . . . . . . . . . 191
SATAn_DMA_CFG0_LSB . . . . . . . . . . . . . . . 175
SATAn_DMA_CFG0_MSB. . . . . . . . . . . . . . . 177
SATAn_DMA_CH_EN . . . . . . . . . . . . . . . . . . 191
SATAn_DMA_CLEAR_BLOCK . . . . . . . . . . . 189
SATAn_DMA_CLEAR_DST_TRAN . . . . . . . . 190
SATAn_DMA_CLEAR_ERR. . . . . . . . . . . . . . 190
SATAn_DMA_CLEAR_SRC_TRAN. . . . . . . . 189
SATAn_DMA_CLEAR_TFR . . . . . . . . . . . . . . 188
SATAn_DMA_COMP_TYPE . . . . . . . . . . . . . 193
SATAn_DMA_COMP_VERSION . . . . . . . . . . 193
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SATAn_DMA_CTRL0_LSB. . . . . . . . . . . . . . .170
SATAn_DMA_CTRL0_MSB . . . . . . . . . . . . . .173
SATAn_DMA_DAR0 . . . . . . . . . . . . . . . . . . . .168
SATAn_DMA_DST_TRAN . . . . . . . . . . . . . . .187
SATAn_DMA_DST_TRAN_STA . . . . . . . . . . .184
SATAn_DMA_ERR_STA . . . . . . . . . . . . . . . .185
SATAn_DMA_ID . . . . . . . . . . . . . . . . . . . . . . .192
SATAn_DMA_LLP0 . . . . . . . . . . . . . . . . . . . .169
SATAn_DMA_MASK_BLK . . . . . . . . . . . . . . .186
SATAn_DMA_MASK_ERR . . . . . . . . . . . . . . .188
SATAn_DMA_MASK_TFR . . . . . . . . . . . . . . .186
SATAn_DMA_RAW_BLOCK . . . . . . . . . . . . .181
SATAn_DMA_RAW_DST_TRAN . . . . . . . . . .182
SATAn_DMA_RAW_ERR . . . . . . . . . . . . . . . .182
SATAn_DMA_RAW_SRC_TRAN . . . . . . . . . .181
SATAn_DMA_RAW_TFR . . . . . . . . . . . . . . . .180
SATAn_DMA_SAR0 . . . . . . . . . . . . . . . . . . . .167
SATAn_DMA_SRC_TRAN . . . . . . . . . . . . . . .187
SATAn_DMA_SRC_TRAN_STA. . . . . . . . . . .184
SATAn_DMA_STATUS_INT . . . . . . . . . . . . . .190
SATAn_DMA_TEST . . . . . . . . . . . . . . . . . . . .192
SATAn_DMA_TFR_STA . . . . . . . . . . . . . . . . .183
SATAn_DMACR . . . . . . . . . . . . . . . . . . . . . . .209
SATAn_ERRMR . . . . . . . . . . . . . . . . . . . . . . .212
SATAn_FPBOR . . . . . . . . . . . . . . . . . . . . . . .208
SATAn_FPTAGR . . . . . . . . . . . . . . . . . . . . . .207
SATAn_FPTCR . . . . . . . . . . . . . . . . . . . . . . . .208
SATAn_IDR. . . . . . . . . . . . . . . . . . . . . . . . . . .214
SATAn_INTMR . . . . . . . . . . . . . . . . . . . . . . . .211
SATAn_INTPR . . . . . . . . . . . . . . . . . . . . . . . .211
SATAn_LLCR . . . . . . . . . . . . . . . . . . . . . . . . .212
SATAn_PHYCR . . . . . . . . . . . . . . . . . . . . . . .213
SATAn_PHYSR . . . . . . . . . . . . . . . . . . . . . . .213
SATAn_SCR0 . . . . . . . . . . . . . . . . . . . . . . . . .201
SATAn_SCR1 . . . . . . . . . . . . . . . . . . . . . . . . .202
SATAn_SCR2 . . . . . . . . . . . . . . . . . . . . . . . . .204
SATAn_SCR3 . . . . . . . . . . . . . . . . . . . . . . . . .206
SATAn_SCR4 . . . . . . . . . . . . . . . . . . . . . . . . .207
SATAn_VERSIONR . . . . . . . . . . . . . . . . . . . .214
SSCn_BRG . . . . . . . . . . . . . . . . . . . . . . . . . . .356
SSCn_BUS_FREE_TIME . . . . . . . . . . . . . . . .362
SSCn_CLR_STA. . . . . . . . . . . . . . . . . . . . . . .363
SSCn_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . .357
SSCn_DATA_SETUP_TIME. . . . . . . . . . . . . .361
SSCn_I2C_CTRL . . . . . . . . . . . . . . . . . . . . . .360
SSCn_INT_EN . . . . . . . . . . . . . . . . . . . . . . . .358
SSCn_NOISE_SUPP_WID . . . . . . . . . . . . . . .364
SSCn_NOISE_SUPP_WID_DOUT. . . . . . . . .365
SSCn_PRE_BRG . . . . . . . . . . . . . . . . . . . . . .363
SSCn_PRE_SCALER_DATAOUT . . . . . . . . .365
SSCn_PRESCALER . . . . . . . . . . . . . . . . . . . .364
SSCn_RBUFF . . . . . . . . . . . . . . . . . . . . . . . . .356
452/454
SSCn_REP_START_HOLD_TIME . . . . . . . . 361
SSCn_REP_START_SETUP_TIME . . . . . . . 361
SSCn_RX_FSTAT . . . . . . . . . . . . . . . . . . . . . 363
SSCn_SLA_ADDR . . . . . . . . . . . . . . . . . . . . . 360
SSCn_STA . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
SSCn_START_HOLD_TIME . . . . . . . . . . . . . 361
SSCn_STOP_SETUP_TIME . . . . . . . . . . . . . 362
SSCn_TBUFF. . . . . . . . . . . . . . . . . . . . . . . . . 356
SSCn_TX_FSTAT . . . . . . . . . . . . . . . . . . . . . 362
TX1024TOMAXOCTETS_GB . . . . . . . . . . . . 294
TX128TO255OCTETS_GB . . . . . . . . . . . . . . 293
TX256TO511OCTETS_GB . . . . . . . . . . . . . . 294
TX512TO1023OCTETS_GB . . . . . . . . . . . . . 294
TX64OCTETS_GB . . . . . . . . . . . . . . . . . . . . . 293
TX65TO127OCTETS_GB . . . . . . . . . . . . . . . 293
TXBROADCASTFRAMES_G. . . . . . . . . . . . . 292
TXBROADCASTFRAMES_GB . . . . . . . . . . . 295
TXCARRIERERROR . . . . . . . . . . . . . . . . . . . 297
TXDEFERRED . . . . . . . . . . . . . . . . . . . . . . . . 297
TXEXCESSCOL . . . . . . . . . . . . . . . . . . . . . . . 297
TXEXCESSDEF . . . . . . . . . . . . . . . . . . . . . . . 298
TXFRAMECOUNT_G. . . . . . . . . . . . . . . . . . . 298
TXFRAMECOUNT_GB . . . . . . . . . . . . . . . . . 292
TXLATECOL. . . . . . . . . . . . . . . . . . . . . . . . . . 297
TXMULTICASTFRAMES_G. . . . . . . . . . . . . . 292
TXMULTICASTFRAMES_GB . . . . . . . . . . . . 295
TXMULTICOL_G . . . . . . . . . . . . . . . . . . . . . . 296
TXOCTETCOUNT_G . . . . . . . . . . . . . . . . . . . 298
TXOCTETCOUNT_GB. . . . . . . . . . . . . . . . . . 292
TXPAUSEFRAMES . . . . . . . . . . . . . . . . . . . . 298
TXSINGLECOL_G . . . . . . . . . . . . . . . . . . . . . 296
TXUNDERFLOWERROR. . . . . . . . . . . . . . . . 296
TXUNICASTFRAMES_GB . . . . . . . . . . . . . . . 295
TXVLANFRAMES_G . . . . . . . . . . . . . . . . . . . 299
8137791 RevA
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List of registers
STi7105
Revision history
Revision history
Document revision history
Revision
22-Aug-2008
Changes
Initial release.
Confidential
Date
Table 70.
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Confidential
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Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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soft modem support: MAFE or DAA

This volume contains information to assist with

ST40-300 core 400 MHz

Main video DEI

6 DACs HDMI VTGs

Conventions used in this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

EMI operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

EMI address map and memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock reconfiguration for synchronous interfaces . . . . . . . . . . . . . . . . . 14

Default/reset configuration for MPX boot . . . . . . . . . . . . . . . . . . . . . . . . 16

Peripheral interface (with synchronous flash memory support) . . . . . . . . 16

Synchronous burst flash support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Burst interrupt and burst reiteration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Synchronous burst enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Support for lower clock rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Use of flash memories in different banks with contiguous memory spaces

Chip select allocation/bank configuration . . . . . . . . . . . . . . . . . . . . . . . 23

Address bus extension to low order bits . . . . . . . . . . . . . . . . . . . . . . . . 23

Master functionality operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Target functionality operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Device configuration specific operation . . . . . . . . . . . . . . . . . . . . . . . . . 31

NAND flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DVB-CI /POD and ATAPI support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

HDD PIO mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

EMI subsystem register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

EMI register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

EMI buffer register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

EMI NAND flash support registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

EMI NAND flash addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

EMI NAND flash register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

EMIBank register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PCI Host Function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

PCI Configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

USB 2.0 host (USBH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Configuration register formats for peripherals . . . . . . . . . . . . . . . . . . . . 48

STBus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

USB 2.0 host (USBH) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Base Addresses and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

AHB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

AHBPC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Serial ATA (SATA) subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Introduction to the SATA subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

PHY feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SATA Controller feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SATA host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

DMA data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

SATA PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Low power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Reset management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Serial ATA (SATA) host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Host overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Internal communication paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129