EECT 7325 VLSI DESIGN

256 word (word size is 8 bits)

SRAM DESIGN
Under the guidance of Carl Sechen
By

MADHURI M KAGINELE (mmk140330)

NIDHI GUNDIGARA (nhg140030)

TABLE OF CONTENTS
1.

INTRODUCTION ................................................................................................................................ 4
1.1 Introduction to SRAM ........................................................................................................................ 4
1.2 SRAM Architecture ............................................................................................................................ 4
1.3 8T (Eight transistor Memory Cell)...................................................................................................... 4
1.4 Memory array: .................................................................................................................................... 6

2.

ROW DECODERS ............................................................................................................................... 7

2.1 Pre Decoded Style row decoder and Sizing of the transistors in the Row decoder ............................ 7
2.2 Transistor sizing .................................................................................................................................. 7

3.

COLUMN DECODERS ....................................................................................................................... 9

3.1 Sizing of the transistors in the column decoder .................................................................................. 9
3.2 Transistor sizing .................................................................................................................................. 9

4.

SENSE AMPLIFIERS ...................................................................................................................... 111

5.

WRITE DRIVERS ............................................................................................................................ 133

6.

AUXILIARY CIRCUITS ................................................................................................................. 155

6.1 Transmission gate ............................................................................................................................. 15
6.2 Pre-charger ...................................................................................................................................... 166
6.3 Clock Buffer.................................................................................................................................... 177
6.4 Wr signal buffer .............................................................................................................................. 178

7.

SRAM DESIGN.................................................................................................................................. 20
7.1Floorplan of SRAM design .................................................................................................................. 20
7.2 Schematic and Layout of SRAM ........................................................................................................ 21
7.3 DRC and LVS of SRAM ....................................................................................................................... 23

8.

TIMING ANALYSIS ......................................................................................................................... 24

8.1 HSPICE code .................................................................................................................................... 24
8.2 Evidence for SRAM operating correctly .......................................................................................... 26
8.3 Worst case Write time for 0 .............................................................................................................. 26
8.4 Worst case Write time for 1 .............................................................................................................. 27
8.5 Worst case Read time for 0 ............................................................................................................... 27

9.

Noise Margin measurements of 6T memory cell ................................................................................ 28

9.1 Read Noise Margin ........................................................................................................................... 28

9.2 Write Noise Margin .......................................................................................................................... 29

10.

RESULTS AND CONCLUSIONS ................................................................................................. 30

LIST OF FIGURES
Figure 1 Memory Cell Schematic ................................................................................................................. 4
Figure 2 8T Layout ....................................................................................................................................... 5
Figure 3 Memory Array Layout .................................................................................................................... 6
Figure 4 Schematic of Row Decoder(single row) .......................................................................................... 7
Figure 5 Layout and Schematic of Row Decoder ......................................................................................... 8
Figure 6 Layout of Column decoder ........................................................................................................... 10
Figure 7 Schematic of Column decoder ...................................................................................................... 10
Figure 8 Schematic of Sense Amplifier ...................................................................................................... 11
Figure 9 Layout of Sense Amplifier ........................................................................................................... 12
Figure 10 Schematic of Write Driver .......................................................................................................... 13
Figure 11 Layout of Write Driver ............................................................................................................... 14
Figure 12 Schematic of Transmission gate ................................................................................................. 15
Figure 13 Layout of Transmission gate ...................................................................................................... 15
Figure 14 Layout of Pre- charger circuit ..................................................................................................... 16
Figure 15 Schematic of Pre- Charger Circuit.............................................................................................. 16
Figure 16 Schematic of Clock buffer .......................................................................................................... 17
Figure 17 Layout of Clock buffer ............................................................................................................... 18
Figure 18 Layout and Schematic of Wr signal buffer..19
Figure 19 Floorplan of SRAM .................................................................................................................... 20
Figure 20 Schematic of Memory Cell Array .............................................................................................. 21
Figure 21 Layout of Memory Cell Array .................................................................................................... 22
Figure 22 DRC Report ................................................................................................................................ 23
Figure 23 LVS Report ................................................................................................................................. 23
Figure 24 SRAM read and write working in sequence ............................................................................... 26
Figure 25 Worst Case Read and Write time ............................................................................................... 27
Figure 26 Read Noise margin of 8T memory cell....................................................................................... 28
Figure 27 Write Noise margin of 8T memory cell...................................................................................... 29

1. INTRODUCTION
1.1 Introduction to SRAM
A 256 word SRAM has been designed using the IBM 130 nm technology with a word size of 8
bits. An output capacitance of 25 fF has been used for simulation. Cadence virtuoso is used for
layout editing, running DRC and LVS.
1.2 SRAM Architecture
An SRAM cell consists of the following blocks:
(a) 8T (eight transistor) Memory cell
(b) Row decoder
(c) Column decoder
(d) Sense amplifier
(e) Write driver
(f) Clock buffer
(g) Pre charge
1.3 8T (eight transistor Memory Cell)
8T cell is used for low voltage application.8T cell consists of a latch, two access transistors and
two transistors for read. Bit is written through WBL and WBLB by asserting WWL. Read is
done by asserting RWL and sensing the voltage change on RBL. WWL/ RWL are asserted by
row decoder depending on Wr signal.

Figure 1 Memory Cell Schematic

Figure 2 8T Layout

Height of the cell: 3.58 um

Width of the cell: 2.26 um
The area of a single 8T cell is found to be 8.0908 um^2 ( 3.58* 2.26).
Aspect ratio: 1.58

1.4 Memory array:

Memory Array is made from the Memory cells by placing it row wise and column wise. The
number of cells per row and column depends upon the memory architecture and memory size.

Figure 3 Memory Array Layout

Height = 100.24um
Width = 153.470um
Area = 100.24*153.47 = 15383.8328squm
Area per bit = 7.5squm

2. ROW DECODERS
The row decoder will activate the pass transistors in our memory cell. In this project, we used a
pre decoded row decoder.
2.1 Pre Decoded Style row decoder and Sizing of the transistors in the Row decoder
The inputs to the row decoder are addr0, addr1, addr2, addr3, addr4, Wr. The outputs of row
decoders are fed to pass transistors to activate the rows. The design has been implemented by
using 3 input nand gates, 2 input nand gates and inverters. We have used multifinger technique to
compress the height of the large inverter. Sizing calculation is shown below.
CPoly = (no. of columns) x (Cpoly/um) x (no. of access transistor) x (width of poly)
=64 x 2 x 2 x 0.28 = 71.68fF
Cwire = (no. of columns) x (width of 1 cell) x (Cwire/um) =64 x 2.26 x 0.2fF = 28.928
Cload = Cpoly + Cwire = 100.608fF= 50.304um
G for 3-input NAND gate, inverter and 2-input NAND gate = 100/27
B = 4 x 4 x 2=32
H =50.304um
From F = GBH = 5969.54
N= log(5969.54) = 6.7 =7(considered)
f = 3.46
2.2 Transistor sizing
Inverter 1(rightmost) = 14.54um
NAND2 = 5.6um
Inverter 2 = 3.24um
NAND3 = 1.56um
Inverter 3 = 1.8um
NAND3 = 0.87um
Inverter 4 = 1um

Figure 4 Schematic of Row Decoder(single row)

5 Layout and Schematic of Row Decoder

3. COLUMN DECODERS
In this chapter, the column decoder required in the SRAM design is explained in detail.
3.1 Sizing of the transistors in the column decoder
Calculations:
We are using 3:8 Column Decoder .Each decoder output goes to 8 columns to get 8 bits of the
word. Each column has WBL, WBLB and RBL. So 3 transmission gates are used for each of the
three bit lines.
In total each column decoder output connects to (3 x 8=24) nmos and pmos gate inputs of the
transmission gate.
Cpoly = 2 x 3 x 8 x 0.56 = 26.88 fF
Cwire = (width of the memory array) * 0.2fF = 29.056 fF
Cload = Cpoly + Cwire = 55.936 fF
H = 55.936fF/2fF = 27.968
F = GBH = 4/3 * 2 * 4 * 27.968 = 298.24
N = 4 Stages
f = 4.15
3.2 Transistor sizing
Transistor sizing at each stage is found by using the formula Cin= (gh)/f^
Inverter 1 (Right most) = 6.73 um
Inverter 2 = 3.24um
NAND3 = 1.04 um
Inverter 4= 4* 1.04/4.15= 1 um

The inputs to the column decoder are addr5, addr6, addr7. The outputs of the column decoders
will be given as inputs to the transmission gates.

Figure 6 Layout of Column decoder

Figure 7 Schematic of Column decoder

10

4. SENSE AMPLIFIERS
Current Mode Differential Amplifier on the bit lines is used to sense the voltage differences on
RBL. The values are passed through pass transistors and are sensed by the sense amplifier. We
used transistors of sizes 2.8 um for PMOS and 0.28 um for NMOS in the circuit. Vdd is
given as input to the bottom most NMOS of the circuit as a sense input. RBL and Reference
voltage are given as inputs to the other two NMOS
8 Sense Amplifiers are used in the design to read 8 of the read bit lines.
.

Figure 8 Schematic of Sense Amplifier

11

Figure 9 Layout of Sense Amplifier

12

5. WRITE DRIVERS
During clock precharging input data must be disabled. Before write operation, one of the
bit lines must be driven high and the other low based on the data bit that is being written.
When Wr signal goes high, write operation is done and the 10 bit data can be written by
giving required bit values to the corresponding input bits. These values are then passed
through a set of transmission gates that are attached to the WBL and WBLB lines so that
the data bit will be written into the corresponding memory cell. Both the read and write
operations are occurred only during evaluation.
8 Write drivers are used in the design for each of the data input.
Calculations:
Cload= 54.12fF
F= GBH= 54.12
N= 3 stages
f^ = 3.78
Inverter 3 (rightmost in top) = 7.16um
Inverter 2 = 3.78um
Inverter 1 = 1um

Figure 10 Schematic of Write Driver

13

Figure 11 Layout of Write Driver

14

6. AUXILIARY CIRCUITS
6.1 Transmission Gate
Each column has three transmission gate connected to each of WBL, WBLB and RBL. Transistors

sizes are 0.56 um each.

Figure 12 Schematic of Transmission Gate

Figure 13 Layout of Transmission Gate

15

6.2 Pre-charger

The pre charger is used for bit line conditioning, which means to pre charge the bit lines to VDD
before the next read or writes operation. The PMOS transistors size is taken as 2um for good
conditioning of bit line and bit line bars.

Figure 14 Layout of Pre- charger circuit

Figure 15 Schematic of Pre- Charger Circuit

16

6.3 Clock Buffer

A clock buffer is used to provide the clock input to the pre chargers. Input to the clock is defined
in the Hspice code. At the pre charge state all the bit lines will be precharged to Vdd.Also when
addr_en is zero ,all the bitlines are precharged. addr_en is given in the clock buffer circuit. A two
input nand gate is used to give clock signal and addr_en.
Calculations:
C poly = 2 * 2 * 3*64 = 768fF
C wire = 0.2 * 64 * memory cell width = 28.928fF
Cload = C poly + C wire = 796.928fF
F = GBH = 531.28
N = 4(considered)
f = 4.8
Transistor sizes :
Inverter 1 (Right most) = 83um:- wp = 55 um , wn= 28um
Inverter 2 = 17.29um :- wp= 11.53, wn= 5.8um
Inverter 3 = 3.6um :- wp= 2.4um wn = 1.2um
Nand2 4 = 1um :- wp = wn =0.5um

Figure 16 Schematic of Clock buffer

17

Figure 17 Layout of Clock buffer

6.4 Wr signal buffer

As Wr signal is used by 32 rows, buffer is needed which also has to be sized according to logical
effort. We have used multi finger technique for the layout of long inverter.
Calculations:
C poly = 32 x 2.8 x 2 = fF
C wire = 32 x 4.47 x 0.2 =
Cload = C poly + C wire = 207.81fF
F = GBH = 103.9
N = 4(considered)
f = 3.2
Transistor sizes :
Inverter 1 (Right most) = 32.46um
Inverter 2 = 10.14um
Inverter 3 = 3.17um
Inverter 4 = 1um
We have equalized delay of inverter2 by two inverter using f = sq. root of 3.2
Inverter 5 = 32.46um
Inverter 6 = 18um
Inverter 7 = 10.14um

18

Figure 18 Layout and schematic of Wr signal buffer

19

7. SRAM DESIGN
7.1

Floorplan of SRAM design

Figure 19 Floorplan of SRAM

20

7.2

Schematic and Layout of SRAM

Figure 20 Schematic of Memory Cell Array

21

Figure 21 Layout of Memory Cell Array

Total Area = (132.6um x 183.740 um) = 24363.924 sq um

Total area per bit = 11.89sq um
Aspect ratio = 0.72

22

7.3 DRC and LVS of SRAM

Figure 22 DRC Report

Figure 23 LVS Report

23

8. TIMING ANALYSIS
8.1 HSPICE code
$transistor model
.include "/home/cad/kits/IBM_CMRF8SFLM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
.include "integratearea.sp"
.option post runlvl=5
xi Wr addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr_en clk in_data0 in_data1 in_data2
in_data3 in_data4 in_data5 in_data6 in_data7 out_data0 out_data1 out_data2 out_data3
out_data4 out_data5 out_data6 out_data7 ref integratearea
vdd1 vdd vss 1.2V
vss vss 0 0
Cout_1 out_data0 0 25fF
Cout_2 out_data1 0 25fF
Cout_3 out_data2 0 25fF
Cout_4 out_data3 0 25fF
Cout_5 out_data4 0 25fF
Cout_6 out_data5 0 25fF
Cout_7 out_data6 0 25fF
Cout_8 out_data7 0 25fF
.VEC sram_worst_case.vec
Vin clk vss pulse (0V 1.2V 0ps 3ps 3ps 5000ps 10000ps)
V5 ref vss PWL 0ns 0.9v
.tr 0.1ns 200ns
.end
Test vector file 1( for sram functionality)
Radix 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Vname Wr addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr_en in_data0 in_data1
in_data2 in_data3 in_data4 in_data5 in_data6 in_data7
IO I I I I I I I I I I I I I I I I I I
Tunit ns
24

Period 10
Trise 0.03
Tfall 0.03
Vih 1.2
Vil 0
1
1
0
0
0
0
1
0
1
0
1
0

01011111
00110101
01011111
00110101
00110101
00000000
11111111
11111111
00000000
00000000
00000000
00000000

1
1
1
1
1
1
0
0
1
1
1
1

10000000
11000000
11100000
00000000
00100000
00000000
11000000
11000000
00000000
11111111
11111111
11111111

Test vector file 2(for worst case analysis)

Radix 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Vname Wr addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr_en in_data0 in_data1
in_data2 in_data3 in_data4 in_data5 in_data6 in_data7
IO I I I I I I I I I I I I I I I I I I
Tunit ns
Period 10
Trise 0.03
Tfall 0.03
Vih 1.2
Vil 0
1
0
1
0
1
0

00000111
00000111
00000111
00000111
00000111
00000111

1
1
1
1
1
1

00000000
00000000
11111111
00000000
00000000
00000000

25

8.2 Evidence for SRAM operating correctly

This waveform shows that data is written and read at 2ns clk

Figure 24 SRAM read and write working in sequence

The worst case timing analysis is done by writing and reading in the cell which is in first row and
last in the column. Thus the address should be 11100000 where first 3 bits give column address
and last 5 bits give row address.
8.3 Worst case Write time for 0
The worst case write time for 0 is found by first writing 1 and then writing 0 to the target cell.
The difference between 50% of Wr signal and 50% of net17 (From figure 1 we can see that net
17 is the output of the first inverter of 8T memory cell).
The worst case write time for 0 was found at 298ps with correct functionality.

26

8.4 Worst case Write time for 1

The worst case write time for 1 is found by first writing 0 and then writing 1 to the target cell.
The difference between 50% of Wr signal and 50% of net17 (From figure 1 we can see that net
17 is the output of the first inverter of 8T memory cell).
The worst case write time for 1 was found at 329 ps with correct functionality
Here we can see that writing 1 is worst case because for writing 1 we will have to write 0 to WBLB

8.5 Worst case Read time for 0

The worst case read time is found by writing 0 and then reading 0 from the target cell. The
difference between 50% of Wr signal and 50% of out_data7
The worst case read time for 0 was found at 924 ps.
Note: Read time for 1 will be 0ps as RBLis precharged to 1

Worst case Write time for 0

Worst case Read time for 0

Worst case Write time for 1

Figure 25 Worst case read and write time

27

9. Noise Margin measurements of 8T memory cell

9.1 Read Noise margin:

During read, WWL and WBL are held at VDD . Feedback from the cross-coupled inverters is broken.
Voltage transfer characteristic (VTC) of the inverter in the half circuit is plotted(vout vs Vin).Butterfly
curve is obtained by overlapping the VTC with its inverse.

Figure 26 Read Noise Margin of 8T memory cell

Read Noise margin is found to be around 0.2V as observed from simulation.

28

9.2 Write Noise margin:

During a write, WWL is at VDD, and the data is driven onto the WBL and WBLB. Feedback from the
cross-coupled inverters is broken. Voltage transfer characteristics (VTCs) of the inverter in the half
circuit is plotted as shown below (V2 vs V1 and V1 vs V2) .Here, VTCs of the two halves are not the same
Since one of the WBL is driven to VDD and other to 0 (asymmetry). Write NM is the side of the largest
square fitted in between the two curves

Figure 27 Write Noise Margin of 8T memory cell

Write margin is found to be 0.6 V as observed from the simulation

29

10.
Area of Memory cell
Aspect Ratio of Memory cell
Memory array area
Memory area per bit
Total Memory area
Total Memory area per bit
Aspect Ratio of total memory
Worst case Write time
Worst case Read time
Operating Frequency
Read Noise Margin
Write Noise Margin

RESULTS AND CONCLUSIONS

8.0908 sq. um
1.58
15383.8328 sq. um
7.5squm
24363.924 sq. um
11.89sq um
0.72
329 ps
924 ps
500MHz
0.2V
0.6V

30