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3-1-1992

Three-Dimensional Insulated Gate Bipolar

Transistor (IGBT) Development
P.V. Gilbert
Purdue University School of Electrical Engineering

G.W. Neudeck
Purdue University School of Electrical Engineering

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Gilbert, P.V. and Neudeck, G.W., "Three-Dimensional Insulated Gate Bipolar Transistor (IGBT) Development" (1992). ECE Technical
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Three-Dimensional Insulated Gate

Bipolar Transistor (IGBT) Development

P.V. Gilbert and G.W. Neudeck

School of Electrical Engineering

Purdue University

W. Lafayette, IN 47907

TR-EE 92-10
March 1992

This research was supported by

Semiconductor Research Corporation Contract W2-SJ-108

TABLE OF CONTENTS
Page

............................................................................. v i
..
LIST OF FIGURES ........................................................................... vi i
...
ABSTRACI' ................................................................................... x l l l
LIST OF TABLES

...

R1
1.1
1.2
1.3
1.4
1.5
1.6
1.7

INTRODUCTION ................................................i ..........1

Background ............................................................................1
Smart Power Technology............................................................ 2
Smart Discretes........................................................................ 4
High Voltage Integrated Circuits.................................................... 4
High Power Integrated Circuits.....................................................5
Scope ................................................................................... 5
References ............................................................................. 6

CHAPTER 2

SEMICONDUCI'OR POWER DEVICES ................................ 7

2.1 Introduction ............................................................................7

2.2 Controllable Switches ................................................................7
2.3 High Power Bipolar Transistor ......................................................8
2.3.1 HPBT Design ............................................................... 10
2.3.2 HPBT Performance....................................................... 13
2.4 Power MOSFET ..................................................................... 14
2.4.1 Power MOSFET Structure .............................................14
2.4.2 Power MOSFET Operation ........................................... 1 8
2.5 Insulated Gate Bipolar Transistor.................................................. 21
2.5.1 Basic Structure of IGBT ................................................... 22
2.5.2 IGBT Operation .............................................................25
2.5.3 Mathematical Analysis .....................................................31
2.5.4 Latch-up in IGBTs......................................................38
.
............................ 41
2.5.5 IGBT Switching Characteristics..........
2.6 References ............................................................................ 45
CHAPTER 3
3.1
3.2
3.3
3.4

PROPOSED 3D-IGBT DEVICE......................................... 49

Introduction .......................................................................... 49
3D-IGBT Structure .................................................................. 49
3D-IGBT Fabrication Sequence................................................... 51
Quasi-Dielectric Isolation .......................................................... 5 6

Page
3.4.1 Fabrication of QDI-BJT................................................... 58
3.4.2 Results of QDI-BJT Fabrication ......................................... 61
3.4.3 Summary of QDI-BJT Study.............................................. 64
3.5 Chapter Summary ................................................................... 68
3.6 References............................................................................ 69
CHAFER 4
4.1
4.2
4.3
4.4
4.5

3D-IGBT SIMULATION STUDIES .................................... 70

Introduction......................................................................... 7 0
Forward Blocking Operation ....................................................... 70
Forward Active Operation........................................................... 76
Summary.............................................................................
84
References ............................................................................ 86

CHAPTER 5

.
PROCESS DEVELOPMENT.............................................
87

Introduction ........................................................................ 87
Cellular Layout...................................................................... -87
3D-IGBT Cellular Design ........................................................ 94
Self-Aligned Seed Window ....................................................... 98
Post Trench R E Sidewall Cleaning............................................. 113
5.5.1 Results ...................................................................... 117
Sidewall MOSFET ................................................................125
5.6.1 Device Characteristics and Discussion .................................. 127
References .......................................................................... 130
CHAPTER 6

ELECTRICAL EVALUATION......................................... 131

6.1 Introduction .........................................................................131

6.2 Device Fabrication
. . .................................................................. 131
6.3 Electrical Verification .......................................................... 132
6.3.1 Latch-up ....................................................................148
6.4 Trench Clean-up Results .......................................................... 154
6.5 Device Scaling...................................................................... 154
6.6 Summary ............................................................................ 164
6.7 References.......................................................................... 165
CHAPTER 7

SUMMARY AND PROPOSED FUTURE RESEARCH........... 166

7.1 Summary ............................................................................ 166

7.2 Future Work .................................................................... 167
APPENDIX............................... o. ................................................... 168

LIST OF TABLES
Table

Page

2.1 Relative Properties of Controllable Switches .......................................... 22

3.1 Substrate vs. QDI-BJT Electrical Data................................................ 62
.
4.1 Forward Device Characteristics........................................................
79

5.1 Breakdown Field and Leakage Currents ............................................ 122

5.2 UMOSFET Characteristics ......................................................... 127
6.1 Averaged DC Parameters for 3D-IGBT device .....................................158

vii

LIST OF FIGURES
Figure

Page

1.1 Smart power technology architecture .....................................................3

2.1 High power bipolar transistor (HPBT) structure[2]................................... 9
2.2 HPBT doping profiles: (a) Single diffused power transistor; (b) n+-p-v-n+
power transistor; (c) n+-p-x-v-n+ transistor.[6] .....................................
11

2.3 Power device blocking voltage design criteria: (a) variation of breakdown
voltage and depletion layer width at breakdown with backround doping level of
abrupt junction diodes; (b) blocking voltage capability of an open base transistor
as a function of the base doping level and base width.[7] ...........................12
2.4 Cross-sections of three high-voltage DMOS devices: (a) LDMOS,
(b) VDMOS, and (c) VMOS ............................................................. 15
2.5 RESURF Principle: (a) Surface limited breakdown, (b) buk breakdown.........17
2.6 Response to overload in a switching power supply: (a) High
power bipolar transistor, (b) power MOSFET.[15]...................................20
2.7 Parallel connection of MOSFETs....................................................... -21
2.8 Vertical cross section of Insulated Gate Bipolar Transistor (IGBT).................23
2.9

Vertical cross section of Lateral Insulated Gate Bipolar Transistor(L1GBT).......24

2.10 Output characteristics of IGBT........................................................... 27

2.1 1 Doping profile and electric field distribution for buffer-layered
and non-buffer-layered IGBTs.[36].....................................................27
2.12 (a)EQuivalentcircuit for the IGBT; (b) Effective MOSFET
and BJT operating portions of IGBT.[30].............................................. 29
2.13 Schematic diagram of the flow of caniers in IGBT....................................30
2.14 Coardinate system used in carrier concentration and current
density analysis ..........................................................................

..36

2.15 Band diagram from the emitter to base contact of IGBT.[42]........................ 36

viii
Figure

Page

2.16 On-state current flow paths of buffered IGBT.........................................39

2.17

(a) Distribution of the electron concentration in the IGBT structure

at a forward drop of 1.25 V (non-latch-up); (b) Distribution of the
elecmn concentration in the IGBT structure at a forward drop of
1.5 V (latch-up).[3 I.] ......................................................................40

2.18 Cross-section of n-channel IGBT with a trench gate stnrcture.[48] .................42

2.19 Turn-off voltage and current waveforms of an IGBT.[30]...........................42
2.20 (a) Schematic drawing of modified vertical IGBT with
external circuitry for removal of excess charge, (b) msssectional view of vertical CIGBT.......................................................44
-

3.1 Cross-sectional view of proposed 3 dimensional insulated

gate bipolar transistor 3D-IGBT ....................................................... 50
3.2 Cross-sectional view of vertical insulated gate bipolar transistor....................50
3.3 Proposed 3D-IGBT process sequence: (a) implant P-base, P+ latch-up protection
and N+ source regions, (b) RIE trench, and form gate oxide, (c) deposit polysilicon
and define photoresist for masking polysilicon, (d) etch polysilicon and gate oxide,
(e) oxidize to form seed window oxide and define photoresist for masking oxide,
(f)etch oxide to form seed window, (g) grow low and moderately doped SEG,
(h) planarize SEG then implant with boron to form anode, (i) etch contacts and
deposit metal to form final structure ..................................................... 52
3.4 (a) Integration of high and low power devices for smart power applications using
QDI .process,
. (b) 3D-IGBT fabricated in QDI tub for use in smart power
applications ................................................................................ -57
3.5 QDI-BJT process flow:(a) Oxidize p-type (100) wafer, (b) define and etch
trench,(c) define seed hole, grow ELO, and implant,(d) grow second ELO,(e)
planarize E L 0 and fabricate BJT's....................................................... 59
3.6 (a)Spreading resistance profile(SRP)data of in-situ doped buried collector,
and (b) ion implanted buried collector ................................................... 63
3.7 Scanning electron micrograph of a cross section of the QDI-BJT before
planarization. ............................................................................... -65
3.8 Output characteristics of QDI-BJT........................................................ 65
3.9 Beta vs I, plot of the QDI-BJT............................................................ 66
3.10 Scanning electron micrograph of QDI-BJT (a) without CMP and (b) with
CMP ......................................................................................... 67

Figure

Page

4.1 Cross-sectional device structure of the (a) 3D-IGBT and (b) the lateral IGBT
(LIGBT) showing critical dimensions used in PISCES simulations. All
dimensions are in microns ............................................................71
4.2 3D-IGBT doping profile used in PISCES simulations................................72
4.3 Forward blocking junction depletion region as anode voltage is
increased ..................................................................................... 74
4.4 Contour plot of equiptential surfaces from 1 volt to 90
volts.......................................................................................... 75
4.5 Hole and electron concentrations in P-base region at (a) 0 volts and (b) 6
volts .......................................................................................... 77
.

...

4.6 Hole and electron concentration in channel region with 3D-IGBT in forward active mode .........................................................................78
4.7 Output characteristics of 3D-IGBT........................................................ 78
4.8 Current vector plots for (a) electron current and (b) hole current ......................80
4.9 Potential energy plot of area under N+.source region for 3D-IGBT (a) protected
from latch-up and (b) not protected from latch-up.......................................81
4.10 Plot of electron current vectors showing injection of electrons into P-base
region after onset of latch-up ............................................................... 82
4.1 1 Hole and electron concentrations in P-Base region (a) at a forwd drop of 8.0
volts (non latch-up) and (b) at a forward drop of 1.8 volts (latch-up)................83
5.1 Self-aligned DMOS structure utilizing buried plysilicon gate.[2] .................... 88
5.2 HEXFET cellular layout configuration for high current applications..[2].............90
5.3 Interdigitated layout of insulated gate bipolar transistor.[2]............................91
5.4 Cellular configuration and critical dimensions of HEXFET.[2]....................... 93
5.5 Isometric view of 3D-IGBT in its high current cellular configuration................. 95
5.6 (a)Mask layout for high-current 3D-IGBT;(b) Close-up view of single:cell device.96
5.7 Mask layout for fabrication of 3D-IGBT................................................. 97
5.8 Close-up view of mask layout for 3D-IGBT device cell................................ 99
5 -9 (a)Originally proposed 3D-IGBT device with overlap region.
(b)Self-Aligned 3D-IGBT with overlap region eliminated............................ 100

Figure

Page

5.10 (a)Effect of seed window dimensions on SEG faceting.(b) Effectiveness

of CMP to eliminate adverse facet formation due to narrow seed window..........101
5.11 3D-IGBT self-aligned process sequence................................................103

.
.....106
5.12 SEM of trench sidewall following RIE of polysilicon layer................
5.13 SEM of trench sidewall and bottom single crystal silicon just prior
to selective epitaxial silicon growth ................................................. 1 0 6
5.14 SEM cross-section of self-aligned poly gate and seed window......................108

5.15 SEM of sidewall poly gate...............................................................1 0 8

- ............109
5.16 SEM showing selective silicon completely filling 4 micron deep trench

5.17 SEM showing SEG coming out of trench and shorting to n+. source..............109
5.18 Anode to n+-source short caused by oxide thinning.................................
5.19 (a)Poor photoresist step profile. (IOO;(b)ideal photoresist step profile. 90

110

........110

5.20 SEM of trench sidewall following R E etch:negative resist........................... 112

5.21 SEM of trench sidewall following RIE: positive resist................................ 112
5.22 SEM of trench following(a)combinationFR115. FR116 etch
and (b) wet etchFreon 115 etch .......................................................... 114
5.23 (a)Trench MOS capacitor with gate formed by R E sidewall spacer
technique;(b)Die border used for trench capacitor with small top surface
contact .......................................................................................116
5.24 TCA vs.Non.TCA Oxide (Planar CAPS)..................
.
.
..................... 118
5.25 Baseline vs. sacrificial oxide ............................................................ -119
5.26 Baseline vs. TCA Oxide.................................................................. 120
5.27 Baseline vs. TCA & Sacrificial Oxide ................................................. 121
5.28 Breakdown field for control capacitor..................................................123
5.29 Breakdown fieId for sacrificial oxide capacitor........................................ 123
5.30 Breakdown field for TCA capacitor..................................................... 124
5.3 1 Breakdown field for TCA/Sacrificial Oxide capacitor................................. 124
5.32 UMOSFET used to investigate quality of RIE sidewall............................... 126

Figure

Page

5.33 Top view of 3D-IGBT cell following RIE of polysilicon............................. 126

5.34 SEM of conformal polysilcon coverage following RIE...............................128
5.35 Output characteristics of UMOSFET.................................................... 128
6.1 SEG growth in 4 micron deep trench .................................................... 133
3D-IGBT following SEG grwoth and anode implant.................................. 133
SEM of polysilicon along trench sidewall and top surface............................ 134
SEM of completed 3D-IGBT device..................................................... 134

SEM of 3D-IGBT device following CMP planarization.................,.............135

Output characteristics of working 3D-IGBT............................................ 137
Output characteristics of (a) Sidewall MOSFET and (b) 3D-IGBT..................138
3D-IGBT device at a forward blocking voltage of 90 volts............................140
Onset of forward breakdown of UMOSFET at 90 volts..............................140
6.10 Depletion region during foward blocking mode in (a)3D-IGBT
and (b) UMOSFET........................................................................ 141
6.11 On-resistance measurement of 3D-IGBT device....................................... 142
6.12 Threshold voltage measurement of 3D.IGBT.VT=6.69 volts .........................143
6.13 Anode to cathode leakage current at Vg=O volts.......................................144
6.14 Gate to cathode leakage current at Vd=O volts ........................................145
6.15 PISCES simulation results of 3D-IGBT channel length dependence...............146
6.16 SUPREM 111simulation results of doping concentration profile
along sidewall channel....................................................................147
6.17 Equivalent circuit of 3D-IGBT device .................................................. 149
6.18 Cross-section of 3D-IGBT device showing latch-up implant offset. ...............149
6.19 Photograph of 3D-IGBT device with latch-up implant in place......................151
6.20 3D-IGBT device at the onset of latch-up.............................................. 151
6.21 Output characteristics of 3D-IGBT device with latch-up implant....................152

xii
Figure

Page

6.22 Comparison of latch-up current between device with latch-up

implant and one without......................................................,...........-153
6.23 PISCES simulation of output characteristicsof 3D-IGBT indicating
the onset of latch-up .................................................................... 155
6.24 Output characteristic of 3D-IGBT indicating latch-up at 27.89 mA .................156
6.25 Latch-up current vs. Implant offset ..............................................157
6.26

SEM of 10 micron wide trench following epi growth out of 5 micron

deep

trench................................................................................. 16 1

6.27 ~ o m ~ a r i s of
o nsimulated and r n e a s d output data
for 3D-IGBT..............................................................................
-163
-.

...

Xlll

ABSTRACT

A new insulated gate bipolar transistor structure, the 3D-IGBT, is presented. The
3D-IGBT utilizes selective epitaxial silicon to form a top contacted anode and still retain the
cellular structure of vemcally oriented devices. The 3D-IGBT , unlike other fully
integrable power devices, exploits the merits of cellular structure to increase its packing
density and thus reduce its on-resistance per unit area. It also eliminates the parasitic JFET
resistance found in vertical IGBT's. To integrate the 3D-IGBT with low power devices,
the QDI method of device isolation is also presented. QDI uses a combination of JI and DI
to electrically isolate low and high power devices. It has been shown that the selective
epitaxial silicon grown in deep trenches is of device quality and that the use of a trench
structure to facilitate isolation and control of SEG thickness should be ideal in applications
where the thickness and resistivity of the control and power areas are independently
optimized.
Electrical feasibility of the 3D-IGBT is demonstrated. Averaged results from
several 3D-IGBT devices indicate that the RIE sidewall treatment techniques have a
negligible effect on the DC characteristics of the device. When scaled, the on-resistance of
the 3D-IGBT was shown to be significantly less than the lateral IGBT; mainly due to the
increased packing density of the 3D-IGBT. Latch-up current for the fabricated devices was
as high as 1,361 Ncm2 and according to PISCES data, can be improved even further by
reducing the latch-up implant offset distance. Finally, structural feasibility of a minimum
3D-IGBT device was demonstrated by the successful growth of more than 5 microns of
selective silicon out of a 10 micron wide, 5 micron deep trench.
The 3D-IGBT device represents the frrst integrable power device with a cellular
layout structure and thus provides the desired ability to lower on-resistance by increasing
the device's channel density, a capability previously afforded only to discrete, vertical
power devices.

CHAPTER 1
INTRODUCTION

1.1 Background
Protection functions for power devices, such as over-current or over-temperature
protection, are important because power devices are subject to destructive modes which
may cause self-damage, damage to other devices, or overall system failure. Until recently,
power electronics relied upon the implementation of these circuit protection functions by
using discrete devices. The dependency of the power electronic industry on discrete part
implementation of complex control and detection circuits caused it to lag behind integrated
circuits in terms of device development and performance because discrete component
implementation increased the overall cost of the system, added inductive noise, took up
space and dissipated power.[l] Due to a commitment in the early years of the
semiconductor device industry to concentrate on the development and manufacture of
digital integrated circuits, the process technology for the power bipolar junction transistor,
the workhorse of the power electronics industry for nearly three decades, lagged behind
that developed for integrated circuits. Furthermore, although microprocessors allowed for
easy integration of control circuits with power devices on the same chip, the relatively high
input currents required by bipolar transistors required large, complex drive circuits that
were incompatible with large scale integration.
With the introduction of the power MOSFET in the 1970's and the development of
MOS/Bipolar devices such as the insulated gate bipolar transistor (IGBT) during the
1980's, the power electronics industry can now benefit from the device processing
advances of integrated circuits. The MOSFET and MOS/Bipolar power devices are highly
integrable because their low input-gate currents allow for much smaller gate drive
circuit.[2] By integrating discrete power devices with the functions of several integrated
circuits on to one chip, power system design can be tremendously simplified and system
reliability is enhanced. Combining low power control circuits on the same chip with high
power devices has created a new technology called "smart power". Smart power allows

power system designers to obtain a large reduction in component count resulting in lower
system cost, area and weight.
1.2 Smart Power Technology
Smart power technology merges small signal logic circuits on the same chip with
power devices. The three major functions performed by smart power technology are:
power control, sensing/protection,and interface.[3] An example of a chip utilizing smart
power would be one which provides level shifting and drive circuits that enable a
microprocessor to control a power load. Display drives, with capacitive loads requiring
much higher voltages than the microprocessor and other circuits, are but one example of
where such a chip would be useful. Figure 1.1 illustrates the overall architecture of the
smart power technology and the components required to implement its three major
functions.
The power control function utilizes external sensors to detect an:y deviation of key
signals and then adjusts the power device to compensate for the deviation. For example,
voltage regulation would require the detection of a deviation in the output voltage of the
device to result in an adjustment to the input current of the device. Power control utilizes
various power devices and their drive circuits. The relatively new h40S-gated power
devices such as the IGBT and the power MOSFET are most favored due to their low inputgate currents and simplified drive circuits. Power control requires the design of drive
circuits which can handle high voltages, up to 30 volts to drive the gate inputs of some
devices, high currents, or a combination of both.

Power devices are subject to destructive modes which are harmful to the power
&vice itself, or to the surrounding circuits. The sensing and protection fhnctions provided
by smart power technology eliminates the possibility of total system failure or power device
damage. The sensing and protection functions utilize local feedback in conjunction with
external sensors to protect the power device. Some examples are over-voltage, overcurrent, or over-temperature detection. High speed bipolar transistors and high
performance analog circuits are used to implement sensing functions bxause very quick
response times are required due to the rapid rise of destructive current levels in a fault
situation.
The interface function allows the microprocessor or other complex digital circuits to
communicate with power devices. Not only should the power device receive control
signals from the microprocessor via the interface circuits, the power device should also
send status information such as excessive voltage or current levels to the microprocessor.

BIPOLAR POWER TRANSISTORS

DEVICES

MOS CONTROLLED THYRlSTORS

30 VOLT CMOS

HIGH VOLTAGE LEVEL SHUT

CIRCUITS

HIGH SPEED BIPOLAR TRANSISTORS

- ANALOG

CIRCrnS

n
0

OPERATIONAL AMPLIFIERS

OVER-VOLTAGE NNDER -VOLTAGE

DETErnON
CIRCUITS

INTERFACE

IAGIC
CIRCUITS

OVER-TEMPERATURE

HIGH D W S rIY CMOS

Figure 1.1 Smart power technology architecture.

This requirement suggests the need for the interface function to perform encode/decode
functions to communicate with the low power digital circuits.
Currently smart power technology can be divided into two major areas: smart
discrete devices and high voltage integrated circuits (HVICts).[4] Smart discrete devices
are finding many uses in the automotive electronics industry, while HVIC's are being
developed for telecommunications applications, display drives, and motor control just to
name a few.
1.3 Smart Discretes
Smart discrete devices are discrete power devices with control and sense circuits
integrated on the same chip. Customer demands for high reliability power devices have
created this market. Sensing, control and protection circuits found on the same chip with
power devices have resulted in more robust, rugged system designs. Smart discrete
devices have taken advantage of the fact that through the use of various isolation
techniques, bipolar transistors, resistors and small signal MOSFETs carr be fabricated on
the same chip with the power &vice. Current flow is vertical in a smart power device and
flows to a common, high current contact on the backside of the wafer. It is this single
backside contact which limits the versatility of smart discrete &vices. For example, many
high performance amplifiers, such as those found in the high-end audio amplifier market,
can't be implemented using smart power discrete devices due to the: single collector
structure of smart discrete power devices.[5] The difficulty arises because only one power
transistor can be fabricated on a chip with control circuits, but to design amplifiers using
the advantages of smart power, the capability of fabricating more than one power transistor
on a chip with control circuits is required.
1.4 High Voltage Integrated Circuits
High voltage integrated circuits (HVIC's) utilize various isolation techniques to
combine high voltage &vices with low voltage control circuits. These isolation schemes
can be divided in to three major areas: self-isolation, junction isolation, and dielectric
isolation.[6] Unlike smart discrete devices, HVIC's are totally integrable with all their
contacts on the top surface of the chip. Vertical devices, those power devices with vertical
current flow, are used sparingly in HVIC's due to the design trade-off between high
voltage capability of the power &vice and current gain of the low-volltage device. By
exploiting the RESURF (reduced surface fields) principle, lateral high vo'ltage devices have
been developed for use in HVIC's. The lateral devices are fabricated in very thin epitaxial

layers and don't compromise the performance of low-voltage control devices. A key
advantage of lateral high voltage devices is that the breakdown voltage can be optimized by
increasing or decreasing the length of the drift region, the distance between the gate-source
and drain regions of the power device. The ability to control the breakdown voltage
photo-lithographically allows for the fabrication of optimized high-voltage devices of
different ratings on the same chip.
1.5 High Power Integrated Circuits
One major disadvantage of the lateral high-voltage device used extensively in
HVIC's is that as the device is optimized for high voltage operation, the amount of current
it can carry decreases due to an increase in the specific "on" resistance.[7] Also, highcurrent, high-voltage discrete devices are commonplace but they are not fully integrable.
Therefore, a fully integrable, 3 dimensional insulated gate bipolar transistor (3D-IGBT)
which utilizes vertical current flow for high current capability and is optimized for highvoltage operation is proposed. This new device utilizes a combination of junction isolation
and a dielectric isolation technique called quasi-dielectric isolation (QDI) to exploit an
emerging third major area of smart power technology called high power integrated circuits
(HPIC's). The limitations experienced by smart discrete devices due to their single
collector structure are eliminated and therefore more flexibility is provided to the smart
power system designer and new markets are opened for smart power technology.
1.6 Scope
A fully integrable, high power insulated gate bipolar transistor is presented in this
document. Chapter 2 will review the literature to provide a thorough background on power
devices with emphasis on IGBT's. A full description of the quasi-dielectric isolation (QDI)
process and a comparison study of the 3D-IGBT with other pertinent power devices will be
presented in chapter 3. Chapter 4 will detail the development and performance of the QDI
technology and will also describe the electrical performance of the 3D-IGBT with the aid of
computer simulation results. Chapter 5 will discuss several process development issues
and how they were addressed. Chapter 6 presents electrical data which verifies the
successful operation of the 3D-IGBT device. Finally, chapter 7 lists concluding remarks
and recommendations for future work.

References
P. Hower, "Power Semiconductor Devices: An overview", Proc. EEE, vol. 76,
pp. 335-342, April 1988.
B. Baliga, "Power Lntegrated Circuits - A Brief Overview", IEEE Trans. Electron
Devices, vol. ED-33, pp. 1936-1938, Dec. 1986.
B. Baliga, "Smart Power Technology: An Elephantine Opportuni.tywI
in EDM
Tech. Dig., abstract 1.1, pp. 3-6, 1990.
S. Robb, J. Sutor, and L.Terry, "Industry Trends in Power Integrated Circuits",
in EDM Tech. Dig., pp. 792-795, 1988.
R.Wrathd1, D. Tam, L. Terry, and S. Robb, "Integrated Circuits for the Control
of High Power", in IEDM Tech. Dig., abstract 16.1, pp. 408-41.1, 1983.
V. Rumennik, "Power Devices are in the Chips", IEEE Spectrum, vol. ,pp. 42-48,
July 1985.

D. Chen, "Power Semiconductors: Fast ,tough, and compact.", IEEE Spectrum,

vo1.24, pp.30-35, Sept. 1987.

CHAPTER 2
SEMICONDUCTOR POWER DEVICES

2.1 Introduction
Since the invention of the bipolar junction transistor in 1948, there has been a
sustained effort to increase the power handling capability of semiconductor power devices.
Now, due to increased power capabilities, ease of control, and reduced cost, a number of
new electronic applications have been developed using today's high performance power
devices.
Based on the degree of controllability, semiconductor power devices can be
grouped into three major categories: diodes, thyristors and controllable switches. The on
and off states of power diodes are controlled by a power circuit, whereas thyristors are
latched on by a control signal but must rely on a power circuit for turn-off. Finally,
controllable switches are turned on and off by control signals only. All but a few of the
major advances in semiconductor power devices in recent years have come from devices
which fall in the controllable switch category. Therefore, this chapter will review the
development and present status of three controllable switches: the high power bipolar
transistor (HPBT), the power MOSFET, and the insulated gate bipolar transistor (IGBT).
2.2 Controllable Switches
Devices capable of being turned on and off by control signals applied to their
control terminal are termed controllable switches. The device off-state is characterized by
the absence of current flow. Ideal controllable switches have the following characteristics:
(1) Block arbitrarily large forward and reverse voltages with zero
current flow when in the off state.
(2) Conduct arbitrarily large currents with zero voltage drop when
in the on state.
(3) Switch from on to off state or vice versa instantaneously when
triggered.
(4) Require vanishingly small power from control source to trigger switch.

Actual power devices are not ideal as evidenced by their finite switching times and power
dissipation. However, based on the desired characteristics of an ideal switch, actual power
devices should possess the following atnibutes[l]:
(1) Small Leakage cment in the off state.
(2) Small on-state voltage to minimize on-state power losses.
(3) Short turn-on and turn-off times.
(4) Small control power for device operation.
The HPBT, the power MOSFET, and the IGBT are all "normally off' devices and
are used exclusively as controllable switches. The negative gate-drive signal required at
power up for "normally on" devices prohibit their use as controllable switches. The
development and present state-of-the-art of normally off power devices will now be
reviewed with special emphasis given to IGBT's.
2.3 High Power Bipolar Transistor
The high power bipolar transistor (HPBT) is a current controlled device in which
the base current (Ib) controls the output current (E).Figure 2.1 shows the basic spucture
of the HPBT. Fletcher[3] showed that at high forward base drive currents, a significant
voltage gradient occurs in the p-base region under the n+-emitter. Thiis voltage gradient
debiases the middle portion of the emitter region, and therefore causes the electron injection
to be confined to the edges of the emitter closest to the p+-base contacts. By showing a
marked fall-off of injected current density as a function of distance from the edge of the
emitter region, Hauser et. a1.[4] clearly demonstrated that large emitter currents were not
attainable by simply increasing the area of the emitter region. It was shown that because
the central portion of the emitter region was inactive, and the resistance between emitter and
base regions should be as uniform as possible, an interdigitated design of narrow emitter
fingers with p+-base contacts was necessary to attain high emitter currents. Very narrow
emitter regions are also advantageous for high-speed turn-off of the HPBT. As the
transistor is switched off, the negative base current supplied for turn-off only affects the
outer perimeter of the emitter region[5] and therefore potentially destructive current levels
could develop in the center portion of the emitter region if this re:gion is too wide.
Consequently, an interdigitated design of the emitter-base region ;also improves the
reliability of the HPBT.

Base

Emitter

Base

w~
P - Base

N -- Drift

+-

Substrate

Collector

Figure 2.1 High power bipolar transistor(HPBT)structure.[2]

2.3.1 HPBT Design

When designing HPBTs, major consideration must be given to their ability to
suppon high reverse bias voltages across the collector-base junction. Power transistors
should also be designed to dissipate large amounts of power without any degradation of
performance. Therefore, because they are required to carry large collector currents and
support high collector-base reverse bias voltages, the structure of the HPBT differs
significantly from the simple, low power n-p-n or p-n-p transistor.
A typical n-p-n HPBT doping profile is shown in Figure 2.2a The profile consists
of &-emitter and n+-collector regions diffused simultaneously into a slab of uniformly
doped p-type silicon. Because the emitter and collector are formed via the same diffusion
step, this transistor is also referred to as a "single diffused transistor". A major
disadvantage of this device structure is its low current gain due to the large base width.
The base width must be very large to avoid punch-through and also to suppon large
collector-base reverse bias voltages when the device is in its forward blocking mode.
Furthermore, the single diffusion step results in a deep emitter-base junction that reduces
the emitter injection efficiency and thereby causes additional degradati.onof the current
gain.
An important improvement in the breakdown voltage of the device in Figure 2.2a
can be obtained with the n+-p-v-n+ doping profile shown in Figure 2.2b Fabrication of a
transistor with this profile begins with a highly doped (n+) substrate and then epitaxially
growing a low-doped n-type (v) collector region from this substrate. The p-base region is
diffused into the n'-collector region followed by the diffusion of the n+-emitter region.
The drift region is designed to suppon high voltages when the col1ecto:r-basejunction is
reverse biased. Large breakdown voltages are possible because the imovement of the
collector-base junction depletion region will be mainly into the n--collector region and only
slightly into the more heavily doped p-base region. The collector region resistivity and
thickness determine the maximum reverse bias voltage the collector-base junction can
suppon. Large reverse bias voltages are obtained by increasing the collector region
resistivity and thickness in accordance to the plots in Figure 2.3.
Failure by punch-through is effectively eliminated with the n'-p-v-n+ design.
Under typical bias conditions, the &vice operates like the aforementioned single diffused
transistor because the n- region is fully depleted. The n+-p-v-n+ structure is superior to
the n+-p-n+ structure because its narrow base width (5-10 pm) resu:lts in a far better
frequency response. As a result of its superior performance, the lour doped collector
region (v) found in the n+-p-V-n+structure is also incorporated in other ,devicetypes such

IMPURITY CONCENTRATION ( ~ r n - ~ )
O

IMP U R I T Y C O N C E N T R ATI O N (cm-'1

IMPURITY CONCENTRATION (cm-3)

10'1
lo1)

,,,I
I
1
1
loi4
10's
BACKGROUND W I N S CONCENTRATION (cm-5)

loo
lo1(

1 1 1 1 1 1

(A)

I'
I

1 1 1 1 1

101'
N-BASE DOPING CONCENTRATION

1 1 1 1

10~5

(ern.')

(B)
Figure 2.3

Power device blocking voltage design criteria: (A) Variation of

breakdown voltage and depletion layer width at breakdown with
background doping level of abrupt junction diodes; (B) Blocking voltage
capability of an open base transistor as a function of the base doping level
and base width.[7]

as MOSFETs and IGBT's. The low doped region is referred to as the drift region in these
devices.
A further improvement in the punch-through voltage can be obtained with the
double epitaxial structure shown in Figure 2 . 2 ~The n+-p-n-V-n+ structure permits the
collector-base junction depletion region to spread uniformly into both the n-region of the
collector and the lightly doped p-region of the base[8,9]. If the built-in potential is
neglected, the maximum field across the collector-base junction for a transistor utilizing the
n+-p-v-n+structure is

where Vap is the applied voltage. However, for a symmetrical p-n junction such as the one
found in the double epitaxial structure with Na = Nd, the maximum field is

due to the uniform spreading of the depletion region on both sides of the p-n j ~ n c t i o n . ~
The n-v structure improves the breakdown voltage capability because it makes it possible
to double the voltage across the junction without increasing the maximum field.

2.3.2 HPBT Performance

As in normal transistor action, the base drive current causes the injection of
electrons from the n+-emitter into the p-base region. However, the base region is usually
optimized for high collector-base breakdown voltages and results in emitter injection
efficiency and base transport factors which provide current gain in the range of 10 to 20.
Therefore, HPBT's designed for high voltage operation require substantial base drive
currents during steady-state "on" conduction. This is one of the major drawbacks of
HPBT's. To address the problem of high input current, the Darlington power bipolar
transistor was introduced as a method of cascading two or more bipolar transistors to
obtain higher current gain. Wheatley[lO] showed several orders of magnitude
improvement in current handling ability for multistage Darlington circuits over conventional
discrete HPBT's.

Another drawback associated with HPBT's involves the difficullty paralleling the
devices. Putting several HPBT's in parallel is a technique generally usled to increase the
total current capability of the composite switch. Due to the decrease in th~eon-resistance of
HPBT's with increasing temperature and poor device matching, some HPBT's will cany
more current than others and thus will have a higher probability of burn-out.[ll]
Drawbacks such as these encouraged the development of other controllable switches such
as the power MOSFET.
2.4 Power MOSFET
The power MOSFET was developed in the early 1970's as a solution to several of
the problems inherent in HPBTs. First, as a current controlled device, the HPBT requires
large base drive currents to maintain steady-state forward conduction, and demands even
higher reverse base drive current for high-speed turn-off. By comparison, the high
impedance input of the power MOSFET requires only a fraction of the HPBT's input
current. Secondly, due to a decrease in the forward voltage drop with increasing
temperature, a complex and expensive ballasting scheme is required to safely balance
cumnt flow in paralleled HPBT's. On the other hand, the positive tempr:rature coefficient
of resistance for power MOSFETs enables them to be paralleled very easily. Finally,
HPBT's are susceptible to secondary breakdown of the collector-base junction.
Secondary breakdown[l2-141 is characterized by a precipitous drop in collector-emitter
voltage at large collector currents resulting in a substantial increase in power dissipation.
Fortunately, power MOSFETs are virtually immune to secondary breakdown.
2.4.1 Power MOSFET Structure
The power MOSFET structure differs from the basic, low voltage structure in two
key aspects. The first difference is the use of a double-diffusion technique to achieve very
short, well controlled channel lengths. The term "DMOS" is used to describe devices
fabricated via this technique. Using the gate material as a mask, sequential diffusions of
the p-base region and the n+-source region result in channel lengths in the P-region
comparable to bipolar transistor base widths.[l6,17] Large device tran!sconductanceand
gain, as well as superior high frequency response are by-products of the short channel
length.
The second major difference is the incorporation of a lightly doped n- extended
drain drift region necessary for high voltage operation. The drift region is located between
the channel and the n+-drain contact, and supports the majority of the applied drain

P - Substrate

Gate
Source

p r +, ~
+

P - Base

1 I

N - Drift Region

N+ - Substrate
Drain

channel region '

channel region

N- drift region

N+-Substrate
Drain

F i p 2.4 Cross sections of three high-voltage DMOS devices: (A) LDMOS,

(B) VDMOS, and (C)VMOS.

potential because it's doped at a level much lower than the p-type channel region.
Although most power MOSFETs utilize these two basic principles, at least three basic
structures exist to implement them. They are the lateral DMOS (LDklOS), the vertical
drain DMOS (VDMOS), and the V-groove MOSFET (VMOS).
Sigg et. a1.[18] and Declerq et. a1.[19] developed n-channel lateral DMOS devices
fabricated on <100> oriented crystal silicon. The basic &vice structure shown in Figure
2.4a is fabricated by first oxidizing an epitaxial n--silicon layer on a1 p-type substrate
wafer. The starting material's resistivity determines the forward blocking capability of the
LDMOS. After patterning the initial oxide, the p-base region, and the n+-source region are
implanted and diffused sequentially through the oxide window. The 11+-drainregion is
also defined and implanted at the same time as the n+-source region. 'I'he gate region is
then patterned and oxidized to the &sired thickness followed by metallization. With the
source, drain and gate contacts on the top surface of the wafer, the LDMOS device has the
advantage of ease of integration but it suffers from poor silicon area utj~lizationdue to an
increase in the drift region length at higher voltage ratings.
In an attempt to address the problem of poor silicon chip usage, Colak et. a!. [20]
developed an LDMOS device which utilized the RESURF (REduceci SURface Field)
principle described by Appels and Vaes[21]. Figure 2.5 shows the basic idea of RESURF.
A thin epitaxial layer of high resistivity is grown on top of a substrate of opposite
conductivity. If the total charge per cm2 in the high resistivity layer (N-region) between
the N+ and P+ contacts is greater than 1.2x1012em2, then the N- region will only be
partially depleted and surface limited breakdown will occur. If the charge in the N- region
is less than 1.2x1012cm2, then the N- region will be fully depleted before the critical field
is reached on the surface and breakdown will occur in the bulk. By carefully &signing the
drift region length and thickness, the requirement for larger chip area can be significantly
reduced because breakdown will now occur in the bulk region of the &vice. However, the
inability of all lateral power devices to effectively minimize electric field crowding in the
vicinity of the channel has hindered their performance at high current 1evc:ls. Even with the
aforementioned enhancements, high-voltage power devices with large current canying
capability are fabricated with vertical current paths which range from the wafer surface to a
central, backside con tact.
The VDMOS device shown in Figure 2.4b utilizes a vertical current flow path to
minimize electric field crowding at the gate and to attain a much higher packing density
compared to LDMOS devices. The VDMOS device is fabricated by starting with a highly
conductive n+ substrate and epitaxially growing an n-type drift region. The doping and

Figure 2.5

RESURF Principle: (a) Surface limited breakdown, (b) bulk breakdown.

thickness of this drift region determines the forward blocking capability of the VDMOS
device. As with the LDMOS device, the p-base region and the n+-source region are
diffused through a common window defined by the edges of the polysilicon gate. The
channel length is determined by the difference in the lateral diffusion between the p-base
and n+-source regions. With the source on the top surface of the wafer and the drain on
the bottom, the VDMOS device provides more area for the source region and thus makes
more efficient use of available silicon. VDMOS devices are easily configured to work in
parallel. The structure shown in Figure 2.4b is called a unit cell, and when the VDMOS
devices are arranged in parallel, thousands of these cells are configured in a square array
with contacts made to the source and gate regions. VDMOS unit cells can be packed very
close because their drift region extends into the wafer, not laterally as in LDMOS devices.
Finally, the fabrication of the VMOS device shown in Figure 2 . 4 ~begins similar to
the VDMOS process. An unpatterned p-type base diffusion is performed followed by the
n+-source diffusion. A V-groove is anisotropically etched through these diffusions and
thus forms the channel region along the walls of the V-groove. Although it was one of the
first commercially successful vertical current flow devices, the VMOS device is less
popular now because of process complexity, lower channel mobility along the <100> Vgroove surface which tends to increase device on-resistance, and premature avalanche
breakdown at the tip of the V-groove[22].
2.4.2 Power MOSFET Operation
Operation of all three device structures is essentially the same. Current flow is
established by forming a conductive path between the n+ source region and the n--drift
region. This conductive path is formed by applying a positive gate: bias to the gate
electrode sufficient enough to invert the surface of the p-base region. Tile application of a
positive drain voltage results in current flow between the n+-source andl n+-drain regions
via the inverted channel. Current flow is along a resistive path which consists of the
channel and drift regions.
The power MOSFET is switched to the off state by externally shorting the gate
electrode to the source electrode. With the gate at zero bias, the inversion layer under the
gate cannot be sustained and the power MOSFET is considered to be in its forward
blocking mode. If a positive bias is maintained on the drain, the p-base/n--drift junction
will be reverse biased and thus will serve as the forward blocking junction of the power
MOSFET. The p-base region is also shorted to the n+-source region so that it can remain
at a fixed potential during device operation. Due to the relative dopings of the n and p

regions, the depletion region of the forward blocking junction will extend mainly into the
n--drift region.
Because the power MOSFET is a voltage controlled device, it eliminates the
problem of large input-gate drive currents encountered with HPBT's. Typically, the inputgate impedance of the power MOSFET ranges from 109 to lo1*ohms compared to lo3 to
105 ohms for the HPBT. The higher input-gate impedance of the power MOSFET allows a
simple bias voltage, typically 5-10 volts, to control its on-off switching with no appreciable
steady-state gate current flow. The low input-gate current is possible because current for
the power MOSFET is required only for short periods to charge and discharge the inputgate capacitance during on-off switching, whereas the input-gate current for the HPBT is
required during the entire conduction cycle.
Current flow in the power MOSFET is by majority carriers only. Power
MOSFETs experience no inherent delay or storage time due to minority carriers. HPBT's,
on the other hand, do suffer from an inherent storage time caused by the build-up of
minority camers in the base needed to sustain normal current flow. This storage time may
be on the order of a few microseconds and adversely affects the HPBT's switching speed.
The power MOSFET's switching speed is limited by an RC time constant determined by
the input-gate capacitance and the source and drain impedances. This aspect of the power
MOSFET enable its switching speed to be orders of magnitude faster than HPBTs. Figure
2.6 illustrates the improved ruggedness of power MOSFETs compared to HPBTs. The
absence of a minority carrier induced storage time enables the power MOSFET to respond
faster when reacting to overload or fault conditions. As a result of its fast switching speed,
the power MOSFET is the device of choice for circuits operating at high frequencies where
switching losses should be kept to a minimum.[23-251
Power MOSFETs are paralleled very easily because their on-resistance increases
with increasing temperature. Consider the two power MOSFETs in Figure 2.7. If the
drain to source on-resistance of transistor T2 exceeds the on-resistance of transistor TI,
then T1 will conduct more current during the on state. As the junction temperature of T1
increases and exceeds that of T2 due to an imbalance in the current distribution, the on-state
resistance of T1 will also increase and approach that of T2. The on-resistance of T1
increases because the electron mobility decreases with increased temperature. Therefore,
thermal instabilities are suppressed and a more balanced current distribution among
paralleled MOSFET devices results. This is a key attribute of the power MOSFET
compared to HPBTs because the parallel configuration significantly enhances the net
current handling capability of power MOSFETs. The positive temperature coefficient of

Figure 2.6 Response to overload in a switching power supply: (A) High power bipolar
transistor; (B) power M0SFET.I IS]

Figure 2.7 Parallel connection of MOSFETs.

resistance for power MOSFETs also enhances their ruggedness because the devices will be
immune to hot spot formation and second breakdown phenomena commonly experienced
with HPBTs.[ll]
2.5 Insulated Gate Bipolar Transistor
Although power MOSFETs can be switched on and off much faster than high
power bipolar transistors and they have considerably lower input-gate current drive
requirements, their on-state conduction losses (particularly for power MOSFET devices
designed for high voltage operation) are much larger. The need for a controllable switch
which combines the key advantages of the power MOSFET and the power bipolar
transistor has led to the development of the insulated gate bipolar transistor (IGBT)[26-291.
The IGBT combines the high impedance gate of the power MOSFET with the small onstate conduction losses of the power bipolar transistor. An added feature of the IGBT is its
ability to block both forward and reverse bias voltages. The combination of these features
make the IGBT a superior power device in many circuits where both power bipolar
transistors and power MOSFETs were previously used. Table 2.1 provides a comparative
view of the basic properties of the three major controllable switches.

Table 2.1 Relative Properties of Controllable Switches

Device

Power Capability

BJT

Medium

Medium

High

MOSFET

Low

Fast

Low

IGBT

Medium

Medium

Low

Switching Speed

Input Power

2.5.1 Basic Structure of IGBT

A cross section of an n-channel vertical current flow IGBT is shown in Figure 2.8.
The basic design of the IGBT is very similar to the power MOSFE'T with one very
important exception. A heavily doped p-type region of the anode of the IGBT forms a p-n
junction with the lightly doped n--drift region. This p+ region replaces the: n+ drain contact
of a conventional power MOSFET such as the one illustrated in Figure 2.4.b. In power
MOSFETs, the lightly doped n--drift region is grown very thick in order to support high
voltages in the device's forward blocking mode. However, the thick n--drift region limits
the current carrying capability of the power MOSFET because the region's high resistivity
contributes to a large on-state resistance. The IGBT eliminates this design limitation with
the addition of the p+-anode contact. The pn junction labeled J3 facilitates a reduction in
the on-state resistance by injecting minority carrier holes into the lightly doped n--drift
region during normal forward conduction operation. A large infusion of minority carriers
across junction J3, typically 100 to 1000 times larger than the backgrou~ldconcentration,
reduces the on-state resistance via conductivity modulation[30].
Generally speaking, with the addition of the p+-anode region, the IGBT structure
resembles that of a four layer thyristor. It was the realization that the M(3S gate could be
used to create an inversion layer channel to link the n+-source region to the n--drift region
without latching-on this thyristor structure that led to the creation of the IGBT. With
junction J3 forward biased, current flow will occur from the source to the anode region via
the conductive channel under the gate. IGBTs are designed to suppress the regenerative
turn-on of the parasitic PN-PN' thyristor because full gate control of the output current is
lost if the thyristor is allowed to latch-on. One very common technique used to minimize
the possibility of thyristor latch-on is to short the n+-source region to the p-body region as

o Gate

Cathode/Source

Body Region

Drift Region

P+ - Substrate

Anode

Figure 2.8 Vertical cross section of Insulated Gate Bipolar Transistor (IGBT).

P
J

nepi drift region

/.
3

P - Substrate

Figure 2.9 Vertical cross section of Lateral Insulated Gate Bipolar Transistor (LIGBT).

illustrated in Figure 2.8. The undesirable turn-on of the parasitic thyristor is termed "latchup" and will be discussed thoroughly later in this chapter.
The p+-anode region is usually a boron doped (0.01 f2 cm) (111) oriented substrate
from which the lightly doped n--drift region is epitaxially grown[31]. The doping level of
the n--drift region is typically 1014 to 1015 cm-3. Just as with the power MOSFET, the
doping level of the IGBT's drift region is extremely important because it determines the
breakdown voltage of both the forward blocking (52) and the reverse blocking junction
(J3). Furthermore, if the doping level of the drift region is too large, the injection
efficiency of junction J3 will be severely degraded. The p-body region is where the
channel is established between the n+-source and the n--drift region. The doping level of
the p-body region establishes the voltage required to invert the surface of this region under
the MOS gate. This doping level is usually 1015 to 1016 cm-3. The n+-source region is
~ . p-body and n+-source regions are usually
typically doped very high at 1021 ~ m - The
implanted and diffused sequentially just as with the power MOSFET. The doping in the pbody region will vary with the highest doping level occuring near the n+-sourcelp-body
junction. This peak doping determines the threshold voltage of the IGBT and care must be
taken to restrict its variation when fabricating a number of devices.
Russell et. a1.[32] showed that the fabrication of complementary p-channel devices
was essentially the same as n-channel IGBTs with only the doping type of each region of
the IGBT reversed. Design of power systems using complementary IGBT's has yet to be
exploited due to several drawbacks noted by Chow et. al.[33]. The most difficult of these
problems is the latch-up of p-channel devices at current levels considerably lower than their
n-channel counterpart. The lower latch-up current is due mainly to the higher parasitic npnBJT gain experienced exclusively with p-channel devices.
The Lateral IGBT (LIGBT) shown in Figure 2.9 has the added advantage of being
highly integrable because all the device contacts are on the top surface of the wafer. Using
the RESURF technique, Darwish and Board[34] developed the lateral IGBT as an
integrable MOS-controlled power switch. The thin epitaxial layers characteristic of
RESURFED devices also enable LIGBTs to be easily integrated with low-voltage logic
circuits. However, just as with LDMOS devices, LIGBTs make poor use of available
silicon because the n--drift region must increase with increased voltage ratings.
2.5.2 IGBT Operation
The I-V characteristics of an n-channel IGBT are shown in Figure 2.10. The
characteristics are very similar to a bipolar junction transistor, but unlike the bipolar

transistor, the gate to source voltage, not the base current, is the controlling parameter. The
horizontal axis corresponds to the anode to source applied voltage and the vertical axis
corresponds to the anode current.
In Figure 2.8, junction 53 is the reverse blocking junction of the IGBT. When a
negative anode to source voltage is applied to the device, junction J3 will become reverse
biased, and only a small leakage current flow will occur. As stated earlier, the doping level
of the drift region is critical because the depletion region of the reverse biased junction
should extend mainly into this region. If the drift region is doped ttm lightly, punchthrough will occur when the depletion region of J3 reaches the depletion region of J2[35].
The n--drift region thickness is designed to be equal to the depletion width at maximum
reverse voltage plus one diffusion length. The drift region thickness is also designed to be
as small as possible to support the desired breakdown voltage because the forward voltage
drop and hence, forward conduction power loss, increases with increasing drift region
thickness. Quation (2.3) shows the relationship between the drift regiorr thickness and the
junction breakdown

where Wdriftis the drift region thickness, VBRis the breakdown voltage of junction J3, Nd
is the drift region doping, and LP is the minority carrier diffusion length[:36].
The forward blocking junction of the IGBT is the p-body -n--drift region
junction (J2). With the gate of the IGBT shorted to the source, the inversion layer cannot
form. Therefore, a positive bias at the anode will not stimulate currenit flow because the
inversion layer does not exist to link the n+-source and n--drift regions.. However, with a
positive voltage applied to the anode and the gate shorted to the source, junction 52
becomes reverse biased and the device is in its forward blocking mode. It is important to
design the p-body doping profile in such a way that the depletion region of junction J2
extends mainly into the drift region. The doping level of the p-body region should also be
low enough to enable inversion of the p-body region under the MOS gate for moderate to
low gate voltages. Furthermore, care must be taken to prevent punch-through[37] of
junctions J2 and J3 as the depletion region extends on both sides of junction J2 during
forward blocking.
In many applications, the reverse blocking capability of the IGiBT is not needed.
Therefore, the device structure can be optimized to support very high forward blocking

PIN Diode

Increasing
Gate Voltage
Reverse Blocking Breakdown

4
Forward

Figure 2.10

locki in^ Breakdown

Output characteristics of IGBT.

DOPING CONCENTRATION

ELECTRIC FIELD

FORWARD BLOCKING
N
"

-- - - I - - - - - - la)

DOPING CONCENTRATION

/ /

N+

REVERSE BLOCKING

ELECTRIC FIELD

-- - ---.__
......--

--

REVERSE BLOCKING

Figure 2.11 Doping profile and electric field dismbution for buffer-layered and
non- buffer-layered IGBTs.[36]

voltages. Yilmaz et. a1.[38]showed that the introduction of a highly doped n-type buffer
layer between the p+-anode and the n--drift region allows the thickne.ssof the n--drift
region to be reduced. The n+ buffer region alters the electric field distribution in the drift
region of the IGBT as shown in Figure 2.11. If the critical electric field is assumed to vary
slowly with drift region doping, and if the drift region is doped lightly,,the electric field
distribution will change from triangular to rectangular. This results in ;an increase in the
forward blocking capability of the IGBT by a factor of 2 for the same total drift region
width. The buffer layer's thickness should be as small as possible and should be doped
high enough to ensure the value of the electric field goes to zero within it:

where G*tis the critical electric field for junction 52, NB is the buffer layer doping and d2
is the thickness of the buffer layer. Forward conduction of the IGBT is compromised if the
doping level of the n+ buffer layer is too high. The high doping level will tend to reduce
the injection efficiency of junction 53 and hence any reduction of forwardl voltage drop as a
result of conductivity modulation will not be realized. Therefore, the bufFer layer thickness
and doping level should be chosen very carefully.
The basic equivalent circuit of the IGBT is shown in Figure 2.12.a. The equivalent
circuit illustrates that the IGBT functions as a wide base pnp bipolar tiransistor which is
supplied base current by an n-channel MOSFET. Physically, the collector of the bipolar
transistor (p-body) is shorted to the source of the MOSFET (n+-source). The n+-source
region , p-body region, and n--drift region of Figure 2.12.b form the MCISFET with the n-drift region serving as the drain. The p+-anode region serves as the ernitter of the p+np
bipolar transistor and the long n--drift region is the wide base of the transistor. Using the
equivalent circuit, the on-state forward voltage drop, VDs(on), can be exl?ressedas

where Vj3 is the voltage drop across the emitter-base junction 53. Vj3 is typically a
constant value between 0.7 and 1.0 volts indicative of a forward biased pn junction. Due
to conductivity modulation, the voltage drop across the drift region of the IGBT (Vdrift)is
smaller than the potential drop across the power MOSFET's drift region. Coupled with
the fact that the IDRchannel voltage components are essentially the sanne for both device

Anode

7;.

Drift region

Gate

P - Substrate
+

Anode
Figure 2.12 (A) Equivalent circuit for the IGBT; (B) Effective MOSFET and BJT
operating pomons of IGBT .[30]

Ic
Collector current

Collector
contact

Collector
Collector-base
metallurgical
junction
Depletion
layer
Base edge
Electrons
which
recombine
in base
Holeswhich
'recombine
in base

Base

Electrons
injected
from base
into emitter
Holes which
recombine with
electrons injected
into emitter

Emitter

Emitter contact
Emitter current
IE

Figure 2.13 Schematic diagram of the flow of carriers in IGBT.

types, it is clear that the overall on-state voltage of the IGBT is much less than that of a
comparable power MOSFET. Finally, due to the analysis of the IGBT as a wide-base
bipolar transistor with the MOSFET supplying the base current, the n--drift region will be
referred to as the wide-base region.
Figure 2.13 is a schematic diagram of the flow of carriers in the IGBT. When the
gate to source voltage exceeds the threshold voltage, an n+ inversion layer forms which
shorts the wide-base region to the n+-source region. If a positive anode to source voltage
is applied, current flow will occur with holes being injected across junction 13 into the
wide-base region. The IGBT is now considered to be in its forward conduction mode.
Holes injected from the emitter drift and diffuse across the wide-base region with some
holes traversing the entire base region and some recombining with electrons supplied by the
n-channel MOSFET. Injected holes which reach junction 52 are swept into the collector
because the junction is reversed biased during forward conduction. As the anode voltage is
increased, more holes are injected from the emitter, and correspondingly more electrons are
introduced from the MOSFET. This increase continues until the hole and electron
concentrations exceed the background doping level of the wide base region. The term
"high-level injection" is used to describe this condition. The conductivity of the base
region is greatly enhanced over its ohmic or low-injection level as a result of this infusion
of minority carriers. By modulating the conductivity of the base region, the IGBT can be
designed to support very high blocking voltages and still operate at very high current
densities.
The I-V characteristics of the IGBT shown in Figure 2.10 will be s e l a r to that of a
forward biased p-i-n diode as long as the gate to source bias is large enough to allow the
MOSFET to supply electrons to the base region. Decreasing the gate bias decreases the
conductivity of the inversion layer under the gate and enables a significant voltage drop to
develop across the channel similar to conventional MOSFETs. When the IGBT gate is
biased this low, the forward current will saturate and the device is considered to be in its
forward active mode. In this mode, the channel limits the base current to a near constant
value. Also note the presence of the diode knee at 0.7 volt in Figure 2.10. This is the
forward bias voltage of junction 53 that should be attained before appreciable current flows
in the device.

2.5.3 Mathematical Analysis

The current gain of the IGBT is low because the base current (I,) is supplied by the
MOSFET and is approximately equal to the hole current (Ip) from the emitter. The hole

current results from minority carrier holes being injected by the p+-emitter and traversing
the base region. The IGBT also operates under high level injection conditions during the
forward conduction mode which increases the total recombination in the base region.
Several early analytical models developed for the IGBT obtained high level injection
characteristics by assuming the electron current was much smaller than the hole current as
had been done traditionally[39,40]. Traditional analysis contradicted the lobserved low gain
condition characteristic of IGBT operation. This contradiction inspired Kuo et a1.[41] and
Hefner et. a1.[42] to use ambipolar transport properties to describe the transport of
electrons and holes in the wide-base region of the IGBT. Ambipolar wansport analysis is
necessary because high level injection conditions exist at normal currerlt densities during
forward conduction of the IGBT. The following is a detailed ambipolar transport analysis
of the wide-base region of the IGBT:
Electron and hole currents are generally described by their diffusion and drift
components as follows:

Under high gain conditions typical of most bipolar transistors, traditional analysis enables
the &coupling of the hole and electron current equations under both hiigh- and low-level
injection conditions. For the high gain, low-level injection condition, the: hole current drift
component is neglected and the hole current transport is by diffusion only. The high gain
condition requires the electron current to be approximately zero. For the high gain, highlevel injection condition, the hole drift component can no longer be neglected because p=n
in the base region. Again, the high gain condition requires that the electron current be very
small and therefore I, is usually assumed to be zero[4]. The electric field is obtained from
equation (2.6) by setting In=O. The hole current is found by using the expression for
electric field found in equation (2.6) and the Einstein relation, Dn,p=(kT/q)pn,p. An
expression is found for the hole current which resembles diffusion bui: Dp is replaced by
2Dp.
Under low gain, high-level injection conditions characteristic of IGBTs, equations
(2.6) and (2.7) cannot be decoupled because the low gain condition requires the net
electron current to be almost as large as the hole current. Therefore, the difference between

33
the electron drift and diffusion currents is significant and I, ;c 0. Under these conditions,
the electron current equation can't be used to solve for the electric field.
Using arnbipolar transport analysis under very high level injection conditions, the
assumption is made that

and that quasi-neutrality, An = Ap, holds. Solving for the electric field from equation
(2.61,

The hole current can now be written as

where b = lf9 is the arnbipolar mobility ratio. If the total cunent is given by

PP
IT = In + Ip
then

Solving for the hole current gives

is the ambipolar diffusivity and An=Ap. The electron current is

%+D,
derived in a similar fashion resulting in the following set of equations:
where D =

Both expressions depend on the total current and are therefore coupled.
The time independent ambipolar diffusion equation is obtained using the hole
continuity equation
1

where 7 is the ambipolar lifetime (7 = [2GAp2 +

=no

I-';

G=Auger coefficient ) and

+ tp0

Jp is the hole current density. From equation (2.14a), we have

The hole continuity equation now becomes

If we assume the total current is independent of position in the base region of the IGBT,
then

where L = *is

the ambipolar diffusion length. The above assumption is valid because

the base current enters the wide-base region from the collector end and flows in the same

Using the ambipolar diffusion equation along with the ambipolar current equations,
the steady-state electron and hole carrier concentrations and current densities can be
derived. The derivation is performed using the coordinate system in Figure 2.14. The
steady-state boundary conditions for the excess carrier distribution in the base are:
Ap(w) = 0
Ap(0) = Po
where x=O is the emitter edge of the base region and x=w is the collector edge of base
region. PO is the concentration of injected holes at the emitter-base edge of the wide base
region. The quasi-neutral base width is given by

where the second term on the right side of equation (2.19) is the p-body-n--drift region
depletion width and NB is the wide base region doping. The solution to equation (2.18)
with

= 0 bears the form

and after applying the boundary conditions and assuming high level injection
sinh
Ap(x) = Po
sinh

W-X

[f]

A similar equation can be derived for electrons. Now, assuming high level injection of
holes into the base region, the electron current at x=O is related to Po by:

Figure 2.14 Coordinate system used in carrier concentration

and current density analysis.

DISTANCE FROM EMITTER-BASE JUNCTION (urn)

Figure 2.15 Band diagram from the emitter to base contact of IGEIT.[42]

where Onej and Opej, as illustrated in Figure 2.15, are the electron and hole quasi-fermi
potentials at the emitter-base junction, and Isne is the emitter electron reverse saturation
current. From equation (2.14.a) we have

where

therefore

and

Finally, combining equations (2.14.a), (2.22) and (2.23) gives

cot,(:)
cosh[(Y)I
2
qDW0
Ip(x) = Po 2
L
b +
w
"i
sin h ( ~ )
The electron current is obtained in a similar fashion and has the form
+

(2.24.a)

Equations 2.24.a and 2.24.b describe the hole and electron current flow in the IGBT
during forward conduction. When evaluated at the collector edge of the wide base region,
these equations provide the steady-state collector Ip(w) and base In(w)currents shown in
Figure 2.12.a. The above equations are typically used to study the effects of electron
irradiation on the performance of the IGBT. Electron irradiation lowers the lifetime in the
wide-base region of the IGBT and therefore modifies the output saturation current of the

IGBT. Electron irradiation also allows the IGBT to switch to the off state much faster as
will be discussed in the next section.
2.5.4 Latch-Up in IGBTs
As stated earlier, latch-up is the undesirable turn-on of the parasitic thyristor present
in IGBTs. Once the IGBT is in the latch-up mode, gate control of current flow is lost and
the only way to turn off the IGBT is by a forced commutation of the cun-ent. If latch-up is
allowed to proceed without termination, the IGBT will be destroyed due to excessive
power dissipation, There are two types of latch-up modes encounteretl, they are: static
latch-up which occurs when the continuous on-state current exceeds a [criticalvalue, and
dynamic latch-up which occurs when the IGBT is switched from on to oi'f[36].
The basic mggering mechanism for latch-up is the same in both the static and
dynamic cases. During current flow, the hole current flows into the p-body region and is
collected by the cathode metal contact. A portion of the hole current travels directly to the
cathode metallization but most of the holes are attracted to the vicinity of the inversion layer
under the MOS gate due to the negative charge of the inversion layer. The attraction to the
inversion layer results in a hole cumnt component that travels laterally through the p-body
region as shown in Figure 2.16. The lateral current flow will develop a liiteral voltage drop
in the ohmic resistance of the body layer and will tend to forward bias junction J1. If this
lateral voltage drop exceeds about 0.7 volts, a substantial injection of electrons from the n+
source into the p-body region will occur as illustrated in Figure 2.17. When the injection
of electrons across junction J1 occurs during forward conduction of the IGBT, the device
is considered to be in the static latch-up mode.
Dynamic latch-up differs from the above description only in the IGBT's mode of
operation when latch-up occurs. During turn-off, the MOSFET portion of the IGBT turns
off rapidly resulting in a rapid decrease in the anode to source voltage. The increased
voltage is supported across junction J2 of Figure 2.16. The depletion region of junction J2
expands to support this voltage just as it does during the forward blocking. The increased
depletion width shortens the quasi-neutral base region and thus enables more holes to
traverse the base without recombining. The magnitude of lateral hole current will increase
due to the overall increase in hole current and hence, the lateral voltage under the n+-source
region will increase. Unfortunately, dynamic conditions may cause latch-up to occur at
current levels far below the maximum current levels required for static latch-up.
Several techniques have been employed to improve the latch-up performance of
IGBTs. Most approaches attempt to modify the resistivity of the p-body region with hopes

Cathode/Source

Anode
Figure 2.16 On-state current flow paths of buffered IGBT

Gate

Figure 2.17 (a)Distributionof the electron concentration in the IGBT sitructure at

a forward drop of 1.25 V(non-latch-up);(b)Distribution of the electron
concentration in the IGBT structure at a forward drop of 1.5Vtlatch-up).

of reducing the ohmic drop experienced during lateral current flow under n+-source.
Baliga et. a1.[43] showed that latch-up can be suppressed by increasing the p-base
conductivity with a deep p+ diffusion. Goodman et. a1.[44]showed that an n+ buffer layer
not only improved the forward blocking performance of IGBTs, but it also increased the
latch-up current capability by suppressing the hole injection from the p+ anode region
during forward conduction. Nakagawa et. a1.[45]and Yilmaz et. a1 [46] optimized device
cell geometry to reduce the base-emitter shunt resistance of the IGBT's parasitic npn
transistor. They found that stripe and multiple surface short(MSS) cells have the highest
latch-up cumnt capability because they experience less current crowding due to their larger
minority carrier collector areas. Chow et. a1.[47] improved latch-up performance by
increasing the p-body doping and then implanting the n-channel region with arsenic to
lower the MOS threshold voltage. The method is called Counterdoping of MOS-Channel
(CDC) and it increases the latching current by a factor of 2. Finally, Chang et. a1 [48]
combined the n+ buffer layer with a trench gate structure, as illustrated in Figure 2.18, to
improve latch-up performance. The UMOS-IGBT, as it is called, exhibits a significantly
reduced forward voltage drop due to its increased channel width density. The on-resistance
of the IGBT is inversely proportional to the channel density, and the trench gate structure
increases this density almost 4 fold. Furthermore, the inclusion of the n+ buffer layer to
improve breakdown performance will not result in the typical increase in on-state losses
because the
significantly lower on-resistance will compensate for any increases caused by the buffer
layer.
2.5.5 IGBT Switching Characteristics

Gate-controlled turn-off is a key feature of the IGBT. By removing the gate

voltage, current flow is intempted because the electron current flow from the n-channel
MOSFET hence the base current to the p+np bipolar device is terminated . On-state to
forward blocking state switching is achieved by connecting the gate to the n+-source via an
external circuit that allows discharging of the gate capacitance. The voltage and current
waveforms for the IGBT during gate controlled turn-off are shown in Figure 2.19. The
initial delay, td(off), is the time required for the gate voltage to fall below the threshold
voltage of the IGBT. The anode to source voltage begins to rise as the inversion channel
is removed and the electron current ceases. These delay times are governed strictly by the
MOSFET portion of the IGBT. The IGBT current waveform consists of two segments.
The abrupt drop that occurs during tfl cornsponds to the sudden reduction of the MOSFET

Emltler

Collector

Figure 2.18 Cross-section of n-channel IGBT with a trench gate structure.[48]

+ I

'd(of0-

MOSFET

CUR~L

6JT current

.
+'m+

'11

-+ I

,
,
-

+t

Figure 2.19 Turn-off voltage and current waveforms of an IGB'T.[30]

channel current (I,). The second portion of the current waveform occurs during time tf2.
This delay time is due to stored charge in the wide base region of the IGBT. The stored
charge is removed from the base region by the relatively slow process of recombination.
A trade-off between on-state losses and faster turn-off must be made when
designing the IGBT because the on-state voltage drop increases as the excess carrier
lifetime decreases. Several methods have been employed to speed up the removal of stored
charge from the wide base region and they accounted for many of the major innovations in
IGBT device design during the 80's.
High energy electron irradiation of the IGBT is a common technique used to control
the excess carrier lifetime in the wide base region of the IGBT [49,50]. The bombardment
of the IGBT with high-energy particles introduces mid-gap states in the silicon which
enhances the recombination rate of minority carriers in the wide base region. This
technique offers the advantage of being a clean, well controlled process with a high degree
of predictability. Electron irradiation has reduced the gate turn-off time of IGBTs from
20 1 s to under 200 ns. Another technique employed to enhance switching speed is the
introduction of a highly doped n-type buffer layer at the p+-anode-n--drift region
junction[51]. Due to a p a t e r recombination rate of holes in the buffer layer, the n+-buffer
layer creates a hole density gradient in the wide base region during turn-off. This hole
gradient causes a large flux of diffusing holes toward the n+-buffer layer where they are
quickly removed. Therefore, the removal of the stored charge by diffusion of holes to the
p+-anode region significantly shortens the tn interval because recombination in the wide
base region is no longer the controlling process.
Circuit techniques have also been used to increase the switching speed of IGBTs.
Boisven et. al. [52] developed external circuits shown in Figure 2.20a that apply voltage to
an external capacitor while the IGBT is in the on-state, and uses this voltage to extract the
excess charge stored in the wide base region when the device is switched off. This The
technique has the advantage of not affecting the on-state voltage of the IGBT and thus
avoids the on-state voltage/switching speed dilemma. The incorporation of a p-channel
MOS transistor in the wide base region shown in Figure 2.20b has also been used to draw
excess charge out of the IGBT[53]. This technique has achieved 700 ns turn-off times.

GATE

G A ~ E FLnLJ

GATE

Gc
C

Lm-7

V'i

D
(b)
Figure 2.20 (a) Schematic drawing of modified vertical IGBT with external circuitry
for removal of excess charge, (b) cross-sectional view of vertical CIGBT.

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CHAPTER 3
PROPOSED 3D-IGBT DEVICE

3.1 Introduction
Chapter 2 detailed the relative merits of the three major power devices. For power
devices designed for high voltage and high current operation, the IGBT is superior because
conductivity modulation drastically reduces its specific on-resistance compared to the
power MOSFET. This chapter details the structure and fabrication sequence of a fully
integrable, area efficient IGBT, the proposed 3D-IGBT. An isolation scheme called quasidielectric isolation is also detailed as a means of integrating low power logic devices on the
same chip with the proposed device.
3.2 3D-IGBT Structure
Traditionally, power devices with large current carrying capability have been
fabricated with vertical current flow paths. Using a cellular layout, vertical device designs
result in significant reduction in chip area compared to lateral devices and also minimize
electric field crowding. Unfortunately, the placement of one large current canying terminal
on the backside of the chip, characteristic of vertical device design, limits the circuit
designer to one power device per chip. On the other hand, lateral power devices are not
limited to one device per chip because all their contacts are on the top surface. Therefore,
lateral power devices are used in many circuit applications where a number of power
devices are integrated on the same chip with low power control and detection circuits.
High voltage integrated circuits (HVIC's) are fabricated exclusively with lateral power
devices because of the accessibility of the contacts. The major drawbacks of lateral power
devices are the interdigitated layout and the large drift region resulting in inefficient
utilization of chip area.
The proposed 3D-IGBT combines the flexibility of surface contacts found in lateral
power devices with the area saving cellular structure of vertical devices. The 3D-IGBT, as
shown in Figure 3.1, forms the MOSFET portion of the IGBT along the sidewall of a 4
micron deep trench. The 13 micron unit cell length of the proposed device is considerably

N -- Substrate

Figure 3.1 Cross-sectional view of proposed 3 dimensional insulated gate bipolar

transistor 3D-IGBT.

Cathode
0

Cathode
9

N -- Substrate

Anode
Pigun 3.2 Cross-sectional view of vertical insulated gate bipolar transistor.

smaller than the 45-60 micron unit cell length of lateral power devices. The proposed
device is similar to the trench IGBT in Figure 2.18; however, the 3D-IGBT uses selective
epitaxial growth of silicon (SEG) to form the anode contact in the trench and therefore
eliminates the central, backside contact. As stated earlier, having all the contacts on the top
surface of the chip enables the integration of several power devices with low power
devices. Not only does the 3D-IGBT provide low on-resistance as a result of conductivity
modulation , a further reduction in on-resistance is attained from an increase in the 3DIGBT's channel density compared to lateral IGBT's. The channel density is defined as the
channel width per cm2 of active area. Therefore, for a given area, the 3D-IGBT has a
higher current conduction capability due to its larger gate width.
A parasitic JFET effect is a major component of the drift region resistance in vertical
IGBTs. The JFET region is located between the two P-base diffusions shown in Figure
3.2, and as the figure illustrates, the resistive component results from the depletion region
pinching off this portion of the IGBT during forward active operation. Because the trench
separates the two P-base diffusions in the 3D-IGBT structure, the JFET component of the
drift region resistance is virtually eliminated. Finally, the 3D-IGBT structure is more
immune to latch-up compared to vertcal IGBT's. Latching current density, the maximum
current in the IGBT before latch-up is encountered, decreases inversely with the n+-source
length, L, illustrated in Figs. 3.1 and 3.2. Compared to the vertical IGBT, the 3D-IGBT's
shorter n+-source length enables it to operate at a higher current level before latch-up is
encountered.
The integrable 3D-IGBT lends itself very well to circuit applications which combine
low power control and detection circuits along with high power devices. To combine low
and high power devices on the same chip, an isolation technique should be employed to
electrically separate them. Junction isolation (JI) and dielectric isolation @I) are the two
major isolation schemes presently being used. As an alternative to Jl and DI methods, an
area saving technique called quasi-dielectric isolation (QDI) is proposed and is discussed
later in this chapter. QDI uses a combination of JI and DI to electrically isolate low and
high power devices. The following sections will detail the fabrication process of the 3DIGBT and present work already completed on the development of QDI.
3.3 3D-IGBT Fabrication Sequence
Processing the 3D-IGBT device begins by implanting an n-type (4.5 R-cm), <100>
wafer with boron to form the P-base region. The boron implant is driven-in and the
resulting surface oxide is patterned to mask the wafer for the P+ latch-up protection

N -- Substrate

Si

Polysilicon

1
Figure 3.3

N -- Substrate

Proposed 3D-IGBT process sequence: (a) implant P-base, P+ latch-up

protection and N+ source regions, (b) RIE trench, and form gate oxide,
(c) deposit polysilicon and define photoresist for masking polysilicon,
(d) etch polysilicon and gate oxide, (e) oxidize to form seed window
oxide and define photoresist for masking oxide, ( f ) etch oxide to form
seed window. (g) grow low and moderately doped SEG , (h) planarize
SEG then implant with boron to form anode, (i) etch contacts and deposit
metal to form final structure.

I
Figure 3.3, continued

N -- Substrate

--

N Substrate

N Substrate

Cathode
?

N -- Substrate

Figure 3.3, continued

implant. Following the P+implant drive-in, the surface oxide is again patterned to expose
areas for the n+ implant. The wafer is implanted with arsenic and then driven-in to form
what will eventually be the n+-source of the 3D-IGBT. Figure 3.3a shows the wafer
following the P-base, P+latch-up, and n+-source implants. The difference in the vertical
junction depths of the n+-source diffusion and the P-base diffusion, LChshown in Figure
3.3a, constitutes the channel length of the MOSFET portion of the 3D-IGBT. Next, silicon
nitride is deposited on the wafer to serve as a mask for the reactive ion etching of the
trench. After patterning the nitride, a 4.0 pm deep, 10.0 pm wide trench is etched as
illustrated in Figure 3.3b. The wafer is then wet etched to remove all the oxide and then
reoxidized to fortp a very thin oxide layer. This thin oxide layer is grown to remove RIE
induced surface damage along the trench sidewall. The thin oxide is removed using a wet
etch, and a 1000 A gate oxide is thermally grown as shown in Figure 3.3b. A 1.0 pm
layer of polysilicon is deposited over the entire wafer and implanted with phosphorous. In
facilities where doped polysilicon is available, it would be simpler to deposit doped
polysilicon. Photoresist is spun on the wafer and defined as shown in Figure 3.3~.RIE is
used to remove any polysilicon and gate oxide not masked by the photoresist. The
resulting device profile is shown in Figure 3.3d.
The photoresist is removed followed by the growth of a 1.0 pm thick thermal oxide
layer. Again, photoresist is spun on and defined as illustrated in Figure 3.3e. The
unmasked oxide layer is etched using a combination of RIE and wet etching. The etched
oxide shown in Figure 3.3f forms the seed window for the low temperature, selective
epitaxial growth of silicon (SEG)[Z]. After removing the photoresist, 3 microns of low
doped n-type SEG silicon is grown followed by approximatelly 2 microns of moderately
doped SEG silicon. The higher doped silicon will serve as the buffer layer between the
anode and the n- - drift region of the 3D-IGBT. As the SEG silicon grows out of the
trench, it begins to grow laterallly over the field oxide as shown in Figure 3.3g. Using the
field oxide as an etch stop, the SEG silicon is planarized using a chemical mechanical
polishing(CMP)technique[2]. In Figure 3.3h, the SEG silicon is planarized back to the
field oxide surface and then implanted with boron to form the anode region of the 3DIGBT. Finally, the metal contact openings are defined and etched, and metal is deposited
to form the final structure of the 3D-IGBT shown in Figure 3.3i.
The most critical aspect of the process is the definition of the oxide and polysilicon
layers in the bottom of the trench. The segregation of the photoresist at the edge of the
trench region and subsequent patterning of the photoresist are the most challenging steps of
the entire process. Misalignment of the polysilcon and oxide layers in the bottom of the

trench can be overcome by simply growing the SEG until it totally fills the trench region
and then using the CMP process to remove the excess silicon. The QDI process described
in the next section demonstrates the ability to define a seed window in the bottom of a deep
trench (10 pm), facilitates the evaluation of the quality of the silicon selectively grown in
deep trenches, and shows the effectiveness of the CMP process in removing excess SEG
silicon. Therefore, the proccessing steps developed for the QDI are crucial to the
successful development of the 3D-IGBT.
3.4 Quasi-Dieleclric Isolation
Using a combination of JI and DI, the QDI process was achieved by selective
epitaxial growth (SEG) of single crystal silicon in an oxide lined trench. The QDI process
for smart power 1 - 0 , as illustrated in Figure 3.4a, offers separate epitaxial thicknesses
( D eand
~ Dele) and resistivities in the control and power device areas and therefore enables
the independent optimization of the control circuits and high power devices. Figure 3.4b
shows the 3D-IGBT in the QDI tub. By controlling the trench depth and SEG silicon
resistivity, key parameters such as the breakdown voltage and collector resistance of the
power device can be optimized without compromising the performance of the low power
control circuits. Similar to DI, the QDI process enables a much denser packing of &vices
which results in significant area savings compared to JI. Furthermore, the QDI process
does not require the complex pre-processing of the substrate as found in most full DI
processes. Also, where other processes require high precision grind iuad polish steps to
detennine the epi thickness[3], the QDI process uses a local oxide etch stop and the trench
depth to establish the epi thickness. The wafer polishing and the trench etch are well
controlled processes and are standard in most I-C facilities.
A modified DI process called VLCS exploits the low thermal resistance of single
crystal silicon by allowing the power device to directly contact a heat sink through single
crystal silicon[4]. Single crystal silicon has about an order of magnitude lower thermal
resistance compared to SiO2. The QDI process also capitalizes on the lower thermal
resistance of single crystal silicon because the device islands are connected directly to the
single crystal silicon through the seed window. Therefore, the QDI process affords the
ability to reduce the thermal resistance of the device island while maintaining the original
substrate, and still avoids the backside polysilicon deposition and full wafer grind and
polish steps of both DI and VLCS. Note that since the Si02 seed winciow area used for
EL0 growth can be varied lithographically, the amount of heat dissipation to the substrate
can be varied as well. The ability to vary the seed window width results iin flexibility when

Low Voltage NPN

7
I

Hlgh Power QDI-BJT

P- Substrate

CathAe Fate

Anode

Gap .Cathode

Figure 3.4 (a)Lntegrationof high and low power devices for smart
power applications using the QDI process,(b) 3D-IGBT
fabricated in QDI tub for use in smart power applications.

device parasitics in high current and high voltage applications are considered. As will be
discussed later, overgrowth of the SEG and local area etch stops for planarization are used
to eliminate any faceting from the SEG and provide a planar surface.
The QDI-BJT discussed here is used to show the feasibility of this novel isolation
process and to facilitate the analysis of the electrical properties of the epitaxial lateral
overgrowth (ELO) silicon grown selectively in a deep trench. The analysis of the electrical
properties was obtained by comparing the QDI-BJT device to identical BJT devices located
in the same die but fabricated in substrate material. The QDI-BJT incorporates an ionimplanted buried collector to reduce collector resistance. It is shown that growth of a
&vice quality second layer of SEG silicon from a previously imp1ant.d SEG layer is
successful in the incorporation of a buried collector. A buried collector h e d by in-situ
doped SEG silicon using phosphine provides an alternative to the ion-implantation and the
double growth approach. Finally, a simple planarization process to remove approximately
10 microns of EL0 silicon above the tub edge is demonstrated. The planarization step
eliminates the EL0 faceting and provides a more planar surface to achieve a minimum
geometry device. The next section describes the fabrication sequence used to fabricate the
QDI-BJT.
3.4.1 Fabrication of QDI-BJT
Fabrication of the QDI-BJT began by thermally growing approximately 0.5 microns
of field oxide on a P-type (100) silicon wafer as illustrated in Figure 3.5a. The field oxide
was then wet etched to form rectangular basin windows oriented 45' to the <110> wafer
flat, along the <loo> direction. Using the field oxide as a mask, a 10 micron deep mnch
was then anisotropically etched using a mixture of potassium hydroxide (KOH), water, and
N-propanol as shown in Figure 3.5b. To achieve a consistent etch rate, the mixture was
maintained at a temperature of 8 1C +/- 1C. Next, the oxi& mask layer was removed by
wet etching the wafer in BHF for 5 minutes. The QDI isolation oxide was then grown to a
thickness of approximately 0.5 microns. The seed window for SEG growth was defined
in this oxide at the bottom of the mnch. Once the SEG grows beyond the seed window, it
grows laterally across the oxide and hence this mode of single crystal silicon growth is
referred to as epitaxial lateral overgrowth (ELO). Definition of the seed hole feature in the
bottom of the basin was challenging due to photoresist breakaway at the: top edges of the
basin rim. To solve this problem, AZ-4620 positive resist was spun on the wafer at 3000
RPM for 30 seconds in order to coat the wafer without resist bre&away[5]. This
provided a relatively thick photoresist coating of approximately 6 microns. A SUSS MJB-

OXIDE

P- Substrate

(b)

IMPLANT

4 4 4 4 4 4 4 4 4 4 4 4

P- Substrate

(c>

---

P- Substrate

(dl
collector

Figure 3.5

emitter

collector

QDI-BJT process flow: (a) Oxidize p-type (100) wafer, (b)

define and etch trench, (c) define seed hole, grow ELO,
and implant, (d) grow second ELO, (e) planarize E L 0 and
fabricate BJT's.

3 contact mask aligner was used to expose the photoresist at the bottom of the 10 micron
deep trench. The seed window was opened by wet etching the exposed oxide in the bottom
of the trench. Seed hole definition in the 10 micron deep trench was excellent with
essentially all seed windows successfully etched.
The exposed silicon served as a seed for the first of two EL0 silicon growth
cycles. Initially, approximately 2 microns of EL0 was grown from the bottom of the
trench. The ELO growth is a complex series of chemical reactions involving dichlorosilane
(DCS), H2 and HCl in a commercial reduced-pressure CVD pancake-type reactor
(Gernini)[l,6]. Typically, the SEGlELO of this work was grown at temperatures which
ranged between 950 OC and 1000 OC, and at pressures of 40 Tom or 150 Tom. The wafer
was then implanted with 3x1015 cm-2 of phosphorous at 25 keV, as illustrated in Figure
3.5c, to form the buried collector. The implanted EL0 was then annealed in a nitrogen
ambient at 1100 OC for 20 minutes. The final EL0 layer was grown using the initial EL0
as a seed. Once the ELO was above the surface of the seed window oxi&, the growth rate
of Si in the vertical direction was approximately equal to the growth rate in the lateral
direction. The maximum distance from the seed window to the basin sidewall, Dsi&, was
10 microns (see Figure 3.4; therefore, the EL0 layer was grown such that the distance
from the field oxide to the top of the ELO was 10 microns as illustrated in Figure 3.5d.
The remaining portion of the buried collector diffused from the oxide sidewall into the
second ELO.
As an alternative to the ion implantation of the buried collector, an in-situ doped
buried collector was also fabricated. The wafer was implanted with, 3x1015 cm-2 of
phosphorous at 25 keV following the seed window oxide growth. The seed window was
then etched and approximately 2 microns of undoped ELO silicon were grown followed by
1 micron of heavily in-situ doped (phosphine) ELO. Finally, for the second and final
growth, approximately 17 microns of undoped EL0 was grown with about 10 microns of
overgrowth out of the trench. Chemical-mechanical planarization (CMP) was then used to
remove the overgrowth of silicon formed by both the ion implantation method and the insitu doping method[2]. This planarization step eliminates the problem of edge faceting
because the entire basin is filled with EL0 silicon. The local field oxide: serves as an etch
stop for the chemical-mechanical planarization of the wafer. The wafeir EL0 uniformity
was excellent since the QDI process does not require backside polysilicon deposition which
introduces wafer bowing. The local etch stop technique employed bly QDI and other
processes have achieved EL0 thickness variations of less than 100 Ilm over a 3 inch

wafer[7]. It should be noted that a Si3N4local etch stop has also been used and resulted in
excellent selectivity between silicon and nitride.
Following the CMP, the base, emitter and collector were implanted and thermally
activated to form a bipolar transistor in the EL0 single crystal silicon and also in the
substrate material. Contact holes for the base, collector and emitter were opened and the
device was metallized with Al-Si, as illustrated in Figure 3.5e. Finally, due to the size of
the seed window, backside gettering could be accomplished following &vice fabrication.
3.4.2 Results of QDI-BJT Fabrication
The most critical aspect for demonstrating the feasibility of the QDI-BJT with an
implanted buried collector, is the quality of the EL0 silicon following the implant and
subsequent anneal. Ideally, the QDI &vices should show no significant degradation as
compared to the substrate devices. Bipolar test structures were placed in the substrate as
well as in the implanted ELO, both being in the same die. This was done to achieve the
best comparison between the substrate material and the implanted EL0 material. Table 3.1
lists the averaged electrical characteristics of un-gettered devices fabricated in both the
substrate and the QDI region. Thirty devices from each area were measured The junction
ideality factors, eta, are ideally 1.00, indicating no recombination current is present. The
eta factors of the QDI-BJT at 1.10 for the base-emitter and 1.07 for the base-collector are
very close to those in the substrate at 1.09 and 1.06 respectively. Junction reverse bias
leakage currents, Jeb, and Jcb, for the E L 0 material are comparable to those in the
substrate devices as well as the reverse bias breakdown voltages , BVebo for the emitterfor the collector-base junction. Note that the collector-base reverse
base, and BVC~O
saturation currents are smaller than the emitter-base as expected. The comparable ideality
factors, leakage currents, and breakdown voltages in the EL0 and substrate materials
indicate that the EL0 material is of device quality and that device performance will not be
compromised when fabricated in the EL0 material. The results clearly demonstrate the
feasibility of an ion implanted buried collector and second EL0 growth.
Table 3.1 shows a drastic reduction in the collector resistance of the QDI-BJT. The
QDI-BJT collector resistance of 204.7 R, compared to that of the substrate device at
1,539.2 R represents almost an order of magnitude reduction in this critical parameter, and
clearly demonstrates the presence of the buried collector. The value of r, can be reduced
even further by additional doping and design of the thickness of the buried layer. Also, a
low temperature doped oxide can be deposited on the trench oxide for better out diffusion
of impurities.

Table 3.1

Substrate vs. QDI-BJT Electrical Data

204.7

1,539.2

Peak Gain

48.8

42.9

BV,,

(volts)

11.0

13.0

BVc,

(volts)

110.0

120.0

c'

Figure 3. 6 (a)Spreading resisitance profile (SRP) data of in-situ doped

buried collector, and (b) ion implanted buried collector.

Figure 3.6a shows spreading resistance profile (SRP) data for the in-situ doped
buried collector QDI-BJT. The buried collector is shown approximately 8 microns below
the EL0 surface. The sharp drop in the doping concentration at the intrinsic collector buried collector interface indicates that the removal of the dopant gas phosphine from the
reactor was rapid and complete. Figure 3.6b shows the SRP data for the ion-implanted
buried collector. Note the buried collector region approximately 6.2 microns below the
device surface. Comparing the in-situ doped EL0 to the ion-implanted material indicates
that both are of high quality. Hence either method is effective in forming the burid
collector.
The collector-substrate junction of the QDI-BJT is also the isolation junction for the
entire device. The leakage cumnt of this un-gettered junction is 10.6x10-~~ l c m *at a
reverse bias of 50 volts. Devices were fabricated with collector to substrate breakdown
voltages as high as 140 volts for this isolation junction. No attempt was made to optimize
these parameters. Figure 3.7 is an electron micrograph of a cross section of the QDI-BJT
before planarization. It indicates a trench depth of approximately 10 microns and an
isolation oxide thickness of approximately 0.5 microns. The output characteristics of the
QDI-BJT in Figure 3.8 indicate a breakdown voltage of 70 volts. Much larger breakdown
voltages are possible since in the QDI-BJT, the breakdown voltage can be controlled by
varying the depth of the trench and by optimizing the resistivity of the ELO.
Figure 3.9 shows a P vs, I, plot of a typical QDI-BJT. Other fabrication runs
have shown betas of over 200. Note the flatness of the P over nearly 3 decades of collector
current, indicating very little recombination current present and excellent crystal quality of
the E L 0 material. Figure 3.10a is an SEM which illustrates the case where no CM
polishing was used. Note the faceting near the edges of the QDI tub. Although the
faceting does not hinder metal step coverage, it does reduce the amount of useable silicon
for device fabrication5. The QDI tub area is typically increased to compensate for the area
lost to faceting. The CMP process enables the possibility of fabricating a minimum
geometry device because by employing the chemical-mechanical polishing technique, the
faceting problem is eliminated and hence, no increase in the QDI tub area is needed. A
QDJ-BJT with CMP is illustrated in Figure 3.10b. This figure shows the effectiveness of
the chemical-mechanical polishing in eliminating the effects of EL0 faceting.
3.4.3 Summary of QDI-BJT Study
A novel quasi-dielectrically isolated bipolar junction transistor was successfully
fabricated and tested. The emitter-base and collector-base ideality factors were very close

Figure 3.7

Scanning electron micrograph of a cross section of the

QDT-BJT before planarization.

Figure 3.8

Output characteristics of QDT-BJT.

HFEf

MARKER ( 1.27rnA , 46.2Ei-00,

1E+03

decade
/div

1E-01
1 E-05

IC

decade/div

Figure 3.9 Beta vs. I, plot of the QDI-BJT.

1E-01
( A)

Figure 3.10

Scanninig electron micrograph of QDI-BJT

(a) without CMP and (b) with CMP.

to devices fabricated in the substrate indicating excellent crystal quality of the EL0 material.
Results indicate that a working QDI-BJT &vice can be achieved with an ion-implanted
buried collector and a second growth, as well as with a buried collector formed via in-siru
doping during growth. Chemical mechanical planarization (CMP) was shown to eliminate
faceting and thus create a uniformly planar surface topology. Fabricated devices
demonstrate isolation breakdown voltages up to 140 volts and leakage currents as low as
1 0 . 6 ~ 1 ~0 /~c~r n ~Due
. to the reduced area nquind for QDI and the ability to independently
modify the high and low voltage process parameters, this novel isolation technique has
been shown to be an effective alternative to existing isolation techniques.
3.5 Chapter Summary
A new insulated gate bipolar transistor structure, the 3D-IGBT, was presented.
The 3D-IGBT should exhibit a much lower on-resistance compared to lateral devices
because it eliminates the need for an interdigitated layout and it also eliminates the parasitic
JFET resistance found in vertical IGBT's. The 3D-IGBT offers the first ever cellular
layout for a fully integrable power device and therefore makes efficient use of available
silicon. To integrate the 3D-IGBT with low power devices, the QDI method of device
isolation was proposed. QDI uses a combination of JI and DI to electrically isolate low and
high power devices. It has been shown that the selective epitaxial silicon grown in deep
trenches is of device quality and that the use of a trench structure to facilitate isolation and
control of SEG thickness should be i&al in applications where the thickness and resistivity
of the control and power areas are independently optimized. Finally, a chemical mechanical
polishing technique has been shown to effectively remove excess silicon to provide a more
planar surface topology and eliminate the problems caused by SEG faceting.

3.6 References
1.

R. Zingg, J.A. Friedrich, G.W. Neudeck, and B. Hoefflinger, "Three Dimensional

Stacked MOS Transistors By Localized Silicon Epitaxial Overgrowth" ,IEEE
Transactions on Electron Devices, vol. 37, p. 1452, June 1990.

2.

B. Davari, C.W. Koburger, R. Schultz, J.D. Warnock, T. Furukawa, M. Jost, Y.

Taur, W.G. Schwittek, J.K. DeBrosse, M.L. Kerbaugh and J.L. Mauer, "A New
Planarization Technique, Using A Combination of R E and Chemical Mechanical
Polish (CMP)," 1989 IEDM Technical Digest, p. 61, December 1989,.

3. J. L. Sutor, B. Boland, S.P. Robb, and L. Terry, "A Novel Isolation Structure For
SMARTpower IC's" ,1986 IEDM Technical Digest, p. 214, December 1986.
4. Y. Sugawara and T. Shirasawa, "Novel Dielecmcally Isolated Intelligent Power IC
Technology Using Vertical Lateral Composite Structure (VLCS)", 1987 IEDM
Technical Digest, p.762, December 1987.
5. S. J. Duey and G. Neudeck, "A Novel Quasi-Dielectrically Isolated Bipolar Junction
Transistors Using Epitaxial Lateral Overgrowth", Proceedings of the Bipolar Circuits
and Technology Meeting, p. 241, September 1988.
6. J.A. Friedrich and G.W. Neudeck, "Interface Characterization of Silicon Epitaxial
Lateral Growth over Existing Si02 for Three-Dimensional CMOS Structures," IEEE
Electron Device Letters, vol. 10, no. 4, p. 144, April 989.
7. G. Shahidi, B. Davari, Y. Taur, J. Warnock, M.R. Wordeman, P. McFarland, S.
Mader, M. Rodriguez, R. Assenza, G. Bronner, B. Ginsberg, T. Lii, M. Polcari, and
T.H. Ning,"Fabrication of CMOS on Ultrathin SO1 Obtained By Epitaxial Lateral
Overgrowth and Chemical-Mechanical Polishing", 1990 IEDM Technical Digest,
p.587, December 1990.

CHAPTER 4
3D-IGBT SIMULATION STUDIES

4.1 Introduction
Two dimensional simulations have been performed on the 3D-IGBT device to
establish its on-resistance, latch-up performance and forward blocking capability. The
PISCES 11-b[l] program was used to analyze the 3D-IGBT. PISCES is a two dimensional
device simulator that utilizes finite element approximations and a Gummel-Newton
numerical method to solve descretized semiconductor equations defining carrier transport.
This chapter verifies the normal forward active and blocking modes of the 3D-IGBT by
illustrating the formation of the conductive inversion channel along the sidewall MOS
portion of the device, by establishing the existence of gate-controlled current flow, by
demonstrating the suppresion of latch-up and by illustrating the blocking of current flow
during forward blocking operation. Only preliminary studies are discussed in this chapter.
Further work will be done to optimize device parameters.
4.2 Forward Blocking Operation
The basic 3D-IGBT unit cell structure used in the PISCES simulations is shown in
Figure 4.la where the unit cell dimensions and dopant types are shown. As noted in
Chapter 3, the inversion channel for the MOS portion of the 3D-IGBT is formed along the
sidewall of the trench, and therefore, the channel length is determined by the difference
between the depths of the P-base and N+-source diffusions. In the forward blocking
mode, the depletion region of the P-basem'-drift region junction extends on both sides of
the junction. The 3D-IGBT is in its forward blocking mode when the gate electrode is
shorted to the source to prevent the formation of the inversion layer under the gate. With a
positive voltage applied to the anode, the P-base/Nm-driftregion junction becomes reverse
biased. This junction is referred to as the forward blocking junction.
Design of the P-base doping profile is complicated by the fact that the P-base
doping must be relatively low to permit the inversion of the channel under the gate during

N - - SEG

---.

n-epi drift region

- 15.
- - 14.0
-.

12.L

-7

' 1

P - Substrate

Figure 4.1 Cross-sectional device structure of the (a) 3D-IGBT and (b) the lateral IGBT
(LIGBT) showing critical dimensions used in PISCES simulations. All
dimensions are in microns.

Figure 4.2

3D-IGBT doping profile used in PISCES simulations.

forward active operation but must also contain sufficient charge to prevent punch-through
of the depletion region to the N+-source when in the forward blocking mode. The surface
concentration of the P-base diffusion and the N+-source depth combine to determine the
peak doping in the P-base region. Note that the peak P-base doping controls the threshold
voltage of the 3D-IGBT. The doping profile of the 3D-IGBT used in the PISCES
simulations is shown in Figure 4.2. Here the profile indicates that the sidewall channel will
occuring near the N+-source
have a graded doping profile with a peak doping of 3xl0'~cm-~
junction. Figure 4.3 illustrates the movement of the blocking junction's depletion region
with increasing anode voltage, and thus verifies the ability of the 3D-IGBT to operate in the
forward blocking mode.
PISCES has also been used to detect premature punch-through of the forward
blocking junction's depletion region to the P+-anode/N--driftregion junction's depletion
region. When the polysilicon gate is held at zero volts, and a positive voltage is applied to
the anode, the trench SEG will become depleted at sufficiently large anode voltages. This
depletion region can link-up with the forward blocking junction's depletion region and
extend toward the P+-anode. The N+ buffer layer in Figure 4.1 is there to safeguard
against punch-through. A thicker seed window oxide could also delay the onset of
depletion along the sidewall of the 3D-IGBT.
Breakdown of the 3D-IGBT is limited by internal local field peaks. F i g u ~
4.4 is a
contour plot of equipotential surfaces and illustrates field crowding around the bottom of
the trench near the polysilicon gate. The typical breakdown voltage of the 3D-IGBT has
been approximately 100 volts. The sharp cornen of the polysilicon gate and the electric
field crowding in the oxide are the two primary reasons limiting the breakdown voltage.
Futu~
simulations will investigate the effects of a smoother polysilicon geometry, thicker
oxide and a modified buffer layer on the breakdown voltage. It is expected that the device
should block forward voltages in excess of 200 volts with the above improvements.
Lateral RESURFED IGBT's designed for breakdown voltages in this range have unit cell
lengths approximately 60 microns long, with drift regions approximately 20 microns long.
Due to the 3D-IGBT's cellular layout, the lateral drift region is eliminated, and it's smaller
unit cell (11.5 pm) makes more efficient use of available silicon when several unit cells are
combined. The 3D-IGBT represents the first integrable power device that doesn't require a
lateral drift region. The next section will detail how the 3D-IGBT's cellular layout reduces
the device's total on-resistance.

Figure 4.3 Forward blocking junction depletion region as anode voltage is increased.

Figure 4.4 Contour plot of equipotential surfaces from 1 volt to 90 volts.

4.3 Forward Active Operation

The formation of the inversion channel along the sidewall MOS portion of the 3DIGBT is necessary for normal current flow during forward active operation. The 3D-IGBT
is in the forward active mode when the gate voltage is biased above the threshold voltage of
the MOS device and the anode is forward biased above 0.7 volts. PISCES simulations in
the forward active region began by verfying the formation of the inversion channel. With
the anode region held at zero volts and the cathode (N+-source/P-bodyshorted) contact held
at zero volts, the gate voltage was stepped from 0 volts to 15 volts in 1 volt increments.
The plot in Figure 4.5a shows the hole and electron concentrations in the P-body region
under the polysilicon gate when the gate is biased at zero volts. Figure 4.5b shows the
formation of the inversion channel under the gate when the gate is biased at 6 volts. At
V,=6 volts, the electron concentration has increased to almost lx10'~cm" while the hole
concentration has fallen to 5xl0~cm". With the inversion channel formed, the N--drift
region is now electrically shorted to the N+-sourceregion via this channel. Increasing the
gate voltage well above the threshold voltage increases the conductivity of the inversion
channel, and allows the injection of more electrons into the drift region.
With the inversion layer formed, a positive bias is applied to the anode of the 3DIGBT. This positive bias forward biases the andeldrift region junction. When the
forward bias is greater than approximately 0.7 volts, an appreciable amount of holes will be
injected from the P+-anodeinto the N--drift region. Electrons from the N+-sourcewill also
be injected in the drift region via the inversion channel to counter the sudden increase in
holes. As the anode bias increased, the hole and electron concentrations continue to
increase until they both exceed the original background doping. The drift xegion is now in
high level injection and its conductivity has been enhanced. Figuxe 4.6 shows the electron
and hole concentrations in the drift region at a gate bias of 15 volts and an anode voltage of
8 volts. The electron concentration has risen from 1 x l 0 ' ~ c mto~almost
~
l x 1 0 ' ~ c mand
~ the
to almost 1xloncm-'. The modulation of the
hole concentration has gone from lx10~cm'~
drift region's conductivity drastically reduces the 3D-IGBT's on-resistance as compared to
similar power MOSFETs. Figure 4.7 illustrates the effect of gate bias on the forward
active output characteristics of the 3D-IGBT. The plot verifies the gate control of current in
the 3D-IGBT device. As expected, the forward conduction characteristics approach those
of a PIN diode as the gate bias is increased well above the threshold voltage. If the
inversion layer's conductivity is low, corresponding to moderate to low gate biases, a

Total Doping

lectron Concentration

Hole Concentration

i . ' . . I . . . I . . . , . . . I . . . I
0.0
2.0
4.0
6.0
8.0
10.0
Distance

(Hicrons)

(a)
1

'

"

"

'

'

'

Vg=6 volts

22

lectron Concentration
C

.:

14

6-

Hole Concentration

4-

0.0

2.0

4.0

6.0

Distance

(Hicrone)

8.0

18.0

(b)
Figure 4.5

Hole and electron concentrations in P-base region at (a) 0 volts

and (b) 6 volts.

Distance

(Hicrone)

Figure 4.6 Hole and electron concentration in channel region with 3D-IGBT
in forward active mode.

- ;;:- /
-

3D-IGBT Output Characteristics

vg=5 volts

8.h-4

Vg=8voltS

vg=9 volts
Vg=15 volts

0.0

1.0

2.0

3.0

4.0

5.0

6.0

Anode Voltage
Figure 4.7 Output characteristics of 3D-IGBT.

7.0

8.0

significant voltage drop will exist across the channel and the forward current will saturate
as shown.
Table 4.0 lists the forward active mode device parameters for the 3D-IGBT and the
lateral IGBT (LIGBT) shown in Figure 4.la and 4.1b respectively. The cellular layout of
the 3D-IGBT enables it to have a considerably higher channel density and drastically lower
specific on-resistance. The specific on resistance of a power device, Ron.Area, is a very
important parameter because it determines the maximum current rating of the power device.
The specific on-resistance should be minimized because the power dissipation per unit area
is defined as

P
- I2Ron
Aand is limited by the maximum junction temperature and thermal impedance.

Table 4.1 Forward Device Characteristics

Device

A m (mm2)

3DIGBT

.46

LIGBT

.46

Channel Density (cm/cm2 )

Ro,,(n)

R d ~ n (n'mm
r
2,

The results in Table 4.1 show that for the same area, the 3d-IGBT's channel width
per unit area is more than 5 times that of the LIGBT[2] and the on-resistance is almost two
orders of magnitude lower. The on-resistance of the 3D-IGBT is comparable to vertical
devices. Presently, vertical devices are the device of choice in applications where high
current performance is required because the on-resistance of lateral devices is unacceptably
high due to the presence of the long drift region and low channel density. The low on-

0.0

"

'

2.0

"

4.0

"'

B. 0

6.0

10.0

Distance (Microns)

0.0

2.0

4.0
6.0
8.0
Distance (Microns)

10.0

(b)

Figure 4.8 Current vector plots for (a) electron current and (b) hole current.

"

.#.

0.0

" --~ -"

. - . ..--2.0
I

4.0

"

'

"

'

"

'

6.0

0.0

10.0

Distance (Microns)

Figure 4.10

Plot of electron current vectors showing injection of electrons

into P-base region after onset of latch-up.

'

0.0

2: 0

'

4.0
6.0
Distance (Microns)

. , .
8.0

10.0

l . . . l . . . , . . . r . . . l . . . I
0.0

2.0

4.0
6.0
Distance (Hi crons)

0.0

10.0

(b)
Figure 4.1 1

Hole and electron concentrations in P-base region

(a) at a forward drop of 8.0 volts (non latch-up)
and (b) at a forward drop of 1.8 volts (latch-up).

resistance of the 3D-IGBT coupled with the fact that several of them could be integrated on
the same chip with low power logic devices, opens the possibility of designing smart
power circuits which have high current requirements such as "smart" high end audio
amplifiers. The electron and hole current vectors are shown in Figures 4.8a and 4.8b
respectively. Note that the electron current flow shown in Figure 4.8a is restricted to the
inversion channel as expected. The restriction of electron flow to the inversion channel
indicates the 3D-IGBT's current flow is still controlled by the gate voltage and the device is
not in the latch-up mode. The P+ diffusion shown in Figure 4.1 is used to increase the
conductivity of the P-base region under the N+-source. This increase in conductivity
suppresses latch-up of the parasitic thyristor and allows higher lateral current flow in the Pbase region. The lateral hole current flow is clearly visible in Figure 4.8b. If the P+
diffusion is removed, the 3D-IGBT will latch-up at a forward anode voltage of 1.8 volts.
Figure 4.9 shows the potential distribution in the P-base region of the 3D-IGBT with a gate
voltage of 15 volts and an anode voltage of 8 volts. This device has the P+diffusion and is
not in latch-up. A significant potential barrier at the N+/P-base junction can clearly be seen
preventing the flow of electrons into the P-base region. In comparison, Figure 4.10 shows
the potential distribution in the &vice when the P+diffusion is not included. The parasistic
thyristor has been latched in this &vice. The potential barrier in between the P-base and
N+ regions is almost non-existent, thus allowing electrons to be injected into the P-base
region. F i g m 4.11 shows electrons being injected across the N+/P-base junction after the
onset of latch-up. Figures 4.12a and 4.12b compare the electron concentration in the Pbase region directly under the N+-source, before and after the 3D-IGBT has latched. AS
stated earlier, when the device goes into latch-up mode, the current can no longer be
controlled by the polysilicon gate.
4.4 Summary
Simulations of the forward active and forward blocking modes of the 3D-IGBT
have been performed. For the forward active operation, results indicate that the sidewall
inversion channel forms when approximately 5 volts are applied to the gate, and with this
gate voltage maintained, appreciable current flow begins to flow when the anode is forward
biased by more than 0.7 volts. The P+ implant adjacent to the N+-source was shown to
effectively control the onset of latch-up. The on-resistance of the 3D-IGBT was shown to
be almost two orders of magnitude lower than a lateral IGBT consuming the same silicon
area. The lower on-resistance results in a considerably higher current rating for the 3DIGBT device. The 3D-IGBT's forward blocking mode was also simulated and results

indicated high internal electric field peaks due to the structure's geometry. Several
improvements will be investigated to minimize these effects and increase the breakdown
voltage of the device. Although initial simulation results indicate the 3D-IGBT has the
potential to offer several improvements over existing IGBT designs, additional simulations
will be performed to optimize device parameters.

4.5

References

1.

TMA PISCES-2B Two-Dimensional Device Analysis Program, Version 8908,

Technology Modelling Associates, Inc., February 15, 1989. Copyright 1989.

2.

M.R. Simpson, P.A. Gough, F.1 Hshieh, and V. Rumennik, "Analysis of the
Lateral Insulated Gate Transistor" ,1985 IEDM Technical Digest, p. 740,
December 1985.

CHAPTER 5
PROCESS DEVELOPMENT
5.1 Introduction
The 3D-IGBT utilizes selective epitaxial silicon to form a top contacted anode and
still retain the cellular structure of vertically oriented devices. The 3D-IGBT , unlike other
fully integrable power devices, exploits the merits of cellular structure to increase its
packing density and thus reduce its on-resistance per unit area. In this chapter, the
advantages of the cellular layout structure compared to the linear structure will be
discussed. The linear layout structure is typically employed in lateral designs such as the
lateral insulated gate bipolar transistor (LIGBT).[l] A discussion of packing density,
device transconductance, and unit cell optimization will also be presented. Finally, an
optimized self-aligned process and results of feasibility experiments will also be discussed.
5.2 Cellular Layout
A cellular layout utilizes vertical current flow to avoid one of the major problems
associated with lateral devices. Lateral devices make poor use of active area silicon due to
the complex metallization schemes they require and the existence of a lateral drift region for
supporting large blocking voltages. A vertical structure eliminates the lateral drift region
because the blocking junctions are arranged such that the breakdown depletion regions
extend perpendicular to the surface of the device. Also, the metallization is simplified by
placing one very large current carrying contact on the backside of the device. Moving the
drain of a power MOSFET or the anode of an IGBT to the backside of the wafer eliminates
the need for a complex interdigitated layout of three electrodes on the top surface.
The introduction of polysilicon in the 1970's as a gate electrode allowed the
development of the self-aligned DMOS structure shown in Figure 5.1. In this device, the
n+-source regions are self-aligned to the polysilicon gate. Metallization is simplified in this
structure because the gate is easily buried under a layer of oxide, leaving only the source
regions to be contacted. Although vertical structures can only be used to fabricate discrete
devices, the trade-off of more efficient use of active area silicon is more attractive in some
cases.

Source

Polysilicon
gate

Gate
oxide
I

Source

n- epilayer

n + substrate
(100)

rain
metallization

Drain

Figure 5.1 Self-aligned DMOS structure utilizing buried polysilicon gate.[2]

The device structure illustrated in Figure 5.1 is referred to as "cellular" because

when implemented in a high-current configuration, it is just one of several thousand cells in
parallel. One of the most popular cellular layouts is the hexagonal cell structure or
HEXFET shown in Figure 5.2. The allowance for a lateral drift region during forward
blocking operation is eliminated because the junction breakdown occurs in the bulk of the
device. Bulk breakdown allows for a closer packing of current carrying cells and therefore
improves the overall current conduction of the device. Packing density is a figure of merit
which describes how efficiently the active area silicon is being utilized in a power device
design. Packing density is defined as the power device gate width per unit active area and
is related to the device transconductance.
As noted previously, the IGBT is a combination device consisting of both a
MOSFET portion and a BJT portion. The packing density directly influences the
transconductance of the MOSFET portion of the IGBT. This is very important because the
MOSFET provides the base drive current for the bipolar portion of the IGBT. The
transconductance of the MOSFET measures the sensitivity of the anode current to the
changes in the gate voltage of the IGBT, and is defined as

The transconductance of the IGBT is larger than for a power MOSFET alone because it is
also influenced by the gain of the wide-base pnp bipolar transistor portion of the IGBT.
The gain apnp
is typically 0.5 and therefore the IGBT's transconductance will be larger by
a factor of 2 compared to a power MOSFET with equal aspect ratio

For a given gate

bias, the transconductance is dependent on the gate oxide thickness through Cox, the gate
width Z and the channel length L.Device voltage ratings generally dictate the gate oxide
thickness. Due to the difficulty controlling the double diffused channel length, LC,for
lengths less than 1.5 microns, the gate width is typically the device parameter used to

optimize the transconductance. Therefore, by increasing the packing density G, the

transconductance of the IGBT can be correspondingly increased.
Generally speaking, the packing density of lateral devices such as the LIGBT is
much less than a vertical device with a cellular layout. Figure 5.3 illustrates the large
amount of active area silicon consumed by the lateral drift region of the LIGBT. The
LIGBT utilizes a linear or interdigitated layout and has a packing density of

Gate
-bonding
pad

Figure 5.2 HEXFET cellular layout configuration for high current

applications.[2]

Sources

Figure 5.3 Interdigitated layout of insulated gate bipolar transistor.[2]

x=s+b=a

The packing density is maximized by minimizing the width of each cell denoted by the
dimension a. The maximized packing density for the LIGBT is

and is limited by the fixed dimension b. In the case of the LIGBT, the dimension b is the
lateral drift region distance and is governed by the desired breakdown performance of the
device.
The cellular layout of the HEXFET provides for a much higher packing density.
The hexagonally packed cells enable a more efficient use of the active area silicon because
an allowance for a lateral drift region is unnecessary. The packing density of the HEXFET
is defined as

where 6s is the total gate width per unit cell and a is the cell spacing. The packing density
can also be written as

where b is shown in Figure 5.4 and a=b

maximized when

+ f l s . The HEXFET packing density is

giving

The cell spacing a of the HEXFET is considerably smaller than that of a lateral device such
as the LIGBT, and therefore the packing density of the cellular structure is far superior.

. . ;;2,.;

qfJ)j

'

II

(5.
..'
...

.':;J;4'.

V..

.
..

- / 2 q m

\\<

-A'

\:...lL .

,JJ.

. . . Y....
\:u;A'.

Figure 5.4 Cellular configuration and critical dimensions of HEXFET .[2]

5.3 3D-IGBT Cellular Design

One of the key features of the 3D-IGBT is its retention of a cellular structure even
though it is fully integrable. As stated earlier, until the development of the 3D-IGBT, the
trade-off was made between full integrability and increased packing density. To have one,
the designer would have to compromise the other.
A cellular structure for the 3D-IGBT is achieved by placing rectangular shaped n+
regions across long narrow trenches. This scheme allows the trench spacing to be
minimized without consuming the area for forming the P-base/n+-source short circuits
needed for device operation. The top surface anode contact is formed by selectively
growing epitaxial silicon in the trench. The selective silicon is isolated from the polysilicon
gate by a thick seed window oxide thermally grown on the surface of the gate. Figure 5.5
is an isomemc view of the 3D-IGBT in its high-current "cellular" configuration. Note the
cell width, a, is determined by both the trench width b, and the trench to trench spacing s.
A view of the mask layout for the high-current IGBT shown in Figure 5.6 also indicates
that the device has a square cell configuration. The maximized channel density for the 3DIGBT is therefore

as was the case with the HEXFET. However, unlike the HEXFET and most other vertical
devices, the 3D-IGBT is not hindered by the parasitic "JFET" region during forward
conduction. The JFET region, shown in Figure 5.4, contributes significantly to the onresistance of the IGBT because as the unit cell size is reduced, more and more carriers are
squeezed into a smaller area due to the pinching of the conductive path by the DMOS
depletion regions. The 3D-IGBT eliminates the parasitic JFET region and therefore, the
cell width, a, is governed only by the process technology used to define the trench and the
ability to selectively grow silicon from a narrow trench.
A closer look at the mask layout in Figure 5.6 indicates that the array structure is
simply a number of independent 3D-IGBT devices in parallel. Development work
described in this chapter and the next involved only one of these device cells. A seven level
mask set shown in Figure 5.7 was designed to investigate the feasibility of the top
contacted, cellular IGBT structure. Device performance of a single cell was determined and
the results extrapolated by assuming uniform current flow in each device of the array

Figure 5.7 Mask layout for fabrication of 3D-IGBT.

configuration. The mask set enabled the investigation of trench etching techniques,
polysilicon gate formation, selective epitaxial growth of silicon from long narrow trenches,
and RIE sidewall etch damage reparation.
Figure 5.8 is a close-up view of the mask layout and corresponding cross-section
of the 3D-IGBT device cell. The figure illustrates that the cell width of the 3D-IGBT is
made smaller by reducing the trench width, b, or by reducing the trench to trench spacing,
s/2. In the next section, a self-aligned seed window process is presented which facilitates a
much easier reduction of the 3D-IGBT trench width and therefore provide a much higher
packing density compared to the original structure proposed in chapter 3.
5.4 Self-Aligned Seed Window
The 3D-IGBT process described in chapter 3 incorporates masking steps to define
the polysilicon gate and the selective epi seed window. When unit cell reduction is
performed to increase packing density, the process in chapter 3 is limited by its inability to
define extremely small features (c1Opm) in the bottom of the trench, and by mask
alignment tolerances such as the gate definition over the trench. Figure 5.9 illustrates the
advantages of a self-aligned 3D-IGBT device compared to the originally proposed structure
having the same seed window dimensions. By using reactive ion etching (RIE) sidewall
spacer techniques, the polysilicon gate and seed window oxide are formed using no
masking steps. In the self-aligned structure, the polysilicon gate and seed window overlap
regions are eliminated resulting in an immediate reduction in the unit cell width compared to
the original 3D-IGBT structure with identical seed window area. The trench width of the
self-aligned device is easily varied photo-lithographically; however, a lower limit on the
trench width based on the selective epitaxial silicon growth parameters and forward
blocking performance must be acknowledged.
During forward blocking operatio11 of the 3D-IGBT, the oxide isolating the
polysilicon gate from the selective epi material also supports a very large voltage drop.
Therefore, based on the strength of this oxide, and the forward blocking performance
desired, oxide thicknesses in the range of 0.5 to 2.0 microns should be used. A lower limit
is placed on the trench width because the growth rate of selective epitaxial silicon from
extremely narrow seed windows (c10 pm) is reduced significantly. Figure 5.10a
illustrates that as the seed window width decreases, slower growth rate (110) facets
consume a larger proportion of the selective epi growth front. At some minimum seed
window width, the facets will consume the entire growth front and terminate on each other.
When the facets terminate, trench widths of this size and even small can still be utilized.

N -- Substrate

Figure 5.8 Close-up view of mask layout for 3D-IGBT device cell.

N -- Substrate

I
I
I
I

Tfifllq

+Seed Window

I
I
I
I
I
I

Width

N - Substrate

Figure 5.9 (a) Originally proposed 3D-IGBT device with overlap region,
(b) Self-Aligned 3D-IGBT with overlap region eliminated.

(a)

Before CMP

After CMP
(b)
Figure 5.10 (a) Effect of seed window dimensions on SEG faceting, (b) Effectiveness
of CMP to eliminate adverse facet formation due to narrow seed window

By continuing to grow the selective epi material, albeit at a much slower rate, until the
trench has been filled, and then chemically/mecl~anicallypolishing back to the field oxide
layer as shown in Figure 5.10b, very small seed windows and thus very small trench
widths can be achieved.
The processing steps for the self-aligned 3D-IGBT are illustrated in Figure 5.11.
The process utilizes sidewall spacer techniques to form a sidewall contacted polysilicon
gate and a self-aligned seed window oxide. The polysilicon gate is buried under the seed
window oxide and extends around the inner portion of the rectangular trench periphery.
The polysilicon gate is contacted at one end of the trench as shown in Figure 5.6. This
contacting scheme eliminates the need to align the gate to the trench edge using a very tight
tolerance mask alignment.
Self-aligned 3D-IGBT Process
Step 1:

After the P-base and n+-source regions are implanted and driven into
an n-type (100) silicon substrate, the PC latch-up regions are
&fined, implanted and driven in.

Step 2:

A 4 micron deep trench is formed by using reactive ion etching

(RIE) with Freon 115 as the etch gas. A very thin 200 A
sacrificial oxide is grown, then removed followed by the growth of
a thin 1000 A gate oxide.

Step 3:

5000 A of plysilicon is deposited and then doped with

POCL3. The plysilicon material is etched using RIE to foxm the
sidewall contacted gate.

Step 4:

The sidewall polysilicon gate is thermally oxidized to foxm a

3000 A oxide layer on its surface. 1500 A of polysilicon
is deposited and then totally consumed by a 3000 A thermal
oxidation. The oxide layer is etched using RIE to foxm the selfaligned seed window.

Step 5:

Selective epitaxial silicon is grown from the 4 micron deep trench

using the bottom, exposed silicon substrate as a seed. The anode

Step 4

N -- Substrate

I Step 5

N -- Substrate

N -- Substrate

Step 6

Figure 5.1 1, continued

region of the 3D-IGBT is formed by implanting the selective epi

layer with boron and then driving it in.
Step 6:

N+-SourceIP-body, gate and anode contact openings are formed in

the oxide. A1-Si metallization is performed.

To verify the structural feasibility of the self-aligned process, a non-testable 3D-IGBT was
fabricated. Non-testable in this case meant that contact metallization to the buried
polysilicon gate was not attempted because the polysilicon contact mask was unavailable.
Fabrication of the self-aligned 3D-IGBT began by thermally oxidizing an n-type
(100) 10-20 Q-cm silicon wafer in a wet 0 2 ambient for 60 minutes. The resulting oxide
layer was 6,000 A. The P-base region was formed by wet etching the initial oxide with
buffered hydroflouric acid (BHF) followed by a boron implant dose of 2x 1014~ r nat- 35
~
keV. The P-base implant was driven-in at 1100C in a dry O2 ambient for 30 minutes. The
resulting oxide thickness in the P-base implant region was 1000 A. The n+-source region
was formed by wet etching the P-Base oxide with BHF followed by an arsenic implant
dose of 5x1015cm-2 at 35keV. The n+-source was driven-in at 1000C in a wet 0 2 ambient
for 25 minutes. The resulting oxide thickness in the n+-source region was 2,500 A. Using
1350 positive photoresist as a mask, the trench was etched with the aid of the Drytek
DRIE-100 etcher and Freon 115 as the etch gas. Assuming a silicon etch rate of 333.3
A/min.. the wafer was etched for 120 minutes at a forward power of 750 watts and a
reverse power of 60 watts. A thin 1000 gate oxide was formed along the trench sidewall
by oxidizing the wafer in a dry 0 2 ambient at 1100C for 55 minutes.
Following the formation of the gate oxide, a 5000 A layer of polysilicon was
conformally deposited on the wafer. The silane flowrate was 70sccm and the temperature
used was 550C. The polysilicon layer was doped using POCL3 at 950C for 15 minutes
to obtain a sheet resistance of 15.6 ohms per square. The phosphosilicate glass (PSG)
layer formed during the POCL3 deposition was removed by a quick 15 second BHF dip.

The sidewall polysilicon gate was formed by reactive ion etching the doped polysilicon
layer. The etch time was 10 minutes using Freon 115 and a forward power of 750 watts.
Figure 5.12 is an SEM of the trench following the RIE of the polysilicon layer. The
residual polysilicon gate material is easily seen adhering to the trench sidewall. The wafer
was then oxidized in a wet O2 ambient for 20 minutes at 1100C to form a 3000 A oxide
layer on the polysilicon gate. The selective epi seed window was opened by reactive ion
etching the oxide layer using Freon 115 and a forward power of 750 watts for 30 minutes.

icon

Figure 5.12 SEM of trench sidewall following RTE of polysilicon layer.

Field Oxidc

--

Figure 5.13 SEM of trench sidewall and bottom single crystal silicon
just prior to selective epitaxial silicon growth.

The oxide etch rate using Freon 115 as the etch gas is assumed to be 100 I$/min.. Figure
5.13 is an SEM of the trench region following the RIE of the oxide layer. With the darker
portion of Figure 5.13 being single crystal silicon, the contrast clearly indicates that only
the oxide in the bottom of the trench has been completely etched. The sidewall and field
regions are still protected by the oxide layer. Following a thorough wafer clean, the trench
was filled by growing approximately 10 microns of selective epitaxial silicon using the
exposed substrate at the bottom of the trench as the seed. The selective epitaxial silicon
was grown in a Gemini-I1reactor at 40 Torr and 970C.
Fabrication results indicate the successful formation of the sidewall contacted
polysilicon gate and self-aligned seed window oxide. The SEMs shown in Figures 5.14
and 5.15 illustrate the complete isolation of the polysilicon gate and the feasibility of a
maskless seed hole definition process. Growth of selective silicon out of the 4 micron deep
trench is verified by Figures 5.16 and 5.17. Field oxide thinning near the edge of the
trench, as shown in Figures 5.15 and 5.18, was a very critical processing concern because
a direct short between the anode and the n+-sourceof the 3D-IGBT results. The problem
of oxide thinning was caused by a degradation of the field oxide near the trench edge due to
poor photoresist profile definition and enhanced photoresist etching during the long trench
RIE step. As illustrated in Figure 5.19, a less than 90' photoresist profile exposes the
underlying oxide layer to the reactive ion etchant because the thinner regions of the
photoresist masking layer are etched away. The resulting field oxide profile at the corner of
the trench is tapered and subsequent RIE steps to form the sidewall gate and self-aligned
seed window further degrade the oxide until none is left.
To solve the problem of oxide degradation along the trench edge, both positive and
negative photoresist masking layers were investigated and various RIE etch gas and power
combinations were evaluated. AZ 1350 positive resist and KT747 negative resists were
evaluated to determine which would provide the optimum edge profile of 90 at the trench
edge. The RIE parameters for this evaluation were as follows:
Etch gas:
Flowrate:
Pressure:
Power:

Freon 115
95 sccm
285 mTorr
750 watts forward

Based on the edge damage allowed by the negative resist shown in Figure 5.20, the 1350
positive photoresist was deemed the most effective masking layer for the underlying oxide.

Figure 5.14 SEM cross-section of self-aligned poly gate and seed window.

Figure 5.15 SEM of sidewall poly gate.

Figure 5.16 SEM showing selective silicon completely filling 4 micron deep trench.

Figure 5.17 SEM showing SEG coming out of trench and shorting to n+- source.

Short

Short

N--SEG

-----------------

N - Substrate
---

Figure 5.18 Anode to &-source short caused by oxide thinning.

Before R E

After R E

Figure 5.19 (a) Poor photoresist step profile, c70; (b) ideal photoresist resist step
profile, 90';

Figure 5.21 illustrates the excellent protection provided by the positive resist compared to
the negative resist. Note the absence of edge damage following the use of the positive
resist. Although the 1350 resist adequately masks the oxide from R E damage during the
long trench etch step, an optimum 90" step profile was not achieved with the standard
photoresist parameters of
4000 rpm, 30 sec.

30 rnin. prebake @ 90C

7.5 sec. exposure
30 min. postbake @ 120C
Through several fruitful discussions with colleagues in the Purdue solid state laboratory, it
was determined that a modified prebake step and elimination of the postbake step provided
a near optimum photoresist step profile. The modified parameters were
4000 rpm, 30 sec.
30 rnin. prebake @ 110C

30 sec. exposure
No postbake
The elimination of the postbake step prevents unwanted reflow of the 1350 resist.
Photoresist reflow causes the step profile to become considerably less than the desired 90'.
Various R E etch gas combinations and power settings were evaluated to minimize
oxide degradation at the trench edge. Initially, the silicon substrate area to be etched by the
RIE was defined by patterning the field oxide layer with 1350 photoresist and then wet
etching the oxide layer with BHF. The edge profile of the oxide layer following the wet
etch was about 60'. To obtain a better oxide edge profile, a combination R E process was
investigated. Due to the excellent anisotropic etching properties of Freon 116 on SiO2, it
was believed that a two step process of etching the oxide layer with Freon 116 followed by
the trench etch using Freon 115 would result in an optimum edge profile. The parameters
for the 2-step process were as follows:
0;ide etch:

Etch gas: Freon 116

Flowrate: 150 sccm
Power: 100 watts (forward)

Figure 5.20 SEM of trench sidewall following R E etch: negative resist .

Figure 5.21 SEM of trench sidewall following R E :positive resist.

Etch rate: 50 hrnin.

Trench Etch: Etch gas: Freon 115
Flowrate: 95 sccm
Power: 750 watts (forward)
Etch rate: 333 b i n .
The results of the combination process were disastrous. Figure 5.22a is an SEM of the
trench following the combination etch process. Apparently, using Freon 116 followed by
an immediate RIE step using Freon 115 causes severe surface roughness in the bottom of
the trench. The roughness was probably caused by the formation of a polymer layer on the
silicon surface. Polymer layers are commonly encountered when Freon 116 etches single
crystal silicon. Figure 5.22b is an SEM of the trench region following removal of the
oxide layer using BHF and R E of the silicon substrate using Freon 115 at 750 watts
forward power.
5.5 Post-Trench R E Sidewall Cleaning
The vertical orientation of the 3D-IGBT is achieved by forming the MOS transistor
along the sidewall of a trench which has been etched using R E . Sidewall MOS devices are
challenging to develop due to the excessive amount of sidewall etch damage induced by
reactive ion etching.[4] S ub-surface interstitial defects, contamination by heavy metals,
and the formation of surface residues are some of the major problems encountered. The
performance of the sidewall MOS transistor, and hence, the entire 3D-IGBT device, is
severely compromised if the etch damage is not conteracted. Several techniques such as
high temperature anneals, wet etching, sacrificial oxidation, and surface gettering are
employed as post-trench RIE sidewall surface cleaning processes. In this section, results
of a study to determine the effectiveness of these techniques are presented.
Sidewall trench capacitors were designed to evaluate the effectiveness of TCA oxide
as a gettering mechanism, and sacrificial oxide layers along the trench sidewall as a surface
cleaning technique to reduce sub-surface defects. The sidewall capacitors also.served as a
means to evaluate the performance of the phophorous doped polysilicon gate which was
formed using sidewall spacer techniques. Although Figure 5.15 verified the formation of
the self-aligned polysilicon gate, electrical operation of the gate was not confirmed at that
time. The sidewall capacitor, shown in Figure 5.23a, was formed along the sidewall of a
trench etched into the die border of the mask set shown in Figure 5.7a. The die border was

(b)
Figure 5.22 SEM of trench following (a) combination FR 1 15. FR116 etch
and (b) wet etch/ Freon 1 15 etch.

utilized in this fashion because a fairly long trench was needed to obtain capacitances
greater than 10 pF. The dimensions of the die border were 10,200 pm x 10,200 pm and
the trench depth was 6.5 pm giving a total area of 2.65~10-3cm-2. Figure 5.23b shows
the small 100 pm xlOO pm polysilicon contact pad in the upper right hand portion of the
die border. The contact pad was placed on a 4000 A field oxi& layer to minimize parasitic
capacitance during measurements.
As stated earlier, the effectiveness of TCA oxide as a gettering mechanism and
sacrificial oxidation as a means to reduce sub-surface defects was investigated using the
sidewall capacitors. Four wafers were used in the study with each wafer containing 4
capacitors for standard C-V and leakage current measurements and an additional 25
capacitors for oxide breakdown measurements. The capacitors were fabricated on 10-20
R-cm, p-type (100) silicon wafers. All four wafers were cleaned in a solution of H2S04H202, rinsed, and then oxidized in a wet 0 2 ambient at 1100C to form a 4000A field
oxide. The oxides of all four wafers were patterned and etched using 1350 positive
photoresist as a mask. A 6 micron deep trench was etched using the Drytek-DRIE 100
system with Freon 115 as the etch gas at 750 watts forward power. To evaluate the
effectiveness of the two sidewall "cleaning" techniques, the four wafers were now
subjected to different processing steps.
The fust wafer was oxidized in dry 0 2 at 1100C to form a l000A gate oxide. A
5000A polysilicon layer was then deposited on the wafer at 550C using a silane flowrate
of 70 sccm. The plysilicon layer was doped n-type using POCL3 at 950C for 15
minutes. The sidewall polysilicon electrode was formed by reactive ion etching the
plysilicon layer for 10 minutes using Freon 115 at a forward power of 750 watts. This
wafer served as the baseline or control wafer against which all the other wafers were
compared.
The second wafer was used to investigate the sacrificial oxide. The wafer was
oxidized in a wet 0 2 ambient at 1000C for 5 minutes to form a 500A oxide layer. The
oxide layer was then removed using BHF. The wafer was then subjected to the same
procedure as the control wafer.
The third wafer was oxidized in a l%TCA ambient at 1100C to form a 100OA gate
oxide. The polysilicon layer was then deposited and etched in the same way as the control
wafer.
The fourth wafer was oxidized in a wet O2at 1000C for 5 minutes to form a 500A
oxide layer. The oxide layer was removed using BHF. The wafer was then oxidized in a

Gate oxide

P - Substrate

Top surface
polysilicon
contact

(b)

Figure 5.23 (a) Trench MOS capacitor with gate formed by RIE
sidewall spacer technique;(b) Die border used for trench
capacitor with small top surface contact.

1% TCA ambient at 1 100C to form a ~OOOA

gate oxide. The wafer was then subjected to
the same procedure as the control wafer following gate oxide formation.
The wafers with gate oxides grown in dry 02 ambient had an actual oxide thickness
of 1lOOA and the wafers grown in the 1% TCA ambient had an actual oxide thickness of
1300A.
Two additional wafers were fabricated as a means of comparing the TCA and nonTCA oxide. The two wafers were not subjected to the RIE trench etch but were instead
cleaned and then oxidized to form the gate oxide. The first wafer was oxidized in 1% TCA
at 1 100C and the second in a dry ambient at 1 100OC. Both wafers were then subjected
to the same procedures as the control wafer following gate oxide formation.
5.5.1 Results
In Figure 5.27, the C-V data of the trench capacitors indicates a 2 volt shift in the
flatband voltage of the TCNSac Ox capacitor. This shift is most likely due to the presence
of fixed charge in the gate oxide. The gradual rise in the inversion capacitance of Figure
5.27 suggests a significant amount of mobile ions on the surface of the wafer. If the
positive charged ions are not counteracted, then a low frequency-like response will result.
This low frequency-like response was observed and counteracted by biasing the capacitors
into accumulation and holding the negative bias constant for 5 minutes. The accumlation
bias attracted the positive ions to the negatively charged gate. Dry nitrogen was then blown
on the wafer to "freeze" the surface charges in place and the capacitor was swept from
accumulation through depletion and into inversion. A significant decrease in the inversion
capacitance was observed using this method but as Figure 5.27 illustrates, their still
remained a small amount of surface conduction. The control wafer appeared to be
relatively immune to this problem because its inversion capacitance remained flat but the
wafers with TCA oxide or the sacrificial oxide showed a definite rise in their inversion
capacitance. The higher inversion capacitance of the TCNsacrificial oxide capacitor
compared to that of the control device is consistent with that of the TCA only and sacrificial
oxide only capacitors of Figures 5.25 and 5.26. The higher inversion capacitance suggests
that the "cleaning" steps may be creating additional problems.

-10

-8

-6

-4

-2

Gate Bias

Figure 5.24 TCA vs. Non-TCA Oxide (Planar CAPS)

10

1.2

-10

-8

-6

-4

-2

No TCAINo Sac Ox
SacOx

Gate Bias

Figure 5.25 Baseline vs. sacrificial oxide

10

---t--

-10

-8

-6

-4

-2

TCA

Gate Bias

Figure 5.26 Baseline vs. TCA Oxide

10

-10

-8

-6

-4

-2

Gate Bias
Figure 5.27 Baseline vs. TCA & Sacrificial Oxide

10

Table 5.1 Breakdown Field and Leakage Currents

GrouD
Control
Sacrificial Oxide
TCA Oxide
TCAjSacrificial Oxide

l%muml
4.09
4.27
5.81
6.08

2-1

4.32
4.08
4.08
4.66

Table 5.1 lists the average breakdown field E, and the gate oxide leakage current for
each of the four wafers. The leakage current was measured at a gate bias of 5 volts and
was essentially the same for all four wafers.
The strength of the gate oxide is expressed in terms of the average breakdown field.
The breakdown field was computed by dividing the voltage at which irreversible
breakdown of the oxide occured by the corresponding gate oxide thickness. Each wafer
contained 25 capacitors designated for breakdown testing only. Table 1 indicates that the
dielectric strength of the control capacitor was less than the other three "treated" wafers.
Figures 5.28 through 5.31 show a dramatic improvement in the breakdown strength for the
oxides grown in a 1% TCA ambient compared to those grown in a dry 0 2 ambient. Where
none of the non-TCA oxides had breakdown fields above 6 MV/cm, 70%of the oxides on
the TCAfSacrificial oxide wafer had breakdown fields above 6 MV/cm. Each wafer
contained 25 capacitors designated for breakdown testing only. Improved dielectric
strength is characterized by a reduction in the number of defects per unit area in the oxide.
In terms of device reliability and performance, the reduced oxide defect density leads to far
fewer low-field breakdowns. Low-field breakdown is one of the dominant failure modes
of MOS devices.
Although an improvement was observed in the dielectric strength of oxides treated
with TCA, the negligible effect of the sidewall treatments on the C-V characteristics suggest
little is gained by employing such treatments. As a source of chlorine, the TCA should
have neutralized any mobile sodium ions or other impurities present in the thin oxide
layers. Shenai [5] made parametric measurements on low on-resistance UMOSFETs and
concluded that oxidation based post-trench RIE sidewall surface cleaning processes have
negligible impact on overall device characteristics. In fact , other studies have reported a
degradation in device performance when a chlorine source such as TCA is introduced.[6]
In these studies, the presence of TCA actually increased the total flatband shift and slightly
increased the interface-trapped charge. These results correlate well with the data in our
study. Hamarnoto [7] used deep level transient spectroscopy (DLTS) to investigate

100

Control

No TCA. No Sac Ox

Breakdown Field WVlcm]

Figure 5.28 Breakdown field for control capacitor.
100

Sac Ox, No TCA

80

..

60 .-

Breakdown Field [MV/cm]

Figure 5.29 Breakdown field for sacrificial oxide capacitor.

VV

TCA, No Sac Ox
80

a-

60..

Breakdown Field [MV/cm]

Figure 5.30 Breakdown field for ?'CA capacitor.

TCA, Sac Ox

Breakdown Field TMVIcml

Figure 5.31 Breakdown field for TCA/Sacrificial Oxide capacitor.

sidewall damage in a silicon substrate. The investigation found that three kinds of deep
level traps are introduced onto the sidewall following RIE. The energy levels of the traps
are E, - 0.30 eV, Ev+ 0.6 eV, and E,+ 0.66 eV. Furthermore, the study concluded that
although not all the damage was removed, the Ev + 0.6 eV trap which served as a
generation-recombination center is removed by annealing at temperatures above l W C .
The results suggest that by simply growing the gate oxide in a dry 0 2 ambient at 1 10O0C,a
significant reduction in the sidewall damage will result due to the elimination of one of the
major generation-recombinationcenters.
5.6 Sidewall MOSFET
The next step in the development of the 3D-IGBT was to verify the feasibility of a
vertical, sidewall contacted UMOSFET shown in Figure 5.32. The sidewall MOSFET
supplies the base current drive for the 3D-IGBT and therefore is very important in the
normal operation of the device. Parameters such as transconductance, on-resistance, and
source to drain leakage current were measured and compared to comparable UMOSFET
devices found in the literature.
Using the mask set shown in Figure 5.7, fabrication began by implanting the
backside of an n-type (100) silicon wafer with an arsenic dose of 5xl015cm-2 to form the
drain. The P-base region was formed by implanting the top surface with a boron dose of
2x1014 cm-2 at 35 keV. The P-base implant was driven-in at 1100C in a wet O2 ambient
for 30 minutes. The n+-sourceregion was formed by implanting with an arsenic dose of
5x1015cm-2at 35keV. The arsenic implant was driven-in at 1000C in a wet 0 2 ambient
for 25 minutes. A 4 micron deep trench was etched using the Drytek DRIE-100 dry etcher
and Freon 115 as the etch gas at a forward power of 750 watts. A thin, 1 0 a gate oxide
was formed along the sidewall by thermally oxidizing the wafer in a dry O2 ambient for 55
minutes. Following the gate oxide formation, a 5000A layer of LPCVD polysilicon was
deposited on the wafer using a silane flow of 70 sccm and a temperature of 550C. The
p l ysilicon was POCL3 doped to obtain a sheet resistance of 16 Wsquare. The polysilicon
layer was then patterned using 1350 positive photoresist and etched. Figures 5.33 and
5.34 show the trench region following the RIE etch of the polysilicon layer. Note the
conformal coverage of the polysilicon along the trench sidewall in Figure 5.34. The wafer
was metallized to form electrodes for the source and gate regions and then tested.

Source

Source

N -- Substrate

~ 6 i n
Figure 5.32 UMOSFET used to invesitgate quality of EUE sidewall.

Figure 5.33 Top view of 3D-IGBT cell following R E of polysilicon.

I
I

5.6.1 Device Characteristics and Discussion

UMOSFETS with a total gate width of 200 pm were fabricated and tested. An
HP4145 semiconductor parameter analyzer was used to test 23 devices for threshold
voltage, transconductance, on-resistance and source to drain leakage current. Figure 5.35
is a typical I-V characteristic of the UMOSFET. It should be noted that although Figure
5.35 indicates a breakdown voltage of approximately 100 volts, the ideal breakdown of the
device is in the 300 volt range. Field rings for junction termination were not utilized in the
fabrication process, therefore it is highly probable that the breakdown shown is due to very
high surface fields.

Table 5.2 UMOSFET Characteristics

Paramete r
VTH(volts)
g,(mS)
Ron(Q)
Is/D(PA)

Mean

Max.

Mh

3.1
1.2
1023.3
1.094

6.6
1.8
3080
9.302

-11

**

0.6
467
0.0 12

60 mS/cm
1.63 Q-cm

**

Table 5.2 lists the measured threshold voltage VTH,maximum transconductance g,,
on-resistance Ron, and source to drain leakage current IsD for the 4 micron deep
UMOSFET. Results indicate the on-resistance is of the UMOSFET is influenced
significantly by the resistance of the channel. Higher transconductance measurements
resulted in correspondingly lower on resistance values for the entire device. As the
transconductance of the UMOSFET increases, the conductivity of the inversion channel
increases also. The on-resistance of the UMOSFET is defined as

Rchmel is the resistance of the inversion channel, Rsouwis the resistance due to the n+source diffusion, Rbuk is the resistance of the bulk silicon substrate, and RKcumis the
resistance of the accumulation layer shown in Figure 5.3 1. The channel resistance can be
written as

Tren

Figure 5.34 SEM of conformal polysilicon coverage following RE.

Figure 5.35 Output characteristics of UMOSFET.

Rchannel =

P ~COX
s

(VG-VT)

(5.8)

where the denominator in equation 5.8 is the transconductance of the UMOSFET.[8]

Table 5.2 also indicates that the maximum transconductance value was 1.8~10-3s.
Normalized to the total width of the UMOSFET gate, the transconductance can be written
as 90 mS/cm. The normalized transconductance compares very favorably with
contemporary UMOSFET transconductance values which are typically 100 mS/cm.[9][ 121

5.7

References

1.

D.N. Pattanayak, A.L. Robinson, T.P. Chow, M.S. Adler, B.J.Baliga and E.J.
Wildi, %-Channel Lateral Insulated Gate Transistors: Part I - S teady-S tate
Characteristics,"IEEE Trans. Electron Devices, ED-33, pp.1956-1962, 1986.

2.

D.A. Grant and J. Gowar, Power MOSFETs - Theory and Applications, John
Wiley and Sons, New York, Chapter 1, 1989.

3.

M.L. Tarng, "On-resistance Characterization of VDMOS Power Transistors,"

IEDM Technical Digest, Abstract 17.7, pp.429-433, 1981.

4.

C.J. Petti, J.P. McVittie and J.D. Plummer, "Characterization of Surface Mobility
on the Sidewalls of Dry-etched Trenches," IEDM Technical Digest, Abstract 5.6,
pp.104-107, 1988.

5,

K. Shenai, W. Hennessy, M. Ghezzo, C. Korman, H. Chang, V. Temple and M.

Adler, " Optimum Low-voltage Silicon Power Switches Fabricated Using Scaled
Trench MOS Technologies,"IEDM Technical Digest, Abstract 32.3, pp.793-797,
1990.

6.

R.G. Cosway, "Effect of Oxidation Ambient on the Electrical Properties of Thin

Silicon Oxide,"Journal of the Electrochemical Society, Vol. 132, No.12, pp.30523054, 1985.

7.

T. Hamamoto, "Sidewall Damage in a Silicon Substrate Caused by Trench

Etching,"Applied Physics Letters, Vol. 58, No.25, 1991.

8.

S.C. Sun and J.D.Plummer, "Modeling the On-resistance of LDMOS, VDMOS

and VMOS Power Transistors," IEEE Trans. Electron Devices, Vol. ED-27,
pp.356-367, 1980.

9.

T. Ohno, S. Matsumoto and K. Izumi, "An Intelligent-Power IC Fabricated by

SIMOX Technology," IEEE International SOI Conference Proceedings, pp.164165, 1991.

10.

H.R. Chang, R.D. Black, V.A.K. Temple, W. Tantrapom and B. J. Baliga, "Ultra
Low Specific On-Resistance UMOSFET," IEDM Technical Digest, Abstract 28.3,
pp.642-645,1986.

11.

D. Ueda, H. Takagi, and G. Kano,"Deep Trench Power MOSFET with an

RonArea Product of 160 ma-mm2" IEDM Technical Digest, Abstract 28.2,
pp.638-64,1,1986.

12.

V.A.K. Temple, R.P. Love and P.V.Gray, "A 600-volt MOSFET Designed for
Low On-Resistance," IEEE Trans. Electron Devices, Vol. ED-27, No. 2, pp.343348, 1980.

CHAPTER 6
E L E m C A L EVALUATION
6.1 Introduction
In the previous chapter, several developmental milestones for the 3D-IGBT process
were presented. First, the structural feasibility of a sidewall spacer process to form a
polysilicon gate using RIE was verified. The sidewall spacer process enables the formation
of a self-aligned polysilicon gate and seed window oxide for selective epitaxial silicon
growth. Next, electrical verification of the sidewall polysilicon gate was achieved by
fabricating several sidewall contacted MOS capacitors and analyzing their C-V data. The
C-V data was also used to evaluate the quality of the sidewall gate oxide and several trench
cleaning procedures. Finally, a sidewall contacted vertical UMOSFET was fabricated,
tested and shown to be comparable in operation to several UMOSFETs reported in the
literature.
In this chapter, electrical feasibilty of the 3D-IGBT is demonstrated. Several 3DIGBT devices were fabricated using the self-aligned process described in chapter 5. DC
parameters such as the on-resistance, latch-up current and leakage current were measured
and compared to PISCES results. PISCES data is also used to demonstrate the dependence
of latch-up current on the latch-up implant offset, and to show the relationship between the
3D-IGBT output conductance and its channel length.
6.2 Device Fabrication
Three wafers were used to evaluate the electrical performance of the 3D-IGBT
device. All three wafers utilized the same basic self-aligned process described in section
5.3 with the exception of a few modifications. Wafer #1, the baseline wafer, had no latchup implant, no sacrificial oxide before gate oxide formation, and the gate oxide was grown
in a normal dry O2 ambient. Wafer #2 was processed just as the first wafer but it did
possess a latch-up implant and a sacrificial oxide before gate oxide growth. The gate oxide
of wafer #2 and all subsequent processing steps were the same as wafer #l. Wafer #3 was
processed the same as wafer #2 except for the use of 1% TCA as the ambient during the

thermal growth of the gate oxide. Each of the three wafers contained 70 active devices for
testing.
Figure 6.1 is an SEM photograph of the 3D-IGBT following selective epitaxial
growth of the anode region. Note how the selective silicon almost completely fills the
trench. Figure 6.2 is an SEM of the 3D-IGBT following the P+-anode implant, drive-in
formation of the contact windows. The plysilicon contact region at one end of the
rectangular trench enables electrical contact to be made to the sidewall plysilicon gate. As
shown earlier, the polysilicon gate is formed along the inner portion of the aench sidewalI
and is very difficult to contact when the aench is completely fdled. The polysilicon contact
region is a simple way to electrically join the top surface to the sidewall. Figure 6.3 is a
close-up view of the encircled area of figure 6.2. Note the polysilicon on the top surface
extending down and contacting the sidewall polysilicon gate. The rough material in the
upper right comer of the SEM is AI-Si metallization. Figure 6.4 is a fully metallized 3DIGBT device. Notice how there is space between the selective epi and the trench sidewall.
Due to processing difficulties, the selective epi seed window was formed using
photolithography. The polysilicon gate was self-aligned as per the process described in
chapter 5. Due to the presence of oxide in the bottom of the trench, the selective epi had to
grow laterally as well as vertically until the trench was completely filled. Chemical
mechanical polishing techniques were employed to planarize the wafer surface when
complete trench refill was desired. The planarization is necessary because the selective
silicon will rise out of the trench by the same amount of oxide overlap in the bottom of the
trench. This is identical to the growth pattern of selective silicon out of the QDI tub in
figure 3.5. Figure 6.5 is an SEM showing the complete fill of the trench following
planarization. The opening at the end of the trench near the polysilicon contact area is
necessary to ensure adequate oxide coverage over the polysilicon gate.
6.3 Electrical Verification
Fabrication of the baseline 3D-IGBT device began by oxidizing a 1-5 Q-cm, <lo>
n-type silicon wafer. The P-base region was implanted with a boron dose of 2x1014 cm-2
at 35 keV and driven in at 1100 OC in a dry O2 ambient for 30 minutes. The n+-source was
formed by implanting with an arsenic dose of 5x10'5 cm-2 at 35 keV and driven in at 1000
O C in a wet O2 ambient for 25 minutes. No latch-up implant was done. Using A21350
positive photoresist as a mask, a 5 micron deep trench was etched using the Drytek DRIE100 system with Freon 115 as the etch gas at a forward power of 750 watts. No post RIE
sidewall cleaning steps were performed. The gate oxide was formed by oxidizing the

Figure 6.1 SEG growth in 4 micron deep trench.

Figure 6.2 3D-TGBT following SEG growth and anode implant.

Figure 6.3 SEM of polysilicon along trench

sidewall and on top surface

Figure 6.4 SEM of completed 3D-IGBT device

Figure 6.5 SEM of 3D-IGBT device following CMP planarization.

wafer in a dry O2 ambient for 55 minutes to form a 1000 A thermal oxide. A 5000 A
polysilicon layer was deposited conformally using an LPCVD reactor with a silane flowrate
of 70 sccm, and a temperature of 550 OC. The polysilicon layer was doped using POCL3 at
950 OC to obtain a sheet resistivity of 15.6 ohms per square. The polysilicon layer was
etched using the RIE system to form the sidewall polysilicon gate. A very loose masking
step was used to protect a portion of the polysilicon at one end of the rectangular trench.
This is the polysilicon region shown in figure 6.1. To protect the polysilicon from the
selective epi gases during the epi growth out of the trench, a moderately thin thermal oxide
layer was grown by baking the wafer at 1 100C for 18 minutes in a wet 0 2 ambient. A
conformal oxide layer was formed by first depositing a 1500 A layer of polysilicon and
then totally oxidizing it. The fmal oxide thickness was approximately 3000 A.
The seed window for selective epi growth was formed by aligning a seed window
mask to the trench. The underlying thermal oxide was wet etched using BHF. The wafer
was cleaned using a 3:1 solution of H2S04:H202.Selective epitaxial silicon was grown at
a temperature of 950C, 40 Ton for 60 minutes. The exposed silicon was implanted with a
boron dose of 5x1015 cm-2 at 35 keV and driven in at 1000 "C in a wet O2 ambient for 25
minutes. The wafer was tested following the opening of contact windows, metallization
and anneal.
The baseline device was tested using the HP 4145 Semiconductor Parameter
Analyzer and the Tektronix Type 576 Curve Tracer. A 3D-IGBT device with a W/L ratio
of 20014 was tested for latch-up current, on-resistance, threshold voltage, gate to cathode
leakage, anode to cathode leakage, transconductance and forward blocking.
Figure 6.6 illustrates the successful fabrication of the 3D-IGBT. The output
characteristics indicate that with increasing gate bias, the forward conduction improves
significantly as expected. With increasing gate bias, the voltage drop across the MOSFET
portion of the 3D-IGBT becomes less significant and the MOSFET no longer limits the
current flow of the device. As the the gate bias is increased even further such that enough
inversion layer charge for providing electrons to the N--drift region is formed, the output
characteristics will resemble those of a PiN diode. Figures 6.7a and 6.7b illustrate another
signature of a properly functioning IGBT device; the diode knee. A diode knee is clearly
evident in the baseline device of figure 6.7b but is noticeably absent in the MOSFET device
shown in figure 6.7a. The diode knee is present because significant forward current will
not flow until the P+-anode/N--drift region junction is forward biased by approximately
0.7 volts. Below 0.7 volts on the anode, relatively little current flows. The diode offset

****** GRAPHICS
MARKER

3. 4 0 0 0 V

4. 000.

4. OSSmA

II

******

PLOT

Figure 6.6 Output characteristics of working 3D-IGBT.

(b)
Figure 6.7 Output characteristics of (a) Sidewall MOSFET and (b) 3D-IGBT.

voltage means that the 3D-IGBT as well as any other IGBT device is not suited for
applications requiring devices with forward drops of less than 0.7 volts.
Forward blocking capability of the 3D-IGBT is illustrated in figure 6.8. In the
forward blocking mode, the polysilicon gate was shorted to the cathode to prevent the
formation of an inversion layer under the gate. The flatness of the I-V characteristic also
indicates the low anode to cathode leakage current of the device. One of the most critical
aspects of the self-aligned process was the N+ doping of the polysilicon gate. Due to the
number of high temperature diffusion steps which followed the POCL3 deposition, the
likelihood of the phosphorous doping to diffuse through the gate oxide was highly
probable. SUPREM III simulations indicated that a minimum gate oxide thickness of 750
A was necessary to protect the channel region. If the phosphorous had diffused through to
the channel, the anode to cathode leakage current would have been much higher and the
flamess of the I-V characteristic shown in figure 6.8 would not have been evident.
With the gate shorted to the cathode, a positive bias applied was applied to the
anode. With this bias applied, the P-body/N--drift region junction becomes reverse biased
and supports the anode voltage. Figure 6.9 illustrates the I-V characteristics of a
UMOSFET as it is biased toward breakdown. Note that in both the 3D-IGBT and the
UMOSFET, the forward blocking breakdown voltage is approximately 90 volts. The
results suggest surface breakdown for both devices because their structural geometries are
vastly different and field rings were not employed to reduce surface fields. Figure 6.10
illustrates that the 3D-IGBT should see a gradual rise in its leakage current due to punch
through if the depletion region is allowed to extend to the P+-anode. The UMOSFET's I-V
will not indicate punch through due to the absence of the P+-anode. Chang et. al.[l]
showed that although the peak field does occur near the bottom comer of the trench in these
type devices, the breakdown voltage was still in excess of 500 volts.
Figures 6.11 through 6.14 are illustrations of the DC measurements for onresistance, threshold voltage, anode to cathode leakage, and gate to source leakage
repectively. Note how the curves in figure 6.11 begin to bunch together at higher gate
biases. This is due to a reduction in the channel mobility at higher gate biases. PISCES
and SUPREM 111 were used to analyze the channel length dependence of the 3D-IGBT
device. The SUPREM 111 concentration profile for the MOSFET channel region of the 3DIGBT is shown in figure 6.16. The channel length for the completed device is
approximately 2 microns. PISCES results shown in Figure 6.15 indicate that as the
channel length is decreased, the total current increases. The simulation results verify that

Figure 6.8 3D-IGBT device at a forward blocking voltage of

90 volts.

Figure 6.9 Onset of forward breakdown of UMOSFET at 90

volts.

surface breakdown
occurs here

surface breakdown
occurs here

Anode
(b)

Figure 6.10 Depletion region during forward blocking mode in

(a) 3D-IGBT and (b) UMOSFET.

****** GRAPHICS

PLOT

******

Figure 6.1 1 On-resistance measurement of 3D-IGBTdevice.

****** GRAPHICS
I
(mA> CURSOR C 17.300V

PLOT

******

2.48E+OO.

Figure 6.12 Threshold voltage measurement of 3D-IGBT: VT= 6.69 volts.

****** GRAPHICS

PLOT

******

Figure 6.13 Anode to cathode leakage current at Vg= 0 volts.

******

GRAPHICS PLOT

MARKER ( 10. OOOV1 , I4.55OpA ,

1 E-03

.---A

A----A -

-I

-/

******

1
- 1I ----.,

>

decade

Figure 6.14 Gate to cathode leakage current at Vd = 0 volts.

LC= 2.5 microns

LC= 1.5 microns

Anode Voltage

Figure 6.15 PISCES simulation results of 3D-IGBT

channel length dependence.

I""

SUPREM-

'

I I I .8628
I

"

"

-Ne t

"

Ac t 1 v e

"

- I

"

0 1 s tcnce f r o m surf a c e

' I "

(microns)

Figure 6.16 SUPREM 111 simulation results of doping concentration profile along
sidewall channel.

"

the transconductance of the 3D-IGBT is inversely proportional to the channel length as

expected.[2]
6.3.1 Latch-up
The 3D-IGBT has a parasitic four layer thyristor structure which could go into a
regenerative latch-up mode under certain conditions. Figure 6.17 is an equivalent circuit of
the 3D-IGBT. The magnitude of the short circuit resistance, Rs,is determined by the sheet
resistance of the P-base region under the N+-source. If the short circuit resistance is kept
as low as possible, then the N+-source/P-body junction at point A in figure 6.18 will not
become forward. biased. If the junction is forward biased, then the upper NPN transistor
of figure 6.17 will be active and the 3D-IGBT will be latched. Once the 3D-IGBT is
latched, it can only be turned off by lowering the anode voltage or by reversing its polarity.
To analyze the latch-up phenomena in the 3D-IGBT, consider that the total current
flowing in the device is

If the 3D-IGBT is thought of as a wide base PNP bipolar transistor whose base drive
current is sourced by the MOSFET, the hole and electron currents of the device can be
related to the gain of the wide base PNP transistor by

where Ih is the hole current injected into the N'-drift region by the anode and is collected by
the P-body region. Ie is the electron current flowing through the MOSFET channel.[3]
The anode current can also be expressed as

As the hole current Ih is swept out of the P-base region, it flows laterally under the n'source region. The lateral hole current flow produces a forward bias across the n+- P
junction at point A in figure 6.18. The forward bias across the junction is given by
VL = Ih Rp
(6.4)

SHORTlNG
RESISTANCE
Rti

Figure 6.17 Equivalent circuit of 3D-IGBT device.

N - Substrate

Figure 6.18 Cross-section of 3D-IGBT device showing latch-up implant offset.

where Rp is the resistance of the P-base region under the n+-source region. Combining
equations 6.2 and 6.3 and inserting them into equation 6.4, the voltage drop across the
junction becomes

The 3D-IGBT latches when the voltage drop across the junction is 0.7 volts; therefore, the
latch-up current is defined as

This relationship shows that the latch-up current can be increased by lowering the
resistance under the n+-source region or by lowering the gain of the wide base PNP
transistor. If the wide base transistor's gain is high, the hole current passing through the
P-base region will be a large fraction of the total current and therefore the latch-up current
will be low. Typically, the current gain is about 0.5 and is made lower by neutron
irradiation to control switching speed. The most common technique employed to increase
latching current density involves reducing the resistance Rp by introducing a deep P+
implant region.[4] This implant is usually referred to as a latch-up implant. The latch-up
implant enables the resistance, Rp, to be lowered. The two stage implant is required
because the original P-base implant is tailored to obtain the desired threshold voltage. The
latch-up implant offset, L,, shown in figure 6.18 should be as small as possible so that
most of the lateral current flow is in the low resistance P+ region under the n+-source.
Figure 6.19 is a photo of the 3D-IGBT with the latch-up implant in place. Wafers #2 and
#3 were fabricated with the latch-up implant. Figure 6.20 illustrates the on-set of latch-up
in the baseline device. Note the snapback nature of the current indicating an increase in the
electron current across the n+-source/P-base junction. The baseline device latched at an
anode current of 3 rnA or 125 ~ / c m 2assuming an anode area of 2.4~10-5cm2. Figure
6.21 illustrates the effectiveness of the latch-up implant. The device whose output
characteristics are shown in figure 6.21 was fabricated with a latch-up offset, L,, of 14
microns and its latch-up current was found to be 1,361 ki/cm2. The P+ implant increased
the latch-up current density by an order of magnitude as illustrated by figure 6.22.

Polysilicon Gate

Figure 6.19 Photograph of 3D-IGBT device with latch-up implant

in place.

Figure 6.20 3D-IGBT device at the onset of latch-up.

****** GRAPHICS PLOT ******

Figure 6.21 Output characteristics of 3D-IGBT device with latch-un imnlant

****** GRAPHICS PLOT ******

Figure 6.22 Comparison of latch-up current between device with latch-up

implant and one without.

The 3D-IGBT was simulated using PISCES. Figure 6.23 illustrates the output
characteristics of the simulated device and indicates that the maximum latch-up current is
approximately 10,000 ~lcrn2. The latch-up offset for the simulated device was 1.5
microns. The output characteristics of an actual 3D-IGBT device are shown in figure 6.24.
The latch-up current density for the device is 27.89 rnA or 1,162 ~ / c m 2 .The latch-up
offset for the fabricated device was 14 microns. Several 3D-IGBT devices with varying
implant offset values, LE, were also simulated using PISCES. The results are illustrated in
figure 6.25. As the implant offset is made smaller by placing the latch-up implant closer to
the edge of the trench, the latch-up current increases. The latch-up current predicted by
PISCES at LE= 14 pm was 4.5~10-5A/pm or 1,150 A/cm2. The PISCES results are in
excellent agreement with the actual device data.[5]-[9]
6.4 Trench Clean-up Results
Table 6.1 lists the averaged values of the key DC parameters measured on all 3
wafers. A minimum of 35 working devices were tested on each wafer. Note the increased
latch-up current for wafers 2 and 3. The baseline wafer did not utilize the latch-up implant
and therefore has a significantly lower latch-up current. The lower on-resistance value of
the baseline devices indicate that their transconductance was somewhat better than the
treated devices. The results of the capacitance study support this data. The large shift in
flatband voltage and increased interface states observed with the treated capacitors can be
related to the device transconductance by
gms-

(l-apnp)

Pns Cox

(VG-VT)

The increased number interface states reduces the mobility of the MOSFET channel of the
3D-IGBT and therefore reduces the device transconductance.
6.5 Device Scaling
The 3D-IGBT device is a fully integrable power device suitable for many power
integrated circuit applications. Presently, only the lateral insulated gate bipolar transistor
offers full integrability for power IC designers. The cellular layout of the 3D-IGBT
enables a reduction in the on-resistance compared to the LIGBT due to an increase in
channel density. If a total active area of 0.46 mm2 is assumed, the on-resistance of the
LIGBT is 3.5 R.[10] If the fabricated 3D-IGBT device shown in figure 6.5 in replicated in

I Litch-up offset = 1.5 microns

0.0

2.0

4.0

6.0

8.0

10.0

Anode Voltage

Figure 6.23 PISCES simulation of output characteristics of 3D-IGBT

indicating the onset of latch-up.

****** GRAPHICS PLOT

a*****

Figure 6.24 Output charateristic of 3D-IGBT indicating latch-up at

27.89 mA.

Vg=15 volts

"

"

"

10
Latch-Up Implant Offset
5

Figure 6.25 Latch-up current vs. Implant offset.

Table 6.1 Averaged DC Parameters for 3D-IGBT device.

Gate to Source
Leakage

-1pA

- 1pA

-1pA

Anode to Cathode
Leakage

46 nA

59 nA

59 nA

1.75E-3

1.05E-03

1.90E-03

g,

(3)

an array configuration with an active area of 0.46 mm2, 67 devices could be paralleled
together. The calculation goes as follows:

Assuming a cell size of 105pm x 65 pm gives an area per cell of 6,825 pm*. Therefore,
the number of 3D-IGBT devices configured in parallel for an active area of 0.46 mm2 is

The on-resistance of the paralleled 3D-IGBT device is found by dividing the on-resistance
of a single 3D-IGBT device such as that in figure 6.11 by the number of paralleled devices.
Therefore, the fabricated 3D-IGBT device would have and on-resistance of

Uniform c m n t flow in each of the individual 3D-IGBT &vice cells is assumed. The onresistance of the paralleled 3D-IGBT device is less than the on-resistance of the LIGBT but
a fiuther reduction in the on-resistance is achieved if the width of the trench is reduced.
During forward active operation of the 3D-IGBT, the N--drift region is conductivity
modulated &d contributes very little to the on-resistance of the total device. The onresistance of the 3D-IGBT during forward active operation is dominated by the resistance
of the sidewall MOSFET channel. Therefore, a reduction in the trench width will have little
or no impact on the amount of current sourced by the 3D-IGBT. With this in mind, if the
3D-IGBT cell size is reduced to 105 pm x 15 pm, then 292 devices could be configured in
parallel for the same amount of active area. Assuming no change in the output
characteristics after reducing the trench width from 60pm to 10pm, the adjusted onresistance is now

which is almost an order of magnitude lower than the LIGBT on-resistance for the same
active ma.

It is evident that the on-resistance of the 3D-IGBT is significantly reduced by

decreasing the the cell size. Using PISCES results in figure 6.23, the on-resistance per
unit cell of a 3D-IGBT whose cell size is 15 p x 15 pis

where the charmel width in each cell is 15pm x 2 = 30 vm. Assuming an area of 0.46
rnrn2, the total number of 3D-IGBT devices which can be combined in parallel is

The on-resistance for this parallel configuration is therefore

which is significantly less than the on-resistance of the LIGBT. The large difference in onresistance is due to the increased channel density of the 3D-IGBT device as shown below:
LIGBT channel density =

3D-IGBT channel density =

.695 cm
= 151 cm/cm2
4.6 x 10-3 cm 2

6.132 cm
= 1,333 cmjcm2
4.6 x 10-3 cm2

Figure 6.26 illustrates the structural feasibility of a cell size on the order of 225pm2. The
trench width is 10 pm wide and the selective silicon totally fill the trench.
The PISCES data used in the calculations above were compared to actual device
data in an effort to gage its accuracy. Several factors such as grid structure, selection of
device constants and physical dimensions play an integral part in how well the computer
simulations accurately predict device behavior. Initially, a PISCES simulation assuming a
2 micron channel length and a mobility degradation factor of 0.88 was analyzed. The
mobility degradation factor is used to approximate the reduction in electron mobility caused
by the reactive ion ecthed sidewall trench. Since the MOSFET channel is formed along this

Figure 6.26 SEM of 10 micron wide trench following epi growth out
of 5 micron deep trench.

sidewall, the mobility will be less than a more conventional planar MOSFET. The results
of this initial simulation are displayed in Figure 6.27 as PISCES(A). From the figure
observe that the device goes into latch-up at approximately 3 volts. Prior to latch-up, the
anode current was 92.7 mA which is an order of magnitude greater than the measured data
at that bias point.
One reason for the large discrepancy was determined to be an inadequate grid
structure for the simulated device. Due to the size of the actual device, a large number of
grid points were required to completely model its structure. Unfortunately, the grid
resolution in the vicinity of the MOSFET channel was not sufficient. In the PISCES(A)
simulation, the grid spacing in the x-direction, within a half micron of the trench edge, was
1000 A. Therefore, when the sidewall channel was formed, it's depth was a minimum of
1000 A. Typical channel depths for MOSFET devices are in the 30-100 A range; so a
larger than expected anode current resulted due to an increased amount of inversion layer
charge.
The PISCES(B) simulation attempted to remedy grid resolution problem by
providing a grid spacing of 30 A in the vicinity of the sidewall channel. The results in
Figure 6.27 indicate the improved grid structure enabled PISCES to more accurately predict
the anode current of the 3D-IGBT. The PISCES(B) results indicate an anode current of
34.7 mA at an anode voltage of 5 volts. The measured anode current was 18.2 mA at an
anode voltage of 5 volts. By improving the grid structure, PISCES data and measured
were brought to within a factor of 2.
PISCES is limited in its ability to accurately model the destructive nature of reactive
ion etching. The most important parameter typically used to compensate for sidewall
damage is the mobilty degradation factor. However, other factors such as interface state
density, trapped oxide charge and mobile ions in the oxide were not accounted for in the
simulations. Also, a 2 micron channel length was assumed based on SUPREM I11 results,
but there is no way of knowing what the actual channel length is unless the device is
sectioned and SRP measurements taken.. Results in Figure 6.15 show that the anode
current decreases with increased channel length and therefore, the channel length may be
longer than 2 microns. With all these factors accounted for, the PISCES data and measured
results should agree even better.

PISCES (A)
PISCES (B)
3D-IGBT(measured)

Anode Voltage
Figure 6.27 Comparison of simulated and measured output data for 3D-IGBZ

6.6 Summary
Elecmcal feasibility of the 3D-IGBT was demonstrated. Averaged results from
several 3D-IGBT devices indicate that the RIE sidewall treatment techniques have a
negligible effect on the DC characteristics of the device. When scaled, the on-resistance of
the 3D-IGBT was shown to be significantly less than the lateral IGBT; mainly due to the
increased packing density of the 3D-IGBT. Latch-up current for the fabricated devices was
as high as 1,361 A/cmZ and according to PISCES data, can be improved even further by
reducing the latch-up implant offset distance. Finally, structural feasibility of a minimum
3D-IGBT device was demonstrated by the successful growth of more than 5 microns of
selective silicon out of a 10 micron wide, 5 micron deep trench.

References
H.R. Chang and B.J. Baliga, "500-V n-Channel Insulated Gate Bipolar Transistor
with a Trench Gate Structure," IEEE Trans. Electron Devices, ED-36, No.9,
pp.1824-1828, 1989.
T.P. Chow and B.J. Baliga, "The Effect of Channel Length on the Performance of
the Insulated Gate Bipolar Transistor," IEEE Electron Device Letrers, Vol. EDL-6,
No.8, pp.413-415, 1985.
B.J. Baliga, Modern Power Devices, John Wiley and Sons, New York, Chapter 7,
p. 370, 1987.
B.J. Baliga, M.S. Adler, P.V. Gray and R.P. Love, "Suppressing Latch-up in
Insulated Gate Bipolar Transistor," IEEE Electron Device Letters, Vol. EDL-5,
No.8, pp.323-325, 1984.
A.L. Robinson, D.N. Pattanayak, M.S. Adler, B.J. Baliga and E.J. Wildi, "Lateral
Insulated Gate Transistors with Improved Latching Characteristics," I E D M
Technical Digest, Abstract 30.6, pp.744-747, 1985.
T.P. Chow, D.N. Pattanayak, B.J. Baliga, and M.S. Adler, "Latching in Lateral
Insulated Gate Bipolar Transistors," IEDM Technical Digest, Abstract 33.5,
pp.774-777, 1987.
J.G. Fossum and Y. Kim, "Static and Dynamic Latch-up in the LIGBT," IEEE
Trans. Electron Devices, Vol. ED-35, pp.1977-1985, 1988.
T.P. Chow, B.J. Baliga, and D.N. Pattanayak, "Counterdoping of MOS Channel
(CDC) - A New Technique of Improving Suppression of Latching in Insulated Gate
Bipolar Transistors," IEEE Electron Device Letters, Vol. EDL-9, No.1, pp.29-31,
1988.
H.Yilrnaz, "Cell Geometry Effect on IGT Latch-up," IEEE Electron Device Letters,
Vol. EDL-6, No.8, pp.419-421, 1985.
M.R. Simpson, P.A. Gough, F.I. Hshieh and V. Rumenik, " Analysis of Lateral
Insulated Gate Transistor," IEDM Technical Digest, Abstract 30.5, pp.740-743,
1985.

CHAPTER 7
SUMMARY AND PROPOSED FUTURE RESEARCH
7.1 Summary
The purpose of this research was to develop a process for the fabrication of a fully
integrable insulated gate bipolar transistor using selective epitaxial silicon and to develop a
novel isolation scheme whereby the power transistor could be easily suited for smart power
applications.. Feasibility of device quality selective epitaxial silicon grown in deep trenches
was demonstrated by the successful development of the quasi-dielectrically isolated bipolar
junction transistor (QDI-BJT). Improved photoresist coverage along trench corners,
definition of small features in bottom of a deep trench and growth of selective silicon out of
a deep trench were other techniques developed during the QDI project and utilized for the
development of the 3D-IGBT developed. Results of the QDI-BJT project also indicated
that a working QDI-BJT device can be achieved with an ion-implanted buried collector and
a second growth. Chemical mechanical planarization was also shown to eliminate the
negative effects of faceting and thus create a uniformly planar surface body. Feasibility of
a single 3D-IGBT device cell was demonstrated. Results indicate a much lower specific
on-resistance for the 3D-IGBT device compared to the lateral insulated gate bipolar
transistor for the same arnout of silicon area consumed. Averaged results from several 3DIGTBT devices indicate the RIE sidewall treatment techniques have a negligible effect on
the DC characteristics of the 3D-IGBT. Independent capacitance data supports this
conclusion.
The most critical aspect of the 3D-IGBT process was the oxide profile at the edge of
the trench following the long trench etch. If the photoresist coverage was insufficient, then
a less than 90' oxide profile resulted which then resulted in anode to cathode shorts if the
oxide degradation at the trench edge was too severe. Several techniques were explored to
improve the oxide step profile. It was determined that the most critical aspect was photoresist reflow caused very high postbake temperatures. By eliminating the photo-resist
postbake step and increasing the temperature of the prebake step, very good oxide step
profiles were obtained.

7.2 Future Work

The 3D-IGBT presented in this document was a single cell device. To adequately
investigate the on-resistance of the 3D-IGBT, a high-current configuration should be
fabricated. The high current device would simply be an array of single cell devices tied
together in parallel using a layout identical to that described in chapter 5. Further studies
should be done to determine the critical device parameters for accurate modeling of the 3DIGBT. Specifically, the actual channel length for the completed 3D-IGBT should be
determined using SRP measurements and this data aSong with fixed oxide charge, interface
trap density, mobile ions, surface fields and mobility degradation parameters should be
used to obtain a more accurate picture of the device performance. Latch-up performance
should also be studied to determine the maximum latch-up current density and
corresponding process constraints. In chapter 6 it was shown that the latch-up current
density increased as the latch-up implant moved closer to the trench edge. Pracess
constaints limit how close the implant can be placed to the trench edge. This information is
needed in order to adequately compare the 3D-IGBT to the full spectrum of power devices.
Although static DC latch-up was discussed in detail in chapter 6, dynamic latch-up
should also be invesitigated. Dynamic latch-up occurs as the IGBT device is switched
from the on to off state. Typically, the dynamic latch up current will be less than that of
static latch-up and therefore is more bothersome for some applcations. Lateral IGBTs are
prone to destructive failure due to dynamic latch-up and therefore several layout schemes
have been developed to reduce this threat.
The breakdown performance of the 3D-IGBT should be examined. The breakdown
perfomance of any power device is of utmost importance because doping levels and device
geometry are directly influenced by it. The 3D-IGBTs breakdown performance should be
similar to that of the UMOSFET and therefore should be as good as the lateral device.

APPENDIX

APPENDIX
3D-IGBT Run Sheet

1. Obtain an n-type silicon wafer.

3" diameter
resistivity:
1-5 R-cm
orientation: ( 100)

2. Mark wafer on backside

3. Ultraclean wafer
5 min. TCA in US cleaner
5 min. acetone in US cleaner
2 min. methanol rinse
1 min. rinse under flowing DI
Blow-dry wafer with dry nitrogen
Mix 2 parts H2SO4 with 1 part Hz02 and leave wafers in this solution
for at least 15 minutes.
5 min. rinse under flowing DI.
4. Field Oxide (4000 -4400 A)
push:
3 rnin.
35 min.
oxidize:
pull:
3 min.

N2@ ll00OC
Hz bum @ 1100C (Tube #4)
N2 @ l l W C

5. Ultraclean or direct transfer to HMDS belljar.

If wafer is directly transfered from oxidation
tube to belljar without storing it for more than
an hour, no ultraclean is necessary.
6.Apply HMDS adhesion promoter
5 min. in HMDS belljar under vacuum
7. Apply AZ-1350 positive photoresist
30 sec @ 4000 rpm
Blow off wafer with N2 gun prior to spinning resist

8. Place wafer in prebake oven

Temperature:
,llo"C
Ti:
30 min.
9. Expose mask level #1 (P-Base region)

Use SUSS aligner

Exposure t
h
&
:
Align wafer flat so that it is 45' off the mask edge.
10.Develop AZ-1350 positive photoresist
5:1 DI:AZ 351 mixture
Development time: 45 sec.
1 1. Inspect under microscope

12.Etch oxide in BHF

Estimated etch time: 4 min.
Recsrd oxide color before etch
Record etch time
13.Inspect wafer under microscope
14.P-Base Implant
Species:
Energy:
DO=:

Boron
35 keV
2 x 1014 cm-2

15.Strip AZ-1350 positive photoresist

Soak wafer in acetone (ACE) for 5 min.
Soak wafer in methanol (METH) for 5 min.
16. Ultraclean wafer
17 Drive-in P-Base implant
3 min.
push:
30 min.
anneal:
3 min.
pull:

N2@ l l W C

Dry 0 2 @ 1 100C
N2 @ 1lW0C

18.Apply HMDS adhesion promoter

19.Apply AZ-1350 positive photoresist

30 sec @ 4000 rpm
20.Place wafer in prebake oven
1 lOOC
Temperature:
Ti:
30 min.

21.Expose mask level #2 (n+-source region)

Use SUSS aligner
30 sec
Exposure time:
22.Develop AZ-1350 positive photoresist
5:1
DI:AZ351 mixture
Development time: 45 sec.
23.Inspect under microscope
24.Etch oxide in BHF

Estimated etch time: 1 min.

Record oxide color before etch
Record etch time
25. Inspect wafer under microscope
26. N+-Source Implant
Species:
Arsenic
Energy:
35 keV
Dose:
5 x 1015 cm-2
27. Strip AZ-1350 positive photoresist
28. Ultraclean wafer
29 Drive-in N+-Source Implant
3 min.
push:
25 min.
anneal:
3 min.
pull:

N2@ lOOOOC
Wet 0 2 @ 1000C
N2 @ lOOOOC

30.Apply HMDS adhesion promoter

31. Apply AZ- 1350 positive photoresist
30 sec @ 4000 rpm
32. Place wafer in prebake oven
Temperature:
1 10C
30 min.
Time:
33. Expose mask level #3 @+-latch-upimplant )
Use SUSS aligner
Exposure time:
30 sec
34. Develop AZ-1350 positive photoresist
D1:AZ 351 mixture
5:1
Development time:
45 sec.
35. Inspect under microscope
36. Etch oxide in BHF
Estimated etch time: 3 min.
Record oxide color before etch
Record etch time
37. Inspect wafer under microscope
38. P+-Latch-upImplant
Species:
Boron
Energy:
35 keV
Dose:
5 x 1015 ~ r n - ~

39. Strip AZ-1350 positive photoresist

40. Ultraclean wafer
41 Drive-in PC-Latch-up Implant
push:
3 min.
anneal:
15 min.
3 min.
pull:

N2@ l l W C
Wet 0 2 @ 1 l W C
N2 @ llOOC

42.Apply HMDS adhesion promoter

43. Apply AZ-1350 positive photoresist
30sec@4000rpm
44. Place wafer in prebake oven
110C
Temperature:
Ti:
30 min.

45. Expose mask level #4 (RE trench mask)

Use SUSS aligner
Exposure time:
30 sec
46. Develop AZ-1350 positive photoresist
5:1
DI:AZ 351 mixture
Development time: 45 sec.
47. Inspect under microscope
48. Etch oxide in BHF
Estimated etch time: 4 min.
Record oxide color before etch
Record etch time
49. Reactive ion (RE)etch 4 micron deep trench
Freon 1 15'
Etch gas:
Power:
750 W (forward)
Pressure:
280 m ~ '
Ti:
120 min.
50. Strip AZ-1350 positive photoresist
50. Ultraclean wafer
51. Grow l 0 d gate oxide
push:
3 min.
anneal:
55 min.
pull:
3 min.

N2 @ 1 100C
Dry02@ 1lOOOC
N 2 @ llOOOC

52. Ultraclean wafer.

If wafer is loaded into LPCVD tube immediately, no
ultraclean is necessary.

53. LPCVD polysilicon (5000 A)

Temperature:
550C
Silane Flowrate:
70 scan
Purge Time:
2 hours
Deposition Ti:
5 hours
54. Ultraclean wafer
55. Dope polysilicon N-type
POCL3 Deposition (tube #6)
push:
3 min.
N2 @ 950C
anneal:
15 min.
POQL3 @ 9 W C
pull:
3 min.
N2 @ 950C
56.Apply HMDS adhesion promoter

57. Apply AZ-4620 positive photoresist

30 sec @ 3500 rpm
58. Place wafer in prebake oven
110C
Temperature:
Time:
30 min.

59. Expose mask level #5 (Polysilicon contact mask)

Use SUSS aligner
30 sec
Exposure time:

60. Develop AZ-4620 positive photoresist

D1:AZ 351 mixture
5:1
Development time:
2.5 min.
61. Inspect under microscope
62. RIE doped polysilicon layer
Freon 1 15'
Etch gas:
POW;:
750 w (forward)
280 mT
Pressure:
Ti:
10 min.
63. Strip AZ-4620 positive photoresist
64. Ultraclean wafer
65. Oxidize sidewall poly gate
3 min.
push:
18 min.
anneal:
3 min.
pull:

N2@ llOOOC
Wet 0 2 @ 1 100C
N2 @ 1 100C

66. LPCVD polysilicon (5000 A)

Temperam:
5WC
Silane Flowate:
50 scan
Purge Time:
1 hour

Deposition Time:

1.5 hours

67. Ultraclean wafer

68. Oxidize conformal p l y layer

3 min.
push:
18 min.
anneal:
3 min.
pull:

N2@ 1100C
Wet 0 2 @ 1 100C
N2@ 1100C

69.Apply HMDS adhesion promoter

70. Apply AZ-4620 positive photoresist
30sec@ 3500rpm
71. Place wafer in prebake oven
110C
Temperature:
30
min.
Time:
72. Expose mask level #6 (Selective Epi seed window mask)
Use SUSS aligner
Exposure time:
30 sec
73. Develop AZ-4620 positive photoresist
5:l
DI:AZ351mixture
Development time:
2.5 min.
74. Inspect under microscope

75. Etch oxide in BHF

Estimated etch time: 8 min.
Record oxide color before etch
Record etch time
76. Strip AZ-4620 positive photoresist
77. U Itraclean wafer
78. Do selective epitaxy
Temperature:
Tm:
Pressure:

950C
60 min.
40 mT

79. Ultraclean wafer

80.Apply HMDS adhesion promoter
81. Apply AZ-4620 positive photoresist
30sec@ 3500rpm

82. Place wafer in prebake oven

Temperam:
110C
Ti:
30 min.
83. Expose mask level #7 (Anode region implant)
Use SUSS aligner
Exposure time:
30 sec
84. Develop AZ-4620 positive photo~sist
5:1
DI:AZ 351 mixture
Development time:
2.5 min.
85. Inspect under microscope
86. F-Anode Implant
Species:
Boron
Energy:
35 keV
Dose:
5 x 1015 cm-2
87. Ship AZ-4620 positive photoresist
88. Drive-in P+-AnodeImplant
3 min.
push:
anneal:
20 min.
3 min.
pull:

N2 @ lOOOOC
Wet 0 2 @ 1000C
N2 @ 1000C

89. Ultraclean wafer

90.Apply HMDS adhesion promoter
91. Apply AZ 1350positive photoresist
30 sec @ 4000 rpm
92. Place wafer in prebake oven
110C
Temperature:
Time:
30 min.
93. Expose mask level #8 (Contact windows)
Use SUSS aligner
Exposure time:
7.5 sec
94. Develop AZ-1350 positive photoresist
5:1
DI:AZ 351 mixture
Development time:
45 sec.
95. Strip AZ-1350 positive photoresist
96. Ultraclean wafer
97.Apply HMDS adhesion promoter

98. Apply A Z 1350positive photoresist

30 sec @ 4000 rpm
99. Place wafer in prebake oven
Temperatme:
110C
Ti:
30 min.

100.Expose mask level # (Metal lift off mask)

Use SUSS aligner
7.5 sec
Exposure time:
101.Develop A Z 1350 positive photuresist
5:l
DkAZ 351 mixwe
Developrynttime: 45 sec.
102.Aluminum deposition
Sputter -1 micron of A1-Si
103.Metal lift off
Use ACE in glass beaker in USC
104.Metal Anneal
heal:
105.Electrical Testing

20 min. @ 400C in N2

Percy V. Gilbert was born on August 30, 1963 in Atlanta, GA. He graduated from
J.E Brown high school in 1981. He then attended Purdue University where he received
the B.S.E.E. degree in 1985. In the Fall of 1985 he received a Master's fellowship from
the Graduate Consortium for Minorities in Engineering (GEM). During the summers of
1985 and 1986 he worked at NASA-Lewis Research Center. While at NASA he helped to
develop a Thermal Acoustic Wave Microscope for which he was awarded a NASA
Technical Innovation Award in 1988. He received the M.S.E.E. degree from Purdue
University in December 1986. In June 1986 he was married to Shireen Cunningham.
From January 1987 to December 1988 he developed testing strategy and design
enhancements for magnetic storage devices as a Test Engineer for Digital Equipment
Corporation in Sprin eld, MA. In January 1989 he returned to Purdue University to
work towards a Ph.D. degree in Electrical Engineering.

gfi

PUBLICATIONS

PUBLICATIONS

P.V. Gilbert, J.L. Glenn, G.W. Neudeck and J. P. Denton, "Silicon Selective Epitaxy
BJTs:Quasi-Dielectrically Isolated and Self-Aligned Single Crystal
Contacted", TECHON '90 Extended Abstract, pp.81-84, 1990.
P.V. Gilbert, G. W. Neudeck, J.P. Denton and S.J. Duey, "Quasi-Dielectrically
Isolated Bipolar Junction Transistor with Sub-Collector Fabricated Using
Silicon Selective Epitaxy", Proceedings of the 3rd International Symposium
on Power Semiconductor Devices and ICS, pp.199-202, 1991
P.V. Gilbert, G. W. Neudeck, J.P. Denton and S.J. Duey, "Quasi-Dielectrically
Isolated Bipolar Junction Transistor with Sub-Collector Fabricated Using
Silicon Selective Epitaxy", IEEE Trans. Electron Devices, Vol. ED-38, pp.
1660-1665, 1991.
P.V. Gilbert, G. W. Neudeck, R. Bashir, J. Siekkinen and J.P. Denton, "A Fully
Integrable Insulated Gate Bipolar Transistor with a Trench Gate Structure",
submitted to IEEE Electron Device Letters
P.V. Gilbert, G. W. Neudeck, R. Bashir, J. Siekkinen and J.P. Denton, "A Fully
Integrable IGBT with a Trench Gate Structure and Latch-Up htection
Using Selective Epitaxial Silicon", submitted tdEEE Trans.Electron
Devices