ANNA UNIVERSITY TIRUNELVELI

M.E. APPLIED ELECTRONICS

CURRICULUM 2005 - FULL TIME MODE
SEMESTER I
Code No.
Theory
MA1616A
AN1601
AN1602
AN1603
AN1604
E1***
Practical
AN1605

Course Title

Applied Mathematics for Electronics Engineers

Advanced Digital Signal Processing
Advanced Digital System Design
VLSI Design Techniques
Advanced Microprocessors and Micro Controllers
Elective I

3
3
3
3
3
3

1
1
1
0
0
0

0
0
0
0
0
0

100
100
100
100
100
100

Electronics Design Lab I

100

3
3
3
3
3
3

0
0
0
0
0
0

0
0
0
0
0
0

100
100
100
100
100
100

100

Elective IV
Elective V
Elective VI

3
3
3

0
0
0

0
0
0

100
100
100

Project Work (Phase I)

12

L
0

T
0

P
24

M
*

SEMESTER II
Code No.
Theory
AN1651
AN1652
AN1653
AN1654
E2***
E3***
Practical
AN1655

Course Title
Analysis and Design of Analog Integrated Circuits
Computer Architecture and Parallel Processing
Digital Control Engineering
Embedded Systems
Elective II
Elective III
Electronic Design Lab II
SEMESTER III

Code No.
Theory
E4***
E5***
E6***
Practical
AN1751

Course Title

SEMESTER IV
Code No.
Course Title
AN1751
Project Work (Phase II)
* As per Regulations 2005
LIST OF ELECTIVES
M.E. APPLIED ELECTRONICS

Code No.

Course Title

AN1621
AN1622
AN1623
VL1601
AN1625
AN1626
AN1627
AN1628
AN1629
AN1630
CO1621
VL1622
VL1623
VL1625
VL1651
AN1645

Digital Image Processing

Neural Networks and Application s
Robotics
DSP Integrated Circuits
ASIC Design
Design and Analysis of Algorithms
Reliability Engineering
Internetworking Multimedia
Electromagnetic Interference and Compatibility in
System Design
High Performance Communication Networks
RF system Design
Low Power VLSI Design
VLSI Signal Processing
Analog VLSI Design
Computer Aided Design of VLSI Circuits
Special Elective

3
3
3
3
3
3
3
3
3

0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0

100
100
100
100
100
100
100
100
100

3
3
3
3
3
3
3

0
0
0
0
0
0
0

0
0
0
0
0
0
0

100
100
100
100
100
100
100

MA1616A APPLIED MATHEMATICS FOR ELECTRONICS

ENGINEERS
(With effect from 2006-2007)
310
100
UNIT I
(9)
Linear Algebraic equation and Eigen Value Problem
System of Equations Solution by Gauss Elimination, Gauss Jordan and LU decomposition
method Jacobi, Gauss Seidal iteration method Eigen Values of a matrix by Jacobi and Power
methods.

UNIT II
(9)
Wave Equation
Solution of initial and boundary value problems Characteristics DAlemberts Solution
Significance of characteristic curves Laplace transform solutions for displacement in a long
string a long string under its weight Longitudinal vibration of a elastic bar with prescribed
force on one end free vibrations of a string.

UNIT III
(9)

Special Functions
Bessels equation Bessel Functions Legendres Equation Legendre Polynomials
Rodrigues formula Recurrence relations generating function and orthogonal property of
Bessel functions and Legendre polynomials .

UNIT IV
(9)
Random Variables
One dimensional Random Variables Moments and MGF Binomial, Poisson, Geometrical,
Uniform, Exponential, Normal and Welbull distributions Two dimensional Random Variables
Marginal and Conditional distribution Covariance and correlation coefficient Functions of one
dimensional and Two dimensional Random Variables.

UNIT V
(9) Queuing Theory
Single and Multiple server Markovian queuing models Steady state system size probabilities
Littles formula customers impatience priority queues M/G/1 queuing system P.K formula.
L 45, T 15, Total
- 60

References:
1. Jain M.K., Iyengar. S.R.K. & Jain. R.K, Numerical Methods for Scientific and Engineering
Computation, New Age International (P) ltd, Publishers, 2003.
2. Sankara Rao K, Introduction to Partial Differential , Prentice Hall of India, 1997.
3. Grewai B.S, Higher Engineering Mathematics, Khanna Publishers, 2005.
4. Kapur J.N & Saxena. H.C, Mathematics Statistics, S.Chand & Company Limited, New
Delhi,2003.
5. Taha H.A, Operations Research- An Introduction, Prentice Hall of India, 2001.
6. Gross D & Harris C.M, Fundamentals of Queuing Theory , John Wiley & Sons, 1985.

AN1601 ADVANCED DIGITAL SIGNAL PROCESSING

3 1 0 100

[Review of discrete-time signals and systems- DFT and FFT, Z-Transform, Digital
Filters is recommended]
UNIT I
DISCRETE RANDOM SIGNAL PROCESSING

Discrete Random Processes- Ensemble averages, stationary processes, Autocorrelation

and Auto covariance matrices. Parseval's Theorem, Wiener-Khintchine Relation- Power
Spectral Density-Periodogram Spectral Factorization, Filtering random processes. Low
Pass Filtering of White Noise. Parameter estimation: Bias and consistency.
UNIT II
SPECTRUM ESTIMATION

Estimation of spectra from finite duration signals, Non-Parametric Methods-Correlation

Method , Periodogram Estimator, Performance Analysis of Estimators -Unbiased,
Consistent Estimators- Modified periodogram, Bartlett and Welch methods, Blackman
Tukey method. Parametric Methods - AR, MA, ARMA model based spectral
estimation. Parameter Estimation -Yule-Walker equations, solutions using Durbins
algorithm
UNIT III
LINEAR ESTIMATION AND PREDICTION

Linear prediction- Forward and backward predictions, Solutions of the Normal

equations- Levinson-Durbin algorithms. Least mean squared error criterion -Wiener
filter for filtering and prediction , FIR Wiener filter and Wiener IIR filters ,Discrete
Kalman filter
UNIT IV
ADAPTIVE FILTERS

FIR adaptive filters -adaptive filter based on steepest descent method-Widrow-Hoff

LMS adaptive algorithm, Normalized LMS. Adaptive channel equalization-Adaptive
echo cancellation-Adaptive noise cancellation- Adaptive recursive filters (IIR). RLS
adaptive filters-Exponentially weighted RLS-sliding window RLS.
UNIT V
MULTIRATE DIGITAL SIGNAL PROCESSING

Mathematical description of change of sampling rate - Interpolation and Decimation ,

Decimation by an integer factor - Interpolation by an integer factor, Sampling rate
conversion by a rational factor, Filter implementation for sampling rate conversiondirect form FIR structures, Polyphase filter structures, time-variant structures.
Multistage implementation of multirate system. Application to sub band coding Wavelet transform and filter bank implementation of wavelet expansion of signals.
L-45 T-15 Total-60
4

REFERENCES:
1. Monson H.Hayes, Statistical Digital Signal Processing and Modeling, John
Wiley and Sons, Inc., Singapore, 2002.
2. John G. Proakis, Dimitris G.Manolakis, Digital Signal Processing Pearson
Education, 2002.
3. John G. Proakis et.al.Algorithms for Statistical Signal Processing, Pearson
Education, 2002.
4. Dimitris G.Manolakis et.al. Statistical and adaptive signal Processing,
McGraw Hill, Newyork, 2000.
5. Rafael C. Gonzalez, Richard E.Woods, Digital Image Processing, Pearson
Education, Inc., Second Edition, 2004.( For Wavelet Transform Topic)

AN1602 ADVANCED DIGITAL SYSTEM DESIGN

3 1 0 100

UNIT I
SEQUENTIAL CIRCUIT DESIGN

Analysis of Clocked Synchronous Sequential Networks (CSSN) Modeling of CSSN

State Stable Assignment and Reduction Design of CSSN Design of Iterative
Circuits ASM Chart ASM Realization.
UNIT II
ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

Analysis of Asynchronous Sequential Circuit (ASC) Flow Table Reduction Races in

ASC State Assignment Problem and the Transition Table Design of ASC Static
and Dynamic Hazards Essential Hazards Data Synchronizers Designing Vending
Machine Controller Mixed Operating Mode Asynchronous Circuits.
UNIT III
FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS

Fault Table Method Path Sensitization Method Boolean Difference Method

Kohavi Algorithm Tolerance Techniques The Compact Algorithm Practical PLAs
Fault in PLA Test Generation Masking Cycle DFT Schemes Built-in Self Test.
UNIT IV
SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES

EPROM to Realize a Sequential Circuit Programmable Logic Devices Designing a

Synchronous Sequential Circuit using a GAL EPROM Realization State machine
using PLD FPGA Xilinx FPGA Xilinx 2000 - Xilinx 3000
UNIT V
SYSTEM DESIGN USING VHDL

VHDL Description of Combinational Circuits Arrays VHDL Operators

Compilation and Simulation of VHDL Code Modeling using VHDL Flip Flops
Registers Counters Sequential Machine Combinational Logic Circuits - VHDL
Code for Serial Adder, Binary Multiplier Binary Divider complete Sequential
Systems Design of a Simple Microprocessor.
L -45 T-15 Total - 60

REFERENCES:
1. Donald G. Givone Digital principles and Design Tata McGraw Hill 2002.
2. John M Yarbrough Digital Logic applications and Design Thomson Learning,
2001
3. Nripendra N Biswas Logic Design Theory Prentice Hall of India, 2001
4. Charles H. Roth Jr. Digital System Design using VHDL Thomson Learning,
1998.
5. Charles H. Roth Jr. Fundamentals of Logic design Thomson Learning, 2004.
6. Stephen Brown and Zvonk Vranesic Fundamentals of Digital Logic with
VHDL Design Tata McGraw Hill, 2002.
7. Navabi.Z. VHDL Analysis and Modeling of Digital Systems. McGraw
International, 1998
8. Parag K Lala, Digital System design using PLD BS Publications, 2003
9. Peter J Ashendem, The Designers Guide to VHDL Harcourt India Pvt Ltd,
2002
10. Mark Zwolinski, Digital System Design with VHDL Pearson Education, 2004
11. Skahill. K, VHDL for Programmable Logic Pearson education, 1996

AN1603 VLSI DESIGN TECHNIQUES

3 0 0 100

UNIT I
MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY.

NMOS and PMOS transistors, Threshold voltage- Body effect- Design equationsSecond order effects. MOS models and small signal AC characteristics. Basic CMOS
technology.
UNIT II
INVERTERS AND LOGIC GATES.

NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient
characteristics , switching times, Super buffers, Driving large capacitance loads,
CMOS logic structures , Transmission gates, Static CMOS design, dynamic CMOS
design.
UNIT III
9
CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION
Resistance estimation, Capacitance estimation, Inductance, switching characteristics,
transistor sizing, power dissipation and design margining. Charge sharing .Scaling.
UNIT IV
VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL
PHYSICAL DESIGN.

Multiplexers, Decoders, comparators, priority encoders, Shift registers.

Arithmetic circuits Ripple carry adders, Carry look ahead adders, High-speed adders,
Multipliers. Physical design Delay modelling ,cross talk, floor planning, power
distribution. Clock distribution. Basics of CMOS testing.
UNIT V
VERILOG HARDWARE DESCRIPTION LANGUAGE

Overview of digital design with Verilog HDL, hierarchical modelling concepts,

modules and port definitions, gate level modelling, data flow modelling, behavioral
modelling, task & functions, Test Bench.
Total: 45

REFERENCES:
1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design,
Pearson Education ASIA, 2nd edition, 2000.
2. John P.Uyemura Introduction to VLSI Circuits and Systems, John Wiley &
Sons, Inc., 2002.
3. Samir Palnitkar, Verilog HDL, Pearson Education, 2nd Edition, 2004.
4. Eugene D. Fabricius, Introduction to VLSI Design McGraw Hill International
Editions, 1990.
5. J.Bhasker, B.S.Publications, A Verilog HDL Primer, 2nd Edition, 2001.
6. Pucknell, Basic VLSI Design, Prentice Hall of India Publication, 1995.
7. Wayne Wolf Modern VLSI Design System on chip. Pearson Education.2002.

AN1604 ADVANCED MICROPROCESSORS AND MICRO CONTROLLERS

3 0 0 100
UNIT I
9
MICROPROCESSOR ARCHITECTURE
Instruction set Data formats Instruction formats Addressing modes Memory
hierarchy register file Cache Virtual memory and paging Segmentation
Pipelining The instruction pipeline pipeline hazards Instruction level parallelism
reduced instruction set Computer principles RISC versus CISC RISC properties
RISC evaluation On-chip register files versus cache evaluation .
UNIT II
HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM

The software model functional description CPU pin descriptions

RISC
concepts bus operations Super scalar architecture pipe lining Branch prediction
The instruction and caches Floating point unit protected mode operation
Segmentation paging Protection multitasking Exception and interrupts
Input /Output Virtual 8086 model Interrupt processing -Instruction types
Addressing modes Processor flags Instruction set -programming the Pentium
processor.
UNIT III
HIGH PERFORMANCE RISC ARCHITECTURE: ARM

The ARM architecture ARM assembly language program ARM organization and
implementation The ARM instruction set - The thumb instruction set ARM CPU
cores.
UNIT IV
MOTOROLA 68HC11 MICROCONTROLLERS

Instructions and addressing modes operating

modes Hardware reset Interrupt
system Parallel I/O ports Flags Real time clock Programmable timer pulse
accumulator serial communication interface A/D converter hardware expansion
Assembly language Programming
UNIT V
PIC MICRO CONTROLLER

CPU architecture Instruction set - Interrupts Timers I/O port expansion I2C bus
for peripheral chip access A/D converter UART
Total - 45

10

REFERENCES :
1.
2.
3.
4.
5.
6.

Daniel Tabak , Advanced Microprocessors McGraw Hill.Inc., 1995

James L. Antonakos, The Pentium Microprocessor Pearson Education, 1997.
Steve Furber, ARM System On Chip architecture Addison Wesley, 2000.
Gene .H.Miller. Micro Computer Engineering, Pearson Education, 2003.
John .B.Peatman, Design with PIC Microcontroller, Prentice hall, 1997.
James L.Antonakos, An Introduction to the Intel family of Microprocessors
Pearson Education 1999.
7. Barry.B.Breg, The Intel Microprocessors Architecture , Programming and
Interfacing , PHI, 2002.
8. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first
reprints 2001.
Readings:
Web links
www.ocw.nit.edu
www.arm.com

11

AN1605

ELECTRONICS DESIGN LABORATORY I

0 0 4 100

1. System design using PIC Microcontroller.

2. Implementation of Adaptive Filters, periodogram and multistage multirate
system in DSP Processor
3. Simulation of QMF using Simulation Packages
4. Modeling of Sequential Digital system using VHDL.
5. Modeling of Sequential Digital system using Verilog.
6. Design and Implementation of ALU using FPGA.
7. Simulation of NMOS and CMOS circuits using SPICE.
8. System design using 16- bit Microprocessor.

12

AN1651

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

3 0 0 100

UNIT I
MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES

Depletion region of a PN junction large signal behavior of bipolar transistors- small signal
model of bipolar transistor- large signal behavior of MOSFET- small signal model of the
MOS transistors- short channel effects in MOS transistors weak inversion in MOS
transistors- substrate current flow in MOS transistor.
UNIT II
CIRCUIT CONFIGURATION FOR LINEAR IC

Current sources, Analysis of difference amplifiers with active load using BJT and FET,
supply and temperature independent biasing techniques, voltage references. Output stages:
Emitter follower, source follower and Push pull output stages.
UNIT III
9
OPERATIONAL AMPLIFIERS
Analysis of operational amplifiers circuit, slew rate model and high frequency analysis,
Frequency response of integrated circuits: Single stage and multistage amplifiers,
Operational amplifier noise
UNIT IV
ANALOG MULTIPLIER AND PLL

Analysis of four quadrant and variable trans conductance multiplier, voltage controlled
oscillator, closed loop analysis of PLL, Monolithic PLL design in integrated circuits: Sources
of noise- Noise models of Integrated-circuit Components Circuit Noise Calculations
Equivalent Input Noise Generators Noise Bandwidth Noise Figure and Noise
Temperature
UNIT V
ANALOG DESIGN WITH MOS TECHNOLOGY

MOS Current Mirrors Simple, Cascode, Wilson and Widlar current source CMOS Class
AB output stages Two stage MOS Operational Amplifiers, with Cascode, MOS TelescopicCascode Operational Amplifier MOS Folded Cascode and MOS Active Cascode
Operational Amplifiers
TOTAL: 45

13

REFERENCES
1. Gray, Meyer, Lewis, Hurst, Analysis and design of Analog ICs, Fourth Edition, Willey
International, 2002.
2. Behzad Razavi, Principles of data conversion system design, S.Chand and company
ltd, 2000
3. Nandita Dasgupata, Amitava Dasgupta,Semiconductor Devices, Modelling and
Technology, Prentice Hall of India pvt. ltd, 2004.
4. Grebene, Bipolar and MOS Analog Integrated circuit design, John Wiley &
sons,Inc.,2003.
5. Phillip E.Allen Douglas R. Holberg, CMOS Analog Circuit Design, Second EditionOxford University Press-2003
AN1652 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING 3 0 0 100
UNIT I
PRINCIPLES OF PARALLEL PROCESSING

Multiprocessors and Multicomputers Multivector and SIMD Computers- PRAM and VLSI
Models- Conditions of Parallelism- Program Partitioning and scheduling-program flow
mechanisms- parallel processing applications- speed up performance law.
UNIT II
PROCESSOR AND MEMORY ORGANIZATION

Advanced processor technology Superscalar and vector processors- Memory hierarchy

technology- Virtual memory technology- Cache memory organization- Shared memory
organization.
UNIT III
PIPELINE AND PARALLEL ARCHITECTURE

Linear pipeline processors- Non linear pipeline processors- Instruction pipeline designArithmetic design- Superscalar and super pipeline design- Multiprocessor system
interconnects- Message passing mechanisms.
UNIT IV
VECTOR, MULTITHREAD AND DATAFLOW ARCHITECTURE

Vector Processing principle- Multivector Multiprocessors- Compound Vector processingPrinciples of multithreading-fine grain multicomputers- scalable and multithread
architectures Dataflow and hybrid architectures.
UNIT V
SOFTWARE AND PARALLEL PROCESSING

Parallel programming models- parallel languages and compilers- parallel programming

environments- synchronization and multiprocessing modes- message passing program
development- mapping programs onto multicomputers- multiprocessor UNIX design goalsMACH/OS kernel architecture- OSF/1 architecture and applications.
TOTAL : 45
14

REFERENCES
1. Kai Hwang, Advanced Computer Architecture, TMH 2001.
2. William Stallings, Computer Organization and Architecture, McMillan Publishing
Company, 1990.
3. M.J. Quinn, Designing efficient Algorithms for parallel computer, McGraw Hill
International, 1994.
AN1653
UNIT I

DIGITAL CONTROL ENGINEERING

3 0 0 100
9

Review of frequency and time response analysis and specifications of control systems,
need for controllers, continues time compensations, continues time PI, PD, PID
controllers, digital PID controllers.
UNIT II
SIGNAL PROCESSING IN DIGITAL CONTROL

Sampling, time and frequency domain description, aliasing, hold operation, mathematical
model of sample and hold, zero and first order hold, factors limiting the choice of sampling
rate, reconstruction.
UNIT III
MODELING AND ANALYSIS OF SAMPLED DATA CONTROL SYSTEM

Difference equation description, Z-transform method of description, pulse transfer function,

time and frequency response of discrete time control systems, stability of digital control
systems, Jury's stability test, state variable concepts, first companion, second companion,
Jordan canonical models, discrete state variable models, elementary principles.
UNIT IV
DESIGN OF DIGITAL CONTROL ALGORITHMS

Review of principle of compensator design, Z-plane specifications, digital compensator

design using frequency response plots, discrete integrator, discrete differentiator,
development of digital PID controller, transfer function, design in the Z-plane.
UNIT V
PRACTICAL ASPECTS OF DIGITAL CONTROL ALGORITHMS

Algorithm development of PID control algorithms, software implementation, implementation

using microprocessors and microcontrollers, finite word length effects, choice of data
acquisition systems, microcontroller based temperature control systems, microcontroller
based motor speed control systems.
TOTAL : 45

15

REFERENCES
1. M.Gopal, "Digital Control and Static Variable Methods", Tata McGraw Hill, New
Delhi, 1997.
2. John J. D'Azzo, "Constantive Houpios, Linear Control System Analysis and
Design", Mc Graw Hill, 1995.
3. Kenneth J. Ayala, "The 8051 Microcontroller- Architecture, Programming and
Applications", Penram International, 2nd Edition, 1996.
AN1654

EMBEDDED SYSTEMS

3 0 0 100

UNIT I
EMBEDDED ARCHITECTURE

Embedded Computers, Characteristics of Embedded Computing Applications, Challenges in

Embedded Computing system design, Embedded system design process- Requirements,
Specification, Architectural Design, Designing Hardware and Software Components, System
Integration, Formalism for System Design- Structural Description, Behavioral Description,
Design Example: Model Train Controller
UNIT II
EMBEDDED PROCESSOR AND COMPUTING PLATFORM

ARM processor- processor and memory organization, Data operations, Flow of Control,
SHARC processor- Memory organization, Data operations, Flow of Control, parallelism with
instructions, CPU Bus configuration, ARM Bus, SHARC Bus, Memory devices, Input/output
devices, Component interfacing, designing with microprocessor development and debugging,
Design Example : Alarm Clock.
UNIT III
NETWORKS

Distributed Embedded Architecture- Hardware and Software Architectures, Networks for

embedded systems- I2C, CAN Bus, SHARC link pports, Ethernet, Myrinet, Internet,
Network-Based design- Communication Analysis, system performance Analysis, Hardware
platform design, Allocation and scheduling, Design Example: Elevator Controller.
UNIT IV
REAL-TIME CHARACTERISTICS

Clock driven Approach, weighted round robin Approach, Priority driven Approach, Dynamic
Versus Static systems, effective release times and deadlines, Optimality of the Earliest
deadline first (EDF) algorithm, challenges in validating timing constraints in priority driven
systems, Off-line Versus On-line scheduling.

16

UNIT V
SYSTEM DESIGN TECHNIQUES

Design Methodologies, Requirement Analysis, Specification, System Analysis and

Architecture Design, Quality Assurance, Design Example: Telephone PBX- System
Architecture, Ink jet printer- Hardware Design and Software Design, Personal Digital
Assistants, Set-top Boxes.
TOTAL : 45
REFERENCES
1. Wayne Wolf, Computers as Components: Principles of Embedded Computing System
Design, Morgan Kaufman Publishers, 2001.
2. Jane.W.S. Liu Real-Time systems, Pearson Education Asia, 2000
3. C. M. Krishna and K. G. Shin , Real-Time Systems, ,McGraw-Hill, 1997
4. Frank Vahid and Tony Givargi Embedded System Design: A Unified
Hardware/Software Introduction, s, John Wiley & Sons, 2000.
AN1655
1.
2.
3.
4.
5.
6.
7.

ELECTRONIC DESIGN LAB II

0 0 4 100

System design using PLL

System design using CPLD
Alarm clock using embedded micro controller
Model train controller using embedded micro controller
Elevator controller using embedded micro controller
Simulation of Non adaptive Digital Control System using MAT LAB control system
toolbox
Simulation of Adaptive Digital Control System using MAT LAB control system
toolbox

AN1621

DIGITAL IMAGE PROCESSING

3 0 0 100

UNIT I
DIGITAL IMAGE FUNDAMENTALS

Elements of digital image processing systems, Elements of visual perception, psycho

visual model, brightness, contrast, hue, saturation, mach band effect, Color image
fundamentals -RGB,HSI models, Image sampling, Quantization, dither, Two-dimensional
mathematical preliminaries.
UNIT II
IMAGE TRANSFORMS

1D DFT, 2D transforms DFT, DCT, Discrete Sine, Walsh, Hadamard, Slant, Haar, KLT,
SVD, Wavelet Transform.

17

UNIT III
IMAGE ENHANCEMENT AND RESTORATION

Histogram modification and specification techniques, Noise distributions, Spatial

averaging, Directional Smoothing, Median, Geometric mean, Harmonic mean,
Contraharmonic and Yp mean filters, Homomorphic filtering, Color image enhancement.
Image Restoration degradation model, Unconstrained and Constrained restoration,
Inverse filtering removal of blur caused by uniform linear motion, Wiener filtering,
Geometric transformations spatial transformations, Gray-Level interpolation,
UNIT IV
IMAGE SEGMENTATION AND RECOGNITION

Edge detection. Image segmentation by region growing, region splitting and merging,
edge linking.. Image Recognition Patterns and pattern classes, Matching by minimum
distance classifier, Matching by correlation, Back Propagation Neural Network, Neural
Network applications in Image Processing.
UNIT V
IMAGE COMPRESSION

Need for data compression, Huffman,. Run Length Encoding, Shift codes, Arithmetic
coding, Vector Quantization, Block Truncation Coding. Transform Coding DCT and
Wavelet. JPEG, MPEG. Standards, Concepts of Context based Compression.
Total: 45
REFERENCES:
1.
2.
3.
4.
5.
6.
7.

Rafael C. Gonzalez, Richard E.Woods, Digital Image Processing, Pearson

Education, Inc., Second Edition, 2004.
Anil K. Jain, Fundamentals of Digital Image Processing, Prentice Hall of India,
2002.
David Salomon : Data Compression The Complete Reference, Springer Verlag
New York Inc., 2nd Edition, 2001
Rafael C. Gonzalez, Richard E.Woods, Steven Eddins, Digital Image Processing
using MATLAB, Pearson Education, Inc., 2004.
William K.Pratt, Digital Image Processing, John Wiley, NewYork, 2002.
Milman Sonka, Vaclav Hlavac, Roger Boyle, Image Processing, Analysis, and
Machine Vision, Brooks/Cole, Vikas Publishing House, II ed., 1999.
Sid Ahmed, M.A., Image Processing Theory, Algorithms and Architectures,
McGraw-Hill, 1995.

18

AN1622

NEURAL NETWORKS AND APPLICATIONS

UNIT I
BASIC LEARNING ALGORITHMS

3 0 0 100
9

Biological Neuron Artificial Neural Model - Types of activation functions

Architecture: Feedforward and Feedback Learning Process: Error Correction Learning
Memory Based Learning Hebbian Learning Competitive Learning - Boltzman
Learning Supervised and Unsupervised Learning Learning Tasks: Pattern Space
Weight Space Pattern Association Pattern Recognition Function Approximation
Control Filtering - Beamforming Memory Adaptation - Statistical Learning Theory
Single Layer Perceptron Perceptron Learning Algorithm Perceptron Convergence
Theorem Least Mean Square Learning Algorithm Multilayer Perceptron Back
Propagation Algorithm XOR problem Limitations of Back Propagation Algorithm.
UNIT II
RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR
MACHINES:
RADIAL BASIS FUNCTION NETWORKS:

Covers Theorem on the Separability of Patterns - Exact Interpolator Regularization

Theory Generalized Radial Basis Function Networks - Learning in Radial Basis
Function Networks - Applications: XOR Problem Image Classification.
Support Vector Machines:
Optimal Hyperplane for Linearly Separable Patterns and Nonseparable Patterns Support
Vector Machine for Pattern Recognition XOR Problem - -insensitive Loss Function
Support Vector Machines for Nonlinear Regression
UNIT III
COMMITTEE MACHINES:

Ensemble Averaging - Boosting Associative Gaussian Mixture Model Hierarchical

Mixture of Experts Model(HME) Model Selection using a Standard Decision Tree A
Priori and Postpriori Probabilities Maximum Likelihood Estimation Learning
Strategies for the HME Model - EM Algorithm Applications of EM Algorithm to
HME Model
NEURODYNAMICS SYSTEMS:
Dynamical Systems Attractors and Stability Non-linear Dynamical SystemsLyapunov Stability Neurodynamical Systems The Cohen-Grossberg Theorem.

19

UNIT IV
ATTRACTOR NEURAL NETWORKS:

Associative Learning Attractor Neural Network Associative Memory Linear

Associative Memory Hopfield Network Content Addressable Memory Strange
Attractors and Chaos - Error Performance of Hopfield Networks - Applications of
Hopfield Networks Simulated Annealing Boltzmann Machine Bidirectional
Associative Memory BAM Stability Analysis Error Correction in BAMs - Memory
Annihilation of Structured Maps in BAMS Continuous BAMs Adaptive BAMs
Applications
ADAPTIVE RESONANCE THEORY:
Noise-Saturation Dilemma - Solving Noise-Saturation Dilemma Recurrent On-center
Off-surround Networks Building Blocks of Adaptive Resonance Substrate of
Resonance Structural Details of Resonance Model Adaptive Resonance Theory
Applications
UNIT V
9
SELF ORGANISING MAPS:
Self-organizing Map Maximal Eigenvector Filtering Sangers Rule Generalized
Learning Law Competitive Learning - Vector Quantization Mexican Hat Networks Self-organizing Feature Maps Applications
PULSED NEURON MODELS:
Spiking Neuron Model Integrate-and-Fire Neurons Conductance Based Models
Computing with Spiking Neurons.
Total: 45
REFERENCES:
1. Satish Kumar, Neural Networks: A Classroom Approach, Tata McGraw-Hill
Publishing Company Limited, New Delhi, 2004.
2. Simon Haykin, Neural Networks: A Comprehensive Foundation, 2ed., Addison
Wesley Longman (Singapore) Private Limited, Delhi, 2001.
3. Martin T.Hagan, Howard B. Demuth, and Mark Beale, Neural Network Design,
Thomson Learning, New Delhi, 2003.
4. James A. Freeman and David M. Skapura, Neural Networks Algorithms,
Applications, and Programming Techniques, Pearson Education (Singapore) Private
Limited, Delhi, 2003.

20

AN1623

ROBOTICS

3 0 0 100

UNIT I
INTRODUCTION TO ROBOTICS

Motion - Potential Function, Road maps, Cell decomposition and Sensor and sensor
planning. Kinematics. Forward and Inverse Kinematics - Transformation matrix and
DH transformation. Inverse Kinematics - Geometric methods and Algebraic methods.
Non-Holonomic constraints.
UNIT II
COMPUTER VISION

Projection - Optics, Projection on the Image Plane and Radiometry. Image Processing Connectivity, Images-Gray Scale and Binary Images, Blob Filling,
Thresholding, Histogram. Convolution - Digital Convolution and Filtering and Masking
Techniques. Edge Detection - Mono and Stereo Vision.
UNIT III
SENSORS AND SENSING DEVICES

Introduction to various types of sensor. Resistive sensors. Range sensors - Ladar (laser
distance and ranging), Sonar, Radar and Infra-red. Introduction to sensing - Light
sensing, Heat sensing, Touch sensing and Position sensing.
UNIT IV
ARTIFICIAL INTELLIGENCE

Uniform Search strategies - Breadth first, Depth first, Depth limited, Iterative and
deepening depth first search and Bidirectional search. The A* algorithm . Planning State-Space Planning , Plan-Space Planning, Graphplan/SatPlan and their Comparison,
Multi-agent planning 1, and Multi-agent planning 2, Probabilistic Reasoning Bayesian Networks, Decision Trees and Bayes net inference .
UNIT V
INTEGRATION TO ROBOT

Building of 4 axis or 6 axis robot - Vision System for pattern detection - Sensors for
obstacle detection - AI algorithms for path finding and decision making
Total: 45
REFERENCES
1. Duda, Hart and Stork, Pattern Recognition. Wiley-Interscience, 2000.
2. Mallot, Computational Vision: Information Processing in Perception and Visual
Behavior. Cambridge, MA: MIT Press, 2000.
3. Artificial Intelligence-A Modern Approach By Stuart Russell and Peter Norvig,
Pearson Education Series in Artificial Intelligence, 2004
4. Fundamentals of Robotics, Analysis and control By Robert Schilling and Craig,
Hall of India Private Limied, New Delhi, 2003.
5. Computer Vision, A modern Approach By Forsyth and Ponce, Person Education,
2003.
21

CO1621

RF SYSTEM DESIGN

3 0 0 100

UNIT I
RF ISSUES

Importance of RF design, Electromagnetic Spectrum, RF behaviour of passive

components, Chip components and Circuit Board considerations, Scattering Parameters,
Smith Chart and applications.
UNIT II
RF FILTER DESIGN

Overview , Basic resonator and filter configuration, Special filter realizations, Filter
implementations, Coupled filter.
UNIT III
ACTIVE RF COMPONENTS & APPLICATIONS

RF diodes, BJT, RF FETs, High electron mobility transistors; Matching and Biasing
Networks Impedance matching using discrete components, Microstripline matching
networks, Amplifier classes of operation and biasing networks.
UNIT IV
RF AMPLIFIER DESIGNS

Characteristics, Amplifier power relations, Stability considerations, Constant gain circles,

Constant VSWR circles, Low Noise circuits, Broadband , high power and multistage
amplifiers.
UNIT V
OSCILLATORS, MIXERS & APPLICATIONS

Basic Oscillator model, High frequency oscillator configuration, Basic characteristics of

Mixers ; Phase Locked Loops ; RF directional couplers and hybrid couplers ; Detector
and demodulator circuits.
Total: 45 Hours
REFERENCES:
1. Reinhold Ludwig and Powel Bretchko, RF Circuit Design Theory and Applications,
Pearson Education Asia, First Edition, 2001.
2. Joseph . J. Carr, Secrets of RF Circuit Design , McGraw Hill Publishers, Third
Edition, 2000.
3. Mathew M. Radmanesh, Radio Frequency & Microwave Electronics, Pearson
Education Asia, Second Edition, 2002.
4. Ulrich L. Rohde and David P. NewKirk, RF / Microwave Circuit Design, John Wiley
& Sons USA 2000.
5. Roland E. Best, Phase - Locked Loops: Design, simulation and applications, McGraw
Hill Publishers 5TH edition 2003.
22

VL1601

DSP INTEGRATED CIRCUITS

3 0 0 100

UNIT I
DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES

Standard digital signal processors, Application specific ICs for DSP, DSP systems, DSP
system design, Integrated circuit design. MOS transistors, MOS logic, VLSI process
technologies, Trends in CMOS technologies.
UNIT II
DIGITAL SIGNAL PROCESSING

Digital signal processing, Sampling of analog signals, Selection of sample frequency, Signalprocessing systems, Frequency response, Transfer functions, Signal flow graphs, Filter
structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform, FFT-The Fast
Fourier Transform Algorithm, Image coding, Discrete cosine transforms.
UNIT III
DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS

FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping
of analog transfer functions, Mapping of analog filter structures, Multirate systems,
Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate
filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Round-off
noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.
UNIT IV
DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES

DSP system architectures, Standard DSP architecture, Ideal DSP architectures,

Multiprocessors and multicomputers, Systolic and Wave front arrays, Shared memory
architectures. Mapping of DSP algorithms onto hardware, Implementation based on
complex PEs, Shared memory architecture with Bit serial PEs.
UNIT V
9
NUMBER SYSTEMS , ARITHMETIC UNITS AND INTEGARTED CIRCUIT
DESIGN
Conventional number system, Redundant Number system, Residue Number System .Bitparallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size,
Complex multipliers, Improved shift-accumulator. Layout of VLSI circuits, FFT processor,
DCT processor and Interpolator as case studies
TOTAL : 45
REFERENCES
1. Lars Wanhammer, DSP INTEGRATED CIRCUITS, Academic press, New York 1999.
2. A.V.Oppenheim et.al, Discrete-time Signal Processing Pearson education, 2000.
3. Emmanuel C. Ifeachor, Barrie W. Jervis, Digital signal processing A practical
approach, 2nd edition, Prentice Hall, 2001.
4. Keshab K.Parhi, VLSI digital Signal Processing Systems design and Implementation
John Wiley & Sons, 1999.
23

AN1625

ASIC DESIGN

3 0 0 100

UNIT I
INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN

Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational
Logic Cell Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor
Parasitic Capacitance- Logical effort Library cell design - Library architecture .
UNIT II
9
PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS AND
PROGRAMMABLE ASIC I/O CELLS
Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel
ACT - Xilinx LCA Altera FLEX - Altera MAX DC & AC inputs and outputs - Clock &
Power inputs - Xilinx I/O blocks.
UNIT III
9
PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC DESIGN
SOFTWARE AND LOW LEVEL DESIGN ENTRY
Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 Altera FLEX Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low
level design language - PLA tools -EDIF- CFI design representation.
UNIT IV
LOGIC SYNTHESIS, SIMULATION AND TESTING

Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan
test - fault simulation - automatic test pattern generation.
UNIT V
9
ASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND ROUTING
System partition - FPGA partitioning - partitioning methods - floor planning - placement physical design flow global routing - detailed routing - special routing - circuit extraction DRC.
TOTAL : 45
REFERENCES
1.
2.
3.
4.

M.J.S .Smith, "Application Specific Integrated Circuits, Addison -Wesley Longman

Inc., 1997.
Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical
Approach, Prentice Hall PTR, 2003.
Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2004.
R. Rajsuman, System-on-a-Chip Design and Test. Santa Clara, CA: Artech House
Publishers, 2000.
24

5.

F. Nekoogar. Timing Verification of Application-Specific Integrated Circuits

(ASICs). Prentice Hall PTR, 1999.

25

AN1626

DESIGN AND ANALYSIS OF ALGORITHMS

UNIT I
INTRODUCTION

3 0 0 100
9

Polynomial and Exponential algorithms, big "oh" and small "oh" notation, exact algorithms
and heuristics, direct / indirect / deterministic algorithms, static and dynamic complexity,
stepwise refinement.
UNIT II
DESIGN TECHNIQUES

Subgoals method, working backwards, work tracking, branch and bound algorithms for
traveling salesman problem and knapsack problem, hill climbing techniques, divide and
conquer method, dynamic programming, greedy methods.
UNIT III
SEARCHING AND SORTING

Sequential search, binary search, block search, Fibonacci search, bubble sort, bucket sorting,
quick sort, heap sort, average case and worst case behavior, FFT.
UNIT IV
GRAPH ALGORITHMS

Minimum spanning, tree, shortest path algorithms, R-connected graphs, Even's and
Kleitman's algorithms, ax-flow min cut theorem, Steiglitz's link deficit algorithm.
UNIT V
SELECTED TOPICS

NP Completeness Approximation Algorithms, NP Hard Problems, Strasseu's Matrix

Multiplication Algorithms, Magic Squares, Introduction To Parallel Algorithms and Genetic
Algorithms, Monti-Carlo Methods, Amortised Analysis.
TOTAL : 45
REFERENCES
1. Sara Baase, "Computer Algorithms : Introduction to Design and Analysis", Addison
Wesley, 1988.
2. T.H.Corman, C.E.Leiserson and R.L.Rioest, "Introduction to Algorithms", Mc Graw Hill,
1994.
3. E.Horowitz and S.Sahni, "Fundamentals of Computer Algorithms", Galgotia Publications,
1988.
4. D.E.Goldberg, "Genetic Algorithms : Search Optimization and Machine Learning",
Addison Wesley, 1989.

26

AN1627

RELIABILITY ENGINEERING

3 0 0 100

UNIT I
PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE

Statistical distribution , statistical confidence and hypothesis testing ,probability plotting

techniques Weibull, extreme value ,hazard, binomial data; Analysis of load strength
interference , Safety margin and loading roughness on reliability.
UNIT II
RELIABILITY PREDICTION, MODELLING AND DESIGN

Statistical design of experiments and analysis of variance Taguchi method, Reliability

prediction, Reliability modeling, Block diagram and Fault tree Analysis ,petric Nets, State
space Analysis, Monte carlo simulation, Design analysis methods quality function
deployment, load strength analysis, failure modes, effects and criticality analysis.
UNIT III
ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY

Reliability of electronic components, component types and failure mechanisms, Electronic

system reliability prediction, Reliability in electronic system design; software errors,
software structure and modularity, fault tolerance, software reliability, prediction and
measurement, hardware/software interfaces.
UNIT IV
RELIABILITY TESTING AND ANALYSIS

Test environments, testing for reliability and durability, failure reporting, Pareto analysis,
Accelerated test data analysis, CUSUM charts, Exploratory data analysis and proportional
hazards modeling, reliability demonstration, reliability growth monitoring.
UNIT V
MANUFACTURE AND RELIABILITY MAQNAGEMENT

Control of production variability, Acceptance sampling, Quality control and stress screening,
Production failure reporting; preventive maintenance strategy, Maintenance schedules,
Design for maintainability, Integrated reliability programmes , reliability and costs, standard
for reliability, quality and safety, specifying reliability, organization for reliability.
TOTAL: 45
REFERENCES
1. Patrick D.T. OConnor, David Newton and Richard Bromley, Practical Reliability
Engineering, Fourth edition, John Wiley & Sons, 2002
2. David J. Klinger, Yoshinao Nakada and Maria A. Menendez, Von Nostrand Reinhold,
New York, "AT & T Reliability Manual", 5th Edition, 1998.
3. Gregg K. Hobbs, "Accelerated Reliability Engineering - HALT and HASS", John Wiley
& Sons, New York, 2000.
4. Lewis, "Introduction to Reliability Engineering", 2nd Edition, Wiley International,
1996.
27

VL1623

VLSI SIGNAL PROCESSING

3 0 0 100

UNIT I
INTRODUCTION TO DSP SYSTEMS

Introduction To DSP Systems -Typical DSP algorithms; Iteration Bound data flow graph
representations, loop bound and iteration bound, Longest path Matrix algorithm; Pipelining
and parallel processing Pipelining of FIR digital filters, parallel processing, pipelining and
parallel processing for low power.
UNIT II
RETIMING

Retiming - definitions and properties; Unfolding an algorithm for Unfolding, properties of

unfolding, sample period reduction and parallel processing application; Algorithmic strength
reduction in filters and transforms 2-parallel FIR filter, 2-parallel fast FIR filter, DCT
algorithm architecture transformation, parallel architectures for rank-order filters, Odd- Even
Merge- Sort architecture, parallel rank-order filters.
UNIT III
FAST CONVOLUTION

Fast convolution Cook-Toom algorithm, modified Cook-Took algorithm; Pipelined and

parallel recursive and adaptive filters inefficient/efficient single channel interleaving, LookAhead pipelining in first- order IIR filters, Look-Ahead pipelining with power-of-two
decomposition, Clustered Look-Ahead pipelining, parallel processing of IIR filters,
combined pipelining and parallel processing of IIR filters, pipelined adaptive digital filters,
relaxed look-ahead, pipelined LMS adaptive filter.
UNIT IV
BIT-LEVEL ARITHMETIC ARCHITECTURES

Scaling and roundoff noise- scaling operation, roundoff noise, state variable description of
digital filters, scaling and roundoff noise computation, roundoff noise in pipelined first-order
filters; Bit-Level Arithmetic Architectures- parallel multipliers with sign extension, parallel
carry-ripple array multipliers, parallel carry-save multiplier, 4x 4 bit Baugh- Wooley carrysave multiplication tabular form and implementation, design of Lyons bit-serial multipliers
using Horners rule, bit-serial FIR filter, CSD representation, CSD multiplication using
Horners rule for precision improvement.
UNIT V
PROGRAMMING DIGITAL SIGNAL PROCESSORS

Numerical Strength Reduction sub expression elimination, multiple constant

multiplications, iterative matching. Linear transformations; Synchronous, Wave and
asynchronous pipelining- synchronous pipelining and clocking styles, clock skew in edgetriggered single-phase clocking, two-phase clocking, wave pipelining, asynchronous
pipelining bundled data versus dual rail protocol; Programming Digital Signal Processors
general architecture with important features; Low power Design needs for low power VLSI
chips, charging and discharging capacitance, short-circuit current of an inverter, CMOS
leakage current, basic principles of low power design.
TOTAL : 45
28

REFERENCES
1.

Keshab K.Parhi, VLSI Digital Signal Processing systems, Design and

implementation, Wiley, Inter Science, 1999.
2.
Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic
Publishers, 1998.
3.
Mohammed Isamail and Terri Fiez, Analog VLSI Signal and Information
Processing, Mc Graw-Hill, 1994.
4.
S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing,
Prentice Hall, 1985.
5.
Jose E. France, Yannis Tsividis, Design of Analog - Digital VLSI Circuits for
Telecommunication and Signal Processing, Prentice Hall, 1994.
AN1628

INTERNETWORKING MULTIMEDIA

3 0 0 100

UNIT I
MULTIMEDIA NETWORKING

Digital sound, video and graphics, basic multimedia networking, multimedia

characteristics, evolution of Internetservices model, network requirements for audio/
video transform, multimedia coding and compression for text, image, audio and video.
UNIT II
BROAD BAND NETWORK TECHNOLOGY

Broadband services, ATM and IP, IPV6, High speed switching, resource reservation,
Buffer management, traffic shaping, caching, scheduling, and policing, throughput, delay
and jitter performance. Storage and media services, voice and video over IP, MPEG-2
over ATM/IP, indexing synchronization of requests, recording and remote control.
UNIT III
RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS

Multicast over shared media network, multicast routing and addressing, scaping multicast
and NBMA networks, Reliable transport protocols, TCP adaptation algorithm, RTP,
RTCP. MIME, Peer- to-Peer computing, shared application, video conferencing,
centralized and distributed conference control, distributed virtual reality, light weight
session philosophy.
UNIT IV
MULTIMEDIA COMMUNICATION STANDARDS

Objective of MPEG- 7 standard, Functionalities and systems of MPEG-7, MPEG-21

Multimedia Framework Architecture, - Content representation, Content Management and
usage, Intellectual property management, Audio visual system- H322: Guaranteed QOS
LAN systems; MPEG_4 video Transport across internet.

29

UNIT V
MULTIMEDIA COMMUNICATION ACROSS NETWORKS

Packet Audio/video in the network environment, video transport across Generic

networks- Layered video coding, error Resilient video coding techniques, Scalable Rate
control, Streaming video across Internet, Multimedia transport across ATM networks and
IP network, Multimedia across wireless networks.
TOTAL : 45
REFERENCES
1.

Jon Crowcroft, Mark Handley, Ian Wakeman, Internetworking Multimedia,

Harcourt Asia Pvt. Ltd. Singapore, 1998.
2.
B.O. Szuprowicz, Multimedia Networking, McGraw Hill, NewYork. 1995
3.
Tay Vaughan, Multimedia making it to work, 4ed, Tata McGraw Hill , New
Delhi, 2000.
4.
K.R.Rao, Zoran S. Bojkovic and Dragorad A. Milovanovic, Multimedia
Communication systems, PHI , 2003 ( Unit 4 and Unit 5)
AN1629 ELECTROMAGNETIC INTERFERENCE AND COMPATIBILITY IN
SYSTEM DESIGN
3 0 0 100
UNIT I
EMI ENVIRONMENT

EMI/EMC concepts and definitions, Sources of EMI, conducted and radiated EMI,
Transient EMI, Time domain Vs Frequency domain EMI, Units of measurement
parameters, Emission and immunity concepts, ESD.
UNIT II
EMI COUPLING PRINCIPLES

Conducted, Radiated and Transient Coupling, Common Impedance Ground Coupling,

Radiated Common Mode and Ground Loop Coupling, Radiated Differential Mode
Coupling, Near Field Cable to Cable Coupling, Power Mains and Power Supply
coupling.
UNIT III
EMI/EMC STANDARDS AND MEASUREMENTS

Civilian standards - FCC,CISPR,IEC,EN,Military standards - MIL STD 461D/462, EMI

Test Instruments /Systems, EMI Shielded Chamber, Open Area Test Site, TEM Cell,
Sensors/Injectors/Couplers, Test beds for ESD and EFT, Military Test Method and
Procedures (462).

30

UNIT IV
EMI CONTROL TECHNIQUES

Shielding, Filtering, Grounding, Bonding, Isolation Transformer, Transient Suppressors,

Cable Routing, Signal Control, Component Selection and Mounting.
UNIT V
EMC DESIGN OF PCBs

PCB Traces Cross Talk, Impedance Control, Power Distribution Decoupling, Zoning,
Motherboard Designs and Propagation Delay Performance Models.
TOTAL : 45
REFERENCES
1. Henry W.Ott, "Noise Reduction Techniques in Electronic Systems", John Wiley
and Sons, NewYork. 1988.
2. C.R.Paul, Introduction to Electromagnetic Compatibility , John Wiley and Sons,
Inc, 1992
3. V.P.Kodali, "Engineering EMC Principles, Measurements and Technologies",
IEEE Press, 1996.
4. Bernhard Keiser, "Principles of Electromagnetic Compatibility", Artech house,
3rd Ed, 1986.
AN1630 HIGH PERFORMANCE COMMUNICATION NETWORKS
UNIT I
PACKET SWITCHED NETWORKS

3 0 0 100
9

OSI and IP models, Ethernet (IEEE 802.3), Token ring (IEEE 802.5), Wireless LAN (IEEE
802.11) FDDI, DQDB, SMDS: Internetworking with SMDS
UNIT II
ISDN AND BROADBAND ISDN

ISDN - overview, interfaces and functions, Layers and services - Signaling System 7 Broadband ISDN architecture and Protocols.
UNIT III
ATM AND FRAME RELAY

ATM: Main features-addressing, signaling and routing, ATM header structure-adaptation

layer, management and control, ATM switching and transmission.
Frame Relay: Protocols and services, Congestion control, Internetworking with ATM,
Internet and ATM, Frame relay via ATM.

31

UNIT IV
ADVANCED NETWORK ARCHITECTURE

IP forwarding architectures overlay model, Multi Protocol Label Switching (MPLS),

integrated services in the Internet, Resource Reservation Protocol (RSVP), Differentiated
services
UNIT V
BLUE TOOTH TECHNOLOGY

The Blue tooth module-Protocol stack Part I: Antennas, Radio interface, Base band, The Link
controller, Audio, The Link Manager, The Host controller interface; The Blue tooth moduleProtocol stack Part I: Logical link control and adaptation protocol, RFCOMM, Service
discovery protocol, Wireless access protocol, Telephony control protocol.
TOTAL : 45
REFERENCES
1. William Stallings,ISDN and Broadband ISDN with Frame Relay and ATM, 4th edition,
Pearson education Asia, 2002.
2. Leon Gracia, Widjaja, Communication networks ", Tata McGraw-Hill, New Delhi,
2000.
3. Jennifer Bray and Charles F.Sturman,Blue Tooth Pearson education Asia, 2001.
4. Sumit Kasera, Pankaj Sethi, ATM Networks ", Tata McGraw-Hill, New Delhi, 2000.
5. Rainer Handel, Manfred N.Huber, Stefan Schroder,ATM Networks,3rd edition, Pearson
education asia,2002.
6. Jean Walrand and Pravin varaiya, High Performance Communication networks, 2nd
edition, Harcourt and Morgan Kauffman, London 2000.
7. William Stallings,High-speed Networks and Internets, 2nd edition, Pearson education
Asia, 2003.
VL1625

ANALOG VLSI DESIGN

3 0 0 100

UNIT I
9
BASIC CMOS CIRCUIT TECHNIQUES, CONTINUOUS TIME AND LOWVOLTAGESIGNAL PROCESSING:
Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting
Techniques-Super MOSTransistor- Primitive Analog Cells-Linear Voltage-Current
Converters-MOS Multipliers and Resistors-CMOS,Bipolar and Low-Voltage BiCMOS OpAmp Design-Instrumentation Amplifier Design-Low Voltage Filters.
UNIT II
BASIC BICMOS CIRCUIT TECHNIQUES, CURRENT
PROCESSING AND NEURAL INFORMATION PROCESSING

9
-MODE

SIGNAL

Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data

Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks 32

Floating - Gate, Low-Power Neural Networks-CMOS Technology and Models-Design

Methodology-Networks-Contrast Sensitive Silicon Retina.
UNIT III

SAMPLED-DATA ANALOG FILTERS, OVER SAMPLED A/D CONVERTERS AND

ANALOG INTEGRATED SENSORS
First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-SwitchedCapacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate A/D ConvertersModulators for Over sampled A/D Conversion-First and Second Order and Multibit SigmaDelta Modulators-Interpolative Modulators Cascaded Architecture-Decimation Filtersmechanical, Thermal, Humidity and Magnetic Sensors-Sensor Interfaces.
UNIT IV
DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS

Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and

General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test BusesDesign for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of
Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for
Prototyping Analog Circuits.
UNIT V

STATISTICAL MODELING AND SIMULATION, ANALOG COMPUTER-AIDED

DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT
Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit SimulationAutomation Analog Circuit Design-automatic Analog Layout-CMOS Transistor LayoutResistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout.
TOTAL : 45
REFERENCES
1. Mohammed Ismail, Terri Fiez, Analog VLSI signal and Information Processing ",
McGraw-Hill International Editons, 1994.
2. Malcom R.Haskard, Lan C.May, Analog VLSI Design - NMOS and CMOS ", Prentice
Hall, 1998.
3. Randall L Geiger, Phillip E. Allen, " Noel K.Strader, VLSI Design Techniques for Analog
and Digital Circuits ", Mc Graw Hill International Company, 1990.
4. Jose E.France, Yannis Tsividis, Design of Analog-Digital VLSI Circuits for
Telecommunication and signal Processing ", Prentice Hall, 1994

33

VL1651

COMPUTER AIDED DESIGN OF VLSI CIRCUITS

3 0 0 100

UNIT I

Introduction to VLSI Design methodologies - Review of Data structures and algorithms Review of VLSI Design automation tools - Algorithmic Graph Theory and Computational
Complexity - Tractable and Intractable problems - general purpose methods for
combinatorial optimization.
UNIT II

Layout Compaction - Design rules - problem formulation - algorithms for constraint graph
compaction - placement and partitioning - Circuit representation - Placement algorithms partitioning
UNIT III

Floorplanning concepts - shape functions and floorplan sizing - Types of local routing
problems - Area routing - channel routing - global routing - algorithms for global routing.
UNIT IV

Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis.
UNIT V

High level Synthesis - Hardware models - Internal representation - Allocation assignment and
scheduling - Simple scheduling algorithm - Assignment problem High level
transformations.
TOTAL : 45
REFERENCES
1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley &
Sons,2002.
2. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation",
Kluwar Academic Publishers, 2002.
3. Drechsler, R., Evolutionary Algorithms for VLSI CAD, Kluwer Academic
Publishers, Boston, 1998.
4. Hill, D., D. Shugard, J. Fishburn and K. Keutzer, Algorithms and Techniques for
VLSI Layout Synthesis, Kluwer Academic Publishers, Boston, 1989.

34

VL1622 LOW POWER VLSI DESIGN

0 0 100

UNIT I

POWER DISSIPATION IN CMOS

Hierarchy of limits of power Sources of power consumption Physics of power
dissipation in CMOS FET devices- Basic principle of low power design.
UNIT II
POWER OPTIMIZATION

Logical level power optimization Circuit level low power design Circuit techniques
for reducing power consumption in adders and multipliers.
UNIT III
DESIGN OF LOW POWER CMOS CIRCUITS

Computer Arithmetic techniques for low power systems Reducing power

consumption in memories Low power clock, Interconnect and layout design
Advanced techniques Special techniques
UNIT IV
POWER ESTIMATION

Power estimation techniques Logic level power estimation Simulation power analysis
Probabilistic power analysis.
UNIT V
SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER

Synthesis for low power Behavioral level transforms- Software design for low power TOTAL : 45
REFERENCES
1. K.Roy and S.C. Prasad , LOW POWER CMOS VLSI circuit design, Wiley,2000
2. Dimitrios Soudris, Chirstian Pignet, Costas Goutis, DESIGNING CMOS CIRCUITS
FOR LOW POWER, Kluwer,2002
3. J.B. Kuo and J.H Lou, Low voltage CMOS VLSI Circuits, Wiley 1999.
4. A.P.Chandrakasan and R.W. Broadersen, Low power digital CMOS design,
Kluwer,1995.
5. Gary Yeap, Practical low power digital VLSI design, Kluwer,1998.
6. Abdellatif Bellaouar,Mohamed.I. Elmasry, Low power digital VLSI design,s Kluwer,
1995.
7. James B. Kuo, Shin chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits.
John Wiley and sons, inc 2001
35