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    ECE 429 - Introduction To VLSI Design Fall 2015

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    nithin s gowda
    This document provides information about the ECE 429 - Introduction to VLSI Design course offered in Fall 2015 including: - The instructor is Professor Ken Choi and the class meets Mondays and Wednesdays from 10:00-11:15 am in Life Science room 111. - Topics covered include MOS transistors, CMOS circuit design, layout, fabrication, and CAD synthesis techniques. - Student performance will be evaluated based on homework assignments, labs, a midterm exam, final exam, and class project.

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    ECE 429 - Introduction To VLSI Design Fall 2015

    Uploaded by

    nithin s gowda
    88 views2 pages
    This document provides information about the ECE 429 - Introduction to VLSI Design course offered in Fall 2015 including: - The instructor is Professor Ken Choi and the class meets Mondays and Wednesdays from 10:00-11:15 am in Life Science room 111. - Topics covered include MOS transistors, CMOS circuit design, layout, fabrication, and CAD synthesis techniques. - Student performance will be evaluated based on homework assignments, labs, a midterm exam, final exam, and class project.

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    ece429-syllabus-2015f

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    This document provides information about the ECE 429 - Introduction to VLSI Design course offered in Fall 2015 including: - The instructor is Professor Ken Choi and the class meets Mondays and Wednesdays from 10:00-11:15 am in Life Science room 111. - Topics covered include MOS transistors, CMOS circuit design, layout, fabrication, and CAD synthesis techniques. - Student performance will be evaluated based on homework assignments, labs, a midterm exam, final exam, and class project.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    88 views2 pages

    ECE 429 - Introduction To VLSI Design Fall 2015

    Uploaded by

    nithin s gowda
    This document provides information about the ECE 429 - Introduction to VLSI Design course offered in Fall 2015 including: - The instructor is Professor Ken Choi and the class meets Mondays and Wednesdays from 10:00-11:15 am in Life Science room 111. - Topics covered include MOS transistors, CMOS circuit design, layout, fabrication, and CAD synthesis techniques. - Student performance will be evaluated based on homework assignments, labs, a midterm exam, final exam, and class project.

    Copyright:

    © All Rights Reserved
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    ECE429 Fall 2015

    Prof. Ken Choi

    ECE 429 - Introduction to VLSI Design


    Fall 2015
    Instructor: Professor Ken Choi
    Office: 318 Siegel Hall
    Phone: 312 567-3461
    E-Mail: kchoi@ece.iit.edu
    Prerequisite: ECE 218 and ECE 311:
    Familiarity with circuits, logic and digital system design.
    Experience with CAD tools and UNIX is a plus.
    Class Time: Mon. and Wed.: 10:00 am. 11:15 am.
    Class Location: Life Science - Room 111
    Office Hours: Monday and Wednesday: 12:00-1:30 pm. SH 318 or available upon
    request by an email
    Class Home Page: http://my.iit.edu/ -> go to blackboard -> choose INTRO TO
    VLSI DESIGN
    Required Textbook: CMOS VLSI DESIGN: A Circuits and Systems Perspective (4th
    Ed.) Neil H.E. Weste, and David Harris, Addison-Wesley, 2009. ISBN-10: 0321547748
    Recommended books: Not required, hand-out will be given in the class if it is needed.
    Course Objective: To give students a clear understanding of the fundamental
    concepts of modern CMOS VLSI design. Students will learn the design of complex and
    high performance CMOS systems from system level to circuit level.
    Topics Covered: MOS transistors, static and dynamic behavior, stick diagrams, MOS
    circuit fabrication, design rules, resistance and capacitance extraction, scaling, logical
    effort, combinational and sequential design, data-path and control unit design, clocking
    schemes, memory design. CAD synthesis techniques, floorplanning and layout.
    Grading: Homeworks 10% / Midterm Exam: 15% / Final Exam: 30% / LABs and
    Project: 40% / Class Participation and Individual Meeting 5%
    Teaching Assistants: Yunlong Zhang (Lab-1) / Shuai Li (Lab-2,3) / Junchao
    Wang (Grader)
    Homework Policy: Homework is due at the start of class. Late homework will not be
    accepted. Working together on homework is encouraged, but copying assignments will
    call for disciplinary action. For the project, you may be asked to work in a group.
    Exam Policy: Makeup exams will not be given. The final is comprehensive.
    Lecture Schedule (tentative, Fall 2015):
    *Note: 9/7 (M): Labor Day, 10/12 (M): Fall Break - No Lecture & No Lab Sessions
    11/2 (M), 11/4 (W), 11/9 (M): No Lecture Classes
    (*Lab. Sessions will be continued)

    1/2

    ECE429 Fall 2015


    Date
    8/24, 8/26

    Prof. Ken Choi


    Related
    Chapters

    Topic
    Overview and VLSI Design Flow
    Design Methodology and Tools

    1.11.12
    14.1-14.5

    8/31, 9/2

    MOS Transistor Theory (Lab1 review,


    basic unix)

    2.1-2.6

    9/9, 9/14

    CMOS Fabrication, Layout, Processing


    Technology
    (Lab2
    Review,
    inverter
    schematic)

    1.5
    3.1-3.6

    9/16, 9/21

    Logical Effort (Lab3 Review, hspice)

    4.1, 4.5

    9/23, 9/28

    Delay Estimation (Lab4 Review, layout


    editor)

    4.2,
    4.3,
    4.4, 4.6

    9/30

    Power Estimation (Lab5 Review, CMOS


    design flow)

    5.1-5.5

    10/5

    Review for Midterm Exam

    Lab &
    Project Due

    HW#1-9/14
    (Due:9/21)

    Lab 1
    9/9(W),
    9/11(F),9/14(M)
    Lab 2
    9/16(W),
    9/18(F),9/21(M)

    HW#1-9/28
    (Due:10/5)

    Lab 3
    9/23(W),
    9/25(F),9/28(M)
    Lab 4
    9/30(W),
    10/2(F),10/5(M)
    Lab 5
    10/7(W),
    10/9(F),10/14(M
    on W)

    10/7
    10/14, 10/19

    Homework

    Midterm Exam
    Interconnect (Lab6 Review, CMOS logic
    gate design)

    6.1-6.5

    Lab 6
    10/16(F),
    10/19(W),
    10/21(M)

    10/21

    Robustness
    (Lab7 Review,
    addition and subtraction)

    bit-slice

    7.1-7.6

    Lab 7
    10/23(F),
    10/26(W),
    10/28(M)

    10/26

    Circuit Simulation (Lab8 Review, Verilog


    HDL)

    8.1-8.5

    Lab 8
    10/30(F),
    11/2(W),11/4(M)

    10/28

    Combinational Circuit Design (Lab9


    Review, Synthesis flow for D-register)

    9.1-9.6

    HW#310/28
    (Due:11/11
    )

    11/11

    Sequential Circuit Design

    10.1-10.7

    Project
    11/17
    (Due:12/4)

    11/16, 11/18

    Individual Student Meeting with Graded


    Midterm

    11/23

    Datapath Subsystems

    11.1-11.9

    11/30

    Array Subsystems (Memories)

    12.1- 12.8

    12/2
    12/7-12/12

    Review for Final Exam


    Final Exam (TBD)

    2/2

    Lab 9
    11/6(F),
    11/9(W),
    11/12(M)

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