Digital Logic Handbook 1972

o
handbook
1972
momoamB
handbook .
1972
digital equipment corporation

i
Copyright 1972 by
Digital Equipment Corporation
Digital Equipment Corporation makes no representation that the interconnection of its modular circuits
in the manner described herein will not infringe on
existing or future patent rights. Nor do the descriptions contained herein imply the granting of licenses
to make, use, or sell equipment constructed in accordance herewith.
Digitai Equipment Corporation is not responsible for
errors which may appear in the pricing, technical
descriptions, illustrations, or photographs of the
products appearing in this Handbook.
Digital Equipment Corporation reserves the right to
make- substitutions and modifications in the specifications of the products described in this Handbook.
Prices quoted are in U.S. dollars and apply to the
United States only. The availability of products listed
and the prices quoted herein are subject to change
without notice.
FLIP CHIP, UNIBUS and OMNIBUS are

trademarks of Digital Equipment Corporation,
Maynard, Massachusetts.
ii
This eighth edition of the LOGIC HANDBOOK is your guide to the most extensive line of products offered by Digital Equipment Corporation for implementing electronic logic designs for instrumentation, computer interfacing, data
gathering or control. This handbook is a basic reference for anyone involved
in specifying, manufacturing or using solid state logic.
Our M Series TTL integrated circuit modules are featured in this edition. The
M 'Series line consists of more than 100 modules ranging from basic and
functional logic modules to self contained computer interfacing modules and
the M Series Logic Lab for use in breadboarding M Series logic designs.
The impact of advancing technology can be seen in M Series evolution. From
the beginning, M Series was TTL-integrated-circuit oriented; the current
trend is toward MOS circuits, MSI and LSI. The result is more complexity
(and more built-in design solutions) per module. Many of the modules in
this handbook amount to full-scale digital subsystems. M1702, for example,
is a complete 12-word input interface that plugs directly into the PDP-8/ e
or 81m OMNIBUS structure.
This edition of the handbook also covers the A Series of analog modules,
the W Series of wire wrappable, collage and blank boards in the FLIP CHIP
form factor, and a complete line of power supplies and hardware. An expanded section on cabling and cable accessories has been added to simplify
system interconnection design. All these support functions provide a total
capability for designing, implementing, and assembling a modular system,
small or large, at the lowest cost per function in the industry.
In the historical modular concept conceived and perfected by DEC, innovation is balanced by performance and value, and the efficiency of highly
complex, specialized modules is complemented by a full array of basic building blocks. All tradeoffs and design decisions have been resolved by DIGITAL,
giving the designer and manufacturer the freedom to concentrate on the best
implementation of his control, instrumentation, or communications system.
Traditional products of the A, K, M, R, Band W product lines are still extensively used and fully supported by DIGITAL. Information on negative logic
R, Band W Series modules and the industrial-environment-oriented K Series
modules is available in previous editions of the Logic Handbook, the Control
Handbook and from Logic Products sales support personnel.
iii
Extensive non-catalog products and services are available from DIGITAL. If,
you require unique functions that are not listed in this handbook, contact
your local DEC office (listed inside the back cover). The product you need
may be available as a non-catalog item. In addition, DIGITAL maintains a
Special Module Products Group with complete capability of design, layout,
manufacturing and test. Custom product capability is not limited to modules
alone but extends to the support hardware and accessories, including cabling,
wire wrapping and cabinets.
A worldwide staff of DIGITAL sales engineers is prepared to respond to your
technical and commercial needs. From a backlog of -logic system design experience, DIGITAL may have a detailed solution to your application or interface requirement.
Please address any comments on this handbook or inquiries concerning
special services to:
.Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754
Atten: Logic Products
Sales Support Manager
iv
............... .,.................................................................................
iii
INTRODUCTION ... ....... ............. ...... ......... ................................ ..... ....... ......
vii
Foreword
Organization of Handbook .......................................................... ...... vii

M Series Module Selector Guide ...................................................... viii
Digital Equipment Corporation Engineering Services ........................ viii
Special Symbols and Abbreviations .................................................. viii
M SERIES LOGIC AND CONTROL MODULES ............................................
List of Modules ...............................................................................

Standard Module Dimensions ..........................................................
Extended Module Dimensions ..........................................................
General Characteristics ....................................................................
Module Descriptions ........................................................................
5
7
8
27
M SER'IES MODULES FOR COMPUTER INTERFACING ............................ 119

OMNIBUS and, UNIBUS Interface Modules ......................................
OMNIBUS/UNIBUS Electrical Characteristics ..................................
External I/O Bus (Positive logic) ....................................................
Negative Bus .... , . ............. ........ ... ..... ........ .. ....... .......... ......................
PDp15 Bus ......................................................................................
Module Descriptions ..........................................................................
121
122
126
128
128
129
A SERIES ANALOG MODULES .................................................................. 225

Notes on Operational Amplifiers ......................................................
2" and Resolution ...................................................................... ......
Digital Codes for A/ D's, 0/ A's, and Data Acquisition Systems ........
Module Descriptions .. ~.....................................................................
227
234
235
236
ACCESSORY MODULES ............................................................................ 295

Wire Wrappable Module Boards ........................................................
Collage Mounting Boards ..................................................................
Blank Modules ......................................................................... .........
Module Extenders ............................................................................
Bus Connectors ................................................................................
297
303
304
308
311
POWER SUPPLIES ........................................ ............................................. 313

Power Supplies and Accessories Summary ...................................... 314
Power Supply Descriptions ............................................................. 315
CABLES AND ACCESSORIES .................................................................... 337

Standard Cables ................................................................................ 339
Cable Connectors .............................................................................. 349
I/O Connectors ................................................................................ 370
HARDWARE .............................................................................................. 373
Connector Blocks ..............................................................................
Mounting Panels ..............................................................................
Module Drawers ................................................................................
Mounting Panel Frames ....................................................................
Cabinets ............................................................................................
Wire Wrapping Service ......................................................................
Accessories ........................................................................................
376
383
394
397
399
418
422
LAB SERIES .............................................................................................. 431

Computer lab .................................................................................. 432
K Series logic lab ............................................................................. 435
M Serie$ lab .................................................................................... 443
ABOUT DIGITAL EQUIPMENT CORPORATION .......................................... 447
General Description of DEC Products ..............................................
Warranty Statement and Discount Schedule ......... ,..........................
Product Index ....................................................................................
Page Index ........................................................................................
vi
450
452
453
473
ORGANIZATION OF HANDBOOK
This edition of the lOGIC HANDBOOK is organized in eight functional sections for maximum ease of reference. Within each section, module descriptions are presented in alphanumeric order by module designation. To locate
a specific module, consult the Product List at the end of the handbook.
Loeic and Control: This section includes all of the M Series basic logic modules and those complex functional modules that are not computer-interface
oriented. An introduction to this section describes the basic characteristjcs
of the TTL integrated circuits which are the principal active elements of
M Series.
Computer Interfacing: This group includes the M Series complex function~
modules that simplify interfacing to the PDpll UNIBUS or PDP-S/e, S/m
OMNIBUS. Also in this group are the modules for interfacing the external
1/0 bus of earlier PDP-S family computers plus level converters and other
interface-oriented support modules. Introductory information defines the control and data signals of the OMNIBUS, UNIBUS, and external I/O bus.
Analog: The A Series of analog modules supports the M Series by providing
a two-way translation between continuously varying realworld voltage measurements and the digital realm of control and computation. The present
A Series emphasizes 10- and 12-bit performance in a family of mutually
compatible functions-multiplexers, operational amplifiers, sample-and-hold
circuits, D/ A and A/ [) converters, reference voltage sources and an expanded
group of multiplying 0/ A converters.
Accessory Modules: DEC offers a wide line of wire wrappable, collage, and
blank modules in the FLIP CHIP form factor for experimenting and breadboarding by users who want to work directly with discrete components and
integrated circuit packages. Included in this section are module extenders
and PDP-Sf e, 8/ m OMN IBUS bus connectors.
Power Supplies: This section describes a wide selection of Hand K Series
dc power supplies for small and large systems. Summary tables are included
that will help the system designer select the power supply appropriate to his
system.
Cabling: This edition of the handbook presents a greatly expanded section

on M and W Series cables and cabling accessories. DEC offers a complete
line of prefabricated cables for interconnection of free-standing logic systems
as well as computer-based installations. Bulk cable and cable cards are
available so that the. user can design and contruct his own custom interconnections with a minimum of custom design and planning.
Hardware: DEC makes a complete line of hardware accessories to support
its module series. Module connectors are available for as few as one module
to as many as 64 in a single 19 u mounting panel. A complete line of
cabinets is available to house the modules and their connector blocks, as
well as provide a convenient means for system expansion. Wiring accessories
and a complete selection of support hardware simplify all phases of physical
construction. This edition's hardware selection is expanded to include the
latest cabinet and hardware features.
vii
Lab Series: This group includes the COMPUTER LAB digital logic trainer, the
K Series logic lab (a rack-mounted, plugboard-panel breadboarding and
training facility for K Series modules) and the M Series logic lab (a console
and rack structure that mounts and interconnects M Series modules for
training, experimentation, and system design).
M SERIES MODULE SELECTOR GUIDE
Available as a companion to this handbook is the M Series Module Selector
Guide, a pocket-sized chart that is used for a quick look-up of the characteristics of the M Series modules and the most important supporting hardware and accessories and power supplies in this handbook. Contact your
local DIGITAL Sales Office for a free copy of the Module Selector Guide.
DIGITAL EQUIPMENT CORPORATION ENGINEERING SERVICES

In addition to supplying a complete line of standard and special hardware
and accessories, Digital Equipment Corporation also provides an engineering,
design and manufacturing service in support of customer applications. These
services are available upon request and consist of the following:
Special logic Modules: Many of the same advanced manufacturing and testing techniques which DEC employs to produce its standard modules are
applied to building special modules. DEC engineers can provide full module
design and development services or they can work with user-supplied drawings and parts lists, depending upon user needs.
Wire Wrapping: Using the latest in automatic wire wrapping equipment, DEC
can efficiently wire and check connector panels according to customersupplied wire list and specifications.
Special Cables: When standard cables and cable lengths are not applicable
to customer requirements, DEC offers a complete cable fabrication service
to build special cables according to customer specifications.
Interface Design: DEC maintains a staff of experienced applications engineers who are capable of designing or providing design information for interfacing DEC computers to custom control systems and equipment.
Logic Arrays: Special-purpose logic systems can be efficiently designed and
built from customer-supplied data_ DEC's capability extends from limited
production system to high-volume production and insures both optimum
design and high reliability at a reasonable cost to the customer.
SPECIAL SYMBOlS AND ABBREVIATIONS

Logic symbols used in this handbook conform, in general, to widely accepted
Mil standards. All basic M Series logic symbols (AND, OR, NAND, NOR,
Inverter, Flip-Flop) are described in the introduction to the M Series togic and
control modules.
Input loading and Output Drive

On the logic diagrams of this handbook, input and output loading, expressed
in TIL unit loads, appear in boxes terminating each input or output signal
line. In the 2input NAND gate example of Figure I, both inputs (pins Al
and 81) present one TIL unit load. The output (pin CI) is capable of driving
10 TIL unit loads. The arrows eliminate any possible confusion as to the
direction of signal flow.
viii
INPUT LOADING
PIN NUMBER
It TTL UNIT LOADY(PINA,SIDEII
~:: ~_~"'::C1;.:..Fu'llW"l.OAOS'
ARROWS SHOW DIRECTION
Of SIGNAL FLOW
Figure 1.
logic Diagram Input loading and Output Drive Symbols
Bus DrIvers and Receivers

Drivers and receivers that transfer data along the bidirectional transmission
lines of the PDP-8/e, 8/m OMNIBUS or the PDP-ll UNIBUS differ somewhat
from similar TTL NAND gates or inverters. Typical examples are shown in
Figure 2. The "s" in the loading box indicates that the driver or receiver
circuit is to be connected to an OMNIBUS or UNIBUS signal or control line.
In this application, unit loading need not be considered. "R" identifies a line
receiver and "0" identifies a line driver. Inputs to line receivers or drivers
may also be standard TTL levels, in which case, TTL unit loads are shown
.as usual in the loading box.
!!lBt
1
~
B
7 GATED BUS
RECEIVER
El
B U2
DATA FROM
BUS
DATA
TO
BUS
DRIVE
TO BUS
READ
FROM BUS
TYPICAL BUS TRANSCEIVER ARRANGEMENT
Figure 2.
Sus Driver and Receiver Symbols
Electrical characteristics of these circuits are described in the introductionto M Series Computer Interfacing Modules.
ix
Level Converters
Whenever logic levels are translated from one set of voltages to another, the
conversion is shown taking place in a square level-converter symbol. Inside
the box, the corresponding logic levels are related in a simple truth table.
The example of figure 3 shows a level converter stage that accepts TIL
levels (LOW and HIGH) and delivers DEC negative voltage levels (-3 V and
ground).
Input loading is two TIL unit loads. Whenever loading is peculiar, it is defined in a note on the drawing as in the output of figure 3.
rzt02 _
n. _
01
~
*'SINKS 20mA AT GROUND
figure 3.
Typical Level Converter
Special Analog Symbols

Symbols used on analog circuit drawings to represent multiplex switches and
operational amplifiers are shown in figure 4. Loading boxes for analog inputs
and outputs contain the letter "A"; do not connect such signals to logic
levels.
MULTIPLEX SWITCH (MOS FET)
CONSTANT IMPEDANCE MULTIPLEX SWITCH
~---.0
LOGIC
CONTROL
INPUT
C~r-Y
INPUT
OPERATIONAL AMPLIFIER
figure 4.
Special Analog Symbols
Signal and Function Names

Inputs and outputs of M Series logic modules may be assigned a signal
name, a function name, or both. (See figure 5.) Signal names appear outside blocks or logic symbols to identify typical input or output signals.
_ - - - - - - S I G N A L NAMES - -_ _ _ _ __
> - _ - - - - - + -___-.:...~.~BTP3 H
~~~I----------~
INlnAUlE
H~L---t-G>--I--~-f ~.'N'T
L-f:>o-+~BINIT
I
(PART OF M1510)
t-'--"-~lJ~~R
~_~_<lUPL
(PART OF M236)
ON H
~_----lENABLE
1 AI
H .
COUNT IN H
Figure 5.
Signal and Function Names
Digital Equipment Corporation uses standard terminology to name signal

lines to aid the reader in determining their active state. Either an H or l
follows the signal name mnemonic, separated by a space. This letter indicates --the asserted (true) state of the signal. An H means the signal is asserted when HIGH (+3 V) and an l means the signal is asserted when lOW
(0 V). for example, a UNIBUS data line is called BUS 000 L and' a grant
line is called BUS BG4 H.
On the logic diagrams of many computer interfacing modules in this handbook, signal names peculiar to one computer, such as the PDP-II, appear
as an example of typical usage. Signal names may be changed to those of
another computer or interfacing device if logically appropriate.
function names appear inside the blocks of functional modules. They identify the function of input or output signals. The user may add his own signal
names.
Abbreviations
Abbreviations used in signal and function names in this handbook are defined in Table 1.
xi
Table I-Abbreviations
ABBREVIATION
DEFINITION
ALTN
Alternate
AMPL
Amplifier
ANLG
Analog
BPS
Bits Per Second
CAP
Capacitor
CLR
Clear
CMPR
Compare
COM
Common
CONT
Control
CVRSN
Conversion
DAC
Digital to Analog Converter
EXT
External
GND
Ground
High (TTL +3 V Logic Level)
INIT
Initialize
INT,INTR
Interrupt
INTL
Internal
Low (TTL 0 V Logic Level)
OUT
Output
P.1.
Program Interrupt
POT
Potentiometer
PRGM
Program
REF
Reference
RTN
Return
SER
Serial
S.H.
Sample and Hold
TRIG
Trigger
xii
m~
logic and
control modules
DEC Module ass~mbly lines combine automated manufacturing

steps with visual Inspection and computer controlled testing.
MSERIES LOGIC AND CONTROL MODULES

Modules in this section appear in numerical order. The six functional cate
gories of MSerie, logic and control modules are:
GATES
MIll
M112
MIl3
MIl5
M117
MIl9
M121
M133
M141
M160
M169
M610
MII03
M1307
Inverters
NOR Gates
NAND Gates
NAND Gates
NAND GATES
NAND Gates
AND/NOR GATES
Input NAND Gates
NAND/OR Gates
AND/ NOR Gates
Gating Module
Open Collector N'AN D Gates
AND Gates
AND Gates
FlIPFLOPS
M202
M203
M204
M205
M206
M207
M208
M232
Triple JK FlipFlop
8 R/S Flip-Flops
GeneralPurpose Buffer & Counter
General-Purpose FlipFlops
GeneralPurpose FlipFlops
GeneralPurpose Flip-Flops
8Bit Buffer/ Shift Register
16Word RAM
TIME RELATED
M302
M306
M310
M360
M401
M403
M404
M405
M410
M452
M501
M521
M602
M606
M671
Dual Delay Multivibrator

Integrating One Shot
Delay line
Variable Delay
Variable Clock
RC Multivibrator Clock
Crystal Clock
Crystal Clock
Reed Clock
Variable Clock
Schmitt Trigger
K to M Converter
Pulse Amplifier
Pulse Generator
M to K Converter
NUMERIC
MI59
MI61
Ml62
Ml6S
M230
M236
M237
Arithmeticl Logic Unit

Binary to Octal Decimal Decoder
Parity Circuit
12Bit Magnitude Comparator
Binary to BCD & BCD to Binary Converter
12Bit Binary Upl Down Counter
3nigit BCD Upl Down Counter
LOGIC AMPLIFIERS
M040
M050
M617
M627
M660
M661
Solenoid Driver
Indicator Driver
4input Power NAND Gates
NAND Power Amplifier
Positive Level Cable Driver
Positive Level Driver
MISCELLANEOUS
M002
M261
M262
M706
M707
M906
M7390
Logic HIGH Source

4State Motor Translator
IOState Motor Translator
Teletype Receiver
Teletype Transmitter
Cable Terminator
Asynchronous Transceiver
M Series modules contain high speed TTL logic in both general purpose and
functional logic arrays. TTL was chosen for its high speed, capacitance drive
capability, high noise immunity and choice of logical elements. High per
formance integrated circuit modules are now available at approximately one
half the price of their discrete or hybrid counterparts.
In addition to the reduced cost of integrated circuits, Digital's advanced
manufacturing methods and computer controlled module testing have resulted in considerable production cost savings, reflected in the low price of
all M Series Modules.
STANDARD MODULE DIMENSIONS
SINGLE-WIDTH FLIP CHIP MODULE
CONDUCTIVE COMPONENT LIMIT
NONCONDUCTIVE
1~32
0.056"
~PO!i~T~ !/i ~x.
~~~~======~SI~~~l~========i===~=a1-U
i t
It~
SIDE 2
GOLD-PLATED CONTACTS
MAXIMUM HEIGHT
OF SOLDERED
~ENT LEADS
ETCHED WIRING SURFACE
SINGLE-HEIGHT FLIP CHIP MODULE
~~-=-==-==--~-- -: = ;:=:-r-'~"= ;r;:-,~o~

Sl~
2.187*
~::::::::~--- 3.875*'-----+--~
o
.045"
,080"
72_5_"~
I~
~IOII""'------- 5~2
rlool
.....
_____ 5
*=MAXIMUM USEABLE COMPONENT AREA
-I.~I
TY
_ _ _ _1/_8__ P._'
DOUBLE WIDTH FLIP CHIP MODULI
CONDJCTIVE COMPONENT
LIM~::~ _ _ _ _ _......,
0.056
27/32mox.
NONCONDUCTIVE
COMPONENTS
SIDE 1
''t6 MAXIMUM HEIGHT OF

SOLDERED COMPONENT
LEADS
SI 2
DOLSLE HEIGHT FIrIP CHIP MODULE
.----.080
.045
0.099
-;;:;:---
==~~=~~==~!~
------
------.,
AD
AE
AJ
:~
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2.240
AR
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1
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3.87!5"
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Y64
.......- - - - - - - - 5 ~2
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_____ 1
~8 TYP,
.......- - - - - - - 5
... MAXIMUM USEABLE

COMPONENT AREA
. 9 37*
IP
.725
EXTENDED MODULE DIMENSIONS

SINGLE-WIDTH FLIP CHIP MODULE
CONDUCTIVE COMPONENT LIMIT 1~32
0.056
NON CONDUCTIVE COMPONENTS
~~~====~SI~DE~'~===t E=~~~$3LL~
=r
SIDE 2
~t6 MAXIMUM
HEIGHT
OF SOLDERED
COMPONENT LEADS
SINGLE-HEIGHT FLIP CHIP MODULE
0.099
-==+===:;===*==1;;;;;;;;:;;;;;;;;;:;
A- - B
C
D
- -
---
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F
2~6 2.240
K
L
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SIDE 2
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=*=I:::::::::::::::Iuv _ _ _ _ _ _ _ _
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.oeo
__ Jo
I/e TYP.
.....------e~
~-------------e1~6---------------~
DOUBLE WIDTH FLIP CHIP MOOI..l.E
CONDUCTIVE COMPONENT LIMITS "".

~--------.
27/32 max.
NONCONDUCTIVE
COMPONENTS
SIDE I
SIDE 2
GOLD- PLATED CONTACTS
~MAXIMUM HEIGHT OF
SOlDERED COMPONENT
LEADS
DOUBLE HEIGHT FLIP CHIP MODULE
r----.080
.045
0.099
~----
==~==~====~!~
AD
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AF
At!
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2.240
AL
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SIDE 2
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8K
8L
8M
8N
BP
aR
as
aT
au
8~
_____ _
~8
.........----8'/2
. . MAXIMUM USEABLE
COMPONENT AREA
TYP.
I
II
~---------------8'~6--------------~
.080
.045
0.099
-----
---,
I
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I
I
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10.436
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10.t87*
SlOE 2
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OF
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DP
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OS
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DU
DV_ _ _ _ _ _ _ _
0.099~
.1
*- MAXIMUM
USEABLE
COMPONENT AREA
DEC has more than 1.5 million square feet of manufacturing space. This view
shows a portion of a module assembly area.
10
GENERAL CHARACTERISTICS
M Series high-speed, monolithic integrated circuit logic modules employ TTL
(transistor-transistor logic) integrated circuits which provide high speed,
high fan out, large capacitance drive capability and excellent noise margins.
The M Series includes a full digital system complement of basic modules
which are designed with sufficient margin for reliable system operation at
frequencies up to 6 MHz. Specific modules may be operated at frequencies
up to 10 MHz. The integrated circuits are dual in-line packages.
The M Series printed circuit boards are identical in size to the standard
FLIP CHIPTM modules. The printed circuit board material is double-sided providing 36'pins in a single height module. Mounting panels (H910 and H911)
and 36-pin sockets (HS03 and HSOS) are available for use with M Series
modules. Additional information concerning applicable hardware may be
found in the Power Supply & Hardware and Accessories section of this
handbook.
M Series modules are compatible with Digital's K Series and, through the
use of level converters, are compatible with all of Digital's other standard
negative voltage logic FLIP CH IP (Ii) modules.
TIL NAND GATE

The basic gate of the M Series is a TTL NAND GATE. Figure 1 is the basic two
input NAND gate schematic diagram. The circuit is divided into 3 major
sections, the multiple emitter input, the phase splitter and the totem pole
output circuit. The two diode model of a transistor shown in Figure 2 will be
used in the analysis of the circuit. A forward biased silicon junction (Le. diode)
gives a voltage drop of about 0.75 volts and a saturated silicon transistor has
a collector emitter voltage of 0.4 volts average. These two figures will be used
throughout the following discussion.
With either input at the La logic level (O.OV-O.SV) the multiple emitter input
transistor will be ON with its base residing at about 0.75
0.4
1.15 volts.
The three diode string consisting of QI'S base collector diode, Q2'S base emitter diode, and Q/s base emitter diode will haye only 1.15 volts across it and
will therefore be conducting only leakage currents (0.75 + 0.75
0.75
2.25 volts required for forward bias). With no current flowing into the base
emitter junction of Q2, the transistor will be OFF and its collector emitter
voltage is alowed to rise. Similarly with no current flowing in the base emitter
diode of Q4 the transistor is OFF and its collector emitter voltage is allowed
to rise. When both Q2 and Q4 are OFF, QJ is freed to pull the output voltage to
a HI level. The voltage levels present in the circuit with one or more lO. inputs is shown in Figure 4.
If both inputs are HI (2.4-3.6 volts) the head of the three diode string will reside at about 2.25 volts and there will be a current path from the 4K base
resistor on the input transistor through the diode string to ground as shown
in Figure 5. With current flowing in the base emitter junctions of both Q2 and
Q4, both transistors will be turned ON. QJ is held OFF whenever Q2 is ON. The
output is driven LO (0.OV-0.4V) by transistor Q4. The voltage levels present in
the circuit with both inputs HI and are shown in Figure 6.
11
~------------,-----------,-------------+5V
Ql
INPUT A ----~_t:....~)'---_ti
Q2
--------------~T
INPUT B - - - - - - - - '
Q4
IK
~--------~~------------~
____
__-----J
~~----J~~----~-----J,\~---MULnPLE
TOTEM
PHASE
EMITTER
POLE
SPl..ITTER
OUTPUT
INPUT
Figure 1
TTL NAND Gate Schematic Diagram
COUECTOR
lASE
eASE
I>
EMITTER
Figure 2
Two Diode Model For Transistor
QUE
INPUT A
N"UT B (LOW)
Figure 3
Q48E
---~IO-""::'=~------*"-i----otf------4~------,
I
t
L.: _ _ _ _ _ _ _ _ _ .J
Diode Equivalent NAND Gate Circuit. One Input LO
12
!III
4K
130....
1.6K.
03
INPUT A
HIGH
3.511
INPUTB
LOWIO.411)
04
______
-----/~'-----~--~
MULTIPLE
EMITTER
IfIIPIJT
Figure 4
OUTPUT
TOTEM
PHASE
POLE
SPUTTER
O\ITPUT
TTL NAND Gate Schematic Diagram. One Input LO
+ !ill
INPUT B ~HI;.:;GHc:..-IO-_ _'"
Figure 5
Diode Equivalent NAND Gate Circuit. Both Inputs HI
+511
I.GK
4K
I30A
03
INPUT A
HIGH 12.4V)
0.4V
OUTPUT
INPUT B
HIGHC2.4VI
04
_______-----/l~--....._---"~
MULTIPLE
EMITTER
PHASE
SPUTTER
INPUT
Figure 6
TOTEM
POlE
OUTPUT
TTL NAND Gate Schematic Diagram. Both Inputs HI
13
,.
OPERATING CHARACTERISTICS
Power Supply Voltage: 5 Volts 5%
Operating Temperature Range: 0 to 70C
Speed: M Series integrated circuit modules are rated for operation in a system environment at frequencies up to 6 MHz. Specific modules may be operated at higher frequencies as indicated by the individual module specifications.
LOGIC LEVELS AND NOISE MARGIN
A gate input will recognize 0.0 volts to 0.8 volts as logical LO and 2.0 volts
to 3.6 volts will be recognized as a logical HI. An output is between 0.0 volts
and 0.4 volts in the logical LO condition. The logical HI output condition is
between 2.4 volts and 3.6 volts. Figure 7 shows diagrammatically the acceptable transistor-transistor logic levels. The worst case noise margin is 400
millivolts that is, an output would have to make at least a 400 millivolt excur
sion to cause an input which is connected to it to go into the indetermined
voltage region. For instance if an output were at 0.4 volts (worst case logical
LO) there would have to be a
400 mv swing in voltage to cause inputs
connected to it to go into their indetermined region.
Input and Output Loading: The input loading and output drive capability of
M Series modules are specified in terms of a specific numDer of unit loads.
Typically the input loading is one unit, however certain modules may contain
inputs which will, present greater than one unit load. The typical M Series
module output will supply 10 unit loads of input loading. However, certain
module outputs will deviate from a 10 unit load capability and provide more
or less drive. Always refer to the individual module specifications to ascer
tain actual loading figures.
Unit Load: In the logic 0 state, one unit load requires that the driver be able
to sink 1.6 milliamps (maximum) from the load's input circuit while main
taining an output voltage of equal to or less than +0.4 v(!)lts. In the logic 1
state, one unit load requires that the driver supply a leakage current 40
microamps (maximum) while maintaining an output voltage of equal to or
greater than +2.4 volts.
Timing: M Series pulse sources provide sufficient pulse duration to trigger
any M Series flip-flop operating within maximum propagation delay specifi
cations. Detailed timing information appears later in this section and in the
module specifications.
14
Figure 7
logic levels
NAND Logic Symbol: logic symbology used to describe M Series modules is

based on widely accepted standards. logic symbols and a truth table for the
NAND gate are shown in Figure 8.
A~-OUTPUT
OUTPUT
B~A.B
A~
O'-lTPUT
B~i+B
Figure 8
NAND Gate logic Symbol and Truth Table
The first symbol is visually more effective in applications where two high inputs are ANDed to produce a low output. The second symbol better represents an application where low inputs are ORed to produce a high output.
TTLAND/NOR GATE
With afew modifications, the basic TTL NAND gate can perform an AND/
NOR (unction useful in exclusive OR, coincidence, line selection and NOR
gating operations. The modified circuit is shown in simplified form in Figure 9.
15
r-----~----_1------------._------_O
. _ - -........_ 0
+vcc
OUTPUT
Figure 9
TTL AND/NOR Gate Simplified Schematic
Circuit Operation: The basic elements of the TTL NAND gate are used without modification. The phase-splitter (Q2) is paralleled with an identical
transistor (Q6), also controlled by multiple-emitter input transistor which
receives two additional inputs, C and D. When either of the input pairs are
high, the phase inverter operates to switch the output voltage low_ Circuit
performance is essentially identical to the TTL NAND circuit.
AND/NOR logic Symbol: The logic symbols for the AND/NOR gate are shown
and defined in Figure 10.
:~OUTPUT
c
AB+CD
ANY
A~
~
Figure 10
OUTPUT
IA+B1IC +01
ANY
H
'H
OUTPUT
L
H
L
H, L
AND/NOR Gate logic Symbols and Truth Table
NOR Configuration: The AND/NOR gate can perform a straight NOR function
if the AND gate inputs are tied toget"er as shown in Figure 11.
16
:~OUTM
:=D-
ANDI NOR INPUTS TIED
Figure 11
OUTPUT
RESULTING NOR SYMBOL
NOR Connection of AND/NOR Gate
NAND GATE FLlPFLOPS
RS FllpFlop: A basic Reset/Set flip-flop can be constructed by connecting

two NAND gates as shown in Figure 12.
SET---Q
RESET---Q
PREVIOUS
STATE
INPUT
CONDITION
SET
RESET
H
L
L
H
RESULT
H
H
NO CHANGE
NO CHANGE
L
H
L
H
H
L
NO CHANGE
NO CHANGE
L
L
L
L
L
L
H
H*
H*
Ambiguous state: In practice the input that stays low longest will assume
control.
Figure 12
RESET/SET NAND Gate Flip-Flop
CLOCKED NAND GATE FLlpFLOPS
The Reset-Set flip-flop can be clock-synchronized by the addition of a twoinput NAND gate to both the set and the reset inputs_ (See Figure 13.) One
of the inputs of each NAN 0 is tied to a common clock or trigger line.
SET
CLOCK
o
RESET
Figure 13
Clocked NAND Gate Flip-Flop
17
A change of state is inhibited until a positive clock pulse is applied. The

ambiguous case will result if both the set and reset inputs are high when the
clock pulse occurs.
M SERIES GENERALPURPOSE FLlpFLOPS
Two types of general-purpose flip-flops are available in the M Series, both of
which have builtin protection against the ambiguous state characteristic of
NAND gate flipflops.
FLlPFLOP CLOCK INPUT SYMBOLS
The D type flip-flop is a true leading (positive going voltage) edge triggered
flipflop and the D input is locked out until the clock input returns to low. The
symbol to indicate this function will be as follows;
o TYPE
FLIP FLOP CLOCK
The operation of the J-K type flip-flop is to transfer the information present
at the J and K inputs just prior to and during the clock pulse to the master
flipflop when the threshold is passed on the leading (positive going voltage)
edge of the clock pulse. The information stored in the master flip-flop is
transfered to the slave flipflop. and consequentially to the outputs, when
the threshold is passed on the trailing (negative going voltage) edge of the
clock ~ulse. The symbol to indicate this function will be as follows;
J K TYPE FL I P FLOP CLOCK
o Type
F1ipFlop: The first of these is the D type flip-flop shown in Figure 14/
In this element, a single-ended data input (D) is connected directly to the
set gate input. An inverter is provided between the input line (D) and the
reset input. This ensures that the set and reset levels cannot be high at the
same time.
LOGIC SYMBOL
18
$ (DC SET)
,------
--,
D-----~-----------~
(SET)
C----+----------+
(CLOCK)
I
I
>---+-~-O
_ ___ --.J
L_
R (DC RESET!
NAND GATE EQUIVALENT
SIMPLIFIED NAND GATE EQUIVALENT
Figure 14. D Type General Purpose Flip-Flop
The flip-flop proper employs three-input NAND gates to provide for de set
ard reset inputs.
D type flip-flops are especially suited to buffer register, shift register and
binary ripple counter applications. Note that D type devices trigger on the
leading (or positive going) edge of the clock pulse. Once the clock has passed
threshold, changes on the D input will not affect the state of the flip-flop due
to 8 lockout circuit (not shown).
A characteristic of the 0 type flip-flop which is not illustrated in the
NAND gate equivalent circuit is the fact that the D input is locked out after
the clock input threshold voltage on the leading (positive going voltage)
edge of the clock has been passed. The D input is not unlocked until the
clock input threshold voltage of the trailing (negative going voltage) edge
has been passed.
19
"MASTERSLAVE JK FLlpFLOP"
The two unique features of a J-K flip-flop are: A) a clock pulse will not cause
any transition in the flip-flop if neither the J nor the K inputs are enabled
during the clock pulse, and B) if both the J and the K inputs are enabled
during the clock pulse, the flip-flop will complement (change states). There
is no indeterminate condition in the operation of a J-K flip-flop_
A word of caution is
must not be allowed
will complement on
for this reason that
transfer information
and K inputs should
in order concerning the clock input. The J and K inputs

to change states when the clock line is high, the output
the negative going voltage transition of the clock. It is
the clock line must be kept .Iow until it is desired to
into the flip-flop and no change in the states of the J
be allowed when the clock line is high.
The J-K flip-flops used are master-slave devices which transfer information
to the outputs on the trailing (negative going voltage) edge of the clock
pulse. The J-K flip-flop consists of two flip-flop circuits, a master flip-flop
and a slave flip-flop. The information which is present at the J and K inputs
when the leading edge threshold is passed and during the clock high will be
passed to the master flip-flop (The J and K inputs must not change after the
leading edge threshold has been passed). At the end of. the clock pulse when
the threshold of the clock is passed during the trailing (negative going
voltage) edge, the information present in the master flip-flop is passed to
the slave flip-flop_ If the J input is enabled and the K input is disabled prior
to and during the clock pulse, the flip-flop will go to the "1" condition when
the trailing edge of the clock occurs. If the K input is enabled and the J input
is disabled prior to and during the clock pulse, the flip-flop will go to the
"0" condition when the trailing edge of the clock pulse occurs. If both the
J and K inputs are enabled prior to and during the clock pulse, the flip-flop
will complement when the trailing edge of the clock pulse occurs. If both the
J and K inputs are disabled prior to and during the clock pulse, the flip-flop
will remain in whatever condition existed prior to the clock pulse when the
trailing edge of the clock pulse occurs.
J INPUT
---+--f
t OUTPUT
CLOCK
o OUTPUT
K INPUT
--t---;
Figure 15. Master-Slave J-K Flip-Flop
20
Figure 16 shows a functional block diagram of 8 master slave J-K flip-flop

using NAND gates. Gates C and D are the master flip-flop. Gates' G and Hare
the slave flip-flop. Gates A and 8 are the steering .network of the master
flip-flop and the steering network for the slave flip-flop is comprised of gates
E, F, and 1. The 1 output of the master flip-flop is point X. The operation of the
flip-flop will be studied by examining the "I" to "0" transition of the flipflops, with both the J and the K inputs enabled with a HI level before the
clock pulse. When the leading edge of a HI clock pulse occurs, gate B wi" be
enabled with three HI inputs. This will provide a RESET signal for t~e master
flip-flop which will then go to the ~'O" condition. The slave flip-flop remains
in the "1" condition while the clock pulse is HI because gate I is providing
a LO signal to both gates E and F, thereby blocking inputs to the slave flip-flop.
When the trailing edge of the clock pulse occurs, gate F will be enabled with
a HI level at both its inputs and a RESET signal will be provided to the slave
flip-flop, which will then go to the "0" condition. The next clock pulse, with
both the J and K enabled, would cause the master flip-flop to go to the "1"
condition on the leading edge of the clock pulse and cause the slave flip-flop
to go to the "1" condition on the trailing edge of the pulse. Figure 16 is a
truth table for the J-K flip-flop showing all eight possible initial conditions_
INITIAL CONDITIONS
OUTPUTS
INPUTS
FINAL CONDITIONS
OUTPUTS
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
H
H
H
L
H
L
H
H
L
L
L
H
L
H
Figure 16. Master-Slave J-K Flip-Flop Truth Table
21
UNUSED INPUTS (GATES AND FLfPFLOPS)

Since the input of a TTL device is an emitter of .a multiple-emitter transistor,
care must be exercised when an input is not to be used for logic signals.
These emitters provide excellent coupling into the driving portions of the
circuit when left unconnected. To insure maximum noise immunity, it is
necessary to connect these inputs to a source of Logic I (High). Two methods
are recommended to accomplish this:
1.
Connect these inputs to a well filtered and regulated source of +3 volts.

Pins UI and VI are provided on the MIl3, MIl7, M1l9, M121, M617, and
M627 for this purpose.
2.
Connect these inputs to one of the active inputs on the same gate. This
results in a higher leakage current due to the parallel emitters and
should be considered as an additional unit load when calculating the
loading of the driving gate.
Connection of unused inputs to the supply voltage, Vcc, is not advisable,

since power supplies are subject to transients and voltage excursions which
could damage the input transistor.
TIMING CONSIDERATIONS
Standard Timing Pulse: In digital system design, a reference for system

timing is usually required. The M Series modules M401 or M405 produces a
standard pulse which provides such a reference. The standard pulse derived
from each of these two modules is shown in Figure 17.
Tf- T,.15nsee. NOM.

Tp .50nsee, NOM. (M401,M602)
-ll0nsee. NOM. (M602 OPTION)
+3.0 j:O.6V -
......- -__ Tp _ _ _......"
+0.4
00 -O.OV -
I
-,- -
-:- I
I
- -
+1.5V NOMINAL
10%
J. THRESHOLD
.I- _ _ _ _ _L 1 ____ , _ -L POINT
~Tf...J
l.-Tr~
Figure 17. Standard Pulse
22
NAND Gate and Power Amplifier Propaptlon Delays: The standard pulse
(Figure 17) is distributed throughout a system in negative form to maintain
the leading edge -integrity. (Since the TIL gate drives current in the logic
o state, the falling edge is more predictable for timing purposes.) However,
the standard pulse is of the wrong polarity for use as a clocking input to
the type D and JK flip-flops, requiring the use of a local inverter. Ordinarily,
a NAND inverter is adequate. Where high fan-out is necessary, a M617
Power NAND is preferred.
For applications requiring both high fan-out and critical timing the M627
Power Amplifier is available. This module contains extremely high-speed
gates which exhibit turn-on times differing by only a few nanoseconds.
Simultaneity is desirable in clock or shift pulses distributed to extended
shift registers or synchronous counters.
Delays introduced by inverting gates and power amplifiers are iUustrated
in Figure 18. (Delays are measured between threshold points.)
STANDARD
PULSE
I
I
I-toff~
le-ton----t
I_~-....
NAND OR POWER
NAND GATE
r-ton
--I
:;I
POWER
AMPLIFIER
M627
,--
j.toff-i
DELAY (NANOSECONDS)
toft
ton
TYP.
MAX.
TYP.
MAX.
1e
29
15
Figure 18_ NAND Gate and Power Amplifier Delays
23
Flip-Flop Propagation Delays: D type flip-flops trigger on the leading or rising

edge of a positive clock pulse; the propagation delay is measured from the
threshold point of this edge. The set-up time of the D flop is also measured
from this threshold point. Data on the D input must be settled at least 20
nanoseconds prior to the clock transition. The advantage of the D-flip-flop.
however, is that the leading edge triggering allows the flip-flop AND gates to
propagate while the clock pulse is still high. Figure 19 illustrates this situation_
'-20 .......
I......---NS50EC~
I NSEC I
~~T
I
I
I
I
I
I
I
+
CLOCK
I
I
t--- 30----.t
NSEC
o TYPE
FLIP FLOP
OUTPUT _ _ _ __
Figure 19. D Type Flip-Flop Timing

JK type flip-flops are, in effect, trailing edge triggering devices as explained
previously. The only restriction on the J and K inputs is that they must be
settled by the time that the rising edge occurs_ Timing is shown in Figure 20.
!..---J AND K
I
___1
INPUTS MUST BE
STABLE BY THIS TIME
TRIGGER
PULSE
\
_ _y
I
-.1I
---l.I
FLIP- FLOP OUTPUT
Figure 20. J-K Flip-Flop Timing
24
35 nsec (TYPICAL!
When using the dc Set or Reset inputs of either flip-flop type, propagation
delays are referenced to the falling edge of the pulse. This is due to the
inverted sense of these inputs. When resetting ripple type counters (where
the output of one flip-flop is used as the trigger input to the next stage) the
reset pulse must be longer than the maximum propagation delay of a single
stage. This will ensure that a slow flip-flop does not introduce a false transition,. which could ripple through and result in an erroneous count.
One-Shot Delay: Calibrated time delays of adjustable duration are generated
by the M302 Delay Multivibrator. When triggered by a level change from a
logical one to a logical zero, this module produces a positive output pulse
that is adjustable in duration from 50 to 750 nsec with no added capacitance.
Delays up to 7.5 milliseconds are possible without external capacitance.
(See M302 specification.) Basic timing and the logic symbol are shown in
Figure 21. The 100 picofarad internal capacitance produces a recovery time
of 30 nsec. Recovery time with additional capacitance can be calculated
using the formula;
tr Nanoseconds
= 30 C Total (Picofarads)
100
0.5.
OUTPUT
L-1I-.J
LOGIC SYMBOL
f4-tr -----.:
,
I
,
I
jf'--~-':'_.__J,.
---'1
OUTPUT
(TYPICAL)
i4--
I
I
50 nsec TYPICAL
: 4 - - 50 TO 750 nsec
___
TIMING
Figure 21. One-Shot Delay Timing and Logic Symbol

SYSTEM OPERATING FREQUENCY
Although individual propagation delays are significant in the design of digital
logic, even more important is the maximum operating frequency of a system
which is composed of these individual modules. Specifically designed systems may be operated at 10 MHz, but a more conservative design may result
in a somewhat lower operating speed. M Series modules can be designed
into a system with a 6 MHz clock rate with relative ease. This system frequency is derived by summing the delays in a simple logic chain:
25
1.
A standard clock pulse width of 50 nsec is assumed. This period is

measured from the threshold point of the leading edge to the threshold
pOint of the trailing edge.
2.
One flipflop propaga~ion delay of 35 nsec from the trailing edge of the
clock pulse to the threshold pOint of the final state of the flip-flop is
allowed.
3.
Two gate-pair delays of 30 nsec each are assumed. (A gate-pair consists

of two inverting gates in series.) Two gate-pair delays are usually required to perform a significant logic function with a minimum of parallel
operations. The two ga~e-pair delays total 60 nsec.
'
The time necessary to perform these operations before the next occurrence of
the clock pulse is the sum of the delays; 50
35
60, or 145 nsec. AII9Wing 20 nsec for variations within the system, the resulting period is 165
nsec, corresponding to a 6 MHz clock rate. This timing is demonstrated in
Figure 22.
CLOCK
WIDTH
t - n~ - t - I
GATE
PAIR
DELAY
F/F
DELAY
I
I
GATE
PAIR
DELAY
IDLE
n~c ...... n!~ ..... n!~c ~ n~~c--i

I
I
I
I
I
I
CLOCK
j
0---------
JK FLIP - FLOP
j
0-----------_ ____I:
GATE PAIR 1
GATE PAIR 2
Figure 22. Delays Determining System Operating Frequency

Substitution of a D type flipflop results in a similar timing situation. In a
system using both D and J-K flip-flops, note that the D flip-flop triggers on
the leading edge of the clock pulse and the J-K flip-flop triggers on the trailing
edge. When calculating system timing using D flip-flops, remember that the
flip-flop inputs must be settled at least 20 nsec prior to the occurrence of the
clock pulse.
Preparation of a timing diagram that considers delays introduced by all logic
elements will aid the designer in achieving predictable system performance_
26
MISCELLANEOUS
M002
,
LOGIC HIGH SOURCE
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$10
+3V
SOURCE
Volts
+5
GND
Power
mA (max.)
16
Pins
A2
C2. T1
To hold unused M Series TTL gate inputs HIGH, the M002 provides 15 out
puts at +3 volts (logic HIGH) on pins 02 through V2. Up to 10 unused M
Series gate inputs may be connected to anyone output. If an M002 circuit
is driven by a gate, it appears as two TTL unit loads or 3.2 rnA at ground.
27
LOGIC
M040
SOLENOID DRIVER
AMPLIFIERS
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$39
LOADS
---,
-v
o
---t-'l
_ _ _ ...I
-v
I
I
+r' - - - , -
10- -I
Volts
Power
mA (max.)
+5
47
-15
GND
P~ I--_...J
L~.!.J
Pins
A2
C2. Tl
82
The M040 contains two identical high-voltage driver circuits. Each consists
of a 4-input positive NAND gate that controls a PNP transistor switch. The
switch is capable of sinking up to 600 rna of current from an external power
supply of up to -70 volts. One terminal of the load device (relay, etc.) must
be connected to the external voltage, the other to the driver output. The
positive terminal of the external supply connects to the module ground.
APPLICATIONS
The M040 can drive relays, solenoids, stepping motor windings and similar
inductive loads.
Restrictions: Not recommended for
Indicator drive
115 V ac applications
Logic level conversion
..
FUNCTIONS
ON Condition: Each driver sinks current from the external circuit when all four
control inputs are HIGH. The amount of current is determined by the external
voltage and load impedance. (The internal switch is a saturated PNP transistor.) Typical output voltage when sinking 0.6 A is -2 volts.
OFF Condition: When one or more control inputs is lOW, the internal switch
is a high impedance and the output voltage approaches the external voltage
source. The output circuit draws a small amount of leakage current (typically
100 p.A for a 70-volt external supply).
28
Anti-Kickback: Pin V2 of the driver module must be connected to the external

supply so that the drivers will be protected from the back voltage generated
by inductive loads. If the wire to the power supply is more than three feet
long, it may have to be bypassed at the module with an electrolytic capacitor
to reduce the pulse overshoot caused by the inductance of the wire.
Improving Recovery Time: If pin V2 is connected to the supply through a resistor, the recovery time of inductive loads can be decreased at a sacrifice in
maximum drive voltage capability. Maximum rated supply voltage less actual
supply voltage should be divided by load current to find the maximum safe
resistance. When both circuits on a module are used, the load current for the
above calculation is the sum of the currents.
PRECAUTIONS
Grounding: High current loads should be grounded directly at pin C2 of the
M040, rather than at a frame or .bus ground.
Parallel Operation: No more than two circuits should be paralleled to drive
loads beyond the current capabilities of single circuits.
SPECIFICATIONS
Current sinking capability: 600 mA per circuit, max.
External supply Yoltage: 70 V dc max.
Circuit Delay: Typical propagation delay for each circuit is 5 p'S (between
10% and 90% voltage points) for an external supply voltage of 70 yolts.
29
LOGIC
AMPLIFIERS
M050
50 MA INDICATOR DRIVER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
+3
-v
$31
01
~
~
L:.J
I.::.J
~
~.
U-.~
+3
-v
L!!.J
Rl
2
2
+3
-v
L1
*
o
~
+3-V
F1
+3
-v
+3
-v
-v
El
~
~
~-~
P1.
Kl
+3
+3
-v
+3
-v
Jl
51
* . 50 MA, -30V MAX.

Volts
Power
mA (max.)
+5
47
-15
16
GND
Pin
A2
C2
82
The M050 contains twelve transistor inverters that can drive miniature incandescent bulbs such as those on an indicator panel.
APPLICATIONS
The M050 is used to provide drive current for a remote indicator, such as
Drake 11-504, Dialco 39-28375, or Digital Indicator type 4908, or as a level
converter to drive 4917 and 4918 indicator boards.
Restrictions: Do not use to drive inductive loads (relays, solenoids).

Note: For those applications requiring the sinking of current, refer to K Series.
fUNCTIONS
A LOW level on the input of the driver causes current to flow in the output.
SPECIFICATIONS
Each output is able to drive 50 mA into an external load connected to any
voltage between ground and -30 volts.
30
GATES
Mill
INVERTER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$22
Volts
+5
GND
Power
mA (max.)
87
Pins
A2
C2, T1
Sixteen Inverters with input! output connections as shown.
APPLICATIONS
Output Expansion
Logical Inversion
31
GATES
Ml12
NOR GATE
M SERIES
length: Standard
Height: Single
Width: Single
Price:
$35
AI
~
~
~
~
~
Cl,O
1 8t
Dl
lZ
~
~
~
~
N2
Fl 10
1 M
F2
1 E2
51
'0
1 R1
10
P2
Ht
Kt
1 J1
P1
DZ
10
52
RZ
1 :
HZ
TZ
K2 t
t JZ
Volts
V2
,0
t UZ
+3V
+5
GND
'0
Power
mA (max.)
50
I ::::
Pins
A2
C2, T1
The M112 contains ten positive NOR gates. each performing the function A
+ B. Pins UI and VI provide two separate logic HIGH sources (+3V) each
capable of holding up to 40 unused M Series inputs HIGH.
APPLICATIONS
Logic gating
32
GATES
M113, MIlS, M117, Ml19

NAND GATES
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
MI13-$IB
MI15-$IB
MI17-$19
"Ml19-$lB
Power
mA (max.)
71 M113
41 M115
41 M117
19 M119
Volts
+5
+5
+5
+5
GND
Pins
A2
A2
A2
A2
C2. T1
~ ~
~ ~
~ ~
CI '0
B1
1M!
FI '0
t EI
FZ
to
.
I R'
I E2
~ ~
~ ~
.
KI 10
JI
J2
S2
1 R2
SI '0
K2
V2
tO
,U2
B :::
M113 2-INPUT NAND GATES
33
E3
E3
S
1 Cl
t F2
'
K2
S
E=i
1 Ll
1 Mt
1 R2
' Rl
t 51
M1t5
3-INPUT NAND GATES
""7 4-1NPUT NAND GATES
34
M119 8-INPUT NAND GATES
These modules provide general-purpose gating for the M Series, and are most
commonly used for decoding, comparison, and control. Each module performs the NAND function (A B C - - - N ) , depending upon the number of
inputs.
APPLICATIONS
~ Logic gating
FUNCTIONS
M1l3-Ten two-input NAND gates that also may be used as inverters_
MIlS-Eight, three-input NAND gates.
MIl7-Six, four-input NAND gates.
MIl9-Three, eight-input NAND gates.
Unused inputs on any gate must be returned to a source of logic HIGH, for
maximum noise immunity. In the M1l3, M1l7, M1l9, MI2I, M6I7 and
M627 modules, two pins are provided (UI and VI) as source of +3 volts for
this purpose. Each pin can supply up to 40 unit loads. MI03, MIll and
M002 provide additional sources of logic HIGH level.
SPECIFICATIONS
Typical propagation delay of M Series gates is 15 ns.
35
GATES
M121
AND/NOR GATE
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$23
Volts
t~D
Power
mA (max.)
50
Pins
A2
C2. T1
The M121 module contains six AND/ NOR gates which perform the function
(AB
CD). By proper connection of signals to the AND inputs, the exclusive
OR, coincidence, and NOR functions can be performed.
APPLICATIONS
Logic Gating
SPECIFICATIONS
Propagation Delay: Typically 15 ns
36
GATES
MI33
TWOINPUT NAND GATES
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$27
A1
~
~
~
~
~
L1
~
~
~
~
Nt 10
C1 10
1 B1
Dt
l2
Ft
1 E1
10
F2
K1
, JI
S1 10
'0
H'
N2
M2
P'
D2
1 E2
1R1
P2
S2
to
, R2
'0
H2
K2,O
1 J2
Volts
+5
GND
Power
mA (max.)
160
Pins
A2
C2, Tl
This module provides general-purpose high-speed NAND gating.

APPLICATIONS
The high-speed characteristic of these gates frequently will solve tight timing
problems in complex systems.
SPECIFICATIONS
Maximum output propagation delay to a logic HIGH or LOW is 10 ns.

Unused inputs on any gate must be returned to a source of logic HIGH for
maximum speed and noise immunity.
37
GATES
M141
NAND/OR GATES
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$29
+5V
+5V
HIV
t.5K
UK
1.51<
~U2
t V2
Volts
+5
Power
mA (max.)
117
GND
Pins
A2
C2. T1
This module provides NAND/OR gates arranged in four groups consisting of

4, 4, 3, and 1 two-input NAND gates respectively. The outputs in each group
are connected together to provide a wired OR for low levels. The function of
these gates can be shown as:
38
+5V
~r----~]~~--~:~~--
AB+CO+EF
By using one of the two inverters provided, a true AND/OR function can be
realized. A maximum of four groups of gates can be connected together.
Connection is made by merely connecting output pins together.
APPLICATIONS
logic Gating
FUNCTIONS
The M141 NAND/OR gate performs two levels of logic. The first is the NAND
function which is identical to the M113 NAND gate. The second level is that
of a wired OR for low logic levels. The twoinput NAND gate which is used
in the M141 does not have the standard TIL output circuit, but only the
lower half of the totem pole output. This allows the outputs of these gates
to be connected together and to share a common punup resistor.
SPECIFICATIONS
Propagation Delay: 70 ns max.
loading: The load resistor of each output presents 2 unit loads when connected to another output. For example, when four groups are connected
together,' 3 groups present two unit loads each to the fourth group, totalling
6 unit loads. This leaves 1 unit load capability.
39
*=OPEN COLLECTORDRIVES 10 UNIT LDADS LOW
Vnlts
+5
<aND
Power
mA (max.)
150
Pins
A2
C2. T1
The M159 can perform 16 word-oriented arithmetic operations and 16 bit

oriented logic functions. Arithmetic operations are performed on two 4-bit
input words and an input carry to produce one 4bit output word and a carry
out. In the logic mode the M159 looks like four 2input functional gates.
Where N indicates one out of four, the output FN depends only on the inputs
AN,B N, and the logic function code selected.
40
The M159 is fully cascadable. The CARRY OUT of the less significant M159
should be connected directly to the CARRY IN of the next more significant
M159. The CARRY PROPAGATE and CARRY GENERATE output should be used
with a carry look-ahead module or left unconnected.
The COMPARE output goes High whenever all the "F" outputs go High. This
output is open-collector so that it can be wire-AND connected when M159
modules are cascaded. An example of how thisoutput can be used is shown
in the table below.
.
When the arithmetic operation A minus B minus 1 is selected, the M159 can
be used as a comparator.
A and B
COMPARE
Data Inputs
Output
CARRY
OUT
=B
AB
The maximum propagation delay from the "AN'" or "BN" bit input to the
output bit "FN" in the logic mode is 48 nsec. which does not change as
M159's are cascaded. In the arithmetic mode, the maximum delay from the
"A" or "B" word input to the "F" word output, CARRY OUT, or COMPARE
. is 50 nsec. which increases by 19 nsec. per additional cascaded M159 when
carry look-ahead is not used. When carry look-ahead is used, the maximum
additional delay is limited to 20 nsec. for up to three additional M159's.
Table of Logic Mode Operations
(MODE Input
= 1)
(CARRY IN has no affect on Logic Mode Operations)

Function
NOTE that FN is com piemented when the Function

Selection Code is complemented
SELECTION CODE
~quals
53
52
51
50 Bit FN
AN
AN
AN AND BN
AN AND BN
Bit
F~
Complemented
Function
SELECTION CODE
Equals S3
S2
SI
SO
AN OR BN
AN OR BN
AN OR BN
AN AND BN
BN
BN
(AN AND BN)

OR
(AN AND BN)
~ AND 'BN
(AN AND BN)

1
OR
(AN AND "BN)
AN OR BN
41
Table of Most Useful Arithmetic Mode Operations

(MODE .nput =0)
Function
Word F Equals
SELECTION CODE
CARRY IN
S3
52
SI
50
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
=1
,WORD A
CARRY IN
=0
WORD A plus 1
Minus 1 (2's Comp.)
ZERO
A Minus B Minus 1
A Minus B
A plus B
A plus B plus 1
A Times 2
A Times 2 plus 1
A Minus 1
42
Table of less Useful Arithmetic Mode Operations

(MODE Input
= 0)
Word F Equals
Function
SELECTION CODE
CARRY IN
S3
S2
S1
SO
0
0
0
0
0
1
1
0
0
0
1-
0
0
0
1
0
1
1
0
1
0
1
0
=1
CARRY IN
=0
A OR B plus 1
A OR 8 plus 1
A OR B
A OR B
A plus (A AN 0 B) plus 1
A plus (A AND B)
(A OR B) plus (A AND S) (A OR B) plus (A AND B)
plus 1
(A AND B) minus 1
A plus (A AND B)
A AND B
A plus (A AND B) plus 1
(A OR
(A AND B) minus 1
A AND B
(A OR B) plus A
(A OR B) plus A
(A OR B) plus A plus 1
(A OR B) plus A plus 1
1
1
1
1
0
1
1
0
B) pIlls (A AND B) (A OR B)
43
plu~
(A AND B)
plus 1
GATES
M160
ANDtNOR GATE
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$33
Power
Volts
ct~D
mA (max.)
30
Pins
A2
e2. T1
The Ml60 module contains three general-purpose AND/NOR gates which

perform functions similar to those of the M121.
APPLICATIONS
These gates can be used to select and place on a single output any of
several input signals.
SPECIFICATIONS
Typical propagation delay of an M 160 gate is 20 ns.
44
M161
.
BINARY TO OCTAL/DECIMAL DECODER
NUMERIC
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$55
ENABLE
BCD TO
DECIMAL
DECODER
DECODED
OUTPUT
Volts
+5
GND
Power
mA (max.)
120
Pins
A2
e2, T1
The M!6! is a funct!onal decoding module which can be used as a binary-tooctal or binary-coded decimal (8421 or 2421 codes) to decimal decoder. In
the binary-to-octal configuration, up to eight M161 's can be linked together to
provide decoding of up to six bits. Three ENABLE inputs are provided for
selective enabling of modules in decoders of more than one digit. In the octal
mode, the bit 2* input is connected to ground, which automatically inhibits
the 8 and 9 outputs. Connections for a 5-bit binary! octal decoder (4 modules) are shown below. The figure assumes that the inputs to the decoder
45
are the outputs of flip-flops such as FF2 (I), 1 output side; and FF2 -(6), 0
output side.
The 2* input may be of decimal value 2,4,6,8 as long as illegal combinations
are inhibited before connections to the inputs, and the 4-2-1 part of the code
is in binary.
The propagation delay through the decoder is typically 55 nsec in the binaryto-octal mode, and 75 nsec in the BCD-to-decimal mode. The maximum delay
in the BCD-to-decimal mode is 120 nsec, frequency-limiting this module to
8HMz when used in this fashion. The enable inputs can be used to strobe
output data providing inputs 2 - 2'" have settled at least 50 nsec prior to
the input pulse.
a::
w
"...z
~
:::6
tIJ~
~ :t
ONN
~~
~7
CII",
",'"
~ ....
::1-"-
Il.CII
~g
0
0
u
w
0
..J
c(
~
):"
a::
c(
Z
iii
~
iii
.;.,
46
NUMERIC
M162
PARITY CIRCUIT
M SERIES
PrIce:
Len8th: Standard
Height: Single
Width: Single
1H
lL
2H
L
DATA
IN
4H
PARITY
ODD H
ODD L
Kl
IO
L
8H
8L
lH
lL
2H
2L
DATA
IN
4H
'A\RtTY
000 H
000 L
4L
8H
8L
Volts
+5
GND
Power
mA (max.)
..
102
Pins
A2
e2, T1
The M162 contains two parity detector circuits. Each circuit indicates
whether the binary data presented to it contains an ODD or EVEN number
of ONES. The data and its complement are required as shown.
APPLICATIONS
Parity checking
FUNCTIONS
Indication of ODD PARITY is .given by a HIGH level at pins Kl and U2 reo
spectively. Pins II and V2, when HIGH, in'tficate EVEN PARITY or no input.
47
NUMERIC
M16S
12BIT MAGNITUDE COMPARATOR
M SERIES
Price:
Length: Standard
Height: Single
Width:
$45
Single
W~DA
A>B
A=B
A>B
12-BIT MAGNITUDE
COMPARATOR
A=B
Bl
"
"3
FROM LESS
. SIGNIFICANT
COMPARATOR
A<B
WORD B
Volts
+5
GND
Power
mA (max.)
250
Pins
A2
C2. T1
The MI68 12-Bit Magnitude Comparator performs magnitude comparison of

two 12-bit words. When the comparison inputs are not connected to the
comparison outputs of another M168, the "A=B" input must be connected
to a logical "I". The A>B and A<B inputs may individually be made a logic
"I" or logic "0". However, connecting both these inputs to GND, a logic "0"
is recommended.
The M168 Comparator may be cascaded to compare longer words. The out
puts T2, U2, and V2 should be connected to the corresponding inputs of the
next comparator which are AI, B1, and Cl respectively. The inputs of the
first comparator must all be made a logical "1".
The propagation delay time from Data (A and B) to outputs is 48 nsec typical
and 72 nsec maximum for one unit.
When cascading the total typical time is 48 nsec plus 36 nsec per additional
unit. The total maximum time is 72 nsec plus 54 nsec per additional unit.
48
INPUTS
A>B
OUTPUTS
A=B
AB A=B
AB
A=B
AB
A=B
AB
A=B
A<B
49
GATING
M169
GATING MODULE
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$33
L'
Power
Volts
t~D
m~
(max.)
50
Pins
A2
C2, Tl
The M169 contains groups of 4-input AND/ NOR gates prewired as four
stages of a 4-input, I-output multiplexer or similar gating function.
APPLICATIONS
Multiplexers
Register Select and Bussing
FUNCTIONS
Raising a DATA INPUT to a HIGH and selecting a corresponding INPUT EN
ABLE line generates a HIGH at the appropriate ENABLED OUTPUT, AI, KI,
MI or V2. Any of the ENABLED OUTPUTS may be enabled directly through
an M121 or M160 AND/NOR gate, used as a NOR Expander.
SPECIFICATIONS
Maximum input to output propagation delay for any circuit is 45 ns.
50
FLIp FLOPS
M202
TRIPLE J-K FLIP-FLOP
MSERIES
Price:
length: Standard
Height: Singte
Width: Single
U2 fO
Volts
+5
GND
Power
mA (max.)
57
Pins
A2
e2, T1
The M202 contains three J-K flip-flops augmented by multiple-input AND

gates_
APPLICATIONS
For general use as gated control flip-flops or buffers_

FUNCTIONS
See M207 for detailed description of logical operation. The J-K flip-flops
used in this module are identical to flip-flops used in the M207 except on
the M202 clock inputs, J-K inputs, direct clear, direct set and both output
lines for each flip-flop are independent.
51
FLlPFLOPS
M203
8 R/S FLlpFLOPS
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$26
L ________
.JI
It"'-L2~_<lS
H29
t fo=-J..;..,I_-as
P2 9
M2 9
IrA"'-1'_-as
CI 9
IrE"'-1'_-0R
OI--_-'-'H"-I' 9
I~B-'-1'_ _aR
Volts
t~D
tt-=V-=t
2 _ _cs
VI 9
IpM'-'i'_ _CR
O~_-.:.:.R'!...j9
'I-'-'N"1'_ _r1S
PI 9
tt-=S'-'i'_-OR
o~_--",U~I 9
Power
mA (max.)
55
Pins
A2
C2. Tl
The M203 is made up of 8 R/ S-type flip-flops. Each flip-flop is made up of

two 2-input NAND gates with cross-coupled outputs.
APPLICATIONS
R/ S flip-flops provide an inexpensive method of storage.
PRECAUTIONS
Care .must be taken not to place the SET and RESET inputs LOW at the
same time. The last of the inputs to go HIGH will determine the final state
of the flip-flop.
SPECIFICATIONS
The propagation delay of the M203 is approximately 30 ns.
52
M204
GENERALPURPOSE BUFFER
AND COUNTER
FLI p. FLOPS
M SERIES
Length: Standard
Height: Single
Price:
Width:
$34
Single
t I-'-'K"'-I'- - - - - I K
Volts
+5
GND
Power
mA (max.)
74
Pins
A2
C2. T1
The M204 contains four JK type flipflops, augmented by multipleinput

AND gates. The gating scheme permits the formation of counters of most
moduli up to 16, by simple connector wiring. Clock, trigger, and input lines
for each flipflop are independent. A common CLEAR input is provided.
APPLICATIONS
For general use as gated control flipflops or buffers
Counters
Shift Registers
FUNCTIONS
Input information is transferred to the outputs when the threshold point is
reached on the trailing (negative going voltage) edge of the clock pulse.
Logical operation of the JK flipflops used in this module is identical to the

M207 (described in detail) except for the addition of dc set inputs to the
M204.
53
M205
GENERALPURPOSE FLlpFLOPS
FLIP-FLOPS
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$33
Volts
+5
GND
Power
mA (max.)
90
Pins
A2
C2. T1
The M206 contains five separate OoType flip-flops. Each flip-flop has independent gated data, clock, de set, and dc reset inputs.
APPLICATIONS
Storage Registers
Counters and Shift Registers
Flags and Control Storage
FUNCTIONS
For each flip-flop, information present on the 0 input is transferred to the
output when the threshold is reached on the leading (positive going voltage)
edge of the clock pulse.
SPECIFICATIONS
Information must be present on the 0 input 20 ns (max) prior to a standard
clock pulse and should remain at the input at least 5 ns (max) after the
clock pulse leading edge has passed the threshold voltage. Data transferred
into the flip-flop will be stable at the output within 50 ns, maximum. Typical
width requirement for the clock, de reset and de set pulses is 30 nsec each.
54
Ali incoming integrated circuits undergo computer controlled testing, with 40 de and 16 ac tests performed in 1.1 seconds. This
100% inspection speeds production by minimizing the diagnosis
of component failures In moduie test.
55
M206
GENERAL-PURPOSE FLIP-FLOPS
FLlPFLOPS
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$30
FACTORY
CON~CTIONS
FF2
FF1
* . 3 UNIT LOADS PER FLIP-FLOP

Volts
+5
GND
Power
mA (max.)
87
Pins
A2
C2. T1
The M206 contains six separate OoType flip-flops. Each flip-flop has independent gated data, clock, and dc set inputs.
APPLICATIONS
Registers
Counters and Shift Registers
Flags and Control Storage
FUNCTIONS
For each flip-flop, information present on the 0 input is transferred to the
output when the threshold is reached on the leading (positive going voltage)
edge of the clock pulse.
56
Provision is made on the printed circuit board for changing the configuration
of the two CLEAR lines to the flip-flops. A" M206 modules are supplied with
the 3-3 configuration, but the grouping can be changed as follows.
CONFIGURATION CLEAR I (AI)
CLEAR 2 (K2)
DELETE JUMPER
ADD JUMPER
3-3
FFO, 1, & 2
FF3, 4, & 5
4-2
FFO & 1
FF2, 3, 4, & 5
Al to FF2
K2 to FF2
5-1
FFO
FFl, 2, 3, 4, & 5
Al to FF2
Al to FFl
K2 to FF2
K2 to FFI
A common CLEAR for a" six flip-flops can be obtained by wiring pins Al
and K2 together externally.
PRECAUTIONS
Note that the loading of each CLEAR line is calculated on the basis of 3
unit loads per flip-flop. For example, the 4-2 configuration results in 12 unit
loads at input K2 and 6. unit loads at input AI.
SPECIFICATIONS
Information must be present on the D input 20 ns (max) prior to a standard
, clock pulse and should remain at the input at least 5 ns (max) after. the
clock pulse leading edge has passed the threshold voltage. Data transferred
into the flip-flop will be stable at the output within 50 ns, maximum. Typical
width requirement for the clock, de reset and de set pulses is 30 nsee each.
57
M207
GENERAL-PURPOSE FLlp:FLOPS
FLIP-fLOPS
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
FFe
FFt
FFl
FF4
FF2
K2
Power
Volts
t~D
mA (max.)
96
FF!S
Pins
A2
C2. Tl
The M207 contains six general-purpose J-K type flip-flops.

APPLICATIONS
Buffers
Control Flip-Flops
Shift Registers
Counters
FUNCTIONS
A truth table for clock set and reset conditions appears below. Note that
when the J and K inputs are both HIGH, the flip-flop complements on each
clock pulse.,
58
STARTING CONDITION
(OUTPUT)
INPUT CONDITION
L
L
H
H"
L
H
L
L
H
RESULT AT END OF
STANDARD CLOCK PULSE
(OUTPUT)
0
No change
No change
H
H
L
L
No change
L
No change
L
L
Two CLEAR inputs are provided, with jumper terminals for optional clearingin groups of 3 and 3 (standard), 4 and 2,- 5 and 1, or 6.and O. Provision is
made on the printed circuit board for changing the configuration of the two
CLEAR lines to the flopflop. All M207 modules are supplied with the 3-3
configuration, but the grouping can be changed as follows:
CONFIGURATION
CLEAR 1 (Al)
CLEAR 2 (K2)
DELETE JUMPER
ADD JUMPER
3-3
FFO, 1, & 2 FF3, 4, & 5
4-2
FFO & 1
FF2, 3, 4, & 5
Al to FF2
K2 to FF2
5-1
FFO
FFl, 2, 3, 4, & 5
Al to FF2
Al to FFl
K2 to FF2
K2 to FFl
SPECIFICATIONS
J and K inputs must be stable during the leading-edge threshold of a
standard CLOCK input and must remain stable during the positive state of
the CLOCK. Data transferred into the flip-flop will be stable at the output
within 30 ns (typical) of the CLOCK pulse trailing edge threshold (negative
going voltage).
Application of a LOW level to an R input for at least 25 ns resets the flip-flop
unconditionally.
59
FLIP-FLOPS
M208
8-BIT BUFFER/SHIFT REGISTER

M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$84
~-----f,~
VI
51
Rl
FF0
FF 1
FI'Z
NI
FF3
LI
JI
FF4
FF5
H2
FI
FF6
SER L-wAo INPUTS----l
L--LOAD iNPUT5---'
NPUT
I
I
I
OCK r - - PARALLEL OUT----,
FF0
FFI
FF2
r-PARALLEL
FF3
FF4
---'
FF5
ou T--.,
FF6
,OUT,
FF1
102
10 to
L H
Volts
+5
GND
Power
mA (max.)
184
Pins
A2
C2. Tl
The M208 is an internally connected 8-bit buffer/shift register. Provisions

are made for gated single-ended parallel load, bipolar parallel output, and
serial input. The shift register is divided into three segments:
Bits 0 through 3: Serial input to bit 0, bipolar outputs from bits 0 through 3.
Bits 4 through 6: Serial input to bit 4, bipolar outputs from bits 4 through 6.
Bit 7: Serial input to 7, bipolar outputs from bit 7.
FUNCTIONS
Each of the register groups shares a common shift line (the ORed CLOCK
1 and CLOCK 2 inputs) and a common parallel load line (LOAD ENABLE).
To form a 6-bit shift register, for example, the true output of bit 3 is connected to the serial input of stage 4. A shift register of 8 bits may be constructed from a single module. Modules may be cascaded to form shift
registers of any desired length. A few additional stages may be formed more
economically from NAND and AND/OR gates plus a D-type flip-flop. A representative stage of this type is illustrated. Two CLOCK inputs are provided so
that individual LOAD and SHIFT CLOCK sources may be used.
60
ID
0
C\I
>
I'f')
\I)~~ID
*C\IX
*,C\I
~
.Jz~~
~~~~
:]:
f W
II..O~\I)
+
Z
II..
II..
Q.::>WO
OQ.XC\I
=o~o~
U r-
~~ci~
>-r-wr-::>~~
woll..lI)
~!;~~
~~~~z
r-r-\I)~Q
et.o;;izr-
~~~~~
ww:::Euu
b~ffi~~
zxr-Q.O
:;
z
II..
II..
<3
.J
en
UJ
CJ
<
~
UJ
>
;::
>
I'f')
UJ
en
UJ
Q::
a.
UJ
Q::
II..
"'0
lC
U
C\I
lC
U
.J
.J
roW
II...J
-CD
Xc
\l)z
W
ow
ct.J
OlD
.Jet.
a:
41
W
.J
U
PRECAUTIONS
Care must be taken that the clock inputs remain in the HIGH state in the
off condition because either input going to the LOW state will produce a
positive edge at the output of the NAND gate and trigger the D type flip-flop.
SPECIFICATIONS
Data shifted or parallel loaded into the M208 will appear on the outputs
within 55 ns (max) of the CLOCK pulse leading edge threshold. LOAD and
SHIFT ENABLE levels and parallel data must be present at least 50 ns prior
to a CLOCK pulse. Propa~ation delay from the leading edge of a CLEAR
pulse to the outputs is 40 ns max.
61
M230
BINARY TO BCD AND BCD TO
NUMERIC
BINARY CONVERTER
M SERIES
Price:
length: Standard
Height: Double
Width: Single
$105
DIGIT
IGIT
}
}
BCD
BCD
INPUT
OUTPUT
2{
}-
.{
,{
BCD-BINARY
OONVERTER
LSB
LSB
C OUT
(BCD)
o
Volts
+5
GND
Power
mA (max.)
860
Pins
A2
C2. T1
62
The M230 converts a binary number to its binary coded decimal equi.valent
or a binary coded decimal number to its bInary equivalent.
The maximu~ number that can be con~erted from either binary to BCD or
BCD to binary is 4095 which is 7777 . This converter utilizes a counting technique where the count frequency is typicalty 5 MHz. Therefore, the conversion time for the maximum number 77778 is typically 0.82 millisec.
The M230 is fully cascadable. When using more than one M230 the COUT
BIN. must be connected to the CtN BIN. and the COUT BCD must be connected
to the CIN BCD of the next higher significant unit. CIN BIN. and CIN BCD of
the least significant unit must be made a logic "I". COUT BIN. and COOT BCD
of the most significant unit may be left open.
CONVERSION CONTROL on pin ACl will cause a Binary to BCD conversion
when connected to ground and a BCD to Binary conversion when connected
to a logic "1" source. When cascading M230's, connect all CONVERSION
CONTROL inputs in parallel.
LOAD/CONVERT on pin AAI reads the input data when connected to a logic
"I" level and starts the conversion when this input is returned to a logiC
"0" level. When cascading M230's, connect all LOAD/CONVERT inputs in
parallel.
CONVERSION COMPLETE on pin BT2 goes High when the conversion process
is finished.
EXT. IN on pin AVI and EXT. OUT on pin AV2 convey conversion finished
information between cascaded M230's. This information travels from the
most significant M230 to the least Significant M230. Therefore, the EXT. IN
of the most significant M230 must be connected to a logic "1" source.
Each EXT. OUT is connected to the EXT. IN of the next less significant M230.
The EXT. OUT of the least significant M230 is left unconnected.
CLOCK CONTROL on pin AT2 of the least significant M230 should be enabled
by connecting it to a logic "I" source. All others should be connected to
ground.
The following is an ordered summary for operating a single M230:
1. Make the conversion control (pin ACl) a logiC "0" for converting Binary
to BCD or a logic "I" for converting BCD to Binary.
2. When converting Binary to BCD, connect the Binary number to the
BINARY INPUTS and ground the BCD INPUTS. Conversely, when converting BCD to Binary, connect the BCD number to the BCD INPUTS and
ground the BINARY INPUTS.
3. CIN BIN., CIN BCD, EXT. IN, and CLOCK CONTROL inputs should be tied
to a source of logic "I". The outputs COOT BIN., COUT BCD, and EXT. OUT
should be left unconnected.
4.- Pulse the LOAD/CONVERT input with a positive pulse of 150 nsec. minimum pulse width. There is no limit on the maximum width of this pulse.
Conversron begins on the negative going edge of this pulse.
5. When converting Binary to BCD read the BCD OUTPUT for the BCD
equivalent. For converting BCD to Binary read the BINARY OUTPUT for
the Binary equivalent. The CONVERSION COMPLETE OUTPUT becomes
a logic "1" when the conversioQ is through.
63
FLlPFLOPS
M232
16-WORD RAM
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
K-SERIES {
INPUTS
$125
I F2
r-::-__- - - f
M-SERIES { 2 U2
INPUTS
2 FS=.2_-------------...,
2 J2
L2
DECODE
~N"""2_-_IIMSB ENABLE
ADDRESS
DECODER
0 - - + - -.....-412
16-WORD/1-BIT
~---IlSB
RAM
lK
+-_--1*
J'2OOPF
Volts
+5
GND
Power
mA (max.)
200
Pins
A2
C2, Tl
The M232 provides individually addressable storage for 16 bits.

FUNCTIONS
Each bit is addressed by a 4-bit code on input lines N2, R2, T2, and V2. If a
binary 0 is stored at an accessed address, the output sense pin E2 remains
HIGH. If a binary 1 is stored, the output sense signal goes LOW.
Writing with M Series signals is achieved by causing pin U2 to go LOW for a
binary 1 or by causing pin S2 to go LOW for a binary 0 after a location has
been accessed. Writing with K Series signals is achieved by causing pin F2
to ,go HIGH for a binary 1, or pin K2 to go HIGH for a binary 0 after a
location has been accessed.
64
All locations can be accessed simultaneously and all bits cleared to binary
by a 5-microsecond LOW signal on the GENERAL CLEAR pin J2. Pin 82
is a special-purpose OUTPUT SENSE connection which is used when module
outputs are ORed or connected in parallel as is done in some PDP14
systems ..
SPECIFICATIONS
Access Time: Access to an addressed location occurs 25 ns after the DE
CODE ENABLE pin L2 goes HIGH.
Write Pulse (M Series): 25 ns min.
Write Pulse (K Series): 5 "'s min.
Clear Pulse (J2): 5 "'s min.
65

NUMERIC
M236
12-BIT BINARY UP/DOWN COUNTER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
MSB J
....
INf\JTS
MAX-
tZ-BIT BINARY COONTER
MINH
<
TZ
to
,--_ _ _ _ _O_UT
.....,.
......
PUT_S_ _ _ _ _-....~~t---I.....K&f1O
MSB '
Volts
t~D
Power
mA (max,)
330
Pins
A2
C2. T1
The M236 is a 12-bit synchronous binary up/down counter. It has a single

control Input that can switch the counting mode from up to down without
disturbing the contents of the counter. The M236 is fully cascadable and
programmable. Cascading simply involves paralleling the respective ENABLE,
LOAD DATA, and UP/DOWN signals while one CARRY-OUT signal drives the
COUNT IN input of the next M236.
APPLICATIONS
The' programmability of the M236 makes it ideal for use as a modulo-N
divider. Modification of the count length is easily done by setting the DATA
input lines to N and loading each time the count down reaches zero. When
counting down the MAX-MIN output goes HIGH when all twelve bits equal
zero.
FUNCTIONS
COUNT IN: Counting occurs on a positive transitio'n of the COUNT IN line.
This input must remain lOW for at least 50 ns before the count. Time between pulses can be no tess than 50 ns. There is no maximum for pulse
width or time between pulses. The maximum count frequency is 10 MHz.
ENABLE: The ENABLE input permits counting while it is HIGH, and disables
counting while it is LOW. Critical timing factors that must be observed when
changing the enabled state are:
66
1. To enable counting, the ENABLE line must remain HIGH from 70 ns

before to 30 ns after the positive transition of the COUNT IN signal.
2. To disable counting, the ENABLE line must go LOW at least 40 "s before
the COUNT IN signal goes LOW, and remain LOW until at least 40 ns
after the positive transition of the COUNT IN signal.
LOAD DATA: The outputs assume the same state as their associated data
inputs, independent of the count, when LOAD DATA goes LOW for at least
50 ns. Loading data overrides all other input signals and may be done at
any time. The maximum propagation delay from the LOAD DATA input to
any output is 50 ns. The DATA inputs will have no effect upon the outputs
within 15 ns after the LOAD DATA line goes HIGH.
UP/DOWN CONTROL: A logic LOW on this line yields an up count. A logic
HIGH on this line yields a down count. This control signal may be changed
when the COUNT IN signal is HIGH. It must not be changed while the
COUNT IN is LOW or during the 40 ns period before the COUNT IN signal
goes LOW.
&
CARRY OUT: When the counter has reached either the maximum up count
state (7777 octal) or the minimum down count state (0000 octa!), the
CARRY OUT signal follows the COUNT IN signal. The maximum delay time
from the COUNT IN transition to the CARRY OUT transition is 60 ns.
MAX-MIN: This provides a logiC HIGH output when the counter has reached
either the maximum up count state (7777 octal) or the minimum down
count state (0000 octal). The maximum delay time for this _output measured
from the positive going edge of the COUNT IN signal is 120 ns. This signal
is also used to accomplish look-ahead for very high speed operations.
Cascading: When cascading M236's, the CARRY OUT should be connected
to the COUNT IN of the next more significant unit. Also, the respective
LOAD DATA, UP/DOWN, and ENABLE signals must be paralleled.
67
M237
3-DtGIT BCD UP/DOWN COUNTER
NUMERIC
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$50
3 C1
LOAD LSB
MSB
OATAL
~ ~ '-----'
1-=.....---1(JUp L
DIGIT 3
DIGIT 2
DIGIT 1
ON H
(LSD)
(MSD)
MAX3-DIGIT BCD COUNTER
MIN H
........._ .....ENABLE H DIGIT 3
DIGIT 2
DIGIT 1
CARRY
A1
COUNT
(LSD)
(MSD)
~'---;INHJ L~ ~ ~B
Volts
+5
GND
Power
mA (max.)
330
OUT H
Pins
A2
C2. T1
The M237 is a 3-digit synchronous BCD upl down counter. It has a single
control input that can switch the counting mode from up to down without
disturbing the contents of the counter. The M237 is fully cascadable and
programmable. Cascading simply involves paralleling the respective ENABLE,
LOAD DATA, and UP! DOWN signals while one MAXI MIN signal drives the
ENABLE input of the next M237.
APPLICATIONS
The programmability of the M237 makes it ideal for use as a modulo-N
divider. Modification of the count length is easily done by setting the DATA
input lines to N and loading each time the count down reaches zero. When
counting down the MAX! MIN output goes HIGH when all three digits equal
zero.
FUNCTIONS
COUNT IN: Counting occurs on a positive transition of the COUNT IN line.
This input must remain LOW for at least 50 ns before the count. Time between pulses can be no less than 50 ns. There is no maximum for pulse
width or time between pulses. The maximum count frequency is 10 MHz.
ENABLE: The ENABLE input permits counting while it is HIGH, and disables
counting while it is LOW. Critical timing factors that must be observed when
changing the enabled state are:
68
1. To enable counting, the ENABLE line must remain HIGH from 70 ns

before to 30 ns after the positive transition of the COUNT IN signal.
2. To disable counting, the ENABLE line mustgo LOW at least 40 ns before
the COUNT IN signal goes LOW, and remain LOW until at least 40 ns
after the positive transition of the COUNT IN signal.
LOAD DATA: The outputs assume the same state as their associated data
inputs, independent of the count, when LOAD DATA goes lOW for at least
50 ns. Loading data overrides all other input signals and may be done at
any time. The maximum propagation delay from the LOAD DATA input to any
output is 50 ns. The DATA inputs will have no effect upon the outputs within
15 ns after the LOAD DATA line goes HIGH.
UP/DOWN CONTROL: A logic LOW on this line yields an up count. A logic
HIGH on this line yields a down count. This control signal may be changed
when the COUNT IN signal is HIGH. It must not be changed while the
COUNT IN is LOW or during the 40 ns period before the COUNT IN signal
goes LOW.
CARRY OUT: When the counter has reached either the maximum up count
state (999) or the minimum down count state (000), the CARRY OUT signal
follows the COUNT IN signal. The maximum delay time from the COUNT IN
transition to the CARRY OUT transition is 60 ns.
MAXMIN: This provides a logic HIGH output when the counter has reached
either the maximum up count state (999) or the minimum down count
state (000). The maximum delay time for this output measured from the
positive going edge of the COUNT IN signal is 120 ns. This signal is also
used to accomplish look-ahead for very high speed operations.
Cascading: When cascading M237's, the CARRY OUT should be connected
to the COUNT IN of the next more significant unit. Also, the respective
LOAD DATA, UP/ DOWN, and ENABLE signals must be paralleled.
69
MISCElLA
M261
FOUR-STATE MOTOR TRANSLATOR
NEOUS
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$40
P2
CK LEVEL H
1/0 SKIP
PULSE L
Ml DISA8l.E FEEOBACK PULSE L
110 SKIPL
R2
H2 FEEDBACK CLOCK
FEED8ACK
NZ DlACTlON A H
FFOII)
Nt DEVICE SELECT H
FFOIO)
B ENABLE H
A ENABLE H
Volts
+5
GND
Power
mA (max.)
175
Lt
FFI(I)
Kl
FFI(O)
D'
Ct
8'
AI
Pins
A2
C2. Tl
The M261 motor translator will develop the sequence of patterns necessary
to step a Sigma or Superior Electric type stepping motor (4 winding). It is a
2-bit switch-tail ring counter which, if initially cleared, would be in state 1.
(Fig. 1)
State
1
2
3
Flip
Flop
0
0
1
1
0
1
State Winding
2
3
4
0
0
1
1
0
0
0
1
1
0
0
0
1
1
= current supplied to winding

FIGURE 2
FIGURE 1
70
The state sequence (1,2, 3, 4, 1, .. or 1, 4, 3, 2, 1, ...) is determined

by the direction gating. The pattern for motor stepping (Fig. 2) is achieved
by assigning flip flop outputs to windings; AFFI(l), BFFO(l), CFF1(O),
DFFO(O). These buffered flip flop outputs can enable Kseries DC drivers to
energize the selected winding.
The translator is clocked by a High to Low transition on A CLOCK or B CLOCK.
The ORed clock signal must be jumpered externally to the counter (J2-K2).
DIRECTION is stored in an RS flip flop and can be loaded by asserting one
of the direction inputs Low. This arrangement facilitates the use of MI03 or
MI07 device selectors; the first pulse of an lOT (input/output transfer instruc
tion) sets the direction, the second clocks the counter.
For closed loop operation, the direction flip flop may be synchronized with
the motor shaft rotation. If there is a direction level available from the trans
ducer, this level should be asserted high when the direction of rotation is
the same as that represented by the A DIRECTION L input to the flip flop.
This gating may be disabled by DEVICE SELECT H. The clock input for feed
back operation is a Low to High transition and is ORed with the other clocks
after gating. The two gating signals are an enable, asserted High, and a pulse
or leve' asserted Low which truncates the clock pulse after it has made its
transition. This is necessary because the clock signal is from an asynchron
ous device and is often a square wave which remains High a long time (20100 MS) after the clocking transition. This High level at the clock input of the
counter will mask subsequent transitions on the other clock inputs.
This module may be used in conjunction with the I/O skip facility on a com
puter. An lOT at I/O SKIP PULSE L and both flip fiops in the zero state will
cause 1/0 SKIP L to be generated.
The unbuffered flip flop outputs are available for additional gating. These lines
are electrically distinct from the buffered outputs.
71
MISCELLA
NEOUS
M262
TEN-STATE MOTOR TRANSLATOR-
M SERIES
Price:
Length: Standard
Height: Double
Width: Single
$65
AE2 ...11...:1doW>"'--_-,
AF2
AP2
B CLOCK
A82 ENABLE FEEDBACK LEVEL H
110 SKIP
PULSE L
B.J2 DISABLE FEEDBACK PUlSE L

AR2
AH2 FEEDBACK CLOCK
82
5 BIT
COUNTER
FEEDBACK
'--.:....:.=~BL2
AN2 DlRECTKlN A H
L-----!.:!:..!!.l.t......8N2
8U2 DEVICE SELECT H

L-----'-!.;"-!..!L...
BR2
L--~~~BT2
-'-'-=... BV2
L . -_ _
SHOWN WIRED
FOR A 10-STATE
TRANSLATOR
Power
mA (max.)
350
Pins
AA2,BA2
AC2, BC2
The M262 motor translator will generate the sequence of patterns necessary
to step a Fujitsu type stepping motor (5 winding). It is a double height
module with a five bit switch-tail ring counter which may be truncated to four
or three bits by external jumpers.
BM-BN
BP-BR
BR-BS
BM-BN
BP-BN
BT-BS
BL-BP
BT-8M
IO-state jumpers
8-state jumpers
6-state
72
j~mpers
2
3
4
1
1
1
1
0
0
0
0
0
0
0
0,
0
1
1
0
0
0
0
0
1
1
State FLIP FLOP
5
6
7
a
9
10
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
0
2
3
4
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
5
6
7
a
1
1
1
Winding
State
1
1
0
0
0
0
0
10
FIGURE 2
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
FIGURE 3
= current supplied to winding
FF2 is removed for the a-state counter and both..FFl and FF2 are bypassed
for the 6-state counter_
.
After the counter is cleared it will be in state 1. (Fig_ 2) The state sequence
(1. 2, 3. 4, 5, 6. 7, 8. 9, 10, 1 ___ or 1, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 _ - .)
is determined by the direction gating. The pattern for motor stepping (Fig. 3)
is achieved by assigning flip flop outputs to windings; FFO(I)-A FF2(1)-B,
FF4(l)-C, FFl(O)-D, FF3(0)-E. These buffered flip flop outputs can enable
K-series DC drivers to energize the selected windings.
The translator is clocked by a High to Low transition on A CLOCK or B CLOCK.
The ORed clock signal must be jumpered externally to the counter (AJ-AK).
Direction is stored in an RS flip flop and can be loaded by asserting one of the
direction inputs Low. This arrangement facilitates the use of MI03 or MI07
device selectors; the first pulse of an lOT (input output transfer instruction)
set the direction, the second clocks the counter.
With a 5-bit counter there are 32 (25) possible states, but the counter is
clocked through a ring of only 10 states (Fig. 2). Gating is available to detect
illegal states and clear the counter to state 1. This gating must be connected
by an external jumper (BD-BE).
For closed loop operation, the direction flip flop may be synchronized with
the motor shaft rotation. If there is a direction level available from the transducer, this level should be asserted High when the direction of rotation is the
same as that represented by the A DIRECTION L input to the flip flop. This
gating may be disabled by DEVICE SELECT H. The clock input for feedback
operation is a Low to High transition and is ORed with the other clocks after
gating. The two gating signals are an enable, asserted High, and a pulse or
level asserted Low which truncates the clock pulse after it has made its transition. This is necessary because the clock signal is from an asynchronous
device and is often a square wave which remains high a long time (20-100
,us) after the clocking transition. This High level at the clock input of the
counter will mask subsequent transitions on the other clock inputs.
This module may be used in conjunction with I/O skip facility on a computer. An lOT at I/O SKIP PULSE L and both flip flops in the zero state will
cause I/O SKIP L to be generated.
The unbuffered flip flop outputs are available for additional gating. These
lines are electrically distinct from the buffered outputs.
73
TIME
M302
RELATED
DUAL DELAY MULTIVIBRATOR

M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$46
PI
".
NOTE:
THESE. PINS MUST BE
JUMPERED IF THERE
IS NO EXT POT
SEE TABL
Volts
+5
GND
Power
mA (max.)
166
Pins
A2
C2. T1
The M302 contains two delays (one-shot multivibrators) which are triggered
by a level change from HIGH to LOW or a pulse to LOW whose duration is
equal to or greater than 50 ns. When the input is triggered,- the output
changes from LOW to HIGH for a predetermined length of time and then
returns to LOW.
The delay time is adjustable from 50 ms to 7.5 ms using the internal capacitors and can be extended by adding an external capacitor.
APPLICATIONS
Time delays
Variable width pulses
FUNCTIONS
Defay Range: The basic DELAY RANGE is determined by an internal capacitor. The delay range may be increased by selection of additional capacitance
which is available by connecting various module pins or by the addition of
external capacitance. An internal potentiometer can be connected for fine
74
delay adjustments within each range or an external resistance may be used.

If an external resistance is used, the combined resistance of the internal
potentiometer and the external resistance should be limited to 10,000 ohms.
Interconnections Required
Delay Range
50 ns -750 ns
500 ns -7.5 IJ-S
5 IJ-s-15 IJ-S
50 IJ-S -750 IJ-S
500 IJ-S -7.5 ms
Above 7.5 ms
Capacitor Value
Delay 1
Delay 2
100 pF (internal)
1000 pF (internal)
0.01 IJ-F (internal)
Add external
capacitors b~tween
specified pins
None
D1-L2
H1-L2
J1-L2
E1-L2
Fl-L2
None
Nl-52
51-52
U1-S2
PI-52
Rl-52
Adjustable Delays: Connect pins D2 to E2 for delay 1 and V2 to R2 for

delay 2 in order to add the internal potentiometers. NOTE: If there is no
external pot, these pins must be jumpered.
Without a potentiometer, the delay will not recover. An external potentiometer of less than 10 K ohms can be used by connecting it between E2 or R2
and ground pin C2. Use of an external adjustment resistor will cause some
increase in jitter. It is recommended that leads to an external potentiometer
be twisted pairs and as short as possible.
PRECAUTIONS
Care should be exercised in the selection of external capacitors to assure
low leakage as leakage will affect the time delay.
SPECIFICATIONS
Trigger Input Fall Time: Must be less than 400 ns
Recovery Time: Defined as the time all inputs must remain HIGH before any
input goes LOW to trigger the delay
l. Without external capacitance: 30 ns min.
2. With external capacitance: 300 C ns min. where C is in nanofarads
75
TIME
RELATED
M306
INTEGRATING ONE SHOT
M SERIES
Price:
Length: Standard
Height: $ingle
Width: Single
$27
INTEGRATING
ONE-SHOT
02
E2
EXT. TIMING
RESISTOR
EXT. TIMING
CAPACITOR
Power
mA (max.)
120
Volts
+5
GND
M2
L2
Pins
A2
C2,T1
The M306 is a zerorecovery-time integrating monostable multivibrator with

complementary outputs. The M306 has the ability to respond to an input
even while in the active state, so that successive inputs above a preset
frequency can postpone the return to the inactive state indefinitely.
FUNCTIONS
The operation of the M306 is illustrated in the timing diagram shown below:
Input applied
to pin H2
or JA
+1.5VJ
I
I
ITpDt
\4I
---+1
I
I
I
I
Output at
pin T2
"y+1.5V
\:1.5V
I
I
I
I
\,:t.5V
14
at
The integration period is measured from the trailing edge of the input pulse
to the trailing edge of the output pulse. The approximate integration time
may be calculated by the following:
t
.87 (R
+ 700 n) (C + 175
76
10. 12 F)
where R is in ohms and C is in farads. The width of the input pulse is independent of the integration time.
TIming Capacitors: Coarse adjustment of the integration period is accomplished by customer-supplied" capacitors which may be attached to module
pins L2 and M2. When using polarized capacitors, the positive terminal
should be connected to pin L2. Two split lugs are provided on the module
for those customers who would like to permanently install the capacitor on
the module itself. The minimum equivalent parallel resistance of capacitor
leakage should always exceed 250K ohms.
Timing Resistance: Fine adjustment of the timing period may be accomplished by a multiturn potentiometer provided on the module. Provision is
also made to allow the customer to connect an external timing resistor or
potentiometer between pins 02 and E2. When an external potentiometer
is used, care should be taken to prevent the coupling of externally generated
electrical noise into the module. The maximum resistance of the timing resistance, including the internally provided potentiometer, should not exceed
25,000 ohms. If an external timing resistor is not used, pins 02 and E2 must
be connected together.
SPECIFICATIONS
Trigger Duration: An input pulse of 30 ns will trigger the M306. TPOI
40 ns max.
Output Duration: The minimum pulse width is 225 ns and maximum pulse
width is limited only by capacitor leakage (40 sec is a typical maximum).
Stability: The inherent temperature stability of the M306 is normally -.06%

per degree C, exclusive of the temperature coefficient of the timing capacitor.
77-
TIME
RELATED
M310
DELAY LINE
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$58
~El ..
J'~
Volts
+5
GND
Power
mA (maX'.)
89
Pins
A2
C2, T1
The M310 consists of a tapped delay line with associated circuitry and two
pulse amplifiers. The total delay is 500 nanoseconds with taps available at
50 nanosecond intervals.
APPLICATIONS
Timing pulse trains
Pulse spaCing
FUNCTIONS
The time delay is increased when the amplifier is connected to the delay
line taps in ascending order as follows: J2, K2, l2, M2, N2, P2, R2, 82,
T2, U2, and V2. The tap J2 yields the minimum delay and the tap V2 yields
the maximum delay.
The pulse amplifiers are intended to be used to standardize the outputs of

the delay line. The output of the pulse amplifier is a positive pulse whose
duration is typically 50 to 200 nanoseconds. These amplifiers are not intended to be driven by TTL Ie logic.
78
Ml60
VARIABLE_ DELAY
_ ______
_
1L--_
__
nME
RELATED
M SERIES
PrIce:
Length: Standard
Height: Single
Width: Single
~~
~E
DELAY
*"SINKS 30MA TO GND.

+20V MAX.
Volts
<t~D
Power
mA (max.)
50
Pins
A2
C2, T1
The M360 contains an adjustable delay line with a standardizing amplifier.

The delay is adjustable between the limits of 50 ns to 300 ns by means of
a slotted screw which is accessible from the handle end of the module.
FUNCTIONS
The output consists of a positive pulse whose width is nominally 100 nano
seconds and the leading (positive going voltage) edge of which is delayed
with respect to the leading (positive gOing voltage) edge of the input by a
length of time determined by the setting of the delay line adjustment.
Pins T and V are outputs consisting of open collector NPN transistors that
can sink 30 milliamperes to ground.
Precautions: Voltage applied to pins T and V must not exceed +20 volts.
SPECIFICATIONS
The resolution of the delay adjustment is approximately one nanosecond.
79
TIME
RELATED
M401
VARIABLE CLOCK
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$55
VARIABLE CLOCK
..,
SEE TABLES
Volts
+5
GND
Power
mA (max.)
80
Pins
A2
C2. Tl
using printed circuit board revision E or later
The M401 Variable Clock is a stable RC-coupled multivibrator which produces standard timing pulses at adjustable repetition rates.
Repetition rate is adjustable from 175 Hz to 10 MHz in five ranges. Internal
capacitors, selected by jumper pin connections, provide coarse frequency
control. An internal potentiometer provides continuously variable adjustment
within each range.
A 0 to 10 volt control voltage will vary the frequency over about 30% of
each frequency range.
APPLICATIONS
This module is intended for use as the primary source of timing signals in
digital system.
FUNCTIONS
Start Control: A two-input OR gating input is provided for start-stop control
of the pulse train. A level change from HIGH to LOW with fall time less
than 400 ns is required to enable the clock.
Frequency Range:
Interconnections Required
Frequency Range
1.5 MHz to
10 MHz
175 KHz to 1.75 MHz

17.5 KHz to 175 KHz
1.75 KHz to 17.5 KHz
175 Hz to 1.75 KHz
(100 pf)
(1000 pf)
(.01 J4fd)
(0.1 Jtfd)
(1.0 ~fd)
80
NONE
N2-R2
N2-S2
N2 ---' T2
N2-P2
Fine Frequency Adjustment: Controlled by an internal potentiometer. No provision is made for any external connections. An external capacitor may be
added by connection between pins N2 and C2.
Voltage Control of Frequency: The M401 may also be voltage controlled
by applying a control voltage to pin M. This feature is available only in
M401 modules using printed circuit board revision E or later. The voltage
applied to pin M should be limited to the range of 0 volts to +10.0 volts.
This voltage swing will allow the frequency to be shifted by approximately
30 percent in the frequency range using the internal capacitors of 1.0, 0.1,
0.01 and 0.001 p,F. If the voltage applied to pin M is dc or low frequency
(below 1 kHz), pin M will appear approximately as a + 1.0 volt source with
a Thevenin resistance of 800 ohms. Modulating the M401 with a 10 volt
p.p signal about a center frequency, as derived by the application of a mean
voltage of +5 volts to pin M, will yield a typical frequency excursion in excess of plus or minus 15% about the center frequency. Typical frequency
excursions which may be obtained are shown below:
Voltage
applied to
Pin M
CAPACITOR
.001 ufd.
1.0 ufd.
0.1 ufd.
0.01 ufd.
10.00
10.49
10.94
100.0
1000
+1
+2
1.000
1.054
1.101
+3
+4
+5
+6
+7
+8
+9
+10
1.147
1.193
1.238
1.282
1.325
1.368
1.408
1.443
11.39
11.83
12.26
104.6
109.2
113.6
118.0
1036
1071
1108
1142
1181
1271
1295
1312
1322
1323
12.69
13.10
13.50
13.87
14.20
122~2
126.4
130.4
134.2
137.7
140.9
Output frequency
in KHz
SPECIFICATIONS
Enabling inputs to output E2 is 50 nanoseconds. The output pulse width is
50 nanoseconds.
81
TIME
M403
RC MULTIVIBRATOR CLOCK
RELATED
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$30
EXT CAP
(PULSE WIDTH)
1 HZ
ENABLE
F2
CLOCK
OUT
FREQ
......
(EXT
CAP
COM
CAP
INTL CAP \
A B C
SPLIT
LUGS
K2
Volts
, t~D
52
Power
rnA (max.)
70
2M2
Pins
A2
C2. T1
The M403 is an RC Multivibrator Clock which produces standard lO-microsecond timing pulses at repetition rates adjustable from 1 kHz to 50 kHz
in three ranges. Internal capacitors, selected by jumper pin connections, provide coarse frequency control, while an internal potentiometer provides continuously variable adjustment within each range.
APPLICATIONS
This module can be used as a source of digital timing signals.
FUNCTIONS
ENABL~ Input: The clock circuit is enabled by a HIGH level on pin H2. If a
LOW level is applied to pin H2, the clock output at F2 will time out and
return to ground and the output at pin J2 will time out and go HIGH. To
prevent an erroneous count, pin H2 should not be retriggered for one complete period. This will allow the circuit to settle.
Selecting Frequency Range: The frequency range is selected by jumpers at

backplane pins:
FREQUENCY RANGE
INTERCONNECTION REQUIRED
N2-S2
M2-S2
L2-S2
1 kHz to
5 kHz
5 kHz to 20 kHz
20 kHz to 50 kHz
82
Lowering Frequency: If frequencies below the capabilities of this circuit are

necessary, external capacitance can be added. Time 2 (see illustration) can
be changd by installing capacitors to the split lugs provided or between pins
K2 and 82. New timing values can be calculated using the following
equation:
---l10p~
___T_1j1.......-T2j1'--____
CLOCK H OUTPUT
T2=O.32RC (1+0.7/R)
T2 is in seconds, R is in ohms, and C- is in farads.- The internal potentiometer varies between 5.1 K and 50K ohms.
Increasing Pulse Width: Larger pulse widths can also be obtained by adding
capacitance to the other set of split lugs provided or between pins E2 and
02. The same equation as above may be used for T1 with the following
exception:
c = 4.7 picofarads + capacitance added

SPECIFICATIONS
Rise Time: 25 ns (max.)
Fall Time: 25 ns (max.)
83
M404
CRYSTAL CLOCK
TIME
RELATED
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$65
......,0 2MHz
r-----~----+_._.--"'
t-----+-.......---IIt..j'O 1MHz
t-----+-......._ T
.;.;:2"-t1O 500KHz
t--_ _-+-............;R:.,::2:...j,O 2~~z
DIVIDER
CIRCUIT
2MHz
CLOCK
P2
t----+_.--'-'
=-i1O 125 KHz
M2
t----+_.......-=--t10 100KHz
N2
t - - - - t -.......---==--4tO
~ KHz
L2
t - - - - t -.......--=
=-i,O 25KHz
t - - - - - t -.......--L>I1It..j1O 25KHz
t--_ _-+-.......~D2~tO 10KHz

t-----+-.......-=:1I..I1O 5KHz
The M404 clock contains a 2 MHz crystal oscillator and frequency dividers.
A HIGH on the CLEAR input clears the frequency divider and all outputs
go LOW.
SPECIFICATIONS
Accuracy: Maximum error from specified output frequency is 0.01 % between
o degrees C and +55 degrees C.
84
TIME
RELATED
M405
CRYSTAL CLOCK
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$100
Volts
+5
GND
Power
mA (max.)
50
Pins
A2
C2, T1
The M40S employs a crystal oscillator to provide a highly stable, precisely

known frequency between 5 kHz and 10 MHz. The frequency within this
range may be specified by the user.
.
APPLICATIONS
Stable clock frequencies
FUNCTIONS
. Outputs: Outputs at pins 02 and E2 are respectively positive and negative
going 50 ns pulses. Pulses at pins 02 and E2 are time shifted by one gate
delay with the negative pulse at pin E2 leading the positive pulse at 02 by
a maximum of 20 ns. The output pulse width can be modified by the ad
dition of an external capacitor between pins K2 and H2. This capacitor will
increase the output pulse width by approximately 1 ns per 2.S pF of addi~
tional capacitance.
SPECIFICATIONS
Frequency Stability: 0.01 % of specified value between 0 degrees C and +55
degrees C.
Ordering Information: When ordering the M405, always specify frequency.
Allow six weeks for delivery.
Standard Stock Frequencies: 1.333 MHz, 2.000 MHz, 5.000 MHz.
85
TIME
RELATED
M410
REED CLOCK
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$70
CLOCK
Fe
M
F8I2{
9
9
F0I4
OJ P2
... ,JONE-SHOT
Volts
+5
I'"
Power
mA (max.)
95
R2[!Q]
Pins
A2
C2, Tl
The M410 is a free-running contactless-resonant-reed-tuned clock which

provides stable timing signals for a system using the M706 and M707 Teletype converter modules.
FUNCTIONS
Outputs: Pin R2 drives 10 unit loads with a nominal 150 ns positive output
pulse. Pin J2 drives 30 unit loads at FO. Under normal operating conditions,
pins L2, M2, N2 are used as test points. Pins N2 and M2 drive 9 unit loads
at FO/2. Pin L2 drives 9 unit loads at FO/4. Pin K2 drives 30 unit loads
at FO/4.
SPECIFICATIONS
Overall Frequency Stability: Better than 0.1 % in the temperature range from
o degrees C to 70 degrees C. Available clock frequencies are listed below.
A pulse amplifier is provided for the generation of nominal 150 ns pulses.
Available Frequencies: (FO in Hz)

400 (50 baud), 550, 600 (75 baud),
750,880 (110 baud), 1200 (150 baud), 1800, 2000, 2200, 2400 (300 baud).
86
TIME
RELATED
M452
VARIABLE CLOCK
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$40
K
88OHZt-----t
..2 9
~ { ~----------~~~N2~9
~OHZ~~--------~~~
[JP2
..
I.fONE-SHOT
Volts
c.t~D
I.
Power
mA (max.)
77
R2~
Pins
A2
C2. T1
The M452 is a free-running clock which generates the necessary timing

signals for the PDP-S/I Teletype control. The available output frequencies
are 880 Hz, 440 Hz and 220 Hz. The pulse amplifier is provided for the generation of nominal 150 ns pulses.
APPLICATIONS
PDP-S/I Teletype Control

FUNCTIONS
Pin J2 drives 30 unit loads at 880 Hz. Pins N2 and M2 drive 9 unit loads
at 440 Hz. Pin L2 drives 9 unit loads at 220 Hz. Pin K2 drives 30 unit loads
at 220 Hz. Pin R2 drives 10,unit loads with a nominal 150 ns positive output
pulse. Under normal operating conditions, pins l2, M2, N2 are used as
test points.
SPECIFICATIONS
Frequency adjustment of this module is limited to less than 5% and the

overall clock stability with respect to supply voltage and temperature variations is about 1 %.
..87
TIME
RELATED
M501
SCHMITI TRIGGER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$25
+5V
~
SWITCH INPUT
TIME CONSTANTS
R2
F2
I"'"
AND
EXPANO P2
SCHMITT
TRIGGER
'lA.
OUTPUT
...
ro...I
E2,O
R1
OR
N2
EXPAND
R2
680
R3
230
120
L2
+5V
00 . ANALOG INPUTS
UPPER
M2
LOWER
THRESHOLD
Power
Volts
mA (max.)
Pins
+5
31
A2.
GND
C2
The M50l is a Schmitt Trigger with variable thresholds and complementary

positive logic outputs.
APPLICATIONS
Switch Filter
Pulse Shaper
Threshold Detector
FUNCTIONS
The input on pin R2 is compared with the thresholds set on pins l2 and
M2 UPPER and LOWER respectively.
Pin F2 goes to LOW when the input on R2 rises above the UPPER THRESH-.
OLD, having been below the LOWER THRESHOLD.
Pin F2 rises to +3 volts when the input on R2 falls below the LOWER
THRESHOLD, having been above the UPPER THRESHOLD.
Pin E2 is the complement of F2.
Miscellaneous Input Functions: AND and OR expansion may be performed
on P2 and N2. Modules ROOl and ROl2 provide the diodes required. An
integrator is provided on the input, allowing switches to be connected to
the Schmitt Trigger with contact bounce effects eliminated. Two switch time
constants are provided. Inputs to pin S2 result in a 7 ms time constant to
pin U2 3.5 ms.
88
ANO,OR EXPANSION
+5V
R2
+5V
2.7K
Oscillator Connection: Connecting a resistor from output pin F to input pin R

with pin T tied to pin R forms an oscillator.
+5V
300Q
MAX.
SPECIFICATIONS
Input Signal Swing: The voltage on pin R2 is limited to plus or minus 20
vQlts.
Thresholds: The UPPER and LOWER THRESHOLDS are preset at 1.7 and 1.1
volts. They may be modified by the addition of a resistor in parallel with the
'internal network; however, the UPPER THRESHOLD must not exceed 2.0
volts or the LOWER THRESHOLD fall below 0.8 volts.
IN
R
R
PARALLEL WITH
PARALLEL
PARALLEL
R2 R1 R3 -
THRESHOLD CLOSER
UPPER RISES
LOWER FALLS
Input Pin R2 Loading: 2.7K ohms to +5 volts or 1.8 rnA at ground.

Pin
Pin
Pin
Pin
Pins
P2
N2
S2
U2
L2,
AND EXPAND input

OR EXPAND input ,
RC SWITCH input filter 7 ms
RC SWITCH input filter 3.5 ms
M2 are available for threshold modification
89
TIME
M521
K TO M CONVERTER
RELATED
M SERIES
ttrice:
Length: Single
Height: Single
Width: Single
$16
mE2
..
[!]K2 ..
[it2
..
~2
Volts
t~D
: =:
: ~:
: ::
: ::
I" M~
I" M~
I" M~
I" M~
Power
mA (max.)
56
Pins
A2
C2
The M521 K Series to M Series Converter contains four circuits which can.
convert any K Series input to complementing M Series outputs.
APPLICATIONS
Rise Time Conversion -
K to M Series
FUNCTIONS
Typically, a K Series input would have a 7 p'S rise time and a 1.5 p'S fall time.
The M521 speeds both these rise and fall times to approximately 15 ns.
The input circuit has built-in hysteresis and is slowed to a maximum frequency of 100 KHz.
SPECIFICATIONS
Each input represents three K Series unit loads.
90
TIME
RELATED
M602
PULSE AMPLIFIER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$28
PAZ
R2
S2
INTERNAL CAPACITORS*
*-JUMPER E2-D2 OR R2-S2 FOR 110n.
PULSE WIDTH. STANDARD PULSE
WIDTH IS 5On.
Volts
+5
Power
mA (max.)
213
Pins
A2
C2. T1
GND
The M602 contains two pulse amplifiers which provide power amplification,
standardize pulses in amplitude and width, and transform level changes into
a standard pulse.
FUNCTIONS
A negative pulse output is produced when the input is triggered by a transition from HIGH to LOW. An internal capacitor is brought out to pin connections to permit the standard 50 ns output pulse to be increased to
110 ns (nominal).
SPECIFICATIONS
Propagation Time: 30 ns max. between input and output thresholds.
Recovery Time: Equal to that of the output pulse width. The input must have
a fall time (100/0 to 90% points) of less than 400 ns and must remain
below 0.8 volts for at least 30 ns. Maximum PRF is 10 MHz.
91
TIME
RELATED
M606
PULSE GENERATOR
M SERIES
length: Standard
Height: Single
Width: Single
~:~
~~2
Price:
$43
{D
,K2 :
~~ :
1 P2
~~
,S2
D
D
D
D
D
D
~JI
:.,
{D
c6J
c{D
[J
~
Volts
t~D
Power
mA (max.)
188
Pins
A2
e2, T1
92
D2~
F2~
J2~
L2~
.N2~
R2~
The M606 contains six pulse generators.
APPLICATIONS
The M606 may be used for setting or clearing of flipf1ops by applying the
output of the M606 to the direct CLEAR or SET inputs of up to 14 flip-flops.
FUNCTIONS
Each circuit will produce a pulse to ground in response to a level shift from
HIGH to LOW to the input.
Each circuit contains an INHIBIT input. The output is inhibited when the
INHIBIT input is grounded. If this input is not used, it should be tied at a
logic HIGH.
Pin VI is a source of logic HIGH and can supply ten unit loads.
SPECIFICATIONS
All outputs consist of a pulse to ground level with a time duration of at
least 30 ns but not greater than 100 ns.
93
M610
OPEN COLLECTOR
TWO-INPUT NAND GATE
GATES
M SERIES
Price:
Length; Sta nda rd

Height: Single
Width: Single
~::
~::
~::
D
D
D
$20
..
~L'
D
~~
D
~:: : D
*.
D200
., F200
[]V2
Volts
+5
GND
.,
L2[!J
.,
N2l!J
..
~[!]
:M2 :
,P2 :
J2[E]
I~~~~RI ..
Power
mA (max.)
41
OPEN COLLEClOA
(SEE TEXT)
U2[!]
Pins
A2
C2, El, HI
Ml, PI, 51
The M610 contains 8 two-input NAND gates with open collector outputs.
It also contains a pulse amplifier which does not have an open collector
output.
94
SPECIFICATIONS
Outputs: 02, F2, J2,. L2, N2, R2
are capable of sinking 16 rnA to ground.
NAND Gate Maximum Propagation Delay: 15 ns when the output goes from
HIGH to LOW; however, when the output goes LOW to HIGH, the propagation
delay depends upon the load impedance. As an example, with the load
shown in the figure, the maximum propagation delay time from a logic LOW
to a logic HIGH is 45 ns.
Pulse Amplifier Maximum Propagation Delay: 60 ns for both HIQH going

and LOW going output pulse transitions.
95
LOGIC
M617
FOUR-INPUT POWER NAND GATE
AMPLIFIERS
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$26
AI
81
CI
01
NI
PI
RI
+3V
Volts
t~D
Power
I: ~::
mA (max.)
97
Pins
A2
C2. T1
The M617 contains 6 four-input NAND gates each capable of driving up to

30 unit loads.
FUNCTIONS
Physical configuration and logical operation are identical to the M 117.

SPECIFICATIONS
Typical gate propagation delay is 15 ns.
96
LOGIC
AMPLIFIERS
M627
NAND POWER AMPLIFIER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$29
i~:~ p:
ij:~ p
i~!~ p
Volts
d~D
Power
mA (max.)
136
Pins
A2
C2. Tl
i~~ p
..
i~~ P
E1@
.. J2@'g
i~~ p
S1~
+3V
V21!j_
I : ~::
The M627 provides six 4-input NAND gates that combine power amplification
with high-speed gating.
APPLICATIONS
For high fan-out of clock or shift pulses to expanded coun,ters and shift
registers.
PRECAUtiONS
L In pulse amplifier applications, unused inputs should be connected
to the +3 volt pins provided.
2. To utilize the timing accuracy of this module, wire runs of minimum
length are recommended.
SPECifiCATIONS
Propagation TIme: Typically 6 ns between input and output transitions.
97
LOGIC
M660
AMPUFIERS
POSITIVE LEVEL CABLE DRIVER

M SERIES
Length: Standard
Height: Single
Width: Single
~H2
_J2 :
1
~::
~::
Price:
$25
0
0
0
Volts
+5
GND
0200
[> .
K2[!]
.~
S2[!]
*=~mA DRIVE
Power
mA (max.)
71
Pins
A2
C2
The M660 Cable Driver consists of three NAND gate circuits each of which
will . drive a IOO-ohm terminated cable with M Series levels. or pulses of
duration greater than 100 ns.
SPECIFICATIONS
Outputs: Can sink 50 mA at a logic LOW, and can source 50 mA at a logic
HIGH.
98
LOGIC
M661
POSITIVE LEVEL DRIVER
AMPLIFIERS
Price:
Length: Standard
Height: Single
Width: Single
$15
)l----f[> .
;:: :
1 T2
[>
*= 20mA
5mA
Volts
+5
GND
Power
mA (max.)
111
02[E]
S2~
AT OV
AT+3V
Pins
A2
C2
The M661 contains three AND circuits which may be used to drive low
impedance unterminated cable with M Series logic levels or pulses of duration greater than 100 ns.
SPECIFICATIONS
Outputs: Can sink 20 rnA at a logic LOW, and can source 5 rnA at a logic
HIGH.
99
TIME
RELATED
M671
M TO K CONVERTER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$52
Volts-
+5
GND
Power
mA (max.)
112
Pins
A2
C2
The M671 M Series to K Series Converter contains four pulse stretc!hing circuits which can convert an M Series input pulse of duration exceeding 50 ns
to complementary K Series output pulses of 10 to 15 p.S.
FUNCTIONS
Triggering: When the ENABLE input is HIGH, the delay is triggered by the
negative-going edge of the trigger input pulse:
100
This circuit is insensitive to input transitions during its timeout period as

shown in the example above.
Increasing Output Pulse Width: Nonelectrolytic capacitors can be connected
to the split lugs provided in each circuit if K Series output pulse widths
longer than 15 p'S are desired. Pulses of up to 40 seconds are possible using
this technique. When capacitance is added, the output pulse. width is increased by 6400 C seconds where C is the capacitance added in farads.
SPECIFICATIONS
Output drive: Each output is capable of driving a 15 rnA load.
101
MISCELLA
NEOUS
M706
TELETYPE RECEIVER
M SERIES
Length: Standard
Height: Double
Width: Single
Price:
$150
DEVICE
SELECTOR
COOE
XV
ENABLE OS I I-'A.;;..P.;..I---+---~::J
-o
REAOER ON I FA~"2=-t--lI-_ _ _ _+-_ _ _
~~----r-----'o--------~~~~~~~~FL~
BO
FLAG STROBE I F ;:,2=-t--lI------+--+----i FL~
J2=-t--lI-_ _ _ _+--+_ _- i CONTROL
CLEAR FLAG I I FB""
AF2
D-_______+-..=BE:::2~
~EARF~2 IfBO~I~~r---------_r-i----;_ _ _~--------1_~A~E=,2

8X~
---+-------t
3 rAN::.:!....1
ENABLE IF~~I~~~----,
I/O CLEAR I I"Be..FI!......t--lI-_ _ _ _-f
PIN CONNECTIONS:
FOR 5 OR 8 BIT COPE
5 BIT-AM2 TO AJ2
AR1 TO GNO
B BIT-AM2 TO ARt
AJ2 TO AKt
FOR STOP TIME
1.0 UNlTS-BP2 TO BT2
~ TOBU2
1.5\l11ITS-8P2 TO BSI
BR2 TO BU2
2.0UNITS-BPZ TO BT2
~ TOBV2
~llTro
SHIFT
REGISTER D---------+-;~~
BT2
BUI
~~ 4FB~M~2__~---------------~
RE~R t~A~L~I--_+_-----------------~
INPUT
OUTPUT
*-THIS
CAN DRIVE A
2DmA LOAD TO.0.1 \IOLTS
Volts
+5
GND
Power
mA (max.)
Pins
400
AA2. BA2
AC2, ATl. BC2. BTl
102
rr~
r
}
The M706 Teletype Receiver is a serialtoparallel teletype code converter self

contained on a double height module. This module includes all of the serial
- toparallel conversion, buffering, gating, and timing (excluding only an external
clock necessary to transfer information in an asynchronous manner between
a serial data line or teletype device and a parallel binary device). Either a
5bit serial character consisting of 7.0, 7.5, or S.O units or an Sbit serial
character of 10.0, 10.5, or 1 LO units can be assembled into parallel form
by the M706 through the use of different pin connections on the module.
When conversion is complete, the start and stop bits accompanying the serial
character are removed. The serial character is expected to be received with
the start bit first, followed by bits 1 through S in that order, and completed
by the stop bits. Coincident with reception of the center of bit eight, the
Flag output goes low indicating that a new character is ready for transmission
into the parallel device. The parallel data is available at the Bit 1 through
Bit 8 outputs until the beginning of the start bit of a new serial character as
received on the serial input. See the timing diagram of Figure 1 for additional
information.
In addition to the above listed features, the M706 includes the necessary
logic to provide rejection of spurious start bits less than one half unit long,
and halfduplex system operation in conjunction with the M707. Device
selector gating is also provided so that this module can be used on the
positive 1/0 bus of either the PDPS/I or the POPS! L. To obtain additional
applications information on the M706, write for Applications Note ApM-013.
Inputs: All inputs present one TTL unit load except where noted. When input
pulses are required, they must have a width of 50 nsec or greater.
Clock: The clock frequency must be eight times the serial input bit rate
(baud rate). This input can be either pulses or a square wave. Input loading
on the clock Hne is three unit loads.
Enable: This input when brought to ground will inhibit reception of new char
acters. It can be grounded any time during character reception, but returned
high only between the time the Flag output goes to ground and a new char
acter start bit is received at the serial input. When not used this input should
be tied to a source of +3 Volts.
I/O Clear: A high level or positive pulse at this input clears the Flag and
initializes the state of the control. When not used, or during reception, this
input should be at ground.
Code Select Inputs: When a positive AND condition occurs at these inputs
the following signals can assume their normal control functions-Flag Strobe,
Read Buffer, and Clear Flag 1. Frequently these inputs might be used to
multiplex receiver modules when a signal like Read Buffer is common to
many modules. The inputs can also be used for device Selector inputs when
the M706 is used on the positive I/O bus of the POPS/ I or POPSI L. The code
select inputs must be present at least 50 nsec prior to any of the three
signals that they enable. If it is desired to bypass the code select inputs,
they can be left open and the Enable D.S. line tied to ground.
Clear Flag 1: A high level or positive pulse at this input while
inputs are all high, will clear the Flag. When not used, this
grounded. Propagation delay from input rise until the Flag
maximum of 100 nsec. The Flag cannot be set if this input
103
the code select

line should be
is cleared is a
is held high.
Clear Flag 2: A high level or positive pulse at this input. independent of the
state of the code select inputs, will clear the Flag. All other characteristics
are identical to those of Clear Flag 1.
Flag Strobe: If the Flag is set, and the code select inputs are all high, a
positive pulse at this input will generate a negative going pulse at the Strobed
Flag output. Propagation delay from the strobe to output is a maximum of
30 nsec.
Read Buffer: A high level or positive pulse at this input while the code select
inputs are all high will transfer the state of the shift register to outputs Bit 1
through Bit 8. Final parallel character data can be read by this input as soon
as the Flag output goes to ground. Output data will be available a maximum
of 100 nsec after the rising edge of this input. See the timing diagram of
Figure 1 for additional information.
Reader On: A low level or ground at this input will turn the internal reader
flip-flop on. This element is turned off at the beginning of a received character
start bit. This input can also be pulsed by tying it to one of the Signals derived
at output pins AE2 or BE2. A low output will exist at pin BE2 if the M706
is addressed and the clear Flag 1 (pin BJ2) is high. A low output will exist at
pin AE2 if the M706 is addressed and the Clear Flag 1 (pin BJ2) is high or if
Clear Flag 2 (pin B01) is high.
Serial Input: Serial data received on this input is expected to have a logical
zero (space) equal to +3 Volts and a logical 1 (mark) of ground. The input
receiver on the M706 is a schmitt trigger with hysterisis thresholds of nominally 1.0 and 1.7 Volts so that serial input data can be filtered up to 10%
of bit width on each transition to remove noise. This input is diode protected
from voltage overshoot above +5.9 Volts and undershoot below -0.9 Volts.
Input loading is four unit loads.
0tItpats: All outputs can drive ten unit loads unless otherwise specified.
Bita: 1 through 8: A read Buffer input signal will transfer the present shift
register contents to these outputs with a received logical 1 appearing as a
gr04.lftd output. If the Read Buffer input is not present, all outputs are at
logicat 1. When the M706 is used for reception of 5-bit character codes, the
ooput data will appear on output lines Bit 1 through 5 and bits 6, 7, 8 will
have received logical zeros.
AdBe..:{O): This output goes low at the beginning of the start bit of each
received character and returns high at the completion of reception of bit 8
for an 8-bit character or of bit 5 for a 5-bit character. Since this Signal uses
from ::ground to +3 Volts one-half bit time after the Flag output goes to
ground, ~t can be used to clear the flag through Clear Flag 2 input while the
Flag Output after being inverted can strobe parallel data out when connected
to Read Buffer.
104
1
\
-.-~-~--...
.....
+3
SERIAL
INPUT
START BIT 1 I BIT 2
o
+3
CLOCK
I I I I I I~
ACTIVE
11111111111111111111111: 111111:
J I: .
+3
(0)
+3
CLEAR
FLAG
U1
I
I
READER
+31 I
o
FLAG
+31 I
BEGINNING
OF
CHARACTER
I BIT
I
I BIT
I
5' BIT 6
I BIT
I
I
BIT 8
STOP' STOP
1 I 2
I
I
: : 111111: 111111111111
.:
- I
I
I
'"
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
o
(0
I BIT
I
I
Figure 1.
TYPICAL TIMING DIAGRAM

SeriallnputParaliel Output 8-Bit (01, 111, 111)2 Unit Stop Time
If an M706 and M707 are to be used in half duplex mode, this output should
be tied to the Wait input of the M707 to inhibit M707 transmission during
M706 reception. Output drive is eight unit loads.
Flag: This output falls from +3 Volts to ground when the serial character
data has been fully converted to parallel form. Relative to serial bit positions,
this time occurs during the center of either bit S or bit 5 depending respectively on the character length. If the M706 is receiving at a maximum character rate, i.e. one character immediately follows another; the parallel output
data is available for transfer from the time the Flag output falls to ground
until the beginning of a new start bit. This is Stop bit time plus one half bit
time.
Strobed Flag: This output is the NAND realization of the inverted Flag output
and Flag Strobe.
Reader (1): Whenever the internal reader flipflop is set by the Reader ON
input, this output rises to +3 Volts. It is cleared whenever a start bit of a
new character received on the serial input.
Reader Run: For use with Digital modified ASR33 and ASR35 teletypes which
have relay controlled paper tape readers. This output can drive a 20 ma at
+0.7 Volts load. The common end of the load can be returned to any
negative voltage not exceeding -20 Volts.
Pin AE2: This output is the logical realization of NOT (Clear Flag 1 or Clear
Flag 2 or I/O Clear) and is a +3 Volts to ground output level or pulse depending on the input. This signal can be used to pulse Reader On for control
of Reader Run as used in DEC POPS/I or POPSI L computers.
Pin BE2: This output is brought from +3 Volts to ground by an enabled
Clear Flag 1 input. It can be connected to Reader On for a different form of
control of Reader Run.
106
j
.
MISCELLA
NEOUS
M707
TELETYPE TRANSMITTER
M SERIES
. Length: Standard
Height: Double
Width: Single
fLAG STROBE I
Price:
$150
+-__-f
~________________~__~~~~~I~ED
FB;:..;;H2=-""~~________
~~F~' lF~~~~---------+----f
~EAR FlAG 2
-p-----------------'t---=BK2
=-t'O FLAG
I pB:;.,:F'2:......--1-------t--ct..__
PIN CONNECTIOf4S:
5 OR 8 BIT COOE
!91T-AKi TO AJI
BBIT-AK'TOAK2
BIT'
BIT 2
FOrb~~1\ TO BR2
BIT 3
BIT 4
SHIFT
REGISTER
BIT!!
1.5UNITS-EINZ TO BP'
2.0.\JNlTS-8N2 TO BN'
*=SEE TEXT
BIT 6
81T7
AH1
MUST BE
CONNECTED AL'
LOAD , AS1
IIUFl'ER
Volts
Power
mA (max.)
+5
375
GND
Pins
A2
C2. T1
107
The M707 Teletype Transmitter is a parallel-to-serial teletype code converter

self contained on a double height module. This module includes all of the
parallelto-serial conversion, buffering, gatirig, and timing (excluding only an
external clock) necessary tot ransfer information in an asynchronous manner
between a parallel binary device and a serial data line or teletype device.
Either a 5-bit or an 8-bit parallel character can be assembled into a 7.0,
7.5, or 8.0 unit serial character or a 10.0, 10.5, or 11.0 unit serial character
by the M707 through the use of different pin connections. on the module.
When conversion is complete, the necessary start bit and selected stop bits
(1.0, 1.5, or 2.0 units) have been added to the original parallel character
and transmitted over the serial line. The serial character is transmitted with
the start bit first, followed by bits 1 through 8 in that order, and completed
by the stop bits. Coincident with the stop bit being put on the serial line,
the Flag output goes low indicating that the previous character has been
transmitted and a new parallel character can be loaded into the M707. Transmission of this new character will not occur until the stop bits from the
previous character are completed. See the timing diagram of Figure 1 for
additional information.
In addition to the above listed features, the M707 includes the necessary
gating so that it can be used in a half-duplex system with the M706. Device
selector gating is also provided so that this module can be used on the
positive bus of either the POPS!I or the POPS! L. To obtain additional applications information on the M707 write for Applications Note ApM-013.
Inputs:
All inputs present one TIL unit load with the exception of the Clock
input which presents ten unit loads. Where the use of input pulses
is required, they must have width of 50 nsec or greater.
ClOck:
The clock frequency must be twice the serial output bit rate. This
input can be either pulses or a square wave.
Bits 1 through 8: A high level at these inputs is reflected as a logic 1 or mark

in the serial output. When a 5bit code is used, bit inputs 1 through 5 should
contain the parallel data, bit 6 should be considered as an Enable. and bits
7, S and Enable should be grounded.
Enable: This
multiplexing.
transmission
for scanning
+3 Volts.
input provides the control flexibility necessary for transmitter

When grounded during a Load Buffer pulse, this input prevents
of a character. It can be driven from the output of an MI61
purposes or in the case of a single transmitter, simply tied to
Wait: If this input is grounded prior to the stop bits of a transmitted character, it will hold transmission of a succeeding character until it is brought
to a high level. A ground on this line will not prevent a new character from
being loaded into the shift register. This line is normally connected to Active
(0) on a M706 in half duplex two wire systems. When not used, this nne
should be tied to +3 Volts.
Code Select Inputs: When a positive AND condition occurs at these inputs
the following signals can assume their normal control functions-Flag Strobe,
Load Buffer, and Clear Flag 1. Frequently these inputs might be used to
multiplex transmitter modules when signals like load Buffer are common
to many modules. These inputs can also be used for device selector inputs
when the M707 is used on the positive bus of the POPS/ I or POP81 L. The
108
code select inputs must be present at least 50 nsec prior to any of the three
signals that they enable. If it is desired to by-pass the code select inputs,
they can be left open and the Enable OS line tied to ground.
Clear Flag 1: A high leve. or positive pulse at this input while the code select
inputs are all high, will clear the Flag. When not used, this line should be
grounded. Propagation delay from input rise until the Flag is cleared at the
Flag output is -a maximum of 100 nsec. The Flag cannot be set if this input
is held at logic 1.
Clear Flag 2: A low level or negative pulse at this input will clear the Flag.
When not used this input should be tied to +3 Volts. The Flag will remain
cleared if this input is grounded. Propagation from input fall to Flag output
rise is a maximum of 80 nsec. If it is desired to clear the flag on a load
buffer pulse, Clear Flag 2 can be tied to pin ARI of the module.
Flag Strobe: If the Flag is set, and the code select inputs are all high, a
positive pulse at this input will generate a negative going pulse at the Strobed
Flag output. Propagation delay from the strobe to otJtput is a maximum of
30 nsec.
I/O Clear: A high level or positive pulse at this input clears the Flag, clears
the shift register and initializes the state of the control. This signal is not
necessary if the first serial character transmitted after power turn-on need
not be correct. When not used, or during transmission, this input should be
at ground.
Load Buffer: A high level or positive pulse at this input while the code select
inputs are all high will load the shift register buffer with the character to be
transmitted. If the Enable input is high when this input occurs, transmission
will begin as soon as the stop bits from the previous character are counted
out. If a level is used, it must be returned to ground within one bit time
(twice the period of the clock).
Ou~puts:
All outputs present TTL logiC levels except the serial output driv~r
which is an open collector PNP transistor with emitter returned to +5 Volts.
Serial Output: This open collector PNP transistor output can drive 20 mA into
any load returned to a voltage between +4 Volts and -15 Volts. A logical
output or mark is +5 Volts and a logical 0 or space is an open circuit. If
inductive loads are driven by this output, diode protection must be provided
by connecting the cathode of a high speed silicon diode to the output and
the diode anode to the coil supply voltage.
Une: This output can drive ten TTL unit loads and presents the serial output
signal with a logical 1 as +3 Volts and logical 0 as ground.
Active: During the time period from the occurrence of the serial start bit and
the beginning of the stop bits, this output is high. This signal is often used
in half duplex systems to obtain special control Signals. Output drive is eight
TTL unit loads.
'
109
Flag: This output falls from +3 Volts to ground at the beginning of the stop
bits driving a character transmission. The M707 can now be reloaded and
the Flag cleared (set to +3 Volts). This output can drive ten TTL unit loads.
Strobed Flag: This output is the NAND realization of the inverted Flag output
and Flag Strobe. Output drive is ten TTL unit loads.
+3 Volts: Pin BJ 1 can drive ten TTL unit loads at a +3 Volts level.
+5 Volts at 375 rnA. (max.)
Power:
Size: Standard, double height, single width FLIP CH IP module.

0:
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0-
MISCELLA
NEOUS
M906
CABLE TERMINATOR
. M SERIES
Length: Standard
Price:
Height: Single
Width: Single
$20
~----------------~------------------~+5V
14 St
*
*
*
*
*
*
*
*
14 H1
14 Jt
14 L1
*
*
*
*
14 P2
14 S2
*
*
*
*
14 T2
14 V2
+3
220
~-----+----~~----+5
*"EOUIVALENT CtRCUITEACH INPUT
GNO
Volts
Power
rnA (max.)
+5
440
GNO
Pins
A2
AI, CI, FI, KI, NI, RI, T1

C2. F2, J2, L2, N2, R2, U2
all signal lines grounded

all ground pins must be grounded
The MOO6 cable terminator module contains 18 load resistors which are
clamped to prevent excursions beyond +3 volts and ground. It may be used
in conjunction with M623 to provide cable driving ability similar to M66l
using fewer module slots.
APPLICATIONS
The M906 may be used to terminate inputs. In this configuration M906 and
Mll1 are a good combination.
This module is normally used with standard M Series levels of 0 and +3
volts to partially terminate lOO-ohm cable. It presents a load of 22.5 mA or
14 TIL unit loads at ground and, therefore, must be driven from at least an
Mll6-type circuit or, preferably, a cable driver.
111
GATES
MII03
TWO-INPUT AND GATES
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$14
~
At
Ct
1 8t
10
~.~
~
~ _S1rr
~
~
~
10
H1
Kt 10
1 J'
52
10
~
.'
Power
Volts
mA (max.)
+5
80
GND
Pins
A2
C2, T1
The MII03 contains ten 2-input AND gates. Unused inputs on any gate must
be returned to a source of logic HIGH for maximum noise immunity. Two
pins are provided (UI and VI) as a source of +3 volts for this purpose.
APPLICATIONS
Positive AND or negative OR gating
112
GATES
MI307
FOUR-INPUT AND GATES
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$12
AI
E2
BI
CI
F2
01
H2
I~
FI
HI
J1
M1
R2
NI
S2
PI
12
RI
U2
+3V
I
Volts
+5
GND
Power
mA (max.)
100
P200]
: ~::
Pins
A2
C2. T1
The M1307 contains six 4-input AND gates. Unused inputs on any gate must
be returned to a source of logic HIGH for maximum noise immunity. Two
pins are provided (UI and VI) as a source of +3 volts for this purpose.
APPLICATIONS
Positive AND or negative OR gating
113
MISCELLANEOUS
M7390
ASYNCHRONOUS TRANSCEIVER
M SERIES
Price:
Length: Extended
Height: Double
Width: Single
$275
L \NOTE 2)
ECHO
R04 L
R03 H
R03 L
RD2 H
RDI L
ROil H
R00 L
ROE L
OA
DADLY H
DADLY L
AUTO RESET
ROA L
P
OR
H
H
$WE L
NOTEs: *-TIED TO -1!lV WHEN M7390 USED TO DRIVE CURRENT LOOP
**-OPEN COLLECTOR OUTPuT

1. MUST 8E TIED TO GROUND IF RDA L NOT U6ED
2.MAY BE LEf"T OPEN '" ECHO NOT IlES'REO
Power
+10
700
3
Pins
BA2
AV2
-12
-15
80
80
BR2
BB2
Volts
+5
GND
mA (max.)
Bci
Requlres -12 V or -15 V only, not both.
114
H (HOTEl)
DESCRIPTION
The M7390 asynchronous transceiver is a modular subsystem which provides

asynchronous serial line compatibility for data communications applications.
The M7390 combines input/ output level converters, parallel-to-serial and
serial-to-parallel conversion, and a crystal controlled clock, into one module.
APPLICATIONS
The M7390 can be used for computer terminal applications, data entry devices or any system which requires asynchronous serial line compatibility.
The M7390 may also be used to drive modems conforming to EIA RS-232C
specifications or currentoperated devices such as Teletypes.
FUNCTIONS
There are three groups of functions on the M739O-error detectioA, data,
and control.
Error Detection: The error function of the module allows three types of
errors to be detected. These are:
1. Parity:
If the rece.ived parity bit does not agree with the expected
parity bit, the parity error flag is set.
2.
Overrun: The receiver section of the M7390 is fully double buffered.

Therefore, one full character time is allowed to remove the received data
from the receiver buffer before a new character is assembled and transferred. If the character is riot removed before a new one is loaded, the
overrun flag is set.
3.
Framing: Since the M7390 is asynchronous, the absence of a stop bit

can be detected. For example, an eight bit data character would have one
start bit, eight data bits, and one or two stop bits. Therefore, a stop bit
is expected as the 10th bit to be received. If the lOth bit is in the logic
TRUE (marking) condition no error is detected. However, if the 10th bit
is a log;c FALSE (spacing) condition, the framing error flag is set. The
framing error flag is useful for detecting open lines or null characters.
Data Functions: The M7390 performs serial-to'parallel and parallel-to-serial

conversion. The parallel side of the module is TTL compatible. The serial
inputs and outputs are available as three signal sources: EIA, current loop
o'r TTL. The current loop and EIA input and output are available only on the
eight-pifl MATE-N-LOK connector on the front of the module.
The EIA input corresponds to RS-232C specifications. In addition to the EIA
signals RECEIVED DATA and TRANSMITTED DATA, the DATA TERMINAL
READY signal and SIGNAL GROUND are also provided.
The current loop input! output is designed to operate on a 20 to 100 mA
current loop. The M7390 uses optical couplers to provide 1500 volts of
isolation between the M7390 ground and power and the driving source. The
serial input will respond to a 20 mA current flow. Current flow is a marking
condition (binary 1). The external source must not exceed 35 volts dc open
circuit voltage or 100 rnA current. The serial output is a transistor switch
that can turn a current loop on or off. The open circuit voltage of the current
source must not exceed 35 volts dc.
The TTL versions of the serial input and output signals are available on the
module pins and may be used in place of the level converter signals.
115
Control: The M7390 provides full control of the receiver and transmitter sections. All control pulses must be greater than 250 ns in width. Data to be
loaded into the module must be present ~50 ns before the DATA STROBE
pulse.
Receiver Control Signals:
DA
DA DLY
AUTO RESET
ROE
RDA
Data Available
Delayed Data Available
Allows DA to be automatically reset.
Receiver Data Enable. Places data and control
signals on the pins of the module.
Reset Data Available
Transmitter Control Signals:

TBMT
ECO
Transmitter Buffer Empty

End of Character
Error Control and other Signals:

NP
POE
SWE
CS
NBl, NB2
SB
XR
RESET
RCLK
TCLK
No Parity
Parity Odd or Even
Status Word Enable
Control Strobe
Number of Bits in data word
Number of Stop Bits (1 or 2)
External Reset (clears all registers) .
Negative pulse used for clearing module during
power-up.
Receiver Clock Input
Transmitter Clock Input
PRECAUTIONS
1.
EI'A and current loop connections are available on an a-pin 'MATE-N-LOK

connector located in the handle position on the B half of the board.
2.
Provision is made to power this module from either -15 or -12 volts
dc. Do not use both simultaneously.
3.
Current loop input and output circuits must not have more than 35 volts
peak applied or greater than 100 mA current flow.
4. The M7390 contains an MOS LSI chip. Care must be taken in proper
handling and grounding of the module to prevent damage to the MOS
chip.
5. The +10 volt dc supply is required only if the EIA level converters are
used, or if the module is gOing to be used as a current source.
6.
If the M7390 is used as a current source, 20 mA additional current must

be supplied by the -15 volt and the +10 volt power supplies.
116
SPECIFICATIONS
Data Format: Asynchronous, serial by bit, least significant bit first.

Input/Output Level (Serial):
= -3 to -25 volts dc
= +3 to +25 volts de
Current Loop: Mark (Binary 1) = 20 to 100 mA currem flow
Space (Binary 0) = <3 mA current flow
TTL: Binary 1 = HIGH
Binary 0 = LOW
1. EIA RS232C:. Binary 1

Binary 0
2.
3.
Data Rates: 110, 150, 300, 600, 1200, 2400, 4800 Baud.
Character Format: One start,S, 6, 7, 8 data, parity (if requested), one or
two stop bits.
Clock Frequencies (kHz): 1.76,2.4,4.8,9.6, 19.2,
38.4~
Input/Output Levels (Parallel): All TTL compatible.
MORE INFORMATION
Additional information is available by writing to:
Logic Products Applications Group
146 Main Street
Maynard, Mass. 01754
117
76.8
118
,
I
m~
modules f:or
computer
interf:acing
119
,
I
120
M SERIES MODULES FOR

COMPUTER
INTERFACING
Design and support of interfaces for the PDP computers is a growing function
of M Series logic. This edition of the logic Handbook emphasizes a cC)lIec~
tion of modules for interfacing to the PDP-8! e, 8/ m OMN IBUS or external
I/O bus, the PDP-ll UNIBUS, or the external I/O bus of earlier members of
the PDP-8 family. Using MSI and LSI technology, many of these designs provide complete interfaces on a single module.
OMNIBUS and UNIBUS INTERfACE MODULES

The OMNIBUS and UNIBUS are electrically compatible and, despite differences in computer architecture, the general sequence of I/O data transfers
is similar from the viewpoint of an external device. Interface modules therefore can be adapted, with a minimum oJ supporting interface logic, to operate with either computer bus. The M1502, for example, provides up to 16
bits of buffered output from either bus. For PDP-ll UNIBUS compatibility,
the M1502 is supplemented by an MI05 address selector and an M7820 Interrupt module. For PDP-8/e or 8/m, an M1500 Bus Gates module and the
M1510 Device Selector provide the necessary OMNIBUS control functions.
Other modules have been tailored specifically for one bus or the other. For
example, the M1702 provides buffering for 12 words of data input on a single
quad-height module that plugs directly into the OMNIBUS structure.
The M1702, like most OMNIBUS or UNIBUS intQrfacing modules, interconnects to external equipment through 40-pin flat cable connectors mounted on
the module itself. (See the description of the H854 and H856 connectors in
the CABLING section of this handbook.)
Modules available for interfacing to the UNIBUS or OMNIBUS are summarized
below. Others are in development. For an up-to-date listing, contact your local
DIGITAL Sales Office.
UNIBUS or OMNIBUS
M1500
MI50I
MI502
M162I
M1623
MI80I
Bidirectional Gates
Data Input
Data Output
DVM Data Ipput
Instrument Remote Control
16-Bit Relay Output
UNIBUS Only
MI05
M783
M784
M7~
M786
M7820
Address Selector
UNIBUS drivers (input)
UNIBUS receivers (output)
UNIBUS Transceiver
Device Interface
Interrupt Control
121
OMN IBUS Only

Bus Device Selector
12-Word Buffered Input
I-Word Input
M1510
M1702
M1703
Signals on the PDP-ll UNIBUS that are used for programmed and interrupt
I/O control are defined in Table l. For complete information on interfacing
to the UNIBUS, see Part II of PDP-ll PERIPHERALS AND IN"PERFACING
HANDBOOK, 1972.
Signals on the PDP-S/e, S/m, OMNIBUS that are used for programmed and
interrupt I/O control are defined in Table 2. For complete information on interfacing to the OMN IBUS, see Chapter 9 of the PDP-SI e and PDP-SI m
SMALL COMPUTER HANDBOOK, 1972.
OMNIBUS/UNIBUS Electrical Characteristics

The OMNIBUS and UNIBUS bus structures both e.J11ploy bidirectional data
and control lines plus a few unidirectional control signals. Each bus line is
a matched and terminated transmission line that must be received and
driven with devices designed for that specific application. (See Figure l.) All
M Series modules designed for interconnections to the OMNIBUS or UNIBUS
employ special line driver and line receiver circuits appropriate for such bus
lines. All drivers (identified by a ".0" in the logic symbol) are open-collector
gates that control the bus through a wired-OR connection. All receivers (identified by the "R" in the logic symbol) are high-impedance gates that present
a minimum of loading to the bus line.
;?)DIR~
Llt;___.
DRIVER
RECEIVER
LOGIC SYMBOI..S
3900 :t5% -
+5V
BUS
BUS
SIMPLIFIED SCHEMATIC
Figure l. Bidirectional Bus Circuits

122
Bus drivers and receivers may be connected to OMNIBUS or UNIBUS lines

without any concern for loading or drive capability. Often, however, a module
r may have unused circuits that can be used with TTL devices provided the
following loading rules are observed:
Receiver Loading: The bus receiver presents two unit loads to a TIL input.
Driver Sink Capability: The open-collector bus drivers are capable of sinking
50 mA, with a collector voltage of 0.8 volts or less. The collector voltage,
when not sinking current, must be less than +6 volts. Leakage current is
less than 25 mAo
Table 1.
UNIBUS 1/0 Signal Summary
SIGNAL
DEFINITION
A <17:00>*
Address lines. The 18 address lines are used by the master

device to select the slave (a unique memory or device register address) with which it will communicate.
Lines A <17:01> specify a unique 16-bit word. In byte operations, AOO specifies the byte being referenced.
Peripheral devices are normally assigned an address from
within the bus address allocations from 760000-777777
(program addresses, 160000-177777).
0<15:00>
nata Lines. The 16 data lines are used to transfer information between bus master and slave.
C <1:0>
Control .Lines. These two bus signals are coded by the master device to control the slave in one of four possible data
transfer operations.
CI
CO
Operation
0
0
0
1
0
1
DATI-Data In
DATIP-Data In, Pause
OAT~Data Out
DATOB-Data Out, Byte
1
1
MSYN
Master and Slave Synchronization. A control signal used by

the master to indicate to the slave that address and control
information is present.
SSYN
Slave Synchronization. The slave's response to the master

(usually a response to MSYN).
PA,PB
Parity Bit low (PA) and Parity Bit High (PB). These signals
are for devices on the UNIBUS that use parity checks. PB
is the parity of the high-order byte (that transferred on
o <15:08 and PA is the parity of the low-order byte
(0 <07:00.
BR <7:4>
Bus Request lines. These four bus signals are used by

peripheral devices to n:;quest control of the bus.
Angle brackets enclose groups of lines; A
<
17:00>
123
Al7 through AOO inclusive.
BG <7:4>
Bus Grant lines. These signals are the processor's response

to a bus request. They are asserted only at the end of instruction execution, and in accordance with the priority de- ,
term i nation.
NPR
Non-Processor Request. This signal is a bus request from a

peripheral device to the processor.
NPG
Non-Processor Grant. This signal is the processor's response

to an NPR. It occurs at the end of a bus cycle.
SACK
Selection Acknowledge. SACK is asserted by a bus-requesting

device that has received a bus grant. Bus control passes to
this device when the current bus master completes its operation.
INTR
Interrupt. This signal is asserted by the bus master to start

a program interrupt in the processor.
BBSY
Bus Busy. This signal is asserted by the master device to

indicate bus is being used.
INIT
Initialization. This signal is asserted by the processor wher1

the START key on the console is depressed, when a RESET
instructiQn is executed, or when the power fail sequence
occurs. INIT may also be used to clear and initialize peripheral devices by means of the RESET instruction.
AC LO
AC -line Low. This signal starts the power fail trap sequence,
and may also be used in peripheral devices to terminate
operations in preparation for power loss.
DC LO
DC line Low. This signal remains cleared as long as aI/ dc

voltages are within specified limits. If an out-of-voltage condition occurs, DC LO is asserted by the power supply.
124
Table 2.
OMNIBUS I/O Signal Summary
SIGNAL
-DEFINITION
MDO-ll
Provides lOT instruction code. Bits 3-8 contain the device

select code; bits 9-11 specify the operation select code.
I/O PAUSE L
Gates the device select and device operation codes into the
programmed I/O interface decoders and generates BUS
STROBE at TP3 and NOT LAST XFER H.
TP3H
TP3H clears the flag and clocks the output buffer of a programmed I/O interface.
INTERNAL
1/0 L
INTERNAL I/O is grounded by the device selector decoder.
DATAO-ll
The 12 DATA lines called DATA BUS serve as a bidirectional

bus for both input and output data between the AC register
in the processor and the interface buffer register.
Clines
CO, CI, C2
Signals CO, Cl, C2 control the data path within the processor
and determine if data is to be placed onto the DATA BUS or
received from the DATA BUS. They also develop control signals required to load either the AC register or the PC register.
SKIP L
An lOT checks the flag and causes the device logic to ground
the SKIP line if the flag is set.
INT RQSTL
tNT RQST is the method by which the device signals the

processor that it has data to be serviced.
BUS
STROBE L
BUS STROBE is used to load the AC and PC registers. Unless special I/O operations are being performed, the designer of an interface need not concern himself with BUS
STROBE.
NOT LAST
XFER L
A ground level on this line indicates to the processor that

the next BUS STROBE does not terminate the I/O transaction.
RUN L
When low, RUN indicates that the machine is executing instructions .
TSI L
TS2 L
TS3 L
TS4 L
TPI L
TP2 L
TP3 L
These time state lines are high if negated, and low if

asserted. Each time state precedes its corresponding time
pulse. Time states are always 200 ns or more in duration,
and change 50 ns after the leading edge of the time pulse.
These 100-ns positivegoing pulses originate in the timing
module. The exact spacing of the timing pulses is a function
of fast or slow cycle.
TP4 L
INITIALIZE H
IN ITIALIZE is a positive-going 600-ns pulse used to clear AC,

LINK, and flags in peripherals.
125
EXTERNAL I/O BUS (POSITIVE LOGIC)

The traditional input! output structure for the PDP-8 family computers is the
external 1/0 bus for programmed and interrupt-controlled data transfers_ The
positive-logic form of this bus, originally developed for the PDP-8! I and PDP81 L, is compatible with TTL logic. Many modules and peripheral controllers
developed for this bus structure are in demand and fully supported by DEC.
Positive-bus modules'and controllers can also be used with a PDP-8/e or 81m
that is equipped with a KA8-A Positive 110 Bus Interface option.
Earlier negative-logic versions of the PDP-8 family computers can be converted for use with positive-bus modules or options by the addition of a
DW08 negative-to-positive bus converter option.
M Series functional modules and' level converters for use with the positivelogic external I/O bus include:
MIOI
Bus Receivers (data output)
MI03
MI07
Device Selectors
MI08
Flags
M623
M624
Bus Drivers (data input)
M730
Bus Output Interface (positive logic output)
M73I
Bus Output Interface (negative logic output)
M732
Bus Input Interface (positive logic input)
M733
Bus Input Interface (negative logic input)
M734
3-Word Input Multiplexer
M735
InputlOutput Interface
M736
Priority Interrupt Control
M737
Bus Receiver Interface
M738
Counter-Buffer Interface
M907
Diode Clamping for Bus Lines
Signals of the external 110 bus are defined in Table 3. For a complete description of external bus Interfacing, see Chapter 10 of the PDP-Sf e and
PDP-SI m SMALL COMPUTER HANDBOOK, 1972.
126
Table 3.
External 1/0 Bus Signal Summary.
SIGNAL
DEFIN ITION
B Initialize
This line is asserted when the processor is initially

powered up or when the start key is depressed.
Usually performs housekeeping on all peripheral
devices-for example, resets all flip-flops on
power up.
ACOO-l1
These lines carry information from the peripheral

device to the accumulator. (Input)
8AC 00-11
These lines carry information from the accumulator to the peripheral devices. (Output)
BMB 00-11
These lines carry the device identifier code, a

unique address to which only one device will respond.
INTERRUPT REQUEST
This line is activated by the device flag and, when

asserted, causes the processor to JMS to location
o of memory field 0 and disables the interrupt
system. (Input)
BIOP 1
This line, when active, is ordinarily used to test

device flags. (Output)
SKIP
This line, when active during an lOP, will set the

Skip flip-flop in the processor.
BIOP 2
This line, when active, is ordinarily used to clear

the device flag and/or cause the device to operate. (Output)
CLEAR AC
This control line, when asserted, changes the

mode of I/O input transfer to a jam transfer.
(Input)
BIOP 4
When active, is ordinarily used to effect data

transfers to or from the peripheral devices. (Output)
B Run
When active, signals peripheral devices that the

processor is executing instructions. (Output)
8TS1 and 8T53
These lines are used to sync peripheral devices

to the processor. (Output)
127
NEGATIVE BUS
Some models of the PDP-8/1 and earlier models of the PDP-8 family employed an 1/ 0 bus structure that is logically identical to the positive-logic
external I/O bus except for the logic levels which are ground and -3 volts.
The following M Series functional modules simplify adapting negative-bus
computer I/O signals to controllers using positive TTL logic:
MIOO
Data Output from Negative Bus (pin compatible

with MIOI which does the same function for the
positive bus)
MI02
Device Selector (pin compatible with the MI03

positive-bus device selector)
M632
M633
Drives negative bus input lines
In addition, there is a wide assortment of level converters for two-way compatibility between the negative bus and M Series modules:
M051
M650
M652
M500
M502
M506
M507
Positive in, negative out
Negative in, positive out
For detailed electrical characteristics and timing on the negative 110 bus,
refer to a 1970 (or earlier) edition of the SMALL COMPUTER Handbook.
PDPl!5 Bus
The following modules were developed specifically for interfacing with the
PDP-15 I/O bus, but may be used in many other positive logic applications.
M510
Positive bus receiver
M622
Positive bus driver
M909
M910
Bus line terminators
128
LEVEL
MOS!
CONVERTERS
POSITIVE TO NEGATIVE
LOGIC LEVEL CONVERTER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$31
*
o
~
2
00-
*
*
*
* ~
*
o
o
o
~
~
*
*
*
o
o
o
~
2
fl- 20 MA.
~6V
Power
mA (max.)
47
-15
16
GND
~30V MAX.
+5
Volts
*. 50 MA.
MAX.
Pin
A2
C2
82
The M05! contains twelve level converters that can be used to shift M and
K Series logic levels to negative logic levels of ground and -3 volts.
APPLICATIONS
Interfacing to negative bus PDP computers
Interfacing to R/ B/W Series Logic Systems
Restrictions: Do not use for indicator drive or current sinking.

FUNCTIONS
A grounded input on the dri"er causes the output to be grounded.
SPECIFICATIONS
The output circuit consists of an open collector PNP transistor that can drive
20 mA to ground. -6 volts maximum may be applied to the output.
129
8-FAMILY
NEG. 1/0 BUS
MIOO
BUS DATA INTERFACE
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$50
*. 3MA AT -3V(WlTH Cl HIGH)

Volts
Power
mA (max.)
-15
10
+5
GND
60
Pin
A2
C2
82
The MIOO Bus Data Interface contains fifteen circuits for convenient recep
tion of data from the PDPS, PDPS/I 'negative voltage bus. It is pin compati
ble with the MI0l Positive Bus Data Interface.
130
APPLICATIONS
Output data transfer expansion for PDPS, PDPS/ I
FUNCTIONS
Each input line is connected to M Series levels and gated to the output by
the ENABLE signal. Each circuit has the following function:
INPUT.
ov
OV
-v
-V
ENABLE
L
H
L
OUTPUT
L
L
L
(l and H refer to standard M Series Levels of 0 and +3V. -V refers to nega- .

tive input. (See Threshold Switching Level.)
PRECAUTIONS
The enable line of the MI00 cannot be used as a strobe line. The output
signals are indeterminate for a period of 200 ns after the enabling line has
become true. The enable is intended to be controlled by the option select
output of the M 102.
SPECIFICATIONS
Input Loading: The loading presented to the negative voltage bus differs from
the loading using the standard bus modules (Le., RI07, RIll) in that the
data lines are loaded only if the device is selected.
Threshold Switching Level: -1.5 volts typo
Propagation Delay: 40 ns typo
131
8FAMILY
M10l
POS.I/OBUS
BUS DATA INTERFACE

M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$24
15 Ct
, V1
Volts
t~D
Power
mA (max.)
82
132
Pins
A2
C2. T1
The MI0l contains fifteen, two-input NAND gates arranged for convenient
data strobing from the POPS/I or POPSI L positive bus.
APPLICATIONS
POPS/I, P~P-Sf L Positive Bus Output Expansion
Can also be used as inverters or a data multiplexer
FUNCTIONS
Inputs are NAND gated to the output by the common ENABLE input (el).
SPECIFICATIONS
Inputs and outputs have standard M Series levels and propagation time. All
data inputs are protected from a negative voltage of more than -0.8 volts.
133
8-FAMILY
NEG. 1/0 BUS
MI02
DEVICE SELECTOR
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$60
ALTN OPTION SELECT
V2 6
lOP 1 N t:-P-=tZ_~
lOP 2 N ~R-=tZ_---t
=-_-I
lOP 4 N FS2
Kl
N HI
Nl
N- RECEIVER FOR POP-8.l8/1

NEGATIVE BUS (SEE Tt.XT)
Power
Volts
t~D
-15
mA (max.)
130
40
Pins
A2
C2, T1
82
The M102 is used to decode the six device address bits transmitted in com
plementary pairs on the negative BMB bus of the PDP8, PDP~8/1. The out
puts of the M102 are compatible with M Series TTL logic. The M102 is pin
compatible with the M103 Positive bus device selector with the exception of
the address inputs.
134
APPLICATIONS
Design of custom M Series interfaces for negative bus pop-a, PDP-a/I.
, FUNCTIONS
OPTION SELECT: The OPTION SELECT output is HIGH when all negative-bus
code inputs (PI-T2) are at ground. (Note: pop-a, pop-all BMB outputs are
asserted at ground.) The OPTION SELECT ENABLE input is an M Series level
that can override the code input.
lOP ENABLE: When the OPTION SELECT output is enabled, lOP pulses from
the computer are gated to output pins AI-Fl. Both LOW to HIGH and HIGH
to LOW pulse output polarities are provided.
Gated Inverters: Two single-input inverters are provided which function as
follows:
Neg. Input
(HI, U)
OV
OV
Gating
Input
Output
H
L
H
H
H
L
-v
-v
SPECIFICATIONS
Negative Input Levels: Negative inputs (-V) are nominally -3V and ground.
Threshold Switching Level is-I.5V typo
Negative Input Loading: BMB input loading is 1 rnA, shared among the inputs that are at ground.
lOP Input Loading: P2, R2, S2, HI and L1
0.2 rnA, when V in
0.0 rnA, when V in
Propagation Delay: 40 ns typo
135
= 0 volts
= -3 volts
8FAMILY
MI03
POS.I/OBUS
DEVICE SELECTOR
M SERIES
Length: Standard
Height: Single
Price:
Width:
$45
Single
~
~
Hl
KI,O
1 J,
t. U2
LI
ALTN
OPTION SELECT
Nt 10
1 Mt
lOP 2
lOP 3 12.'iI--la.------1
Volts
+5
GNO
Power
mA (max.)
110
Pins
A2
C2. T1
The MIG3 is used to decode the six device bits transmitted in complement
pafts-:..-w the positive bus of the POPS/I and POPS/ L Selection codes are
obtaiftedby selective wiring of the bus signals to the code select inputs 02,
E2, F2,ii2, J2, and K2. This module also includes pulse buffering gates for
the lOP signals found on the positive bus of the above computers. Two twoinput NANO gates are also provided for any additional buffering that is required.
136
APPLICATIONS
Special-purpose M Series Interfaces for positive bus PDP-Sf I, PDP-Sf L
FUNCTIONS
OPTION SELECT: The OPTION SELECT output is HIGH when all code inputs
(D2-N2) are HIGH. The OPTION SELECT ENABLE input is able to override
the code input.
.
lOP ENABLE: When the OPTION SELECT output is enabled, lOP pulses from
the computer are gated to output pins Al-Fl. Buffered and unbuffered outputs are provided (of opposite polarity).
Unused Inputs: Unused code inputs should be connected to a source of logic
HIGH. Inputs U2, L2, and N2 need not be tied to logic HIGH.
SPECIFICATIONS
Input Protection: All inputs which receive positive bus signals are protected
from negative voltage undershoot of more than O.8V.
137
PDPII
MI05
UNIBUS
ADDRESS SELECTOR
M SERIES
Length: Extended
Height: Single
Width: Single
Price:
$65
SSYN INHIBIT
BUS MSYN
BUS SSYN L
Jt 8
TEST POINT
\A,I
12
"
SELECT. H
S2
SELECT 2 H
U tO
SELECT 4 H
R2,0
SELECT6H
St '0
10
9
en
en
\A,I
8
7
Cl
5
4
[!] .. CONNECTS TO
Volts
+5
GND
Power
mA (max.)
338
UNIBUS
Pins
A2
C2. T1
The MI05 is used in PDP-ll device interfaces to control the flow of data
between the device registers and the UNIBUS. It provides gating signals for
up to four device registers that indicate a register is being referenced and
three control signals that indicate the path for data flow.
The selector decodes the 18-bit address A <17:00> as follows: A <17:13>
defines the memory "page" assigned to peripheral devices (external bank)
and must all be asserted. A <12:03> is determined by jumpers on the card.
138
When the jumper is "in" the selector will look for a zero on that address line.
A02 and AOI provide a coding array for the four SELECTED addresses. AOO
is for byte control.
Signals for gating control are determined by decoding AOO, CI, and
signals obtained are: IN, OUT LOW, and OUT HIGH.
IN
DATI
OUT LOW
OUT HIGH
co.
The
+ DATIP
= DATO + (DATOB AOO)

= DATO + (DATOB. AOO)
IN is used to gate data from a device register onto the bus. OUT LOW is
used to gate 0 <07:00> into the low byte of a device register. OUT HIGH
is used to gate 0 <15:08> into the high byte of a device register.
In relation to bus control, the MI05 is actually the "slave" in the relationship when data transfer occurs on the Unibus.
SSYN is asserted whenever it sees its address being referenced and MSYN
is asserted. SSYN is negated when MSYN is negated. There is an approximate
100 nsec. delay between receiving MSYN and the assertion of SSYN to allow
for decoding.
EXT GND is used for testing purposes and should be tied to
ground in normal operation.
SSYN INHIBIT can be left open when not used.
139
8.. FAMILY
POS.I/OBUS
MI07
DEVICE SELECTOR
M SERIES
length: Standard
Height: Double
Width: Single
Price:
$105
~
BF
BPI
CLA
=8AJS
I BV2
----+--I
IJ=AA:llt___
,A81
.., 'F~~'-------~
, An
I AU2
9ITIFM=2_ _ _ _ _ _ _ _~_a
R , AS2
Volts
IN IT , j.:=Ai&IL..._ _ _ _ _--I
+5
GND
140
Power
mA (max.)
110
Pins
A2
C2. Tl
The MI07 is a device selector which, by the use of extended decoding of the
BMB lines 9-through 11, will provide seven discrete lOT pulses. Five additional
lOT pulse outputs are provided to allow the user to reduce software requirements by the combining of lOT codes. The lOT instruction and the lOP times
at which the various lOT pulses occur at the module pins are outlined in the
following chart:
..
AT lOP TIME
Module
Pin
lOT
BH2
1-1
2-2
BM2
BJ2
3-1
BN2
3-2
4-4
BS2
X
X
X
X
BP2
BU2
5-1
5-4
6-2
6-4
Bl2
7-1
BR2
BV2
7-2
7-4
BK2
BT2
X
X
X
X
X
Example: If an IOP-7 is issued, lOT pulses will exist only at output pins Bl2
(7-1), BR2 (7-2) and BV2 (7-4). lOT pulses will not exist at any other
output pin.
The MI07 also contains two flag flip-flops which may be directly cleared or set.
The outputs of the flag flip-flops are connected to the skip and program interrupt lines. Interrogation of the flags is accomplished by lOT I -1 for flag
.
I and lOT 2 - 2 for flag 2.
The MI07 also provides two inputs to accomplish the "clear the accumulator"
function.
Outputs: Option Select Pin ADI can drive 13 TTL loads. Bus driver outputs
pins BPI, BSl, and BRI are open collector NPN transistors and can sink
30 mao at ground. The maximum voltage applied to these outputs must not
exceed +20 Volts and each output is diode protected against negative undershoot in excess of -0.9Volts.
141
MIOS
FLAG MODULE
Length: Standard
Height: Single
Width: Single
a-fAMILY
POS.I/OBUS
M SERIES
Price:
$45
02
ENABLE H
+3V
~------4
FLAG
~TH2FK~2.-___________~cj
___..l:L2~9
FLAG L
0
R
RESET L 1 ~J,","2. - - - - - - 0
TDTL,~H~2'-
~BUH
_ _ _ _r-_______________~
. ~E2~_____-r_____~________~
r-------t--t-.,...:.R2
=t 9 FLAG L
~TH2~~~------r---------~
RESET L 1 ~N;:.2""_ _ _ _+--Q
~STLIFM~_-_~---------------~
~Hn. :~F2~_ _ _ _~__- - - . - - -__----~
,...--_ _ _ _ _ _~-___..:.:V2~9 FLAG L

SET H 2
RESET
~T
r:u~a
_ _ _----If--_ _ _ _-I
L , .........- - - - - I f - - Q
,~----+--------------~
*-OPEN COLLECTORS: IOOMA,+20V MAX.
Volts
cr~D
Power
mA (max.)
137
142
Pins
A2
C2. T1
The MI08 contains three general-purpose clocked flip-flops for use in flag
applications in I/O interfaces, etc. Gating is provided so that the flags can be
individually set or gated to the program interrupt inputs of a positive-bus
PDP-8 computer.
APPLICATIONS
Device Ready logic in custom device interfaces for positive-bus PDP-8 computers
FUNCTIONS
CLEAR Inputs: Each flag flip-flop may be independently cleared or all flip-flops
may be cleared simultaneously.
Flag Outputs: The output of each flag flip-flop is gateable and is open collector ORed to the Program Interrupt bus.
The output of each flag flip-flop is passed through a gate and open collector
to the skip bus. This facility allows the user to test for a flag.
The 0 side of each flip-flop has been extended to module pins for peripheral
control.
SET Inputs: Each flip-flop may be independently set by the application of the
leading (positive going voltage) edge of a pulse or level to the clock inputs.
Disabling PI Feature: If use of the Program Interrupt feature is not desired,
the ENABLE inputs (02, E2, F2) must be connected to ground. If Program
Interrupt is desired, no connections to the ENABLE inputs are required.
SPECIFICATIONS
Pin Rl, (PI Function) and SI (Skip Function) are open collector NPN Transistors and will sink 100mA to ground. The voltage applied to these outputs
must not exceed +20 volts.
143
PDPlS
M500
BUS
NEGATIVE INPUT POSITIVE

OUTPUT RECEIVER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$55
j {>
bJ
(J j {>
OOD2 ..
-y
: H':
(J 1 {> : K':
j {> : M':
hJ
(::J 1 c{> : ::
CJ I c{> : =:
5'
:
1
:
b] c{>
~:
1
:
(J {>
OOH2 ..
[!] K2 ..
-y
-Y
Ft to
J1 t
[!] M2 ..
Lt 10
@P2 ..
OOR2
00 S2.
[!] Ul
0' :
Ct 10
Rt to
...
VItO
-v
* -1mA AT GROUND
Volts
+5
GND
-15
Power
mA (max.)
160
64
144
Pins
A2
C2, T1
82
The M500 module is used to convert negative input signals to positive

output signals. Each card contains e:ght converters and is pin compatible
with the POP-15 positive receiver card (M510).
FUNCTIONS
A ground input at 02 will yield a +3 at 01 and ground at Cl. Do not connect to pin E2 (used for manuf. test only).
SPECIFICATIONS
Propagation time (each circuit):
FROM
Input
TO
Output
145
ns (max.)
40
LEVEL
CONVERTERSi
M502
HIGH SPEED
NEGATIVE INPUT CONVERTER
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$26
tOO
*. EQUIV. Of 3 MA CL.'AMPED LDAO

Volts
+5
GND
-15
Power
mA (max.)
49
Pins
A2
92
B2
NOTE
CONNECT TO OUTPUT WHEN
C2, T1
NOT DRIVING 92l COAX.
Add 44 mA for each 100 ohm resistor connected to outputs.
~J
-l
t- 20ns TYPICAL. BETWEEN THRESHOLD
I--
';:
----I......
\~_
IJ
tr = Bns NOMINAL
~--
The M502 contains two non-inverting high-speed signal converters which interface standard negative (-3 volts and ground) logic levels or pulses with
M and K Series positive logic modules. These converters provide sufficient
current drive at a low output impedance for system interconnections by
means of terminated 92-ohm coaxial cable.
FUNCTIONS
Outputs: Each output can drive a terminated 92-ohm coaxial cable and
supply an additional 30 rnA at +3 volts or sink an additional 30 rnA at
ground ..
SPECIFICATIONS
The converters operate at frequencies up to 10 MHz with typical output rise
and fall times of 8 ns. Propagation times for output rise and fall are typically
20 ns.
Input loading is equivalent to a 3 IlJA clamped load ..

Output rise and fall times depend on the length of coaxial cable driven.
When coaxial cable is not driven, switching speeds are increased by connecting the 100-ohm resistor to the output.
146
...------M506
MEDIUM SPEED
NEGATIVE INPUT CONVERTER
LEVEL
CONVERTERS
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$52
*10mA AT GND,D10DE CLAMPED
Volts
Power
mA (max.)
81
Pins
A2
-15
ll5
82
t~D
147
C2. Tl
M~
The
contains six nO:lnverting signal converterS which can be used t o \
interface the negative logic levels or pulses of duration greater than 100 ns
to M and K Series positive logic levels of +3 volts and ground.
In addition to the negative level inputs, each converter circuit has three additional NOR inputs for positive logic levels of +3 volts and ground. A
source of logic HIGH for unused inputs is provided at each gate.
FUNCTIONS
(Pins A1, etc.)
IN
-3V
OV
OUT
OV
+3V
SPECIFICATIONS
These converters operate at frequencies up to 2 MHz with typical rise and
fall propagation times of 70 ns and 40 ns respectively.
All negative level inputs ,(AI, 02, ... R2) present a 10 rnA load at ground.
Caution: These inputs are diode-clamped to -3
volts; input voltages greater than -3 volts may
draw excessive current.
148
LEVEL
CONVERTERS
M507
MEDIUM SPEED
NEGATIVE BUS CONVERTER
M SERIES
Price:
Length: Standard
Height: Singte
Width: Single
$45
IEJE2
[!]H2
OOK2 ..
[!]M2 ..
..
02t!!j
F2~
0
0
U
D
J2~
..
L2~
N2~
+3
(E]P2 ..
+3
~S2
+3
R2~
*. 10 mA CLAMPED LDAD
**. SINKS 'OOmA TO GND; +20V MAX.

+5
Power
mA (max.)
42
-15
115
Volts
GND
Pins
A2
C2, T1
B2
The M507 contains six inverting level shifters which will accept -3V and
GND as inputs. The input to each level shifter consists of a 10 mA clamped
load and is diode protected against positive voltage excursions.
The output consists of an open collector NPN transistor. The output of each
level shifter will sink 100 mA to GND.
The output transistor is protected against negative voltage excursions by a
diode connected between the collector and GND. The output rise is delayed
by 100 ns for pulse spreading.
149
APPLICATIONS
The M507 is used to convert negative voltage logic levels or pulses .of duration greater than 100 ns to M Series levels (or pulses).
FUNCTIONS
INPUT
OUTPUT
GND
-3V
GND
+3V
SPECIFICATIONS
Input loading is equivalent to a 3 mA clamped load.

Each output can sink 100 rnA to GND. Maximum voltage applied to any
output is +20 volts.
150
PDpI5
BUS
M510
I/O BUS RECEIVER
Length: Standard
Height: Single
Width: Single
Price:
[>: :::
[>:
1 [>: ~::
1 [>: L':
1 [>:
[>: U2:
[>:
(>
~:
!>:
i>
~
~
1!1R2.
M SERIES
i>
i>
i>
i>
i>
i>
[>
[>
[>
[>
[>
$51
=:
MI to
::
::
T210
V2
OUTPUT
#2
*80MA Icr HIGHft.3V)
Volts
t~D
Power
mA (max.)
170
Pins
A2
C2. TI. F2
J2. L2, N2
The M510 is a positive input/output receiver card for use with the PDplS.
It contains 8 high impedance input circuits of at least 27K ohms and input
switching thresholds of about +1.5 V. Each receiver has two outputs, one
of the same polarity as the input, the other, the complement of the input.
The receiver card can be used anywhere on the PDPIS I/O Bus.
PRECAUTIONS
Do not connect to pin E2 (used for manuf. test only). Power (8+) must be
applied at all times since the input impedance drops to lK ohm when power
is off.
SPECIFICATIONS
Inputs: The input impedance is 27K ohms (min.). Each input load current
is 80 mA (max.) and the threshold switching level is 1.4 to 1.6 volts.
Outputs: Output no. 2 delay
= 50 ns (from input).
151
PDPIS
BUS
M622
EIGHTBIT POSITIVE INPUT/OUTPUT
BUS DRIVER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$45
:8' D
::: : D
:FI D
:.,,~ D
, :Ct :
1.3
H1
Kt :
..
D2[!]
..
E2~
H2@
..
KZ[!]
:LI1;M1 : D
:Nl :
:Rl :
:Ul :
,::P1
1. S1
1. VI
*. DRIVES PDP-15 POSITIVE BUS

Power
mA (max.)
210
Volts
+5
GND
.. M2[!]
D
D
D
P2~
..
SZ[KJ
.,
V2[!]
Pins
A2
C2. n. F2.
J2. L2. N2.
R2. U2
excluding output current
The M622 contains 8 two-input AND gate bus drivers for convenient driving
of the positive input bus of the PDP-15. The output consists of an open
collector NPN transistor.
M910 r - - - - ,
I
I
IL
+5V
I
I
I
oJ
6en.
____
- -
6eA
I
I
L
_ _ _ _ ...1
I
1ST
2ND
DEVICE
DEVICE
152
'M909
r -
I
I
I
Pull-up resistors of 68 ohms to +5.0 V (supplied on M910) must be tied to

the output and the last device should terminate all lines to ground with a
68-ohm resistor (supplied pn M909)_
PRECAUTIONS
Outputs: The maximum voltage applied to the output transistor must not
exceed +20 volts and the collector current must not exceed 100 rnA.
SPECIFICATIONS
Propagation Time: Typically 25 ns.
153
aFAMILY
POS.I/OBUS
M623
BUS DRIVER
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$40
*- SINKS tOOMA 10 GROUND,

Volts
t~o
+20V MAX.
Power
mA (max.)
71*
Pins
A2
C2. T1
UI. VI
does not include output current
The M623 contains 12 twoinput AND gate bus drivers for convenient driving
of the positive input bus of either the PDPS/I or PDPS! L. The output con
sists of an open collector NPN transistor.
APPLICATIONS
Driving PDpall or PDPSI L positive input bus

FUNCTIONS
A driver output will be at ground when both inputs are at ground.

SPECIFICATIONS
Output Drive: Each driver can sink 100 rnA at ground and can withstand
maximum output voltage of +20 volts.
Output Rise and Fall Times: Typically 30 ns when a 100 rnA resistive load
is connected to a driver output.
154
a-FAMILY
POS.I/O BUS
M624
BUS DRIVER
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$45
12 CI
*.SINKS 100mA 10 GNO; +20V MAX.

Volts
+5
GND
Power
mA (max.)
89
Pins
A2
C2, Tl
driver outputs not connected
The M624 contains 15 bus drivers intended for convenient driving of the
positive input bus of either the PDP-8/1 or PDP-SIlo Twelve of the drivers
have a common gate line for selecting data. There are three additional
drivers, two sharing a common gate line and the third without a gate line.
These three additional drivers were intended to accommodate the functions
of PROGRAM INTERRUPT, 10 SKIP and CLEAR AC.
Each output consists of an open collector NPN transistor.
155
APPLICATIONS
PDPSfl or PDpSf L positive input bus
driving
SPECIFICATIONS
All outputs can sink 100 mA to ground. Voltage applied to the output should
be equal to or less than +20 volts. Output rise and fall times are typically
30 ns when a 100 mA resistive load to +5 volts is connected to a driver
output.
156
I
I
I
M632
POSITIVE INPUT NEGATIVE OUTPUT
BUS DRIVER
*-FAMILY
NEp. 1/0 BUS

Price:
Length: Standard
Height: Single
Width: Single,
$55
~
~
D---D
~:::
oo
... P21!]
... S2[!]
.. V2[!)
*=SINKS 100mA AT GND
Volts
Power
mA (max.)
+5
175
-15
H2[!]
~
~
L.J U
GND
00
E2oo
.. K2
~::
02
Pins
A2
C2.
n.
F2. J2.
l2. N2. R2. U2,
40
82
excluding output current
157
The M632 contains eight two-input AND gate bus drivers for convenient
driving of the negative bus of the PDP-8/1 or PDP-Sf L.
FUNCTIONS
Each stage operates according to the following truth table:
INPUTS
LL
LH
HL
HH
OUTPUT
OV
-V
-V
-V
SPECIFICATIONS
Output Drive: The output is internally clamped to keep it between -3 volts
and ground. The output current must not exceed 100 mAo
Propagation Delay: 50 ns max.
158
M633
8FAMILY
NEG. 1/0 BUS
NEGATIVE BUS DRIVER
PrIce:
Lencth: Standard
Height: Single
Width: Single
$50
*. DRIVES
PDP-e, PDP-en
NEGATIVE BUS
Power
Volts
mA (max.)
+5
100
-15
40
GND
Pins
A2
C2. T1
82
The M633 contains 12 bus drivers intended for convenient driving of the
negative bus of the PDP-S, PDP-S/1. Each driver consists of an open collector
PNP transistor. It is pin-compatible with the M623 positive voltage bus
driver.
159
FUNCTIONS
Each stage operates according to the following truth table:

INPUTS
II
OUTPUT
lH
Hl
HH
OV
OV
OV
-V
SPECIFICATIONS:
Output Drive: Each output is an open collector PNP transistor capable of

supplying 20 mA from ground. Voltage applied to the output should not
exceed -6 volts.
Propagation Delay: Typically 40 ns .
160
LEVEL
CONVERTERS
M650
NEGATIVE OUTPUT CONVERTER
M SERIES
Price:
Length: Standard
Height: Single
Width: Single
$25
)~n
..
02
00
T.
SEE
TEXT
..
~T2
~::
b J----tf)
..
K2~
52
00
*=20 MA AT GND OR -3V
Volts
Power
mA (max.)
+5
37
-15
29
GND
Pins
A2
C2, T1
82
The M650 contains three non inverting signal converters which can be used
to interface the positive logic levels or pulses (of duration greater than
100 ns) of K and M Series to digital negative logic levels of -3 volts and
ground. These converters provide current drive at a low output impedance
so that unterminated cables or wires can be driven with a minimum of
ringing and reflections.
FUNCTIONS
A positive AND condition at the input gate produces a ground output. If any
input is at ground, the converter output is at -3 volts.
SPECIFICATIONS
The converters operate at frequencies up to 2 MHz with maximum rise and
fall total transition of respectively 75 ns and 115 ns. By grounding pin E2
(l2 or R2) the rise and fall total transition times can be increased to avoid
ringing on exceptionally long lines. The converter then operates at frequencies up to 500 kHz with typical rise and fall total transition times of 500 ns.
Each output is capable of driving 20 rnA at ground and at -3 volts.
161
LEVEL
CONVERTERS
M652
NEGATIVE OUTPUT CONVERTER
M SERIES
Price:
Length: Standard
HelJht: Single
Width: Single
$26
~TE
N01'E2
NOTES:
t. CONNECT TO OUTPUT WHEN NOT
DRIVING 92 (1 COAX.
n.
2. CONNECT TO GROUND PIN FOR

500
INPUT
RISE TIME
+3V~:
.
IV
OUTPUT ""
\~-
'.
t- 20ns TYPICAL. BETWEEN THRESHOLDS
1:
-3V:
{I
-t t-
Volts
ct~D
-15
t, 8ns NOMINAL
"---~ WITH PIN H2(N2) GROUNDED
Power
mA (max.)
122
Pins
A2
e2, M2
82
202
The M652 contains two noninverting high-speed signal converters which can
be used to interface the positive logic levels or purses of the K and M Series
to digital negative logic levels of -3 volts and ground. These converters
provide current drive at a low output impedance so that system interconnections can be made using terminated 92-ohm coaxial cable.
FUNCTIONS
Each section:
INPUT
l
H
OUTPUT
-3V
OV
162
SPECIFICATIONS
Timing: The converters operate at frequencies up to 10 MHz with typical
output rise and fall times of 8 "s. Propagation times for output rise and fall
are typically 20 ns. The slope of the output transition can be decreased by
grounding an internal RC network, to avoid ringing on exceptionally long
lines. The converter then operates at frequencies up to 1 MHz.
Inputs: Positive logic levels of a and +3 volts (nominal). Input signals more
positive than +6 volts will damage the circuit.
Outputs: Each output can drive terminated 92-ohm coaxial
an additional 20 mA at ground or sink an additional 20
Output rise and fall times are dependent on the length
driven. When coaxial cable is not driven, switching speeds
by connecting the lOa-ohm resistor to the output.
163
cable and supply

rnA at -3 volts.
of coaxial cable
will be increased
8FAMILY
M730 & M731
POS.I/OBUS
BUS INTERFACES
M SERIES
Length: Standard
Height: Double
Width: Single
Price:
M730-$160
M731-$160
Volts
Power
mA (max.)
+5
400
-15
90
GND
Pins
AA2. BA2
AC2. ATl. BC2. BTl
AB2. BB2
M731 only
LEVEL
CONVERTERS
BMB AND lOP SIGNALS

FROM COMPUTER
BAC
SIGNALS
FROM
COMPUTER
12-BIT
STORAGE
REGISTER
FLAG
CONTROL
DEVICE
SELECTOR
FLAG CONTROl:
SIGNALS
TO COMPUTER
TIMING
GENERATOR
(INCLUDING
LEVEL
CONVERTERS)
LEVEL
CONVERTERS
12 DATA LEVELS
TO INTERFACE
DEVICE
The M730 and M731 interface modules provide extremely flexible interface
control logic to connect devices, systems, and instruments to the output half
of the programmed I/O transfer bus of either a POPS/! or a POPS/l positive
bus computer. Peripheral equipment which operates either asynchronously
or synchronously to a computer and expects to receive data from that computer, can to a large degree be interfaced by either the M730 or M731. Basic
restrictions on the device or system to be interfaced are simply that it receive
data in parallel, provide one or more control lines. and operate at a data
transfer rate of less than 20 KHz. Complete interfaces to such peripheral
gear as card punches and other repetitive devices is possible using the M730
and M731; however part of the controlling functions, such as counting etc.
must be performed by computer software.
164
_5
_6
8MB 3
fil!-----+-I__
8MB 4
&MBr
8MB 8
~~~~~~---~
C~LXK-'>----~---~--r-----------------r--~
BAC.
BACZ
BAC3
BAC4
BACe
P'------t----f ..O"
TYPE
D------f
r=--t----I~lZ;~i~
OUTPUT
DFI.VEFIS
1---------+---"""1
1-------------------j1--;...,,9
BACS
BAC7
r-----------------i~~B~*~~7
BAC9 P 1"""'5._-+----1
1-----------------j-.-,-"'8I'l.""1* OATA 9
t-----------------Ir-...,.BU2=j* ~lA'O
Z II ~TAtI
1---------------t-.-,-"'9
1------------------r~~~8
~10 P rA~Ul'""_-+--_-I
BAC'I~
NOTE:
*. CAN S.NK 30mA
AT GI!OUNO
BUS INTERFACE -
M730 (POSITIVE OUTPUT)
165
IOP1 !Tlt...._-+---~
lOP 2
5MB3 rn:~-H
__
8MB 4
8M85
8MlI6
SM87
5MB8
!lACe
!lAC!
BACt
BAC3
BAC4
OUTPUT
DRIVERS
BACS
BIIC6
BAC7
&ACe
NOTE:
*. CIIN
SINK 30mA AT GROOND
BUS INTERFACE -
M731 (NEGATIVE OUTPUT)
166
Functionally, these modules contain five distinct sections which are as follows:
1. Device Selector-Th is logic n~twork converts the buffered memory buffer
(8MB) signals and lOP timing pulses from the computer into internal
module control pulses.
2. Timing Generator-Through the use of device selector signals, control
signals from the interfaced device, and module jumpers, this unit can
supply variable width pulses or synchronous control levels at amplitudes
specified in section 5 below.
3. Storage Register~This 12bit flip.flop buffer register provides output data
storage for information to be transmitted to the interfaced device.
4. Flag Control-Provisions for generation of I/O Skip and Program Interrupt
signals for the computer are made in this area.
5.
level Converters-All level converters from the storage register or timing

generator are open--collector transistor types which can drive 30 ma
at ground. The M730 has npn drivers and can interface loads returned
to a maximum positive supply of +20 Volts and the M731 has pnp
drivers which can interface loads returned to a maximum negative supply
of -20 Volts. level converters which input control signals to the Flag
control can receive signals of the same polarity and magnitude as the
output drivers can sustain.
Thresholds on the input converters are +1.5 Volts and -1.5 Volts for the
M730 and M731 respectively. All positive voltage levels are compatible with
K and M series and all negative voltage signals are compatible with R, 8 and
W Series.
For additional information, technical specifications and applications assist
ance, a Digital module specialist can be contacted at any Digital Sales office.
Application Note ApM-017 contains useful information concerning the use
of the M730 and M731.
167
8FAMILY
POS.I/OBUS
M732 & M733
BUS INTERFACES
M SERIES
Length: Standard
Height: Double
Width: Single
Price:
M732-$160
M733-$165
Volts
Power
mA (max.)
+5
400
-15
125
GND
Pins
AA2. BA2
AC2. ATl. BC2. BTl
AB2. BB2
M733 only
FLAG
CONTROL
LEVEL
CONVERTERS
BMB AND lOP SIGNALS

FROM COMPUTER
DATA
SIGNALS
FROM
INTERFACE
DEVICE
DEVICE
SELECTOR
LEVEL
CONVERTERS
FLAG CONTROL.:
SIGNALS
TO COMPUTER
TIMING
GENERATOR
(INCLUDING
LEVEL
CONVERTERS)
TIMING
SIGNALS
TO
INTERFACE
DEVICE
12-BIT
STORAGE
REGISTER
The M732 and M733 inte(face modules provide extremely flexible interface
control logic to connect devices, systems, ~nd instruments to the input half
of the programmed I/O transfer bus of either a positive bus POPS! I or
POPS! L computer. Peripheral equipment which operates either asynchronously or synchronously to a computer and expects to transmit data to that
computer, can to a large degree be interfaced by either the M732 or M733.
Basic restrictions on the device or system to be interfaced are simply that it
transmit data in parallel, provide one or more control lines, and operate at
a data transfer rate of less than 20KHZ. Complete interfaces to such peripheral gear as card readers and other repetitive devices is possible using the
M732 and M733; however, part of the controlling functions such as counting,
etc., must be performed by computer software.
168
DONE ,-
ITJ!!!L-
-r~
F\~
~"
'"'"'"--
DONE 1+ ~
DONE 2-
~
~
VH
r~ S I f - - -
fu:P~~
r~
L-
'---
Of-'--
O L e
DONE 2+
SELECf
INITIAlIZE
ENA8lE
lOP'
lOP 2
D!!&--
V
o
II
SKIP'
BAlli
H
L
r----
GJAlZ
fil ...1
,;~
BPI II
~
_9111 ~"'AI
DEVICE
SELECTOR
lOP 4
_3 WS'
_4
~~
_7 ~
...,m ~I
l:!:~-
81111111(1}
BVI-=!
........
_5 IT~
I---'
_6
~
811181
ss,
IIIli!II
PULSE'-
~II PULSE'+
"'-
~OF
IIF2I1
t...../I/.
L--
DolT....
DAT"'I
DAT... Z
DoIOlI3
DolT... 4
DAlJI5
DAT"'I!
'1'_
r----
~8J2
~8K2
=i={BL2
~"'-
DAT... .
DAT...tO
OAT... "
IIAI~,AC.
~~,AC'
et,~,AC2
eo ~,At3
r.;~8N2
l..
INPUT
0," TYPE
fDM"ill'
AEGlsID
lEVEL
T18P2
STORAGE
DAlJI7 ml!ll2
OAT... a
II PU.SE2+
-.II[l~.AC4
Sfl P At5
...!!!!!p AC8
II.J' P AC7
m.
ifi:ST2
,8S2
~'P
Ace
~:
ACt
,1N2
"--
NOTE:
----
II-CAN SIN< 30tnA AT GROUND
BUS INTERFACE -
M732 (POSITIVE INPUT)
169
AClO
P ACI'
CLK
DATA.
DATAl
DATAZ
DATA 3
DATA4
0ATA7
DATAl
NOTE: It-CAN _
30nIA AT GROU'l
BUS INTERFACE -
M733 (NEGATIVE INPUT)
170
Functionally, these modules contain five distinct sections which are as

follows:
1. Device Selector-This logic network converts the buffered memory buffer
(BMB) signals and lOP timing pulses from the computer into internal
module control pulses.
2. Timing Generator-Through the use of device selector signals, control
signals from the interfaced device, and module jumpers, this unit can
supply variable width pulses or synchronous control levels at amplitudes
specified in section 5 below.
3.
Storage Register-This 12bit flip-flop buffer register provides input data

storage of information received from the interfaced device. Information
is loaded into this register by a control line from the peripheral.
4.
Flag Control-Provisions for generation of I/O Skip and Program Interrupt signals for the computer are made in this area.
5.
level Converters~AII level converters from the timing generator are open
collector transistor types which can drive 30 mA at ground. The M732 has
npn drivers and can interface loads returned to a maximum positive supply of +20 Volts and the M733 has pnp drivers which can interface to a
maximum negative supply of -20 Volts. level converters which input
control and data signals to these modules can receive signals of the same
polarity and magnitude as the output drivers can sustain. Thresholds on
the input converters are +1.5 Volts and -1.5 Volts for the M732 and
M733 respectively.
All positive voltage levels are compatible with K and M Series and all
voltage signals are compatible with R, B, and W Series.
For additional information, technical speCifications and applications assistance, a Digital module speCialist can be contacted at any Digital Sales Office.
Application Note ApM-018 contains useful information concerning the use of
the M732 and M733.
171
8FAMllY
POS.I/OBUS
M734
I/O BUS INPUT MULTIPLEXER
M SERIES
Length: Standard
Height:.w Double
Width: Single
Volts
+5
GND
Power
mA (max.)
325
Price:
Pins
AA2, BA2
AC2, ATl, BC2, BTl
~105
r-------~----------------------_+~M~I~t8 l~t
lOP I
lOP2
r-------t--+--------------------I-.,..!A8~I t8 IOT2
r---...,....-t--t---------------------I-.....:A~Cl 18 IOT4
IOP4
AOO
ACI
A02
A03
A04
AC5
ACS
A09
AtO
All
80t
802
803
B04
B05
BUS
!lRIVERS
B06
B07
808
809
Bl0
811
COO
COl
CO2
C03
C04
005
COS
C07
C08
C09
CIO
CII
172
The M734 is a three-word multiplexer used for strobing 12-bit words on a

positive voltage input bus, usually the input of the PDP-S/I or the PDP-S/l.
Device selector gating is provided. The data outputs of the M734 Multiplexer
consist of open collector NPN transistors which allow these outputs to be
directly connected to the bus.
FUNCTIONS
Code Select Inputs: When a positive AND condition occurs at these inputs,
the pulse inputs 10PI, IOP2, and IOP4 are enabled for use in strobing input
data. The code select inputs must be present at least 50 ns prior to any of
the three signals that they enable. If all select inputs are not required, unused inputs must be tied to a source of +3 volts (pin AL2). These inputs are
all clamped so that no input can go more negative than -0.9 volts.
IOPI, 2, 4: These 50 ns (or longer) positive pulse inputs strobe 12bit words
A, B, and C to the bus driver. All three lines are clamped so that no pulse
input can go more negative than -0.9 volts.
Data Inputs: Bits 0-11 on words A, B, and C are strobed 12 bits at a time.
Bus driver output lines (0-11) correspond to the selected word input lines
(0-11). A HIGH data input forces a bus driver output to ground during a data
strobe. Data signals must be present at least 30 ns prior to issuance of 10.P
1,2,or4.
Bus Driver: These open collector NPN transistor bus driver outputs can sink
100 rnA at ground. Each ~driver output is protected from negative undershoot
by a diode clamp. When this module is used with the PDP-S/I or PDP-S/L,
these outputs would be connected to the accumulator input lines of the I/O
bus. Typical rise and fall times at these outputs with a 100 rnA resistive load
are 100 ns.
Data Strobes: Pins AAI, AB1, and ACl appear coincident with IOPl, IOP2,
and IOP4 respectively only if the code select inputs are all HIGH.
+3 Volts--Pin AL2: Can hold 19 inputs at a logic HIGH level.
PRECAUTIONS
Bus driver maximum output voltage must not exceed +20 volts.
173
8FAMILY
POS.I/OBUS
M735
1/0 BUS TRANSFER REGISTER

M SERIES
Price:
Lenlth: Standard
Heilht: Double
Width: Sinlle
$135
(' ~,
, AEZ
CODE
SELECT
1 AF2
f
AHZ
1 AJZ
1 AK2
t-'\r--
lOP 1 2 AM2
lOP 2 1 AN2
lOP 4
1 AP2
IIM89( 1)
1 AAI
BM89C1O
1 ASI
JOTXYI
IMI ,O (TO SKIP GATES)
8S1 I
,OTXY2.1
3.,,1
DEVICE
SELECTOR
IUS
IOTXY 4.5,6,7
--r-
I BJ2
SAl. ACO
881. ACI
I 111<2
8CI
AC2
I Bl2
801
*.
AC3
ENAeLE
111M2
1 SP2
1 8A2
1 SS2
.1"
, 812
J'O
BUS
ORIVE"5
, 8U2
LillBV2
~"BtEt--+
AC o P AFI
fit:. I p AHI
AC 2 P AJI
AC 3 P AKI
AC4 pAll
AC5 P AMI
INPUT
GATES
NI
P
AC T P API
AC6
AC9
ACIO
8M.
ACII
AD110
AEllO
AA2110
AS2 0
AT2
"0' TYPE
10
AUZ,=
STORAGE
t - - - REGISTER
AV2~
eo2~
8E2;1O
81' 2 10
--:r-
I AL2
8M1
ACtO P AU'
ACt I P AVI
8L1
r----
AC8 pARI
AC9 P ASI
FI=
* AC'I
8FI * AC5
AC6
P-- -~
~JI
ACT
I!KI * AC8
8EI
I 8H2
OATA
* (AC CLEAR)
r-'
I BH2
INPUTS
BM
Ell110
BVIIO
NOTE:
.-CAN SINK 100mA TO GROUND
Volts
+5
GND
Power
mA (max.)
425
Pins
AA2. BA2
AC2, ATl, BC2. BTl
174
OATA
OUTPUTS
The M735 provides one 12-bit Input bus driver and one 12-bit output buffer
register for input .and output data transfers on the positive II o bus of either
a POPSII or a POPSI L. Device selector gating plus additional signal lines provide the flexibility necessary for a complete interface with the exception of
flag sense signals. Use of the M735 is not restricted to a computer, as it can
be used in many systems to provide reception and transmission of data over
cables.
Inputs:
All inputs present one TTL unit load with few exceptions as noted in the
functional descriptions below:
Code Select Inputs: When a positive AND condition occurs at these inputs,
the pulse input gates for IOPI, IOP2, and IOP4 are enabled for use as detailed below. The code select inputs must be present at least 50 nsec prior
to any of the three signals that they enable. If all select inputs are not required, unused inputs must be tied to a source of +3 Volts. These inputs are
all clamped so that no input can go more negative than -0.9 Volts. When this
module is used with the POPS/lor PDPS/l these inputs would be connected
to BMB outputs 3-8 to generate a device code. Where required in discussions
below, this 6-bit device code will be referred to as code XV.
-
10Pl, 2, 4, BMB9(1) and BMBI0(1): These three lOP's 50 nsec or longer

positive pulse inputs, in conjunction with control level inputs BMB9(1) (Pin
AA) and BMBI0(1) (Pin ABl) provide all of the necessary signals for opera
tion of this module. Table 1 below indicates the recommended use of these
pulses and levels. A"l" or "0" in this table indicates the presence or
absence respectively of a pulse (an lOP) or the logic level at pins AAI or AB!.
Module
Operation
lOP lOP lOP BMB BMB

PDP/8
1 9(1) 10(1) Mnemonic
4
2
0
IOTXY I
+3V -+ OV output pulse on pin BRI

used for skip function.
IOTXY2
+3V -+- OV output pulse on pin

BSl, bus driver output on BPI
pulsed to ground and is used for the
AC clear function.
IOTXY3
load output register from accumulator outputs on IOPl execute

IOTXY2.
IOTXY4
Data inputs strobed onto accumulator inputs.
IOTXY5
Load output register on IOPI, Execute IOTXY4.
IOTXY6
Execute IOTXY2, and IOTXY4.
IOTXY7
Execute IOTXY3, and IOTXY4.

175
The M735 module operation as associated with the various mnemonic lOT
codes is quite explicit with the exception of IOTXY5. This code (lOTXY5)
would be used to load zeros into the M735 with IOTXYl and then to load
into the AC the data present at the data inputs of the bus driver when
IOTXY4 occurs. In this particular operation the AC has been effectively
cleared as the content of the AC was zero during IOTXY1 thereby allowing
the transfer of data into the AC without the use of the AC clear command
usually generated by IOT2.
Although it is not implicit from Table 1, BMB9(1) and BMBIO(l) inputs are
gated in a positive OR Circuit, so that when the M735 is not used on a
PDPS/I or POPS/ L I/O bus one of these inputs can be grounded and the
other used for control. They must appear at least 50 nsec prior to an lOP
pulse. If the M735 is used with one of the above computers, these inputs
must be tied to the corresponding I/O bus lines. The input load on 10Pl is
two TIL unit loads. All five inputs are clamped so that no input can go more
negative than -0.9Volts.
Data Inputs: Each data input when at ground, enables the corresponding bus
driver output to be pulsed to ground during IOTXY4. A high input will inhibit
the bus driver from being strobed. Since each input is ANOed with IOTXY4,
any change of data after this strobe begins will change the bus driver output.
Accumulator Inputs: The input level presented to these inputs will be the
same as that assumed by the buffer outputs after executing inputs strobes
10TXY, 5, or 7. Input data must be present at least 50 nsec prior to an lOP.
Each input Is protected from negative undershoot by a diode clamp.
Reset Register Pin AL2: A positive pulse of 50 nsec or longer at this input
sets all buffer outputs to ground. When high, this input overrides any data
loading from the accumulator inputs. The output register will be cleared
within 70 nsec from the rising edge of this input. Diode input clamping is
provided to limit negative undershoot to -0.9 Volts.
Outputs:
Pin BRI: This output can drive ten TIL unit loads and has a propogation delay of less than 20 nsec. See Table 1.
Bus Driver: These open collector npn transistor bus driver outputs, including
.pin BPI, can sink 100 rna. at ground. The maximum output voltage cannot
exceed +20 Volts and each driver output is protected from negative undershoot by a diode clamp. When this module is used with the POPS/lor
PDPS/l, output pins BAl-BNl would be connected to the accumulator input
lines and pin BPI to the clear accumulator Ii.ne of the 1/0 bus. Typical rise
and fall Tn of these outputs with a 100 rnA. resistive load are 100 nsec.
Buffer Outputs: Each output can drive ten TIL unit loads.
176
8-FAMILY
POS.r/OBUS
M736
PRIORITY INTERRUPT MODULE
Length: Standard
Height: Double
Width: Single
M SERIES
Price:
Power
Volts
+5
GND
mA (max.)
Pins
A2
400
$125
C2, T1
HARl)-WIflED
ADORESSES
AC6
ACT
meel
'reEl
r---
Ace [Tl!IFI
AC9 --; AP2
NON-
PRIORITY
[ AClO 1 AJI
ACII I AH2
lieS
I &AI
AC7 I AS2
I AL2
ACe
AC9 I AMI
PRIORITY
4
[
ACIO I AOI
ACII I ACt
AC7 I AR2
I AM2
Ace
AC9 I ALI
PRIORITY ~
---------------
AV2
AC6 t AT2
PRIORITY
ADDRESS
GATES
AC INPUT
BUS GATE
r---
[ ACtO I AEt
ACtt t ASI
P AC6
A~p
AK2 P
ACT
AC8~
AD2p AC9
AJ2 ,; ACIO
AE2 P ACtI
b.IOTt
AC6 t AU2
AC7 I ASI
AHt
Ace
AK1
AC9
PRIORITY
2
ACIO I AFt
r--
ACI I I AAI
1-4-
AC6 r,t8DI
~88t
~APt
ACe
r-r--
ACT
PRIORITY
I
AC9
~ARt
ACI I I AF2
PRIORITY I I BJ2
PRIORITY 2 t 8Ht
8Ft
f'RIORITY 3 ,
PRIORIlV4 I SKI
PRIORITY ENABLE I BEt
INITIALIZE
8TS-3
I 8L2
I BlI
802
PRIORITY
10 ENABLE OUT
r------
ACIO ~AHt
PRIORITY
ADDRESS
SELECTION
GATE
"--~r-----
PRIORITY
fLI~~
~~'.
ENABLE I 81'12
t 8T2
I BSI
t BRI
DEVICE
SELECTION
BPI
DEVICE
SELECTOR
IIOT2)
I BNI
I BJI
lOP 2
lOP 4
BM2
, 8HZ
CLA
BR2 7 SELECT
I 8S1
lOP I
But P
L...---
177
The M736 is used in conjunction with the PDPS/' or B/l. to provide the
capability of assigning priorities to various I/O devices connected to the 1/0
bus of the computer. The M736 can be used to assign priorities for one thru
four external devices. Priority assignment may be provided for more than four
devices by using additional M736 modules for each additional group of
four devices. All M736's in a particular priority system would utilize the same
device code.
THEORY OF OPERATION
Basically the M736 module consists of the following:
1. The Ml03 device selector function.
2. A Bit Time State-3 (BTS-3) input.
3. Four priority input lines.
4. Priority enable line, input and output.
5. Five groups of six gates, each of which is capable of being hard wired to
provide address information to locate subroutings to service the various
devices associated with the priority interrupt system. The output of each
of these gates is strobed onto the accumulator input bus on lines AC(6)
thru AC(l1).
SEQUENCE OF OPERATION
. The external device activates its skip andlor interrupt FLAG flipflop. The
activation of the FLAG causes two things to happen; (a) The computer's interrupt request line ;s pulled to ground. This tells the computer that an external devices requires service and requests the computer to jump to an I/O
priority interrupt service subroutine as soon as the computer completes its
present cycle. (b) The external device FLAG pulls to ground the appropriate
hard wired priority line connected to a "0" flip-flop in the M736.
A Bit Time State-3 (8TS-3) pulse from the computer is applied to the clock
input of the "0" flip-flop to which the activating device flag is connected, as
mentioned in section Ib above, and causes this flip-flop in the M736 to set.
If more than one priority devices called to be serviced at the same time, all of
the associated priority "0" flip-flops in the. M736 would be set at this time.
The outputs of the prio'rity flip-flops in the M736 are connected to a priority
gate structure which is arranged in such a manner that only one output line
will be activated and that line will be associated with the external device with
the highest priority.
This activated output of the priority gate structure is applied to one group of
six two-input gates which make up the address gate. The other input of each
of the six two-input gates of the address gate is hard wired to provide a discrete address which will correspond to the startilJg lo~ation of the particular
subroutine associated with that priority request. Each of the six output lines
of the activated address gates is applied to one input of a two-input gate of
the AC input strobe gate.
178
The computer now has had time to jump

routine and now issues a device selection
wired device selection code assigned to the
This device selection code will preenable
M736's.
to the priority interrupt service

code corresponding to the hard
M736 priority interrupt modules.
the lOP gates of the M736 of
The computer now issues an IOp2 pulse to the IOp2 gate of the M736
module. The output of the IOP2 gate now produces an IOT2 pulse which
causes the "Clear the AC" line of the I/O bus to be pulled to ground, and
thereby clears the AC.
The computer issues an IOpl pulse to the IOPl gate of the M736 module.
The output of the lOP! gate produces an IOTl pulse which is applied to the
strobe inputs of the AC input bus gate. As the other inputs of the AC input
bus gate are connected to the outputs of the address gate, appropriate lines
of the AC input bus (AC 6 thru AC 11) will be pulled to ground thereby load
ing into the AC the starting address of the subroutine associated with the
particular priority I/O device to be serviced.
The computer now refuses to accept any further interrupt requests and jumps
to the subroutine with the particular starting address which was loaded into
the AC. The service routine of the particular priority device contains an in'
struction to clear the interrupt flag flipflop of the particular I/O device and
at the end of the subroutine issues the M736 device selector code with an
IOP4 which clears the priority flag flipflops of the M736. The computer now
turns on the priority interrupt system capability which allows the computer to
service any future interrupt requests.
USING THE M736 PRIORITY INTERRUPT MODULES
1. Assign a device selection code to the M736 priority system and connect
the device selection inputs of the M736 to the proper device selection
lines to assure decoding for that code. If more than one M736 is used
connect the device selection lines for each M736 in exactly the same
manner. Each M736 will use the same device selection code.
These inputs are: BT2, BSl, BRl, BPI, BNI and BS2.
2. Connect the enable input, BN2, of each M736 to +3V.

3. Connect the 10P'1 input, BJl, to the IOP1 bus line.
4.
Connect the IOP2 input, 8M2, to the IOP2 bus line.
5. Connect the IOP4 input, BH2, to the IOP4 bus line.

6. Connect the BTS3 input, Bll, to the BTS3 bus line.
7.
Connect the outputs of the external I/O device flag flipflops to the priority
NOTE: In normal operation, 10P-4. is not required as the flas flipflop In the external prl.
ority I/O device is cleared by the SUbroutine servicing that device. When the flas in the
I/O device is cleared. the next BTS03puise will load the disabled flag outpu tinto Its
r~spective priority flag flip-flop in the M/36 effectively clearing the priority flaB flip-flop.
fllp.flop.
179
inputs in such a manner as to pull the corresponding priority input line

of the M736 to GRO when the device flag is activated. These inputs are
as follows:
1st priority
BJ2
1st
2nd priority
BH 1
3rd priority
BF2
4th priority
BKI
5th priority
BJ2
2nd
6th priority _
BHI
Carry on for additional priority interrupt devices.
M736 Module
8. Assign starting address to the subroutines which will service each priority
interrupt device attached to the priority interrupt system. Also assign a
starting' address for the subroutine to service non-priority devices. Hardwire the various starting address of the service routines as follows:
AC(S)
AC(9)
AC(lO) AC(ll)
AC(6)
AC(7)
Priority I
BOI
BBI
API
ARI
AH I
AF2
Priority 2
AU2
ASI
AN 1
AKI
AFI
AAI
Priority 3
AT2
AR2
AM2
AL2
AEI
ABI
Priority 4
BAI
AS2
AL2
AMI
ADI
ACI
NON-Priority
BCI
BEl
BFI
AP2
AJ I
AH2
NOTE: If more than four external I/O devices require priority assignments,
the NON-priority address inputs BCI, BEl, BF1, AP2, AJl and AH2 of the
M736 module used for the first four highest priorities, must be connected to GRD. If more than two M736 modules are required all of the
NON-priority addrE;ss lines of each module except the last M736 containing the lowest priorities, must be connected to GRD. The NONPriority
address is hardwired to the NON-Priority address inputs of only the lowest
priority M736 module. All un-used priority address inputs must be
grounded. Logic 1 level for address may be obtained from module pin
BV2 of each M736 module. Lower priority addresses would be hardwired
on succeeding M736 modules in the same order hard wired to the second
M736 module as follows:
AC(6)
AC(7)
AC(S)
AC(9)
AC(lO) AC(ll)
Priority 5
BDI
BBI
API
ARl
AHl
AF2
Priority 6
AU2
AH2
AK2
AD2
AJ2
AE2
9. Connect the AC input bus gate outputs to the AC bus as follows:

Module Pins
AC(6)
AV2
AC(7)
AH2
AC(8)
AK2
AC(9)
AD2
AC(10)
AJ2
AC(ll)
AE2
10. Connect the Priority Enable input line BE2, of the M736 with the highest
priorities, or the only priorities, to ground.
11. If lower priorities of 5 or more are assigned, connect the Priority output
of the module with the higher priorities, Pin BD2, to the next M736
module (with the next following four lesser priorities) Priority enable in'
put pin BE2.
12. Last, but not least, connect the INITIALIZE input, BL2 to the Initialize line
of the computer 1/ 0 bus.
180
8-FAMllY
M737
12BIT BUS RECEIVER INTERFACE
POS.I/OBUS
M SERIES
Priee:
Length: Standard
Height: Double
Width: Single
$120
lOP1 1UI1W2
=>
['~
7'AE2
AOORSS
INPUTS
~AF2
L.!J
rpAtlZ
~lW2
"fAK2
.,..",AEI
I:::J
k.l8ll1
~
+3V-
~
CR.~
lOP 2 .... AN2
r---
r--'--
"""
IlU'fVI
CLEAREOON
.-OUTPUTS
SINK 250nA
8H2 0
BJ2
IIK2i
BL2,
AC 4 pAll
AC S P AMI
IIUS
GATE
OUTPUT
BUFFER
r"GISTER
BUFFER
AC6i@Al'41
AC1 P APt
8N2~
1IP2:;;:
BSZ~
pARt
ACe
AC9 pASt
P AU'
ACt t p AVt
aIlr.:t TEST
POINT
NarES:
AC 2 P AJI
AC 3 P AKt
* SKIP
BIIt@ P.I.
~~r~
2 -'52
INITIAL.Z! 1 Al2
ACe p AFI
AC t p AHI
esl
"---
Volts
+5
GND
Power
mA (max.)
300
~
1!U2~
BV2~
<=I
Pins
AA2, BA2
AC2, ATl, BC2. BTl
The M737 12Bit Bus Receiver Interface is completely contained on a double

height, single width module.
The M737 was designed primarily to receive and store in a buffer register
twelve parallel data bits from the positive bus of the PDp8/1 or PDp8/.L.
The M737 is pin compatible with the M738 CounterBuffer Interface, the
MI07 Device Selector, the MI08 Flag Module, and the I2Bit Bus Paneloid
E100. The 12Bit Bus Receiver Interface, M737, consists of three basic sec
tions: device selector, flag, and buffer register section.
181
Device Selector Section

The device selector section contains six address inputs which are to be connected to the proper BMB bits for address selection. lOP 1 input is used to
generate an lOT 1 which is used internally to test the flag. The output of flag
test gate is connected directly to the skip bus with an NPN transistor. The
output of the address selection gate is connected to the bus gate of the buffer
register section and functions as an option select level. lOP 2 is used for two
purposes. It is internally connected in such a manner as to clear the flag and
to load the buffer register with the contents of the BAC lines.
The Flag Section
The flag section is used to generate a programmed interrupt. The flag flip-flop
may be set by a level shift from low to high (a positive gOing voltage) applied
to the set input at pin AS2. The output of the flag is connected to the P. I.
line by way of a P. I. enable gate and an open collector NPN transistor. The
output of the flag is also connected to pin BUl. The flag is reset by IOP2
applied to pin AN2 or by initialize pulses applied to Pin AL2.
Buffer Register Section
Data from the bus is applied to the inputs of the bus gate. The bus gate
prevents the buffer register from loading the bus when M737 is not addressed.
The bus gate is enabled by the option select level derived internally from the
output of the device selector section. The buffer register is loaded by jam
transfer upon the command of an IOT2 instruction. The output of the buffer
register is buffered by the use of TTL circuitry.
Inputs: All inputs which receive positive bus signals are protected against
negative voltage undershoot. AE1, BV1 represent 1.25 TTL unit loads. These
two inputs need not be tied to a logic 1 source when not used.
AM2, AN2 represent 2.5 TTL unit loads.
AS2 represents 2 TTL unit loads.
All other inputs represent 1 TTL unit load.
Outputs: BSl, BRI will sink 25 MA to ground. Voltage applied to these outputs
must not be allowed to exceed +20 Volts. These outputs are protected
against negative voltage undershoot and consist of open collector NPN
transistors.
All other outputs will drive 10 TTL unit loads.
182
8.;FAMILY
M738
COUNTER-BUFFER INTERFACE
POS.I/08US
M SERIES
Length:
Height:
Width:
Standard
Single
Single
Volts
+5
GND
Price:
$185
Power
mA (max.)
Pins
AA2, BA2
AC2, ATl, BC2, BTl
250 mA-no strobe onto bus

370 mA-during bus strobe
The M738 provides a 12-bit binary up-counter that can be read to the positive external I/O bus of a PDP-8j I or PDP-81 L. The counter can be cleared
or preset to a starting value by a jam transfer from an external device. When
a count enable flag is set, the counter operates as an up-counter in response
to external clock pulses. The content of the counter can be strobed to the
I/O bus through data gates under program control.
APPLICATIONS
Interfacing a counting register to 1/ 0 bus
Parallel buffered data transfer to I/O bus
183
FUNCTIONS
Loading Counter/Buffer: The 12-bit counter/buffer consists of three MSI, 4-bit

presetable counters connected in tandem. Twelve parallel bits of data may be
applied to the data inputs and then transferred into the counter by the application of a LOW level (250 ns or longer) to the STROBE DATA IN pin AS2.
This input could be an lOT pulse from an MI02 or MI07.
Clearing Counterl Buffer: The counter may be cleared by a logic LOW at least
3 p,s in duration applied to the CLEAR COUNTER! BUFFER input pin 802.
The requirement of a 3 p'S pulse precludes the direct use of an lOT pulse for
clearing the counter. If it is required to clear the counter by an lOT pulse, an
M302 dual delay multivibrator could be used to stretch the lOT pulse length.
Bus Driver: The I2-bit bus driver strobes the contents of the buffer counter
onto the bus when a logic LOW is applied to the STROBE DATA OUT pin AU2_
The input to the STROBE DATA OUT pin AU2 would normally be an lOT
pulse derived from an MI03 or MI07.
.
All bus driver outputs consist of open collector NPN transistors which are
capable of sinking 25 mA to ground. Voltage applied to these outputs must
not exceed +20 volts. The outputs are diode-protected against negative
voltage undershoot in excess of -0.9 volts.
CLOCK ENABLE Flip-Flop: The clock enable flip-flop gates clock pulses to the
counter/buffer. This flip-flop may be cleared by a logic HIGH pulse to pin AL2
or by a logic LOW to the STOP input AT2. When the flip-flop is cleared, clock
pulses applied to the clock input, pin AV2, are not counted.
Counting: Clock pulses may be counted by setting the
flop with the application of a logic LOW pulse to the
AR2. The four inputs-ClOCK, START CLOCK, STOP
quire a minimum pulse width of 50 ns and, therefore,
derived from the device selectors MI03 or MI07.
COUNT ENABLE flipSTART CLOCK input

and INITIALIZE-recould use lOT pulses
Tandem Operation: At times, it may be desirable to connect two or more

M738 module counters in tandem. This may be accomplished by connecting
the "overflow" output pin BE2 of the first M738 to the START CLOCK input
pin AR2 of the next M738. Also, the signal on pin AR2 must be inverted and
connected to CLOCK pin AV2. The clear pulse time duration should be an
additional 3 p,S for each M738 added in tandem: i.e., 24 bits would require
a 6 p'S clear pulse.
184
PDP-II
M783
UNIBUS DRIVERS
UNIBUS
M SERIES
Price:
Length: Extended
Height: Single
Width: Single
$30
:
~12
:
~S1
:
~JI
1 J2
1 Nl
1 R2
~V2
1 :Vl
[!] =CONNECTS
~
~
~
~
TO UNIBUS
0= BUS DRIVERS
Volts
+5
GND
Power
mA (max.)
70
Pins
A2
C2. T1
The M783 consists of 12 drivers to be used as an input interlace to the

UNIBUS of the PDp11. Pin U1 provides +3 volts as a source of logic HIGH
for 10 TTL loads.
185
PDP-II
M784
UNIBUS RECEIVERS
UNIBUS
M SERIES
Length: Extended
Height: Single
Width: Single
Price:
sao
~
~
~
~
~
~
~
~
~
Volts
t~D
Power
mA (max.)
200
~
~
.~
R- BUS RECElVER
Pins
[~}'CONNECTS
A2
e2, T1
TO UNIBUS
The M784 consists of 16 inverting receivers that are used as an output in

,terface from the UNIBUS ofthe PDPH.
SPECIFICATIONS
Input Loading: All inputs present one UNIBUS receiver load. (See UNIBUS
description.)
Output Olive: Each output has a fanout capability of 7 standard TTL loads.
186
PDPll
M785
UNIBUS TRANSCEIVER
UNIBUS
M SERIES
Price:
Length: Extended
Height: Single
Width: Single
$35
B CI
1 81
R= BUS RECEIVER
O' BUS ORIVER
[j):CONNECTS TO UNIBUS
Volts
+5
GND
Power
mA (max.)
118
Pins
A2
e2, T1
The M785 consists of eight drivers and eight receivers for use as a device
interface with the PDpl1 UNIBUS. Pin Ul provides +3 volts and has an
output capability of 10 TTL loads. Driver gates have open collectors and are
capable of sinking 50 rnA with a collector voltage of less than 0.8 volts.
187
PDpII
UNIBUS
M786
DEVICE INTERFACE
M SERIES
Price:
Len~h: Extended
Height: Double
Width: Single
$220
(T(
.'[[
J
-I
['"'
~INTERRUPT
ENABLE a
INPUT
, CONTROL
a.;.
"-
I'
HIGH
BYTE
OUTPUT
CONTROL
BUS or-DIS
08-CL2
09-CK2
10- CJ2
If - CHI
12- CH2
13- CF2
00-25'
0'-252
02-2PI
03-2Lt
04-2P2
OS-2K2
06-2MI
07-2T2
08-2M2
09-202
10-2EI
~, REGISTER
8 BIT
I
HIGH-BYTE
a:~~1
13- 2E2
14-281
'5-2J'
_ 0 ATA TRANSMITTEO 2V2

_ N EW OATA READY 'V2
l::g~
BUS INTL L OLI
BUS 0
INT 8 2H2
0 0IN- OISIN
PROCESSOR
INT A 1T2
TRANSFER
001'
OUTPUT
-IJ LOW
BYTE
CONTROL
L:J
0 aou -O'SOUT
DEVICE
I.
,II
a alT
REGISTER
-, LOW 8YTE
0 eOUT -070UT
I"
OO-CS2
01- CR2
8i:g~
83:8~
-c
BUS oes, CP2
oe6,CV2
8~:1~
8~::~
04- IK2
1M'
06- lSI
01- ILl
os-
POWER
CA2, 0A2 +SV,600111A (max.l

C82,082 -ISV
CC2, CTI,OCI, on GAO
Volts
+5
GND
Power
mA (max.)
600
Pins
A2
C2, Tl
188
The M786 Device Interface is a double height module used in conjunction

with the- MI05 Address Selector and the M782 Interrupt Control to enable
an external device containing up to 16 bits to communicate with the KAll
Processor.
The Device Interface contains controls for reading a 16 bit word from an external device into the processor, a 16 bit register that may both be loaded
and read by the processor (whose outputs are available to an external device), two interrupt enable flip-flops which may also both be read and loaded
by the processor, and two REQUEST bits controlled by an external device.
The device may signal the processor by generating an interrupt signal on
one of the two REQUEST lines. If the appropriate interrupt enable flip-flop in
the device interface is set, an interrupt signal is sent to the processor_
Input Loading:
All standard TIL loads.

All one unit loads except REQUEST lines which are two unit
loads.
Output Drive:
All 8 unit loads.
189
8FAMILY
M907
DIODE CLAMP CONNECTOR
POS.I/OBUS
M SERIES
Length: Standard
Height: Single
Width: Single
Price:
$16
AI 81 Cl 01 E 1 F t HI
Jl Kl L1 M1 Nl P1 Rl SI T1
r f Iff Iff 1 f f 1- f I f 1~
~~
Ut VI
C2 02 E2 F2 H2 J2 K2 L2 M2 N2 P2 R2 S2 T2 U2 V2
1IfIiI!Il IiI fiI ~

Power
Volts
mA (max.)
+5
10
GND
Pins
A2
AI, Cl, Fl, KI, NI, RI, T1

C2, F2, J2, l2, N2, R2, U2
The M907 is used to provide proper undershoot ground clamps for positive
1/0 bus signals not using MI03 or MIO} inputs.
The M907 also provides +3 volts for clamping 25 unused inputs. Diode
ciamps appear on signal leads used in double-sided alternate-ground I/O
cables.
190
PDP-I5
BUS
M909
TERMINATOR
Length: Standard
Height: Single
Width: Single
M SERIES
Price:
81
"
02
"-
$14
6eA
01 n
E2
n.
"-
H2
I"\.
Hi
Jf
K2
Lt
--
--,..
n
,..
M2
M1
P2
P1
52
$II
T2
V2
Volts
+5
GND
Power
mA (max.)
NONE
,..
,..
,..
,..
-,..,..
-
-'-
Pins
AI, CI. C2. Fl. J2. KI

L2. NI. N2. RI. R2. n. U2
The MOO9 module contains eighteen 68ohm resistors tied to ground through
a common bus.
.
APPLICATIONS
This module is intended to be used with the M910 to form half of the
biasing circuit used in the driving network of the M622.
191
PDP-IS
BUS
M910
TERMINATOR
length: Standard
Height: Single
Width: Single
Volts
+5
GND
Power
mA (max.)
1350
68il
M SERIES
Price:
Pins
A2
AI, CI, C2, FI, F2, J2. Kl

L2, NI. N2, RI. R2, n. U2
$20
-. 81
"
J"\ 02
-.
." 01
-.
E2
"
-.
--
E'
-. H2
"
-. H1
-. K2
--
-.
-.
"
-.
Jf
M2
L1
J"\ M1
-.
--.
P2
P1
-.
S2
-. S1
,.
-. T2
---
-. V2
+5V
A2
The M910 module contains eighteen 68-ohtn resistors tied to a common +5

volt bus .
. APPLICATIONS
This module is intended to be used with the M909to form half of the biasing
circuit used in the driving network of the M622.
192
UNIBUS/
OMNIBUS
M1500
BIDIRECTIONAL BUS
INTERFACING GATES
Length: Extended
Height: Single
Width: Single
M SERIES
Price:
Power
Volts
mA (max.)
+5
300
GND
193
Pins
A2
e2, T1
$35
This module provides gating arrangements useful for interfacing to the

PDPa/ e, PDPa/ m and PDpll computers. It is designed specifically to pro
vide additional gating and output drive when using the M1501M1502 In
put/Output modules. Examples are shown in Figures 1 and 2.
SET
FLAG L - - - - - ,
r------------,I
.~+_~'~I
.1
.a.JUll'Ell$ CUf-()Uf
IL..
-1;'-500tp;\~)- -
I
ACORESS
SELECTOR
f50-;RT~) -
I=L
'I
I
I
I
Skip and Interrupt Drivers for PDPal e or PDpS/ minter

facing.
Figure 1.
f;;;ARTW.) -
___________
-:- - -lftOjMiiT!AlI-,
S I
Sl.ECT 4 H
SELECT 8 H
OUT HIGH
OUT LOW H
IN H
I
I
______
Figure 2.
___
___ LI ________
l.aJUlolP,.,INOROUT
___ _
Using M1500AND Gates with M1501 in POpll 'Interfac

ing.
194
APPLICATIONS
PDpll Interfacing:
1. ANDing SELECT signals w.th direction signals (OUT HIGH, OUT

LOW) to load registers
2. ANDing SELECT signals with direction signals (OUT HIGH, OUT
LOW) to form set or reset pulses
3. Receiving the INIT (initialize) signal from the UNIBUS and distributing it via high-power drivers
PDP8/e, PDP8/m Interfacing:
1. Generation of addditional SKIP and INT RQST signals to supplement

those available on the M1510
2. ANDing BTP3 with an lOT for loading registers
GeneralPurpose Use:
1. Providing general-purpose high fan-out drivers

2. Providing a stage of inversion with high fan-out capability
Restrictions: The module is electrically, but not mechanically, compatible
with the PDP-S/e OMNIBUS. 00 not plug the module directly into the OMNIBUS. OMNIBUS signals may be connected to appropriate module pins by
backplane wiring. This module is designed for use in bus expansion hardware
such as:
BBll Blank System Unit (PDP-ll UNIBUS)
H9190 Bus Expander (PDPS/ e OMNIBUS)
FUNCTIONS
Inputs marked B present one bus receiver load to the UNIBUS or OMNIBUS.
All other inputs are standard TTL; unit loads are shown on the logiC diagram.
Output drivers marked 0 provide open collector outputs with jumpered-in

pull-up resistors to enable their use in general logic applications. These outputs may be used to drive UNIBUS or OMNIBUS lines if the associated jump
ers are cut out by the user.
All other outputs provide standard TTL drive as shown on the logic diagram.
195
UNIBUSI
OMNIBUS
M1501
BUS INPUT INTERFACE
M SERIES
Price:
Length: Extended
Height: Single
Width: Single
$50
r------+---V2
~~~======~-~---+v'
Volts
+5
GND
Power
mA (max.)
300
196
Pins
A2
e2, T1
The MI501 contains 16 bus drivers for interfacing parallel input data to a
bidirectional data bus structure such as the POP-l1 UNIBUS or the PDP-Ble
OMNIBUS. The module includes two control flags that can be used for interrupt request and enable. Data inputs from an external device enter a 40-pin
flat cable connector mounted on the module itself. All inputs are diodeclamped to ground and +5 volts.
.
APPLICATIONS
This module is designed for use in bus expansion hardware such as:
H9I90 Bus Expander (PDP-Ble OMNIBUS)
Expandability: In PDP-ll applications, up to four M1501 modules (64 bits)
can be controlled by one MI05 Address Selector module, one M7B20 Interrupt Control module, and one Ml500 Bus Gates module. Similarly, several
M1501's can be combined for multiple word input to a PDP-S/e by using an
M1510 Bus Device Selector module.
Restrictions: The module is electrically, but not mechanically, compatible with
the PDP-Ble OMNIBUS. Do not plug the module directly into the OMNIBUS.
OMNIBUS signals may be connected to appropriate module pins by backplane
wiring.
FUNCTIONS
Input from Cable: Data is gated from the input connector to the bus when
.
both loading inputs (AK2, AJ2) are HIGH.
Sendl Receive Control Signal: Two additional lines are provided from the cable
connector (Pins X and Z) to the module to allow communications between
the device and the computer.
Flags: A request flag (RE) and a request enable flag (RQE) are included on
the M1501. Both flags can be cleared on start-up directly from the GENERAL
CLEAR bus line. Both flag clock inputs are transition sensitive. The data input
to each flag is buffered by a bus receiver; thus, status data can be entered
directly from a bus line if desired. The request enable flag clock input responds to a HIGH going transition. The request flag has an input that is sensitive to a LOW going transition and an input that is sensitive to a HIGH going
transition. (Whichever input is not used should be connected to the proper
logic level to unassert it.) The user is given the maximum degree of freedom
to use the request enable flag as a 0 flop or as an RS flop because all inputs are accessible.
The output of each flag is fully buffered to protect the flag data as well as
to provide high output drive.
SPECIFICATIONS
Propagation Time:
FROM
TO
ns (max.)
40-Pin Connector
Inputs
Bus Data Outputs
50
Flag Clock Inputs
Flag Outputs
75
197
M1502
BUS OUTPUT INTERFACE
Length: Extended
Height: Double
Width: Single
Volts
+5 .
GND
Power
rnA (max.)
750
UNIBUSI
OMNIBUS'
M SERIES
Pins
A2
C2, Tl
Price:
$100
The M1502 is a versatile buffered output interface for up to 16 data bits,

arranged in two 8-bit bytes. The module accepts data from a bus structure
such as that provided in PDP-8/e or PDP-11. Storage flip-flops are included.
Outputs are supplied both to a 40-pin flat ribbon connector and to the backplane. Open-collector output drivers with pull-up resistors are included on
the module. Three flip-flops with type 0 as well as type RS inputs are provided as flags or synchronizing devices.
APPLICATIONS
H9I90 Bus Expander (PDP-8/e OMNIBUS)
Although intended for parallel data output, this module may be used to drive
indicators or relays.
Expandability: In PDP-ll applications, up to four M1502 modules (64 bits)
can be controlled by one MI05 Address Selector module, one M7820 Interrupt Control module, and one MI500 Bus Gates module. Similarly, several
M1502's can be combined for multiple word output from a PDP-8/e, by using
an M1510 Bus Device Selector module.
Restrictions: The module is electrically, but not mechanically, compatible with
the PDP-8/e OMNIBUS. Do not plug this module directly into the OMNIBUS.
OMNIBUS signals may be connected to appropriate module pins by backplane
wiring.
FUNCTIONS
Input from Bus: Data is loaded from the bus to the storage register on a
positive transition of the loading input (AMI), which loads all 16 stages.
Separate loading inputs are also provided for the lower and upper bytes (ABI
and AAI).
Flags: Three edge-triggered flip-flops are provided. Two of the flags may be
triggered by either negative or positive transitions; these supply buffered
drive to 40-pin connector outputs. The third flag is triggered by positive-going
transitions only, but has a SET input available at the backplane. This flag
provides an output to the backplane only.
All flags have separate reset inputs and may also be cleared by a common
reset line. The set and reset functions occur on logic HIGH levels. Unused
inputs should be connected to a logic level that will unassert them.
Note: Any of the flag outputs can be wired from the backplane to one of the
spare bus driver gates (AP2, etc.) for use as READY or INTERRUPT outputs.
198
~It=t::~~~
il-...,......---..
SA'
88
A82
r---------~~.---Y2
ALIa
J-------------~~~8
199
Spare Lines: Two additional lines are provided between the cable connector
and the module for additional communication between the module and the
external device. These lines are diode protected against voltage over shoot
below -0.75 volts or above +5.75 volts.
"
SPECIFICA,,{IONS
Propagation Time:
FROM
TO
ns (max.)
BUS DATA Input
40Pin Output
100
FLAG CLOCK Input
40-Pin Output
150
FLAG SET or CLEAR Input
Backplane Output
100
Output Drive: Outputs to the 40-pin connector are supplied by open-collector

high-voltage drivers. Resistors included on the module provide pull-up or
current sinking for, up to 20 TTL unit loads. If the supplied resistors are removed, the output stages will sink up to 40 mA at logic LOW and will with. stand a HIGH level of up to '+30 volts. These outputs may therefore be used
to drive many types of indicators and even relays. However, if inductive
loads are driven, diodes should be wired across each load to swamp inductive kickback.
200
M1510
BUS DEVICE SELECTOR MODULE
Length: Extended
Height: Double
Width: Single
PDP-8/E, 81M
OMNIBUS
M SERIES
Price:
Volts
+5
GND
Power
mA (max.)
Pins
600
AA2, BA2
AC2, ATl, BC2, BTl
MI510
OMNIBUS DEVICE SElECTOR
201
* STROBE
THESE COULD DRIVE BUS
IF PARALLEL
$100
The M1510 Bus Device Selector is designed for use with the PDPS/e
and PDPSI m computers. It provides a convenient and efficient method of
decoding the device code for an interface system. The M1510 decodes the
six device selection bits to produce a device selection level. It also de,:odes
the three function selection bits to produce a one-of-eight function level
output.
The Ml5l0 contains bus drivers for: SKIP, INT RQST, CO, Cl, C2 (control
signals), INTERNAL I/O, and NOT LAST XFER; bus receivers for INITIALIZE,
TP3, 1/0 PAUSE, MD LINES; and a binary-to-octal decoder for MD LINE
decoding and generating a one-of-eight function level signal.
APPLICATIONS
H9l90 Bus Expander (PDP-8/e OMNIBUS)

with the PDP-8/e OMNIBUS. Do not plug the module directly into the OMNIBUS. OMNIBUS signals may be connected to appropriate module pins by
backplate wiring.
FUNCTIONS
Decoding: To decode a device code on MD lines 03 through 08, enter the
code in the DECODE MD inputs by grounding the zeroes and leaving the
ones disconnected. The example below shows the connections that will detect device code 58 (octal).
lOT CODE
...
OEVIC~
CODE
FUNcrl~
"
CODE
L~sl~'__'_1~0_1~'_1~0__
1,__
10__
1'~I1_I~x__lx~lx~1
BIT
234567891011
.........------103
t=~----i1O,4
.......~...----10S
.............--406
~~---'107
t=t':"-'---I08
Figure 1.
Detecting Device Code 53 (octal)

202
Spare Circuits: Additional AND gates, open collector NAND gate drivers and
non-inverting drivers are available on the M1510. These devices are useful
as general M Series devices if some standard bus signals (e.g., TP3, INIT,
e LINES) are not needed.
SPECIFICATIONS
Propagation Time:
FROM
I/O PAUSE
ns (max.)
TO
Device Selection
Output
100
lOT Outputs
100
203
UNIBUS!
OMNIBUS
M1621
DVM DATA INPUT INTERFACE
M SERIES
Lengt": Extended
Height: Quad
Width: Single
CABL
CONNECTOR
I
'A
GND
Volts
+5
Power
mA (max.)
777*
GND
Pins
A2
C2, T1
plus current required by instrument
204
Price:
$125
The M1621 is a PDP-l1 and PDP-8/e, 8/m interface module containing all
. the bus drivers and control logic needed to input TTL-level information from
several types of digital voltmeters and multimeters. All inputs from the instruments enter a 40-pin cable connector mounted on the module.
Some of the digital voltmeters and multimeters that can be interfaced by
the M1621 are:
Fluke
Hewlett-Packard
Data Precision
Systron- Donner
Dana
Model
Model
Series
Model
Model
8200A, 8400A
3450A, 3480A
2000
7110
4800
The user should first compare the interfacing requirements of his particular
instrument with the capabilities of this module. Many instrument manufacturers have various control options which should be chosen carefully for
compatibility with the M1621.
APPLICATIONS
PDP-II Interfacing: For interfacing to the PDP-lI, the MI62I must be used
with the MI05 Address Selector (or equivalent). The MI05 decodes the
UNIBUS address lines and causes transfer of information through the M1621
under program control. Interrupt circuitry is also built into the MI62I and
can be used in conjunction with the M7820 or equivalent. An example of a
typical PDP-II interface using the M1621 is illustrated in Figure 1.
<"
INTERRUPT
"
,/
M7820
INTERRUPT ENABLE
SELECT LINES
"\/'
MI621
II"
COMPUTER
AOORESS BUS
'"
/I/'
MI05
CONTROL
DATA LIlES
FROM QVM
OUT HIGH
OUT LOW
IN
Figure 1.
Typical PDP-ll Interface
PDP-8/e Interfacing: To interface to the PDP-S/e, the M162I must be used

with the MI5I0 Bus Device Selector which performs the same functions as
the MI05 besides having skip capability. For a PDP8/e interface, it is necessary to change jumpers on the M1621 control inputs. Remove jumpers WI,
W3, and W13. Insert jumpers W2, W4, and W14.
such as:
BBlI Blank System Unit (PDP-ll UNIBUS)
H9190 Bus Expander (PDP-8/e OMNIBUS)
205
FUNCTIONS
Bus Drivers: The bus drivers on the M1621 are arranged in separately enabled groups of input words. A 12bit word normarty transfers the DVM's
range and function data outputs. Another 16bit word transfers the first four
digits of data output. The third sixbit word might represent the fifth digit
of data output plus the overrange and polarity outputs. Each word can be
strobed to the computer bus by signals created by the MI05. The output
circuits consist of bus drivers connected in a wiredOR arrangement as
shown in Figure 2. Note that input lines from the DVM are protected by
clamping diodes to prevent input signal swings above or below the normal
TIL levels.
SELECT
+5V
CABLE
CONNECTOR
I
I
Figure 2.
Typical Input Circuit
Fla,s: The INTERRUPT flag can be set by the PRINT COMMAND or END OF
CONVERSION signal from the instrument. Jumpers (Wll, W12) are provided
which allow the user to select whether the positive or negative transition will
set the flag. Interrupt capability is enabled by a second flag INTERRUPT
ENABLE, which can be set under program control. Both the INTERRUPT
and INTERRUPT ENABLE flags are applied to an M7820 (or equivalent) for
computer interrupt. The INTERRUPT flag can be cleared by signals from the
MI05 (or MI5IO); both flags are always cleared by ~omputer power up.
Status Gates: Status gates'on the M1621 giv~ the programmer the ability to
check the states of the INTERRUPT and INTERRUPT ENABLE flags and the
overload status of the external instrument. These gates are software enabled
through the address selector (MI05 or MI510).
Trigger Pulse Generator: For triggering of external equipment, the MI62I
contains a one-shot circuit that can be triggered from the device selector
(MI05 or MI5IO). The output pulse width is adjustable from 2 to 12 JJ.s by
a trimpot on the module. Longer pulses can be obtained by adding a capacitor at the split lugs on the module. The following equation can be used to
determine added capacitance:
Tpw=O.32(RC)
where Tpw is in milliseconds, R is in ohms, and C is in micro.farads. (The
internal trimpot varies from 5.2K to 50 K ohms.)
206
UNIBUS/
OMNIBUS
M1623
INSTRUMENT REMOTE
CONTROL INTERFACE
M SERIES
Price:
length: Extended
Height: Quad
Width: Single
The M1623 is a PDP-ll and PDP-8/e, 81m interface module containing all
the bus drivers and control logic needed to remotely program several types
of digital voltmeters and programmable power supplies. All outputs to the
instrument are through a 4O-pin cable connector mounted on the module.
Some of the digital voltmeters and power supplies that can be interfaced by
M1623 are:
th~
DIGITAL VOLTMETERS
Model 8200A, 8400A
Models 3450A,' 3480A
Series 2000
Model 7110
Model 4800
Fluke
Hewlett-Packard
Data Precision
Systron-Donner
Dana
PROGRAMMABLE POWER SUPPLIES

Models 4210A, 4216A,
4250A, 4265A
Models 6130B, 6129B,
6131B
Fluke
Hewlett-Packard
The user should first compare the interfacing requirements of his particular
instrument with the capabilities of this module. Many instrument manufacturers have various .control options whi.ch should be chosen carefully for
compatibility with the M1623.
APPLICATIONS
PDP!! Interfacing: For interfacing to the PDPll, the M1623 must -be used
UNIBUS address lines and causes transfer of information through the M1623
under program control. Interrupt circuitry is also built into the MI623 and
can be used in conjunction with the M7820 or equivalent. An example of a
typical PDPll interface using the MI623 is illustrated in Figure 1.
INTERRUPT
.A
<'"
'"
M7820
INTEI'RUPT ENA8LE
SELECT LINES
COMPUTER
ADORESS BUS
'"
.AI"
Mt05
Mf623
CONTftOL TO
INSTRUMENT
OUT HIGH
Figure 1.
"
...
OUT lDW
IN
Typical PDP-ll Interface

207
~ STATUS
.. ~::
...,
Rl.4.
SlL41N
.....
".oJ
it
c....
Jf
...!III..
_~";;....J
----LJ
__ l
uu
.
NIL
r---;+
...
~:
-...
:!::....
....
_D. L ......
l' ...~
it .,.
~
~
~
""Ill
~~
h-,"
V
tEL 2 OUT ......
~~~'
"I
=-.
0=0
-r
010 H
. =,
DII H
I
1
013"
Ot4t4
C,
D"
1
1
"H
""
.-
""
=
lIE.""
DATA
-:;:
..
...
~1fT.PIOTl
Power
mA (max.)
1600 ,
Pins
A2
e2, T1
plus current required by instrument
208
AU---'j'1.,
."2 ~
"17
_T
_ m ..
..
--::-'...
r:'"WI,
...--l..V
CClNTI'tOL II1ft"'A
+5
DO
..
GND
....
.., ,
Volts
--."_..
1
1
1
1
I
.-o...o<}-l
..
".l-J
"'.-.
"!!.
SHOT
1
1
.,.....!.!..c
~~:
I-;tW
.. ~e;
'=
DH_
DH _
=,
~~
,----
--_.
1
...
~
.
ii
QUTI.,OW
,.,-
II
SELlIN
.......
mA112
".,
s.
,..9;"
'-sr.. I
--.
_H
vv
~~W
---
".7
;~~
:i:_
....... L
DH
15
1
1
iil....
"DlGl
D.".
".,
';"f
-
r-~U
DO
pp
f-----L.i
DO,H
KlZ.
... ...'"
---'-
=1
1
1
SL.4OUT L.OW
- - !~!
101
\+
_.
_..
COfiIiIEClOfl:
1
H", }.T._
-- " " II
~ I
""-ru+J
"'"
....
--m..
PDP-8/e Interfacing: To interface to the PDP-8/e. the MI623 must be used

with the M15IO Bus Device Selector which performs the same functions as
the MI05 besides having skip capability. For a PDP-8/e interface, it is
necessary to change jumpers on the MI623 control inputs. Remove jumpers
WI, W4, W5, W7 and WIO. Insert jumpers W2, W3, W6, W8 and W9.
such as:
FUNCTIONS
Registers: The M 1623 contains two registers, one 8-bit and one I6-bit, both
interfaced tei the computer bus data lines by ungated receivers. Data from'
the computer is cfocked into the registers by strobing signals derived from
an MI05 or MI510. The user has the option of strobing whole words or
8-bit bytes. All register outputs go to the 40-pin connector.
Flags: The INTERRUPT flag can be set by the CONVERSION COMPLETE or
READY signal from the instrument. Jumpers (WI9, W20) are provided which
allow the user to select whether the positive or negative transition will set
the flag. Interrupt capability is enabled by a second flag, INTERUPT ENABLE, which can be set under program control. Both the INTERRUPT and
INTERRUPT ENABLE flags are applied to an M7820 (or equivalent) for computer interrupt. The INTERRUPT flag can be cleared by register-load signals
from the MI05 (or MI510); both flags are always cleared by computer
power-up.
Register Content Check: To add flexibility to this module, gates are provided
to allow the program to check the state of each register output. Each register
bit is fed to a bus driver which can be enabled by a signal from the MI05
(or M15IO).
Register Preset Jumpers: The MI623 also has the option of either setting or
clearing the registers during computer power-up. Jumper WI 1 will cause all
register bits to clear on power ~p. If WI 1 is removed and WI2 inserted,
all register bits will set on power-up.
Status Gates: Status gates on the MI623 give the programmer the ability to
check the states of the INTERRUPT and INTERRUPT ENABLE flags and the
status of the external instrument (overflow, remote enable, and latch status,
for example). These gates are software enabled through the address selector
(MI05 or MI510).
Trigger Pulse Generator: For triggering of external equipment, the M 1623
contains a one-shot circuit that can be triggered from the device selector
(MI05 or MI510). The output pulse width is adjustable from 2 to 12 ~s by
a trimpot on the module. Longer pulses can be obtained by adding a capacitor at the split lugs on the module. The following equation can be used to
determine added capacitance:
Tpw=O.32(RC)
209
where Tpw is in milliseconds, R is in ohms, and C is in microfarads. (The

internal trimpot varies from 5.2K to 50K ohms.) Jumpers (W13, W14) are
provided which allow the user to select either a positive or negative output
pulse.
SPECIFICATIONS
Output Drive: Outputs to the 40-pin connector are supplied by open-collector
high-voltage drivers. Resistors included on the module provide pull-up or
current sinking for up to 20 TTL unit loads. If the supplied resistors are removed, the output stages will sink up to 40 mA at logic LOW and will withstand a HIGH level of up to +30 volts. These outputs may therefore be used
to drive many types of indicators and even relays. However, if inductive
loads are driven, diodes should be wired across each load to swamp inductive kickbaCk.
210
M1702
OMNIBUS INPUT INTERFACE:
TRIPLE 4-WORD REGISTER FILES
PDP8/E, 81M
OMNIBUS
M SERIES
Price:
length: Extended
Height: Quad
Width: Single
$200
DESCRIPTION
The M 1702 provides, on a single quad-height module, a complete, selfcontained interface that will buffer twelve 12bit words of TTL-level data for
input to the PDP-8/e, 8/m OMNIBUS under Interrupt or programmed I/O
control. Input data is stored in three independent 4-word register file~ that
operate on a firstin/first-out basis. The external device can load up to four
words into each of the three files. When a file is full, it delivers a WRITE
DISABLE output to inhibit writing until space has been created by reading
one or more words to the OMNIBUS input data lines. To read a word of
data, the computer generates an lOT instruction addressed to one of the
three files. The oldest word of data in the specified file is input to the computer on the OMNIBUS and then erased from the register.
The M1702 plugs directly into the OMNIBUS connector assembly, and the
external device plugs into three 40-pin flat cable connectors on the module
itself. The module includes device selectors, operation decoders, flags, and
all control logic needed to r.equest interrupt and respond to programmed I/O
commands on the OMNIBUS. Command codes assigned to this module
include:
ENABLE and DISABLE INTERRUPT
CLEAR FLAGS
SKIP IF DEVICE FLAG A, B, or C SET
READ DATA A, B, or C
Device selection codes of 14 and 15 (octal) are assigned to this module
but the codes can be changed by moving wire jumpers.
APPLICATIONS
Lowcost multiword input buffering
Convenient handling of 12 to 36-bit word lengths
FUNCTIONS
loading Register Files: To enter data into a fife, the external device presents
TTL-level data to one of the 40'pin connectors and applies a negative pulse
to the WRITE IN line for that file. The data is loaded into one of the four
registers in the file and an internal DEVICE FLAG is set. After every WRITE
IN operation, an internal cou'nter is stepped to select the next register in the
file. When all four registers are loaded, the WRITE DISABLE output for that
file is asserted.
Reading Into Computer from Register Files: When anyone of the device flags
is set, the INT RQST line to the OMNIBUS is asserted (if the INT ENABLE
flag is set). The computer then can determine which of the three files initiated the interrupt by a sequence of programmed lOT skip commands. When
the interrupting file is located. the computer generates a READ DATA (A, B,
211
, .. f - - - - - - ,
r-t--------.J1 1L-_ _4 - _ - - - ,
I
I
~~+---+_+_+__-___+_JI~
b
,I
III
...
a a au
~.
Ii
.~ ~!~
I i
T
nHIH
I!I !lI1!ll 1l"'1! !!II !!I
iii~lii
~
Volts
t~o
Power
mA (max.)
2200
Pins
AA2,
AC2,
ANI,
ATl,
AFl,
BA2, CA2
BCI, BC2, CCI, CC2, OCI, OC2
AN2, BNI, BN2, CNI, CN2, ONI, ON2
AT2, BTl, BT2, CTl, CT2, OTl, DT2
AF2, BFl, BF2, CFI, CF2, OFl, OF2
212
or C) command to gate the output of the specified file through the multiplexer gates to the OMNIBUS data lines. Words are read out in the same
sequence in which they were stored. Each file contains an internal counter
which keeps track of the next register to be read (the one containing. the
oldest data). As each register in a file is read, it is erased (cleared), creating
space for more data.
NOTE: If the computer attempts to read data from an empty file (one whose
flag is not set), the data lines will contain 7777 octal.
Device Selection Decoders: The device is addressed through two decoders,
assigned octal codes 14 and 15 respectively. A decoder is activated when
I/O PAUSE is asserted and the octal device code for the decoder is received
through <MD03:08>. The decoder output asserts the INTL I/O line and
enables the operation decoder.
Operation Decoders: The select bits (Moo9, 10, and 11) determine the type
of operation to be performed when one of the operation decoders is enabled by a device selection decoder.
INT RQST: This line is asserted by anyone of the device flags if the INT
ENABLE is set). The computer responds to the interrupt request by executing
a JMS 0 instruction.
INT ENABLE: This flag is set to enable and cleared to disable the jnterrupt
request function.
SKIP Control Line: If a DEVIOE FLAG is set, one of the SKIP ON DEVICE
FLAG instructions will assert the SKIP line, incrementing the content of the
computer's program counter.
Changing the Device Code: The device selection decoders are preset for device codes of 14 and 15 octal, respectively; however, split lugs on this
module permit the codes to be changed by the user to any octal number
from 00 to 77. To obtain the desired octal numbers, jumper the split lug
pairs that select the binary equivalent of the device code, as shown below:
3242311
20
19
:II
10
II
A. PHYSICAL LAYOUT Of JUMPER HOLES
DEVICE CODE
80
'
22 21 20 22 2' 2 0
1 3 5 7 9 It
81T"
81T-O 2 4 6 8 10 12
13 15 17 19 21 23
81T"
BITO 14 16 IB 20 22 24
ADO
JUMPER
AT:
rECOOER
A
DECODER
B
13
::I:iI::I
17
EXAMPLE
(DECOOER Al
0 I I 0 0
2 4 5 7 10 12
BINARY EQUIV. OF t4 OCTAt

REQUIRED JUMPERS
B. DETERMINING JUMPERS FOR NEW COOE ASSIGNMENTS
213
lOT INSTRUCTION ASSIGNMENTS

OCTAL
CODE
INSTRUCTION
PURPOSE
6140
Disable Interrupt
Clears the INT 'ENABLE flag is disable the

INT RQST line
6141
Enable Interrupt
Sets the INT ENABLE flag to enable the

INT RQST line
6142
Clear All Flags
Clears DEVICE FLAGS A, B, and C and

the INT ENABLE flag
6143
Skip if Device
Flag A+B+C Set
Asserts the SKIP line if any DEVICE FLAG'

is set. The computer responds by incrementing the program counter so that the
next instruction is skipped.
6150
SKIP On Device
Flag A
Asserts the skip line if flag A is set
6151
Skip on'Device
Flag B
Asserts the SKIP line if flag B is set
6152
Skip on Device
Flag C
Asserts the SKIP line if flag C is set
6153
Read A
Selects the earliest-Ioatled register of FILE

A and transfers its content to <ACOO: 11 >
over the OMNIBUS data lines; also clears
the register after reading
6154
Read B
Same as Read A but addresses File B
6155
Read C
Same as Read A but addresses File C
NOTE: Inner two code digits (14, 15) are the device code and are subject
to change.
SPECIFICATIONS
Each WRITE IN signal must be a negative pulse at least 50 ns in width; there
must be at least 50 ns between the end of one pulse and the beginning of
the next. The data inputs must be settled at least 15 ns prior to the negative
transition of this pulse. WRITE IN lines may be paralleled for simultaneous
loading of 24 or 36 bits of data.
214
PDP-8/E,8/M
OMNIBUS
M1703
OMNIBUS INPUT INTERFACE
M SERIES
Length: Extended
Height: Quad
Width: Single
Price:
$75
CABLE
CONNECTOR
BUS
RECEIVER
AND
DEVICE
RD DCtIE L
DEVICE
SEL
SELECTION
L -______________
DECODER
~ !2
011
~~ ""9
~ ~
II:
~ d ...
iii ... ~
cu
co
Cl
tEl
CII
CSt
CPI
CAl
INIT
M1703
12-BIT WORD BIE
BUS INTERFACE
Volts
+5
GNO
Power
mA (max.)
555
Pins
AA2, BA2, CA2
AC2, BCI, BC2,CCI,CC2, OCI, OC2
ANI,AN2, BNI, BN2,CNI,CN2. ONI, ON2
ATl, AT2, BTl, BT2, CTl, CT2, OTl, OT2
AFl, AF2, BFl, BF2, CFl, CF2, OFl, OF2
215
The M1703 provides, on a single quad-height module, a complete, selfcontained interface that will input 12 bits of parallel TIL-level data to the
PDp-ale or 8/m OMNIBUS, under interrupt or programmed I/O control. The
M1703 plugs directly into the OMNIBUS connector assembly, and the external device plugs into a 40-pin flat cable connector on the module itself.
The module includes a device selector, an operation decoder, flags, and all
control logic needed to request interrupt and respond to programmed 110
commands on the OMNIBUS. Command codes assigned to this module
include:
ENABLE AND DISABLE INTERRUPT
CLEAR FLAGS
SKIP IF DEVICE FLAG SET
READ DATA
A device selection code of 14 (octal) is assigned to this module but the
code can be changed by moving wire jumpers_
FUNCTIONS .
Device Selection Decoder: The device is addressed through this decoder
when I/O PAUSE is asserted and the octal device code for the decoder is
received through <MD03:08>. The decoder output asserts the INT. I/O line
and enables the operation decoder.
Operation Decoder: The select bits (Moo9, 10 and 11) determine the type of
operation to be performed when the operation decoder is enabled by the
device selection decoder.
DATA <00:11>: Data from the external device is applied to the bus drivers
on these lines. A READ DATA command enables the bus drivers and asserts CO and C1, thereby entering the data into ACO-ll via corresponding
OMNIBUS data lines.
READ RQST: When the external device is ready to input stable data, it applies a logic LOW for at least 50 ns on this control line, to set the DEVICE
FLAG. READ DONE goes HIGH within 60 ns after READ RSQT goes LOW.
DEVICE FLAG: After being set by a LOW on the RD RQST line, this flag
initiates an interrupt request (if INTERRUPT is enabled). This flag is sensed
by the SKIP control line.
INTERRUPT RQST: When this line is asserted by the DEVICE FLAG, an interrupt request is sent to the computer which responds by executing a JMSO
instruction.
INTERRUPT ENABLE: This flip-flop is set to enable and cleared to disable the
interrupt request function.
SKIP Control Line: If the device flag is set, the instruction SKIP ON DEVICE
FLAG asserts the SKIP line, incrementing the contents of the computer's
program counter.
READ DONE: This line stays HIGH as long as the DEVICE FLAG is set, and
signals the end of a data transfer by going LOW after the end of a RD DATA
pulse.
Changing the Device Code: The device selection decoder is preset for a
device code of 14 octal. However, split lugs on this module permit the code
to be changed by the user to any octal number from 00 to 77. To obtain the
216
desired octal number, jumper the split lug pairs that select the binary equivalent of the device code, as shown below:
to
A. PHYSICAL LAYOUT OF SPLIT LUGS

ISHOWING JUMPERS FOR DEVICE CODE 14 OCTAL)
ADD
JUMPER
AT:
DEVICE CODE
80
8'
22 2' 2 0 22 2' 20
BIT= 1
BIT=O
10 t2
EXAMPLE
0
1 I
to
11
0
12
BINARY Eaulv. OF 14 OCTAL

REQUIRED JUMPERS
B. DETERMINING JUMPERS FOR NEW CODE ASSIGNMENTS
lOT INSTRUCTION ASSIGNMENTS

Octal
Code
. Instruction
Purpose
6140
" Disable Interrupt
Clears the INTERRUPT ENABLE flag to disable the INT RQST line
6141
Enable Interrupt
Sets the INTERRUPT ENABLE flag to enable

the INT RQST line
6142
Clear Flags
Clears the DEVICE FLAG, asserts READ DONE

and clears INTERRUPT ENABLE flag
6143
Skip if Device
Flag Set
Asserts the SKIP line if the DEVICE FLAG is

set. The computer responds by incrementing
the program counter so that the next instruction is skipped.
6144
Read Data
Transfers input data bits <00:11> to

<ACOO:ll> through the OMNIBUS data
lines. Also clears the DEVICE FLAG, allowing
the RD DONE output to go LOW when the
data transfer is complete.
SPECIFICATIONS
Propagation Time:
FROM
LOW on
RD RQST input
ns (max.)
TO
RD DONE
going HIGH
217
60
M1801
16-81T RELAY
OUTPUT INTERFACE
Length: Extended
Height: Quad
Width: Single
UNIBUS/
OMNIBUS
M SERIES
Price:
$350
The M1801 is a PDP-11 and PDP-8/e, 81m interface module containing all
the bus receivers, relay drivers, and control logic needed to program 16
isolated single-pole relay contacts_ The relay contacts are available at two
40-pin cable connectors mounted on the module.
APPLICATIONS
PDP11 Interfacing: For interfacing to the PDP-11, the MI801 must be used
UNIBUS address lines and causes transfer of information throughh the
M1801 under program control. Interrupt circuitry is also built into the M1801
an(f can be used in conjunction with' the M7820 or equivalent. An example
of a typical PDP-ll interface is shown in the M1623 description.
POp-ale Interfacing: To interface to the PDP-8/e, the M1801 must be used

with the M1510 Bus Device Selector which performs the same functions as
the MI05 besides having skip capability. Two separate 8-bit words or one
12-bit word can be loaded from the OMNIBUS. For a' PDP-8/e interface, it is
necessary to remove jumper W33 and insert jumper W34 on the bus INIT
input..
with the PDP-8/e OMNIBUS. Do not plug the module directly into the OMNIBUS. OMNIBUS Signals may be connected to appropriate module pins by
such as:
BB11 Blank System Unit (PDP-11 UNIBUS)
FUNCTIONS
Registers: The M1801 contains two 8bit registers, both interfaced to the
computer bus data lines by ungated receivers. Data from the computer is
clocked into the registers by strobing signals derived from an MI05 or
M1510. The user has the option of strobing a single 16-bit word or two
8-bit bytes. A logic HIGH loaded into a register bit activates the corresponding relay output. Each relay output has a jumper and split lugs which allow
the user to insert contact filter circuits.
Data Strobe Outputs: Either of the register-loading input pulses will trigger
the two DATA STROBE output circuits. One of these outputs is a transistor
driver circuit capable of sinking 100 mA (clamped to +5 volts). If jumper
W54 is removed, the user can switch up to 20 volts at this output.
The second DATA STROBE circuit contains a one-shot which drives a relay
to provide a momentary contact closure. The one-shot has an internal
potentiometer for pulse-width adjustment from 5 to 20 ms. External capacitance can be added to split lugs on the module ~o increase the contact
218
lNHT 8t
SEl2 H L!t s""
CABlE
CONfECTORS
,,
,,
J'
I
I
!
I
I
I
"
8 :
v'
".,
".,
IN'
.. 180t
16-81T ftLAY
OUTPUT IIIITEI'tFACE
Volts
+5
GND
Power
mA (max.)
1450
219
Pins
A2
C2. T1
1:"1
closure time. Jumpers (W56 and W55) are provided which allow the user to
choose whether the relay output will be energized on a HIGH or lOW logic
level. Both DATA STROBE outputs are available at the 40-pin connector.
READY Relay and Level Inputs: When the interfaced device has received
data, it can signal the M1801that it is ready for another transfer by energizing the READY relay. This relay has a 5-volt coil rating and pulls in at
4.2 volts. A jumper (W52) and split lugs are provided for users who want
to add a voltage divider circuit. A second method of ready signaling is to
apply a voltage level (less than + 12 V) to connector pin IT. Contact filtering
(0.6 ms min.) is provided for either ~EADY input to prevent false triggering.
The switch filter output sets the INTERRUPT flag, thus requesting more data.
Flags: The INTERRUPT flag can be set by the READY signal from the external
equipment. The positive transition will set the flag. Interrupt capability is
enabled by a second flag, INTERRUPT ENABLE, which can be set under
program control. Both the INTERRUPT and INTERRUPT ENABLE flags are
applied to an M7820 (or equivalent) for computer interrupt. The INTERRUPT
flag is cleared by the register-loading signals from the MI05 (or MI510);
both flags are always cleared by computer power-ups.
Register Content Check: To add flexibility to this module, gates are provided
to allow the program to check the state of each register output. Each
register bit is fed to a bus driver which can be enabled f>y a signal from the
MI05 (or MI510).
Register Preset Jumpers: Each register bit on the MI80I has a jumper
which causes that particular bit to clear on power-on. If the user wishes to
set a particular bit, he must remove the jumper provided and install the
particular jumper which sets that bit. Care should be taken to insure that
both the set and clear jumpers are not inserted simultaneously.
DATA
Bit
Jumper
to CLEAR
Jumper
to SET
000
WI
W3
W5
W7
W9
Wll
W13
W15
W17
W19
W21
W23
W31
W29
W27
W25
W2
W4
W6
W8
WI0
W12
W14
W16
W18
W20
W22
W24
W32
W30
W28
W26
001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
Status Gates: Status gates on the MIS0l give the programmer the ability
to check the states of the INTERRUPT and INTERRUPT ENABLE flags. These
gates are software-enabled through the address selector (MI05 or MI510).
220
CAUTION
When the high output voltage or current capabilities of the Ml801 are used,
the M1801 should be shielded from all computer circuitry.
SPECIFICATIONS
Relay Contact Ratings:
Voltage:
Current:
Power:
Insulation resistance:
100 V max.
0.5 A max.
lOW max. resistive load
1,000 megohms
Data Strobe Output:

Current Sinking:
Voltage:
100 rnA max.
20 V max.
221
________________________________________-,o
r------------,
PDP!!
UNIBUS
M7820
INTERRUPT CONTROL
Length:
Height:
Width:
M SERIES
Extended
Single
Single
Q..EAR A H
Price:
$100
I RI
INTR A H
INTR ENBL A H
BG IN A H
BG OUT A H BV2
BUS BBSY L
BUS SSYN L Bet
BUS SACK L
INTR B H I
INTA ENBL B H 1
B MASTER
CONTROL
BG IN B H B El
BG OUT B H B AI
CLEAR B H 1 SI
02
VECTOR BIT 2 H I ~~~r-----~----~-~-~--=~~
630--~_.....--=L''-f
~--o---H~....:..:.::..j
NQ_
~~~ ~-<>---...--~
060. --U---t-i~~
670---o--+......---:..:.~
6BO---o--+......~..:...t
M
D---If-+._:.:.:,I.=...f B BUS INTR L
VECTOR
START INTR B L
CONTROL
J2
~--If-+._.:::L2=-t B INTR OONE A H

~--If-+._M:.:.:.2=-t B lNTR DONE B H
M7820
INTERRUPT CONTROL
MUST BE
GROUNDED
Volts
+5
GND
Power
mA (max.)
290
222
Pins
A2
C2, Tl
The M7820 is used in PDpll device interfaces. It consists of logic circuits

that can be divided into three functional sections: Master Control A. Master'
Control B. and INTR Control.
The Master Control circuits are used to gain control of the UNIBUS for satis'
fying the need to either gain direct memory access (DMA). or to perform the
INTR bus operation which alters program flow.
To become master of the bus involves a question of priority. Briefly. this
priority question is split into three phases: 1) bus request lines, 2) processor's priority level, and 3) physical placement of a device on the UNIBUS.
1) NPR
BR7
BR6
BR5
BR4
(highest)
(except for trap instructions)
(lowest)
2) The processor acknowledges

BR's of level > N:
where N is an Octal number in pro

cessor's status register. (NPR's are
not affected.)
3) Highest priority goes to the device closest to the processor on the unique
bus grant chain.
Theory Of Operation
If a device wants control of the bus, it asserts both INT A and INT ENS A.
Then a request is made on a BR. This then leads to priority determination
and a BG results. Now the Master Control A responds with BUS SACK. The
processor sees this acknowledgement and removes BG. When BUS BBSY
and BUS SSYN are negated, the Master Control A removes its BR and asserts
BUS BBSY itself. It also asserts Master A when it is in control of the bus.
Now the device can use the bus. To release control of bus, the device C8[J
assert CLEAR A or negate: INT A or INT ENB A. Master Control B is identical
to A.
The INTR operation transfers a "vector address" to the processor. At th}s
address is stored two consecutive words: 1) The starting address of the in
terrupt service routine, and 2) A status word. When the processor detects
this, a trap sequence is initiated (current value of PC and current status of
PS are stored and new ones are fetched). Now the interrupt service routine
is executed.
To start the process: START INTR A or START INTR B is asserted. Then BUS
INTR is asserted along with a 7-bit address. This is transferred onto the
data lines: BUS D <08:02> providing a range of 000 to 374 (OCTAL) in in
crements of 4. D <08:03>are controlled by jumpers, which when "in,"
force the bit to zero. The processor seeing BUS INTR asserts BUS SSYN.
When this is detected, an INTR DONE A is asserted which negates the START
INTR signal. This in turn negates BUS INTR, which negates BUS SSYN. As a
result, a trap sequence is initiated. Vector bit 2 controls D02. When it is
asserted D02 is asserted. It does not control any other bits.
The grant chain to tie in the Master Control is as follows:
BG IN has 3900 to GND and BG has 180n
+5 Volts.
EXT GND is used for testing purposes and should be tied to ground in nor
mal operations.
223
224
a~
analog modules
225
The A Series analog module line has been substantially expanded. Shown
here are a few of the new units.
The A Series additions are DTL and TTL compatible and compatible with
DEC K and M Series modules, computers, control systems and standard
instrumentation.
226
NOTES ON OPERATIONAL AMPLIFIERS

I. INTRODUCTION
This article describes some of the basic characteristics and uses of operational amplifiers. It is written especially for people with a digital background,
but with a limited exposure to analog technology. The equations presented
are not exact, but are good engineering approximations, which are accurate
enough for most applications. It is hoped that this simplified discussion will
provide more insight into the uses and limitations of operational amplifiers
than a more rigorous approach.
The operational amplifier is a basic building block in analog work, much the
same way as a NAND gate can be a basic building block in a digital computer. An operational amplifier (op amp) together with other components
such as resistors and capacitors, can be used to perform addition, subtraction, integration, and many other functions. Op amps can be used to make
oscillators, active filters, and even digital circuits such as Schmitt triggers,
gates, and flip-flops. When used with AID and 01 A converters in data processing work, op amps perform such functions as scale changing, offsetting,
and isolation between source and load.
II.
GENERAL CHARACTERISTICS
An operational amplifier can be considered a 3 terminal device, plus a' cbmmon or ground return, see Fig. 1. Chopper-stabilized op amps, which will
not be considered here, have the Plus Input permanently tied to ground. The
op amp is really a difference amplifier, in that it amplifies only the difference
between the two inputs, and tries to reject any DC or AC signal that is common to both inputs.
.'
Op amps are characterized by high DC gain, high input impedance, low output
impedance, and a gain that decreases with increasing frequency. Op amps
used without feedback would be operating open loop, a rare situation; but
with feedback the operation would be closed loop. The use of properly applied
negative feedback stabilizes the operation of the composite circuit against
changes in the amplifier, and provides its versatility and usefullness.
When an op amp is working in the linear region, two approximations can be
made to help in the analysis of the circuit configuration. First, the voltages
of the two inputs are the same; and second, no current flows into or out of
the input terminals. Fig. 2 shows a simple inverting amplifier. Assume the
Minus Input is 0 volts, the same as the Plus Input, and that no current flows
into the Minus Input, called the summing junction. Then il
iF, and some
simple manipulations show that the gain is equal to -RF/RI_ Similar reasoning applied to the non-inverting amplifier of Fig. 3 shows that the gain is
R, R 2 An easy way to remember this is to think of the two
equal to
-+
R,
reSistors as forming a tapped divider network.
III. SPECIFICATIONS
Specifications are usually given for open loop performance, so that the user
has to interpret and .calculate how this will affect his particular closed loop
circuit. The following section will give some brief descriptions of what some
of the specifications mean.
227
Settling time. This is the time it takes the output to get within and stay
within a certain amount of is final value, after the input has received a step
input, see Fig. 4. This parameter is important when an amplifier is used in
front of an AI D converter, since the AI D should not begin its conversion until
the amplifier has settled.
Overload recovery. It takes an overload recovery time for the output to
first assume its proper value after an overdriving input signal has been removed. However, the output still has not settled, and this extra time must
be waited before the output is valid.
Slew rate. This term is comparable to rise or fall time in a digital circuit.
It is a measure of how fast the output can change. If an amplifier output
could go from 0 volts to 10 volts in 2 Ilsec, it would have a slew rate of 5
volts/Ilsec.
Frequency for full output. This is the maximum frequency a~ which a full
scale sine wave (such as +10 to -10 volts) can be assured at the output,
without noticeable distortion. In many ways this is real frequency limitation
of an op amp, since up to this frequency there are no other restrictions on
the amplitude of the input signal.
Frequency for unity gain. The open loop gain of an amplifier is equal to
one at this frequency. But the input signal must be restricted in amplitude
such that the maximum rate of change of output (slew rate) is not exceeded.
Usually only millivolt signals may be processed at this frequency, therefore
the full amplifier bandwidth is not usable for normal data processing systems.
Impedance. The input impedance is simply the resistance between the
two inputs. The common mode impedance is the highest resistance attainable
with feedback.
Common mode rejection. This is a measure of how well an amplifier will
not respond to a signal common to both inputs. If used as a voltage follower,
an op amp with a common mode rejection ratio (CMRR) of 10,000 could
have error of 1 mv if the input were 10 v. (10/10,000 volts).
Voltage offset. The inability to achieve perfect balance in the input circuit
causes the output to respond to an apparent signal when the inputs are tied
to ground. For an inverting amplifier, the output error due to the input voltage
offset is equal to the offset times the closed loop gain plus one. With an
input offset of 3 mv, and a gain of 1, the output error would be 6 mv.
Fortunately, initial voltage offset can be trimmed with a potentiometer at the
right place in the circuit.
Current offset. Current offset (or bias current) multiplied by the feedback
resistor (Fig. 2) produces an output error. This effect can be minimized by
using the differential offset (the difference in offset currents for the two
inputs) when the resistance seen from both inputs to ground are equal. For
Fig. 2, the Plus Input should than be returned to ground through a resistor
equal to the parallel combination of R, and RF.
Output ratings. The output voltage and current ratings imply a minimum
value for the load resistor. 10 volts and 5 ma would correspond to a load
resistor of 2 K. In an inverting amplifier, the feedback resistor is a load for
the output, and the current through this resistor must be subtracted from
228
the amount of current still available at the output. All really useful operational
amplifiers can be shorted to ground without damage, but shorting to a volt
age will usually destroy some of the circuitry.
IV. APPLICATIONS
Some common configurations for operational amplifiers are shown in Figs.
5 through 10. The pin letter assignments correspond to the op amps sold
by Digital Equipment Corp. If these op amps are used, the jumper between
Pin S and the Minus input should be removed.
The voltage follower, Fig. 5, features high input impedance, but will have an
error depending on the CMRR. Large voltages cannot be handled, since com
mon mode voltage ratings should not be exceeded. The inverter configuration,
Fig. 7, is very versatile and does not have a common mode voltage prob
lem, since both inputs are near groumt Large input voltages can be handled
if the input resistor is made appropriately large. One disadvantage of the
inverting configuration is that the input impedance is relatively low, essen
tially equal to the input resistor. When a gain trim potentiometer is used,
the gain accuracy by itself becomes irrelevant. What is important is gain
resolution (mostly determined by the potentiometer), and the gain stability
(mostly determined by the temperature coefficients of the input and feedback
resistors). The ratio of the closed loop gain to the open loop gain gives the
suitability of an amplifier as far as static accuracy is concerned. With a closed
loop gain of 5, and an open loop gain of 10,000, an amplifier could be used
in a system with an allowable error of 1 part in 2,000.
The possibility of oscillation must always be considered when feedback amplifiers are used. Usually the more feedback used, the greater is the tendency
to oscillate. Oscillations can always be attributed to phase shift. Therefore,
stabilization of operational amplifiers involves phase shifting to oppose oscillation. In Fig. 7, the feedback capaCitor allows high frequency signals to be
fed back to the inverting input (degenerative feedback) with a phase lead.
0
In the inverting configuration, the output will be 180 out of phase with the
input at low frequencies, and the feedback signal will oppose the input signal.
At high frequencies, there are additional phase lags in the amplifier and
feedback circuitry. If the feedback signal has a total phase shift (lag) of 360 0
with a gain through the amplifier and feedback network of greater than 1,
the amplifier will OSCillate, since the input and output are in phase.
V.
REFERENCES
1.
"An Operational Amplifier Application Manual"

Analog Devices, Inc., Cambridge, Mass.
2.
"Handbook of Operational Amplifier Applications"

BurrBrown Resear~h Corp., Tucson, Arizona
3.
"Linear Integrated Circuits Applications Handbook"

Fairchild Semiconductor, Mountain View, California
4.
"Applications Manual for Operational Amplifiers"

Philbrickl Nexus Research; Dedham, Mass.
229
MINUS INPUT
(OR INVERTING
INPUT)
+/'
>----0 OUTPUT
j+
0-------1+
/
Yp
PLUS INPUT,
(OR NON-INVERTING
INPUT)
YOUT
O------~------------l~--------~O
VOUT ;: A (vp- vN)' WHERE A IS THE AMPLIFIER GAIN
Fig. 1, Basic Operational Amplifier Symbol
>--4......0
ASSUME:
Ys. 0
THEN
iss 0
VOUT
i t iF
YIN
YOUT
R;--R;VOUT
RF
YIN .. -
R;""
Fig. 2, Inverting Amplifier
ASSUME:
YOUT
THEN
iz~
5
it
Rz
.. YIN
is
.. 0
it
.. '2
Ys
At
Vs
+:--
Ys
YIN
..
"R,"-
Rt
vOUT- Vs
R2
vOUT - vlN
Rz
YIN R2 .. vOUT Rt - vlN Rt
RZ
'::"
R,
~= + - - Rt
vlN
Fig. 3, Non-Inverting Amplifier
230
INPUT
/\
OUTPUT.J
-"
AV.i
-:].J~\OJ1~~...~===:..
AV - - - - FINAL VALUE
,
I
IE- ts-+l
SETTLING TIME
Fig. 4, Setting Time
VOUT
ReOM MODE
v,N
(S)
RtN
VOUT
Fig. 5, Voltage Follower
fOpf
VOUT
VIN
--1
viN
lK
lK
R'N VOUT
Fig. 6, Inverter
231
lK
Your
YIN
RF
= -
R,
RIN
RI
GAIN STABILITY
DEPE NOS ON THE
INPUT AND FEEDBACK
RESISTOR, AND GAIN
TRIM POTENTIOMETER
Your
P
Rp
SELECT Rp =
R, RF
R,
+ RF
FOR
CURRENT DRIFT COMPENSATION.

TYP VALUES
R,
1K TO 10K
RF
1K TO 100K'
Rp
500n TO 5K
THE USE OF CF REDUCES THE

TENDENCY OF THE OP AMP
TO OSCILLATE
Fig. 7, Adjustable Gain and Current Compensation
VIN
R,
Your
I,
Ro
':"
vOFF
Fig. 8, Offsetting
232
YOUT
NON-INV
GAIN
R3
YOUT
~
RF+ R1
= Yz <R+'RH-R--)
ATTENUATION
FACTOR
Fig. 9, Differential Gain
233
RF
Y1 ( R )
INV GAIN
2n and Resolution
OF
BITS
2n
1
2
4
8
16
32
65
131
1
2
4
8
16
32
64
128
256
512
024
048
096
192
384
768
536
072
RESOLUTION
(%)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
100.0
50.0
25.0
12.5
6.25
3.125
1.563
0.781
0.391
0.195
0.0977
0.0488
0.0244
0.0122
0.00610
0.00305
0.00153
0.000763
234
PPM
1,000,000
500,00
250,000
125,000
62,500
31,250
15,625
7,812
3,906
1,953
977
488
244
122
61
31
15
8
DIGITAL CODES FOR AID'S,
DI A'S AND DATA ACQUISITION SYSTEMS

OFFSET BINARY
(BIPOLAR)
FULL SCALE -1 LSB ........................

+3/4 FULL SCALE .............................
+ 1/2 FULL SCALE .............................
ZERO ........................................
- 1/2 FULL SCALE .............................
- 3/4 FULL SCALE .............................
- FULL SCALE +1 LSB .........................
- FULL SCALE .................................
111111111111
111000000000
110000000000
100000000000
010000000000
001000000000
000000000001
000000000000
STRAIGHT BINARY
(UNIPOLAR)
+ FULL SCALE -1 LSB .........................
+ 3/4 FULL SCALE .............................
+ 1/2 FULL SCALE .............................
ZERO +1 LSB ...............................
ZERO ........................................
111111111111
110000000000
100000000000
000000000001
000000000000
TWO'S COMPLEMENT
(BIPOLAR)
+ FULL SCALE -1 LSB ........................
FULL SCALE ..... . . .. . . . .. . .. . . . .. . .. . . . .
+ 1/2 FULL SCALE .............................
ZERO .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
- 1/2 FULL SCALE .............................
-3/4 FULL SCALE .............................
- FULL SCALE +1 LSB ............ , . . . . . . . . . . . .
- FULL SCALE ..... . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 3/4
011111111111
011000000000
010000000000
000000000000
110000000000
101000000000
100000000001
100000000000
BINARY CODED DECIMAL

(UNIPOLAR)
+ FULL SCALE -1 LSD ......................
+ 3/4 FULL SCALE ...........................
+ 1/2 FULL SCALE ...........................
ZERO + LSD ..............................
ZERO ......................................
235
1001
0111
0101
0000
0000
1001
0101
0000
0000
0000
1001
0000
0000
0001
0000
A123
FOUR-INPUT MULTIPLEXER
Length: Standard
Height: Single
Width: Single
MULTIPLEXERS
A SERIES
Price:
$58
A R
A S
A T
A U
0'ANALOG SIGNAlS
(00 NOT CONNECT TO
LOGIC LEVELS)
Power
Volts
mA (max.)
+10
+5
18
45
-20
50
GNO
Pins
02
A2
C2. Tl
E2
236
I would like additional information on those items checked:
o
o
o
o
o
o
o
oo
Interface Design (50)

Support Hardware (40)
Standard Logic Modules (50)
Cabinets (40) .
Data Terminals (40)
Lab Series (40)
Special Logic Modules (50)
Wire Wrap Sel'\!ice(50)
Computers PDP" ________
o Logic Arrays (50)
Other _________________________________________________
I would also appreciate another copy of this 1972 LOGIC HANDBOOK. (50)
Name
Title
Company
Division
Street
City
I~
Zip
I would like additional information on those items checked:
o Interface Design (50)

o Support Hardware (40)
o Standard Logic Modules (50) o Cabinets (40)
o Data Terminals (40)
o Lab Series (40)
o SpeCial Logic Modules (50)
o Computers
Wire Wrap Service (50)
o
PDP" ________
o
Logic
Arrays
(50)
Other __________________________________________________
I would also appreciate another copy of this 1972 LOGIC HANDBOOK. (50)
Name
Title
Company
Division
Street
City
State
Zip
rio'" Ii
FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESARY
IF MAILED IN THE UNITED STATES
Postage will be paid by:
DIGITAL EQUIPMENT CORPORATION

DEPT. A.
MAYNARD, MASSACHUSETTS 01754
FIRST CLASS
PERMIT NO. 33
MAYNARD, MASS.
BUSINESS REPLY MAIL
NO POSTAGE STAMP NECESARY
IF MAILED IN THE UNITED STATES
Postage will be paid by:
DIGITAL EQUIPMENT CORPORATION

DEPT. A.
MAYNARD, MASSACHUSETTS 01754
The A123 Multiplexer provides 4 gated analog switches that are controlled
by logic levels of OV and +3V. The module is equivalent to a single'pole,
4'position switch. since one output terminal of each MOS FET switch is tied
together. If all three digital inputs of a circuit are at +3V (or not connected)
the two output terminals are connected together. If any digital input is at OV.
the switch terminals are disconnected. Two switches should not be on at
the same time. The analog switch can handle signals between +10Vand
-IOv. with currents up to 1 rnA.
The positive power supply must be between +5V and

15V. and at least
equal to or greater than the most positive excursion of the analog signal.
The negative power supply must be between -5 and -20v. and at least 10
Volts more negative than the most negative excursion of the analog signal.
The voltage difference between the two supplies must not be more than 30V.
SPECIFICATIONS
Digital Inputs
Logic ONE:
Logic ZERO:
Input loading:
+2.4v to +5.0V
O.Ov to +0.8V
0.5 rnA. at OVolts
Analog Signal
Voltage range:
Current (max.):
+lOv to -lOv
1 rnA
Output Switch
On resistance. max.:
On offset:
Off leakage, capacitance:
Turn on delay. max.:
Turn off delay, max.:
1000 ohms
o Volts
10 nA.lO pF
0.2 J,tsec
0.5 J,tsec
237
MULTI
A160
PLEXERS
HIGH IMPEDANCE MULTIPLEXER

EXPANDER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$250
A 852
A 8P2
8M2
Ar8=K2""""--+-++-+-_ _ _ _ _ _~)(}__+_...
A 8H2
A A
AAP
Volts
+15
GND
-15
Power
mA (max.)
25
ANALOG
25
238
Pins
AD1. AD2
AF1. AF2
AE1, AE2
<ANALOG SIGNALS
L~~U:VOE~~~CT TO
The A160 is a high impedance multiplexer expander consisting of 8 inde

pendent FET channels.
This unit may be used with any of the DEC high impedance multiplexers to
perform single or double level multiplexing. It also may be used to expand
the channel capabilities of the A162, A163, and A164, Multiplexer.
The A160 is DTL and TTL compatible and may be used with DEC's standard
K and M Series logic modules. Each channel has its own channel selector
driver and may be controlled from an external source such as a shift register,
clock, or gating function.
Advanced shielding techniques and optimized circuit layout have been
employed in the A160, ensuring stable operation under normal ambient elec
trostatic and electromagnetic conditions, as well as allowing minimal cross
talk between channels.
SPECIFICATIONS
Analog Inputs:
8 single ended
Input Voltage Range:
10V. Maximum full scale
Expander Node:
Common point of 8 channels brought

out to a common pin for input to ex
ternal buffer amplifier
Feedback Input:
Feedback control point of multiplexer

switches connected to output of buffer
amplifier
Input Leakage:
0.5 nano. Ampere max., per channel
Input Feedthrough Capacity:
4 pF per channel
OFF Channel Capacity:
7 pF per channel, shunt capacity at

common node
ON Resistance of Channel
(Without Buffer):
1000 ohms
Max. Input Voltage
15V.
Switching plus Settling Time:
5 JA.sec.,
Output Range:
Same as input ( 10 VFS)
Transfer Accuracy:
0.01 % of full scale at 25 C.
Selector Input
(Direct into Multiplexer):
One TTL load
ma~, to settle to within .01 %

of full value for full scale excursion
with zero source impedance
ON Level
logic Zero (0 Volts)
OFF level
logic One (+3 Volts)
239
MULTI-
A161
PLEXERS

WITH OUTPUT BUFFER
A SERIES
Length: Standard
Height: Double
Width: Double
Price:
$375
148$2
A BP2
A BM2
A BK2
-ANALOG SIGNALS
(00 NOT CONNECT TO
LOGIC LEVELS)
ABHZ
"AS2
"
"P2
Volts
+15
GND
GND
-15
Power
mA (max.)
35
LOGIC
ANALOG
35
Pins
ADl,
ACl,
AFl,
AEl,
240
A02
AC2, BCl, BC2
AF2
AE2
The A16l is a high impedance multiplexer consisting of 8 independent FET

switched channels and a non inverting unity gain follower amplifier. designed
for application where accuracy, high speed, and high input independance are
prime requirements.
This unit is OTL and TTL compatible and may be used with DEC K and M
Series logic modules. It will also provide excellent performance with systems
employing sample and holds, high speed multiplexing, A /0 converters. as
well as single and double level multiplexing.
Provided on the A161 are eight channel select lines, which may be controlled
from an external source such as a shift register, clock, or gating function.
The Al61 has been engineered and factory adjusted to provide rated performance. It also employs advanced shielding techniques and optimized circuit
layout, ensuring stable operation under normal ambient electrostatic and electromagnetic conditions, as well as allowing minimal crosstalk between
channels.
The AlGI has the capability of output channel expansion simply by typing
in the A1GO or A1G2 Multiplexer Expanders.
SPECIFICATIONS
Analog inputs:
8 single ended
Input voltage range:
10 V. Maximum full scale
Expander node:

out to pin as well as to input of buffer
amplifier.
Input leakage:
0.5 nano Ampere, max., per channel
Input feedthrough capacity:
4 pF per channel
OFF channel capacity:

common node
Series ON resistance of channel:
1000 ohms
Shunt ON Resistance to ground:
10 ohms min.
Switching plus settling time:
5 ~sec., max., to settle to within .01 %

of final value for full scale excursion
Fault protection:
Current limiting to 10 rnA. provided
Max. Input Voltage

(Without Damage):
15 V.
Output Range:
Output Current:
20 mA., maximum
Output Protection:
Short circuit protection, indefinitely to

ground
241
AmpJifier Offset:
Adjustable to zero
Transfer Accuracy:
0.01 % of full scale at 25 C.
Temp. Coefficient:
30 JA,V/ o C.
Selection Inputs
(Direct into Multiplexer):
One TTL Load
ON Level:
Logic Zero
OFF Level:
Logic One
242
MULTIPLEXERS
-A162
WITH DECODER
A SERIES
Length: Standard
Height: Double
Width: Double
Price:
$270
AU2
trl I
~~E
7
At
DECOOE
Volts
+15
+5
GND
GND
-15
AO
Power
mA (max.)
35
30
LOGIC
ANALOG
35
Pins
ADl; AD2
MI, AA2, BA1, BA2
AC1, AC2, BCI, BC2
AFI, AF2
AE1, AE2
~
AR2 9
AT2 9
ATZ 9
BL2 9
BN2 g
BR29
BT~-
g=
A BU2
BV2
.c"?I.
A 852
i5.c"?I.
A BP2
b
A BM2
~.
EXPANSIO NNODE
L"'A
A BK2
L"'A
[~}ANALO G SIGNALS
(00 NOT CONNECT TO
LOGIC L EVELS)
.10\
A 8H2
~
.10\
A A52
&
A APZ
jI('X
~
243
A F8NO DE
The A162 is a high impedance multiplexer with decoder consisting of 8 independent FET switched channels. Included on this module is a gated binary
to octal decoder for selecting any of the eight high speed channels.
The A162 may be used as a stand-alone multiplexer or with any of the high
impedance multiplexers to perform single or double level multiplexing. It
also may be used as an expander to increase the channel capabilities of the
A163 or A164, Multiplexers.
This unit has been engineered and factory adjusted to provide rated performance, and is fully compatible with DTL and TTL systems.
The A162 employs advanced shi~lding techniques and optimized circuit layout, ensuring stable operation under normal ambient electrostatic and electromagnetic conditions, as well as allowing minimal crosstalk between channels.
SPECIFICATIONS
Analog Inputs:
8 Single Ended
10 V. Maximum full scale
Expander Node:

out to a common pin for connection to
the input of the external buffer amp.-
Feedback Input:
Feedback control pOint of multiplexer

switches connected to output of buffer
amplifier.
Input Leakage:
0.5 nano Ampere. max., per channel
4 pF per channel

common node
ON Resistance of Channel,
(Without Buffer):
1000 ohms
Switching Plus Settling Time:
5 J.tsec., max., to settle to within .01 %

Decoder
Decoder:
One of 8 lines, decoded, binary
Decoder Outputs:
Select: Logic zero

De-select: Logic one
Decoder InputsAO IN to A2 IN:
Address Lines
One TTL Load
High = One
244
Decoder Gate Input:
logic zero enables decoder out
Fault Protection:
Current limiting to 10
Max. Input Voltage

(Without DaDmage):
15
Output Range:
245
v.
rnA provided
MULTIPLEXERS
A163
WITH DECODER AND BUFFER AMPLIFIER
A SERIES
Length: Standard
Price:
Height: Double
Width: Double
$395
t
AU2
rr' I
~t
8F2
Lt~2 ~
BFt
,~
Volts
Power
mA (max.)
+15
+5
35
30
-15
35
GND
GND
LOGIC
ANALOG
Pins
AD1, AD2
AA1, AA2, BAI , BA2
ACl, AC2, BC I, BC2
AFl, AF2
AEI, AE2
, 7 BLE DECOOE
I ~
AR2 9
AT2 9
BJ2 9
BL2 9
BN2 9
8R2 9
BT2 9
BV2 9
A BU2
:t;=
JID\
~
r>..
A BP2
[AlBM2
~
A BK2
D-00-r>.
A NODE
AJ2
~W
AH2
A
OUTPUT
OFFSET
AOJ
-r>.
-r>.
A BH2
~
A AS2
f~~
JID\
~
-r>.
A AP2
~
246
'ANALOG SIGNALS
(00 NOT CONNECT TO
LOGIC LEVELS)
The A163 is a high impedance multiplexer consisting of 8 FET switched

channels, a noninverting unity gain follower amplifier, and an 8 bit binary to
octal decoder for channel selecting.
This unit was designed for application where accuracy, speed, and high input
impedance are important factors. It also may be. used in systems which
employ sample and holds, Of A converters, and high speed multiplexing.
Provided on the A163 is an expansion node, which when used in conjunction
with either of the high impedance multiplexer expanders (Al60, A162) will
provide additional input channels.
The A163 is fully compatible wiht DTL and TTL logic levels and may be used
with DEC's standard K and M Series digital logic modules.
This module has been engineered and factory adjusted to provide proper
operation over the specified range.
Optimized circuit layout has been employed in the packaging of the A163
ensuring minimal crosstalk between channels. Advarrced shielding techniques
of the switching circuitry have been used to allow proper operation under
normal ambient electrostatic and electromagnetic conditions.
SPECIFICATION
No. of Inputs:
8 Si ngle Ended
10 V. maximum full scale
Expander Node:
Input Leakage:

out to pin as well as to input of buffer
amplifier
0.5 nano Ampere, max., per channel
4 pF per channel
7 pF per channel, shunt capaCity at

common node
ON Resistance of Channel
(Without Buffer):
1000 ohms
5 J,Lsec, max. to settle to within .01 %

Fault Protection:
Current limiting to 10 mA provided
Max. Input Voltage

(Without Damage):
15 V.
Output Range:
Same as Input ( 10 VFS~
Output Current:
20 mA, max.
Output Protection:
Short circuit protection, indefinitely to

ground
247
Amplifier Offset:
Adjustable to zero
Transfer Accuracy:
0.01 % of full scale at 25 0 C.
Temp. Coefficient:
30 IAv/
C.
Decoder
Decoder:
One of 8 lines, decoded, binary
Decoder Outputs:
Select: logic zero

De-select: logic one
Decoder Inputs-
AO IN to A2 IN:
Decoder Gate Input:
Address Lines One TIL load
logic zero enables decoder out
248
MULTIPLEXERS
A164
CONSTANT IMPEDANCE MULTIPLEXER

EXPANDER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$350
A BU2
10K
A 852
fOK
ABP2
10K
A 8M2
10K
AM2 A
EXPANSION
NODE
A 8K2
10K .
[~} ANALOG
SIGNALS
(00 NOT CONNECT TO
\.OGIC LEVELS)
A 8H2
10K
AAS2
10K
A AP2
10K
Volts
+15
GND
GND
-15
Power
mA (max.)
40
LOGIC
ANALOG
40
Pins
AD1, AD2
ACI, AC2, BCI, BC2
AFl, AF2
AEI, AE2
249
The A164 is an 8 channel constant impedance multiplexer expander utilizing eight FETS to switch the input signal through e:ght precision resistors
either to ground (OFF) or to a virtual ground null point of an operational
amplifier (ON).
This unit is used primarily with the A165. A166. and the A167 as a means
of providing additional input channels. It may also be used to do high voltage
multiplexing and input scaling.
The AI64 does not contain an output amplifier; thetefore. to ensure proper
operation. the output must be terminated into a buffer amplifier whose gain
is equal to minus one. The A164 or the A165 may be used to accomplish
this if the A164 is being used as an expander to either of these modules.
If used as a stand alone module. the A260 dual amplifier card may be used
as a buffer amplifier.
Provided on the A164 are eight channel select lines. These lines are brought
to pin connections and may be controlled from an external source such as
8 shift register. clock. or gating functions.
SPECIFICATIONS
Number of Inputs:
Input Impedance:
10.000 ohms
Input Range:
10 Volts
5 J,A.sec to .01 %
Expander Node:
Summing point brought to pin to allow

expansion of number of channels.
Switch Leakage:
0.5 nano Amp per "OFF" channel
Feedthrough (all channels OFF &

20 Vp-p at inputs):
-86d8 at 1 kHz (Ratio
Select Lines (1 TTL Load)"ON":
Logic Zero
"OFF":
Logic One
250
= 20,000: 1)
MULTI
PLEXERS
A165

WITH OUTPUT AMPLIFIER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$475
A 8U2
10K
A BS2
10K
10K
A BP2
10K
A 8M2
10K
AM2 A
E)(PIIINSION
NOllE
A BK2
10K
o
A BH2
'ANALOG SIGNALS
(00 NOT CONNECT TO
LOGIC LEVELS)
10K
A AS2
10K
A AP
10i<
Volts
+15
GND
GND
-15
Power
mA (max.)
40
LOGIC
ANALOG
40
Pins
AD1, AD2
AC1, AC2, BCI, BC2
AFl, AF2
AEl, AE2
251
The A165 is a constant impedance multiplexer consisting of eight independent channels which utilize FETS to switch the input signal through precision
resistors into either a ground (OFF) or a virtual ground of an operational
amplifier (on).
Included on this module is the operational amplifier, which has been factory
adjusted to yield a gain of minus one. Also included on the A165 are eight
channel select lines which may be controlled from an external source, such
as a shift register, clock, or gating functions.
The A165 is DTL and TTL compatible and may be used with DEC's standard
10K" and .oM" Series modules to perform control functions.
The A165 may also be used in the multiplexing of high voltage or input
scaling. It also may be used in conjunction with other constant impedance
multiplexers.
DEC's constant impedance multiplexers have been engineered and packaged
using optimized circuit layouts to ensure minimal crosstalk between channels.
Advanced shielding techniques allow stable operation under normal ambient
electrostatic and electromagnetic conditions.
SPECIFICATIONS
Number of Inputs:
Input l'lWedance:
10,000 ohms
Input Range:
10 Volts
Output Range:
10 Volts, inverted with respect to

input.
Output Drive:
20 mAo
5 f.,I.sec to .01 %
Expander Node:

Switch Leakage:
Transfer Ratio:
Minus one for 10V range
Transfer Accuracy:
0.015% of full scale
Temp. Coefficient of Offset:
50 IN I degrees C.
Temp. Coefficient of Gain:
7 PPM/degrees C.
f'eedthrough (all channels OFF &

20 Vpp at inputs):
-86d8 at 1 kHz (Ratio 20,000 :: 1)
Logic Zero
"OFF":
Logic One
252
MULTI-
Al66
PLEXERS

EXPANDER WITH DECODER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$365
Power
Volts
40
30
-15
40
GND
GND
Pins
mA (max.)
+15
+5
AD1,
AA1,
ACl,
AFl,
AE1,
LOGIC
ANALOG
AD2
AA2,BA1,. BA2
AC2, BC1, BC2
Af2
AE2
A 8U2.
tOK
A BS2
10K
A BP2
tOK
A BM2
10K
AM2
EXPANSION
NODE
A BK2
10K
o
A BM2
tOK
A AS2
10K
A AP2
10K
253
-ANALOG SIGNALS
(00 NOT CONNECT TO
LOGIC LEVELS)
The Al66 is a constant impedance eight channel multiplexer with decoder.

This unit can be used for multiplexing high voltage signals, single level or
double level multiplexing, input scaling, or as a means to expand the channel
capabilities of either the A165 or A167 DEC multiplexer.
Contained on the A166 as a binary to octal decoder which can be used to
select either randomly or in sequence any of the eight analog input channels.
If the A166 is to be used as a stand alone multiplexer, its output must
terminate into the null point of a buffer amplifier whose feedback resistor is
10,000 ohms.
SPECIFICATIONS
Number of Inputs:
Input Impedance:
10,000 ohms
Input Range:
10 Volts
Switching Plus SettHng Time

with output amp
5 ~sec to .01 %
Expander Node:

Switch Leakage:
Transfer Accuracy:

20 Vpp at .inputs):
-86dB at 1 kHz (Ratio 20,000: I)
Decoder
Decoder:
One of 8 lines decoded, binary
Decoder Outputs:
9 TIL Loads
Select
Logic Zero
Deselect
Logic One
Logic Zero
"OFF":
Logic One
Decoder InputsAO IN to A2 IN:
Decoder Gate:
Address Lines-3 bit binary code

One TTL Load
Positive Voltage = Logic One
One TTL Load
Logic One yields disable
Logic Zero yields enable
254
MULTIPLEXERS
A167

WITH DECODER AND OUTPUT AMPLIFIER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$490
Power
Volts
40
-15
40
GND
GND
Pins
mA (max.)
+15
+5
ADl,
AAI,
ACI,
AFI,
AEI,
30
LOGIC
ANALOG
AD2
AA2, BAI, BA2
AC2, BCI, BC2
AF2
AE2
A BU2
10K
A BS2
10K
10K
ABP2
10K
A 11M2
10K
AM2
EXPANSION
NODE
A BK2
10K
A 8H2
~ -ANALOG
SIGNALS
(00 NOT CONNECT TO
LOGIC LEVELS)
10K
AAS2
101<
A AP2.
10K
255
The A167 is an eight channel. constant impedance multiplexer with output

amplifier and decoder. The operation of the A167 is performed in the same
manner as any of the other DEC constant impedance multiplexers, where
the input signal is switched via FETs to either ground (OFF) or into a virtual
ground null point (ON) of the operational amplifier.
This unit may be used for multiplexing of high voltages, input sr:aling, and
in situations that require single or double level multiplexing.
The A167 has the capability of being expanded by any of the constant impedance multiplexers (A166, Al64). The limitation to the number of channel
expansions will depend upon system specifications, speed, leakage current
of OFF channels, and the output drive capabilities of the source.
The output amplifier has been factory adjusted and preset to a gain of
minus one. The decoder is an eight bit binary to octal decoder with gating
facilities on the decoder to control its states.
Advanced shielding and layout techniques have been employed on the A167
to allow stable operation under normal ambient electrostatic and electromagnetic conditionl as well as minimal crosstalk between channels.
SPECIFICATIONS
Number of Inputs:
Eight
Input Impedance:
10,000 ohms
Input Range:
10 Volts
Output Range:
10 Volts
Output Drive:
20 rnA.
5 JA,sec to .01 %
Expander Node:

expansion of number of chann~ls.
Switch Leakage:
Transfer Ratio:
Minus one for 10V range
Transfer Accuracy:
50 p.V/degrees C.
Temp. Coefficient 15f Gain:
7 PPM/degrees C.

20Vp-p at inputs):
-86dB at 1 kHz (Ratio 20,000 : 1)
Logic Zero
"OFF":
Logic One
256
Decoder
Decoder:
One of eight lines decoded, binary
Decoder Outputs:
9 TTL loads
Select
logic Zero
Deselect = Logic One
Decoder InputsAO IN to A2 tN:
Address lines-3 bit binary code

One TTL load
Positive voltage
logic One
Decoder Gate:
One TTL Load

Logic One yields disable
logic Zero yields enable
257
AMPLIFIERS
A207
OPERATIONAL AMPLIFIER .
A SERIES
Length: Standard
Height: Single
Width: Single
Price:
$45
-INPUT 5
(INVERTING) 0N-O-iTOE=2=::O-..,.L.--I
V
">--'-....,....0 OUTPUT
',,-,,'
+INPUT
(NON-INV) 0 - - - : : - - - - - - 1
-15V
F
ANALOG GNO
GND
Power
mA (max.)
6
ANALOG
-15
10
Volts
+15
NOTE 1.
Pins
02
F2
E2
Mounting holes are provided on the module so that input and feedback
components can be added. Components shown with dashed lines are not
included with the module.
NOTE 2. This jumper comes with the module. It may be removed to suit circuit reo
quirements.
NOTE 3.
Pins L & M can be connected together to improve settling time, but parameters such as drift and open loop gain are degraded.
The A207 is an economical Operational Amplifier featuring fast settling time

(5 J,LS to within 10 mv), making it especially suited for use with Analog-toDigital Converters. The A207 can be used for buffering, scale-changing, offsetting, and other data-conditioning functions required with AI D Converters.
All other normal operational amplifier configurations can be achieved with
the A207.
258
The A207 is supplied with a zero balance potentiometer. Provisions are made
on the board for the mounting of input and feedback components, including
a gain trim potentiometer. The A207 is pin-compatible with the A200 Operational Amplifier.
SPECIFICATIONS-At 25C, unless noted otherwise.

Pins L & M Differences with Pins
Connected L & M Not Connected
Settling Time
Within 10 mV, 10V step input, typ:
Within 10 mV, 10V step input, max:
Within 1 mV, 10V step input, max:
F~uency
3 ~tsec
5 ~sec
7 ,tsec
6
8
10
15,000
100,000
~lsec
~sec
~sec
Response
Dc open loop gain, 670 ohm load, min:

Unity gain, small signal, min:
Full output voltage, min:
Slewing rate, min:
Overload recovery, max:
3 MHz
50 kHz
3.5v/~sec
8 ~~ec
Output
Voltage, max:
Current, max:
lOV
15mA
Input Voltage
Input voltage range, max:
Differential voltage, max:
Common mode rejection, min:
lOV
lOV
10,000
Input Impedance
Between inputs, min:
Common mode, min:
100 k ohms
5 M ohms
Input Offset
Avg. voltage drift vs. temp, max:
Initial current offset, max:
Avg. current drift vs. temp, max:
.60 ,.,.V/oC
0.5 ~A
5 nA/oC
Temperature Range
OC to +60C
Gain of I, inverting or noninverting configuration.
259
30,.,.v/oe
AMPLIFIERS
A260
DUAL AMPLIFIER CARD

A SERIES
length: Standard
Height: Double
Width: Double
Rt2
Price:
$300
13
R21
Rl1
R24
~ =ANALOG SIGNALS
(DO NOT CONNECT TO
LOGIC LEVELS)
Power
Volts
+15
GND
-15
mA (max.)
20
ANALOG
20
Pins
AD2
AF2
AE2
The A260 is a universal dual amplifier card which contains two independent
operational amplifiers. Provisions have been made for mounting input and
feedback components so that \the A260 may be used in a variety of modes.
Some of the configurations in which the A260 may be used are:
1. Voltage follower with a gain of plus one.
2. Voltage follower with positive gain of greater than one.
3. Attenuated follower with positive gain of less than one.
4.
Differential amplifier with differential input and single ended output.
5.
Inverter with negative gain of one or greater.
The A260 may also be used as the output buffer for the Al60 and AI64
multiplexer series, as well as the input buffer for the A400 series sample
and hold modules. Individual offset adjustments are provided for on each
amplifier.
260
SPECIFICATIONS
Description:
Two differential amplifiers mounted

on one board with provision for
mounting resistors in a variety of
modes.
Offset:
Adjustments provided to adjust offset to zero.
Configurations
A.
B.
C.
Follower
High input impedance, gain of pius

one.
Transfer Accuracy:
0.01% of FS
Settling Time (0 to 10v):
1.5 lAS to .01 %
Output drive:
20 rnA.,
ground.
Input! output range:
10 Volts
Input impedance:
1000 megohms
Temp. Coefficient:
30 p.V/ DC.
Follower with Gain-
High input impedance, positive gain

greater than one.
Transfer accuracy:
Function of resistors provided.
Gain:
R14+ R15
Determined by
R15
Settling Time:
(Gain) x (1.5 p.s) to .01 %
Output Drive:
20 rnA.
ground.
Input/Output range:
10 Volts
short
short
circuit
circuit
proof
proof
to
to
Input Impedance:
~100
Temp. Coefficient:
30 p.V/ D C. (referred to input)
Attenuated follower-
Gain:
Input attenuator, positive gain less

than one.
R13
R12 + R13
(see schematic)
Transfer Accuracy:
Settling Time:
1.5p.s to .01 % if not limited by attenuator.
Input Range:
o to
Output Range:'
10 Volts
261
megohms
100 Volts, max.
D.
Output Drive:
20 rnA.,
ground.
short
circuit
proof
to
+ R13
Input Impedance:
R12
Temp. Coefficient:
30 I-'V! 0 C. plus input attenuation.
Differential Amplifier:
Differential input. single ended output.

R14
Gain:
Ri5
E.
Transfer Accuracy:
Settling Time:
(Gain) x (1.5I-'s)
Input Voltage (Signal plus common mode):
(1
+ _1_.
Gam
) X (10V) max.
Output Range:
10 Volts
Output Drive:
20 rnA., short
ground.
Temp. Coefficient:
(30 I-'V/ C) x (1
Common Mode Rejection:
Function of resistor matching in

each input> 86dB for .01 % resistor watch in addition to transfer
accuracy of .01 %
Inverter
Negative gain of one or greater
circuit
proof
Gain)
Specs same as differential amplifier, except input referenced to ground.
262
to
1. FOLLOWER
R12
R22
R13
R23
R14
R24
R15
R25
on
cD
cD
5K
on
cD
G=
5K
+2
2. PLUS GAIN
R4
EO
9K
R4+R5
EIN&~
1K
G&
HO
R5
3. POSITIVE GAIN LESS THEN ONE
~31 ~--+--I
50K
EO
EIN
SDK
+112
CD
G=
20K
20K
20K
1
20K
G=
10K
20K
20K
G=
-1
R3
="'R3+'R"2
4. DIFF. INPUT
R4
C2-5pF
R5
EO
R2
EO
R4
EIN
"'""'R5
R3
5. INVERTER
CD
R4
C2=5pF
R5
263
SAMPLE
& HOLD
A404
SAMPLE AND HOLD
A SERIES
Price:
, Length: Standard
Height: Double
Width: Single
'$130
GAIN TRIM
(8)
PINS AH
,,-- ......
---
a AJ SHOUlD
BE CONNECTED TOGETHER
TO~~T~
~ ANoOfilNlOOP--GAIN ARE DEGRADED.
AJ
TRACK CONTROL ElF

(POS')
(E)~
SAMPLE
AM>
HOLD
(D)
~ -ANALOG SIGNALS
DROOP
(C)
PE~ESTAL
(DO NOT CONNECT TO
LOGIC DEVICES)
Volts
+15
GND
-15
Power
mA (max.)
22
ANALOG
35
Pins
AD2
AC2. AF2
AE2
JUMPER CONNECTIONS TO OFFSET OUTPUT

MODE
PIN
BF (pos)
BO (neg)
TRACK (sample) HOLD
3v or open
Ov
-3v or open
Ov
Positive
Negative
AU to BJ
AU to BJ
BL to AD
BM to AE
BK to AF
Analog gnd (pin AF) and digital gnd (pin AC) must
be connected together at one point in the system.
264
BN to AF
The A404' Sample & Hold has an acquisition time of 6 JASec for a 10 volt
signal to within 10 mV (0.1 %). The circuit inverts the input signal, and has
an input impedance to 10 k. Features of the circuit include potentiometers
, to control the pedestal and the droop of the output signal.
Two digital Track Control (sample) inputs are provided: one for negative logic
(Ov & -3v), and the other for positive logic (Ov & +3v). Either input by .
itself will perform the neoessary control, and the inadvertent application of
both digital signals will cause no damage to the circuit.
Potentiometers are also provided for zero balancing, gain trim, and offset adjustment (up to 10v). If offsetting is desired, connections should be made
aecording to the table shown with the diagram.
SPECIFICATION8--At 25C, unless noted otherwise. Pins AH & AJ are connected together.
Acquisition Time
Within 10 mY, 10V step input, typ:
Within 10 mV, 10Vstep input, max~
Within 2.5 mV, 10Vstep input, max.
Aperture Time, max:
4 J,Lsec
6 JASec
11 J,Lsec
0.2 J,Lsec ,
Gain
-1.000 (adjustable 0.2%)
Input
Voltage range, max:
Impedance:
10V
10k ohms
Output
Voltage range, max:
Current, max:
10V
10mA
PedestalInitial pedestal:
Pedestal variation vs. temp, max:
Adjustable to less than 1 mV

0.2 mV/oC
Droop
Adjustable to less than 5 mVI ms
2 mV/ms/oC
Initial droop:
Droop variation vs. temp, max:
Track Control
Pos. (pin BF)
+3V, Track
OVat 2 mA, Hold
-3V, Track
OVat 1 mA, Hold
Neg. (pin BO)
Board Size
1 double height board, single module width
Temperature Range
OC to +50C
Difference in output voltage when changing from Track to Hold mode.
265
SAMPLE &
HOLD
A460/A461
SAMPLE AND HOLD
A SERIES
Length:
Height:
Width:
Standa:-d
Double
Double
Price:
A460-$400
A461-$525
NORMALLY
JUMPERED
r---- -,
I
1 AM2
CONTROL INPUT
=ANALOG SIGNALS
(00 NOT CONNECT TO
LOGIC LEVELS)
Volts
..L15
GND
-15
Power
mA (max.)
12, 20
ANALOG
12, 20
Pins
AD2
AF2
AE2
"with buffer
The A460 and A461 are one-channel sample and hold modules used to
sample the value of a changing analog signal at a particular point in time
and store this information as a stable analog voltage level. The A460 is without input buffering; the A461 includes a unity-gain input buffer amplifier.
When the A461 is used an external jumper is required betweeri pins BH2 and
AR2.
Provided on the A460 and A461 is a select line which can be used to control
the sample or hold operation of the module.
Both the A460 and A461 are DTL and TTL compatible and may be used with
standard "M" or "K" Series modules in control and system configurations.
The output circuitry consists of a buffer amplifier with output drive capability
of 20 mAo Both the A460 and A461 are compatible with DEC "A" Series high
impedance and constant impedance multiplexers and may be used with either
to perform various levels of multiplexing.
266
SPECIFICATIONS
Transfer Accuracy at 23 C.:
0.01 % FS in Hold mode
Input/Output Voltage Range:
10V Full Scale
Transfer Characteristic:
+1 (non-inverted)
Acquisition Time (to 0.01 %):
5 microseconds for -lOV to +10V

excursion
Aperture Time
Less than 50 nanoseconds
Input Impedance (During Sample

Time)(With No Buffer):
100 ohms in series with 0.002 mi

crofarad capacitor
1000 megohms in parallel with 10
pF.
(With Buffer):
Output Drive:
20 rnA.
Pedestal in Sample mode:
10 mV max.
Hold Decay:
15 IJ-V per millisecond
Offset:
Adjustable to zero
50 IJ-V per degree C.
Control Input (1 TTL Load)Sample:

Hold:
Logie Zero
Logic One
267
DIGITAL TO
ANALOG
A613
12-81T D/ A CONVERTER
A SERIES
Price:
Length: Standard
Height: Double
Width: Single
$200
MS8
2"
2 10
29
28
SWITCHES
27
26
BK
COM
24
2
BE2
BIN
25
____ J
B02
BCD
MODE
SELECT
22
8J2
BIN
21
COM
20
LSB
BCD
8M2
81-2
~~~~~]
BI~ '~~
IV
+3
+3
IV
(I
+3
OUTPUT
+O.OOOV
+5.000 V
+9.9915 V
0'ANALOG SIGNALS
(00 NOT CONNECT TO
LOGIC LEVEl.S)
Volts
+15
+5
GND
GND
-10 REF
-15
Power
rnA (max.)
35
60
LOGIC
ANALOG
-7
60 .
Pins
AD2
AA2
AC2
AF2
AH2
AE2
Analog and Logic ground must be connected together at some point in the system
reverse cu rrent
The A613 is a 12-bit Digital-to-Analog Converter for moderate speed applications. The module i!? controlled by standard positive logic levels, has an output between Ov and +10v, and will settle within 50 JJ.sec for a full scale
input change. The input coding can be either straight binary or 3 decades of
8421 BCD with only simple connector jumpers required to take care of the
change.
268
The A613 requires a -10.Ov reference that can supply negative current,
such as an A704. Provisions are made for adding up to 3 extra resistors to
implement offsetting functions. Potentiometers are provided for zero balancing, and gain trim.
An input of all Logic O's produces zero volts out; all Logic I's produces close
to +IOv out. The operational amplifier output can be shorted to Ground
without damaging the circuit.
SPECIFICATIONS
Inputs
Logic ONE:
Logic ZERO:
Input loading:
+2.0V to +5.0V
O.OV to +0.8V
I mA (max.) at 0 Volts
Output
Standard:
Optional, (requires
Positive REF)
Settling time, (IOV step):
Output current:
Capacitive loading:
Binary Dig. In.
000 - 00
000 - 01
100-00
111-11
OVto +IOV
10v range between -lOVand +lOV
50 ....sec
10 mA
0.1 p.F (without oscillation)
Analog Out
O.OOOOv
+0.0025
+5.0000
+9.9975
Accuracy
At +25C:
Temp. coef:
BCD (8421)
000
001
050
500
999
Binary
O.OOl%/oC ..
(plus drift of REF)
Analog Out
O.OOOv
+0.010
+0.500
+5.000
+9.990
BCD
0.05% of full scale
0.002%/oC
(plus drift of REF)
Temperature Range
+lOC to +50C
If the Output is accidentally shorted to Ground, the output amplifier will not
be damaged.
269
DIGITAL TO
ANALOG
A618 AND A619

10BIT D/ A CONVERTER
SINGLE BUFFERED
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
A618-$300
A619-$325
BINARY WEIGHTED NETWORK
r - INTL I +V REF
~BP.
.EXT
+V REF
0- --<)--..J\JI\II,,-----,
~~~L
_ _ _ _ _ _.JI
Power
Volts
mA.(max.)
+15
GND
25"
135
LOGIC
ANALOG
-15
85"
ct~D
-10.06
60
Pins
BV2
AA2
AC2
BT2
BR2
BU2
ref
plus output loading
The A618 and the A619 Digital to Analog Converters (DAC)are double width in
the lower (B section) half. The converters are complete with a 10-bit buffer
registers, level converters, a precision divider network, and a current summing amplifier capable of driving external loads up to 10 mAo The reference
voltage is externally supplied for greatest efficiency and optimum scale
factor matching in multi-channel applications.
The A619 DAC output voltage is bi-polar while the A618 DAC output voltage
is uni-polar.
Binary numbers are represented as shown (right justified) in Table 1:
270
TABt.E 1
Analog Output (Standard)
Binary Input
A619
A618
-sv
OV
+2.SV
+S.OV
+7.SV
OOOOR
0400 8
10008
1400 R
1777 8
-2.SV
oVolts
+2.5V
+10.0V
+5V
SPECIFICATIONS
OUTPUT:
Voltage: A618
Voltage: A619
Current:
Impedance:
Settling Time:
(Fu" scale step, resistive load)
(Fu" scale step, 1000 pf)
Resolution:
Linearity:
Zero Offset:
Temperature Coefficient:
Temperature Range:
o to +10 volts
S volts
10 mAo (max)
<0.1 ohm
<S.O
f,tS
<10.0 f,tS
1 part in 1024
O.OS% of full scale
5 mY. (max)
<0.2 mV/oC
o to 50C
INPUT
Level: 1 TTL Unit Load
Pulse:
(positive)
, Input loading: 20 TTL Unit load
Rise and Fa" Time:
Width:
Rate:
Timing:
20 to 100 nsec
>50 ns
106 Hz max.
Data lines must be settled 40 ns before the "LOAD DAC" pulse (transi
tion) occu~s.
271
DIGITAL TO
ANALOG
A620 AND A621

10-BIT D/ A . CONVERTER
DOUBLE BUFFERED
A SERIES
Price:
Length: 'Standard
Height: Double
Width: Double
A620-$300
A621-$375
28
26
2!5
24
23
22
21
20
10-81T REGISTER
BINARY WEIGHTED NETWORK
r-INii-
Volts
+15
ct~D
GND
-10.06-
-15
~BP.
I +v R
I C>---~--AJVv------,
EXT
+V REF
~~2!!.L:!
Power
mA (max.)
25--
190
LOGIC
ANALOG
60
85"
______
...J
Pins
BV2
AA2
AC2
BT2
BR2
BU2
- ref.
- - plus output loading
The A620 and the A621 Digital-to-AnalogConverters (DAC) are double-width in

the lower (8 section) half. The converters are complete with two 10-bit buffer
registers, level converters, a precision divider network, and a current summing amplifier, capable of driving external loads up to 10 rnA_ The reference
voltage is externally supplied for greatest efficiency and optimum scale-factor
matching in multi-channel-application.
The A621 DAC output voltage is bi-polar while the A620 DAe output voltage
in uni-polar.
272
The double-buffered DAC's are offered to satisfy those applications where it

is imperative to update several analog output simultaneously_ When DAC's
deliver input to a multi-channel analog tape system or update the constants
of an analog computer, the doublebuffer feature may be necessary to prevent
skew in the analog data.
Binary numbers are represented as shown (right justified) in Table 1:
TABLE 1
Analog Output (Standard)
Binary Input
00008
04008
10008
14Q0 8
1777R
A620
A621
OV
+2.5V
+5.0V
+7.5V
+10.0V
-5V
-2.5V
-0 Volts
+2.5V
+SV
SPECIFICATIONS
OUTPUT:
Voltage: A620
Voltage: A621
Current:
Impedance:
Settling Time:
(Full scale step, resistive Load)
(Full scale step, 1000 pf)
Resolution:
Linearity:
Zero Offset:
Temperature Coefficient:
Temperature Range:
o to 10 Volts
5 Volts
lOrnA. (max)
<0.1 ohms
<5.0 tJ.s
<10 J4s
1 part in 1024
0.05% of full scale
5 mY. (max)
<0.2 mV/oC
o to 50C
INPUT:
Level: 1 TTL Unit load
Pulse:
(positive)
Input loading:
20 TTL Unit load
Rise and Fall Time:
20 to 100 ns
Width:
>50 ns
106 Hz (max)
Rate:
Timing:
1. Data lines must be settled 40 ns before the "LOAD DAC" pulse
(transition) occurs.
2. The "Update DAC" pulse must occur more than 100 ns after the
':LOAD DAC" pulse.
273
DIGITAL TO
A660
ANALOG
12BIT MULTIPLYING
D/A CONVERTER
A SERIES
Length: Standard
Height: Double
Width: Double
211
A AJ'
Price:
$500
2tO
2'
ANLG
REF V
INPUT
MULTIPLYING OAC
o
Volts
Power
rnA (max.)
+15
+5
25
-15
25
GND
GND
45
LOGIC
ANALOG
20
ANLG
OUT
AHI A
=ANALOG SIGNALS
(DO NOT CONNECT TO
LOGIC LEVELS)
Pins
ADl, AD2
AAl, AA2, BAl, BA2
AC2, BC2
AFl, AF2
AEl, AE2
The A660 is a precision 12 bit multiplying digital to analog converter whose

output is the product of the external analog reference voltage supplied and
digital code presented.
This 0/ A Converter is OIL and TTL compatibie, requires essentially zero
warmup time. It also may be used in either unipolar or bipolar operations.
This unit may be used in applications where precision digital control must
be exercised over an analog signal. It also may be used in systems requiring synchro to digital conversion, AC transducer digitization, or in hybrid
computation.
.
When operating in conjunction with an external DC reference source, the
A660 may be used as a conventional D/ A converter with the output polarity
determined by the reference voltage polarity.
The A660 employs advance shielding techniques which allow proper operation under normal ambient electrostatic and electromagnetic conditions.
274
SPECIFICATIONS
Number of Bits:
12
Coding:
Binary-Absolute Value
Input Logic Levels:
High
Logic One
I TTL Load
Accuracy-( dc to 4 kHz)
.025% FS, 0.01 % of output
200 microvolts/ o C.
Temp. Coefficient of Range:
20 PPM/ o c.
Feedthrough (for 20 V. p.p sine /

wave; all bits off):
at 1
Analog Reference Input Range:
10 v. Full Scale
KH~:
1 mV RMS
Input Impedance:
10 k ohms
Frequency:
Down 0.02% at 20 kHz
Phase Shift:
<7
at 20 kHz
Output Range:
10 V.
Output Current:
15 mAo
Short Circuit Protection:
Indefinitely to ground
Phase
Output in Phase with Ref.
Attenuation Range-Absolute Value

OUTPUT
DIGITAL
000
000
000
000
0.0000 Volts
111
111
111
111 Binary
(0.9976) X (Input Ref.) Volts

10ms.
Settling Time to Digital Change:
275
DIGITAL TO
ANALOG
A661
12-BIT BCD MULTIPLYING
D/A CONVERTER
Length:
Height:
Width:
A SERIES
Price:
Standard
Double
Double
$500
BCD
MULTIPLYING OAC
ANALOG
OUTPUT
AHt A
1--.....~--tANALOG
GND
-ANALOG SIGNALS
DO NOT CONNECT TO LOGIC LEVELS
Volts
Power
mA (max.)
+15
+5
25
45
-15
25
GND
GND
LOGIC
ANALOG
Pins
ADl,
AAl,
AC2,
AFl,
AEl,
AD2
AA2, BAl, BA2
BC2
AF2
AE2
Exclusive of load.

This 0/ A converter is OTl and TTL compatible, requires essentially zero
This unit may be used in applications where precision digital control must be
exercised over an analog signal. It also may be used in systems requiring
synchro to digital conversion, ac transducer digitization, or in hybrid computation.
When operating in conjunction with an external dc reference source, the
A661 may be used as a conventional D/ A converter with the output polarity
The A661 employs advanced shielding techniques which allow proper operation under normal ambient electrostatic and electromagnetic conditions.
276
SPECIFICATIONS
Number of Bits:
12
Coding:
BCD-Absolute Value
Input Logic Levels:
High
Logic One
1 Unit TTL Load
Accuracy (de to 4 kHz):
.025% FS 0.01 % of Reading
Temperature Coeff. of Offset:
200 Microvolts/oC
Temperature Coeff. of Range:
20 PPM/oC
Feed through for (20V p.p sine

@ 1 kHz: ImV RMS
10V Full Scale Min.
Input Impedance:
> 10k ohms
Frequency:
Down less than 0.02% @ 20 kHz
Phase Shift:
< 7
Settling Time for -F.S. to +F.S.

Digital Increment:
12 p'sec to .015% of FSR
@ 20 kHz Maximum
Output Range:
10 Volts (min)
Output Current:
15 rnA (min)
Short Circuit Protect.:
Indefinitely to Ground
Phase:
Output in Phase with Reference

DIGITAL
OUTPUT
000 000 000 000

III III 111 III Binary
0.0000 volts
(0.9990) x (input ref.) volts
277
DIGITAL TO
ANALOG
A662
1281T 2'5 COMPLEMENT
D/A CONVERTER
Height:
Length:
Width:
A SERIES
Standard
Double
Double
2'1
Price:
$500
2 '0
29
28
27
26
25
24
23
22
2'
(MSB)
2'S COMPLEMENT
~-"'--II
20
(LSB)
MULTIPLYING
___ ANAL.OG
OAC
ANALOG
OUTPUT
AHI A
GNO
=ANALOG SIGNALS
(DO NOT CONNECT TO LOGIC LEVELS)
Volts
+15
+5
GND
GND
-15
Power
mA (max.)
25*
LOGIC
ANALOG
25*
* Exclusive
Pins
AD1, AD2
AAl, AA2, BAl. BA2
AC2, BC2
FI, AF2
AEI, AE2
of load.

This Df A converter rs OTl and TTl-compatible, requires essentially zero
This unit may be used in applications where preCision digital control must be
exercised over an analog signal. It also may be used in systems requiring
synchro to digital conversion, ac transducer digitization, or in hybrid computation.
A662 may be used as a conventional Of A converter with the output polarity
The A662 employs advanced shielding techniques which allow proper operation under normal ambient electrostatic and electromagnetic conditions.
278
SPECIFICATJOIIIS
Number of Bits:
12
Coding:
Binary, 2's Complement
Input Logic Levels:
High
Logic One
1 Unit TTL Load
Accuracy-(dc to 4 kHz):
Temp. Coeff. of Offset:
200 Microvolts/oC
Temp. Coeff. of Range:
20 PPM/oC
Feedthrough for 20V pop sine wave:

(all bits off)
@ 1 kHz: 2mV RMS
10V Full Scale Min.
Input Impedance:
> 10k ohms
Frequency:
Phase Shift:
< 7

Digital Increment:
12.uS to .015% of FSR
Output Range:
Output Current:
15 mA
@ 20kHz Maximum
10 Volts
Indefinitely to Ground
Phase:
Output Phase Depends on Bl .
Attenuation range-bipolar
OUTPUT
(-1) X (Input Ref.) Volts
0.0000 Volts
DIGITAL
100 000 000 000
000 000 000 000
011111111111
279
A663
DIGITAL TO
12BIT STRAIGHT BINARY

D/ A CONVERTER WITH BUFFER
A SERIES
ANALOG
Price:
Length: Standard
Height: Double
Width: Double
+5V
$585
10K
10K
10K
p~=-~--+----a~~
.~~________~OOUN~T~
BUFFER COUNTER
~--~~~~--~~-r~~~~~--~
DIGITAL
OUTPUTS
211 2'0 29
27
28
26
25
24
23
22
2'
(MSB)
20
(LS8)
MULTIPLYING DAC
ANALOG
OUTPUT
AHI A
~ .~NA~~ 10 LOGIC LEVELS

Volts
Power
mA (max.)
GND
GND
LOGIC
ANALOG
+15
+5
25
125
-15
25
Pins
AD1,
AA1,
AC2,
AF1,
AE1,
AD2
AA2, BA1, BA2
BC2
AF2
AE2
Exclusive of Load

digital code presented. A 12 bit Buffer Counter provides input to the 0/ A
Converter and external digital outputs.
This 0/ A Converter is OTL and TTL compatible, requires essentially zero
warmup time. It also may be used in eit~er unipolar or bipolar operations.
280
This unit may be used in applications where precision digital control must
be exercised over an analog signal. It also may be used in systems requiring
synchro to digital conversion, ac transducer digitization, or hybrid com
putation.
A663 may be used as a conventional Of A converter with the output polarity
-determined by the reference voltage polarity.
The A663 employs advanced shielding techniques which allow proper oper
ation under normal ambient electrostatic and electromagnetic conditions.
Number of Bits:
Coding:
SPECIFICATIONS
12
Binary - Absolute Value
Input Logic Levels:

Accuracy (dc to 4 kHz):
High
Logic One
200 Microvolts/oC
Temperature Coeff. of Range:
20 PPMfop
Feed through for (20V p.p sine

Input Impedance:
Frequency:
Phase Shift:
Counter Input: (normally high)
@ 1 kHz: ImV RMS
10V Full Scale Min.
> 10k ohms

@ 20 kHz Maximum
Ripple Counter counts once each
time input signal goes low for 0.5
p's (min).
Resets buffer to all lows when signal
goes low for 0.5 p'S (min).
Overides all other digital inputs.
Normally High Level, transfers data
when brought low for 0.5
p.smin
12 p's to .015% of FSR (from low
going edge of the Data Strobe
pulse or Counter In pulse).
< 7
Reset (normally high):
Data Transfer

Digital Increment:
Settling Time for Worst Case
One Count (mid scale):
5 p.sto 0.015% of FSR (from the

low going edge of the counter in
pulse).
Output Range:
10 Volts (min)
Output Current:
15 mA (min)
Indefinitely to .Ground
Phase:
Output in Phase with Reference

DIGITAL
000 000 000 000
111 111111 111 Binary
OUTPUT
0.0000 Volts
281
REFERENCE
SOURCES
A704
REFERENCE SUPPLY
A SERIES
Price:
Length: Standard
Height: Double
Width: . Single
$184
REGULATOR
-SENSE
-15V
AB2
-,m
lJNREG.
INPUT
OUTPUT
+SENSE
GND
Volts
GND
Power
mA (max.)
250
ANALOG
TI
AE21
AT2 ....
T
I
I
I
I
-15-
AV2
AC21
Pins
AB2
AC2
- pllJS or minus 2 volts
The A704 Reference Supply converts an ordinary -15 volt logic supply
voltage into a precisely adjustable regulated -10 volt reference source for
AID and 0/ A converters of up to l~ binary bits.
FUNCTIONS
Remote Sensing: The input to the regulating circuits of the A704 is connected at sense terminals AT (+) and AV (-). Connection from these points
to the load voltage at the most critical location provides maximum regulation
at a selected point in a distributed or remote load.
When the sense terminals are connected to the load at a relatively distant
location, a capacitor of approximately 100 .uF should be connected across the
load at the sensing point.
Preloading: The supply may be preloaded to ground or -15 volts to change
the amount of current available in either direction. For driving DEC Digital/
Analog Converter modules, -125 mA maximum can be obtained by connecting a 270-ohm plus or minus 5%, one-watt resistor from the reference output (pin AE2) to ground (pin AC2).
282
SPECIFICATIONS
Input Power
-15 V
Use:
See text for sensing and preloading
Output:
-10V
Current:
-90 to +40 mA
Regulation:
0.1 mV, no load to full load
Temperature
Coefficient:
1 mV/8 hrs
1 mV/ 15 to 35 degrees C
4 mV/O to 50 degrees C
Peak-to-Peak
Ripple:
0.1 mV
Adjustment
Resolution:
0.01 mV
Output
Impedance:
0.0025 ohms
283
AS11
10-BIT AI D CONVERTER
ANALOG TO
DIGITAL
A SERIES
Length: Standard
Height: Double
Width: Double (A Section only)
Price:
$350
ANALOG GND
ABN
lK
ANALOG
AID
INPuT
REGISTER
ABV
AND
DAe
START
to AH
tl'olts
+15
+5
GNO
GNO"
-15
Power
mA (max.)
20
300
LOGIC
ANALOG
160
Pins
BU2
AA2
AC2
BN2
AV2
Supply voltages must be regulated to within 1 %.
The ASII is a complete, 10bit successive approximation, analog to digital

converter with a built in reference supply. Conversion is initiated by raising
the Convert input to logiC 1 <+4 volts). The digital result is available at the
output within 10 microseconds. An AI D Done Pulse is generated when the
result is valid. The A-Sll uses monolithic integrated circuits for control logic,
output register, and comparator.
284
100
NANOSECONDS
BIT 10
< ] 1 - - - - - - - - 1 0 /.L S
CONVERT
PULSE
AD Done
PULSE
----~----------------~
BIT
I 10 I
Options:
The input impedance of the AI Dconverter can be raised to greater than 100
megohms by adding an input amplifier module. A sample and hold amplifier
module may also be included. The impedance of the converter with sample
and hold is 10,000 ohms. Both options may be included simultaneously if
high impedance and narrow aperture are both required.
SPECIFICATIONS
Max.
Convert Pulse Input:
Input loading
Pulse Width
Pulse Rise Time
AID Done Pulse Output:
Pulse Width
Digital Output:
Logical "0"
Logical "I"
Output Current "0"
Output Current "1"
Input:
Input Voltage
Input Impedance
Resolution:
Accuracy:
Temperature:
Coefficient:
Operating Temperature:
Conversion Rate:
Output Format:
Min.
10 TTL unit load

500 nsec
'100 nsec
250 nsec
300 nsec
100 nsec
+0.4V
+3.6V
16mA
OV
+2.4V
-d'.4
rnA
o to +10V
1000 ohms
10 bits
0.1 % of full scale
0.5 mV/oC
OC to 50C
100 KHz (max)
Parallel Binary ~ni-polar
285
ANALOG TO
DIGITAL
A860
12BIT INDUSTRIAL AI D CONVERTER
A SERIES
Length: Standard
Height: Double
Width: Double
Price:
$395
A AJ1 AJ2
(+)
OVER RANGE
POLARITY (+ )H
(-)L
AFt ,AF2,AMt,
AM2.AR1,AR2
ANALOG
GND
MSB
INPUT
(t)2V
WORD LENGTH
100Q
II.
BDZ 8
BF28
BKt 1 ~~-l
I
___ .JI
29
A AK1,AK2
A860
ADC
(-)
28
27
AAt
INTL TRIGGER
/IC SYNC (tOVp-p)
r---
I
I
IL ____
A AU2
1 A 2
INTL TRIG ENABLE
AC1AC2
BC1,Be2
DATA
OUT
EXT TRIG
LOGIC GND
END OF CONVERSION
P~S
{5mM
RESET
CLOCK
REMOVE FOR DIFFERENTIAL INPUT

*** --MUST
BE CONNECTED TO ONE OF THE DATA OUT BITS
Volts
+15+5
GND
GND
Power
mA (max.)
20
150
LOGIC
ANALOG
20
Pins
AEI.
BAl.
BCI,
AF1,
ARI,
AEI.
AE2
BA2. AAI. AA2
BC2. ACI. AC2
AF2, AMI, AM2
AR2
AE2
-must be regulated to within 0.3%.
286
An 8
The A860 is a 12-bit (sign

ll-bit magnitude) AID converter using the
dual-slope integrating technique in which the analog input signal is sampled
and integrated for a fixed period of time (about 3 ms). The resulting dc level
is then quantified by integrating an internal reference voltage and counting
the time until the result equals the input sample level. Depending on the
magnitude of the sampled analog voltage, this time is 6 ms or less. Since
the worst case time for integration and conversion is 9 ms, the maximum
useable conversion rate is a little greater than 100 conversions (1200 bits)
per second.
APPLICATIONS
The 860 is especially useful in a noisy industrial environment. Integrating
the analog voltage effectively reduces medium and high frequency ac noise.
The high input impedance of the A860 makes it convenient for applications
using analytical instruments, strain gauges, and resistance bridges.
FUNCTIONS
Start of Conversion: Start of conversion can be controlled externally or can
be selfstarting when the ENABLE INTERNAL TRIG is asserted LOW.
Converted Word Length: The number of bits converted can be controlled by
gating or wiring tfie WORD LENGTH input to an appropriate output bit. (see
WORD LENGTH below)
Connection for Differential Input: The (-) input of the differential analog input is connected to ground through a 100ohm resistor. For a true differential input, remove the resistor but be careful to keep the input common
mode voltage to less than
or - 1.25 volts.
INTL TRIG AC SYNC: The internal trigger will sync on the negative peak of a
10-volt peak-to-peak signal applied to this input. The ac input impedance is
2K ohms nominal.
INTL TRIG ENABLE: Must be LOW to enable the internal trigger .. Must be
HIGH if an external trigger is used .
. EXT TRIG: A negative transition on this input resets the converter and starts
a new conversion.
WORD LENGTH: When BKI is connected to BK2, the word length is maximum (11 bits plus sign). Word length and conversion time can be reduced
by connecting control input BKI to a less significant DATA OUT bit. (However, BKI must be connected to one of the DATA OUT bits.)
Sign Plus Magnitude Coding: The POLARITY bit is HIGH if the analog
input voltage is greater than the (-) input voltage.
(+>
The OVER RANGE bit is LOW if the magnitude of the analog input voltage is
less than 2.0 volts.
The MSB bit is LOW jf the magnitude of the analog input voltage is less than
1.0 volt.
The binary magnitude of the analog input voltage is present on the MSB and
DATA OUT lines when the END OF CONVERSION signal goes LOW.
END OF CONVERSION: Goes LOW when a conversion is complete. This
signal is HIGH during conversion.
287
SPECIFICATIONS
Accuracy at 23 degrees C:
Error less than 0.05% of input

voltage 1 mV
Conversion Time:
Less than 9 ms
Sample Aperture Time:
3 ms max. (part of conversion time)
Analog Input Voltage Range:
+2 Vto -2 V
DC Input Impedance:
1000 megohms minimum
Common Mode Rejection:
70 dB min. de to 60 Hz
Common Mode Voltage Limit:
+1.25 V or -1.25 V
(average of both input voltages
with respect to analog ground)
Analog Input Voltage Limit:
+2.25 V or -2.25 V
(either input with respect to
analog ground)
Internal Trigger Rate:
2 per second nominal
AC SYNC Voltage:
.10 volts ac 1 V with allowable de

offset of 2 V
288
ANALOG TO
DIGITAL
A861
HIGH SPEED 12-81T
UNIPOLAR AID CONVERTER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$595
SERIAL OUT
A AJ2
ANALOG INPUT
BEt 8
Bl
MS8
B1
82
A AFt
83
ANALOG GND
B4
B5
DATA
OUT
TRIG
IN
B6
B7
B8
TRIG
ENABLE
89
810
BU
LSB
CLOCK
ADJ.
WORD LENGTH
BV1 1
END OF
8Ft B
CONVERSION
201<
BBt
TEST
Volts
GND
GND
START
AUt 1
CLOCK
BOt t
-15
Power
mA Pins
55
420
LOGIC
ANALOG
12
ADl,
AA2,
AC2,
AFl,
AEI.
289
--
BHt t
r~T
*=MUST
BE CONNECTED TO ONE OF THE
OATA OUT BITS.
+15
+5
---,
812
AD2
BA2, Ml, BAI
BC2, ACl, BCl
AF2, AK2
AE2
___ J1*
,TheA861 provides up to 12 bits oLadjustment-free anaklg to digital CORversion in the range from 0 to +io volts., The A86J uses the fast successive
approximation technique, is complete with an internal reference voltage, and
includes a selfcontained adjustable clock that allows control of the conversion time from 12 to 48 microseconds. Analog and digital ground returns
are separate to minimize potential ground loop problems. Advanced shielding
techniques make the A861 relatively immune to ambient electrostatic and
electromagnetic cond itions.
APPLICATIONS
Computer Interfacing
Biomedical Data Conversion
Process Control Systems
Instrumentation Data Conversion
SPECIFICATIONS
o to +10 volts
Analog Signal Input Loading:
2.5K returned to +5 volts
Conversion Time:
Adjustable from 12 to 48 p's
Resolution:
12 bits
Accuracy vs Speed @ 23C:
0.01 % of FS @ 48 p's conversion

0.015% of FS @ 24 ,u.s conversion
0.05% of FS @ 12 ,u.s conversion
References:
Internal +5V and +10V (adjustable)
0.001 % of FS per degree C
Temperature Coeff. of Gain:
12 ppm per degree C
SERIAL DATA:
NRZ code, available during

conversion
DATA OUT:
12 bits of parallel data and the

complement of the MSB are '
available 250 ns after the END
OF CONVERSION goes HIGH.
CODE:
Straight Binary
WORD LENGTH:
Must be connected to the DATA OUT

bit the user wants to be the LSB
TRIG ENABLE:
A HIGH on this input and a negative

transition on the TRIG IN starts
the conversion
TRIG IN:
A negative transition on this input

and a HIGH on the TRIG ENABLE
starts the conversion
"
Multi-turn pot to control conversion
time from 12 p.S to 48 ,u.S
Clock Adjust:
290
ANALOG TO
DIGITAL
A862
HIGH SPEED 12-BIT

BIPOLAR AID CONVERTER
A SERIES
Price:
Length: Standard
Height: Double
Width: Double
$595
SERIAL OUT ...................;:B=E~1 8
A AJ2
81 l>-......~=I
ANALOG INPUT
MSB
B1
~.......-lI!!..~
B2 1---.--==-1
A ~A..;.;,..F...;..t-"---~ANALOG GND
B3 ..................::.:;=1
B4 ......-......--~
B5 ..............--=::*1
TRIG
IN
DATA
B6 ......-............=:.::~
OUT
B7 ..............-=..:..-=1
B8 .................:.:..;=1
TRIG
B9......-..........:QIi!::..I
ENABLE
B10 ..............-=.=.f
Bl1~......-=~
LSB
Bt2 ..............-=.=.f
WORD LENGTH~-4-"':':'~
END OF
8Ft
CONVERSlON~"""-=-~8
CLOCK
ADJ.
TEST
{:~::~ ~ -=.;:.: :~
......
CLOCK ..............-=~
*. MUST
8E CONNECTED TO ONE OF THE
DATA OUT 8ITS.
Volts
Power
mA Pins
+15
+5
55
420
-15
12
GND
GND
ADl,
AA2,
AC2,
AFl,
AEl,
LOGIC
ANALOG
291
AD2
BA2, AA1, BAI
BC2, ACl, BCl
AF2, AK2
AE2
---,1*
___ J
The A862 provides up to 12 bits of adjustment-free analog to digital conversion in the range from -10 to +10 volts. The A862 uses the fast successive approximatlon technique, is complete with an internal reference
voltage, and includes a self-contained adjustable clock that allows control of
the conversion time from 12 to 48 microseconds. Analog and digital ground
returns are separate to minimize potential ground loop problems. Advanced
shielding techniques make the A862 relatively immune to ambient electrostatic and electromagnetic conditions.
APPLICATIONS
Computer Interfacing
Biomedical Data Conversion
Process Control Systems
Instrumentation Data Conversion
SPECIFICATIONS
-10 to +10 volts
Analog Signal Input Loading:
5K returned to +5 volts
Conversion Time:
Adjustable from 12 to 48
Resolution:
12 bits
Accuracy vs Speed at
23 degrees C:
0.01 % of FS @ 48 JLS conversion

0.015% of FS @ 24 JLS conversion
0.05% of FS @ 12 JLS conversion
References:
Internal +5V and +10V (adjustable)
0.001% of FS per degree C
JLS
Temperature Coeff. of Gain:
12 ppm per degree C
SER.AL DATA:
NRZ code, Offset Binary available

during convers;on
DATA OUT:
12 bits of parallel data and the

complement of the MSB are
available 250 ns after the 'END
OF CONVERSION goes HIGH.
CODE:
Offset Binary: use the MSB

2's Complement: use the complement of the MSB
WORD LENGTH:
Must be connected to the DATA OUT

bit the user wants to be the LSB
TRIG ENABLE:
A HIGH on this input and a negative

transition on the TRIG IN starts the
conversion
TRIG IN:
A negative transition on this input

and a HIGH on the TRIG ENABLE
starts the conversion
Clock Adjust:
Multi-turn pot to control conversion

time from 12 JLS to 48 JLS
292
A990, A992
AMPLIFIER BOARDS
AMPLIFIERS
A SERIES
Price:
Length: Standard
Height: Single
Width: Double (typ. amp.)
A990-$4
A992-$4
Many types of commercially available operational amplifiers can be mounted

in the holes provided on these predrilled etched boards. Mounting holes and
printed wires provide for balance trim, gain trim, and feedback networks required to build such common operational devices as voltage followers,
inverting or non-inverting amplifiers, integrators, differentiators, summers and
subtractors. Most amplifiers listed in the table below require 15 V regulated
supplies which are readily available from the amplifier manufacturers. Notable
exceptions are Analog Devices' Models 101, 103, and 104 which may be used
with standard DEC +10V, -15V supplies at some sacrifice in voltage range
(+5, -10V) and noise.
Power: Positive at pin Dr negative at pin E, common at pin F for all types.
Space is provided for mounting bypass capacitors used with some high
frequency amplifiers.
Trimming: Mounting holes on I" centers at the handle end accept wirewound
potentiometers for balance and feedback (gain) trimming. Gain rheostat
may be connected in series with feedback components to allow precise adjustment of gain using inexpensive 1 % feedback resistors. Board is etched
293
-to allow for use without gain trimming, and one pointed conductor must be
cut at caret marks to put a rheostat in the circuit. Gain rheostat stray capacitance to ground is driven by amplifier output.
Types accepted
by A990
Amplifier Supplier
Analog Devices
Burr-Brown*
Data Device Corp.
Nexus
Philbrick
Union Carbide
Zeltex
Types accepted by
A992 (boosters too)
101, 102, 104, etc.

1500-15,15C 1500-25
103, 106, 107, etc.
most types, except boosters

Case Q
Case PP
most types
Case A
Case K or Case L
"'Except Burr-Brown differential output and chopper stabilized types: Perforated board W994 or other blank module may be used to mount non'
standard configurations.
FO~--------------~OF
.. 5>l,
VOLTAGE FOLLOWER (NON-INVERTINGl
DIFFERENTIATING
CAPACITOR
GAIN
IGH -FREQUENCY
ROLL -OFF NETWORK
DIFFERENTIATING
RESISTOR
S~
T
o-----------~----------~F
DIFFERENTIATOR WITH OOUBLE BAND STOPS
INVERTING AMPLIFIER
:~ ljf>-----"---<J::
v
Fo---~----------~
FOUR-INPUT SUMMER
NON-INVERTING AMPLIFIER
:?~~::
INTEGRATOR
RI
U o----.JVo".,....-'---j
MATCHING TRIMMER CAN BE

_ _ USED TO OPTIMIZE COMMONMOOE REJECTION ALSO
AFFECTS GAIN
RI
R2 PLUS
112 RT
o--~----------------~F
SUBTRACTOR AND COMMON-MODE REJECTOR
294
DEC offers a wide line of wire wrappable, collage, and blank modules in the
FLIP CHIP form factor for experimenting and breadboarding by users who
want to work directly with discrete components and integrated circuit pack
ages. Included in this section are module extenders and PDP8/ e, 8/ m
OMNIBUS bus connectors.
295
W940-W943, W950-W953
WIRE WRAPPABLE MODULES
ACCESSORY
MODULES
W94l
W940
These wire wrappable boards with wire wrappable pins wi" accommodate
dual-in line, IC's. Two separate leads of 30-gauge may be wire wrapped to each
pin. A" boards have accommodations for 14 and/or 16 pin dual-in line IC's.
However, the W950, W95l, W952 and W953 boards also have accommodations for 24 pin dual-in-line IC's. Some boards are supplied with low profile
IG sockets. The boards are designed to offer customer flexibility by providing
additional pin locations for mounting discrete components,such as transistor
sockets and potentiometers. These boards offer the user such advantages as
easy construction of prototypes and low cost limited production runs. The
following table describes each individual module:
MODULES W940, W942
W950, W952
<E-<E-- {
MODULES W94l, W943

W95l, W953
~
AA2, BA2, CA2, DA2, - - + 5

AC2, ATl, BC2, BTl} -GND
CC2, CTl, DC2, DTI
297
AA2, BA2 - - + 5
AC2, ATI } -GND

BC2, BTl
MODULE CONNECTOR SIZE

PINS
DESCRIPTION
PRICE
W940
144
Entended length Accommodates up to 50

Quad height
14 and/or 16 pin IC's
with or without sockets.
(sockets not included)
$70.00
W941
72
Entended length Accommodates lip to 25

Double height
14 and/ or 16 pin IC's'
with or without sockets.
(sockets not included)
$40.00
W942
144
Entended length Contains low profile IC

Quad height
sockets. Accommodates
up to 50 14 and/or 16
pin IC's
$140.00
W943
72
Entended length Contains low profile IC

Double height
sockets. Accommodates
up to 25 14 and/ or 16
pin IC's
$75.00
W950
144
Entended length Has 30 14 and/ or 16 pin

Quad height
type accommodations.
Also contains 8 24 pin
type accommodations
that can also accommodate 14 and! or 16 pin
IC's. IC's may be
mounted with or without
sockets (sockets not
included).
$65.00
W951
72
Entended length Has 15 14 and/ or 16 pin

Double height
type accommodations.
Also contains 4 24 pin
type accommodations
that can also accommodate 14 and! or 16 pin
IC's. IC's may be
mounted with or without
sockets (sockets not
included).
$40.00
W952
144
Extended length Contains 30 16-pin lowprofile.IC sockets that

Quad height
can accommodate 14pin or 16-pin IC's. Also
contains eight 24-pin
low-profile IC sockets
that can accommodate
24-pin IC's as wen as
14-pin or 16-pin IC's.
$140.00
298
W953
72
Extended length
Double height
299
Contains 15 16-pin lowprofile IC sockets that

can accommodate 14pin or 16-pin IC's. Also
contains four 24pin
low-profile IC sockets
that can accommodate
24-pin IC's as well as
14-pin or 16-pin IC's.
$75.00
, W960
MSI MOUNTING BOARD
ACCESSORY
MODULES
The W960 is a single-height, standard-length, double-sided PC board that can

accommodate either two 14 or 16 pin dual-in-line IC's, or one 24 pin dual-inline IC with or without socket(s). All IC pins are brought out to connector pins.
W960-$8
300
W964
UNIVERSAL TERMINATOR BOARD
ACCESSORY
MODULES
Typical Circuit Configuration.

The W964 is a blank, etched and drilled module for mounting components
which will provide a variety of termination or voltage source circuits for up
to 28 signal pins. Each signal pin may have two components connected to
ground (pin C2) and one component connected to a common point as shown
in the schematic diagram. The potential of the common point is determined
by components which connect it to pin A2 andj or pin 82. The schematic
diagram shows the physical layout of this section as well as the electrical
connections.
Any components can be mounted on the board provided the physical size is
similar to a Ih -watt resistor or disk capa~itor.
The W964 may be used to terminate single lines, for mounting pull-up resistors, for open-collector devices or to provide various output voltages via
voltage-divider networks.
Single height, single width.
Current depends on components used.
Pin assignments:
Output/Input
(28)
BI, 01, EI, Fl, HI, JI,

KI, LI, MI, NI, PI, RI, 51
02, E2, F2, H2, J2, K2, l2, M2,
N2,P2, R2,S2, T2, U2,V2

Voltage
GND
A2, E2*
C2
In many systems. pin 82 is bussed to -15 V de.
W964-$8.00
301
W966, W967
ACCESSORY
MODULES
WIRE WRAPPABLE MODULES
W967
W966
The W966 is the 8/ e collage mounting board. It is double sided, extended

length, and quad he!ght with wire wrappable pins. It will accommodate 14
and! or 16 pin dualinline IC's with or without 16 pin sockets. Two separate
leads may be wire wrapped to each pin. Up to 42 IC's can be mounted on
the W966. Discrete components may be directly soldered onto the board.
The top center of the W966 board has 72 terminal fingers with terminating
wire wrap pins. An I/O connector (male) terminating in wire wrap pins is
mounted on the left side of the W966 board to provide access to the "outside
world" when using BC08JXX cable with a double sided connector board or a
BC08KXX single sided connector board. Both connector boards have 18
conductor lines.
All power and ground lines are common to the 8/E"OMNIBUS".
~--
ACl,
BCl,
CCl,
OCl,
AC2,
BC2,
CC2,
OC2,
AA2, BA2, CA2
---+5
AFl, AF2, ANI, AN2, ATl, AT2j-GNO

BFl, BF2, BNl, BN2, BTl, BT2
CFl,CF2,CNl, CN2,CTl,CT2
OFl, OF2, ONl, ON2, OTl, OT2
The W967 is similar in aI/ details to the W966 except that the W967 is supplied with 42 low profile IC sockets.
W966- $85
W967-$165
302
W968, W969
COLLAGE MOUNTING BOARDS
W968
ACCESSORY
MODULES
W969
The W968 and W969 collage mounting boards will accommodate 14 and/ or
16 pin dual-in line IC's with or without 16 pin wire wrap sockets and/ or solder
sockets_ The W968 is a double-sided, quad-height, extended length board
and can accommodate up to 72 IC's.
The W969 is the double-height version of the W968 and can accommodate
up to 36 IC's. Among the unique uses of the collage boards are that they
facilitate construction of prototypes and production of limited runs.
W969
W968
oE--oE--- {
AA2, BA2, CA2, DA2
-+5
+ - - - AA2, BA2
AC2, AT1, BC2, BTl} -GND

CC2, CTl, DC2, OTI
oE--- {
--+5
AC2, ATl } -GNO

BC2, BTl
W968-$45
W969-$30
303
W970-W975, W990-W999
BLANK MODULES
MODULES
W992
W990
ACCESSORY
W998
These 10 blank modules offer convenient means of integrating special circuits

and even small mechanical components into a FLIP CHIP system, without loss
of modularity. Both single and doublesize boards are supplied with contact
area etched and gold plated. The W990 Series modules provide connector pins
on only one module side for use with HSOO connector blocks. W970 series
modules have etched contacts on both sides of the module for use with
double density connectors Type HS03, and low density Type HSOS.
Module
Con
nector
Pins
Size
Handle
Description
Price
W970
36
Standard
length
Single
height
Attached
Bare board, no split lugs,

similar to W990.
$ 4.00
W971
72
Standard
length
Double
height
Attached
Bare board, no split lugs,

similar to W991.
$ S.OO
W972
36
Standard
length
Single
height
Separate
Copper clad, simiiar

to W992.
$ 4.00
W973
72
Standard
length
Double
Separate
Copper clad, similar

to W993.
$ 6.00
Attached
Same as W998, contact

both sides.
$ 9.00
h~ight
W974
36
Standard
length
Single
height
304
Module
Connector
Pins
Size
Handle
Description
Price
W975
72
Standard
length
Double
height
Attached
Same as W999, contact

both sides.
$18.00
W990
18
Standard
length
Single
height
Attached
Bare board, split lug

terminals.
$ 2.50
W991
36
Standard
length
Double
height
Attached
Bare board, split lug

terminals.
$ 5.00
W992
18
Standard
length
Single
height
Separate
Copper clad, to be
etched by user.
$ 2.00
W993
36
Standard
length
Double
height
Separate
Copper clad, to be
etched by user.
$ 4.00
W998
18
Standard
length
Single
height
Attached
Perforated, 0.052" holes, $ 4.50

18 with etched lands. The
holes are on 0.1" centers,
both horizontally and
vertically.
W999
36
Standard
length
Double
height
Attached
Perforated, 0.052" holes,

36 with etched lands. The.
holes are on 0.1" centers,
both horizontally and
vertically.
305
$ 9.00
".W972, W973,.W992, . . W993
ACCESSORY
BLANK COPPER ClAD MODULES

I,~"---2,~
1,
3-1
MODULES
1~-------------5~--------------~1
0,
W992
W993
Type W992 and W993 are single side copper clad boards. The diagrams above
indicate the copper clad area that is usable for etching purposes. The
identifying numbers are etched from the clad using a minimum of etchable
area. Type W972 and W973 are equivalent to the above types but have copper
clad on both sides.
W972-$4
W973-$6
W992-$2
W993-$4
306
W979
COLLAGE MOUNTING BOARD
ACCESSORY
MODULES
The W979 Collage Mounting Board will accommodate 14 and/or 16 pin dualin-line IC's with or without 16 pin wire wrap sockets and/ or solder sockets.
It is the double-height, standard-length version of the W969.
W979- $20
307
W980
MODULE EXTENDER
ACCESSORY
MODULES
The W980 Module Extender allows access to the module circuits without
breaking connections between the module and mounting panel wiring.
For double size flip-chip modules use two W980 extenders side by side. The
W980 is for use with A, K and W Series 18 pin modules.

W980-$14
308
W982
MODULE EXTENDER
ACCESSORY
MODULES
The W982 serves a function similar to the W980 except it contains 36 pins
for use with M series modules. The W982 can be used with all modules in
this catalog. A, K, and W series modules will make contact with only 2 side
pins. A2, 82, etc.
W982-$18
309
"M920.iAND M935
BUS CONNECTOR MODULES
ACCESSORY
MODULES
UNIBUS Jumper Module M920-The M920 Module is a double module that

connects the UNIBUS from one system unit to the next. The printed circuit
cards are on one-inch centers. A single M920 Module carries all 56 UNIBUS
signals and 14 grounds.
M935 Bus Connector-used to interconnect ale assemblies. The H9190 may
be connected to the ale OMNIBUS using two M935's.
M 920-$45. 00
M935-$45.00
311
All DEC modules are exhaustively inspected and tested, both

visually and electronically. A typical module undergoes a printed
circuit board inspection procedure that consists of over 70 indio
vidual steps.
312
Power supplies for both large and small systems and reference supplies are
available.
Each of the power supplies with a frequency-sensitive regulating transformer
is available in a multi-voltage 50-cps version. All 50-cps supplies have the
same input connections. The line input is on pins 3 and 4. Jumpers should
be connected depending on the input voltage. These connections are shown
with a schematic.
313
POWER SUPPLIES & ACCESSORIES SUMMARY

+5V POWER SUPPLIES (POSITIVE LOGIC USE)
..
Part No.
Input Specs
Output Specs
H710
105-125 Vac
210-250 Vac
(47-63 Hz)
5 Vdc @ 5A
1 % Regulation
Dimensions
5 1,4"
x8" x 6"
Remarks
Price
Short Circuit Proof

Floating Output
Remote Sensing
Over-Voltage Protection
Parallel Operation
$180.00
714
120/240 Vac
(47~500 Hz)
+5Vdc @ 7A
1 % Regulation
5" x 6" x 6"

Flat Surface
Mount
Floating Output
Short Circuit Proof
Parallel Operation
$200.00
H716
120/240 Vac
(47-63 Hz)
+5 Vdc @4.0A
3% Regulation
-15 Vdc @ 1.5A
5% Regulation
5 1.4" x4Vs" x 123,4"

Type H021
Mounting Frame
Floating Output
Short Circuit Proof
Parallel Operation
for +5 Vdc Output
$150.00
+5 Vdc @ 7.0A
1 % Regulation
16 112" x 2 1,4" x 6 112"

Panel Mounted
Floating Output
Short Circuit Proof
Parallel Operation
$200.00
H726
120/240 Vac
(47-500 Hz)
---
-_ _-..
----
--
+lOV, -5V SUPPLIES (NEGATIVE LOGIC USE)

Part No.
H701
H701A
....
U'I
OJ
Input Specs
Output Specs
Same as H701
782A
Same as H701A
Same as
H701
728A
Same as
H701A
783
Same as
H701
783A
Chassis Mounted
8" x 5" x 5 3/4"
Floating Output
Parallel Operation
$136.00
Panel Mounted
19" x 5" x 5 3/4"
Same as
H701, H701A
$128.00
Chassis Mounted
160/8" x 8 3/4" x 5%"
Same as
H701, H701A
$240.00
Panel Mounted
19" x 8 3/4" x 5 3/4"
Same as
H701, H701A
$240.00
$116:00
-15V@ 3A
+10V @ O.4A
782
728
Characteristics
115V (60Hz)
112.5, 123.5,
195,220, 235V
(50Hz)
Same as
H701A
Price
Dimensions
-15V @ 8.5A
+10V @ 7.5A
Same as
728, 728A
$148.00
$260.00
$260.00
15V POWER SUPPLIES

Part No.
Input Specs
Output Specs
Dimensions
Remarks
Price
H704
105125 Vdc
(47420 Hz)
2/ 15 Vdc
Outputs
@ 400 rnA
.1 % Regulation
3s" x 5IA" x 6%"
215V Floating Outputs

Overload Protection
Remote Sensing
Parallel Operation
$200.00
H707
Same as
H704
2/ 15 Vdc
Outputs
@ 1.5A
.1 % Regu lation
4" x 5" x 5Y2"
Same as H704
$400.00
w
....
en
SPECIAL SUPPLIES AND ACCESSORIES
-..
Part No.
Input Specs
Output Specs
Dimensions
Remarks
Price
K731
Source Module
105-130V Line
12.6 Vac Input
from Power
Transformers
K741 or K743
+5 Vdc @ 1.0A
5% Regulation
Power for Pin A of
K Series Modules
3 Standard
Module Widths
Current Capability
can be increased
using K732
Regulators
$30.00
K732
Slave Regulator
105-130V Line
12.6 Vac Input
from Power
Transformers
K741 or K743
Used with K731 to

Regulate Output
Current
4-Standard
Module Widths
Three K732's
Controlled from One
K731 Extend Output
to +5 Vdc @ 7.0A
$27.00
K741
Power Transformer
120/~40 Vac
(50 or 60 Hz)
12.6 Vac
for K731 or K732
Modules
3lh" x 5"
(Plate)
Can be mounted
using two K943
Mounting Panels
$30.00
K743
Power Transformer
120 Vac
(50-60 Hz)
12.4 Vac @ 2.0A

12.6V for K731
or K732 Modules
5" x 5"
(Plate)
Can be mounted
using two K943
Mounting Panels
$45.00
K771
Display Supply
120 Vac
(50-60 Hz)
Provides Power
for up to Six K671
Display Tubes
2 314" x 2 314" x 4"
....
.......
-------
--
'without K671
Display Tubes
--
----
$35.00
H70l, H70lA, 782, 782A
POWER
POWER .SUPPLIES
+ 10, - 15 VOLTS
i
SUPPLIES
I ~----tJIt--"t--+-......--ot---O+ 10V
~------~~~~~~COMMON
'-----<I-----4~~-__O-15V
The 782 and 782A power supplies are ruggedly built, low cost units that fit
into a standard 19-inch rack. The H701 and H701A are identical to these units,
except they can be mounted on a chassis or panel in applications where space
is added to an existing device. The basic supply can be mounted in various
configurations and is identical to the power supplies used in models 7000
and H900. The Types 782A and H701A are Power Supplies with 50 Hertz
transformers. The Types 782 and 701 are 60 Hertz.
ELECTRICAL CHARACTERISTICS
Input Voltage: H701: ll5 V 60 cps. H701A: ll2.5, 123.5, 195, 220, 235 V,
50 cps. See "50 cps power"
Output Voltage: +10V, -15 vdc, floating
Output Current: -15V:
% to 3 amp; +10V: 0 to 0.4 amp.
Line and Load Regulation: The output voltage remains between -14.5 and
-16.5 V for the -15 output, and within +9.2 and + 11.5 V for the
+10.output, when load varies from minimum to maximum and line voltage
varies 10%.
p.p Ripple: Less than 0.6 V for +10 output. Less than 0.6 V for -15 output;
20% more ripple on the 50-cps type.
Line Frequency Tolerance: 2% of line frequency.
MECHANICAL CHARACTERISTICS
Height: 5-3/4"
Width: 4-15/16"
Length: 8"
finish: Chromicoat
Power Connections: Screw terminals are provided on transformer for input
power conections. Output power connections are made via tab terminals which
fit the AMP "Faston" receptacle series 250, part #41774 or Type 914 power
jumpers. All required mounting hardware is suppli~d with this unit.
H701
H701A -
$116.00
$136.00
318
782
782A
-$128.00
- $148.00
H704, H707
POWER
SUPPLIES
DUAL POWER SUPPLY

15 Volts
H707
H704
These supplies differ only in dimensions and output current capabilities:

400 mA and 1.5 Amperes respectively for the H704 and H707. May be
mounted on the bars in an H920 drawer, taking the space of two COnnector
blocks.
DIMENSIONS: 3%" x 5%" x 6%" height (H704)
DIMENSIONS: 4" x 5" x 5lh" height (H707)
CONNECTIONS: All input-output wires must be soldered to octal socket at
the base of the power supply.
OPERATING TEMPERATURE: -20 to +71 C ambient
319
POWER CONNECTIONS:
Input power connections are made via tab terminals which fit the AMP
"Faston" receptacle series. Output power is supplied to solder lugs. All required
mounting hardware is supplied with this unit. See 914 power jumpers.
Length: 8"
Width: 5"
Height: 6"
Finish: Chromicoat
INPUT VOLTAGE: 105 to 125 vac; 47420 cps.

OUTPUT VOLTAGE: floating 15V .
OUTPUT VOLTAGE ADJUSTMENT: 1 Veach output
REGULATION: 0.05% line, 0.1 % load for both voltages
RIPPLE: 1 mv rms max for both outputs
OVERLOAD PROTECTION: The power supply is capable of withstanding output
short circuits indefinitely without being damaged.
IF REMOTE SENSING IS NOT USED, CONNECT:
4 TO 5 (+15V OUT)
6 TO 7 TO 8 TO 9 (AC GND)
11 TO 11 (-15V OUT)
-15V SENS
+15V SENS
+15V
---~~-.,---15V
+15V
NC
115-125VAC
NEUT
+t5V SENS
---'--~
-15V SENS
-15V
The H704 and H707 contain two 15 Volt floating power supplies. To get 15
Volt supply, connect pins 7 and 8 and use this point as ground. Pin 4 will now
be at positive 15 Volts and pin 11 will be negative 15 Volts.
H704-$200
H707-$400
320
H710
POWER SUPPLY
POWER
SUPPLIES
The H710 power supply is ruggedly b}Jilt, low cost, regulated, floating output,
five volt power supply that can be mounted in an H920 chassis drawer or
used as a free standing unit. Remote sensing to correct for loss due to long
Jines is provided. When shipped from the factory, the remote sensing inputs
are jumpered to their respective outputs. Especially useful in systems that
require maximum repeatability from K303 timers in the millisecond region.
INPUT VOLTAGE: 105-125 VAC
or 210-250 VAC 47-63 HZ
POp RIPPLE:
Less than 20 mv.
OUTPUT VOLTAGE:
5 vdc.
OUTPUT CURRENT:
0-5 amps. shirt-circuit protected for parallel supply operation.
LINE AND LOAD REGULATION:
The output voltage will not vary more than 50 mv over the full range of load
current and line voltage.
OVERVOLTAGE PROTECTION:
The output is protected from transients which exceed 6.9 Volts for more than
10 nsec. However, the output is not protected against long shorts to voltages
above 6.9 Volts.
POWER CONNECTIONS:
Input power connections are made via tab terminals which fit the AMP
"Faston" receptacle series. Output power is supplied to solder lugs. All
required mounting hardware is supplied with this unit. See 914 power
jumpers.
Length: 8"
Width: 5"
Height: 6"
Finish: Chromicoat
H710-$200
321
714
POWER SUPPLY
POWER
SUPPLIES
The Type 714 power supply provides +5 volts at up to 7 amps with overvoltage protection. This supply is ruggedly constructed on a compact
aluminum Ibeam chassis suitable for mounting on any flat panel. Electrical
characteristics are identical to the H726 power supply but the Type 714 does
not include a builtin onoff switch or convenience outlet.
Size: 5" H x 6" W x 6" D. Maximum outside dimension.
Weight: 7 pounds.
Mounting: Four tapped holes, 1032 thread.
Input/Output Connections: Screw terminals on barrier strips accept as large
as No. 16 wire.
ELECTRICAL SPECIFICATIONS
Input: 120/240 V ac, 47 to 500 Hz, normally supplied wired for 120 V ac.
Output: +5 volts with 5 mV rms ripple and noise, max. Line and load regulation combined is 1 % or less.
Temperature Range: _20 0 C to 71
C.
Dissipation: 80 watts maximum.
714-$200
322
H716
POWER SUPPLY
POWER
SUPPLIES
Type H716 provides +5 Volts at 4 amperes and -15 Volts at 1.5 amperes
with over voltage protection for +5 Volts. This dual voltage power supply is
designed to be mounted at the right end of any mounting panel. The supply is ,mounted by using the four holes in the Type H020. The supply takes
2 connector blocks of Type H800, H803, or H808. This provides 48 module
slots with Types H800 and H803, 24 slots with Types H800 and H803 and
24 slots when Type 808 is used:
Maximum Dimensions 5IA" x
4~"
x.123A" deep
Power input via Amphenol 160-5 or equivalent connector with an Amphenol

160-5 or equivalent, in parallel.
Low voltage connections are by.slip on terminals.
Input:
120/240 vac 10%,47-63 H,z. Normally supplied wired for

120V. For 240 Volts change, transformer tap connections.
Output 1:
+5V, adjustable from 4.5 to 5:5 Volts at 4 amperes maximum. line-Load-Ripple total regulation 3%.
Output 2:
-15V 5% at 1.5 amperes, maximum. Line-Load-Ripple

total regulation 5%.
Temp. Range:
Above specifications are over a range of 0-50C.
H716-$150
323
H726
POWER SUPPLY
POWER
SUPPLIES
The H726 power supply provides +5 volts at 7 amps with over-voltage protection. A convenience outlet as well as an off switch for the 5. V supply
are supplied; both may be operated in parallel. This power supply is built
into a systems unit mounted via the two mounting screws in the systems
unit. The H014 mounting plate may be used to mount the supply horizontally in a 19" rack.
Maximum Dimensions: 16.5" x 2.23" x 6.5" deep.
Power Input: Screw terminals on terminal ~trip.
5 Volt Output: 0.25" Faston connectors on terminal strip_

Input: 120/240 V ac, 47 to 500 Hz, normally supplied wired for 120 V ac_
Output: +5 volts with 5 mV rms ripple and noise, max. line and load
regulation combined is 1 % or less.
Temperature Range: __ 20 0 C to 71 0 C.
H726-$200
324
TYPE 728, 728A
POWER
SUPPLIES
POWER SUPPLIES
+ 10, - 15 VOLTS
I
I
,
I
---1-----I
10
2: 0
-,~\I
30
40
SO
60
CHAfIiII"'n CUIII'R[NT
70
10 "0
(""PSI
'~+IO'
:~;~
Ut(OI
CO .. MO"
The Types 728 and 728A (+10, -15 v) Power Supplies are capable of with
standing wide line and load variations for general system use. When used
singly, the 10v channel can supply 0 to 7.5 amp, or the 15v channel can
supply 1.0 to 8.5 amp. The 728 Power Supply is electrically identical to the
783 but is made on a shorter chassis specifically designed for mounting on
the plenum door of a DEC computer cabinet.
INPUT VOLTAGE: 728: 115 v, 60 cps, 728A: 112.5, 123.5, 195, 220, 225 v,
50 cps. See "50 cps power."
OUTPUT VOLTAGE: +10 v, -15 vdc, floating.
OUTPUT CURRENT: 1) When only one output is loaded: +10 v: 0 to 7.5 amp
-15 v: 1.0 to 8.5 amp. 2) When both outputs are loaded: +10 v: 0 to 7
amp, -15 v: 1.0 to 8.0 amp. At least 1.0 amp must be drawn from the
-15 v channel to assure proper load regulation.
LINE AND LOAD REGULATION: The output voltage remains between -14.5
to -16.5 v for the -15 v channel and within +9.5 to +11.5 v for the +10 v
channel, when load varies from minimum to maximum and line voltage varies
from 105 to 125 vac.
p.p RIPPLE: Less than 0.7 v for 10 v output; less than 0.7 v for output (20% more ripple on the 50 cps type).
LINE FREQUENCY TOLERANCE:
15 v
2% of line frequency.
The sum of the output currents is limited by the following equation: 5(110)
+6(1 15 )
53 (see Figure).
325
PANEL WIDTH: 16% in.
PANEL HEIGHT: 8 3,4 in.
DEPTH: 5% in.
FINISH: Chromicoat.
POWER INPUT CONNECTION: Screw terminals on transformer.
POWER OUTPUT CONNECTION: Heyman tab" terminals to fit with AMP
"Faston" receptacles series 250, part 4177.4 or Type 914 power jumpers.
728 728A -
326
$240.00
$260.00
TYPE 783, 783A
POWER
SUPPLIES
POWER SUPPLIES
+ 10, - 15 VOLTS
"'..~~.
II
"'"',,,_
""
-~------
a.-
--t::;,>!
,1 I
10
2: 0 :)0
40 !lO
60
70
10 10
The Type 783 Power Supply (+10, -15 v) is a simple, rugged supply capable
of withstanding wide line and load variation for general system use. The
graph above sh.ows the permissible region of operation when both outputs
are used. When used singly, the 10-v output can supply 0 to 7.5 amp, or
the 15-v output can supply 1.0 to 8.5 amp. It is designed for mounting in a
standard 19-in. rack. The Type 783A is a 783 Power Supply with a 50-cps
transformer.
INPUT VOLTAGE: 783: 115 v, 60 cps. 783A: 112.5, 123.5, 195, 220, or 235 v,
50 cps. See "50 cps power."
OUTPUT VOLTAGE: +10 v, -15 vdc, floating.
OUTPUT CURRENT: 1) When only one output is loaded: +10 v: 0 to 7.5 amp
-15v: 1.0 to 8.5 amp. 2) When both outputs are loaded: +10 v: 0 to 7.0
amp*, -15 v: 1.0 to 8.0 amp*. At least 1.0 amp must be drawn from the
-15 v channel to assure proper load regulation.
LINE AND LOAD REGULATION: The output voltage remains between -14.5
and -16.5 v for the -15 v output and within +9.5 and +11.5 v for the
+10 v output, when load varies from minimum to maximum and line voltage
varies from 105 to 125 vac.
Pop RIPPLE: Less than 0.7 v for +10 v output. Less than 0.5 v for -15 v
output. (20% more ripple on the 50-cps type.)
LINE FREQUENCY TOLERANCE:
2% of line frequency.
*The sum of the output currents is limited by the following equation: 5(1, ov)
6(1, 5v) =53.
327
PANEL WIDTH: 19 in.
PANEL HEIGHT: 8 3A in.
DEPTH: 5% in.
FINISH: Chromicoat
POWER INPUT CONNECTION: Screw terminals on transformer.
OUTPUT POWER CONNECTION: Heyman tab terminals designed to mate with
AMP "Faston" receptacles series 250, part #41774 or Type 9144 power
jumpers.
783 783A -
328
$240.00
$260.00
K731 POWER SOURCE MODULE
POWER
SUPPLIES
NEMA
SENSING OUTPUT
ITO K732)
t2.6VCT
TRANSFORMER
MIL
~I~~~~.:
+5YDC,IAMPERE
LINE SYNC
S
SENSING OUTPUT
ITO K73Z1
ITRIPLE THICKNESS MOOULEI
TRIPLE THICKNESS
The K731 supplies +5 volt DC power to pin A of all K Series modules and
provides several specialized once-per-system control. functions. Any source of
center-tapped 12.6 v (50 or 60 Hz) allows the K731 to deliver up to 1 amp dc,
which is sufficient to operate most typical control systems of up to 32
modules. The K731 is short-circuit proof.
This module is normally plugged into one of the innermost sockets on a K941
mounting bar, where its large components occupy space otherwise unused.
The turn-on output goes to ground during the power-up transient, and remains
at ground until after the supply voltage has fully reached its quiescent value.
It may be used to initialize flip-flops to a known starting condition.
The OK level output goes to ground when ~e supply voltage reaches 90% of
its final value, and returns positive when less than 90% of full voltage is
available. It is normally used as an enabling input to the K273 Retentive
Memory module.
The line sync output anows a Kl13 or K123 gate to switch in synchronism
with ac supply zero-crossings. This permits the line frequency to drive a real
K731-$30
329
time clock, or serve as the standard in a phase-locked loop with K303 timers,
where higher frequencies must be synchronized with the line. Line sync fanout is limited to 1 ma (for high fanout, use K113 or K123 for distribution).
None of the K731 logic outputs may be used to obtain the OR function, and
they may not be wired to any other output.
K731 delivers up to 1 ampere when used with a 12.6 volt tranformer rated
for 105130 volt line. For 5% input v91tage reduction (12.0v tranformer or
100 volt line) the output current capability decreases 10%.
The K731 can also be used with M Series modules provided overvoltage
protection is not necessary, sioce voltage regulation is 5% .
330
POWER
SUPPLIES
K732 SLAVE REGULATOR
NEMA
--
12.6VAC
CT
u
......---~~
~
~
+5VDC, 3 AMPS
(TO PIN A,
ALL MODULES)
TURN'ON
K731
...
V
OK LEVEL
SENSING
LEVEL
LINE SYNC
r - +-+-t--i-------f-------_+_.
GROUND
(TO PIN C,
ALL MODULES)
K732
SLAVE
REGULATOR
* HASH FILTERS
(SEE CONSTRUCTION
RECOMMENDAT IONS)
FOUR MODULES THICK
This module is normally tied to corresponding pins A,C,S,U, and V of a K731

Source. For each unit of current emitted by the K731, the K732 emits two.
Up to three K732 slaves can be controlled by a single K731 for a total system
current of 7 amperes.
In high-current systems, use short heavy wires for transformer secondary
connections. Loss of 5% of secondary voltage in either ground return or
transformer output leads will reduce regulator..current ratings more than 10%.
Tabs near the handle end of the K732 may be connected to K741 or K743
transformers by using convenient 914 Power Jumpers. Then by wiring pins U
and V to corresponding pins on K731, AC connections are provided through
the K732 to the source modulp.. To avoid loss of regulation, do not connect a
K732 until enough modules have been plugged in to draw a reasonable cur
rent (several hundred milliamperes).
For self contained low-ripple supplies see H710, and H716.
K732--$27
331
MIL
tl.,VAC
CT
[0-
TUiiiON
K731
VAC
'];*
OK LEVEL
SENSING
LEVEL
r -
,f,
* HASH FILTERS
(SEE CONSTRUCTION
LINE SY,.C
GROUND
(TO PIN C.
ALL MODULES)
A
+5VDC~ 3 AMPS
(TO PIN A.
ALL MODULES)
K732
SLAVE
REGULATOR
RECOMMENDATIONS)
FOUR MODULES THICK
One K731 plus up to 3 K732 can provide from 1 to 7 amperes at +5v.
332
K771
"
POWER
________D_s_p_~_y__S_U_pp_L_y______~ __
SU_P_P_L_IE_S~
3/S'
i ,.....-------,
+
+
\4-- 2"-----1
I
1
2 3/4"
(SHOWN WITH 3 K671'SI
Shown above from the viewing side, the K771 supplies power and a convenient two-screw mounting for up to 6 K671 display tubes. Display tubes are
stacked to the left, the first tube board being attached to the K771. The
second tube board attaches to the first, and so on. Board mounting screws
provide both mechanical mounting and electrical power connections. The two
panel mounting screw locations dimensioned above have No.6 steel threaded
inserts. Several 1" holes using a standard chassis punch may be cut on 0.8" .
centers for viewing display tubes. To seal opening against dust, a 3" by 3-6"
piece of Lucite or Plexiglas may be assembled betwe,en display and mounting surface. Power 120 VAC enters the supply from a terminal strip at the rear.
Total depth behind mounting surface: '4".
.
K771-$35
333
K741, K743
POWER
SUPPLIES
POWER TRANSFORMERS
r240VAC
12.6 VCT
FOR 1<731,
1<732
2Fl//~--="----'''
K741
~)
.~~
12~A0---U ~~:
12 VAC 2 AMPS
) 12.6 VCT FOR
1<731, 1<732
GN
K743
These hashfiltered, 50/60 Hz transformers supply K731 Source and K732
Slave Regulator modules. The K743 also provides an auxiliary winding for
use with K580 Dry Contact Filters, K681 or K683 Lamp Drivers (requires
additional ~ridge rectifier, and the K730 Supply and Control Module. Type
914 Power Jumpers are convenient for connecting to tab terminals on these
transformers and on the K732 and K943. Both transformers have holes at
the corners of the chassis plate for mounting on K980 end plates:
PLATE DIMENSIONS
K741
K743
12" x 5"
5" x 5"
31
HOLE CENTERS MATCHING K980 Ctrs.
21f2" X 30/8"
4" X 30/8"
21f2"
4"
The K741 is sufficiently light in weight to be mounted on one side only, as at

the end of a K943 mounting panel.
K741-$30
K743-$45
334
K741
K743
335
336
Digital provides a complete line of pre-assembled cables, cable cards and

cable accessories which are compatible with DEC and customer supplied
equipments. In addition some cables are available in customer specified
lengths for special applications.
337
Cable Ordering Information

The standard lengths of most of the pre-assembled cables are 3, 5, 7, 10,
15 and 25 feet. Cables listed with an xx designation are available in lengths
specified by the customer, however the length must be ordered in increments
of feet only.
To determine the cost of special length cables, the price per foot of the type
of cable required is added to the basic price of the pre-assembled cable.
Example: BC02L-07
$34.20 Total Cost
. Ldenotes cable
tength in ft.
1-BC02L-xx
7 ft. ribbon at 0.06/ft
$30.00
4.20
$34.20
"'cost/ft x 2 for double cables

CABLE TYPES AVAILABLE
CABLE TYPE
20
9
19
9
40
36
Conductor Ribbon
Conductor Flat Coax
Conductor 1 1/4" Mylar (Flexprint)
Conductor Round Coax
Conductor Flat Cable
Twisted Pair Coax
338
PART NO.
PRICE/FOOT
91-07575
17-00001
17-00002
17-00003
91-07722
91-07599
$ .60
1.00
.75
1.50
2.00
2.00
STANDARD CABLES
(SINGLE SIDED CONNECTOR CARDS)
CABLES
RIBBON CABLES
(20 CONDUCTOR)
TYPE
BC02FXX
BC02LXX
BC02MXX
BC02pXX
BC02SXX
BC02WXX
BC02YXX
BC04AXX
BC04BXX
BC04FXX
CONNECTORS
W018W023
W021W021
W021W022
W022W022
W023W023
W028W028
W011W021
WOllOPEN END
W0180PEN END
W0230PEN EN D
CABLE TYPE BC02L
339
BASIC
PRICE
$33.00
30.00
30.00
30.00
30.00
30.00
31.00
15.00
18.00
15.00
FLAT COAX CABLES

(9 CONDUCTOR)
TYPE
BC03A-XX
BC03B-XX
BC03C-XX
BC03D-XX
BC03J-XX
BC04L-XX
BC04M-XX
BC04NXX
CONNECTORS
WOll-WOll
WOll-W021
W021-W021
W021W022
W02S-W021
WOll-OPEN END
W0210PEN END
W022-0PEN END
CABLE TYPE BC03B
340
BASIC
PRICE
$3S.00
37.00
36.00
36.00
36.00
lS.00
lS.00
18.00
MYLAR FLEXPRINT CABLES

(19 CONDUCTOR)
BASIC
DESIGNATION
CONNECTORS
BC03E-XX
BC03F-XX
W031-W031
W033-W033
CABLE TYPE BC03E
341
PRICE
29.00
28.00
STANDARD CABLES
(DOUBLE SIDED CONNECTOR CARDS)
CABLES
All M Series cables connector cards are double sided and attached to double
cables unless otherwise noted.

(19 CONDUCTOR-1 1/4")
TYPE
CONNECTORS
BC03H-XX
BC04T-XX
BC04U-XX
BC08A-Ol
BC08A-03
BC08A-05
BC08A-07
BCOSA-lO
BC08A-l5
BC08A-25
M90lM901
M90l-0PEN END
M903-0PEN END
M903-M903
M903-M903
M903-M903
M903-M903
M903-M903
M903-M903
M903-M903
BC08.C-Ol
BC08C-03
BC08C-05
BC08C-07
BC08C-I0
BC08C-15
BC08C-25
M903-2/W03I
M903-2/W03I
M903-2/W03I
M903-2/W03l
M903-2/W03I
M903-2/W03I
M903-2/W03I
CABLE TYPE BC08A

342
PRICE
$54.00
27.00
22.00
45.00
48.00
51.00
54.00
59.00
66.00
81.00
46.00
49.00
52.00
55.00
60.00
67.00
82.00
CABLE TYPE BC08C
RIBBON CABLE
(20 CONDUCTOR-DOUBLE)
TYPE
BC02X-XX
BC04W-XX
CONNECTORS
M908-M908
M908-0PEN EN D
343
BASIC
PRICE
$58.00
28.00
FLAT COAX CABLES

(19 CONDUCTORS-DOUBLE)
TYPE
CONNECTORS
BC04pXX
M9040PEN END
SC08S01
SCOSB03
BCOSB05
SCOSB07
SCOSB10
SCOSS15
BC08B25
M904M904
M904M904
M904M904
M904M904
M904M904
M904M904
M904M904
SCOSOOl
SCOSO03
SCOSO05
SCOSO07
SC08010
SCOSO15
SCOSO25
M9042/WOll
M9042/WOll
M9042/WOll
M9042/WOll
M9042/WOll
M9042/WOll
M9042/WOll
CABLE TYPE BC080

344
PRICE
36.00
$ 70.00
74.00
7S.00
S2.00
88.00
98.00
11S.00
74.00
78.00
82.00
86.00
92.00
102.00
122.00
FLAT CABLES
(40 CONDUCTOR-IS SIGNALSI AlT GNDS)
TYPE
CONNECTORS
BC08J06
BC08JI0
BC08J15
BC08J25
BCOSJ-50
H856-M953
H856-M953
H856-M953
H856-M953
H856-M953
BC08K06
BC08K10
BC08K15
BC08K-25
BC08K-50
H856-*M955
H856-*M955
H856-*M955
H856-*M955
H856-*M955
M955 single sided board
CABLE TYPE BC08J
345
PRICE
$ 70.00
80.00
90.00
110.00
160.00
65.00
75.00
85.00
105.00
155.00
CABLE TYPE BC08K
FLAT CABLE
(40 CONDUCTOR-36 SIGNALS)
TYPE
CONNECTORS
PRICE
BC08l-06
BC08l-10
BC08l-15
BC08l-25
BC08l-50
2/H856-M954
2/ H856-M954
2/ H856-M954
2/ H856-M954
2/ H856M954
$110.00
130.00
150.00
190.00
290.00
346
CABLE TYPE BC08l
FLAT CABLES
(40 CONDUCTOR-40 SIGNAL LINES)
TYPE
CONNECTORS
BC08ROI
BC08R06
BC08RIO
BC08R20
BC08R25
BC08R50
Be08R60
BC08RIOO
BC08RI30
BC08RI60
H856H856
H856H856
H856H856
H856H856
H856H856
H856H856
H856H856
H856H856
H856H856
H856H856
BC04Z01
BC04Z06
BC04Z10
BC04Z-15
BC04Z-25
BC04Z-50
H856-0PEN
H8560PEN
H8560PEN
H856-0PEN
H8560PEN
H856-0PEN
PRICE
$ 42.00
54.00
62.00
82.00
92.00
142.00
162.00
240.00
300.00
360.00
END
EN 0
END
END
EN 0
END
$ 14.00
23.00
32.00
42.00
58.00
90.00
Cables BC08J, BC08K, BC08l, BC08R, and BC04Z are terminated at one
end by a female connector which is available separately under Part No.

H856. The male I/O connector which mates with the H856 cable -and is
available under part no. H854 for custom applications.
347
BCIIA UNIBUS CASLE

The BCllA Cable consists of two 60 conductor mylar Flexprint cables used
to connect system units in different mounting drawers or to connect peripheral devices not located within the drawer.
The 120 Conductors include all 56 UNIBUS signals and 64 ground lines.

(60 CONDUCTOR-DOUBLE)
TYPE
CONNECTORS
BCllA-02
BCIIA-05
BCI1A-08F
BCllA-10
BCllA-15
BC11A-20
BC11A-25
BCllA-35
M919-M922
M919-M922
M919-M922
M919M922
M919M922
M919M922
M919M922
M919M922
CABLE TYPE BClIA
348
PRICE
$ 90.00
100.00
105.00
110.00
125.00
140.00
160.00
180.00
FLEXPRINT CABLE CONNECTORS
CABLE
ACCESSORIES
Flexprint cable connectors are available for use with 1 1/4 inch mylar Flexprint cable (19 conductor) and 3 3/4 inch mylar Flexprint (60 conductor).
A series of double sided boards allows the connection of two cables per
connector board.
TYPICAL MYLAR FLEXPRINT CABLE CONNECTORS
349
FLEXPRINT CABLE CONNECTORS

(11/4"-19 CONDUCTOR)
TYPE
NO. OF
SIDES
CABLES
NO.OF
PIN CONNECTIONS
SIGNAL
GROUND
BOARD
SIZE &
(TERM)
PRICE
M901
36
(4100
resistors)
M903
18
14 Alternate
Single Height/
Single Length 10.00
(PC Solder)
M915
24 (W/390n
Clamp)
9 (Direct)
Single Height/
Single Length 30.00
(PC Solder)
M91S*
36
None
Assigned
Single Height/
Single Length 10.00
(PC Solder)
M922*
36
None
Assigned
Single Height!
Single Length
(PC Solder)
6.00
M925'"
18
Single Height/
19 (Alternate) Short Length
(PC Solder)
9.00
M926
12 (W/ lOOn
Resistors)
24 (Direct)
W031
Single Height/
Short Length
(PC Solder)
5.50
W033'"
18
None
Assigned
Single Height/
Si ngle Length
(PC Solder)
5.25
Jumpers or Resistors requited (see schematic)

Cable connects at right angle to board
350
None
f.ssigned
Single Height/
Single Length 15.00
(PC Solder)
None
Assigned
Single Height/
Single Length 27.00
' (PC Solder)
FlEXPRINT CONNECTOR BOARD SCHEMATICS
@I "'
DO EI FI HI JI ., "MOM
M "
"
~~
FLfXPftINT
CAlLE 1
~R~Mn~~~~~.~~~Rn~~
113M
FLfXf'RINT
CABLE 2
RI-IM o IOO,1I4W
M901
,,
E,
~C2o---------~~
Mo---------_+_~
8
GNO C t
E2o---------_+_~
F2o---------~~
01
H2o---------_+_~
J2o---------~~
FI
HI
JI
Kl
LI
M1
~o---------_+_-o
L2o---------~_o
FLEXPRINT
.o---------~_o
FLEXf'R1NT
N2o---------~_o
~o---------_+__o
R2o---------~_o
N
PI
szo---------_+__o
"
I
SI
no----------+-_o
TI
V2~D------------~
~o---------~-o
M903
81
CI
01
EI
Fl
HI
.II
K!
LI
MI
NI
PI
ft!
51
&NO
Tt
UI
VI
FLEXPRINT
CAlLE 20-__ <) 'JUMPERS REQJlREO
M918
Mmau'~U"r~MUTtll
.,
FLEXPRINT
CABLE 1
IlamUl~a~u
.. n.Rn~r .
,
FLEXPRINT
CABLE 2
~---<)
JUMPERS REQUIAED
M922
T
19
"
~-----<ll
16
I5
14
I3
I2
I1
E
F
H
oJ
K
L
~~:
:~ ~~?
P
N
M
L
K
oJ
4
5
6
7
8
9
14
5
4
16
C
B
3
2
U
V
"
18
ffi
M925 .
352
III r n~trl ~rM~1 r~

\
FLEXPRINf
CABLE ,
l,tl! allllII ~ "un ~
FLEXPRItIT
CABLE 2
Rl-A8tOOQ,V4W
R9-Rt2toO,V4W
M926
(GNDIC~
-------+--
<>----+--------
F~
H --+---------0
J
<>-----------+-
--+---------0
'L~
FLEXPRINT
N --+--------0
p~
-------+-----
----+----------
----+----------
u----+v------+--------
W031
353
0
0
D
E
0--- 0
0--- 0
0
0
F 0
H D
J 0
K 0
L
FLEX PRINT
0
p 0
'0
R 0
So
T 0
U 0
Yo
e>---~JUMfIERS AEQUIAEJ)
W033
354
COAX CABLE CONNECTORS
CABLE
ACCESSORIES
Coax cable connectors are available for use with both 9-conductor flat coax
cable (DEC No. 17-00001), 9 conductor round cable (DEC No. 17-00003),
and 36 conductor, twisted pair cable (DEC No. 91-07599). Both single and
double sided connector can be provided.
TYPICAL COAX CABLE CONNECTORS
355
COAX CABLE CONNECTORS

(9 CONDUCTOR)
TYPE
NO. OF
SIDES
NO. OF
CABLES
PIN CONNECTIONS
GROUND
SIGNAL
BOARD
SIZE &
(TERM)
PRICE
M904
18
Single Height/
13 (Alternate) Single Length
(Split Lug)
M927
18
18 (Alternate)
Single Heightl
Short Length
(Split Lug)
6.00
W024
16
Single Height/
Short Length
(Split Lug)
6.00
W028*
Single Height/
(Split Lug)
6.00
NOTE: Connectors WOl i. W021. W022 are also used with 9

conductor coax cable (Refer to Ribbon Connectors for details).
Jumpers or Resistors required (see schematic)
356
10.00
COAX CONNECTOR BOARD SCHEMATICS
AI
BI
A2 }
B2
CI
C2~"""---
02
01
~
EI
NOT USED
--f---
E2 - 4 - - F2
Fl
-4......---
H2-~--
HI
COAXIAL
CABLE
JI
Kt
J2
-41......---
K2
--1---
L2 -4........- -
LI
~
Mt
M2-~-
Nt
N2
-41......---
. PI
P2
---1---
Rt
R2
-4......---
SI
S2 --l'---T2~--
Tt
Ul
VI
COAXIAL
CABLE
U2
NOT USED
-4"---
V2
M904
AAI
A810
ACI
ADI 0
AElo
AFI
AHIO
AJI 0
AK!
ALI 0
AMro
ANI
APi 0
ARI
ASlo
AT'
oAD2
o AE2
AF2
oAHl
AJ2
o AK2
BAI
BBI 0
Bel
BOI 0
BElo
BFI
&HI 0
BJI 0
BKI
Al2
o AM2
AN2
BLI 0
8M! c
&Nt
o An
AR2
o AS2
oATZ
AU2
BPI 0
GNO
AC2
BR1
GND
Be2
0802
o BE2
BF2
oBH2
8J2
cBK2
..-
Bl2
oBU2
8N2
BS! 0
BTl
oBP2
BR2
oBS2
o8T2
BU2
~
oAV2
o BV2
SPLIT lUGS
M912
357
C2
]~
DZ
E2
I111" III "11 It It It1

c
~
~
M927
R2
--""""---0
0-0
B oo_ _......RN!......-_--o
p C>o-------o
E C>o-------o
F 000-------0
H 0-0-------0
U C>o-------o
K C>o-------o
L 0-0-------0
M 0-0-------0
C>o-------o
P 0-0-------0
------0
R 0-0
S C>o-------o
T C>o-------o
Uo-o------O
V0---------0
R1,R2'10Q ,1/4W
W024
GNO
Co
r r
6D
6H
'F
~I
6
E
tb
y
~N
?
fR
6
P
r
t
6
S
o-----oJUMPERS REQUIRED
W028
358
y
fu
6T
t
I
RIBBON CABLE CONNECTORS
CABLE
ACCESSORIES
Cable connectors are available for use with 20 conductor ribbon cable (DEC
No. 91-07575). The cable conductors are soldered directly to split lugs on
the boards. The M908 and M957 are double sided boards to allow the connection of two 20-conductor cables per board.
TYPICAL RIBBON CABLE CONNECTORS
359
RIBBON CABLE CONNECTORS

(20 CONDUCTOR)
TYPE
NO. OF
SIDES
PIN CONNECTIONS
NO. OF
CABLES
SIGNAL
GROUND
BOARD
SIZE &
(TERM)
PRICE
Single Height/
9 (Alternate) Short Length
(Split Lug)
$6.00
WOII
W018
18 (WI 0664
Diodes)
None
Assigned
Single Heightl
Short Length
(Split Lug)
9.00
W020
18 (W/15000
Resistors)
None
Assigned
Single Height!
Single Length
(Split Lug)
8.00
W021
W022
(WI 1000
9
Loads)
Single Height!
(Split Lug)
6.00-
Sing!e Height!
(Split Lug)
6.00
6.00
W023 *
18
None
Assigned
Single Height!
Single Length
(Split Lug)
W027
18
(30000
Resistors)
None
Assigned
Single Heightl
Single Length
(Split Lug)
7.00
M908
4 (W!I00
Resistors)
32 (Direct)
None
Assigned
Single Height!
Single Length
(Split Lug)
10.00
M917
18
Single Height!
(Split lug)
10.00
M957
36
None
Assigned
Jumpers or Resistors required
360
Single Height/
Extended Length 21.00
(Split Lug)
RIBBON CONNECTOR BOARD SCHEMATICS
GNO c
:::
E
F
H
J
K
L
"
"
WOII
III
aBU<
Ot611t
a flED
Ol"~
a YEt.
012 ~
aew
018
A a
Qt7
8 a
III
C 0
ollRN
Ot5~
oa
E a
oORN
OI3~
F 0
H a
011
J a
a GIIN
IJlI
K 0
a VIO
OIO~
oORY
08
111
o8LK
06
to!
09.,1
L 0
M 0
aWHT
07.,1
N 0
p 0
R 0
05
lit
03
t-I
Ot
t-I
a 8RN
a VEL
o GfIN
ott-!
U a
V 0
a flED
o ORN
04 ..1
S a
T 0
RtI80N CAkE
o IILU
a V10
DIODES ARE 0664
W018
361
Itt
A 0
F 0
R6
H 0
J
RB
0
R9
0
M 0
N 0
RM
Rt5
Itt6
W020
W021
362
8lK
IGNOIC
REO
ORN
GRN
8lu
GRY
8lK
REO
l
T
BRN
Rl
VEL
VIC
WHT
BRN
ORN
R7
VEL
GRN
RlB80N
CABLE
8Lu
VIQ.
R9
GRY
RI-R9l00n. V4W,tl0%
W022
A 0
0--- 0
B
C
o
E
F
o ---
0
0
0
0
0
SBLK
SBAN
SRED
SORN
S
S
ell
S
H 0
J 0
K 0
L 0
MO
No
P 0
R 0
S 0
TO
U 0
Vo
VEL
GRN
IIUJ
VIO
ISIGRY
S WHT
S 8LK
lSI BRN
SlED
ID ORN
II VEL
IIGRN
ID !lLU
ID VIO
W023
363
RIBBON
CABLE
RI
oo--------~~----------~o~K
oo--------~~----------~o~
R2
R3
C OO----------"I"".
R4
-------------()o RED
oO---------Y.~----------~o~
OO---------'\I\~----------~O
OO---------Y~~----------~O~
R5
VEL
00--------_R7~-:----------~0 BLU
oo--------~~----------~o~
Oo--------~~----------~o
R8
R9
GRY
RIBBON
~E
RiO
L 00-------........,.,.,..-------------00 WHT
Ril
oo-------_~----------~oax
O O - - - - - - - -........N.'r__-----------()O
Ri2
8RN
Ri3
P oO--------.........N.'r__-----------()O RED
R14
R 00--------_,.,.,..-------------00 ORN
R15
S 00-------........,.,.,..---------_0 VEL
R16
T oO-------_.N.,;..------------()o GRN
Ri7
U 00--------_,.,.,..----------_0 BLU
Ria
v 00-------_,.,.,..-------------00 VIO
All. RESISTORS ARE:
3OOO,V4W,:t5'11o
W027
oAI
081
OCt
001
oEI
E20
F20
H2o
oJ'
J20
oK!
K20
o Lf
L20
OMf
10120
ONt
R4
R3
D20
oHl
OF!
wIT
A20 _
820
C20
H2o
OP1
P20
ORi
R20
o SI
520
oT!
120
oUt
\120
oVl
Wo
R1-R4otOQ,V4W
SPLIT LUG
MOOS
364
SPLIT lUllS
' - - -2
-' - -- 5 ,7
.
\I
A
10"
II
IZ
IS.
I.
II
17
II
TI
,,,
&1
"
CI
DI
EO
"
HI
JI
.,
LI
III
HI
PI
RI
SO
TI
CZ
DZ
'2
HZ
.IZ
MZ
lZ
liZ
HZ
P2
M917
AI Ifl CI DI EI FI HI JI KI LI MI HI P1 RI 51 TI UI V1
jljjljjljjjjjjljt~ ..
~~~~u~~n~u~~n~un~w
. . rrl jIIjIIjIjIjIIjj
RI-lM o IOA,1I4W
M957
365
RZ
lit VI
FLAT CABLE CONNECTORS
CABLE
ACCESSORIES
A series of solderless cable connectors are provided for use with 40 conductor flat cable (DEC No. 91-07722). These connectors are used for general
interface and with the PDPBe.
TYPICf1.L FLAT CABLE CONNECTORS
366
..
FLAT CABLE CONNECTORS

(40 CONDUCTOR)
TYPE
NO. OF
SIDES
NO. OF
CABLES
PIN CONNECTIONS
SIGNAL
GROUND
None
Assigned
Not
H856
Applicable
40
M953
18
BOARD
SIZE & (TERM)
Mates with
H854
(Board
Mounted
Male)
Single Heightl
Single Length
18 (Alternate)(Solderless
Connect JI)
M954*
36
None
Assigned
M955
18
None
Assigned
Jumpers or Resistors required
367
PRICE
8.00
$25.00
Single Height/
Single Length
27.00
(Solderless
Connect Jl & J2)
Single Height!
Single Length
(Solderless
Connect Jl)
27.00
FLAT CABLE CONNECTOR BOARD SCHEMATICS
M..L 01MER PINS ON Jt. GROUND
M953
ro--
->
~
~
;!
r:!
....
C",,,-
81
....,
>
:;
i=
iii
I!
-'"
I
::c
...,-
I
_or
-~
t
I:f
II
8
8
8
c
It
1:1
i
~
:;
)(
;;
>
:;
.
C
I:
a::
!&:
&i
IL
101
I!
E
...
ts
:II:
iIi
G
:II:
81
IL
Ii
.
~
>;
368
;1;
en
:E
A
Itt
c:
ft2
M955
369
STU
I/O CONNECTOR
CABLE
ACCESSORIES
H854 AND H856
The H854 is an I/O connector (male) housing that can be mounted at right
angles to a PC module board and soldered in place. The H854 mates
with the H856 (female) which is used to terminate a 40-conductor flat cable
as shown on cables BC08J, BC08K, BC08L, BC08R and BC04Z. All 40 pins
can be used for the transfer of signals. Purchased separately, the H856 consists of a connector housing and 40 contacts. The contacts of the H854 are
premounted in the housing:
H854
H856
370
NOT USED
UU
SS
NOT USED
VV
TT
RR
pp
NN
JJ
MM
KK
HH
FF
DO
EE
CC
BB
AA
LL
y
W
Z
X
V
T
U
S
M
K
H
L
J
F
0
E
C
NOT USED
NOT USED
H856 PIN ASSIGNMENTS
H854 - $12.00
H856-$ 8.00
371
372
Digital manufactures a complete line of hardware in support of its module

series. Module connectors are available for as few as one module and as
many as 64 in a single rack (H020). A complete line of cabinets is available
to house the modules and their connector blocks, as well as providing a
convenient means for system expansion.
Coupled with the recent additions to the hardware line, Digital has made
every effort to maintain or improve the high standards of reliability and
performance of its present line. Through the availability of a wide range of
basic accessories DEC feels that it is offering the logic designer the necessary 'building blocks which he requires for complete system design.
373
WIRING HINTS
These suggestions may help reduce mounting pan~1 wiring time. They are
not intended to replace any special wiring instructions given on individual
module data sheets Qr in application notes. For fastest and neatest wiring,
the following order is recommended.
(1) All power & ground wiring and any horizontally bussed signal wiring. Use
Horizontal Bussing Strips Type 932 for type H800, 933 for type HS03, or
939 for type HSOS.
(2) Vertical grounding wires interconnecting each chassis ground with pin C
grounds. Start these wires at the uppermost mounting panel and continue
to the bottom panel. Space the wires 2 inches apart, so each of the
chassis-ground pins is in line with one of them. Each vertical ground wire
makes three connections at each mounting panel.
(3) All other ground wires. Always use the nearest pin C above the pin to be
grounded, unless a special grounding pin has been provided in the module.
(4) All signal wires in any convenient order. Point-to-point wiring produces
the shortest wire lengths, goes in the fastest, is easiest to trace and
change, and generally results in better appearance and performance than
cabled wiring. Point-to-point wiring is strongly urged.
The wire size for use with the HSOO connector blocks and 1943 mounting
panel is 24 for wire wrap, and 22 for soldering. The size for use with HS03
block and H911 mounting panel is # 30 wire. Larger or smaller wire may be
used depending on the number of connections to be made to each lug. Solid
wire and a heat resistant spaghetti (Teflon) are easiest to use when soldering.
Adequate grounding is essential. In addition to the connection between mounting panels mentioned above, there must be continuity of grounds between
cabinets and between the logic assembly and any equipment with which the
logic communicates.
When soldering is done on a mounting panel containing modules, a 6-V (transformer) soldering iron should be used. A llO-V soldering iron may damage
the modules.
When wire wrapping is done on a mounting panel containing modules, steps
must be taken to avoid voltage transients that can burn out transistors. A
battery- or air-operated tool is preferred, but the filter built into some lineoperated tools affords some protection.
Even with completely isolated tools, such as those operated by batteries' or
compressed air, a static charge can often build up and burn out semiconductors. In order to prevent damage, the wire wrap tool should be grounded
except when all modules are removed from the mounting panel during wire
wrapping.
AUTOMATIC WIRING
Significant cost savings can be realized in quantity production if the newest
automatic wiring techniques are utilized. Every user of FLIP CHIP modules
benefits from the extensive investment in high-production machinery at
Digital, ~ut some can go a step further by taking advantage of programmed
wiring for their FLIP CHIP digital systems.
374
While the break-even point for hand wiring versus programmed wiring depends upon many factors that are difficult to predict precisely, there are a
few indications:
1. One-of-a-kind systems will probably not be economical with automatic
wiring, unless a customer has high overhead costs and performs a timeconsuming (costly) hand assembly.
2. At the other end of the spectrum, production of 50 or 100 identical

systems of almost any size would be worth automating, not only to lower
the cost of the wiring itself but also to reduce human error. At this level
of volume, machine-wired costs can be expected to be considerably less
than the cost of hand wiring.
3.
For two to five systems of several thousand wires each, a decision on the
basis of secondary factors will probably be necessary: ease of making
changes, wiring lead time, reliatsility predictions, and availability of relevant skills are factors to consider.
Digital can supply further information to those interested in programmed

wiring techniques. Contact Logic Products Marketing, DEC, Maynard, Mass.
01754.
COOLING OF FLIP CHIP MODULES

The low power consumption of K and M series modules results in a total of
only about 25 watts dissipation in a typical 1943 Mounting Panel with 64
modules. This allows up to six panels of modules to be mounted together
and cooled by convection alone, if air is attowed to circulate freely. In higherdissipation systems using modules in significant quantities from the A series,
the number of mounting panels stacked together must be reduced without
forced-air cooling. In general. total dissipation from all modules in a convection-cooled system should be 150 watts or less.
The regulating trarisformers used in most DEC power supplies have nearfy
constant heat dissipation for any loading within the ratings of the supply.
Power dissipated within each supply will be roughly equal to half its maximum
rated ouput power. If power supplies are mounted belOW any of the modules
in a convection-cooled system, this dissipation must be included when checking against the 150 watt limit.
375
CONNECTOR BLOCKS
The Series 800 Connector Blocks are compatible with a wide variety of both
single and double sided DEC modules and connector boards. The Summary
is a general listing of the types available. For detailed information, refer to
the connector block descriptions which follow.
CONNECTOR BLOCK SUMMARY
NO. OF
BLOCK
PART NO. SLOTS
CONTACTS
PER SLOT
NO. OF
CONTACT
SIDES
WIRE
WRAP
PIN SIZE
BUS
STRIP
NO.
MODULE
TYPE
H800
18
24 (AWG)
932
All Except
M Series
H802
18
24 (AWG)
None
All Single
Height Except
M Series
H803
36
30 (AWG)
933
All
H807
36
30 (AWG)
None
H808
36
24 (AWG)
939
376
All Single
Height
,AU
HSOO-W, HSOO-F
CONNECTOR BLOCKS
This is the 8-module socket assembly used in FLIP CHIP mounting panels_
Because of its 18 pin connectors, it can be used for all modules except those
with pins on both sides of the board. Pin dimensions are .031 inches by .062
inches and may be of either a wire wrap or solder fork type. Number 24 awg.
gauge wire should be used with these connectors.
The drawings below show the pertinent dimensions.
I..-- L 750 ---.I
1WIRE
WRAP
TERMINAL
Ir-I
!
I
--I
, CLEARANCE FOR COMPONENTS
ON Tl MOOtA...E IN THIS SLOT"
1r----------- ~I
I
2.585
3/t6'DRlLL-QUT
r-,-5It6'COl.WTER8ORE
II .
L__
f-@
31'16'DEEP
J
0.575
r-1-----~3--'
\.-- 1.575
SOLDER
FORK
j.-- V4'
~,.
TERMINAL
5.110'
~2.0'~
VIEW FROM MODULE SlOE
REPLACEMENT CONTACTS TYPES HSOI-W, H801-F
These contacts are offered in packages of 18 for replacement purposes. In

each package, nine straight and nine offset contact~ are included, enough
to replace all contacts in one socket.
HSOI-W is for wire-wrap connectors; HSOI-F is for solder-fork connectors.
H800F-$8
HSOOW-$8
HSOIF-$2
HBOIW-$2
377
I~
H802
C_O_N_N_E_C_T_O_R_B_Li_OC_K_____
.a...-_ _ _
1OIII~t-----
2.594
L::J
REF.------1~~1
f
L~
1.000
0.125
REF.
j;::
o~
-10.125
REF.
-----I L
This is an 18 pin connector block for a single FLIP CHP module. It can be
used to mount all modules except those with pins on both sides of the board.
Pin dimensions are .031 inches by .062 inches and may be of the wire wrap
type only. Number 24 wire should be used with this connector.
H802-$4
378
H803,H805
CONNECTOR BLOCK AND PINS
1r-
CLEARANCE FOR COMPONENTS ON THE
r+ ,"-l
MODULE IN THIS
SLOT.
~ ----.J 1-
0.125
118"
62
r----
0125
r-2
C
o
K
L
R
R
S
S

, ,
A B
C
0
E
A
B
L ____ _
--j05" __
~1
~. ~
05"
20"
0.25"
U.
C o
E
K L

.
C0
.
E
A
A 8
B
/II
R
S
F
H
L
M
R
T
/II
, V
V
T
U
VIEW FROM MODULE

SIDE
The H803 is the 8-module molded Connector Assembly used in the H911
mounting panels. For each of the eight modules, it provides a 36-pin connector with the wirewrap pins forming a 0.125-inch staggered grid as shown
above, This connector is designed to be used with M Series modules; however, it can also be used with all other series listed in this handbook.
The blocks have the same physical dimensions as the HSOO with the exception of pin length. These blocks are only available with wire wrap pins which
are designed to be wrapped with number 30 wire. Pin dimensions are 0.025
inches square. W&K Series IS pin modules will make contact with only the
2-side pins (A2, 82, etc,).
H805 is a package of 36 pins (18 left and 18 right) to be used as replacements in H803 blocks.
H803-$13
HS05- $4
379
H807
~___C_O_N_N_E_C_TO_R_B_l_O_CK_ _ _
/r=:=l
L::::J
--I
This is a 36 pin single slot connector. It is provided for M-Series modules but
can be used with modules or connector boards in the K and W Series. Uses
include mounting in confined or irregular spaces. Often the H807 is used to
terminate a connector board at a remote location. The H807 is available only
with wire wrap pins.
H807-$5
380
H80S CONNECTOR BLOCK

AND H809 PINS
WIRE-WRAP
~t.750!
HARDWARE
;t~:'~AL
LENGT,H
2
r--WIRE
TERMINAL
~~
:
I:
r--I
I
I
I
I
I
I
L. __ _
I
r-2.0'~
VIEW FROM MODULE SIDE
The H808 is a relatively low density connector block for use with all modules
in the catalog. This includes A, K, M, and W Series modules. The connector
provides 4 module slots each having 36 pins. On A,K and W Series modules
only the 2 side pins, (A2, 82, etc.) will make contact. This connector adds
a measure of convenience and versatility to the many uses to which these
catalog modules can be applied. Hand wiring of connector pins is more easily
accomplished for M Series prototype work. H80D and HSDS connector blocks
can be mixed for M and A, K, W module mixing purposes. Wire wrapping
patterns can be maiJatained even though module letter series are mixed because H8DD & H8D8 pin layout is identical. H8D9 is a package of 36 replacement pins, 18 left and 18 right.
H808-$lO
H809-$ 4
381
1r=:J
L::J
H8St
ED_G_E_C_O_N_N_EC_T_O_R_ _ _......I
L - -_ _ _
The H851 edge connector is used to bus signals from the top center terminal
fingers to an adjacent quad board with similar terminals.
H85! 382
$i5.00
HOOl, HOO2, H020, H021, H022
<-----_H_02_4_,_H_O_2_5
_ MOUNTING _A_N_D_190_7_C_O_V_E_R_~
PANEL HARDWARE
HARDWARE
Pairs of brackets. H001 provides %" standoff to mount 1907 over mounting
panel wiring. H002 provides a 2/1 setback so a control panel with switches,
lamps, etc. can be mounted flush with mounting rack or cabinet in front of
logic wiring.
The H020 consists of a 19" mounting frame casting. Components which can
be mounted on this frame include, HBOO, HB03, HBOB connector blocks,
power supplies or customer components that are adapted to the frame
mounting requirements.
H021-Single offset end plate which mounts to the H020. This end plate
provides a mount for the 1945-19 hold down bar, if required.
H022-Single end plate similar to the H021 on which is mounted a terminal
block assembly for ease of parallel power wiring to adjacent panels.
H024-Single offset end plate B% II (Extended length version of H021).
H025-Single offset end plate B%" (Extended length version of the H022
with terminal block).
194519 HOLD DOWN BAR: Reduces vibration and keeps modules securely
mounted when panel or system is moved. Adds % in. to depth of mounting
panel.
383
1907 Panel Cover-Blue or brown tweed painted aluminum cover with captive screws to mate threaded bushings in K980 and HOOt. Adds to appearance while protecting system against vibration and tampering. When choice
of color is not specified, blue will be supplied.
HOOl- $7
Hoo2-$15
H020-$15
H021-$7
H024-$7
H025-$20
384
H022-$20
1945-19 - $20
1907~$9
K940, K941
MOUNTING HARDWARE
r- - - -
STANDARD MOW..E (SIDE VIEW)
..
rt=-~~===----:' ==----------:'~-===-===1
~/
I
I
:
Heoo
I H803
I OR
I HS08
I
L..; ____
I
I
JI
r---- ,
I
I
I HaOO
Ha03
I Ha08
I
OR
I
I
L ____
JI
SIDE VIEW
K941
QJIDE PIN FOR QUICK ASSE.a.Y

TWO M6" HEAD MOUNTING BOlTS
EQUIPMENT MOUNTING IWEL
This convenient mounting hardware permits logic connector pin wiring to be

done before logic is installed in the enclosure.
K940 is a mounting support that attaches to the enclosure. K941 is a removable bracket that mounts up to four H800, H803, or H808 connector
blocks. Any connections to external equipment are made through the ribbon
connectors of interface signal modules (K508, K524, K604, K644) to the
K716 Interface Block.
385
K940
K941
TOP VIEW
K940-$6
K941-$6
386
Cabinets for DEC systems are manufactured In this portion of DEC's recently
opened Westfield, Massachusetts production facility.
387
K943-R. K943-S
19
L..--_ _ __'_'_M_O_U_N_T_IN_G_P_A_N_E_L_ _- ,
r=::=:l
L::J
1907
These low cost, 19" panels have sixty-four 18 pin connector sockets with
either wire wrap (S) or solder fork (R) contact pins_ Shipped with connector
blocks installed and pins A and C bussed.
No terminal strips are included in the K943, since power regulators K731
and K732 will normally be plugged in to make power connections. If holddown is required to prevent modules from backing out under vibration, order
a pair of end plates K980 or K981 (8112" extended length version of K980).
'These assemble by means of added nuts on the rear of the rack mount
screws. They accept the painted 1907 cover plate, making a hold-down system that contacts the module handles and can allow flexprint cables to be
threaded neatly out the end. Rack space: 5 1/4". See photos showing K943-S,
K980, 1907, and HOOL
K943R-$96
K943S- $96
K981- $10
388
H911-J, H911-K,
~
H_9_1_1-_R_'_H_9_1_1_-S_________
_ ____
MOUNTING
PANEL
HARDWARE
H911-K
The H9ll mounting panel uses eight H803 connector blocks and houses
sixty four, 36 pin connectors. Mechanical dimensions are identical to those
of the H910.
The H911 is available with wire wrap pins only, and is generally used for M
Series modules.
The unit is a combination of the following parts:
H020 - Mounting frame
H021 - Standoffs
H803 - Connector blocks
933 - Bussing strips (optional with H022 standoff)
The
The
The
The
H911J is not prewired or bussed for power.

H91l-K does have prewired power.
H91l-R similar to H911-J except with 8'12" extender end plates.
H9II-S similar to H911-K except with 8 1h" extender end. plates.
933 BUS STRIP - For H911 mounting panel, makes wiring power and
register pulse busses easy.
Consult following table for mounting panel options and ordering information.
H911J - $151
H911-K -:- $161
H911-R - $151
H911-S - $161
389
H914, H916 & H917

MOUNTING- PANEL
H914 -
This panel houses 8 low density H808 connector blocks. The panel
will hold 32 of either A, K, M or W Series modules. It can be used
for expanding slot capacity in conjunction with H913 or alone using
other voltage supply options. e. g. K731 and K732 combinations.
Mechanical characteristics are like those of the H911.
H916 -
This panel contains an H716 power supply and 6 H803 (green)

connector blocks. The unit provides for forty-eight, 36 pin module
slots. Although generally used for mixes of M and A series modu les,
K and W series modules can also be accommodated.
H917 -
This panel is similar to the H916 panel except 6 low density H808
connector blocks are supplied instead of H803 b10cks. With these
connector blocks, 24 module slots are available, allowing the use
of any module series. Electrical and mechanical characteristics are
similar to those of type H916 with the exception of the connector
blocks.
H913-$270
H914-$125
H916-$270
H917-$260
390
TABLE OF MOUNnNG PANELS

tWlTH& WITHOUT .POWEll SUPPLY
AVAILABLE
VARIATIONS
ORDER NO.
ORDER
LETTER
PANEL
H911
J,R
H911
K,S
H914
H916
101
H917
=I<
K943
K943
1943
'"
'"
'"
'"
'"
'"
'"
101
101
'"
'"
'"
(5ee.1943 for
X
V
PRICE
'"
P
$151
101
$125
101
$270
$260
101
$96
'"
$ 96
d~tails)
~PREWIRED
= NO POWER
= POWER OPTION
$161
FOR POWER
105-125 VAC OR
210-250 VAC
47-63 Hz
.
F-
SOLDER FORKED
CONNECTIONS
W-WIRE WRAP
CONNECTIONS
B-
POWER INPUT VIA TERMINAL

BLOCK. BOTH CONVENTIONAL
SCREW CONNECTIONS AND
TAPER TABS CAN BE ll'sED
Example Order: H911 KX

This describes a Type H020 casting with 8 Type H803 wire wrap connectors
and ground wired to a terminal block incorporated into the end plate
assembly.
391
l__________
_
--------~11
MOUNTING
PANEL
H_O_14__
HARDWARE
The H014 is a 5- IA" mounting panel for a standard 19" rack or cabinet. The
H014 may be used to mount the H726 power supply or an H933 systems
unit casting. When the H933 systems unit casting is mounted on an H014,
the back plane pins are available behind the H950-P bezel cover panels.
H014-$20
392
H933
SYSTEMS UNIT CASTING
The H933 Systems Unit Casting provides a way to mount standard DEC
connector blocks on a flat panel such as the H014. Casting dimensions are
161f2" by 2 1,4". The H933 may be ordered plain or with connector blocks
installed:
Item
H933
H933-A
H933-B
H933-C
H933-D
SYSTEMS
H933 with
H933 with
H933 with
H933 with
Description
UNIT MOUNTING PANEL
3 HSOOW connectors-24-1S pin
3 HSOO-F connectors-24-1S pin
3 HS03. connectors-24-36 pin
3 HSOS connectors-12-36 pin
H933-$15
H933-A-$37
H933-B-$37
H933-C-$54
H933-D-$42
393
I~
H920
______M_O_D_U_L_E_D_R_A_W_E_R_____
L::J
The H920 Module Drawer provides a convenient mounting arrangement for a

complete digital logic system. The H920 has space for 20 mounting blocks in
addition to an H710, or H716 power supply, or 24 mounting blocks without
a supply. It accepts H800, H803, and H808 mounting blocks and fits standard
19" racks. Width of the H920 is 16 3,4", depth is 19" and height is 6 3,4"
including an H921 front panel. The H920 is equipped with a bracket for distributing power within the drawer, or to other drawers or mounting panels.
Mounting arrangements are provided for the H921 front panel and H923
slide tracks.
The H921 front panel is designed for use primarily with the H920 Module
Drawer. It provides mounting space for switches, indicators, etc. The H921 is
pre-drilled and ready to mount on the H920. Height of the H921 is 6 3,4",
width is 19".
H923 chassis slides are intended for use with the H920 Module Drawer.
The H923 allows the user to slide the drawer out of the rack and tilt the
drawer for easy access to either the pin or module side.
H920-$170
H921-$ 10
H923-$ 75
394
I~
H925
"'--____
M_O_D_U_LE_D_R_A_W_E_R_ _ _---..
The H925 Module Drawer provides mounting space for HSOO. H803. and
H80S connector blocks to accommodate up to 144 modules. The connector
blocks mount pins upward on the H925 for easy access during system
checkout.
The right side of the H925 is provided with three axial flow fans (300 cfm)
which are mounted internally. They provide cooling air flow across the
mounted modules.
For power supply mounting in the H925 cabinet. omit 4 connector blocks
thereby deleting 32 module slots, when using the HSOO or H803 connector
blocks. If the HSOS blocks are used, 16 module slots are deleted. Mount the
power supply externally if all logic mounting space is required.
For ease of mounting, the H925 is provided with two non-tilting slides. similar
to Grant type SS-I68-NT. ConSidering possible serviCing, the H925 should be
mounted with enough hei~ht for using ~ttom access.
The H925 includes top and bottom cover plates along with an attractive bezel
and front subpane!. The subpanel is made of sturdy 16-guage metal for
mounting front panel controls and accessories. The bezel is designed for
installing a customer-supplied dress panel. The dress panel should have a
thickness of Va ". The H925 fits all DEC 19" racks.
H925-$250
395
H941AA
,,--_1_9_"_M_O_U_N_T_I_N_G_P_A_N_E_L_FR_A_M_E_____
L:J'
This rugged steel frame holds four 19" x 5 1h" mounting panels. A quickrelease pin snaps out to allow the two-piece frame to swing open for easy
access to the back panel wiring and connections. The construction of this
frame allows sufficient rigidity for vertical or horizontal mounting. The Black
Tweed finished aluminum cover affords mechanical protection for ,the circuitry as well as a neatly finished appearance for your digital logic system.
The cover attaches to the frame with two thumb-release, positive-grip fasteners.
The H941 AA holds up to 32 H800, H803 and H808 Connector Blocks. It
provides up to 256 module slots with H800 and H803 Connector Blocks and
128 slots with the H808's. The frame is designed to accept K943. H911.
H914, 1943 Module Panels and H900, H910, H913. H916. H917 panels with
power supplies. These panels attach to the pre-tapped frame with 1032 x
112" machine screws.
Frame Height: 23"
Frame Width: 24"
Overall Depth (Cover and Frame):
H941-AA-8"
H941-BA-8"
H941-BB-ll"
Frame Mounting Hole Centers: 12 x 22112"
Frame Mounting Bolt: 114" dia.
Weight (Cover and Frame): Approx. 25 Ibs.
Cover Material: .093" Sheet Aluminum
397
H941AA (Mounting Panel

Frame 19")
-
$125
H941-BA (Cover 5 1h")

H941-BB (Cover 8%")
$ 80
- $ 70
-
H9190, H019
PDp8e INTERFACE HARDWARE
H9190 Mounting Panei-contains M Series connector blocks with 8/etype

packaging for PDpl6 options or standard M Series modules. Also included
are the 81 e power wiring harness and power bus board. There is M Series
power bussing for all but the four slots in the first column. Four mounting
spacers allow the H9190 to be easily mounted in the second half of an 8/e
chassis.
H9190-$250
H019 Mounting Bar-an aluminum casting with the power bus 'board and
power wiring harness. It also includes four mounting _spacers for mounting
in an 8/ e chassis. Up to ten connector blocks of any type may be accommodated by this frame.
H019-$70
398
H950, H954 AND H957 SERIES

CABINETS
HARDWARE
The logic Products Group offers standard 19" mounting cabinet

assemblies in three series-H950-AA (68 25/32" high x 25" deep
mounting space), the H954-AC cabinet frame assembly (49 8/16 high
deep x 42 1/16" mounting space) and H957 (50" high x 25" deep
mounting space).
frame
x 63"
x 25"
x 42"
The above-listed cabinet frame assemblies offer complete flexibility and expandability to present and future DEC customers, single users, multiple
users and original equipment manufacturers. The enclosure area in these
cabinet frames is adaptable to customer-designed hardware, logic module
racks, power supplies, computer systems, and peripherals.
The cabinet frame assemblies are constructed of rugged 12- and 13-gauge
steel. The frame uprights have 9/32" holes drilled at standard EIA spacing
(5/8-5/8-1/2) the full length of the 42" and 63" front and rear mounting
panel heights.
Note: The cabinets described in the following pages, Cabinet A through H,
do not include in their listed price the front cabinet mounting options.
Cabinet customers have the option of selecting the type of front cabinet hardware mounting of their choice. Consult the H950 and H954
parts list for prices and add to basic cabinet price listed.
Cabinet A
I-H950-M 19" Mounting Frame (71 7/16" w/casters x 25" x 63"), includes mounting hardware
1-7406782 Kickplate (Lower Cab Trim)
* 1 pro H952-BA Stabilrz~r Feet
I-H952-FA leveler Set (4)
*1-H950-lA logo Frame Panel
2-H952M End Panels
1~H950BA Full Door Rear (Right Hanging)
I-H952EA caster Set (4)
I-H952-CA Fan Assembly
Cabinet A-List Price--$411.00
OPTION: Front Cabinet Mountingl Cover PanelsH950-P (5 1/4") and/or H950-Q(10 1/2")
H950-SA Filter (for fan) Assembly
See Special Considerations Sections 5, 8 and 13.
Cabinet B
1-H950-M 19" Mounting Frame (71 7/16" w/casters x 25" x 63") includes mounting hardware
1-7406782 Kickplate (lower Cab Trim)
* 1 pro H952-BA Stabilizer Feet
I-H952-EA Caster Set (4)
I-t1952FA leveler Set (4)
399
*1-H950-LA Logo Frame Panel

2-H952-AA End Panels
I-H950-DA Mounting Panel Rear Door (Right Hanging)
I-H950-FA Mounting Panel Door Skin
Cabinet B-List Price-$431.00
OPTION: Cabinet Front Mounting/Cover PanelsH950-Q (10 1/2") and/or H950-P (5 1/4")
H950SA Filter (for fan assembly)
See Special Considerations, Sections 5, 8, and 13.
Cabinet C
I-H950AA 19" Mounting Frame (71 7/16" w/casters x 25" x 63") includes mounting hardware
*1-H950-LA logo Frame Panel
I-H952-FA Leveler Set (4)
I-H950-DA Mounting Panel Door (Right Hanging) .
I-H950-BA Full Door Rear (Right Hanging)
Cabinet C-List Price-$437.00
OPTION: Front Cabinet Mounting/Cover PanelsH950-P (5 1/4") and/or H950'Q (10 1/2")
Short Doors-See H950 Cabinet Parts listH950HA-HK-short door selection.
H950-SA Filter (for fan assembly)
Cabinet D
I-H950-AA 19" Mounting Frame (71 7/16" w/casters x 25" x 63") includes cover filter and mounting hardware
1-7406793 Kickplate (lower Cab Trim)
1-H952-CA Fan Assembly
*1-H950-LA logo Frame Panel
I-H952-FA leveler Set (4)
I-H950-BA Full Door Rear (Right Hanging)
Cabinet D-list Price-$390.00
OPTION: Front Cabinet Mounting-Cover PanelsH950-P (5 1/4") and/or H950-Q (10 1/2")
Short Doors-See H950 Parts ListH950-HA-HK-Short Door Selection.
H950SA Filter (for fan assembly)
400
Cabinet E,
Same as Cabinet 0, except:
I-H950bA Mounting Panel Door Rear (Right Hanging) and
I-H950FA Mounting Panel Door Skin,
are substituted for:
I-H950BA Full Door Rear (Right Hanging)
Cabinet E-List Price-$410.00
OPTIONS: Front Cabinet MountingSame as listed for Cabinet 0
Cabinet F (H961-A)
Addon-Designed for combining two or more cabinets, in the H96O-'Series.
No end panels are required (H952-AA).
1-H950-AA 19" Mounting Frame (71 7/16" w/casters x 25 x 63"), includes mounting hardware
1-74-6793 Kickplate (Lower Cab Trim)
I-H950-FA Mounting Panel Door Skin
I-H9~0-EA Mounting Panel Door Plenum (Left Hanging)
I-H952EA Caster Set (4)
-1-H950-LA Logo Frame Panel
I-H952-GA Filler Strip (Front and Rear)
11
Cabinet F-List Price-$340.00
OPTIONS: Front Cabinet Mounting

Same as used for Cabinet D.
See Special Considerations Section 13, 2
Cabinet G--Short Cabinet Series

I-H954-AC 19" Mounting Frame (51 12/16" w/casters x 25" x 42 1/16")
includes mounting hardware
I-H954-BA Full Door-Rear Mounting (Right Hanging)
1-H950-LB Logo Frame Panel
I-H954SA Filter (for fan assembly)
I-H954-UA Cabinet Cover
2-H952-AM End Panels
-I pro H952-BA Stabilizer Feet
1-74506782 Kickplate (for use with H952-BA)
Cabinet G-List Price-$523.00
OPTION: Front Cabinet Mounting/ Cover Panels
H950-P (5 1/4") and/or H950-Q (10 1/2")
See Special Considerations, Section 5
401
Cabinet H
I-H954-AC 19" Mounting Frame (51 12/16" w/casters x 25# x 42 1/16")
I~H954-BA Full Door Rear (Right Hanging)
1-H950-LB Logo Frame Panel
1----H954SA Filter (for fan assembly)
1-H954-UA Cabinet Cover
2-H952-AM End Panels
Cabinet H-List Price--$502.00
OPTION: Front Cabinet Mounting/Cover Panels
H950-P (5 1A") and/or H950-Q (l0lh")
Short Doors from H950-HA (21") through H950HF (42") only.
Cabinet I-Short Cabinet Series
1-H957-AA 19" Mounting Frame (50" w!casters x 25" x 42") includes
mounting hardware
1-H957-BA Full Door-Rear Mounting (Right Hanging)
I-H957-DA Mounting Panel Door-Rear Mounting (Right Hanging)
1-H957-FA End Panel (Right Hanging)
1-H957-FB End Panel (Left Hanging)
I~H957-LA Logo Frame Panel
1-H957SA Filter
*1-H957-HA Fan Assembly
*1 pr H952-BA Stabilizer Feet
1-74-6782 Kickplate
See Special Considerations Section 5, 14
Cabinet I-List Price--$476.00

OPTION: Front. Cabinet Mounting! Cover Panels
H950'Q (10lh ").
H950P (5 IA ")
and/ or
Cabinet J
I-H957-AA 19" Mounting Frame (50" w/casters x 25" x 42") includes
mounting hardware
1-H957BA Full Door-Rear Mounting (Right Hanging)
1-H957FA End Panel (Right Hanging)
I-H957-FB End Panel (Left Hanging)
I-H957-LA Logo Frame Panel
*1-H957-HA Fan Assembly
1-74-6793 Kickplate
I-H957-SA Filter
See Special Considerations Section 14
Cabinet J-List Price--$419.00

402
OPTION: Front Cabinet Mounting/Cover Panels H950-P (51;4") and/or

H950-Q (lOlh "). Short Doors from H950-AA (21") through
H950-HF (42") only.
OPTION: Front Cabinet Mounting/Cover Panels H950-P (5 1,4") and/or

H950-Q (10 112 ").
Short Doors from H950-HA (21") through H950-HF (42") only.
Cabinet K
Add On Cabinet-Designed for Combining Two or More Cabinets in the H957
Series-No End Panels Required (H957-FA, FB).
1-H957-AA 19" Mounting Frame (50" w/casters x 25" x 42") includes
mounting hardware
1-H957-BA Full Door-Rear Mounting (Right Hanging)
I-H957-HA Fan Assembly
1-H957-EA Mounting Panel Door (Plenum) Rear Mounting (Left Hanging)
1-H952-EA Caster Set (4)
1---H952-FA Leveler Set (4)
1-74-6793 Kickplate
I-H957-LA Logo Frame Panel
1-H957-SA Filter
I-H957-GA Filler Strip Set (3) Front, Rear and Top
1-H957-HA Fan Assembly
1-H954-CA Fan Assembly (Bottom Mounted)
See Special Considerations Section 14
Cabinet K-List Price-$365.00
Cabinet Specials
Non-standard cabinet configurations are made to order by using the two
basic cabinet frame assemblies-H950-AA (68 25/32" x 25" x 63"),
H954-AC (49 8/16" x 25" x 42 1/16") and H957-AA (47 12/16/1 x 25" x
42")
It is recommended that all cabinet specials have the following basic parts:
1. H950 Series Cabinet
A-H950-AA-Frame (71 7/16" height w/casters x 25" x 63")
B-H952-EA Caster Set (4)
C-H952-FA Leveler Set (4)
A-H954-AC Frame (51 12/16" height w/casters x 25" x 42")
B-H952-EA Caster Set (4)
C-H952-FA Leveler Set (4)
D-H954-UA Cabinet Cover
A-H957-AA Frame (50" height wI casters x 25" x 42")
B-H952-EA-Caster Set (4)
C-H952FA Leveler Set (4)
Consult H950, H954 and H957 Cabinet Parts List to complete special cabinet
configuration. Cabinets are shipped assembled.
403
Special Considerations
Before ordering a cabinet, the following should be considered:
If logo frame H950LA or H950LB is used, short doors and! or cover
panels H950P (5 114 ")-H950Q (101h") can be used for cabinet front
mounting.
2. When ordering a cabinet to add to an existing system with a H950AA
frame assembly, or in joining two or more cabinets front and rear, filler
strip H952-GA is used. (See Cabinet F and Cabinet K.)
3. If power supplies with meters or switches are mounted to the rear
mounting panel, (plenum) door H950DA (RH) or H950EA (LH), a full
door H950DA (RH) or H950LA (LH) is needed. (See Cabinet C.)
4. The mounting panel door skin 950FA bolts to the plenum door H950
DA (RH) or H950EA (LH) and is used in place of a full door when
hardware mounted to the plenum door (mounting panel door) does not
require servicing. (See Cabinet B, E, and F.)
1.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
When using stabilizer feet H952-BA, the kickplate #7406782 (lower cab
trim) is used. If short doors are used, special mounting is required.
When using fan assembly, indicate direction of airflow (up or down).
When using short doors, make certain that the equipment for cabinet
installation wilt not interfere with door height.
The filter H950SA for use with H952-CA fan assembly should be ordered
only for fans that are to be used for airflow intake.
Fan assembly specifications for H952-CA, H954-CA and H957-AA are
500 CFM.
H952-EA casters add 2 4/16" to cabinet frame assembly height.
H950AA-Gabinet frame height wI casters-71 7/16".
H954-AC-Gabinet frame height w/casters-51 12/16".
H957-AA~Cabinet frame height w/casters is 50".
Short doors H950'HA (21 ") through H950HK (63") series-Dimen
sions of the doors listed in Parts List only cover mounting panel height;
e.g., the H950AA cabinet frame has 63" mounting panel height. Using
a H950'HA (21") short door would leave 42" of mounting panel space.
Doors for rear mounting are listed as right hanging in Cabinets A, B, C,
0, E. Left hanging doors may be substituted by changing suffix letters
as listed in Parts List.
Key: (RH)-Right Hanging
(LH) Left Hanging
The H950LA Logo Frame Panel is an aluminum extrusion that can be
supplied with a blank adhesive inlay strip in assorted color combina
tions. "When the inlay strip is ordered as part of a cabinet, there is no
charge for the inlay. Inlay strips ordered separately are priced at $15.00
each." The adhesive inlay strip designed for PDp-8/ E, PDp-ll require
the H950LB Logo Frame or H957-LA.
1. Adhesive inlay color strip available for use with H950LA frame panel
a. Brown/Yellow
b. Navy Blue! Bright Copen Blue
c. Bright Chartreuse/ Lime Peel
2. Adhesive inlay color strips available for use with H950LB panel.
a. Terra Cotta/ Amber
b. Magenta! Bright Rose
The Fan Assy. H957-HA may be mounted on top of rear frame or rear
mounting door. When mounted to bottom of frame or mounting panel
door, a bottom cover plate H957-JA must be used for upward air flow
through cabinet.
404
Color
Basic color of cabinet hardware is black. Gray is used for end panels and
the inlay of the cover panels.
Customized painting will be accepted with a minimum lot release of 10
cabinets at an extra charge of $10 per cabinet painted. The customer must
supply a color chip for color desired. DEC will not inventory custom painted
cabinets without special consideration.
Order should be sent to Module Marketing Services. No cabinet hardware will
be accepted for creditor exchange without the prior written approval of DEC,
and without the proper return authorization number (RA#). No cabinet returns are accepted on special paint orders.
Prices do not include state or local taxes. Prices, discounts, and specifica
tions are subject to change without notice.
Cabinet Discount Schedule
The following discount schedule is for cabinet purchases only. The discount
is computed from the total list price of cabinet parts purchased. On blanket
purchase orders, minimum releases of ten units (cabinets) or balance is
required.
Sale In Dollars
Discount
8%
12%
20%
25%
26%
28%
30%
$ 500 - $ 999
1000 1500 2500 5000 7500
$10;000 .
1499
2499
4999
7499
9999
And up
PARTS AND PRICE LIST

Catalog No.
H950 SERIES CABINET
Description
List Price
H950-AA
Frame, 19" wide, 69" hi, 25" deep, ........................ $163.00

63" mounting panel, includes mounting hardware.
H950-BA
Full Door (RH), front and rear door mounting........
47.00
H950-CA
Full Door (LH), front and rear door mounting ........
47.00
H950-DA
Mounting Panel (Plenum) Door, (RH) rear ............

mounting
47.00
H950-EA
Mounting Panel (Plenum) Door, (LH) rear mounting
47.00
H950 FA
Mounting Panel Door Skin ......................................
20.00
H950HA
Short Door (covers 21" mounting)
48.00
405
H950-HB
Short Door (covers 22 3;4" mounting) ................... .
48.00
H950-HC
Short Door (covers 26%" mounting) ................... .
48.00
H950-HD
Short Door (covers 31 2" mounting) .................. ..
48.00
H950-HE
Short Door (covers 36%" mounting) ............. : .... ..
48.00
H950-HF
Short Door (covers 42" mounting) ....................... .
48.00
H950-HG
Short Door (covers 47 1;4" mounting) ................... .
48.00
950-HH
Short Door (covers 522" mounting)
48.00
H950-HJ
Short Door (covers 57 3;4" mounting)
48.00
H950-HK
Short Door (covers 63 "mounting) ...................... ..
48.00
H950-G
Table Top Assembly (19" wide, 21 7/32" x 1 3;4")
50.00
H950-LA
Frame Panel Aluminum ........................................ .
9.00
H950-LB
Frame Panel. Plastic ............................................. ..
7.00
H950-PA
5 1;4 /I Bezel Cover Panel ....................................... ..
8.00
H950-QA
10Yl" Bezel Cover Panel ...................................... ..
11.00
H950-SA
Filter (for Fan Assembly) ....................................... .
4.00
*H952-AA
End Panel (require 2 per cabinet) ......................... .
57.00
H952-BA
Stabilizer Feet (pair) ............................................... .
23.00
H952-CA
Fan Assembly (specify airflow), top mounted ......... .
40.00
H952-EA
Caster Set (4) ......................................................... .
7.00
H952-FA
leveler Set (4) .................... , ................................ ..
2.00
H952-GA
Filler Strip (front and rear), jOining two cabinets .. ..
44.00
7406782
Kickplate (use with H952-BA) ............................... .
5.00
7406793
Kickplate (Lower Cab Trim) .................................. ..
8.00
12-9154
Mounting Slides .............. ,.', ..... ' ................. ,..... ,.. ,.. .
25.00
12-9703
Tilt Slides ., ........ ,....... ,... ' ..... ', .. ,." .... ' ...................... .
52.00
70-5909
AC Distribution Panel ............................................ ..
50.00
406
PART DESIGNATIONS
H950 SERIES CABINET
1. Frame
2.
3.
4.
5.
-...I
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Full Door
Mounting Panel (Plenum) Door
Short Door
Table Top Assembly (19" wide,
21%2" x 1%")
Frame Panel
5~" Bezel Cover Panel
10!t!" Bezel Cover Panel
End Panel (require 2 per cabinet)
Stabilizer Feet (pair)
Fan Assembly (specific airflow),
top mounted
Caster Set
Leveler Set
Filler Strip (front & rear), joining
two cabinets
Slides
Kickplate
~IO
--~
71-7/16"
* CENTER
MOUNTING HOLES
TO CENTER ALL SIDES
18-5/16"
H950 CABINET DIMENSIONS
408
Rear view of H950 frame.
Front view of H950 frame.
409

H954 -
Catalos No.
H954-AC
SERIES CABINET
Description
Ust Price
Frame, 19" wide, 49 8/16" high, .......................... $160.00

25" deep, 42" mounting panel,
H954-BA
Full Door, rear mounting (RH) ............................. ..
65.00
H954-CA
Fan Assembly 500 CFM (bottom mounted) .......... ..
85.00
H954-SA
Filter (use with H954-CA) .................................... ..
3.00
H954-UA
Cabinet Cover .............. :.......................................... .
65.00
*H952-AM
End Panel (require 2 per cabinet) ........................ ..
50.00
H950-LB
Logo Frame Panel ................................................ ..
7.00
H952-BA
Stabilizer Feet (pair) .............................................. ..
23.00
H952-EA
Caster Set (4) ......................................................... .
7.00
H952-FA
Leveler Set (4) ....................................................... .
2.00
H950-HA
Short Door (covers. 21" mounting) ....................... .
48.00
H950-HB
Short Door (covers 22 3,4" mounting)
48.00
H950-HC
Short Door (covers 26%" mounting)
48.00
H950-HD
Short Door (covers 31 %" mounting) .............. ......
48.00
H950-HE
Short Door (covers 36 3,4" mounting) ......................
48.00
H950-HF
Short Door (covers 42" mounting) ........................
48.00
H950-PA
5 %" Bezel Cover Panel ..........................................
8.00
H950-QA
.10%" Bezel Cover Panel........................................
11.00
7406782
Kickplate (use with H952-BA) ................................
6.00
7406793
Kickplate (Lower Cab Trim) ....................................
8.00
Prices and discounts shown are subject to change without notice.

Color of end panel is gray. Consult color section for customized painting.
410
PART DESIGNATIONS
H954 SERIES CABINET
-I:ao
....
....
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Frame
Full Door
Fan Assembly
Cabinet Cover
End Panel
Logo Frame Pane'
Stabilizer Feet
Caster 'Set
Leveler Set
Short Door
5 ~" Bezel Cover Panel
1014" Bezel Cover Panel
Kickplate
Slides
~I
II
" II
14
T
42-1116"
51-'2116"
'8-5/16"**
* EFFECTIVE
MOUNTING SPACE IS
37-1116" DUE TO 5" CLEARANCE
NEEDED FOR FAN ASSEMBLY
** CENTER
MOUNTING HOLES 18-5116"
TO CENTER ALL SIDES
412

H957 SERIES CABINET
CATALOG NO.
H957-AA
H957-BA
H957CA
H957-DA
H957-EA
H950-HA
H950-HB
H950-HC
H950-HD
H950-HE
H950-HF
H950-PA
H950-QA
H952-BA
H952-EA
H952-FA
H957-FA
H957-FB
H957-GA
H957-HA
H957-JA
H957-LA
H957-SA
74-06782
74-06793
DESCRIPTION
LIST PRICE
Frame 19" Wide 47 8/16" High 25" Deep, ....... . $142.00

47" Mounting Panel includes Mounting
Hardware
Full Door Rear Mounting (Right Hanging) ......... .
60.00
Full Door Rear Mounting (Left Hanging) ........... .
60.00
Mounting Panel Door Rear Mounting Plenum ... .
36.00
(Right Hanging)
Mounting Panel Door Rear Mounting Plenum
36.00
(Left Hanging)
Short Door (Covers 21/1 Mounting) .............. .
48.00
Short Door (Covers 22 3,4" Mounting) ........... ..
48.00
Short Door (Covers 26 1,4 II Mounting) ........ ..
48.00
Short Door (Covers 31 %" Mounting) ......... ..
48.00
Short Door (Covers 36 3,4" Mounting) ......... ..
48.00
Short Door (Covers 42" Mounting) ................ .
48.00
5%" Bezel Cover Panel
............. .
8.00
10%" Bezel Cover Panel ..................... .
11.00
Stabilizer Feet (Pair) ..........
.. .......... ..
23.00
Caster .Set (4) .................................................. ..
7.00
Leveler Set (4) ..........
.. .......... ..
2.00
End Panel (Right Hanging) .............. .
63.00
End Panel (Left Hanging) .................................. .
63.00
Filler Strip ~et (3) Top, Front and Rear ............. .
36.00
Fan Assembly (500 CFM) ........
50.00
Bottom Cover Plate ... .
9.00
Logo Frame Panel .............................. .
20.00
Filter ............................................... ..
4.00
Kickplate (use with H952-BA) ........ .
6.00
Kickplate (Lower Cabinet Trim) .. .
8.00
413
fi
ii!l
()
BJ
I
============ln~~~~::::==~I\~\---~B
i
PART DESIGNATIONS
2
H957 SERIES CABINET
1. Frame
'!!
~
2. Full Door
3. Door Mounting Panel
4. Short Door
5.
6.
7.
8.
9.
10.
U.
12.
13.
Logo Frame Panel

5lh II Bezel Cover Panel
10lh" Bezel Cover Panel
End Panel
Stabilizer Feet
Fan Assemblies
Caster Set
leveler Set
Filler Strip Set
47-8/16"
* EFFECTIVE
MOUNTING SPACE IS
37-tl16" DUE TO 5" CLEARANCE
NEEDED FOR FAN ASSEMBLY
** MOUNTING HOLES 18-5/16"
CENTER TO CENTER ALL SIDES
415
8811
,--_SY_S_T_EM_I_N_TE_R_F_A_CI_N_G_U_N_I_T_--,
L::J
The 8811 is a prewired system uni: used for general interfacing. It consists
of three 288-pin blocks assembled end-to-end in a casting which can be
mounted in the basic PDP-II box or extension box. Six of the module slots
are used for bus and power connectors. These slots are:
416
POWERA3
UNIBUSAIBI and A4B4
+5 Volts to all A2 pins
-15 Volts to all B2 pins (except in slots AI,
B1, A4 and 84)
Ground to all C2 and T1 pins.
BB11 POWER PIN ASSIGNMENTS
PIN
POWER
Al
-15V
+5V
-I5V
-15V
A2
Bl
.B2
CI
C2
01
02
El
E2
Fl
F2
HI
H2
Jl
J2
Kl
K2
II
l2
Ml
M2
NI
N2
PI
P2
Rl
R2
Sl
S2
Tl
T2
Ul
U2
VI
V2
-I5V
GND
-15V
GND
-15V
GND
-15V
GND
-15V
+5V
-15V
+5V
-15V
+5V
-15V
+5V
-15V
. +5V
GND
-25V
GND
LTC l
GND
ACLO L
GND
DClO l
GND
+8V
GND
+8V
GND
+8V
NOTE
POWER IS IN MODULE SLOT A3 OF All SYSTEM
UNITS MOUNTED IN BAll MOUNTING BOXES
EQUIPPED WITH H720 POWER SUPPLIES.
417
WIRE WRAPPING SERVICE

The electronics industry has long been aware of the many advantages of
wire wrapping over soldering for interconnecting electronic circuits. Soldering
introduces numerous human errors and presents problems of cold solder
joints, flux removal and overheating sensitive components. Automatic,
computer-controlled wire wrapping, however, not only eliminates the problems associated with soldering but adds many technical and economic benefits unattainable with soldering. Automatic wire wrapping provides extremely
high reliability, high production rates, elimination of human error, long-life
connections, simple mechanical inspection techniques, high density wiring,
rework ability, reduced labor and reduced inspecting time.
Digital Equipment Corporation has developed an extensive high-production
wire wrapping capability and offers to its customers the significant cost
savings of automatic wire wrapping. Digital can provide a full wire wrapping
service and our "Smooth-Flo" processing insures control at each step in the
process.
DIGITAL automatically verifies the corr~ctness of the wiring on each panel
with its computer-controlled Automatic Wire Test equipment. This verification
is a standard part of DIGITAL's wire wrapping service and is provided at no
charge. The only restriction is that the size of the panel be limited to four
connector blocks high by ten connect6r blocks wide. No price reduction is
given for elimination of the verification service.
For additional information on DIGITAL's wire wrap service, write for wire
wrap data sheets available from Logic Products, Digital Equipment Corporation, Maynard, Massachu.setts 01754.
Customer Requirements
A wire listing prepared by the customer on Digital Form DR22A must accompany the purchase order, specifying which mounting panels are being purchased. In addition, if any s(:ecial bussing is needed, a copy of the updated
bussing diagram must also accompany the purchase order. It is extremely
important that complete wire listing and bussing information be received
with each order. Pricing of a wire wrapping order cannot be completed until
the source deck has been processed and buss print received. These are
needed to determine wire count and number of points to be bussed.
For the purpose of identifying specific pins and module slots for wire listings,
the panels or connectors are viewed from the wiring side as shown.
The wiring list is compiled from the logic design diagrams together with
module utilization charts. The pin numbers, signal names and logic module
type are specified for each of the logic functions on the diagram as shown;
The location of a module and the utilization of each of the logic functions
are compiled on the Module Utilization drawing. These drawings prevent the
use of the same logic circuit more than once.
418
~Mt~ _ _ _
LOGIC DESIGN DIAGRAM
SLOT-Ot
02
-------
04
03
T
A
2
-A_
M206 Mtl3
.1(.
A-
- P
- N
p R _
5
T
U - U - V
t V 2
t
2
#803 CONNEC'roR
B -
F
F
H
J
J
1C
L L
- M
M - N - N
- p
p R
- 5
5 T
T
U
U
t V
t V 2
MODULE UTILIZATION DIAGRAM
" ..
PIN LOCATIONS
(WIRING SlOE SHOWN)
419
A.
C
0
- M
R.
5 T -
MH2
- - - -
- M
M50f
04
03
1 A 2
_
8
B
C
- C C
0
D- E - E E
F
F
H
H
H
J
J
_ L _ K
A 1C_ L
_
02
Ot
t
Wire .Iisting form DR22A should be filled out in the following manner to
facilitate processing:
DR22A for LOGIC 1
A
SIGNAL
NAMES
Run Clock
Data Set
Run 1
Run 0
GOSW
RUN PIN
LINE NO.
OR REMARKS
DR22A
LINE NO.
A02Cl
AOID2
B04Cl
AOICI
AOIEI
A0281
AOIFI
A02F2
B02F2
A02J2
Column Designations
A. 'Signal-Identifies a particular run and can be any alphanumeric character
.up to a maximum of 22 characters.
NOTE: 1. Only one name may be used for a particular wire run
2. Like signals should be combined if on different sheets, or
they will be combined later by computer processing.
B. Run Pin-Four or five digits (see Absolute Pin Identification) lists the
..address of each pin in a wire run. (May express maximum of 65 pins for
anyone run.) These addresses do not have to appear in order and, along
with their signal name, can be on separate sheets.
C. Remarks and Line Number-Available for convenience of user and need
not be filled in.
SPECIAL SERVICES
The customer will receive one copy each of the Name Sort and Pin Sort lists
at no charge.
DIGITAL will perform special bussing where required. The rate for this is
$0.20 (including the cost of the buss strip) per point.
Delivery
The normal delivery time for wire wrapped panels is two to four weeks after
receipt of the purchase order, accurate source inputs (card or wire list), and
updated bussing diagram if special bussing is required.
On repeat orders for the same panels and wiring configuration, normal de
livery time is often reduced to almost half that of initial processing time.
420
..
PRICING
*30 gao Setup Charge
$125.00
*24 gao Setup Charge
175.00
30 gao Wirel Cost per Wire (2 connections)
.30
24 gao Wirel Cost per Wire (2 connections)
.25
.20 per point for special bussing, including buss strip

... One time charges are not discountable
421
H850, H852, H853

MODULE ACCESSORIES
SUPPORT
HARDWARE
H850 HANDLE EXTENDER
The H850 Handle Extender mounts over the existing handle of a standard
height module to provide compatibility with the 8lh inch extended modules.
When using two or more W940, W941, W942, W943, W950 or W951 boards
in parallel in logic connector blocks, rigidity of the boards is maintained by
using the H852 rib type holder between board handles 1 and 2, 3 and 4, and
using the H853 nonrib type holder between board handles 2 and 3.
H850 - $10.00
H852 (pkg/25) - $7.00
H853 (pkg/25) - $7.00
422
932, 933, ,934, 935, 936, 939

H810, H810D, H810E, H811,
H812, H813, H814
ACCESSORIES
WIRING ACCESSORIES
932 BUS STRIP
Simplifies wiring of register pulse busses, power, and grounds. Same as used
in K943 with H800 blocks.
932-$0.60
933 BUS STRIP
Simplifies wiring of power, ground and signal busses on mounting panels using
H803 connectors.
933-$1
934 WIRE WRAPPING WIRE
1000 ft. roll of 24 gauge solid wire with tough, cut-resistant insulation. (Use
Teflon insulated wire instead for soldering.)
934 - $50
For use with H800 connectors.
423
935 WIREWRAPPING WIRE
1000 foot roll or 30 gauge insulated solid wire for use with H803 connectors.
935-$60
939 BUS 'STRIP

For use with H808 connectors.
939-$1
H810 PISTOL GRIP HAND WIRE WRAPPING TOOL
424
The type H8l0 Wire Wrapping Tool is designed for wrapping #24 solid wire
on Digital-type connector pins. The H8l0 Kit includes the proper sleeves and
bits. It is recommended that five turns of bare wire be wrapped on these
pins. This tool may also be purchased from Gardner-Denver Co. (GardnerDenver part No. l4H-lC) with No. 26263 bit and No. lB840 sleeve for wrapping # 24 wire. When ordering from Digital specify the sleeve and bit size
desired for # 24 wire.
HBlO(24) - $ 99
30 gao HB10A - $ 99
30 and 24 gao H8l0:B ~ $150
The Type HBll Hand Wrapping tool is useful for service or repair applications. It is designed for wrapping # 24 solid wire on DEC Type HBOO-W and
H808 connector pins.
Wire wrapped connections may be removed with the Type H8l2 Hand Unwrapping tool.
The HB1l-A and HB12A are equivalent to the HB1l and the H8l2 except that
the A versions are designed for #30 wire. The HB13 is a #24 bit; H813-A,
a # 30 bit. The HB14 is a # 24 sleeve; HB14-A, a # 30 sleeve.
None of the Wire Wrapping Tools will be accepted for credit under any
circumstances.
HBll(24) H81l-A(30) H812(24) HBI2-A(30) H813(24) -H813-A(30) HBI4(24) H814-A(30) 425
$24
$24
$10
$10
$30
$30
$21
$21
The Battery Powered Wire Wrap Gun is equipped with a rechargeable Nickel
cadmium battery and requires no ac power connection while in use. The gun
is available with a 24 gauge sleeve and bit (810-C). a 30 gauge sleeve and
bit (810-0) and without the sleeve and bit (H8l0-E).
Also available from Gardner Denver Co. Model 14R2 (Battery Powered Gun)
with No. 507063 bit (H813A) and No. 507100 sleeve (H814A)
H810-C H8l0D H8l0-E 426
$150
$150
$100
913, 914,915, 917

H820, H821, H825, H826
WIRING ACCESSORIES
ACCESSORIES
913 AND 915 PATCHCORDS

These patchcords provide slip-on connections for FLIP CHIP mounting panels
and are available in color-coded lengths of 2, 3, 4, 6, 8, 12, 16, 24, 32, 48,
and 64 inches. All cords are shipped in quantities of 100 in handy polystyrene
boxes. Type 913 patchcords are for 24 gauge wirewrap and use ~MP Terminal
Type #60530-1. Type 915 patchcords are for 30 gauge wirewrap and use
AMP Terminal Type #85952-3.
PATCHCORD COlOR-CODE
Size
2"
3"
4"
6"
8"
12"
Color
brown
black/white
red
red/white
orange
orange/white
Size
16/1
24"
32"
48"
64"
Color
yellow
yellow/white
green
green/white
blue
H820 AND H821 GRIP CLIPS FOR SlIPON PATCHCORDS

The type H820 and H821 GRIP CLIPS are identical to slip-on connectors used
in respectively the 913 and 915 patchcords. These connectors are shipped in
packages of 1000 and permit fabrication of patchcords to any desired length.
H820 GRIP CLIPS will take size 24-20 awg. wire. H821 GRIP CLIPS will take
size 30-24 awg. wire.
427
H825 HAND CRIMPING TOOL

Type H825 hand crimping tool may be used to crimp the type H820 GRIP
CLIP connectors. Use of this tool insures a good electrical connection. This
tool may also be obtained from AMP, Inc. as AMP part #90084.
H826 HAND CRIMPING TOOL
Type H826 hand crimping tool may be used to crimp the type H821 GRIP
CLIP connectors.
914 POWER JUMPERS

For interconnections between power supplies, mounting panels, and logic
lab panels, these jumpers use AMP "Faston" receptacles series 250. Specify
914-7 for interconnecting adjacent mounting panels, or 914-19 for other runs
of up to 19 inches. 914-7 contains 10 jumpers per package; 914-19 contains
10 jumpers per package.
428
917 DAISY CHAIN

Type 917 is a continuous length of unbroken # 25 AWG stranded wire. 250
gold plated and insulated terminals are crimped at predetermineg intervals
on each reel. In conjunction with type H803 or type H807 connector blocks
and M Series modules, hand patch wiring of prototype systems is easily and
quickly accomplished. All that is required is a reel of type 917 Daisy Chain
and wire cutters. These dependable push on connections are also easily
removable, making this wiring technique ideal in cases where wiring and
unwiring for changing systems needs is required. If ever a third lead is
necessary a type 915 patchcord can be used if placed on the pin before the
Type 917 termination. Two contact spacings available at 2% II or 5".
917 -
2.5 -
917 -
blue
white
Also available from:

Berg Electronics
New Cumberland, Pa. 17070
Tel. (717) 938-6711
$ 25 pkg. of 100
4 pkg_ of 10
$ 4 pkg. of 10
$ 33 pkg. of 100
H820 - $ 48 pkg. of 1000
H821- $ 98 pkg. of 1000
H825 -$146
H826-$210
913 -
914-7 914-19 915 -
429
430
431
""'-_ _ _
C_OM_PU_T_E_R_LA_B_ _ _.....,II
S~~S
The COMPUTER LAB is a high performance low-cost dig;tal logic trainer.

It uses the same monolithic integrated transistor-transistor logic circuitry
used in DIGITAL's latest computers.
The digital logic fundamentals presented by the COMPUTER LAB can foster
a basic understanding of computer technology for the computer career
oriented user, or for a user applying computers for the first time. The COMPUTER LAB will a,lso help the math-oriented user understand "new math"
concepts, as computer logic operates with binary numbers according to
Boolean algebraic laws.
Wiring is easy because of the standard logic symbology used on the front
panel and the color coded Patchcords which are easily inserted and removed.
An improper circuit will not damage the COMPUTER LAB. The faulty circuit
'merely "waits" for correction.
Features:
Transistor-Transistor logic circuitry as used in DIGITAL's PDP computers
Teaches modern computer logic
Easy to use: MILSTD 806 logic symbology on front panel
Portable: Dimensions of 12 112" x 17" x 3 1,4", weighing only 11 Ibs.
Comprehensive Workbook provides:
-Ten detailed chapters
-More than 30 experiments
-Over 200 hours of laboratory study
-Dozens of tables and diagrams
-An extensive appendix of supplementary information
Instructor's Guide with answers, additional text, extra problems, course
plans, at only $5.00
1.ow cost: COMPUTER LAB, Workbook and Patchcord set, ready to use
H500-$375
H500A*- $375
*220v
QUANTITY
NET PRICE! EACH
2-9
10-19
$350
325
432
434
KSERIES LOGIC LAB
LAB
SERIES
INTRODUCTION
The K Series logic laboratory is designed for use wIth K Series Modules.: It
is a device for building prototype systems for experimentation and proof of
logic design as well as an effective tool for learning solid state control logic.
It is excellent for training users in digital logic techniques by enabling an
individual to construct logical networks, with a "hands on approach" to
learning control systems for Industrial Applications.
The K Series Logic Lab is a completely self contained system consisting of a
power supply, photo cell, pulse generator, switch controls, indicators, mounting hardware and a recommended basic complement .of logic modules necessary to construct a working system. The system is expandable and can
accommodate additional K901 patchboard panels for mounting additional
logiC modules.
EDUCATION AND TRAINING

As a training device the K Series LogiC Lab offers the engineer, technician,
and user a step by step approach to building an understanding of various
digital logic functions, such as, AND, OR and the operations of NAND and
NOR etc. The user has the option of using NEMA or MIL spec symbology
when making logic connections. Symbology cards on basic logic modules for
use with the K901 patchboard panel are printed with NEMA on one side and
MIL SPEC 806 on the reverse side.
BREADBOARDING AND TESTING
The logic laboratory power supply is capable of supplying 5V-OCfor about

lOO modules. There is no restriction on the size of a system which can be
implemented, since additional patchboard panels can be ordered and 14K"
Logic Laboratories interconneCted directly.
There is no substitute for actually building the system and verifying the logic.
Some common uses of the Logic Laboratory are listed below. Many of these
are described in detail in the Control Handbook and part III in the 1969
Posttive Edition Logic Handbook.
Timer Sequencers
Shifter Sequencers
Parallel Counters
Pulse Rate Multiplier
Serial Adder
Stepping Motors Control
Pulse Generator
Annunciator
435
IWl
K900
I.....-.,C_O_NT_R_O_L_P_A_N_EL_-_PO_W_E_R_S_U_P_P_LY_.
The K900 is a combination power supply and input control panel. The input
devices include a photocell, three push button pulsers and timing components
for a K303 clock mounted in a K901 panel. Clock timing components are pro
'vided for frequency steps in ranges of 2Hz to 60Hz and 200Hz to 6K Hz~ Wiring
diagrams for properly connecting the clock are shown in the logic and control
handbooks (reference K303). The power supply can drive approximately ten
type K901 panels of K series flip chipTM logic. Pulsers consist of a K501 schmitt
trigger with a K581 switch filter. Power is supplied by K731, K743 and K732
power supply modules.
Electrical Characteristics
Input voltage: Power supply: 115V 5060 cps
Output voltage: + 5 VDC 10%
Output current: 3 amp
Mechanical Characteristics
Power Output connection: Hayman Tab
Panel width: 19"
Panel height: ~6"
terminals which fit AMP "Faston" reDepth: 12"
ceptacle series 250, part 41774 or ..Type
914 Power Jumpers.
Finish: black
Power Unit connection: 18/3 AC power cord
K900-$185
436
K901, 911
LAB
SERIES
PATCH BOARD PANEL
K901 PATCHCORD MOUNTING PANEL

This panel provides up to ten FLIP CHIP modules with power and patch connections. Space between patching sockets allows insertion of logic diagrams.
Logic diagrams are printed on all FLIP CHIP module data sheets. More permanent plastic diagrams are available for those modules listed.
PANEL WIDTH: 19 in.
PANEL HEIGHT: 5!6 in.
DEPTH: 6~ in. with FLIP CHIP modules inserted
FINISH: Black
POWER INPUT CONNECTIONS: Tabs which fit
AMP "Faston" receptacle
series 250, part 41774.
911 PATCHCORDS
DEC Type 911 BananaJack Patchcords are supplied in color-coded lengths of
2 in. (brown), 4 in. (red), 8 in. (orange), 16 in. (yellow), 32 in. (green), and
64 in. (blue). Patchcords may be stacked to permit multiple connections at any
circuit point on the graphic panels of the DEC K901 Mounting Panel. The cords
are supplied in snaplid plastic boxes of ten for handy storage.
K901-$125
911 437
$9/pkg. of 10
K902
LAB
INDICATOR SWITCH PANEL
SERIES
The H902 Panel provides facilities for control and observation of the Logic
Laboratory. It contains eight indicator lights and a lamp driver module, eight
toggle switches and four potentiometers. Connections to these devices are
made with Type 911 Stacking BananaJack Patchcords.
INDICATORS: Indicators inputs accepts signals of +5V and ground. An open
circuit input will light the indicator. If the input is returned to ground, the
indicator will not light. The load is 1 rnA.
TOGGLE SWITCHES: The toggle switches are single pole, single throw with
a logic diagram to show the open and closed positions.
POTENTIOMETERS: The potentiometers are 250,000 ohms. They may be used
to control the frequency of delay one-shots or clock circuits in the K901
Mounting Panel.
PANEL WIDTH: 19 in.

PANEL HEIGHT: 53m in.
DEPTH: 6% in.
FINISH: Bhick
AMP "Faston" receptacle series 250, part 41774.
K902-$145
438
K903
PATCH PANEL BOARD
~
~
This patch panel provides logic power and patch connections for four doubleheight or eight single height FLlPCHIP modules. The panel was designed
particularly for K Series double height modules including the interfacing
modules (K5xx and K6xx). Two K903 panels cannot however be mounted
together on a mounting rack due to socket overhang at the bottom of each
K9()3 panel. Space between patching sockets allows insertion of logic dia
grams. Logic diagrams are printed on all FLlPCHIP module data sheets.
More permanent plastic diagrams are available for those modules listed.
PANEL WIDTH: 19 in.
PANEL HEIGHT: 5~6 in.
DEPTH: 6Y2 in. with FLlPCHIP modules inserted.
FINISH: Black
AMP "Faston" receptacle series 250, part 41774
K903-$155
439
4913,914
LAB
MISCELLANEOUS ACCESSORIES
SERIES
4913 MOUNTING RACK

The 4913 Mounting Rack provides support for a and up to four K901 Patchcord Mounting Panels, for a total of up to 40 FLIP CHIP modules ready to be
patched together for experiments. It may also be used to mount general purpose mounting panels such as the K943. The power supply must be mounted
at the bottom for stability.
Height: 26% in. Threads for mounting panels: 10-32
914 POWER JUMPERS

For interconnections between power supplies, mounting panels, and logic lab
panels, these jumpers use AMP "Faston" receptacles series 250. Specify 914-7
for interconnecting adjacent mounting panels, or 914-19 for other runs of up
to 19 inches. 914-7 contains 10 jumpers; 914-19 contains 5.
4913 -$25
914-7 - $ 4
914-19-$ 4
440
BASIC EQUIPMENT LISTS

BASIC LOGIC LABORATORY
'IK901
IK902
Patchboard panel
Indicator Switch Panel
(complete with K683 module)
Power Supply and Control Panel
(complete with Power modules)
Mounting Rack
1K900
1 pair-4913
125.00
145.00
lS5.00
25.00
RECOMMENDED LOGIC MODULES AND PATCHCORDS

FOR USE WITH THE LOGIC LA~ORATORY
4K003
2K012
3K113
3K123
2K134
IK161
IK174
IKl84
2K202
IK206
2K210
IK220
IK230
IK303
IK323
IK376*
IK37S*
IK373*
IK522
Expander
Expander
Gate
Gate
Inverter
Decoder
Comparator
Rate Multiplier
Flipflop
Flipflop
Counter
Updown Counter
Shift Register
Timer
One shot delay
Timer Control (0.13.0 sec)
Timer Control (1.030 sec)
Timer Control (20 Hz600 Hz clock)
Sensor Converter
4 pks. of 10 patchcords
1 pkg. of 10 patchcords
26 symbology cards
(911-2")
(9114")
(911-16")
(91116")
UNIT PRICE
5.00
S.OO
11.00
12.00
13.00
25.00
24.00
25.00
27.00
20.00
27.00
55.00
40.00
27.00
35.00
15.00
15.00
11.00
25.00
9.00
9.00
9.00
9.00
.25 ea.
Comptete KSeries logic lab with workbook

and modules listed - H510
TOTAL PRICE
20.00
16.00
33.00
36.00
26.00
25.00
24.00
25.00
54.00
20.00
54.00
55.00
40.00
27.00
35.00
15.00
15.00
11.00
25.00
36.00
45.00
18.00
9.00
6.50
$995.00
Asterisk denotes symbology cards unavailable. Symbology cards for use with K901
patchboard panel, .25 ea., minimum purchase of $5.00 applies.
IF ADDITIONAL K901 PATCHBOARDS ARE ORDERED:

1911-4"
19118"
1-91116"
1:91132"
pkg.
pkg.
pkg.
pkg.
of
of
of
of
10
10
10
10
patchcords
patchcords
patchcords
patchcords
9.00
9.00
9.00
9.00
441
KSERIES INTERFACE MODULES

Recommended logic modules for input/ output functions.
AC InputlOutput
IK578
IK614
120 VAC Input converter

120 VAC Isolated AC switch
so. 00
88.00
DC Input/Output
IK580
28.00
Dry Contact Filter
listed below are a number of DC output drivers that may be used:
IK644
IK656
~K658
66.00
DC output Driver
or
DC output priver
or
80.00
128.00
DC output Driver
5.00
Each additional K series workbook
Note: only 3 out of 4 circuits are available when using above 3 modules with the K90J
. mounting panel.
Reference logic or control handbook for additional module information and selection.
A rear view of the K Series Logic Lab shows how modules are plugged into
mounting panels.
442
M SERIES lOGIC LAB
LAB
SERIES
Introduction
The M Series Logic Lab is a highly versatile unit that can be used succeessfully at all stages of digital logic design, from training, to experimentation, to
systems design, to final system checkout. It can be used to build prototype
logic systems or as a tool to test and design actual hardware. Educationally,
it provides the designer with a flexible system for experimentation as well as
a basic unit for learning the fundamentals of electronic circuitry and logic
design.
The logic Lab's exceptional training abilities stem mainly from the fact that
the student can design and actually construct his logic networks directly on
the unit. This provides valuable practical reinforcement of theoretical concepts.
The M Series Logic Lab is designed for use with any Series of DEC modules
which uses +5 Volts for power.
The M Series Logic Lab is a completely self-contained system, consi'Sting of a
power supply, lights, switches, and two racks of connector blocks. The system
is expandable and can accommodate an additional rack of connector blocks.
Education and Training
As a training device, the M Series Logic Lab offers the user an easy step-bystep way to gain an understanding of various. logic functions,- such as AND,
OR, NAND, NOR, etc. Because this tool is not limited to anyone technology,
it can be used to study not only TIL but also DTL, ECTL, and other types of
logic.
Breadboarding and Testing
The Logic Lab power supply can supply +5 V dc at 6.5 amps (max.). This
supplies sufficient current for systems using aI/ module slots.
The Logic Lab is an effective tool for bridging the gap between paper design
and a fully tested, marketable product.
Console
The Console consists of a light and a switch panel. The light panel is made
up of 80 lights arranged in four rows of 16 lamps and four roWs of four
lanips. The user can write designations on the panel adjacent to each lamp.
The switch panel has three groupings of switches-I6 on/ off-type switches,
two on/ off-type switches, and two pulsertype switches. This switch configuration provides highly versatile control.
Connector Racks
The M Series Logic Lab has two 19" racks of lowdensity H808 connector
blocks. Each rack contains eight connector blocks and each connector block
has four module slots; therefore, there are 32 module slots per rack for a
total of 64 module slots in the standard M Series Logic Lab. One additional
rack can be mounted increasing the available module slots to 96. Regardless
of how many racks are used, four slots must be dedicated to receiving flexprint cables from the switch and light panels.
443
Power bussing of pins A2. C2. Tl is also available as a standard item on the
rack of connector blocks.
CABLES
Switch Board (Switches are numbered from right to left)
SOPin
SIPin
52-Pin
. 53-Pin
54-Pin
55-Pin
56-Pin
57-Pin
58-Pin R2
59-Pin P2
SIO-Pin N2
511-Pin M2
512-Pin l2
S13-Pin K2
S14Pin J2
515-Pin H2
EI
01
CI
BI
V2
U2
T2
52
CI-Pin E2
C2Pin F2
PI-Pin Al
P2-Pin 02
Light Board
First letter of each title below designates the row of lights. lights are num'
bered on the indicator panel from right to left.
Second letter designates cable from indicator panel.
Third letter and associated number designates pin in a module slot used for
light function.
AO pin BVI
Al pin BJI
A2 pin Bll
A3 pin BPI
A4 pin BE2
AS pin BS2
A6 pin BF2
A7 pin CK2
A8 pin CE2
A9 pin CS2
AIO pin CN2
All pin CV2
Al2 pin CP2
Al3 pin CRI
Al4 pin CPI
A15 pin CNI
BO pin BUI
Bl pin BHI
B2 pin BF!
B3 pin BKI
B4 pin BR2
B5 pin BL2
B6 pin BM2
B7 pin BV2
B8 pin CR2
B9 pin CL2
BIO pin CU2
B11 pin CJ2
B12 pin C02
BI3 pin CSI
B14 pin CMl
B15 pin Cll
CO p'in BRI
Cl pin BMI
C2 pin BNI
C3 pin BEl
C4 pin BA1
C5 pin B02
C6 pin BK2
C7 pin BU2
C8 pin BJ2
C9 pin BP2
CIO pin CH2
CII pin CVI
C12. pin CUI
Cl3 pin CKI
Cl4 pin CHI
CIS pin COl
DO pin BSI
01 pin BBI
02 pin BCl
03 pin BOI
D4 pin BT2
05 pin BH2
06 pin BN2
07 pin CF2
08 pin CT2
09 pin CM2
010 pin CAl
011 pin CBI
012 pin CCI
013 pin eEl
014 pin CFl
015 pin CJ1
EO
E1
E2
E3
FO
FI
F2
F3
GO
GI
G2
G3
HO
HI
H2
H3
pin
pin
pin
pin
API
ARI
ANI
AAI
pin
pin
pin
pin
ASI
AUI
AMI
AC1
pin
pin
pin
pin
AJI
AKI
All
ABI
pin AHI
pin AF1
pin AEI
pin AD1
H520-A (240v./50Hz) ALSO AVAILABLE

For complete information, request M Series Data Sheets from logic Products,
Digital Equipment Corp., Maynard, Mass. 01754.
M Series Logic Lab H520 -
444
$995
M SERIES LOGIC LAB (REAR VIEW)
446
In approximately 15 years, Digital Equipment Corporation has grown from

three employees and one floor of production space in a converted woolen
mill, to a major international corporation. DEC now employs more than 7000.
Our products are manufactured in several plants, and are sold and serviced
from customer support centers in the United States, Canada, Japan, Australia
and seven European countries.
We produce a wide variety of computer and control products ranging from
logic modules to large time sharing computer systems. In addition to those
logic modules and associated equipment detailed in this handbook, DEC
also manufactures 12, 16, 18 and 36bit computers, peripheral devices,
special systems, accessories, programmable controllers and a wide variety
of software.
DEC first began manufacturing computerrelated equipment in 1957 when
we introduced a line of solid state logic modules. These were initially used
to test and build other manufacturers' electronic equipment. The logic module
product lines have been continually broadened, and DEC now ranks as the
world's largest manufacturing supplier of digital logic modules, producing
more than three million per year.
447
Our first computer, the PDP-I was introduced a decade ago, selling for
$120,000 while competitive machines were priced over $1 million. Ever
since the PDP-I, DEC has specialized in on-line, real-time computers.
The PDP-5, introduced in 1963, was the first truly small computer. The PDP-8
series, the PDP-5 successor announced in 1965, is one of the most popular
and successful families of computers ever produced.
DEC is a leading force,in small computers, but it also has been a pacesetter
in other parts of the industry. For example, one of the first time sharing
systems ever built incorporated a PDP-I. DEC introduced the first large-scale,
commercially available time sharing system in 1965-the PDP-6. Its successor, the PDP-10, can do more at a price well under $1 million than competitive systems costing several times as much.
With more than 15,000 computers now installed, DEC is the second largest
manufacturer in terms of installations.
In industry, DEC computers provide engineers with a powerful control and
testing tool. They control blast furnaces and open hearths, monitor slab mills
and finishing mills, and control and monitor a variety of machine tools,
transfer and material handling equipment. DEC computers assisted in the
analysis of lunar rock samples, guided the SS MANHATTAN as she sailed
the Northwest Passage, and are being used in testing the Boeing 747 jumbo
jet, and the Anglo-French Concorde supersonic airplane.
In science, our computers have cut the researchers experiment time with
direct, on-line data reduction. DEC computers control and monitor powerful
nuclear reactors, control X-ray diffractometers, and analyze nuclear spectroscopy data. They are used extensively in environmental research and
pollution control.
In virtually all DEC computer installations, DEC solid state logic is used for
interfacing or control application.
GENERAL INFORMATION
FINANCIAL RESULTS
Net Income (in millions)
Total Sales (in millions)

1971
1970
1969
1968
1967
1966
1971
1970
1969
1968
1967
1966
$ 146.8
$ 135.4
$ 91.2
$ 57.3
$ 38.8
$ 22.7
MAIN PLANT & CORPORATE HEADQUARTERS;

146 Main Street, Maynard, Massachusetts
(617) 897-5111
1,000,000 square feet
448
$ 10.6
$ 14.4
$ 9.4
$
$
6.8
4.5
1.9
OTHER MANUFACTURING FACILITIES

Carleton Place, Ont., Canada ........................................
40,000 square feet
Reading, England ..........................................................
25,000 square feet
San German, Puerto Rico ..............................................
58,000 square feet
Westfield, Mass. ............................................................ 260,000 square feet

Westminster, Mass. ......................... .... . ........................ 260,000 square feet
TOTAL EMPLOYEES ....................................................................... :........ 7,275
Sales, Service and Support ...... ............ ....... ............. ........... ..... .............. 1,945
Manufacturing ........................................................................................ 3,121
Engine~ring, Marketing, Programming ................. ~................................
850.
General and Administrative .............. ................ ......... ....... ..... ....... ..... ..... 1,359
PDP-8/ E
449
GENRAl DESCRIPTKlNS' Of DEC-PRODUCTS

(Excluding those discussed in this Handbook)
COMPUTERS
POP8/ E The lower cost successor to the PDP-S/I and PDP-Sf L. It is the
outgrowth of the largest concentration of minicomputer engineering, programming and user expertise in the world. Among the PDP-8/ E features are~
a unique internal bus system called OMNIBUSTM, which allows the user to
plug memory and processor options into any available slot location; the
availability of 256 words of read only or read/write memory; a 1.2 microsecond memory cycle time; the use of TTL integrated circuitry with medium
scale integration; expansion to 32,768 12-bit words; low cost mass storage
expansion with DECdisk or DECtape.
PDPl1 An expandable general purpose computer with 4,096 basic words of
standard core memory, each word 16 bits in length. Memory cycle time is
1.2 microseconds. Machine uses integrated circuitry and has some mediumscale integration in central processor.
POP12 Laboratory computer system capable of executing PDP-8 and LlNC-8
programs. It has basic 4,096word core memory. Each word is 12 bits in
length. Basic laboratory system includes interactive graphics capability,
magnetic tape storage, A/O converter, and pre-wired, real-time clock.
POP15 A medium-scale series with an 18-bit word length. Four basic versions: POP-15/10, POP-15/20, POP-15/30, POP-15/40, and PDP-15/50.
DECSYSTEMIO General purpose large computer with basic memory of 8,192
(36-bit) words, expandable to 262,144. Will handle up to 63 time-sharing
users simultaneously with batch and real-time jobs at the same time.
COMPUTER-BASED SYSTEMS
The following describes a sample of some of the hardware! software application systems available from DEC.
IDAC SYSTEM5--Small computer-based systems for industrial data acquisition, process control, data logging, process monitoring and quality testing,
uses simplified language designed for engineers, not programmers.
LAB-II and LAB-8/E Small computer-based data signal averaging systems
used in bio-medical, chemistry, and physics laboratories. Include software for
other functions.
TSS8 and RST5-11 Small computer-based general purpose time-sharing systems designed to accommodate up to 16 users with a variety of software for
many tasks.
TYPESET-8 Small computer-based system for setting type, producing punched
tape containing all hyphenation, justification and format commands needed
to set 12,000 liries of copy per hour.
CDP Small computer-based gas liquid chromatography system that will
. service 20 or more gas chromatographs simultaneously. It reduces and
analyzes data accurately, repetitively and economically.
CliNICALLAB12 Real-time, on-line multiterminal small computer system
designed to provide the clinical laboratory with an economical means of data
collection, data reduction, and analysis.
450
EDUCATIONAL SYSTEMS These systems include computer and a variety of

applications software. In the group are single language time-sharing systems
and hardware/ software calculator replacements.
DISPLAYS A variety of displays are available for all applications where the
speed and flexibility of graphic communications increase system efficiency.
SPECIAL SYSTEMS
DEC's special systems group custom builds hardware and software systems
for speCial applications.
SOFTWARE
A comprehensive line of software is available with DEC's hardware. Assem
biers, debugging routines, editors, monitors, ofloating pOint packages and
mathematical routines, diagnostic programs, are made available.
DEC has also developed such conversational, interpretive languages as:
FOCAL, an on-line language used as a tool by students, engineers and
scientists in solving a wide variety of numerical problems; and DIBOL, a
business-oriented computer language designed to bring the speed and power
of PDP-S family computers to small- and medium-size business establishments.
OPTIONS & PERIPHERALS
Analogi Digital converters, display and plotting equipment, drums and disks,
magnetic tape equipment, card equipment, line printers, teletypewriters and
many others.
SUPPLIES
Power supplies, cabinetry, mounting hardware, tape, tape reels, storage racks,
teletype ribbon and paper.
451
WARRANTY
WARRANTY I-B, R, W, M, K, AND A MODULES - All B, R, W, M, K, and A
modules as shown in the Logic Handbook and Control Handbook, as revised
from time to time, are warranted against defects in workmanship and material
under normal use and service for a period of ten years from date of shipment providing parts are available. DEC will repair or replace, at DEC's option,
any B, R, W, M, K, or A module found to be defective in workmanship or material within ten years of shipment for a handling charge of $5.00 or 10 per
cent of list price per unit, whichever is higher. Handling charges will be applicable from one year after delivery.
WARRANTY 2-SYSTEM MODULES, LABORATORY MODULES, HIGH CURRENT PULSE EQUIPMENT, G, S, H, AND NONCATALOG FLiP-CHIP MODULES
- All items referenced are warranted against defects in workmanship and
material under normal use and service for a period of one year from date of
shipment. DEC will repair or replace, at DEC's option, any of the above items
found to be defective in workmanship or material within one year of shipment. Repair charges will be applicable from one year after delivery with
repair charges varying depending on the complexity of the circuit.
The Module Warranty outside the continental U.S.A. is limited to repair of the
module and excludes shipping, customer's clearance or any other charges.
Modules must be returned prepaid to DEC. Transportation charges covering
the return of the repaired modules shall be paid by DEC except as indicated
in previous paragraph, and will be made on a UPS basis, where available,
or Parcel Post insured. Premium methods of shipment are available at customer's expense and will be used only when requested. If DEC selects the
carrier, DEC will not thereby assume any liability in connection with the
shipment nor shall the carrier be in any way construed to be the agent of
DEC. Please ship all units to:
Module Marketing Services
Repair Division
146 Main Street
Maynard, Mass. 01754
No module will be accepted for credit or exchange without the prior written
approval of DEC, plus proper Return Authorization Number (RA,#).
All shipments are F.O.B. Maynard, Massachusetts, and prices do not include state or local
taxes. Prices and specifications are subject to change without notice.
DISCOUNT SCHEDULE
Applicable Discount
Aggregate List Price

$
5,000 - 9,999
10,000 19,999
20,000 - 49,999
50,000 99,999
100.000 . 249,999
250.000 . 499.999
500,000 . 999,999
1,000,000 . AND OVER
3%
5%
10%
15%
18%
20%
22%
25%
Discounts apply to any combination of FLIP CHIP Modules.

See separate cabinet discount schedule on paKe 247.
452
453
TYPE
p~C~
PR1CE
S
SllE
LHW
~-- - . - - - -
714,
728
322
325
20e,00
24".00
728A
325
260,00
782
:'15
128,00
182-.
783
783A
~
UI
~
911
913
91"'
91'19
915
917
932
933
934
935
939
191!17
1 94 !)"19
4913
12.e1954
12."9103
1'10081
318
321
321
431
427
42A
428
427
429
423
423
423
424
424
383
383
440
486
406
238
Max, POWER
VOLTS x "'.
-- -- Ne
S1.0+5
.,
10
-15
10
-15
10
148,00
-1'
10
2421.00
-15
1f1
260.00
9 , 0flJ
25. ~H~
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4.~1
33,31
50,01
,61
1,0"
5121,"1
61'1J.e"
1,51
9.~1
20 9 00
25,011
215.QIl0
52,30
1.01/ft
-15
10
-15
TITLE
p - -
71"1
POWI, SUDDI:tJ
POWII' SUDDJy
85"1
1500
8511
401
Pow ...
15011
38""
~UDD I Y
POWII' SUDDly
411H'
3011111
POWII' SUDDI:tJ
15Q'"
POWII' SUDDly
850.
75"1
pOWlr SUDol:tJ
8581
patc~cOl'd' (ll/ok;)
Patc~col'd. (101/DK')
POWII' JU~D.rs (10/D~O)
POWII' JU~DII'S tlL'1/~ka)
Patc~oo'd'
Oa'.~
Cnal,..
(1""/oKa)
91.1 1 5t,.lD
Byl 5tl'ID
,WI,.. W"IDDlno WII" <1""'1 ft, 1" II)
WI" WrlDDTno Wlr. (tlee ft, '0.11)
BUI 5"10
Pa,..I' CO".,
~olo DowP'! 9a,
Mo,-,ntfP'!Q Rackl
MountJ"Q Slfdl.
TIlt Slldl.
Clb,I, "It Coax 9.co"ducter
TYPE
.~~.-.-
PAGE
. -..
11'.011'002
1'000PJ3
721.2159219
14-06782
74."6'793
91-211575
91-217599
91-217722
A123
A160
~
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(J'1
A161
A162
4163
JJ8
338
406
406
406
338
338
338
236
2J8
24~
243
246
PRICE
S
-.-.~-
SUE
No.
~-
0.75/ft
1. IS ",
51i'J.~0
6.0"
8,00
".60/ft
2.1ZI"'/ft
2.""/ft
58.00 SSS
250.~"
315,00
SOD
SOD
210.""
SOO
395,00
SOD
1
4
4
4
A16~
249
350.00
SOD
A165
251
475,210
SOD
A166
A161
253
255
MalC. POWER
Sl.OTS
VOL.TS x ,"A
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.. -.
- -- -.
-.-. _T
-w _ _ _. __ ._ __
365!~0
490,00
SOO
SOD
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15
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18
521
25
25
35
_.~
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cable, 1.25" Myla, FI.xDrT~t 19-cO"d,

Cable, Rou~d Ceax 9~eo"ductor
AC Ol.trfbytfo" Pa~el
KJelcDllte
Klcl<Clat.
Cable, Rfbbo" ~0-cenducto,
cable, TwIsted caTr r.o.~ J6.eo~ducto,
Cable, ~Iat 40.conduetor
Four-C"I"",' Mu'tTDII~.r
H'o~Jmp'danee Multl~I.~e,
HlO~lmpldane. Multl~le~.,
wIth OutDut ~u'f.r
E-cander
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15
30
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15
35
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40
constant Impedance MultTDlext,
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40
40
30
15
Constlnt Impedanee MultT~I'x.'

wJt" OutDu t Am~I'fTe~
CO"ltant l~ped.nee MultTpllXI' Expande'
wltn Cecode,
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w't~
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wIt" Olc~d'r & Bufflf
Ex~and.'
con, tint Impedanee Multlalexe,

wIt" Oecode, & Outeut AmDITffep
TYPE
-..
PRICE
PAGE
A2""
..258
A260
260
-.-.~
-.-.~
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NO.
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-10
-1'
-.-.-.~
2"
6f?J
SI"QI. SamD'. & ~old fer 10-b,t
S~.t.m.
51";1. SamDI. & ~old fer 12-b)t
S~.t.m.
SI";I. Samel. & ~old
wlt~
fO" 12-blt SYlt,ml
12-SI~
BOO Or'
e,".,.~
I"DU t Buff,1"
OAe
3'
10-Blt OIA Conv.,.t.r. Sf";11
B~ff''''d
1"-81' OIA Conv,,.,.r. sf";11 Bu f f'I"'d
85
l"-SIt OIA Conv.,."r, Ooubl, Bij'f'!".d
25
85
A621
272
37'.00
SOD
'.
+15
-1"
6"
25
8'
1"-81; OIA Conv,r,.r, Ooubll BUff'l",d
PRICE SUE
TVPE
~
PACE ___ . __5 ... __L.Io4W

... _.........
...
A660
274
'1~.0e
SOD
Ne~
SI.OTS
_.w_~_.
M.alll.
III
.5
"'15
.661
A662
A663
~
(J1
"
276
510,211
278
515121,00
SOD
SOD
28'"
585,00
SOO
A70~
282
184,0riJ
1.811
284
350.1210
50S
SOC
A860
286
395,""
SOO
A861
289
59'."'0
SPO
A862
291
595.00
sao
293
293
4."1
A99.
.992
4,131
ssc
S50
.
..
..
-1'
.,
4'
2'
.. ,
2'
"15
25
25
+15
2~
-15
25
12'
25
25
25121
+15
.,
.5
+15
-15
.2
.
-15
.5
+15
-15
.5
..
..
.,
"'1'
-15
.,
2
2
POWER
",A _.... -.w

TITI.
__ ....VOI.TS
_. __ ._ ...
....... .. ....... _._ .... _.. _...
+15
-15
"'1'
-15
4~
3~~
20
160
1'0
20
2fc1
~._
12-Slt MultJDI~T"g CIA

sV.lg"'t 9Tnll'Y
CO"~.~t.,.
12-SIt
Multl~I~'"g
OIA
cc~ve~ter,
12-Slt
Multlol~l"g
OIA Ccnve,te"
2"
C;O",D' ""'"'
BCD
12-Slt Mult'DI~I"g OIA Cc"ve,t.l',

Buff'red StraTaht ~l"aP~
Reflrl"O. SUPD'~
la-SIt AIO Convert.r
12-SIt I"dustpTI' A/O eO"v.rt.,
420
5'
H1Dn-SDe.d 12-elt
421
Hl.n-SD.ed 12-Blt eiDOla' AID Convert.,
12
"12
If' .,,'
I , f ,., Boa'"
Am" I
Aoa,d
AI'lD
unT~ela~
AIO ConvlPter
PRICE
No
Hax
POWER
Ie
01
00
SllE
VOL t_...
S ",A _._._aTITL.E
.. _. __ ....PAGE_... _. S__ ... LMW
_. __ SL.ots
. __ ._. __ ...
.. _._. __ .. . _.... _.. _... _._._ . _
TYPE
R8l1
BC0iF'-XX
9C021.-XX
8C132MXX
RC13iP.XX
RCI2I2S.XX
BC132W"XX
RC02X.XX
416
339
339
339
339
339
33'
343
8C0~V.XX
339
BC03A"XX
ACI2I3B.XX
8C03C.XX
ACI2I30.XX
3421
34'"
34121
~C03E.X)(
341
341
34121
342
BC03F' .. XX
RC03J.XX
RC03H-XX
BC04A.XX
eC048.XX
BCet4F'.XX
BCQJ41.-XX
RC04M-XX
BC04N.XX
BC04P.XX
RC04TwXX
eC04U.XX
AC04W.XX
eC04l
BC08A
Be0BB
34~
339
339
339
340
34PJ
340
344
342
342
343
347
342
344
90.~21
33.021
3A.2!21
3".021
3121.1210
313.130
3121,12121
58,12121
3l,P'21
3e,~0
31,12121
36,2'0
36,!2!21
' 29,00
28.210
36,210
54.00
15.00
18,00
1,.i?J0
18.O21
18."'0
18.021
36,00
21.~21
2'-,~0
28,021
S
S
S
~llt'"Q
~'lt'"Q
~lltl"a
S~st.m u"lt f
91-01575 Cabl
91-''''575 Cab I
93,-rIP575 Cab I
91-07575 Cabl
91-217575 Cabl
91-07575 Cabl
93,"07575 Cabl
93,-,,75 75 Cabl
11-0~2101 Cabl
1'-002101 Cabl
11-00001 Cabl
1'-"0001 Cab'
l1-iH/lfU2 Clb I
1'-"0002 Clbl
11-000211 Cabl
1'-00002 Cabl
91-"7515 Cabl
91-07,75 Cabl
91-,,7575 Cabl
17-rlH'I001 Cab I
17-000 01 Cabl
1'-00001 Cabl
1'-00001 C,bl
1'-"0002 Cabl
11-00002 C,bl
91-,,7575 Cabl
91-07122 Cabl
17-"0002 Cabl
1'0~a01 Cabl
~.~.~., l"t.,.faclrHI
(wQl18.W~23)
(W2I21Wt'!21)
tW2l'-1-WL'l22)
(w2l~2-WCJJ22)
(W0':S.WL'l2:5)
(W2I,-e.WA28)
(~99'e-~908)
(W2I!1-W~21)
(W011-W"'11)
(W011-WL'l21)
(WIIJ~1-WL'l212
C\tl2l~1-W022)
(W0~1-W"'31)
(WIIJ~3-WL'l33)
(W0'8-W~2e)
(M9"'1-M901)
(W011-0~EN)
(W018-0 PEN)
(W0~3.0PEN)
(W0il-0J!EN)
(W"~1-0PEN)
(W0!2.0PEN)
(M9~4-0PEN)
(M9"'1-0 PEN,
(M9"'3-0PEN)
(M9~80PEN)
(1)48!56-0PEN)
(M9~J-Mge3)
(M9~4-M9QJ4)
TYPE
...
BC08C
-~
---~.-.-
BC"8D
~C"'bJ
PCl2!bK
RC~bL
P'C08~
~C11A
Cab
Cab
Cab
Cab
Cab
Cab
~
10
C
D
E:
F"
Cab G
Cab
Cab
Cab
Cab
PRICE
344
345
345
346
341
348
399
399
4 121 PI
4""
401
41211
41211
~lstl"Q
~I.t'ng
See
See Llst'ng
~Ist'"g
s Lilt'";
S.e LIst'ng
S,.' Llst'ng
411.~0
4Jl.QJ0
431~P!21
39"'.~1I.I
41",~0
34"'.t'!11.1
523,~0
502,00
4f(J2
41212
416~~0
403
419f~0
~6'5.fl0
1.1001
363
',00
~0"2
15,~0
1-402"
383
392
398
383
~flJ21
383
',~0
101022
101024
101025
H500
10150".
"'510
38~
2'1,021
383
1,00
383
432
2"',00
315,00
1-4014
~1'D19
",521)
432
441
444
~HW
--.~.-
4"2
SIZE
No.
.. S., ... -.. -.-.-- .. -- ..

342
P.GE
20,"'0
10,~0
15e~1I.I
315,I!II
995,20
995,~1
S~OTS
Ma
VO~TS
POWE~
II(
-------~
.... -- ..... .. Cabl' .. ..o-.-.-...

mA
TlT~E
-.~
-.--~-.-
~.-
~-.--.-.-
17-012!102
(M9tJ-T w W~Jl)
l1aI'D12!001 Cabl, (M9P4-Two W(11)
91-01722 Cabl. (",856-1'1'53)
91-01722 Cabl. ("'S56-M'55)
91-07722 Cabl. (tWD HS~6-M954)
91-07722 Cabl' (H856.H856)
91-56-92-6 Cabl. CM919-M929)
Cabl",.t
Clbln,t
Cabl""t
Clbln,t
Cabln.t
Clbln,t
Cabln,t
Clbl",.t
Cabln,t
Cabln,t
Clbl""t
Mountl,.,g a,aek,t, (D~)

Mount'"g B'le~et. (D"
MountIng Panel
0.1~"
2.01'D"
Mo",nt'''g Bar
19" ~OU"t'"g
E:"d Plate
r,a~,
CattIng
E'nd Pllte
End Pllte 8.5 'nch,.
nd Pllte 8,5 'nch" wTtn T,'m'nll Bloek
cO~Dui"
~Ib
(120 Vae)
comDut',
~Ib
~oglc ~.b
~OgrC ~.b
SI"
M Se,'"
(24e Vae)
TYPE
~.-.-.-
H''''l
!o!701-A
SIZE
-.~
318
I.. HW
No,
51.0TS
MaK. POWER
VOI.TS K "'.
-.-.-.-.-.~
... -.- .... -.... -..-...-........-.-.-..-....
+UJ
4~"
-15
3000
4 II! 0
30l1Z
4fHtJ
4l1Z
+10
2rn.OJ"
15
31 9
41l1~."'''
101710
101716
321
223
15
"15
150,210
101726
H8QJ0-r
H8qlZW
324
21l1~,0"
377
8.210
8,O0
101707
136.""
H7~4
,J:.
PRICt
.. -.-318....-116.""
.. .. -.. -..
PAGE
31 9
18~.0"
"'SS,Z-C
377
377
371
378
379
379
380
381
381
424
425
425
426
150, 01 0
H8U'''O
426
150.0Z
",8UJ ... (
426
UJ0,0Z
H8~1-r
H801 .. W
HSQJ2
H8"'3
H80!t
1018"'''
101808
H809
"'812'
H81~-.
HS10 ... 8
2!~"
2.20
4,""
13,~0
4."''
5,3"
10.210
4,010
99."'
'
99."'21
15~.0l0
-15
-15
.5
+5
-15
.5
15~1!I
1500
5000
4000
1500
700Z
TITI.
POWI' SUDD!Y
-.~.-----
POWII' SUDP I y
Pow.,. SUDP I y
POWI' SUDPly
Pow., SUDP!y
Powir SUDPly
POWI' SuoPlt
COI'I"lctO' eloele
COI'I"leto, ~loclc
RI~laelme"t
R'~lacem."t
pJ",.
pI",.
CO"'"ICtOl' BloOIc
COI'I"letor Aleelc
CO""lctor Bleele
COI'I"ICtOI' Alock
CO""lctor Blecle
R'olaC'ment 1'1"'1
"'al'ld WIre Wrap"''''Q Teol (24 Qa.)
Hal'ld Wl~e WraPD''''; Teol (30 ;a.'
Hal'ld WIre Wrap","; Tool (24 & Jill gal)
eattl,y OPlratld WTre W,aplu",
(2~gauQ' ,'eIYI & bit)
Battery Op.~.ted WTre WraDDU"
C31-0Iu;e I'IIVI & bit)
Batt,py Oper.ild Hlr. WraDDU"
.. -
101811
10181.1-.
101812
101812-.
101813
101813-.
101814
104814..
101820
PACE
SllE
LHW
-.--~.--
101825
101826
101850
101851
101852
101853
101854
425
425
425
425
425
425
425
425
421
421
428
428
422
382
422
422
37'
H856
370
9 11-J.A
11-K,S
104913
10491'
104916
104917
101920
389
389
429
390
391!
101921
39.
110,210
15,12l21
~92;S
394
75,211
H925
395
250,2121
104821
~
....
P~I~E
... -.-- ... -..... 24,IZIiI ...
TYPE
Io4
Io4 9
39~
39.
24,"'''
11Z1,t'lil
UJ,P!1lI
JlZlelZllll
No,
SLOTS
-.~---
Max, POWER
VOLTS K
m. -... TITLE........-... .. -.-.-.- ..

........----.-...
'00\
--~.~
~and
SI"v,
98,1ZI"
GplD CIID'
3,".210
3,5.00
'.""'
7."'
12.0121
8,IZI0
151,IZIIlI
161.1110
270.2'0
12'.021
271?J."'0
260,01l1
.. -- .. -
Hand WPIDPTno '001

wand U"WPIDPlnl Toel (~4.gau;.'
Hand U"WPI~D'ng foal (3,,-gau;.'
Blt C2'.gau;e)
Blt (JIll-gau;e)
S"IV' (24-gaUI.)
J".""1lI
21. 1ZI 1lI
21i0"
48,2J1lI
146,"'''
21"',00
-.~.-
Wpl~plnQ
(3ZgaU,I'
CpfD CIID'
(1Il1~"/Dkg,
(1"~"/Dkg)
Hand CPlmDTng Tool

Hand CplmpTno '001
Modul. Handle Ext,"d,p
Co"n,c to I' f .dgl)
Modul. Hold., CpTb typ 25/D~;)
Modul. Holde, fnon pTb typ., 25/Dka,
110 CO""lcto,
C40-Dl" mall' eoape Mount
1/0 Conll.etCl'
C40.Dl" female' Cabll MOU"t
Mou"tl"g Panel
Mountl"; Pan,1
Mountl"; Pa"'1
Mountl"; Ita", I
MOunt'n; Pa"el
MOI'''"t, nQ Pane I
Modu Ie O,awlP
rront Pa"'1
C"II',' 1S11de'
O,.awll'
Modu"
TYPE
.-.. -..
1-1933
'"
I\)
H933-"
1-1933-e
H933 .. C
1-1933 .. 0
101941-1414
1-1941-8A
1-1941 .. 88
H950-AA
1-1950 .. 814
1-195"CA
1-1952-0A
H950-EA
H950 .. FA
1-1951lJ .. G
1-1952' .. HA
1-1950-1018
1-1950-HC
101950 .. 10040
1-1950 .. IoIE
1oI950 .. HF'
1oI950-HG
H95RJ-HH
1-195ra-HJ
1oI9!50-IoIK
101950"1.14
H950-I.G
H950 .. F'A
1oI950-QA
1-1950-5A
PAGE
PRlct
S
397
397
391
405
405
405
4215
405
405
4 III 6
4""
406
406
4216
4136
406
406
406
4iU
406
406
406
4iU
406
406
I.HW
NOt
SI.O S
.. --... -.. --.. --..

15,I2!0
-~----.-.-.-.-
393
393
393
393
393
SUE
3',~0
31,00
54,"''''
42,00
125,~"
10 e li'J0
8~.~"
16:5,00
47,~Ql
41,I2!ID
4'.1'l21
41."'0
201,"'0
6~t0'"
48,~0
48,00
48,1.'Jrl)
48,i1HD
48 4 "'0
48.013
4A,I.'J0
48."'0
48,91Z
48,01
9,011
1,0(Z1
8,0S
11,~1I
4.fZ'0
Max. POWER
VOI.TS lC "'.
--.--~--.-
TITI.E
.. -.. -...-.w---.---..
.
...
S~'~lm UnIt MountT~g Panll
~
-.~.-
H933 wIth 3-H81.'JQI

101933 wIth 3-H8"'QI
101933 wIth 3 .. H81.'J3
101933 wIt'" ~.H8~8
19" MOU"t'~g Panel F"l'a"'l
Covlr (5,5")
COVII' (8.5")
F'l'ame
F'u II 0001'
F'u'l 0001'
Mountl~g Panel 000'
Mou"t'~g Panel 0001'
Mo~"t 11"1g p.anel 0001' Skln
Tabll TOD Asslmbly
SI'Iort 0001' (21" "'0 1,.11"1 t "~g)
SI'IOl't 0001' (22~15" meu~t'''IS)
SI'Iort 000,. (26~25" meu~t'nos)
SMHt 000,. (31~5~ ",ount1ngs)
Short 000,. (~6~7~" meu~tln,s)
Sno,t 000' (042" Iftount''''g!)
S,",o I' tOOtH
SI'Iort 0001'
SI'IOl't 000'
S,",ort 000,.
F',.aml PI"II
F'rl",e F'II"III
CavIl' alzl' 1'1"'1' f'.2~")
Cove" alze, 1'1"1' CUr.~",
F'llter
--.----~
PRICE
SllE
No.
-.. --.---.--406.. -.- ..57,00

-- .. -- .. -- ... -.--- ...
H952AA
TYPE
H952-BA
4216
~952CA
4fU
406
101952 .. (,4
H95Z .. F'A
ffi
PAGE
4"6
23,"'''
40,00
7,00
2,~0
~952GA
4flJ6
44,00
!-I952-AM
1oI954-AC
H954-BA
1-1954 .. CA
1oI954.SA
1oI954-UA
H957 .. AA
1oI957-8A
H957 .. CA
H9570A
413
5liL ~0
16~~2I0
104957 .. (A
4UI
~HW
S~OTS
Max, POWER
VOLTS x mA
-~.--
.. -- .. -.-.. End
-TITLE
.......
-.. -- ..
Pan,I
stabIlizeI' Fe,t
ran ASS,,.,b!,
caster Set
l.ev,le,. SIt
nil',.
(Da)",
stl"lD
Pa", ,
rrame
ru I I 0001"
ra'" AsS,mbly
r 11 te,.
(!'Id
41~
65,~121
410
410
410
413
41 3
85.00
65,2'0
142,1Z1ll
60,01l1
41~
6~,2I0
413
36.01l1
413
36,00
Me~nt'"g Panel
~.2'0
--.--~~.-.-.--.-.-
Cov."
F'l'a",.
F'ul I 0001" Real' Mou",t (RH)

I 0001" Mount (LH)
Mountf"" Panel (Plenum) Door,
",ar rnaunt (Rio!)
F'~I
(PI'!'Ium' Doe",
raar mount (un
1-1957 .. rA
413
63,~0
~957F'B
413
41 3
63,00
End Pa"el, rT;~t "a no

End Pa"'el, left "'a"'o
36,00
F'II 1'1' Stl'TD GI'OUD
413
413
5~_t'!0
ra" ASSembly C50~ CF~)

Bottem Covel' Plate
413
221,"'0
413
... t'!0
398
2521,210
1-1957-GA
~957-HA
H957JA
H957-L.A
104957SA
H919t!'
91~0
1.000
"'am, Pa"el
r II t,1'
Mount,,,,; Panel
(~)
.. --- ..
TYPE
-.~----
..
PAGE
~~.-.-
Sle Control
!<131
1(132
~
PRlct
I,.HW
No,
SL.OTS
Mlle.
;HJ.~e
27.0Z
SST
sse
3
4
.5
.5
22100
121"'0
33~
3~.1.'J0
1<"4~
334
333
436
431
438
439
385
38'
388
388
12.6
45."'0
12.6
1<94~.R
K94~.S
-.~
for K S,rl.' ModUlls
1(141
K171
I< 9 12IR1
I< 9 QlJl
1<902
1<9Q1J3
1<94R1
K941
POWE~
VOL.TS )( iliA
--~
~I~dbook
329
331
SllE
.... -.... -... -.. -- ....... -....... -... --TPL.E

.. .. ...-... -- ..... ...
5
35.~0
Soure. Moduli
Siavi "'Qulltoft
powlr Transfor"'lr
Powlr Tra~sfor"'lr
UHlHlI
6Z2!f6
01IDI,)I SUDDly
18'5.00
Control PI"" Pow,r SUDPI~

Pate" SOlrd Pa"11
I"dle,tor ~wlteh Panel
Pate" Pan" Board
Mountl"g SUDDort
Mountl"Q F'paml
Mo~ntl"g Panll
MCtuntfnQ Pa,,11
2t2'."''
145.2Z
155.'-'0
6.PlRl
6.20
96,00
96.1Z(ll
-~.-.---
...
-...
TYPE
M002
,.,1214"
en
U1
SUE
I.~W
No,
~.--
2A
39,00
SSS
51.0T5
321
31,021
SSS
M051
129
31,021
SSS
MU'"
1J~
50,~111
SSS
M1I2'1
132
134
2<4.e'1/l
61115 021
SSS
SSS
,,5.021
SSs
ESS
SOS
5SS
SSS
SSS
SSS
SSS
SSS
S5S
SSS
S5S
SSS
1
1
M103
M1!?)5
M107
M10e
Ml11
M112
M113
M115
M117
M119
M121
M13J
M141
M159
M16i1
M"'l
M162
M168
M169
136
1J8
14"
142
31
32
33
33
33
33
36
J'
38
421
44
45
~I
65.~0
HI5,Illl/l
45."'111
22,~1/l
35.221
18,0121
18,00
1 9 .021
18,00
23,021
2',12121
29,01/l
3',00
3J,21Z
55,00
63,08
'.88
33, ~I'
SSS
SSS
S5S
S5S
S5!
S5!
Male. POWER
VOI.TS x !I'IA
-.---.-.-~.--.~.-
M050
1-1102
~
-.-.~
PRICE
...21-.-.-.-..... ...
10,Z0 SSS
PAGE
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.5
.5
-15
.5
-15
-5
-15
+5
-15
-5
.5
-15
+5
.5
-5
.5
-5
+5
+5
-5
.5
-5
.5
-5
+5
+5
-5
+,
.,.,
.,
....... TPI.E
....... ... ... ...... ......
Loale
~
16
41
~ZCH
-.~
Sou~ce
Sol.nold C,lv.,.
41
16
47
16
60
121
82
130
.0
lUI
338
245
137
87
50
11
4.
41
1~
50
160
117
1'0
:U
,.
120
102
2'
50 mA l"dteato" o,lver
pOSitIvI to NiiatrYI l.o;Ic

I.IVI' ~o"vertll'
gus Oat, Znte"'ael
Bus Oata Inte,faci
Oevlce Salacto,.
Dlvlce Salacto,"
Add,ess Slr'eter
Dlvlo, Selectol'
rlag MOdule
Irw.,t"
NOR Gatl
NAND Gat,.
NAND Gatel
NAND Gates
NAND Gat,.
ANO/NOR Gatl
Two-l"~ut NAND Gat.1
NAND/OR Catl,
A'lt"m.tlG/~oglc UnIt
ANO/NOR Catl
B'"''"~ to Oot.I/O"'~'l O.ood.~
Pa~lt)l C'reult
12-el' MaQ~Jtu~. Com~a'ato~
Gatl.,; Module
-.~--
...
TYPE
PAGE
PRICE
$
sUE:
l.HW
NOe
SL.OTS
Max. POWER
VOI.TS )( ",A
-..... -.. -- ... -........ -.- .... _- ... -- .... _- ....
M202
1-1203
M20'
M2""~
M21l'6
M2~1
SSS
~3
341~0
!;SS
54
56
33,"'''
30,00
33,"'0
SSS
1
1
58
6'"
62
c;ss
sss
~236
64
66
M237
M261
1-1262
M302
105,t':!"
125,"'''
5"'.00
68
70
72
74
4a."'0
sss
M3~6
76
46."""
27;~0
1-1310
M360
78
58.0~
~,232
29,021
26.2!21
SSs
50S
!)Ss
SSS
M208
M230
~
SSS
'1
52
79
84t~0
5a.~"
65.~0
68,1i"21
8~
55,~0
JA,I2I0
M41214
82
84
M41215
65,:2lrIJ
85
100.1210
M4UJ
86
87
10.I2IZ
4121!00
M4"1
M4121J
M452
SSS
50S
SSS
SSS
SSS
SSs
sss
SSs
SSS
SSS
SSS
SS5
1
1
1
2
1
1
1
1
~
1
1
1
1
1
1
1
1
1
1
.5
.5
+5
.5
.5
.5
+5
+5
5
+5
.5
+5
.5
+5
57
5~
'74
90
81
96
184
86"
200
330
330
17!)
.5
350
166
120
89
50
80
.5
.5
53'
.5
.5
.,
.5
.5
70
50
9:>
77
TIT~E
-- .~-.-.-
....... -.. --.----.-.- ... -.. ------.-
HlOlt J-I< F'I ',,"Iog

e RIS ~"O.F'IO"S
C.nt~al.PU'DOS' Ruffer & Cou~t.r
Ge~.pal.PUPDuse rITo-F'lops
Gentra'.Pu'ooSI rITo.F'loos
General.PUPDoSI rlTo.rlocs
a-Bit Buff.rIS~"t RegTst,r
81nap~ to RCD 4 ~Co to Binary Convert"
16-WOl'd RAM
12-S1t STnary Up/Down Counttr
3.01;,t BCO Uo/Down Countef
4.Statt Motor TrA~sIAt~r
121-State Metor Translator
OUII oela~ Multlvferater
t~tt;r.tl"o 0"8 5"et
O'la~ ~Ir'\'
Vaplablt OeiaY
Va'lablt Cloek
RC Multlvlerater Cloek
C~y.tal Cleck
Cl'~stal Clock
Reed Cloek
var ,ab It CTock
P~lCE
SllE
NO.
LMW
51..0T5
144
55,210
SSS
M5211
M502
89
146
25,O0
SSS
26.210
SSS
1
1
M506
14'
52~00
SSS
149
45 4 0rl:1
TYPE
PAGE
M500
Max. POWER
VOI.TS x
1".
.... -..... --- ..... -_ ...... -_._---_ .. -- .,

..... -...
M507
SSS
SSS
M5U'
M521
151
51.~0
9~
16,00
M602
91
28,~0
SS5
,.,606
92
94
96
152
154
155
43.00
2A4?10
26,00
SSS
SSS'
SSS
~61e
......
M617
"'622
M623
M624
M627
M632
0\
SSS
-15
-15
1
1
1
1
1
45.~0
sss
41'1.00
SSS
97
45.00
29,2'8
152
55.~0
SSS
SSs
SSS
M633
159
5~.00
sss
M65a
161
25.?J8
SSS
M652
M66t
M661
101671
162
26,08
SSS
98
25.01
SSS
99
U'12I
15!Pl8
s~s
52.0"
S5S
.5
5
1
1
1
1
1
1
+5
.. 15
.5
-15
+5
.5
+5
+5
.5
.5
.5
.5
.5
.5
.,
-15
.5
.,
1~
-1'
.5
-15
.5
.5
.~
160
64
31
49
92
e1
11~
42
11~
1'0
56
213
18e
41
97
2121
'11
ell
136
115
~0
Ul0
40
37
.-- ....
TITL.E
~.--.-.-
.. -.--....
-.-~
2"2
'1
111
112
--~.-
..-
SotH"ltt TftTgo ...

NI;atlvl l"Dut Co"ye~ter, High-Soeed
Negattye J"out
Ce"v.~tlr,
Bus
MedTu",!p.ed
Co"verte~.
~.dlum-See.d
tlO Bus Rleeryer

to M Con"., tar
Puis' Arnplfne'
Pul'l G."e,ato ..
Or"" Co II.eto~ Z-l"out NAND Cate
4.rncu t Power NANO Gate
e.slt Posl"ve I"out/OutDut BUI OrTve"
91.1 1 D"lver
Bus 01'1'181'
NAND POWII' Amp/"r.r
~oeltlve l~out NegatTve outout
Bus DrTver
Ne;atlv. By. O,JVI'
I(
Negattve Outcut
Co~v.rter
N.Gatlve OutDut
Co~v.rt.r
~9
122
.. -..
Nlgat1vI l"put/PesTtTvl outout Rlellvl'
PosItIve Leye' Cab 'e O"lve,

Posltfve Leye'Drlver
M to K Co",verter
PRICE
SIlt
LHW
NO;
... -.. ----... ---- .. -... -- ... -...

M7Q16
102
TYPE
P~GE
SLO S
-.~
.,e:.
en
00
150.~0
50S
SO~
2
2
2
2
M?QJ1
M730
M731
164
164
1521,210
160.00
160.12Jf(J
SOS
M'132
M733
168
168
160.00
165 c 00
SDS
SOS
M734
M'135
M736
M?:5?
M'138
M?B3
M?84
172
174
117
181
183
185
186
18'1
188
105, rlllZl
135,0f(J
125.00
120.00
50S
~7e5
M786
M901
M903
~9214
M906
M90.,
~91i!8
~909
M9S,0
~912
M91'
M917
M918
1117
3'' '
105.~0
3C1J,12!0
3121,12121
35.00
22A,~2I
191
192
35'1
15."'0
1121,00
1"J.00
20,00
16.00
UJ,00'
14,1221
20,00
25,00
J'~
3~."'2I
351!1J
356
111
190
360
360
350
UI,0"
10.021
SOS
SOS
SOS
SOS
50S
e:S5
E:SS
(S5
EOS
SSS
SS!
sss
sss
SSS
SSS
SSS
sss
SOS
SSS
SSS
SSS
2
2
2
2
1
1
1
2
1
1
1
1
1
1
1
1
2
1
1
1
MI POWER
VOLoTS )( ",A
-.~-~
.... -- ....-.... TITLE

....... -... ...-...... ....-... -- ...-.~
.5
.5
.5
.5
15
.5
.5
15
.5
.5
.5
.5
.5
.5
.5
.5
.5
5
.5
.,
4~"IJ
31'
400
4"'0
90
4~rIJ
4"'1
125
32~
42!
401
3!!0
250
'1"
2~0
118
6"'0
..."
11
1350
T"'t~P' R,ce'".~
T'I.t~P, T~a"I""tte~
l"t,~face
Bus
BUI
r"t,,.flce
But l"t,,.face
BUI l"t,rfaCI
1/0
1/0
Byl I"Dut MUlilol'K"

Bu' T~an!f'r R.gl,t.r
pplo,.tty Z~te"pu~i Module

12-Blt But RecII"I' I"t,,.face
COU"t,I'
~uft.,
1"'11'.111
UNIBl)S 0,,1"1"1
UNIBUS Reoll"l .. t
UNlBUS TI'I"'OllvI,
O,vIO, l"~.rf.e.
r".op'"t ~able CO""lctOl'
rl.x~""t eabll
Coaxial Ca~l~ ~o"n.ctol'
Cab" T'I'mTnater
Olod' CllrnD
RIbbon Co"",eier
Termlnatol'
T,"m'natol'
COIX cabl' Co"~.etol'
R'bbon Cabl, Ce"~.etor
RlbbO" Cabl, Cen".etol'
r,exop'"t Cabl' eO~".cto'
PRICE
PAGE
-.~
M922
M925
M926
M927
M935
M953
~954
M95~
,f:Ir.
0\
CD
M95'
M1103
M130'
M150~
M15Qll
M15Z2
~1510
~1621
S%~E
I.~W
SL.OTS
1
1
1
1
1
361
367
367
25,I2lla
21,"1a
21,~"
sss
36~
21.:?J2I
(5S
112
113
12,~Ql
sss
(5S
(55
35~
256
311
MIM, POWER
VOI.TS
6,~"
9.e"
2' , I2lIa
6.021
45.021
14!~21
SSS
1~3
J5.~21
196
19B
2211
2214
501.""
100.021
125,00
UJ7
15Q1."'0
EQS
100!t'l0
M1623
M1102
211
20".~21
Ml,103
M1801
M1390
215
218
114
75.~"
35"',"0
275.0Ql
e"
UNIBUS Co"~,ete~ Module

r\exorf"t eabl' Co~necto~
rl'.c~l"t elb\e r,on"ector
rllxor,"t eable co"nector
COlx Cabl' Con",etor
Int'~nal BUI Conneetor
rllt Cabl. Connlcter
r,at Clbl. Con"eete~
r,at cabl' Co"~.ete~
Rtbbon Cable Cen"'letor
2-!"cu~ A~O Gat,s
t"Out ANO Gate!
B'dlr.et'O~11 Bu! !nt,,'acJna Gate.
BUI Incut Inte,face
Bus Outout Inter'ac'
Bus O.~'ee Selectop
OVM Oat. I~Dut I"ter'.e.
l"strum.~t Remote eontpo\ Int.pface
OMNIBUS '"Dut InterfacI'
Trlp\ Worcl R.oI.tlP rf,es
OMNIBUS !"Dut fnt.,fac.
16-aft Relay OutDut I"t.rfaci
1
1
1
1
r.OS
EOS
1
2
2
n~s
.,
EQS
..
..
.5
.5
.5
(QS
-1
.5
.5
.5
(QS
EOS
4
2
.. 15
222
TITL.E
1
1
.5
.5
.5
.5
.5
1210.1210
E55
.5
... -.. -.. -- ...... -.- ...
",A
+10
M182P.J
l(
--~
SSS
SSS
SSS
SSS
SSS
SSS
SSS
SSS
350
351!l
No
.. -- ... --.-.- ..-- ....-.-.- .... -...-...

4'.0"
... -.. ---311......

M920
TYPE
UH~
3""
J"0
7S0
6"'21
"7
160"
22"0
55~
1450
700
;,
80
298
-.~
A.~ne",o~ou. T'a~lellY.r
Int.rpupt Cont'OI. UNIBUS
-~.--.--
...
TYPE
PAGE
PRICE
S
SUE
I.Io4W
NOt
SL,O S
M'._ POWER
VOl. S iliA
TITL.E
- . - - - - - - - - - ~.p ~.- .. w~~----
WJ11
WI18
well
Wlnl
1tJ1/I22
WR!23
Wl204
WIJ27
.f::o
'"
WIIZ8
we3l
W033
w941
W941
;.9.2
W943
W9'1
1J9'"
W9'2
W953
w96'
W'6.
W'66
W967
361
36~
360
368
368
36!
356
361
356
35"
350
297
291
297
29'
297
291
291
297
31.,J
31/J1
3i12
312
9.~'
S5S
55S
A.~8
SSS
6,01
S5S
6.BI
6,01
SSS
6.12'1/1
6.01
1.118
6.fJl
5.88
S5S
555
S55
S5S
S5S
55S
1
1
1
1
1
1
1
1
1
1
[00
EQO
5,~1
QO
1Qt,0.
40.01
140,0.
15,11
65,01
41,8.
140,0'
00
8.'"
1Qt,08
00
SSS
SSS
1
1
75.~1
85.211
165."
S
4
QO.
[QO
rOD
EQS
QS
Ribbon Cabt. Conn.o~or

RIbbOn Cabll Conn,o~or
RIbbOn Cabll Conn,etor
RIbbOn Cabl' Cenn.eto,
RIbbOn Cabtl Conn,etor
RIbbon Cabll Cennloto,
RlbbOn Cab,e Connleto,
RIbbOn Cabl, Conn.eto.
Coax cabll Con~lc'o'
rtl.orlnt Cabl- ~o"n.cto'
r".orlnt Cabl. CO"nlcto'
WI'I WPIDDabl1 Moduli
wl,1 WrlODabl1 Module
WI'I W'loDabl1 Moduli wlt~ Socklt.
wlr. WrloDabl. Moduli wlth Socklt.
WI,. W'IPD.bla Moduli
WI" wrloDabl1 Moduli
wlrl wrloDabl1 Moduli wlt~ Socklts
WI'I wrloDabl1 Moduli wlth SOCNlt.
MSt Mo~ntl~g BOlrd
col,ag' U"'v.r.al Tlrm'nl'.'
OMNIBUS
w,ae MOd~11
OMNIBUS WIr. W,aD Mod~11 wIth Soek,tl
wr,.
....-.-...
TYItE
~
~
PAGE
~.--
PRIct
30~
w"3
w9'.
3m4
304
W9"
304
18,0e
w9'9
3m'
20,00
14,00
w980
W982
w98.
w990
w991
w992
W993
w998
w999
308
~0,00
4.0e
8,00
4.00
6,0e
9,00
18.0B
304
2.00
5.00
2.00
4.00
4.00
9,00
304
3m4
304
304
30.
NO+
Max, POWER
VOLTS III ",4
51.0 5
--.~
4',00
309
31~
L.~w
~-
w968
W9,9
W970
w971
W912
303
303
30.
30.
SllE
....-- .......
......
..
QS
4
S
~A,00
05
55S
5gs
S5!
50S
55S
SQS
SQS
1
2
1
2
sss
rSS
rgs
1
2
2
1
1
2
55S
SOS
SSS
50S
SSS
SOS
2
1
2
1
2
~.--
.........
....... ............ -... -.... -...
T%TI,.E
~-
col 110 1 Mountl~g Boa~d

col 1101 Mountl~g Board
BJan~ MOduli
Blln~ Moduli
Blink Module
811"~ Modul.
Blln~ Module
Blink Modul.
col 110' Mountl~g Board
Modul. E~'.nde,
Moduli Extlndl~
MOdul. Ext.nde,
Blink Moduli
Blank Moduli
BlinN Moduli
Blink Modul.
811nk Moduli
Blank Moduli
-.~-
472
Bus Converter ........................

Bus Data Interface ........ 130,
Bus Device Selector .....
Bus Driver .................... 154,
Bus Driver, Negative ..............
Bus Driver, Positive Input/
Negative Output ..................
Bus Driver, Positive Input!
Output
................
Bus Input Interface ........ 196,
Bus Interface ................ 164,
Bus Interface, Negative Input ..
Bus Interface, Negative
Output ...............................
Bus Interface, Postive Input ....
Bus Interface, Positive Output
Bus Interfacing Gates .... 193,
Bus Interfacing, Interrupt
Control ...............................
Bus Multiplexer ......................
Bus Output Interface 198, 207,
Bus Receiver Interface, PDP-8
Bus Receiver, PDP-15 ...........
Bus Strip ........................ 389,
Bus Transfer, Register, PDP-8
Bus, Negative
......................
Bus, Positive
... ................
A Series Modules ......

225
Accessories, Power
Supplies .................... 315, 317
A/D Converter, 10-Bit ............ 284
A! 0 Converter, 12-Bit High
Speed ....................... 289, 191
AID Converter, 12-Bit
Industrial....................
286
A! 0 Resolution Table .
234
ADC Codes ............................. 235
Address Selector .......
.. ... 138
Adjustable Delays
.. ........... 75
Amplifier Boards
293
Amplifier, Operational .... 258, 260
Amplifier, Pulse ..........
91
Analog Modules ........
225
Analog Multiplexer ........ 236, 238,
240, 243, 246, 249, 251,
253, 255
Analog Switch .... ............... 236
Analog Voltage Reference ....... 282
~nalog-To-Digital Code Table .... 235
AND Gates ...................... 112, 113
AND! NOR Gates .......... 16, 36, 44
Anti-Kickback .......................... 28
Arithmetic Mode Operations 42, 43
Arithmetic Operations .............. 40
Arithmetic! Logic Unit ................ 40
Asychronous Transce:ver ........ 114
Automatic Wiring .............. 374, 418
149
132
201
155
159
157
152
204
168
170
166
169
165
196
222
172
218
181
151
423
174
130
133
Cabinet Color ........................

Cabinet Cover ..........................
Cabinet Dimensions for
H950 Series ........................
H954 Series ........................
H957 Series ........................
Cabinet Discount Schedule ....
Cabinet Special Consideratings
Cabinet Summary for
H950 Series ................. 405,
Cabinet Summary for
H954 Series ........................
Cabinet Summary for
H957 Series ........................
Cabinets .' 399, 400, 401, 402,
Cable Connector, 40 Pin ........
Cable Connector, Coax
Cable Connector, Flat .... 366,
Cable Connector, Flexprint ....
B
Bar for Mounting ..........
398
Bar, Hold Down ...................... 383
Battery Powered Wire Wrap
Gun ..................................... 426
BBll Power Pin Assignments .. 417
Bezel Cover Panel .................... 410
Bidirectional Bus Gates ...
193
Blank Modules ........................ 304
Blank Modules, Copper Clad .... 306
Blocks, Connector ........ 377, 378,
379, 380, 381
Blocks, Connector Summary
376
BMB ........ 134, 140, 167, 171, 181
Buffer-Counter ......................... 53
Buffer/ Shift Register
60
Bus Connector
................ 311
473
405
410
408
412
415
405
404
406
410
413
403
370
355
370
349
Cable
Cable
Cable
Cable
Cable,
Cable,
Connector, I/O ............ 370

Connector, Ribbon ...... 359
Ordering Information .... 338
Terminator .................... 111
9 Conductor
338, 340
19 Conductor ...... 338, 341,
342, 344
Cable, 20 Conductor.
.. ..... 338,
339, 343
Cable, 36 Conductor ....... .
338
Cable, 40 Conductor
338, 345
Cable, 60 Conductor
" ... 348
Cable, Coax ............ 338, 340, 344
Cable, Flat ......................
345
Cable, Mylar Flexprint
348
Cable, Ribbon .............
343
Cable, UNIBUS ...... .........
348
Cables and Accessor:es
337
Cables, Standard .......... 339, 342
Casting, Systems Unit........... 393
Clock, 1 kHz to 50 kHz ..
82
Clock, 175 kHz to 10 MHz .
80
Clock, 5 kHz to 2 MHz. ........
84
Clock, Adjustable ........ 80, 82, 87
Clock, Crystal . .. .... .... .. .. ..... 84, 85
Clock, RC ........................... 80, 82
Clock, Reed ............................. 86
Coax ........................ 338, 340, 344
Coax Cable Connector ............ 355
Coax, Twisted Pair .................. 338
Collage Mounting
Boards ................... .... 303, 307
Color Code for Patchcords ..... 427
Communications Interface
114
Communications Transceiver.. 114
Comparator, Magnitude
48
Computer Lab
432
Connector Assembly..........
379
Connector Block Pins .... 379, 381
Connector Block Replacement
Contacts ..........
377
Connector Block Summary .... 376
Connector Blocks .......... 377, 378,
379, 380, 381
Connector Cards, Double Sided 342
Connector Cards, Single Sided 339
Connector, Diode Clamp ........ 190
Connector, Edge .........
382
Constant Z Multiplexer
Expander ...................
249
With Amp ............................ 251
With Dec, & Amp ..........
255
With Decoder ..............
253
Contacts for Connector Blocks 377

Control Interface for Remote
Instruments ...................... 207
Control Panel, K Logic Lab..
436
Converter, BCD To BINARy ...... 62
Converter, BINARY To BCD ..... 62
Converter, High-Speed
146
Converter, K To M .....
90
Converter, M To K ................. 100
Converter, Medium-Speed
147
Converter, Negative-Input 146, 147
Converter, NegativeOutput
161, 162
Converter, Positive to Negative
Logic .................
129
Cooling ..
375
Counter, BCD .......
... 68
Counter, BINARY
66
Counter, General Purpose
53
Counter, Ring
70
Counter, Synchronous
66, 68
Cou nter, UP/DOWN
66, 68
Cover Panel Hardware ...
383
Crimping Tool ....................... 428
Crystal Clock
84, 85
Current Compensation ............ 232
Current Loop ........................ 114
Current Offset
.............. 228
o
DAC ............ .. 268, 270, 272, 274,
276, 278, 280
DAC Codes .. .......................... 235
DAC, 10-Bit BINARy ...... 270, 272
DAC, 12-Bit BCD .................... 276
DAC, 12-Bit BINARy ...... 268, 274
DAC, 12-Bit Binary with
Input Buffer ...................... 280
DAC, 12-Bit 2's Complement.. 278
DAC, 3-Dig;t BCD .................... 268
DAC, Bipolar ................. 270, 272
DAC, Double Buffered .... 270, 272
DAC, Multiplying ............ 274, 276,
278, 280
DAC, Unipolar .......... 268,270,272
Daisy Chain ............................ 429
Data Acquisition System Codes 235
Data' Communications Interface 114
Data Multiplexer ...................... 133
Data Transceiver .................... 114
DECIMAL Decoder ..................... 45
Decoder, BINARY To OCTAL/
DECIMAL .............................. 45
Delay .................................... 23, 74
Delay Line ............................... 78
Delay Range ............................ 74
474
Delays, Adjustable .. ,................... 75

Device Interface .............. 138, 188
Device Selector .............. 134, 136,
140, 201
Differential Gain ..................... 233
Digital Codes for DAC and
ADC Systems ...................... 235
Digital Indicator
30
Digital-To-Analog Code Table
235
Digita I-To-Ana log Converter,
10-Bit ....................... 270, 272
Digital-To-Analog Converter,
12-Bit .. 268, 274, 276, 278, 280
Display Supply
333
Double Coax Cables
344
Double Flexprint Cable
348
Double Ribbon Cable .
343
Double-Height .
6, 8
Double-Width ..
6, 8
Drawer ..............
394, 395
Driver, High Current
28
Driver, Inductive Load
28
Driver, Positive Level ....
98, 99
Driver, Solenoid ..........
28
Dual 15V Power Supplies..
319
Dual Op-Amp ......
260
DVM Data Input Interface
204
Flip-Flops,
Frequency
Frequency
Functional
RS ............................ 52
For Full Output ...... 228
For Unity Gain ........ 228
Decoding .................. 45
G
Gain Compensation ................. 232
Gating Modles ..........
50
Gating Modules List .................. 3
H
Hand Crimping Tool ................ 428
Hardware
.............. 373, 385
Hardware, Panel Cover.... ....... 383
Hareware for PDP-8! e
Interfacing...
398
Height ..... ..................... .... 5, 6, 9
HIGH, Logic Source .........
. 27
High Z Multiplexer Expander .. 238
High Z Multiplexer With Bllf,
& Decoder ............
246
High Z Multiplexer With
Buffer ........................
240
High Z Multiplexer With
Decoder
243
Hold Down Bar.
383
Hold, Sample And ........... 264, 266
E
Edge Connector
................ 382
EIA 1/0 .................................. 114
End Panel ................................ 410
EVEN Parity .............................. 47
Extended Decoding.
140
Extended Module. ..............
7
F
Fan Assembly.
. ............... 410
Filter for Cabinet Fans ........... 410
Flag Module ....
.............. 142
Flat Cable
........... 338, 345
Flat Cable Connector ... 366, 370
Flat Coax Cable ........... 340, 344
Flexprint Cable, Connector .... 349
Flexprint Cable,
Mylar
338, 341, 342, 348
FLIP CHIP ................ ..........
5
Flip-Flop Modules list ........
3
Flip-Flop Propagation Delays .... 24
Flip-Flop, 0 Type .... 18, 54, 56, 142
Flip-Flop, JK
........... 18, 58
Flip-Flop, Master Slave JK
19
Flip-Flop, Triple JK ... ............. 51
Flip-Flops, General
Purpose ...............
54, 56, 58
Impedance, Op-Amp ................ 228

Incandescent Bulbs .................. 30
Indicator Driver ........................ 30
Indicator Switch Panel ............ 438
Inductive Load Driver ................ 28
Input Interfacing to
OMNIBUS ................. 211, 215
UNIBUS ..
.. ........ 222
UNIBUS/OMNIBUS ...... 196, 204
Input Loading .....
14
Input NAND Gates
......... 37
Instrument Remote Control
Interface
207
Interface, Counter-Buffer ........ 183
Integrating One-Shet ................ 76
Interface Modules, K Series
442
Interfacing Hardware for
PDP-8e
.............. ..
398
Interfacing to PDP-8/ e .. ..
201
Interfacing to UNIBUS!
196
OMNIBUS, Input ..
Interfacing to UNIBUS/
OMNIBUS, Output ............ 198
475
Interrupt Control ................... ,

Interrupt Module ....................
Inverter, Logic ................ 31,
Inverting Amplifier ........ 230,
I/O Cable Connector ..............
lOP Signals ..... ................ 134,
222
177
132
231
370
136
Multiplexer, Logic .... 50, 133, 172

Multiplying DAC ............ 274, 276,
278, 280
Multivibrator, Dual Delay .......... 74
Multivibrator, Integrating .......... 76
Multivibrator, RC Clock ...... 80, 82
Mylar Flexprint
Cable ............ 338, 341, 342, 348
J
Jumper Modules for UNIBUS
and OMNIBUS .................... 313
Jumpers, Power ............ 428, 440
N
NAND
NAND
NAND
NAND
NAN D
NAND
K
K Series Logic Lab .................. 435
K to M Series Converter ............ 90
Kickplate .................................. 410
Gate Schematic ...... 12,

Gate, 2-lnput ..................
Gate, 4-lnput .......... 96,
Gate, Open-Collector ....
Gate, Power .. ... ..... 96,
Gates ........ 11, 15, 33,
13
94
97
94
97
34,
35, 94, 96, 97, 133, 136

NAND Power Amplifier '............ 97
NAND/NOR Gates ...................... 38
Negative Bus ................. 130, 134
Lab Series ..................... " ...... , 431

Level Converter, Positive To
Negative Logic .................. 129
Logic Amplifiers List .................. 4
Logic Functions ........................ 40
Logic HIGH Source .................... 27
Logic Lab, K Series .. .. .. ....... 435
Logic Lab, M Series .. .... .... .... 443
logic Levels ...................... 14, 15
Logic Mode Operation .............. 41
Logo Frame Panel ............... 410
Negative LogiC Power Supplies

Summary ............................ 315
Nixie Display Power Supply .... 333
Noise Margin ............................ 14
Non-Inverting Amplifier .......... 230
NOR Configuration .................... 16
NOR Gates .......................... 15, 32
Notes On Op-Amps .................. 227
Numeric Modules List ................ 4
M Series General
Characteristics ... .... .... .. .. ... .. .. 11
M Series Logic Lab ................ 443
M Series Timing ...................... 14
M to K Series Converter ........ 100
Magnitude Comparator .............. 48
Module Accessories ............... , 422
Module Cooling ...................... 375
Module Dimensions .............. 5, 7
Module Drawer ... .. .. . ...... 394, 395
Module Extender .... 308, 309, 310
Module Handle Extender ...
422
Motor Translator ................ 70, 72
Motor, Stepping ................ 70, 72
Mounting Bar ....................... ,.. 398
Mounting Board - ...................... 300
Mounting Hardware ................ 385
Mounting Panel .... 388, 389, 390,
000 Parity ................................ 47

Offset ...................................... 232
OMNIBUS Input
Interface ........... , ........ 211, 215
OMNIBUS Interfacing .............. 193
OMNIBUS Interfacing, Device
Selector . . . .. . . .. . ... . . .. . . .. .. .. . . ... 201
OMNIBUS Jumper Module ...... 311
One-Shot Delay .......................... 25
One-Shot, Integrating ................ 76
Operational Amplifier 230, 258, 260
Operational Amplifier Notes .... 227
Output Drive .............................. 14
Output Interfacing to
UNIBUS ................................ 222
Output Interfacing to UNIBUSI
OMNIBUS ............ 198, 207, 218
Output Loading ........................ 14
Overload Recovery .................. 228
392, 393, 398

397
383
391
437
440
236
Mounting Panel Frame ..........

Mounting Panel Hardware
Mounting Panel Table ............
Mounting Panel, Patchcord ....
Mounting Rack, K Logic Lab ..
Multiplexer, Analog ..................
Panel ........ 388, 389, 390, 392, 398

Panel Cover ............................ 383
Panel Frame for Mounting ...... 397
476
Panel, Indicator & Switches .... 438

Panel, Patch Board . .... ... .... . .... 439
Parallel to Serial Converter
114
Parity Circuit ............................ 47
Patch Board Panel ........ 437, 439
Patchcord Color Code .............. 427
Patchcord, K logic lab .......... 437
Patch cords ............................ " 427
PDP-8 ...................... 130, 134, 159
PDP-8/1 ........ 130, 133, 134, 159,
164, 168, 172, 174, 178,
181, 183
PDP-8f l .................. 133, l36; 164,
168, 172, 174, 178,
181, 183
Pins for Connector Blocks 379, 381
Pistol Grip Hand Wire
Wrapping Tool.......
424
Positive Bus................... 132, 136
Power Amplifier Delays ........... 23
Power Amplifiers ...................... 23
Power Jumpers
.... 428, 440
Power Regulator, +5V
331
Power Source Module .............. 329
Power Supplies ...................... 313
Power Supplies,
+10V ....... '" 315, 318, 325, 327
Power Supplies, +5V .... 314, 321,
322, 323, 324, 329, 331
Power Supplies,
-15V .......... 318, 323, 325, 327
Power Supplies, -5V .............. 315
Power Supplies, 15V .............. 316
Power Supplies, Dual 15V
319
Power Supplies, Nixie Display 333
Power Supplies, Special
Summary ............................ 317
Power Supply, K Logic Lab.... 436
Power Transformers .......
334
Priority Interrupt Module
177
Programmed Wiring ................ 375
Propagation Delays . ...............
23
Pulse Amplifier ...............
91
Pulse Generator .. . . . .
92
Pulse Train ............... .. 80, 82, 84
Q
Quad-Height ............................... 9
R
RAM ......................................... 64
RC Clock ............................ SO, 82
Receiver, Negative Input
Positive Output ................... 144
Receiver, TELETYPE ..........
102
Reed Clock ................................ 86

Reference Supply .................... 282
Register Files, Triple 4-Word .... 211
Regulator, Power Slave for +5V 331
Relay Driver .............................. 28
Relay Output Interface ............ 218
Remote Indicator ...................... 30
Ribbon Cable ........... 338, 339, 343
Ribbon Cable Connector ........ 359
Ring Counter ..................... 70, 72
RS Flip-Flop .............................. 17
S
Sample And Hold ....
264, 266
Schmitt Trigger........
.......... 88
Serial to Parallel Converter .... 114
Settling Time .................. 228, 231
Single-Height ........................ 5, 7
Single-Width ............................ 5, 7
Siava Regulator ....................... 331
Solenoid Driver .......................... 28
Stabilizer Feet .......................... 410
Standard Cables ........... 339, 342
Standard Module ........................ 5
Standard Timing Pulse .............. 22
Stepping Motor Control .... 70, 72
Stepping Motor Drive ... " ....... " 28
Switch Panel ............................ 438
Synchronous Counter ........ 66, 68
System Interfacing Un:t, BBll 416
System Operating Frequency .... 25
Systems Unit Casting .............. 393
T
Table of Mounting Panels ........ 391
TELETYPE Receiver ................ 102
TELETYPE Transmitter ............ 107
Terminator ...................... 191, 192
Terminator Board .................... 301
Time'Related Modules List .......... 3
Timing Considerations .............. 22
Timing Signal Source 80, 82, 84, 85
Training Aids ..... '" .......... 431, 432
Transceiver, Asynchronous ...... 114
Transformers, Power .............. 334
Transmitter, TELETYPE ............ 107
Triple 4-Word Register Files .... 211
Triple JK Flip-Flop .................... 51
TTY Current loop .. .. . . . .. . ....... . 114
TTY Interface .......................... 114
Twisted Pair Coax Cable .......... 338
U
UNIBUS Cable ........................ 348
UNIBUS Drivers ...................... 185
477
UNIBUS Interfacing ................ 193

UNIBUS Interfacing,
Interrupt Control .
222
UNIBUS Jumper Module..
311
UNIBUS Receivers . ...........
186
UNIBUS Transceiver .............. 187
UNIBUS/OMNIBUS Interfacing,
Instrument Control ............ 207
UNIBUS/OMNIBUS Output
Interfacing, I6-Bit Relay.
218
Un~ Load ............................... 14
Universal Terminator Board
301
Unused Inputs
................ 22
Variable Delay .......................... 79

Voltage Follower ...................... 231
Voltage Offset .. .. .. ... .. .. .
228
W
W:dth .....................................
Wire Wrap Module ..............
Wire Wrappable Modules .......
Wire Wrapping Pricing ............
Wire Wrapping Service ........
Wire Wrapping Tool 424, 425,
Wire Wrapping Wire ...... 423,
Wiring Accessories
423,
Wiring Hints ...........................
Wiring, Automatic ....
v
Variable Clock
... 80, 82, 87
478
5, 6
302
297
421
418
426
424
427
374
374
NOTES
479
NOTES
480
NOTES
481
NOTES
482
NOTES
483
NOTES
484

Digital Logic Handbook 1972

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Digital Logic Handbook 1972

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o

digital equipment corporation

FLIP CHIP, UNIBUS and OMNIBUS are

Organization of Handbook .......................................................... ...... vii

List of Modules ...............................................................................

M SER'IES MODULES FOR COMPUTER INTERFACING ............................ 119

A SERIES ANALOG MODULES .................................................................. 225

ACCESSORY MODULES ............................................................................ 295

POWER SUPPLIES ........................................ ............................................. 313

CABLES AND ACCESSORIES .................................................................... 337

LAB SERIES .............................................................................................. 431

Cabling: This edition of the handbook presents a greatly expanded section

DIGITAL EQUIPMENT CORPORATION ENGINEERING SERVICES

SPECIAL SYMBOlS AND ABBREVIATIONS

Input loading and Output Drive

logic Diagram Input loading and Output Drive Symbols

Bus DrIvers and Receivers

TYPICAL BUS TRANSCEIVER ARRANGEMENT

Sus Driver and Receiver Symbols

Typical Level Converter

Special Analog Symbols

MULTIPLEX SWITCH (MOS FET)

CONSTANT IMPEDANCE MULTIPLEX SWITCH

Special Analog Symbols

Signal and Function Names

Signal and Function Names

Digital Equipment Corporation uses standard terminology to name signal

Bits Per Second

Digital to Analog Converter

High (TTL +3 V Logic Level)

Low (TTL 0 V Logic Level)

Sample and Hold

DEC Module ass~mbly lines combine automated manufacturing

MSERIES LOGIC AND CONTROL MODULES

Dual Delay Multivibrator

Arithmeticl Logic Unit

Logic HIGH Source

STANDARD MODULE DIMENSIONS

SINGLE-WIDTH FLIP CHIP MODULE

CONDUCTIVE COMPONENT LIMIT

~PO!i~T~ !/i ~x.

ETCHED WIRING SURFACE

SINGLE-HEIGHT FLIP CHIP MODULE

~~-=-==-==--~-- -: = ;:=:-r-'~"= ;r;:-,~o~

*=MAXIMUM USEABLE COMPONENT AREA

DOUBLE WIDTH FLIP CHIP MODULI

''t6 MAXIMUM HEIGHT OF

... MAXIMUM USEABLE

EXTENDED MODULE DIMENSIONS

CONDUCTIVE COMPONENT LIMIT 1~32

NON CONDUCTIVE COMPONENTS

ETCHED WIRING SURFACE

SINGLE-HEIGHT FLIP CHIP MODULE

DOUBLE WIDTH FLIP CHIP MOOI..l.E

CONDUCTIVE COMPONENT LIMITS "".

DOUBLE HEIGHT FLIP CHIP MODULE