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Verilog Tutorial 1

This document provides an overview of variables, data types, logic values and operators in Verilog. It defines nets and registers, their uses, and generic term. It lists the four basic Verilog signal values and their meanings. It describes data types for nets and registers, including declaration syntax and semantics. It covers register assignment, strings, constants, parameters, arithmetic, bitwise, logical, relational, shift and conditional operators. It explains how operator widths are determined based on operand widths and how expressions with operands containing 'x' or 'z' are evaluated.

Uploaded by

Sivanantham Sadhasivam
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
74 views

Verilog Tutorial 1

This document provides an overview of variables, data types, logic values and operators in Verilog. It defines nets and registers, their uses, and generic term. It lists the four basic Verilog signal values and their meanings. It describes data types for nets and registers, including declaration syntax and semantics. It covers register assignment, strings, constants, parameters, arithmetic, bitwise, logical, relational, shift and conditional operators. It explains how operator widths are determined based on operand widths and how expressions with operands containing 'x' or 'z' are evaluated.

Uploaded by

Sivanantham Sadhasivam
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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FPGA Based System Design

Tutorial 1 - Logic Values, Data Types & Operators

Variables
In Verilog, what are nets used for?
Ans: _______________________________
What are registers used for in Verilog?
Ans: _______________________________
What is the generic name for both nets and registers?
Ans: _______________________________
What is a single bit net called?
Ans: _______________________________
What is a multiple bit register called?
Ans: _______________________________

Logic Values
Give the four basic Verilog signal values and their meanings
Ans: _______________________________

Data Type - Nets


Give the two methods for explicitly assigning a value to a net.
Ans: _______________________________
Give the two methods for implicitly assigning a value to a net.

Net Declaration Syntax


Explain the difference between a net declared as vectored and a net declared as
scalared.
Ans: _______________________________
What is the default for a net, vectored or scalared?
Ans: _______________________________

Initial Value & Undeclared Nets


What is the default initial value of a net at tsim = 0?
Ans: _______________________________
What is the default type for a net that is not declared?
Ans: _______________________________
How can the default type for a net that is not declared be changed?
Ans: _______________________________

Data Type Register


Register Semantics
Give the function that each of the following register types performs.
reg
: Ans: _______________________________
integer : Ans: _______________________________
time : Ans: _______________________________
real : Ans: _______________________________
realtime: Ans: _______________________________

Register Assignment
List four Verilog constructs within which a register can be assigned.
Ans: _______________________________
List two Verilog constructs by which a register can never be assigned.
Ans: _______________________________

Strings
What is the data type for a string?
Ans: _______________________________
A string must be stored in reg (or array). Describe a register with identifier buffer
for storing in a string of 32 8-bit characters.

Ans: _______________________________
2

Constants
Declaration of parameters
A sequential circuit has three states A, B, and C with state codes 00, 01, and
10, respectively. Write a parameter statement assigning these codes to their
respective states.
Ans: _______________________________

The following gives a parameter regsize and its instantiation. If n = 8, how


many bits are in reg R and how are they numbered?
parameter regsize = n;
reg R[0: n - 1];

Ans: _______________________________
Operators
Give the function that each of the operators listed performs:
Arithmetic (binary)
+
A:
A:
*
A:
/
A:
%
A:
Arithmetic (unary)
+
A:
A:
Bitwise
~
A:
&
A:
|
A:
^
A:
~^ or ^~

A:

Reduction
&
A:
~&
A:
|
A:
~|
A:
^
A:
~^ or ^~ A:
Logical
!
&&
||

A:
A:
A:
3

==
!=
===
!==
Relational
<
>=
>
<=

A:
A:
A:
A:

A:
A:
A:
A:

Shift
>>
<<

A:
A:

Conditional
?:
A:
Concatenation and Replications
{,}
A:
{int{ }}A:

Expression Bit Widths


Depends on:
widths of operands and
types of operators
Verilog fills in smaller-width operands by using zero extension.
Final or intermediate result width may increase expression width
Width (Unsized constant number) = same as integer (usually 32)
Width (Sized constant number) = number of bits specified.
Arithmetic binary and bitwise
x op y where op is +, -, *, /, %, &, |, ^, ^~:
Bit width = max (width(x), width(y))
What is the width of A + B for reg[7:0] A; reg[15:0] B;?
Ans: _______________________________
Will the assignment statement assign result = (A+B) >> 1; work properly for all
possible pairs of 16-bit operands for reg[15:0] A, B;?
Ans: _______________________________

Arithmetic unary
op x where op is +, Bit width = width(x)
Bitwise negation
op x where op is ~
Bit width = width(x)
Logical, relational and reduction
x op y where op is = =, !=, = = =, != =, &&, ||, >, >=, <, <= or op y where op is !, &, |,
^, ~&, ~|, ~^
Bit width = 1
What is the bit width of (X && (A + B)) for wire X; wire[7:0] A, B;?
Ans: _______________________________
Shift
x op y where op is <<, >>
Bit width = width(x)
Conditional
x?y:z
Bit width = max(width(y), width(z))
What is the bit width of assign result = X ? A:B; for wire X; reg[9:0] A; reg[18:10]
B;
Ans: _______________________________
Concatenation
{x, , y}
Bit width = width(x) + + width(y)
What is the bit width of {A, B, C} for wire A; reg[7:0] B; reg [15:0] C;?
Ans: _______________________________
Replication
{x{y, , z}}
Bit width = x * (width(y) + + width(z))

Expressions with Operands Containing x or z


Arithmetic
If any bit is x or z, result is all xs.
Divide by 0 produces all xs.
What is the result of assign result = A + B; for A = 4'b1100; B = 2'b11?
Ans: _______________________________
What is the result of assign result = A + B; for A = 4'b1100; B = 4'bx11?
Ans: _______________________________
Relational
If any bit is x or z, result is x.
Logical
= = and != If any bit is x or z, result is x.
= = = and != = All bits including x and z values must match for equality;
otherwise unequal. Lengths of operands must be equal.
Operands are reduced to bit 0 or 1, respectively, based on zero or nonzero
value
What is the value of (4'b0011) = = (2'b11)?
Ans: _______________________________
Can (4'b0011) = = = (2'b11)? be evaluated? Explain your answer.
Ans: _______________________________
&&, || combines logical values 0,1, x according to:
Bitwise
Defined by tables for 0, 1, x, z operands.
Reduction
Defined by tables as for bitwise operators.
Shifts
z changed to x.
Vacated positions zero filled.
Conditional
If conditional expression is ambiguous (e.g., x or z), both expressions are
evaluated and bitwise combined as follows: f(1,1) = 1, f(0,0) = 0, otherwise x.
What is the value of result in assign result = (2'b1x)? 4'b0011: 4'b0101;
Ans: _______________________________

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