0% found this document useful (2 votes)

1K views

Ece-Vii-dsp Algorithms & Architecture (10ec751) - Notes

This document outlines a university syllabus for the course DSP Algorithms and Architecture. The syllabus covers 8 units over 2 parts. Part A includes units on introduction to digital signal processing, architectures for programmable digital signal processors, and programmable digital signal processors. Part B covers implementation of basic DSP algorithms, implementation of FFT algorithms, interfacing memory and parallel I/O peripherals to DSP devices, and interfacing and applications of DSP processors. The syllabus provides an overview of topics to be covered in each unit, including digital filters, DFT, FFT, architectures, instructions, programming, algorithms, and applications. References and textbooks are also listed.

Uploaded by

rass

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (2 votes)

1K views

Ece-Vii-dsp Algorithms & Architecture (10ec751) - Notes

Uploaded by

rass

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 186

DSP Algorithm and Architecture

10EC751

University Syllabus
DSP Algorithms and Architecture
Subject Code

: 10EC751

IA Marks

: 25

No. of Lecture Hrs/Week : 04

Exam Hours

: 03

Total no. of Lecture Hrs. : 52

Exam Marks

: 100

PART - A
UNIT - 1
INTRODUCTION TO DIGITAL SIGNAL PROCESSING: Introduction, A Digital SignalProcessing System, The Sampling Process, Discrete Time Sequences, Discrete Fourier Transform
(DFT) and Fast Fourier Transform (FFT), Linear Time-Invariant Systems, Digital Filters, Decimation
and Interpolation.
5 Hours
UNIT - 2
ARCHITECTURES FOR PROGRAMMABLE DIGITAL SIGNAL-PROCESSORS:
Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and
Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program
Execution, Features for External Interfacing.
8 Hours
UNIT - 3
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Introduction, Commercial digital
Signal-processing Devices, Data Addressing Modes of TMS32OC54xx., Memory Space of
TMS32OC54xx Processors, Program Control.
6 Hours
UNIT - 4
Detail Study of TMS320C54X & 54xx Instructions and Programming, On-Chip peripherals, Interrupts
of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor.
6 Hours

PART - B
UNIT - 5
IMPLEMENTATION OF BASIC DSP ALGORITHMS: Introduction, The Q-notation, FIR Filters,
IIR Filters, Interpolation and Decimation Filters (one example in each case).
6 Hours

Dept.ECE, SJBIT

Page 1

DSP Algorithm and Architecture

10EC751

UNIT - 6
IMPLEMENTATION OF FFT ALGORITHMS: Introduction, An FFT Algorithm for DFT
Computation, Overflow and Scaling, Bit-Reversed Index Generation & Implementation on the
TMS32OC54xx.
6 Hours
UNIT - 7
INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP DEVICES:
Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface,
Parallel I/O Interface, Programmed I/O, Interrupts and I / O Direct Memory Access (DMA).
8 Hours
UNIT - 8
INTERFACING AND APPLICATIONS OF DSP PROCESSOR: Introduction, Synchronous
Serial Interface, A CODEC Interface Circuit. DSP Based Bio-telemetry Receiver, A Speech
Processing System, An Image Processing System.
6 Hours
TEXT BOOK:
1. Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.
REFERENCE BOOKS:
1. Digital Signal Processing: A practical approach, Ifeachor E. C., Jervis B. W PearsonEducation, PHI/ 2002
2. Digital Signal Processors, B Venkataramani and M Bhaskar TMH, 2002
3. Architectures for Digital Signal Processing, Peter Pirsch John Weily, 2007

Dept.ECE, SJBIT

Page 2

DSP Algorithm and Architecture

10EC751

INDEX SHEET
Sl.
No.

1
2
3
4
5

6
7
8
9
10
11
12
13

14
15
16
17
18
19
20
21
22
23
24
25

26
27
Dept.ECE, SJBIT

Unit & Topic of Discussion

PART-A:
UNIT-1: INTRODUCTION TO DIGITAL SIGNAL
PROCESSING:
Introduction, A Digital Signal-Processing System,
The Sampling Process, Discrete Time Sequences
Discrete Fourier Transform (DFT) and Fast Fourier
Transform (FFT),
Linear Time-Invariant Systems, Digital Filters,
Decimation and Interpolation
UNIT-2 : ARCHITECTURES FOR
PROGRAMMABLE DIGITAL SIGNALPROCESSORS:
Introduction, Basic Architectural Features
DSP Computational Building Blocks
Explanations of functional blocks
Bus Architecture
Memory, Data Addressing Capabilities
Address Generation Unit,
Programmability and Program Execution
Features for External Interfacing
UNIT-3 : PROGRAMMABLE DIGITAL SIGNAL
PROCESSORS
Introduction, Commercial Digital Signal-processing
Devices,
Data Addressing Modes of TMS32OC54xx-1
Data Addressing Modes of TMS32OC54xx-2
Special addressing modes
Memory Space of TMS32OC54xx Processors
Program Control, Programming
UNIT-4 : INSTRUCTIONS AND PROGRAMMING
Detail Study of TMS320C54X
Instructions
Programming
On-Chip peripherals,
Interrupts of TMS32OC54XX Processors
Pipeline Operation of TMS32OC54xx Processor
PART-B
UNIT-5 : IMPLEMENTATION OF BASIC DSP
ALGORITHMS
Introduction, The Q-notation
PROBLEMS on Q- notation

Page No.

5-15

16-35

36-59

60-119

120-134

Page 3

DSP Algorithm and Architecture

28
29
30
31

32
33
34
35
36
37

38
39
40
41
42
43
44
45

46
47
48
49
50
51
52

Dept.ECE, SJBIT

FIR Filters
IIR Filters,
Interpolation Filters
Decimation Filters
UNIT-6 : IMPLEMENTATION OF FFT
ALGORITHMS
Introduction, An FFT Algorithm for DFT Computation
Overflow and Scaling
Bit-Reversed Index Generation
Routine for bit reversed index
Implementation on the TMS32OC54xx.-1
Implementation on the TMS32OC54xx.-2
UNIT-7 : INTERFACING MEMORY AND
PARALLEL I/O PERIPHERALS TO DSP DEVICES
Introduction, Memory Space Organization,
External Bus Interfacing Signals
Timing Diagram of interfacing
Memory Interface
Problems on memory interface
Parallel I/O Interface
Programmed I/O
Interrupts and I / O Direct Memory Access (DMA).
UNIT-8 : INTERFACING AND APPLICATIONS
OF DSP PROCESSOR
Introduction, Synchronous Serial Interface
Block diagram of CODEC
A CODEC Interface Circuit
ADC interface
DSP Based Bio-telemetry Receiver
A Speech Processing System
An Image Processing System

10EC751

135-154

155-170

171-186

Page 4

DSP Algorithm and Architecture

10EC751

UNIT-1
Introduction to Digital Signal Processing

Syllabus:INTRODUCTION TO DIGITAL SIGNAL PROCESSING: Introduction, A Digital SignalProcessing System, The Sampling Process, Discrete Time Sequences, Discrete Fourier Transform
(DFT) and Fast Fourier Transform (FFT), Linear Time-Invariant Systems, Digital Filters, Decimation
and Interpolation.
5 Hours
TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

Digital Signal Processing: A practical approach, Ifeachor E. C., Jervis B. W PearsonEducation, PHI/ 2002
Digital Signal Processors, B Venkataramani and M Bhaskar TMH, 2002
Architectures for Digital Signal Processing, Peter Pirsch John Weily, 2007

1.1 What is DSP?

DSP is a technique of performing the mathematical operations on the signals in digital domain.
As real time signals are analog in nature we need first convert the analog signal to digital, then we
have to process the signal in digital domain and again converting back to analog domain. Thus ADC is
required at the input side whereas a DAC is required at the output end. A typical DSP system is as
shown in figure 1.1.

Dept.ECE, SJBIT

Page 5

DSP Algorithm and Architecture

10EC751

1.2 Need for DSP

Analog signal Processing has the following drawbacks:
They are sensitive to environmental changes
Aging
Uncertain performance in production units
Variation in performance of units
Cost of the system will be high
Scalability
If Digital Signal Processing would have been used we can overcome the above shortcomings of ASP.
1.3 A Digital Signal Processing System
A computer or a processor is used for digital signal processing. Anti aliasing filter is a LPF
which passes signal with frequency less than or equal to half the sampling frequency in order to avoid
Aliasing effect. Similarly at the other end, reconstruction filter is used to reconstruct the samples from
the staircase output of the DAC (Figure 1.2).

Dept.ECE, SJBIT

Page 6

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 7

DSP Algorithm and Architecture

10EC751

1.4 The Sampling Process

ADC process involves sampling the signal and then quantizing the same to a digital value. In
order to avoid Aliasing effect, the signal has to be sampled at a rate at least equal to the Nyquist rate.
The condition for Nyquist Criterion is as given below, fs= 1/T 2 fm
Where, fs is the sampling frequency, fm is the maximum frequency component in the message
signal. If the sampling of the signal is carried out with a rate less than the Nyquist rate, the higher
frequency components of the signal cannot be reconstructed properly. The plots of the reconstructed
outputs for various conditions are as shown in figure 1.4.

Dept.ECE, SJBIT

Page 8

DSP Algorithm and Architecture

10EC751

1.5 Discrete Time Sequences

Consider an analog signal x(t) given by, x(t)= A cos (2ft). If this signal is sampled at a
Sampling Interval T, in the above equation replacing t by nT we get, x (nT) = A cos (2fnT)
where n= 0,1, 2,..etc
For simplicity denote x (nT) as x (n)
x (n) = A cos (2fnT) where n= 0,1, 2,..etc
We have fs=1/T also = 2fnT
x (n) = A cos (2fnT)= A cos (2fn/fs) = A cos n
The quantity is called as digital frequency.
= 2fT = 2f/fs radians

Fig 1.5 A Cosine Waveform

Fig 1.7 Structure of a Digital Filter

Values of the filter coefficients vary with respect to the type of the filter. Design of a digital filter
involves determining the filter coefficients. Based on the length of the impulse response, digital filters
are classified into two categories via Finite Impulse Response (FIR) Filters and Infinite Impulse
Response (IIR) Filters.

Dept.ECE, SJBIT

Page 12

DSP Algorithm and Architecture

10EC751

1.8.1 FIR Filters

FIR filters have impulse responses of finite lengths. In FIR filters the present output depends
only on the past and present values of the input sequence but not on the previous output sequences.
Thus they are non recursive hence they are inherently stable.FIR filters possess linear phase response.
Hence they are very much applicable for the applications requiring linear phase response.
The difference equation of an FIR filter is represented as

The frequency response of an FIR filter is given as

The major drawback of FIR filters is, they require more number of filter coefficients to realize a
desired response as compared to IIR filters. Thus the computational time required will also be more.
1.8.2 IIR Filters
Unlike FIR filters, IIR filters have infinite number of impulse response samples. They are
recursive filters as the output depends not only on the past and present inputs but also on the past
outputs. They generally do not have linear phase characteristics. Typical system function of such
filters is given by,

Stability of IIR filters depends on the number and the values of the filter coefficients. The major
advantage of IIR filters over FIR is that, they require lesser coefficients compared to FIR filters for the
same desired response, thus requiring less computation time.
1.8.3 FIR Filter Design
Frequency response of an FIR filter is given by the following expression,

Design procedure of an FIR filter involves the determination of the filter coefficients bk.

1.8.4 IIR Filter Design

IIR filters can be designed using two methods viz using windows and direct method. In this
approach, a digital filter can be designed based on its equivalent analog filter. An analog filter is
designed first for the equivalent analog specifications for the given digital specifications. Then using
appropriate frequency transformations, a digital filter can be obtained. The filter specifications consist
of passband and stopband ripples in dB and Passband and Stopband frequencies in rad/sec.
Dept.ECE, SJBIT

Page 13

DSP Algorithm and Architecture

10EC751

Fig 1.11 Lowpass Filter Specifications

Direct IIR filter design methods are based on least squares fit to a desired frequency response. These
methods allow arbitrary frequency response specifications.
1.9 Decimation and Interpolation
Decimation and Interpolation are two techniques used to alter the sampling rate of a sequence.
Decimation involves decreasing the sampling rate without violating the sampling theorem whereas
interpolation increases the sampling rate of a sequence appropriately by considering its neighboring
samples.
1.9.1 Decimation
Decimation is a process of dropping the samples without violating sampling theorem. The
factor by which the signal is decimated is called as decimation factor and it is denoted by M. It is
given by,

Fig 1.12 Decimation Process

Dept.ECE, SJBIT

Page 14

DSP Algorithm and Architecture

10EC751

1.9.2 Interpolation
Interpolation is a process of increasing the sampling rate by inserting new samples in between.
The input output relation for the interpolation, where the sampling rate is increased by a factor L, is
given as,

Fig 1.13 Interpolation Process

Problems:
1. Obtain the transfer function of the IIR filter whose difference equation is given by y (n)=
0.9y (n-1)+0.1x (n)
y (n)= 0.9y (n-1)+0.1x (n)
Taking Z transformation both sides
Y (Z) = 0.9 Z-1 Y (Z) + 0.1 X (Z)
Y (Z) [1- 0.9 Z-1] = 0.1 X (Z)
The transfer function of the system is given by the expression,
H (Z)= Y(Z)/X(Z)
= 0.1/ [ 1- 0.9 Z-1]
Realization of the IIR filter with the above difference equation is as shown in figure.

Dept.ECE, SJBIT

Page 15

DSP Algorithm and Architecture

10EC751

2. Let x(n)= [0 3 6 9 12] be interpolated with L=3. If the filter coefficients of the
filters are bk=[1/3 2/3 1 2/3 1/3], obtain the interpolated sequence
After inserting zeros,
w (m) = [0 0 0 3 0 0 6 0 0 9 0 0 12]
bk=[1/3 2/3 1 2/3 1/3]
We have,
y(m)= bk w(m-k) = b-2 w(m+2)+ b-1 w(m+1)+ b0 w(m)+ b1 w(m-1)+ b2 w(m-2)
Substituting the values of m, we get
y(0)= b-2 w(2)+ b-1 w(1)+ b0 w(0)+ b1 w(-1)+ b2 w(-2)= 0
y(1)= b-2 w(3)+ b-1 w(2)+ b0 w(1)+ b1 w(0)+ b2 w(-1)=1
y(2)= b-2 w(4)+ b-1 w(3)+ b0 w(2)+ b1 w(1)+ b2 w(0)=2
Similarly we get the remaining samples as,
y (n) = [ 0 1 2 3 4 5 6 7 8 9 10 11 12]

Recommended Questions
1. Explain with the help of mathematical equations how signed numbers can be
multiplied. The sequence x(n) = [3,2,-2,0,7].It is interpolated using interpolation
sequence bk=[0.5,1,0.5] and the

interpolation factor of 2. Find the interpolated

sequence y(m).
2. An analog signal is sampled at the rate of 8KHz. If 512 samples of this signal are used
to compute DFT X(k) determine the analog and digital frequency spacing between
adjacent X(k0 elements. Also, determine analog and digital frequencies corresponding
to k=60.
3. With a neat diagram explain the scheme of the DSP system.
4. What is DSP? What are the important issues to be considered in designing and
implementing a DSP system? Explain in detail.
5. Why signal sampling is required? Explain the sampling process.
6. Define decimation and interpolation process. Explain them using block diagrams and
equations. With a neat diagram explain the scheme of a DSP system.
7. With an example explain the need for the low pass filter in decimation process.
8. For the FIR filter y(n)=(x(n)+x(n-1)+x(n-2))/3. Determine i) System Function ii)
Magnitude and phase function iii) Step response iv) Group Delay.
9. List the major architectural features used in DSP system to achieve high speed program
execution.
Dept.ECE, SJBIT

Page 16

DSP Algorithm and Architecture

10EC751

10. Explain how to simulate the impulse responses of FIR and IIR filters.
11. Explain the two method of sampling rate conversions used in DSP system, with suitable
block diagrams and examples. Draw the corresponding spectrum.
12. Assuming X(K) as a complex sequence determine the number of complex real
multiplies for computing IDFT using direct and Radix-2 FT algorithms.
13. With a neat diagram explain the scheme of a DSP system. (June.12, 8m)
14. With an example explain the need for the low pass filter in decimation process.
(June.12, 4m)
15. For the FIR filter y(n)=(x(n)+x(n-1)+x(n-2))/3. Determine i) System Function ii)
Magnitude and phase function iii) Step response iv) Group Delay. (June.12, 8m)
16. List the major architectural features used in DSP system to achieve high speed program
execution. (Dec.11, 6m).
17. Explain how to simulate the impulse responses of FIR and IIR filters. (Dec.11, 6m).
18. Explain the two method of sampling rate conversions used in DSP system, with suitable
block diagrams and examples. Draw the corresponding spectrum. (Dec.11, 8m).
19. Explain with the help of mathematical equations how signed numbers can be
multiplied. (July.11, 8m).
20. With a neat diagram explain the scheme of the DSP system. (Dec.10-Jan.11, 8m)
(July.11, 8m).

Dept.ECE, SJBIT

Page 17

DSP Algorithm and Architecture

10EC751

UNIT-2
Architectures for Programmable Digital Signal Processing
Devices

Syllabus:ARCHITECTURES FOR PROGRAMMABLE DIGITAL SIGNAL-PROCESSORS:

Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and
Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program
Execution, Features for External Interfacing.
6 Hours
TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

10EC751

2.2.4 Speed
Conventional Shift and Add technique of multiplication requires n cycles to perform the
multiplication of two n bit numbers. Whereas in parallel multipliers the time required will be the
longest path delay in the combinational circuit used. As DSP applications generally require very high
speed, it is desirable to have multipliers operating at the highest possible speed by having parallel
implementation.
2.2.5 Bus Widths
Consider the multiplication of two n bit numbers X and Y. The product Z can be at most 2n
bits long. In order to perform the whole operation in a single execution cycle, we require two buses of
width n bits each to fetch the operands X and Y and a bus of width 2n bits to store the result Z to the
memory. Although this performs the operation faster, it is not an efficient way of implementation as it
is expensive. Many alternatives for the above method have been proposed. One such method is to use
the program bus itself to fetch one of the operands after fetching the instruction, thus requiring only
one bus to fetch the operands. And the result Z can be stored back to the memory using the same
operand bus. But the problem with this is the result Z is 2n bits long whereas the operand bus is just n
bits long. We have two alternatives to solve this problem, a. Use the n bits operand bus and save Z at
two successive memory locations. Although it stores the exact value of Z in the memory, it takes two
cycles to store the result.
b. Discard the lower n bits of the result Z and store only the higher order n bits into the memory. It is
not applicable for the applications where accurate result is required. Another alternative can be used
for the applications where speed is not a major concern. In which latches are used for inputs and
outputs thus requiring a single bus to fetch the operands and to store the result (Fig 2.2).

Fig 2.2: A Multiplier with Input and Output Latches

2.2.6 Shifters
Shifters are used to either scale down or scale up operands or the results. The following
scenarios give the necessity of a shifter

Dept.ECE, SJBIT

Page 21

DSP Algorithm and Architecture

10EC751

a. While performing the addition of N numbers each of n bits long, the sum can grow up to n+log2 N
bits long. If the accumulator is of n bits long, then an overflow error will occur. This can be overcome
by using a shifter to scale down the operand by an amount of log2N.
b. Similarly while calculating the product of two n bit numbers, the product can grow up to 2n bits
long. Generally the lower n bits get neglected and the sign bit is shifted to save the sign of the product.
c. Finally in case of addition of two floating-point numbers, one of the operands has to be shifted
appropriately to make the exponents of two numbers equal.
From the above cases it is clear that, a shifter is required in the architecture of a DSP.
2.2.7 Barrel Shifters
In conventional microprocessors, normal shift registers are used for shift operation. As it
requires one clock cycle for each shift, it is not desirable for DSP applications, which generally
involves more shifts. In other words, for DSP applications as speed is the crucial issue, several shifts
are to be accomplished in a single execution cycle. This can be accomplished using a barrel shifter,
which connects the input lines representing a word to a group of output lines with the required shifts
determined by its control inputs. For an input of length n, log2 n control lines are required. And an
dditional control line is required to indicate the direction of the shift.
The block diagram of a typical barrel shifter is as shown in figure 2.3.

Fig 2.3 A Barrel Shifter

Dept.ECE, SJBIT

Page 22

Dept.ECE, SJBIT

Page 26

DSP Algorithm and Architecture

10EC751

10EC751

a. SAR < EAR & updated PNTR > EAR

Page 37

DSP Algorithm and Architecture

10EC751

Recommended Questions:
1. Explain implementation of 8- tap FIR filter, (i) pipelined using MAC units and (ii)

parallel

using two MAC units. Draw block diagrams.

2. What is the role of a shifter in DSP? Explain the implementation of 4-bit shift right barrel
shifter, with a diagram.
3. Identify the addressing modes of the operands in each of the following instructions & their
operations
i)ADD B

ii) ADD #1234h

iii) ADD 5678h

iv) ADD +*addreg

4. Draw the schematic diagram of the saturation logic and explain the same.
5. Explain how the circular addressing mode and bit reversal addressing mode are implemented in
a DSP.
6. Explain the purpose of program sequencer.
7. Give the structure of a 4X4 Braun multiplier, Explain its concept. What modification is
required to carry out multiplication of signed numbers? Comment on the speed of the
multiplier.
8. Explain guard bits in a MAC unit of DSP. Consider a MAC unit whose inputs are 24-bit
numbers. How many guard bits should be provided if 512 products have to be added in the
accumulator to prevent overflow condition? What is the overall size of the accumulator
required?
9. With a neat block diagram explain ALU of DSP system.
10. Explain circular buffer addressing mode ii) Parallelism iii) Guard bits.
11. The 256 unsigned numbers, 16 bit each are to be summed up in a processor. How many guard
bits are needed to prevent overflow.
12. How will you implement an 8X8 multiplier using 4X4 multipliers as the building blocks.
13. Describe the basic features that should be provided in the DSP architecture to be used to
implement the Nth order FIR filter, where x(n) denotes the input sample, y(n) the output
sample and h(i) denotes ith filter coefficient.(Dec.09-Jan.10, 8m)
14. Explain the issues to be considered in designing and implementing a DSP system, with the help
of a neat block diagram. (May/June10 , 6m)
15. Briefly explain the major features of programmable DSPs. (May/June10, 8m)

Dept.ECE, SJBIT

Page 38

DSP Algorithm and Architecture

10EC751

16. Explain the operation used in DSP to increase the sampling rate. The sequence x(n)=[0,2,4,6,8]
is interpolated using interpolation sequence bk =[1/2,1,1/2] and the interpolation factor is 2.find
the interpolated sequence y(m). (May/June10, 8m)
17. Explain with the help of mathematical equations how signed numbers can be multiplied.
(Dec.10-Jan.11, 8m)
18. The sequence x(n) = [3,2,-2,0,7].It is interpolated using interpolation sequence bk=[0.5,1,0.5]
and the interpolation factor of 2. Find the interpolated sequence y(m).(Dec.10-Jan.11, 6m)
19. Why signal sampling is required? Explain the sampling process. (Dec.12, 5m)
20. Define decimation and interpolation process. Explain them using block diagrams and
equations. (Dec.12, 6m).

Dept.ECE, SJBIT

Page 39

DSP Algorithm and Architecture

10EC751

UNIT-3
Programmable Digital Signal Processors

Syllabus:PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Introduction, Commercial digital

Signal-processing Devices, Data Addressing Modes of TMS32OC54xx., Memory Space of
TMS32OC54xx Processors, Program Control.
6 Hours

TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

3.1 Introduction:
Leading manufacturers of integrated circuits such as Texas Instruments (TI), Analog devices &
Motorola manufacture the digital signal processor (DSP) chips. These manufacturers have developed a
range of DSP chips with varied complexity.
The TMS320 family consists of two types of single chips DSPs: 16-bit fixed point &32-bit floatingpoint. These DSPs possess the operational flexibility of high-speed controllers and the numerical
capability of array processors
3.2 Commercial Digital Signal-Processing Devices:
There are several families of commercial DSP devices. Right from the early eighties, when
these devices began to appear in the market, they have been used in numerous applications, such as
communication, control, computers, Instrumentation, and consumer electronics. The architectural
features and the processing power of these devices have been constantly upgraded based on the
advances in technology and the application needs. However, their basic versions, most of them have
Harvard architecture, a single-cycle hardware multiplier, an address generation unit with dedicated
address registers, special addressing modes, on-chip peripherals interfaces. Of the various families of
programmable DSP devices that are commercially available, the three most popular ones are those
Dept.ECE, SJBIT

Page 40

DSP Algorithm and Architecture

3.4 Data Addressing Modes of TMS320C54X Processors:

Data addressing modes provide various ways to access operands to execute instructions and place
results in the memory or the registers. The 54XX devices offer seven basic addressing modes
1. Immediate addressing.
2. Absolute addressing.
3. Accumulator addressing.
4. Direct addressing.
5. Indirect addressing.
6. Memory mapped addressing
7. Stack addressing.
3.4.1 Immediate addressing:
The instruction contains the specific value of the operand. The operand can be short (3,5,8 or 9
bit in length) or long (16 bits in length). The instruction syntax for short operands occupies one
memory location,
Example: LD #20, DP.
RPT #0FFFFh.
3.4.2 Absolute Addressing:
The instruction contains a specified address in the operand.
1. Dmad addressing. MVDK Smem,dmad, MVDM dmad,MMR
2. Pmad addressing. MVDP Smem,pmad, MVPD pmem,Smad
3. PA addressing. PORTR PA, Smem,
4.*(lk) addressing .
3.4.3 Accumulator Addressing:
Accumulator content is used as address to transfer data between Program and Data memory.
Ex: READA *AR2
3.4.4 Direct Addressing:
Base address + 7 bits of value contained in instruction = 16 bit address. A page of 128
locations can be accessed without change in DP or SP.Compiler mode bit (CPL) in ST1 register is
used.
If CPL =0 selects DP
CPL = 1 selects SP,
It should be remembered that when SP is used instead of DP, the effective address is
computed by adding the 7-bit offset to SP.

Dept.ECE, SJBIT

Page 52

DSP Algorithm and Architecture

10EC751

Figure 3.7 Block diagram of the direct addressing mode for TMS320C54xx Processors.
3.4.5 Indirect Addressing:
Data space is accessed by address present in an auxiliary register.
TMS320C54xx have 8, 16 bit auxiliary register (AR0 AR 7). Two auxiliary register arithmetic units
(ARAU0 & ARAU1)
Used to access memory location in fixed step size. AR0 register is used for indexed and bit reverse
addressing modes.
For single operand addressing
MOD _ type of indirect addressing
ARF _ AR used for addressing
ARP depends on (CMPT) bit in ST1
CMPT = 0, Standard mode, ARP set to zero
CMPT = 1, Compatibility mode, Particularly AR selected by ARP

Dept.ECE, SJBIT

Page 53

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 54

DSP Algorithm and Architecture

10EC751

Table 3.2 Indirect addressing options with a single data memory operand.
Circular Addressing;
Used in convolution, correlation and FIR filters.
A circular buffer is a sliding window contains most recent data. Circular buffer of size R must
start on a N-bit boundary, where 2N > R .
The circular buffer size register (BK): specifies the size of circular buffer.
Effective base address (EFB): By zeroing the N LSBs of a user selected AR (ARx).
End of buffer address (EOB) : By repalcing the N LSBs of ARx with the N LSBs of BK.
If 0 _ index + step < BK ; index = index +step;
else if index + step _ BK ; index = index + step - BK;
else if index + step < 0; index + step + BK
Dept.ECE, SJBIT

Page 55

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 56

DSP Algorithm and Architecture

10EC751

Bit-Reversed Addressing:
o Used for FFT algorithms.
o AR0 specifies one half of the size of the FFT.
o The value of AR0 = 2N-1: N = integer FFT size = 2N
o AR0 + AR (selected register) = bit reverse addressing.
o The carry bit propagating from left to right.
Dual-Operand Addressing:
Dual data-memory operand addressing is used for instruction that simultaneously
perform two reads (32-bit read) or a single read (16-bit read) and a parallel store (16-bit
store) indicated by two vertical bars, II. These instructions access operands using indirect addressing
mode.
If in an instruction with a parallel store the source operand the destination operand point to the
same location, the source is read before writing to the destination. Only 2 bits are available in the
instruction code for selecting each auxiliary register in this mode. Thus, just four of the auxiliary
registers, AR2-AR5, can be used, The ARAUs together with these registers, provide capability to
access two operands in a single cycle. Figure 3.11 shows how an address is generated using dual datamemory operand addressing.

Dept.ECE, SJBIT

Page 57

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Dept.ECE, SJBIT

Page 61

DSP Algorithm and Architecture

10EC751

3.6. Program Control

It contains program counter (PC), the program counter related H/W, hard stack, repeat
counters &status registers.
PC addresses memory in several ways namely:
Branch: The PC is loaded with the immediate value following the branch instruction
Subroutine call: The PC is loaded with the immediate value following the call instruction
Interrupt: The PC is loaded with the address of the appropriate interrupt vector.
Instructions such as BACC, CALA, etc ;The PC is loaded with the contents of the accumulator
low word
End of a block repeat loop: The PC is loaded with the contents of the block repeat program
address start register.
Return: The PC is loaded from the top of the stack.
Problems:
1. Assuming the current content of AR3 to be 200h, what will be its contents after
each of the following TMS320C54xx addressing modes is used? Assume that the
contents of AR0 are 20h.
a. *AR3+0
b. *AR3-0
c. *AR3+
d. *AR3
e. *AR3
f. *+AR3 (40h)
g. *+AR3 (-40h)
Solution:
a. AR3 AR3 + AR0;
AR3 = 200h + 20h = 220h
b. AR3 AR3 - AR0;
AR3 = 200h - 20h = 1E0h
c. AR3 AR3 + 1;
AR3 = 200h + 1 = 201h
d. AR3 AR3 - 1;
AR3 = 200h - 1 = 1FFh
e. AR3 is not modified.
AR3 = 200h
f. AR3 AR3 + 40h;
AR3 = 200 + 40h = 240h
g. AR3 AR3 - 40h;
AR3 = 200 - 40h = 1C0h

Dept.ECE, SJBIT

Page 62

DSP Algorithm and Architecture

10EC751

2. Assuming the current contents of AR3 to be 200h, what will be its contents after
each of the following TMS320C54xx addressing modes is used? Assume that the contents of AR0 are
20h
a. *AR3 + 0B
b. *AR3 0B
Solution:
a. AR3 AR3 + AR0 with reverse carry propagation;
AR3 = 200h + 20h (with reverse carry propagation) = 220h.
b. AR3 AR3 - AR0 with reverse carry propagation;
AR3 = 200h - 20h (with reverse carry propagation) = 23Fh.

Recommended Questions:
1. Compare architectural features of TMS320C25 and DSP6000 fixed point digital
processors.

signal

(Dec.09-Jan.10, 6m)

2. Write an explanatory note on direct addressing mode of TMS320C54XX processors. Give

example.

(Dec.09-Jan.10, 6m)

3. Describe the operation of the following instructions of TMS320C54XX processors.

i) MPY *AR2-,*AR4+0B

(ii) MAC *ar5+,#1234h,A

(iii) STH A,1,*AR2 iv) SSBX

SXM

(Dec.09-Jan.10, 8m)

4. With a block diagram explain the indirect addressing mode of TMS320C54XX processor using
dual data memory operand. (June.12, 6m)
5. What is the function of an address generation unit explain with the help of block diagram.
(Dec.12, 6m)
6. Why circular buffers are required in DSP processor? How they are implemented? (Dec.12, 2m)
7. Explain the direct addressing mode of the TMS320C54XX processor with the help of a block
diagram. (Dec.12, 2m)
8. Describe the multiplier/adder unit of TMS320c54xx processor with a neat block diagram.
(May/June2010, 6m)
9. Describe any four data addressing modes of TMS320c54xx processor(May/June2010, 8m)

10. Assume that the current content of AR3 is 400h, what will be its contents after each of the
following. Assume that the content of AR0 is 40h. (May/June2010, 8m)

Dept.ECE, SJBIT

Page 63

DSP Algorithm and Architecture

10EC751

11. Explain PMST register. (May/June2011, 8m)

12. With

example

each,

explain

immediate,

absolute,

and

direct

addressing

mode.(May/June2011, 12m)
13. Explain the functioning of barrel shifter in TMS320C54XX processor. (June.12, 6m)
14. Explain sequential and other types of program control(June.11, 7m)
15. With an example each, explain immediate, absolute, and direct addressing mode.
16. Explain the functioning of barrel shifter in TMS320C54XX processor.
17. Explain sequential and other types of program control
18. Assume that the current content of AR3 is 400h, what will be its contents after each of the
following. Assume that the content of AR0 is 40h.
19. Explain PMST register.
20. Compare architectural features of TMS320C25 and DSP6000 fixed point digital

signal

processors.

Dept.ECE, SJBIT

Page 64

DSP Algorithm and Architecture

10EC751

UNIT-4
Instruction and programming
Syllabus:Detail Study of TMS320C54X & 54xx Instructions and Programming, On-Chip peripherals, Interrupts
of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor.
6 Hours
TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

4.1 Assembly language instructions can be classified as:

Arithmetic operations
Load and store instructions.
Logical operations
Program-control operations

Dept.ECE, SJBIT

Page 65

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 66

DSP Algorithm and Architecture

10EC751

10EC751

MVPD: Move Data From Program Memory to Data Memory

PORTR: Read Data from Port

PORTW: Write Data to Port

Dept.ECE, SJBIT

Page 96

DSP Algorithm and Architecture

10EC751

READA: Read Program Memory addressed by Accumulator A and Store in Data

Memory

WRITA: Write Data to Program Memory Addressed by Accumulator A

Branch Instructions
B[D]: Branch Unconditionally

BACC[D]: Branch to Location Specified by Accumulator

Dept.ECE, SJBIT

Page 97

DSP Algorithm and Architecture

10EC751

BANZ[D]: Branch on Auxiliary Register Not Zero

BC [D]: Branch Conditionally

FB [D]: Far Branch Unconditionally

FBACC [D]: Far Branch to Location Specified by Accumulator

Dept.ECE, SJBIT

Page 98

DSP Algorithm and Architecture

10EC751

CALA [D]: Call Subroutine at Location Specified by Accumulator

CALL[D]: Call Unconditionally

CC [D]: Call Conditionally

Dept.ECE, SJBIT

Page 99

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 100

DSP Algorithm and Architecture

10EC751

FCALA [D]: Far Call Subroutine at Location Specified by Accumulator

Dept.ECE, SJBIT

Page 101

DSP Algorithm and Architecture

10EC751

4.1.5. Interrupt Instructions:

INTR: Software Interrupt

TRAP: Software Interrupt

Dept.ECE, SJBIT

Page 102

DSP Algorithm and Architecture

10EC751

4.1.6. Return Instructions

FRET [D]: Far Return

FRETE [D]: Enable Interrupts and Far Return From Interrupt

RC [D]: Return Conditionally

Dept.ECE, SJBIT

Page 103

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 104

DSP Algorithm and Architecture

10EC751

RET [D]: Return

RETF [D]: Enable Interrupts and Fast Return From Interrupt

4.1.7. Repeat Instructions

RPT: Repeat Next Instruction

RPTB [D]: Block Repeat

Dept.ECE, SJBIT

Page 105

DSP Algorithm and Architecture

10EC751

RPTZ: Repeat Next Instruction and Clear Accumulator

4.1.8. Stack-Manipulating Instructions

FRAME: Stack Pointer Immediate Offset

POPD: Pop Top of Stack to Data Memory

Dept.ECE, SJBIT

Page 106

DSP Algorithm and Architecture

10EC751

POPM: Pop Top of Stack to Memory-Mapped Register

PSHD: Push Data-Memory Value onto Stack

PSHM: Push Memory-Mapped Register onto Stack

4.1.9. Miscellaneous Program-Control Instructions

SSBX: Set Status Register Bit

RSBX: Reset Status Register Bit

Dept.ECE, SJBIT

Page 107

DSP Algorithm and Architecture

10EC751

NOP: No Operation

RESET: Software Reset

4.3. On chip peripherals:

Dept.ECE, SJBIT

Page 108

DSP Algorithm and Architecture

10EC751

It facilitates interfacing with external devices. The peripherals are:

General purpose I/O pins
A software programmable wait state generator.
Hardware timer
Host port interface (HPI)
Clock generator
Serial port
4.3.1 It has two general purpose I/O pins:
BIO-input pin used to monitor the status of external devices.
XF- output pin, software controlled used to signal external devices
4.3.2. Software programmable wait state generator:
Extends external bus cycles up to seven machine cycles.
4.3.3. Hardware Timer
An on chip down counter
Used to generate signal to initiate any interrupt or any other process
Consists of 3 memory mapped registers:
The timer register (TIM)
Timer period register (PRD)
Timer controls register (TCR)
Pre scaler block (PSC).
TDDR (Time Divide Down ratio)
TIN &TOUT
The timer register (TIM) is a 16-bit memory-mapped register that decrements at every pulse from the
prescaler block (PSC).
The timer period register (PRD) is a 16-bit memory-mapped register whose contents are loaded onto
the TIM whenever the TIM decrements to zero or the device is reset (SRESET).
The timer can also be independently reset using the TRB signal. The timer control register
(TCR) is a 16-bit memory-mapped register that contains status and control bits. Table shows the
functions of the various bits in the TCR.
The prescaler block is also an on-chip counter. Whenever the prescaler bits count down to 0, a
clock pulse is given to the TIM register that decrements the TIM register by 1. The TDDR bits contain
the divide-down ratio, which is loaded onto the prescaler block after each time the prescaler bits count
down to 0.
That is to say that the 4-bit value of TDDR determines the divide-by ratio of the timer clock
with respect to the system clock. In other words, the TIM decrements either at the rate of the system
clock or at a rate slower than that as decided by the value of the TDDR bits. TOUT and TINT are the
output signal generated as the TIM register decrements to 0. TOUT can trigger the start of the
conversion signal in an ADC interfaced to the DSP.

Dept.ECE, SJBIT

Page 109

DSP Algorithm and Architecture

10EC751

The sampling frequency of the ADC determines how frequently it receives the TOUT signal.
TINT is used to generate interrupts, which are required to service a peripheral such as a DRAM
controller periodically. The timer can also be stopped, restarted, reset, or disabled by specific status
bits.

Dept.ECE, SJBIT

Page 110

DSP Algorithm and Architecture

10EC751

4.3.4. Host port interface (HPI):

Allows to interface to an 8bit or 16bit host devices or a host processor

Signals in HPI are:
Host interrupt (HINT)
HRDY
HCNTL0 &HCNTL1
HBIL
HR/w

Dept.ECE, SJBIT

Page 111

DSP Algorithm and Architecture

10EC751

Important signals in the HPI are as follows:

The 16-bit data bus and the 18-bit address bus.
The host interrupt, Hint, for the DSP to signal the host when it attention is required.
HRDY, a DSP output indicating that the DSP is ready for transfer.
HCNTL0 and HCNTL1, control signal that indicate the type of transfer to carry out. The
transfer types are data, address, etc.
HBIL. If this is low it indicates that the current byte is the first byte; if it is high, it
indicates that it is second byte.
HR/W indicates if the host is carrying out a read operation or a write operation
4.3.5. Clock Generator:
The clock generator on TMS320C54xx devices has two options-an external clock
and the internal clock. In the case of the external clock option, a clock source is directly connected to
the device. The internal clock source option, on the other hand, uses an internal clock generator and a
phase locked loop (PLL) circuit. The PLL, in turn, can be hardware configured or software
programmed. Not all devices of the TMS320C54xx family have all these clock options; they vary
from device to device.
4.3.6. Serial I/O Ports:
Three types of serial ports are available:
Synchronous ports.
Buffered ports.
Time-division multiplexed ports.
Dept.ECE, SJBIT

Page 112

DSP Algorithm and Architecture

10EC751

The synchronous serial ports are high-speed, full-duplex ports and that provide direct
communications with serial devices, such as codec, and analog-to-digital (A/D) converters. A buffered
serial port (BSP) is synchronous serial port that is provided with
an auto buffering unit and is clocked at the full clock rate. The head of servicing interrupts. A timedivision multiplexed (TDM) serial port is a synchronous serial port that is provided to allow timedivision multiplexing of the data. The functioning of each of these on-chip peripherals is controlled by
memory-mapped registers assigned to the respective peripheral.
4.4. Interrupts of TMS320C54xx Processors:
Many times, when CPU is in the midst of executing a program, a peripheral device may require
a service from the CPU. In such a situation, the main program may be interrupted by a signal
generated by the peripheral devices. This results in the processor suspending the main program in
order to execute another program, called interrupt service routine, to service the peripheral device. On
completion of the interrupt service routine, the processor returns to the main program to continue from
where it left.
Interrupt may be generated either by an internal or an external device. It may also be generated by
software. Not all interrupts are serviced when they occur. Only those interrupts that are called
nonmaskable are serviced whenever they occur. Other interrupts, which are called maskable interrupts,
are serviced only if they are enabled. There is also a priority to determine which interrupt gets serviced
first if more than one interrupts occur simultaneously.
Almost all the devices of TMS320C54xx family have 32 interrupts. However, the
types and the number under each type vary from device to device. Some of these interrupts are
reserved for use by the CPU.
4.5. Pipeline operation of TMS320C54xx Processors:
The CPU of 54xx devices have a six-level-deep instruction pipeline. The six stages of the
pipeline are independent of each other. This allows overlapping execution of instructions. During any
given cycle, up to six different instructions can be active, each at a different stage of processing. The
six levels of the pipeline structure are program prefetch, program fetch, decode, access, read and
execute.
1 During program prefetch, the program address bus, PAB, is loaded with the address of the next
instruction to be fetched.
2 In the fetch phase, an instruction word is fetched from the program bus, PB, and loaded into the
instruction register, IR. These two phases from the instruction
fetch sequence.
3 During the decode stage, the contents of the instruction register, IR are decoded to determine the
type of memory access operation and the control signals required for the data-address generation unit
and the CPU.
4 The access phase outputs the read operands on the data address bus, DAB. If a second operand is
required, the other data address bus, CAB, also loaded with an appropriate address. Auxiliary
registers in indirect addressing mode and the stack pointer (SP) are also updated.
Dept.ECE, SJBIT

Page 113

DSP Algorithm and Architecture

10EC751

5 In the read phase the data operand(s), if any, are read from the data buses, DB and CB. This phase
completes the two-phase read process and starts the two phase write processes. The data address of the
write operand, if any, is loaded into the data write address bus, EAB.
6 The execute phase writes the data using the data write bus, EB, and completes the operand write
sequence. The instruction is executed in this phase.

Dept.ECE, SJBIT

Page 114

DSP Algorithm and Architecture

10EC751

Recommended Questions:
1. Describe Host Port Interface and explain its signals.
2. writes an assembly language program of TMS320C54XX processors to compute the sum of
three product terms given by the equation y(n)=h(0)x(n)+h(1)x(n-1)+h(2)x(n-2) with usual
notations. Find y (n) for signed 16 bit data samples and 16 bit constants.
3. Describe the pipelining operation of TMS320C54XX processors.
4. Explain the operation of serial I/O ports and hardware timer of TMS320C54XX on chip
peripherals.
5. Expalin the differents types ofinterrupts in TMS320C54xx Processors.
6. Describe the operation of the following instructions of TMS 320c54xx processor, with example
Describe the operation of hardware timer with neat diagram.
7. By means of a figure explain the pipeline operation of the following sequence of instruction if
the initial values of AR1,AR3,A are 104,101,2 and the values stored in the memory locations
101,102,103,104 are 4,6,8,12. Also provide the values of registers AR3, AR1,T & A.
8. Describe the operation of the following instructions of TMS320C54XX processors.
9. Describe the operation of the following instructions of TMS320C54XX processors. (July 12,
8m)
10. Explain the following assembler directives of TMS320C54XX processors (i) .mmregs (ii)
.global (iii) .include xx (iv) .data ( v) .end (vi) .bss

(Dec 09/Jan 10 6marks)

11. Describe Host Port Interface and explain its signals. (Dec 09/Jan 10 6marks)
12. writes an assembly language program of TMS320C54XX processors to compute the sum of
three product terms given by the equation y(n)=h(0)x(n)+h(1)x(n-1)+h(2)x(n-2) with usual
notations. Find y (n) for signed 16 bit data samples and 16 bit constants. (May/June 2011,
6m)
13. Describe the pipelining operation of TMS320C54XX processors.(Dec.11, 8m)
14. Explain the operation of serial I/O ports and hardware timer of TMS320C54XX on chip
peripherals. (Dec.11, 8m)
15. Expalin the differents types ofinterrupts in TMS320C54xx Processors.(May/June 2009, 6m)

Dept.ECE, SJBIT

Page 115

DSP Algorithm and Architecture

10EC751

UNIT-5
Implementation of Basic DSP Algorithms
Syllabus:IMPLEMENTATION OF BASIC DSP ALGORITHMS: Introduction, The Q-notation, FIR Filters,
IIR Filters, Interpolation and Decimation Filters (one example in each case).
6 Hours
TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

5.1 Introduction:
In this unit, we deal with implementations of DSP algorithms & write programs to implement
the core algorithms only. However, these programs can be combined with input/output routines to
create applications that work with a specific hardware.
Q-notation
FIR filters
IIR filters
Interpolation filters
Decimation filters
5.2 The Q-notation:
DSP algorithm implementations deal with signals and coefficients. To use a fixed point DSP
device efficiently, one must consider representing filter coefficients and signal samples using fixedpoint2s complement representation. Ex: N=16, Range: -2N-1 to +2N-1 -1(-32768 to
32767).Typically, filter coefficients are fractional numbers.
To represent such numbers, the Q-notation has been developed. The Q-notation specifies the number
of fractional bits.

Dept.ECE, SJBIT

Page 116

DSP Algorithm and Architecture

10EC751

A commonly used notation for DSP implementations is Q15. In the Q15 representation, the least
significant 15 bits represent the fractional part of a number. In a processor where 16 bits are used to
represent numbers, the Q15 notation uses the MSB to represent the sign of the number and the rest of
the bits represent the value of the number.
In general, the value of a 16-bit Q15 number N represented as:

Multiplication of numbers represented using the Q-notation is important for DSP implementations.
Figure 5.1(a) shows typical cases encountered in such implementations.

Dept.ECE, SJBIT

Page 117

DSP Algorithm and Architecture

10EC751

5.3 FIR Filters:

A finite impulse response (FIR) filter of order N can be described by the difference equation.

The expanded form is y(n)=h(N-1)x(n-(N-1))+h(N-2)x(n-(N-2))+ ...h(1)x(n-1)+h(0)x(n)

Dept.ECE, SJBIT

Page 118

DSP Algorithm and Architecture

10EC751

Figure 5.2 A FIR filter implementation block diagram

The implementation requires signal delay for each sample to compute the next output,
y(n+1), is given as y(n+1)=h(N-1)x(n-(N-2))+h(N-2)x(n-(N-3))+ ...h(1)x(n)+h(0)x(n+1) Figure 5.3
shows the memory organization for the implementation of the filter. The filter Coefficients and the
signal samples are stored in two circular buffers each of a size equal to the filter. AR2 is used to point
to the samples and AR3 to the coefficients. In order to start with the last product, the pointer register
AR2 must be initialized to access the signal sample x(2-(N-1)), and the pointer register AR3 to access
the filter coefficient h(N-1). As each product is computed and added to the previous result, the pointers
advance circularly. At the end of the computation, the signal sample pointer is at the oldest sample,
which is replaced with the newest sample to proceed with the next output computation.

Program to implement an FIR filter:

It implements the following equation;
y(n)=h(N-1)x(n-(N-1))+h(N-2)x(n-(N-2))+ ...h(1)x(n-1)+h(0)x(n)
Where N = Number of filter coefficients = 16.
h(N-1), h(N-2),...h(0) etc are filter coefficients (q15numbers) .
The coefficients are available in file: coeff_fir.dat.
x(n-(N-1)),x(n-(N-2),...x(n) are signal samples(integers).
The input x(n) is received from the data file: data_in.dat.
The computed output y(n) is placed in a data buffer.

Dept.ECE, SJBIT

Page 119

DSP Algorithm and Architecture

10EC751

Dept.ECE, SJBIT

Page 120

DSP Algorithm and Architecture

10EC751

FIR Filter Routine

; Enter with A=the current sample x(n)-an integer, AR2 pointing to the location for the current sample
x(n),andAR3pointingtotheq15coefficienth(N-1). Exit with A = y(n) as q15 number.

5.4 IIR Filters:

An infinite impulse response (IIR) filter is represented by a transfer function, which is a ratio of two
polynomials in z. To implement such a filter, the difference equation representing the transfer function
can be derived and implemented using multiply and add operations. To show such an implementation,
we consider a second order transfer function given by

Dept.ECE, SJBIT

Page 121

DSP Algorithm and Architecture

10EC751

Figure5.4 Block diagram of second order IIR filter

Program for IIR filter:

The transfer function is

Which is equivalent to the equations:

w(n) = x(n) + a1.w(n-1) + a2.w(n-2)
y(n) = b0.w(n) + b1.w(n-1) + b2.w(n-2)
Where w(n), w(n-1), and w(n-2) are the intermediate variables used in computations (integers).a1, a2,
b0, b1, and b2 are the filter coefficients (q15 numbers). x(n) is the input sample (integer). Input
samples are placed in the buffer, In Samples, from a data file, data_in.dat y(n) is the computed output
(integer). The output samples are placed in a buffer, Out Samples.

Dept.ECE, SJBIT

10EC751

5.6 Decimation Filters:

A decimation filter is used to decrease the sampling rate. The decrease in sampling rate can be
achieved by simply dropping samples. For instance, if every other
sample of a sampled sequence is dropped, the sampling the rate of the resulting sequence will be half
that of the original sequence. The problem with dropping samples is that the new sequence may violate
the sampling theorem, which requires that the sampling frequency must be greater than two times the
highest frequency contents of the signal.
To circumvent the problem of violating the sampling theorem, the signal to be decimated is first
filtered using a low pass filter. The cutoff frequency of the filter is chosen so that it is less than half the
final sampling frequency. The filtered signal can be
decimated by dropping samples. In fact, the samples that are to be dropped need not be computed at
all. Thus, the implementation of a decimator is just a FIR filter implementation in which some of the
outputs are not calculated.
Figure 5.8 shows a block diagram of a decimation filter. Digital decimation can be
implemented as depicted in Figure 5.9 for an example of a decimation filter with decimation factor of
3. It uses a low pass FIR filter with 5 taps. The computation is similar to that of a FIR filter. However,
after computing each output sample, the signal array is delayed by three sample intervals by bringing
the next three samples into the circular buffer to replace the three oldest samples.

Figure 5.8: The decimation process

Dept.ECE, SJBIT

Dept.ECE, SJBIT

Page 131

DSP Algorithm and Architecture

10EC751

Unit 6
Implementation of FFT algorithms
Syllabus:IMPLEMENTATION OF FFT ALGORITHMS: Introduction, An FFT Algorithm for DFT
Computation, Overflow and Scaling, Bit-Reversed Index Generation & Implementation on the
TMS32OC54xx.
6 Hours

TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

6.1 Introduction: The N point Discrete Fourier Transform (DFT) of x(n) is a discrete
signal of length N is given by eq(6.1)

By referring to eq (6.1) and eq (6.2), the difference between DFT & IDFT are seen to be
Dept.ECE, SJBIT

Page 132

DSP Algorithm and Architecture

10EC751

the sign of the argument for the exponent and multiplication factor, 1/N. The computational
complexity in computing DFT / I DFT is thus same (except for the additional multiplication factor in
IDFT). The computational complexity in computing each X(k) and all the x(k) is shown in table 6.1.

In a typical Signal Processing System, shown in fig 6.1 signal is processed using DSP in the DFT
domain. After processing, IDFT is taken to get the signal in its original domain. Though certain
amount of time is required for forward and inverse transform, it is because of the advantages of
transformed domain manipulation, the signal processing is carried out in DFT domain. The
transformed domain manipulations are sometimes simpler. They are also more useful and powerful
than time domain manipulation. For example, convolution in time domain requires one of the signals
to be folded, shifted and multiplied by another signal, cumulatively. Instead, when the signals to be
convolved are transformed to DFT domain, the two DFT are multiplied and inverse transform is taken.
Thus, it simplifies the process of convolution.

6.2 An FFT Algorithm for DFT Computation: As DFT / IDFT are part of signal processing system,
there is a need for fast computation of DFT / IDFT. There are algorithms available for fast
computation of DFT/ IDFT. There are referred to as Fast Fourier Transform (FFT) algorithms. There
are two FFT algorithms: Decimation-In-Time
FFT (DITFFT) and Decimation-In-Frequency FFT (DIFFFT). The computational complexity of both
the algorithms are of the order of log2(N). From the hardware / software implementation viewpoint the
algorithms have similar structure throughout the
computation. In-place computation is possible reducing the requirement of large memory locations.
The features of FFT are tabulated in the table 6.2.

Dept.ECE, SJBIT

Page 133

DSP Algorithm and Architecture

10EC751

Consider an example of computation of 2 point DFT. The signal flow graph of 2 point DITFFT
Computation is shown in fig 6.2. The input / output relations is as in eq (6.3) which are arrived at from
eq(6.1).

Similarly, the Butterfly structure in general for DITFFT algorithm is shown in fig. 6.3. The signal flow
graph for N=8 point DITFFT is shown in fig. 4. The relation between input and output of any Butterfly
structure is shown in eq (6.4) and eq(6.5).

Dept.ECE, SJBIT

Page 134

10EC751

6.4 Bit-Reversed Index Generation: As noted in table 6.2, DITFFT algorithm requires input in bit
reversed order. The input sequence can be arranged in bit reverse order by reverse carry add operation.
Add half of DFT size (=N/2) to the present bit reversed ndex to get next bit reverse index. And employ
reverse carry propagation while adding bits from left to right. The original index and bit reverse index
for N=8 is listed in table 6.3

Dept.ECE, SJBIT

Page 139

DSP Algorithm and Architecture

10EC751

Consider an example of computing bit reverse index. The present bit reversed index be
110. The next bit reversed index is

There are addressing modes in DSP supporting bit reverse indexing, which do the computation of
reverse index.
6.5 Implementation of FFT on TMS32OC54xx: The main program flow for the implementation of
DITFFT is shown in fig. 6.10. The subroutines used are _clear to clear all the memory locations
reserved for the results. _bitrev stores the data sequence x (n) in bit reverse order. _butterfly computes
the four equations of computing real and imaginary parts of butterfly structure. _spectrum computes
the spectrum of x (n). The Butterfly subroutine is invoked 12 times and the other subroutines are
invoked only once.

Dept.ECE, SJBIT

Page 140

10EC751

Dept.ECE, SJBIT

Page 144

DSP Algorithm and Architecture

10EC751

Figure 6.18 depicts the part of the main program that invokes butterfly subroutine by supplying
appropriate inputs, A and B to the subroutine. The associated butterfly structure is also shown for
quick reference. Figures 6.19 and 6.20 depict the main program for the computation of 2nd and 3rd
stage of butterfly.

Dept.ECE, SJBIT

Page 145

DSP Algorithm and Architecture

10EC751

Unit 7
Interfacing Memory & Parallel I/O Peripherals
to DSP Devices
Syllabus:INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP DEVICES:
Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface,
Parallel I/O Interface, Programmed I/O, Interrupts and I / O Direct Memory Access (DMA).
8 Hours
TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

7.1 Introduction: A typical DSP system has DSP with external memory, input devices and output
devices. Since the manufacturers of memory and I/O devices are not same as that of manufacturers of
DSP and also since there are variety of memory and I/O devices available, the signals generated by
DSP may not suit memory and I/O devices to be connected to DSP. Thus, there is a need for
interfacing devices the purpose of it being to use DSP signals to generate the appropriate signals for
setting up communication with the memory. DSP with interface is shown in fig. 7.1.

Dept.ECE, SJBIT

Page 153

DSP Algorithm and Architecture

10EC751

7.2 Memory Space Organization: Memory Space in TMS320C54xx has 192K words of 16 bits each.
Memory is divided into Program Memory, Data Memory and I/O Space, each are of 64K words. The
actual memory and type of memory depends on particular DSP device of the family. If the memory
available on a DSP is not sufficient for an application, it can be interfaced to an external memory as
depicted in fig. 7.2. The On- Chip Memory are faster than External Memory. There are no interfacing
requirements. Because they are on-chip, power consumption is less and size is small. It exhibits better
performance by DSP because of better data flow within pipeline. The purpose of such memory is to
hold Program / Code / Instructions, to hold constant data such as filter coefficients / filter order, also to
hold trigonometric tables / kernels of transforms employed in an algorithm. Not only constants are
stored in such memory, they are also used to hold variable data and intermediate results so that the
processor need not refer to external memory for the purpose.

Dept.ECE, SJBIT

Page 154

DSP Algorithm and Architecture

10EC751

External memory is off-chip. They are slower memory. External Interfacing is required to
establish the communication between the memory and the DSP. They can be with large memory
space. The purpose is being to store variable data and as scratch pad memory. Program memory can be
ROM, Dual Access RAM (DARAM), Single Access RAM (SARAM), or a combination of all these.
The program memory can be extended externally to 8192K words. That is, 128 pages of 64K words
each. The arrangement of memory and DSP in the case of Single Access RAM (SARAM) and Dual
Access RAM (DARAM) is shown in fig. 7.3. One set of address bus and data bus is available in the
case of SARAM and two sets of address bus and data bus is available in the case of DARAM. The
DSP can thus access two memory locations simultaneously.

There are 3 bits available in memory mapped register, PMST for the purpose of on-chip
memory mapping. They are microprocessor / microcomputer mode. If this bit is 0, the on-chip ROM is
enabled and addressable and if this bit is 1 the on-chip ROM not available. The bit can be manipulated
by software / set to the value on this pin at system
reset. Second bit is OVLY. It implies RAM Overlay. It enables on-chip DARAM data memory blocks
to be mapped into program space. If this bit is 0, on-chip RAM is addressable in data space but not in
Program Space and if it is 1, on-chip RAM is mapped into Program & Data Space. The third bit is
DROM. It enables on-chip DARAM 4-7 to be mapped into data space. If this bit is 0, on-chip
DARAM 4-7 is not mapped into data space and if this bit is 1, on-chip DARAM 4-7 is mapped into
Data Space. On-chip data memory is partitioned into several regions as shown in table 7.1. Data
memory can be onchip / off-chip.

Dept.ECE, SJBIT

Page 155

10EC751

10EC751

Unit 8
Interfacing and Applications of DSP Processor
Syllabus:INTERFACING AND APPLICATIONS OF DSP PROCESSOR: Introduction, Synchronous
Serial Interface, A CODEC Interface Circuit. DSP Based Bio-telemetry Receiver, A Speech
Processing System, An Image Processing System.
6 Hours
TEXT BOOK:

Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.

REFERENCE BOOKS:

8.1 Introduction: In the case of parallel peripheral interface, the data word will be transferred with all
the bits together. In addition to parallel peripheral interface, there is a
need for interfacing serial peripherals. DSP has provision of interfacing serial devices too.
8.2 Synchronous Serial Interface: There are certain I/O devices which handle transfer
of one bit at a time. Such devices are referred to as serial I/O devices or peripherals. Communication
with serial peripherals can be synchronous, with processor clock as reference or it can be
asynchronous. Synchronous serial interface (SSI) makes communication a fast serial communication
and asynchronous mode of communication is slow serial communication. However, in comparison
with parallel peripheral interface,
the SSI is slow. The time taken depends on the number of bits in the data word.
8.3 CODEC Interface Circuit: CODEC, a coder-decoder is an example for synchronous serial I/O. It
has analog input-output, ADC and DAC. The signals in SSI generated by the DSP are DX: Data
Transmit to CODEC, DR: Data Receive from CODEC, CLKX: Transmit data with this clock
reference, CLKR: Receive data with this clock reference, FSX: Frame sync signal for transmit, FSR:
Frame sync signal for receive, First bit, during transmission or reception, is in sync with these signals,
RRDY: indicator for receiving all bits of data and XRDY: indicator for transmitting all bits of data.
Similarly, on the CODEC side, signals are FS*: Frame sync signal, DIN: Data Receive from DSP,
DOUT: Data Transmit to DSP and SCLK: Tx / Rx data with this clock reference. The block diagram
Dept.ECE, SJBIT

Page 169

DSP Algorithm and Architecture

10EC751

depicting the interface between TMS320C54xx and CODEC is shown in fig. 8.1. As only one signal
each is available on CODEC for clock and frame synchronization, the related DSP side signals are
connected together to clock and frame sync signals on CODEC. Fig. 8.2 and fig. 8.3 show the timings
for receive and transmit in SSI, respectively.

As shown, the receiving or transmit activity is initiated at the rising edge of clock, CLKR
/ CLKX. Reception / Transfer starts after FSR / FSX remains high for one clock cycle. RRDY /
XRDY is initially high, goes LOW to HIGH after the completion of data transfer. Each transfer of bit
requires one clock cycle. Thus, time required to transfer / receive data word depends on the number of
bits in the data word. An example of data word of 8 bits is shown in the fig. 8.2 and fig. 8.3.
Dept.ECE, SJBIT

Page 170

DSP Algorithm and Architecture

10EC751

Fig. 8.4 shows the block diagram of PCM3002 CODEC. Analog front end samples signal at 64X over
sampling rate. It eliminates need for sample-and-hold circuit and simplifies need for anti aliasing filter.
ADC is based on Delta-sigma modulator to convert analog signal to digital form. Decimation filter
reduces the sampling rate and thus processing does not need high speed devices. DAC is Delta-sigma
modulator, converts digital signal to analog signal. Interpolation increases the sampling rate back to
original value. LPF smoothens the analog reconstructed signal by removing high frequency
components. The Serial Interface monitors serial data transfer. It accepts built-in ADC output and
converts to serial data and transmits the same on DOUT. It also accepts serial data on DIN & gives the
Dept.ECE, SJBIT

Page 171

DSP Algorithm and Architecture

10EC751

same to DAC. The serial interface works in synchronization with BCLKIN & LRCIN. The Mode
Control initializes the serial data transfer. It sets all the desired modes, the number of bits and the
mode Control Signals, MD, MC and ML. MD carries Mode Word. MC is the mode Clock Signal. MD
to be loaded is sent with reference to this clock. ML is the mode Load Signal. It defines start and end
of latching bits into CODEC device.
Figure 8.5 shows interfacing of PCM3002 to DSP in DSK. DSP is connected to PCM3002 through
McBSP2. The same port can be connected to HPI. Mux selects one among these two based on CPLD
signal. CPLD in Interface also provides system clock for DSP and for CODEC, Mode control signals
for CODEC. CPLD generates BCLKIN and LRCIN signals required for serial interface.

PCM3002 CODEC handles data size of 16 / 20 bits. It has 64x over-sampling, delta-sigma ADC &
DAC. It has two channels, called left and right. The CODEC is programmable for digital de-emphasis,
digital attenuation, soft mute, digital loop back, power-down mode. System clock, SYSCLK of
CODEC can be 256fs, 384fs or 512fs. Internal clock is always 256fs for converters, digital filters.
DIN, DOUT are the single line data lines to carry the data into the CODEC and from CODEC.
Another signal BCLKIN is data bit clock, the default value of which is CODEC SYSCLK / 4. LRCIN
is frame sync signal for Left and Right Channels. The frequency of this signal is same as the sampling
Dept.ECE, SJBIT

Page 172

DSP Algorithm and Architecture

10EC751

frequency. The default divide factor can be 2, 4, 6 and 8. Thus, sampling rate is minimum of 6 KHz
and maximum of 48 KHz.
Problem P8.1: A PCM3002 is programmed for the 12 KHz sampling rate. Determine the divisor N
that should be written to the CPLD of the DSK and the various clock frequencies for the set up.
Solution: CPLD input Clock=12.288MHz (known)
Sampling rate fs=CODEC_SYSCLK / 256 =12KHz (given)
CPLD output clock, CODEC_SYSCLK =12.288 x 106 / N
Thus, CODEC_SYSCLK =256 x 12 KHz
& N=12.288 x 106/(256 x 12 x 103)
=4
Problem P8.3: Frame Sync is generated by dividing the 8.192MHz clock by 256 for the
serial communication. Determine the sampling rate and the time a 16 bit sample takes when
transmitted on the data line.
Solution: LRCIN, Frame Sync = 8.192x106/256 =32 KHz
Sampling rate fs= frequency of LRCIN=32 KHz
BCLKIN, Bit clock rate=CODEC_SYSCLK / 4=8.192x106/4=2.048MHz

LRCIN, Frame Sync = 8.192x10^6/256 =32 KHz

Sampling rate fs= frequency of LRCIN=32 KHz
BCLKIN, Bit clock rate=CODEC_SYSCLK / 4=8.192x10^6/4=2.048MHz
Bit clock period= 1/2.048x10^6 =0.488x10^-6s
Time for transmitting 16 bits =0.488x10^-6x16 =7.8125x10^-6s (refer fig. P8.3)

Dept.ECE, SJBIT

Page 173

DSP Algorithm and Architecture

10EC751

The CODEC PCM3002 supports four data formats as listed in table 8.1. The four data formats depend
on the number of bits in the data word, if the data is right justified or left justified with respect to
LRCIN and if it is I2S (Integrated Inter-chip Sound) format.

Figure 8.6 and fig. 8.7 depicts the data transaction for CODEC PCM3002. As shown in fig. 8.6, DIN (/
DOUT) carries the data. BCLKIN is the reference for transfer. When LRCIN is high, left channel
inputs (/ outputs) the data and when LRCIN is low, right channel inputs (/ outputs) the data. The data
bits at the end (/ beginning) of the LRCIN thus Right (/ left) justified.

Another data format handled by PCM3002 is I2S (Integrated Inter-chip Sound). It is used for
transferring PCM between CD transport & DAC in CD player. LRCIN is low for left channel and high
for right channel in this mode of transfer. During the first BCKIN, there is no transmission by ADC.
During 2nd BCKIN onwards, there is transmission with MSB first and LSB last. Left channel data is
handled first followed by right channel data.

Page 176

DSP Algorithm and Architecture

10EC751

A DSP based PPM signal decoding is shown in fig. 8.11. PPM signal interface generates the interrupt
for DSP. DSP entertains the interrupt and starts a timer. When it receives another interrupt, it stops the
timer and the count is treated as the digital equivalent of the sample value. The process repeats. Dual
DAC converts two signals encoded into analog signals. And heart rate is determined referring to the
ECG obtained by decoding

Heart Rate (HR) is a measure of time interval between QRS complexes in ECG signal. QRS complex
in ECG is an important segment representing the heart beat. There is periodicity in its appearance
indicating the heart rate. The algorithm is based on 1st and 2nd order absolute derivatives of the ECG
signal. Since absolute value of derivative is taken, the filter will be a nonlinear filtering.

Dept.ECE, SJBIT

Page 177

DSP Algorithm and Architecture

10EC751

Mean of half of peak amplitudes is determined, which is threshold for detection of QRS complex.
QRS interval is then the time interval between two such peaks. Time Interval between two peaks is
determined using internal timer of DSP. Heart Rate, heart beat perminute is computed using the
relation HR=Sampling rate x 60 / QRS interval. The signals at various stages are shown in fig. 8.12.

Dept.ECE, SJBIT

Page 178

DSP Algorithm and Architecture

10EC751

8.5 A Speech Processing System: The purpose of speech processing is for analysis, transmission or
reception as in the case of radio / TV / phone, denoising, compression and so on. There are various
applications of speech processing which include identification and verification of speaker, speech
synthesis, voice to text conversion and
vice versa and so on. A speech processing system has a vocoder, a voice coding / decoding circuit.
Schematic of speech production is shown in fig. 8.13. The vocal tract has vocal cord at one end and
mouth at the other end. The shape of the vocal tract depends on position of lips, jaws, tongue and the
velum. It decides the sound that is produced. There is another tract, nasal tract. Movement of velum
connects or disconnects nasal tract. The overall voice that sounds depends on both, the vocal tract and
nasal tract.
Two types of speech are voiced sound and unvoiced sound. Vocal tract is excited with quasi periodic
pulses of air pressure caused by vibration of vocal cords resulting in voiced sound. Unvoiced sound is
produced by forcing air through the constriction, formed somewhere in the vocal tract and creating
turbulence that produces source of noise to excite the vocal tract.

By the understanding of speech production mechanism, a speech production model representing the
same is shown in fig. 8.14. Pulse train generator generates periodic pulse train. Thus it represents the
voiced speech signal. Noise generator represents unvoiced speech. Vocal tract system is supplied
either with periodic pulse train or noise. The final output is the synthesized speech signal.
Sequence of peaks occurs periodically in voiced speech and it is the fundamental frequency of speech.
The fundamental frequency of speech differs from person to person and hence sound of speech differs
from person to person. Speech is a non stationary signal. However, it can be considered to be
relatively stationary in the intervals of 20ms. Fundamental frequency of speech can be determined by
Dept.ECE, SJBIT

Page 179

DSP Algorithm and Architecture

10EC751

autocorrelation method. In other words, it is a method of determination of pitch period. Periodicity in

autocorrelation is because of the fundamental frequency of speech. A three level clipping scheme is
discussed here to measure the fundamental frequency of speech. The block diagram for the same is
shown in fig. 8.15.

The speech signal s(t) is filtered to retain frequencies up to 900Hz and sampled using ADC to get s(n).
The sampled signal is processed by dividing it into set of samples of 30ms duration with 20ms overlap
of the windows. The same is shown in fig. 8.16.

Dept.ECE, SJBIT

Page 180

DSP Algorithm and Architecture

10EC751

A threshold is set for three level clipping by computing minimum of average of absolute values of 1st
100 samples and last 100 samples. The scheme is shown in fig. 8.17.

The transfer characteristics of three level clipping circuit is shown in fig. 8.18. If the sample value is
greater than +CL, the output y(n) of the clipper is set to 1. If the sample value is more negative than -

Dept.ECE, SJBIT

Page 181

DSP Algorithm and Architecture

10EC751

CL, the output y(n) of the clipper is set to -1. If the sample value is between CL and +CL, the output
y(n) of the clipper is set to 0.

The autocorrelation of y(n) is computed which will be 0,1 or -1 as defined by eq (1). The largest peak
in autocorrelation is found and the peak value is compared to a fixed threshold. If the peak value is
below threshold, the segment of s(n) is classified as unvoiced segment. If the peak value is above
threshold, the segment of s(n) is classified
as voiced segment. The functioning of autocorrelation is shown in fig. 8.19.

As shown in fig. 8.19, A is a sample sequence y(n). B is a window of samples of length N and it is
compared with the N samples of y(n). There is maximum match. As the window is moved further, say
to a position C the match reduces. When window is moved further say to a position D, again there is
maximum match. Thus, sequence y(n) is periodic. The period of repetition can be measured by
locating the peaks and finding the time gap between them.

Dept.ECE, SJBIT

Page 182

DSP Algorithm and Architecture

10EC751

8.5 An Image Processing System: In comparison with the ECG or speech signal considered so far,
image has entirely different requirements. It is a two dimensional signal. It can be a color or gray
image. A color image requires 3 matrices to be maintained for three primary colors-red, green and
blue. A gray image requires only one
matrix, maintaining the gray information of each pixel (picture cell). Image is a signal with large
amount of data. Of the many processing, enhancement, restoration, etc., image compression is one
important processing because of the large amount of data in image.
To reduce the storage requirement and also to reduce the time and band width required to transmit the
image, it has to be compressed. Data compression of the order of factor 50 is sometimes preferred.
JPEG, a standard for image compression employs lossy compression technique. It is based on discrete
cosine transform (DCT). Transform domain compression separates the image signal into low
frequency components and high frequency components. Low frequency components are retained
Dept.ECE, SJBIT

Page 183

DSP Algorithm and Architecture

10EC751

because they represent major variations. High frequency components are ignored because they
represent minute variations and our eye is not sensitive to minute variations.
Image is divided into blocks of 8 x 8. DCT is applied to each block. Low frequency coefficients are of
higher value and hence they are retained. The amount of high frequency components to be retained is
decided by the desirable quality of reconstructed image. Forward DCT is given by eq (2).

Since the coefficients values may vary with a large range, they are quantized. As already noted low
frequency coefficients are significant and high frequency coefficients are insignificant, they are
allotted varying number of bits. Significant coefficients are quantized precisely, with more bits and
insignificant coefficients are quantized coarsely,
with fewer bits. To achieve this, a quantization table as shown in fig. 8.20 is employed. The contents
of Quantization Table indicate the step size for quantization. An entry as smaller value implies smaller
step size, leading to more bits for the coefficients and vice
versa.

The quantized coefficients are coded using Huffman coding. It is a variable length coding Huffman
Encoding. Shorter codes are allotted for frequently occurring long sequence of 1s & 0s. Decoding
requires Huffman table and dequantization table. Inverse DCT is taken employing eq(3). The data
blocks so obtained are combined to form complete image. The schematic of encoding and decoding is
shown in fig. 8.21.

Dept.ECE, SJBIT

Page 184

DSP Algorithm and Architecture

10EC751

Recommended Questions:
1. With the help of a block diagram, explain the image compression and reconstruction using
JPEG encoder and decoder.
2. Write a pseudo algorithm heart rate(HR), using the digital signal processor.
3. Explain briefly the building blocks of a PCM3002 CODEC device. What do you understand by
a DSP based biotelemetry receiver?
4. With the help of block diagram explain JPEG algorithm.
5. Explain with the neat diagram the operation of pitch detector.
6. Explain with a neat diagram, the synchronous serial interface between the C54xx and a
CODEC device. Explain the operation of pulse position modulation (PPM) to encode two
biomedical signals.
7. Explain with a neat block diagram the operation, the operation of the pitch detector.
Dept.ECE, SJBIT

Page 185

DSP Algorithm and Architecture

10EC751

8. Explain PCM3002 CODEC, with the help of neat block diagram.

9. Explain DSP based biotelemetry receiver system, with the help of a block schematic diagram.
10. Explain the memory interface block diagram for the TMS 320 C54xx processor.(Dec 2010)
11. Draw the I/O interface timing diagram for read write read sequence of operation (Dec 2010)
12. What are interrupts? How interrupts are handled by C54xx DSP Processors. (Dec 2010,12)
13. What are interrupts? What are the classes of interrupts available in the TMS320C54xx
processor. (JUNE/July 11, 8m)

Dept.ECE, SJBIT

Page 186

Model QP Solution
No ratings yet
Model QP Solution
23 pages
Speech PROCESSING NOTES 8TH SEM VTU Module3
100% (1)
Speech PROCESSING NOTES 8TH SEM VTU Module3
26 pages
Oracle DB Basic Commands
75% (4)
Oracle DB Basic Commands
1 page
Ece Vii DSP Algorithms Architecture 10ec751 Notes
No ratings yet
Ece Vii DSP Algorithms Architecture 10ec751 Notes
181 pages
Ece-Vii-dsp Algorithms & Architecture (10ec751) - Question Paper
No ratings yet
Ece-Vii-dsp Algorithms & Architecture (10ec751) - Question Paper
9 pages
Networksecurity3rdmoduledr 230408050150 852c8d47
No ratings yet
Networksecurity3rdmoduledr 230408050150 852c8d47
37 pages
DC Simp
No ratings yet
DC Simp
3 pages
Introduction To Big data-21CS753-syllabus
No ratings yet
Introduction To Big data-21CS753-syllabus
3 pages
Mobile Communications: Chapter # 3 (Rappaport)
No ratings yet
Mobile Communications: Chapter # 3 (Rappaport)
28 pages
Question Bank New
No ratings yet
Question Bank New
3 pages
Ece
No ratings yet
Ece
75 pages
DSP LAB MANUAL 2017 ODD RMK PDF
100% (2)
DSP LAB MANUAL 2017 ODD RMK PDF
144 pages
Digital Signal Processing Question Bank PDF
No ratings yet
Digital Signal Processing Question Bank PDF
15 pages
Vlsi Lab Viva Questions and Answers
No ratings yet
Vlsi Lab Viva Questions and Answers
11 pages
18MAT41 Blow Up Syllabus
No ratings yet
18MAT41 Blow Up Syllabus
3 pages
Write A Program To Find The Shortest Path Between Vertices Using Bellman-Ford Algorithm
No ratings yet
Write A Program To Find The Shortest Path Between Vertices Using Bellman-Ford Algorithm
3 pages
VTU Exam Question Paper With Solution of 18EC54 Information Theory and Coding Jan-2021-Sridhar N - Suganya S - Harsha
No ratings yet
VTU Exam Question Paper With Solution of 18EC54 Information Theory and Coding Jan-2021-Sridhar N - Suganya S - Harsha
20 pages
Dip Notes 17ec72 Lecture Notes 1 5
No ratings yet
Dip Notes 17ec72 Lecture Notes 1 5
204 pages
Chapter 5: Image Transforms: (From Anil. K. Jain)
No ratings yet
Chapter 5: Image Transforms: (From Anil. K. Jain)
35 pages
TMS320c50 Programs
50% (2)
TMS320c50 Programs
28 pages
CU5151-Advanced Digital Communication Techniques
No ratings yet
CU5151-Advanced Digital Communication Techniques
15 pages
Vlsi Lab Question Set
100% (1)
Vlsi Lab Question Set
4 pages
DSP Mod1@AzDOCUMENTS - in
No ratings yet
DSP Mod1@AzDOCUMENTS - in
60 pages
Module 1 NS Notes
100% (1)
Module 1 NS Notes
27 pages
Ds Solved 2021-22
No ratings yet
Ds Solved 2021-22
54 pages
B.Tech EC Syllabus 3rd Year
No ratings yet
B.Tech EC Syllabus 3rd Year
35 pages
Course File
No ratings yet
Course File
254 pages
Concept Learning
No ratings yet
Concept Learning
85 pages
Ap7102 Adsd
No ratings yet
Ap7102 Adsd
5 pages
Cse III Computer Organization (15cs34) Question Paper
No ratings yet
Cse III Computer Organization (15cs34) Question Paper
4 pages
IO Blocks and Programmable Interconnection Points
No ratings yet
IO Blocks and Programmable Interconnection Points
29 pages
CSE-UG Curriculum and Syllabus - MEPCO
No ratings yet
CSE-UG Curriculum and Syllabus - MEPCO
212 pages
JNTUH - B Tech - 2019 - 3 2 - May - R18 - EEE - 136FT PCCN Principles of Computer Communications and
No ratings yet
JNTUH - B Tech - 2019 - 3 2 - May - R18 - EEE - 136FT PCCN Principles of Computer Communications and
2 pages
CC Mod5
No ratings yet
CC Mod5
121 pages
DLD GTU Question Bank: Chapter-1 Binary System
No ratings yet
DLD GTU Question Bank: Chapter-1 Binary System
129 pages
Question Bank
No ratings yet
Question Bank
23 pages
Ktu Syllabus
No ratings yet
Ktu Syllabus
87 pages
Priority Encoder
No ratings yet
Priority Encoder
5 pages
Lesson Plan DPSD
No ratings yet
Lesson Plan DPSD
5 pages
ITC Unit 4 Convolution Code
No ratings yet
ITC Unit 4 Convolution Code
12 pages
RTOS
0% (1)
RTOS
1 page
Antenna & Wave Propagation
No ratings yet
Antenna & Wave Propagation
175 pages
Dspa 17ec751 M5
No ratings yet
Dspa 17ec751 M5
34 pages
Dspa 17ec751 M2
No ratings yet
Dspa 17ec751 M2
27 pages
ASIC Placement
No ratings yet
ASIC Placement
28 pages
DDCA - CO-1 & 2 - Terminal Questions & Answers
No ratings yet
DDCA - CO-1 & 2 - Terminal Questions & Answers
15 pages
Ec8004-Wireless Networks - Handouts
No ratings yet
Ec8004-Wireless Networks - Handouts
30 pages
2marks With Answer
No ratings yet
2marks With Answer
46 pages
Table Look Up Decoding Using Standard Array
No ratings yet
Table Look Up Decoding Using Standard Array
6 pages
EC 2301 Digital Communication Unit I and II Question Bank
No ratings yet
EC 2301 Digital Communication Unit I and II Question Bank
63 pages
DSD Model Paper 2
No ratings yet
DSD Model Paper 2
8 pages
21EC72_Question Bank-2
No ratings yet
21EC72_Question Bank-2
2 pages
DIGITAL SYSTEMS LAB MCQs
No ratings yet
DIGITAL SYSTEMS LAB MCQs
5 pages
C Notes Python - World - in
No ratings yet
C Notes Python - World - in
291 pages
Digital Lab VIVA Questions
No ratings yet
Digital Lab VIVA Questions
4 pages
Baseband M Ary Transmission and Digital Subscriber Lines
100% (1)
Baseband M Ary Transmission and Digital Subscriber Lines
17 pages
Ece VII DSP Algorithms Architecture 10ec751 Notes PDF
No ratings yet
Ece VII DSP Algorithms Architecture 10ec751 Notes PDF
181 pages
ECE-VII-DSP ALGORITHMS & ARCHITECTURE Part A
No ratings yet
ECE-VII-DSP ALGORITHMS & ARCHITECTURE Part A
111 pages
Nba Document
No ratings yet
Nba Document
8 pages
DSP
0% (1)
DSP
3 pages
Some Case Studies on Signal, Audio and Image Processing Using Matlab
From Everand
Some Case Studies on Signal, Audio and Image Processing Using Matlab
Dr. Hedaya Mahmood Alasooly
No ratings yet
IES - Interview Toppers Scores
No ratings yet
IES - Interview Toppers Scores
1 page
Current Affairs PDF September 2015
No ratings yet
Current Affairs PDF September 2015
1 page
PXL BA
No ratings yet
PXL BA
3 pages
Defining Skew, Propagation-Delay, Phase Offset (Phase Error)
No ratings yet
Defining Skew, Propagation-Delay, Phase Offset (Phase Error)
10 pages
Tps 544 C 25
No ratings yet
Tps 544 C 25
100 pages
retrievePDF JSP
No ratings yet
retrievePDF JSP
2 pages
Crypto Currency Prediction Using Deep Learning in Bitcoin
No ratings yet
Crypto Currency Prediction Using Deep Learning in Bitcoin
66 pages
STM32 Firmware Upgrade Tool UGD V1.00
No ratings yet
STM32 Firmware Upgrade Tool UGD V1.00
18 pages
Difference Betweew Celeron and Pentium
No ratings yet
Difference Betweew Celeron and Pentium
3 pages
XenMobile Architecture
No ratings yet
XenMobile Architecture
31 pages
UMS Database Design v1
No ratings yet
UMS Database Design v1
10 pages
Decoder 2 To 4 With Enable
No ratings yet
Decoder 2 To 4 With Enable
2 pages
Cara Instal Oracle 11g
No ratings yet
Cara Instal Oracle 11g
10 pages
Interview Questions
No ratings yet
Interview Questions
52 pages
Map Tour - App Inventor For Android: Learn Tutorials
No ratings yet
Map Tour - App Inventor For Android: Learn Tutorials
6 pages
Online Phone Billing System
No ratings yet
Online Phone Billing System
78 pages
A Boolean Array Puzzle
No ratings yet
A Boolean Array Puzzle
3 pages
Microprocessor Lab Exercises
No ratings yet
Microprocessor Lab Exercises
5 pages
Software Directsoft5
No ratings yet
Software Directsoft5
6 pages
MC0073 System Programming
No ratings yet
MC0073 System Programming
35 pages
QV Imp Qus and Answers
No ratings yet
QV Imp Qus and Answers
131 pages
Data Extraction
No ratings yet
Data Extraction
153 pages
Automatic Goods Receipt For Co Products
No ratings yet
Automatic Goods Receipt For Co Products
3 pages
Fsd-Question Bank - Imp (Gtu Papers)
No ratings yet
Fsd-Question Bank - Imp (Gtu Papers)
2 pages
Masters in Computer Science Course Details
100% (2)
Masters in Computer Science Course Details
14 pages
16 Mark Questions OOAD
100% (2)
16 Mark Questions OOAD
9 pages
Chapter 6: Classes and Data Abstraction: - Object-Oriented Programming (OOP)
No ratings yet
Chapter 6: Classes and Data Abstraction: - Object-Oriented Programming (OOP)
44 pages
Palo Alto Networks - PA-5000 Series - Datasheet
No ratings yet
Palo Alto Networks - PA-5000 Series - Datasheet
2 pages
Fundamental Design Concepts
No ratings yet
Fundamental Design Concepts
9 pages
Drone Delivery Problem
No ratings yet
Drone Delivery Problem
11 pages
Disk Part
No ratings yet
Disk Part
2 pages
Ap7003 02
No ratings yet
Ap7003 02
15 pages
Term Paper On DBMS
No ratings yet
Term Paper On DBMS
27 pages
2013 Cc111 Int Comp Sheet 1 No Answer
No ratings yet
2013 Cc111 Int Comp Sheet 1 No Answer
8 pages
How To Hide Parameters On Selection Screen
No ratings yet
How To Hide Parameters On Selection Screen
6 pages