1-2 (Invited)

Process Innovation for Future Semiconductor Industry

M. OGIRIMA

Device Development Center, Hitachi, Ltd.,

Ome-shi, Imai 2326, Tokyo, Japan

Abstract 11 .Device develooment trends and scaliny strategies

During the last few years, the semiconductor The history of the development of LSI process
industry has been gradually deviating from its traditional technologies has been going along the same way as that
course. This change seems to be due to the diversification of fine patterning technology. Fine patterning brings LSIS
of market needs and to technical difficulties. TO break large integration and low-cost as well as high
through to future technological generations, new device performance. Advanced process technologies which were
and process concepts must be introduced . This paper developed for DRAM as a process driver have been
discusses several innovative processes for future applied step-by-step to many other devices such as
developments in the semiconductor industry. It suggests microcomputers, ASICs and analog LSIs. But in the sub
that material innovation is important for simplifying micron regime, the above trend has changed slightly.
device structure and lowering costs. Finer patterning accompanies with process complexity,
higher cost, and the slow down of bit cost improvement
which used to go down to 1/4 every generation. Also
large integration decreases flexibility of IC application
and lowers the capability of response to the needs of
market diversification. Beyond the 4Mb DRAMs
I. Introduction generation, system needs cannot keep pace with
Over the last two decades the semiconductor industry technology development speed, which slows down the
has made remarkable progress supported by the build-up of DRAM market. That is, the LSI market has
development of semiconductor technologies. During this been changing from a needs-driven one to a technology-
period, the integration of memory LSIs have increased by driven one.
4 times per generation and feature sizes have decreased On the other hamd, the* system trend is headin4 towards
by 0.7 times exactly followed a simple curve. But below down-sizing and needs diversification . The
-1.0 p m feature sizes(1Mb- 4Mb DRAMs), the simple macro-trend of system needs for LSIs are
trend has gradually changed. This change indicates that - Small size, value-added
the trend in chip price (constant, 7r -rule) has slowed - Low-voltage, low power-dissipation
down to a bi-rule. This might be the symptom of the - Large chip size/large integration
slow-down in the progress of semiconducto,r - Highspeed
technologies. So far, for the purpose of keeping this - Low cost
trend, many basic technologies have been investigated Without a scaling effect, it is very difficult to satisfy
and many kinds of new technologies have been these requirements, and in future, scaling will still be one
introduced for every generation. of the most important problem for system LSIs.
In this sense, the new technologies introduced have been User's requirements for the memories have become
becoming more difficult generation by generation. more diversified, such as byte-wide, synchronous high-
Especially the technology transfer from research and speed DRAMS, flashEEPROMs and FRAMs, which need
development to production has been becoming more a variety of process and device technologies. In the sub-
difficult because of the loss of margin. micron age, the prolonged DRAM generation
On the other hand, needs from a system side have (3-5yeardgeneration) and difficulties with fine patterning
diversified and usual high integration-low cost alone can have led to reconsideration of the traditional scaling
not keep up with the trend. These trends force the factor (- 0.65/generation). That is, the traditional
semiconductor industry to change its development generation of 3years has been divided into two or three
strategy. steps, "step-by-step scaling". DRAMs of three or four
In the above context, this paper describes the expected generations coexist in a market at any time, and the
innovations of process and material technologies which original 4Mb DRAM (0.8 p m-rule) is scaled down
are necessary for future semiconductor industry. The stepwise to 0.7 p m to 0.6 p m and 0.5 p m.
selected items are At the last step, the older generation DRAM (4Mb) is
- Device trerids produced using the newer generation (1 6Mb) technology
- Fine pattenling technology (cut down version). This tendency is more conspicuous
- Substrate engineering for logic LSI, and the progress or process technologies
- Simplified inulti-level metallization and design of logic LSI proceeds simultaneously-the age
- Challenge t3 low-cost process of concurrent engineering.
In the above background, close attention must be payed

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 for making development schedule of device and process Figure3 shows a feasible lithography scheme for 1Gb
technologies. DRAMs(O.15 /A m) taking all above improvements into
consideration. Applying all these technologies to
production will require improvements in other parameters
I11 .Macroscooic prosDects of Drocess technologies such as alignment accuracy while maintaining process
Development scheme of process technology should be margins.
considered for long-term, middle-term, and short-term. In A cost analysis for these new technologies is also given
this paper, middle-and long-term prospects are mainly in Fig, 3. This shows that fine patterning down to the
concerned. 0.2 j.i m generation can be achieved using ultraviolet
In order to improve LSI performances, miniaturization light, and beyond 0.2 /A m new light sources such as
is one of the most important technologies now and still in electron beam and X-ray will be needed. The success or
near future. However in the age of 16Mb DRAMs failure of X-ray lithography is thought to depend on the
(0.5 j.i m), the limit of process technologies with scaling reduction optical system (reduction mirror) and strong X-
has been tangible gradually. Indeed, in a laboratory, ray source (Synchrotron Orbital Radiation).
devices with 0.1 U , m rule are feasible, and 256Mb Resist materials are also an important factor, and higher
DRAM chips have been announced at conferences. Also, performance materials than the current chemical;
high-speed devices have shown remarkable progress such amplification types are needed for quarter-micron
as silicon bipolar/CMOS devices of tpd<20ps. lithography.
But, because of the complexity of device structure, From the viewpoint of fine patterning, dry etching is
process margin is decreasing in the age of deep-sub micron, very important as well as lithography. The problems of
and yields are decreasing in the stage of mass production. dry etching are
For DRAMs from the generation of lMb, bit redundancy - Control of pattern size (- 1/10 of minimum pattern
technology has been introduced, and as a result apparent size),
yield of 4Mb is almost the same as lMb, though net yield - Etching of new materials (high E dielectrics, copper
obviously decreases, as indicated in Fig, 1. This etc.),
tendency is thought to be due to the defect density and - Sequential etching of multi-layered films,
also to the decrease in process margin caused by the - Selectivity,
complexity of device structure and miniaturization. - Etching rate uniformity of large diameter wafers.
Table 1, lists important problems in device and process So far, dry etching technologies are somewhat empirical
technologies and feasible solutions. linproving the and the plasma field cannot be completely controlled.
traditional technologies is not the best solution, and More fundamental research and development of plasma
drastic changes in materials may be necessary. In the physics are needed to solve the listed problems. The key

-
past, materials changes have included, such as Al-gate- factors of plasma physics are plasma density, ion energy,
Si-gate, AI wiring +silicide(WSi2/MoSi2 etc.)-*W, and the issues in electric and magnetic fields, ion impinging
S i 0 2 Si3N4. These materials breakthrough have angle, radical density and so on. The important point is
uprooted the progress of the semiconductor industry. In
how to control these parameters by reactor and system
the future, such materials innovations will be more and
design.
more important.

$yg - 4
In the deep-sub micron regime, the main problem in
miniaturizing DRAMs is related to the capacitors. The
capacitance required for 256Kb- 1Mb DRAMs can be
4.1 Fine-Patterning Technology achieved with planar-type capacitor. For the 4Mb
As mentioned in Section I, the most important generation trench, STC, and fin-type capacitor cell have
technology for improving LSI performance is still fine been proposed as listed in Fig, 4. The 64Mb DRAMs will
patterning. Although photolithography has been used for require very complicated and sophisticated structures for
LSI production down to the 0.5 p m era, it is gradually the capacitor cells. All the proposed designs are three-
becoming difficult to keep resolution as the pattern size dimensional and the difficulty and number of process-
approaches the wavelength of the ultraviolet light source. steps are close to limit. The complexity of the cell
New technologies have been introduced every generation structure is due to the thin dielectric materials
to improve resolution, and the life of photolithography (SiOz/Si3N4) which must be very reliable while having a
has been repeatedly prolonged. For example, for 64Mb low dielectric constant ( E ).Breaking through the limit
DRAMs (0.3-0.4U , m), new technologies such as phase- definitely requires some new dielectric (high E )
shift mask and off-axis exposure proinise to keep fine materials for capacitor cells.
resolution, Another approach is a new light source, and The required capacitance of about 30fF for 256Mb
excimer lasers are considered to be most promising. DRAMs cannot be achieved using Ta205 for planar-like
There are three methods for raising the resolution of cell structures, and higher E materials such as SrTiO3
photo-lithography; shortening wavelength , will be necessary. Usually the e value of a thin film
increasing the numerical aperture (NA)of the lens, and material is lower than that of the bulk material, and some
improving process parameters as indicated Fig, 2 . For margin of the e value is needed for practical use.
lithography technology there is a trade-off between Despite the intense R&D of the high E materials for
resolution and depth of focus (DOF), which is a very DRAM capacitors, many problems still remain unsolved
important factor. Therefore, fine patterning technology for the film deposition process (CVD, sputtering), cell
strongly depends on the other process technologies such structure, stoichiometric control, and dielectric break-
as planarization. down, etc. Among these factors, break-down voltage (V)

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is critical because of the relation, E X V=constant. It does 4.4 Substrate Technology
not make siense to combine high E materials with a The quality of bulk silicon substrate has been improved
trench/fin :structure to solve cell complexity and cost in many ways such as flatness (LTV/TTV), periphery
problem. New dielectrics ( E >loo) will be needed for treatment, control of oxygen (carbon) content and defect
density. The higher device performance needs the use of
the 256Mb generation. SO1 substrates. SOS (silicon on sapphire) has not yet
attained practical use because of crystalline defects. It
needs greater effort to apply SO1 (Silicon on Insulator) to
4.3 Metalhation Technology the half- p m regime, in order to break through problems
Multi-layer metallization will be indispensable for such as LY -particle immunity and switching speed
system on-chip or high-speed design. Even now, 4-6 limit. Two methods proposed for making SO1 are
metal layers are used for high-speed bipolar LSI and SIMOX and a bonded wafer. Both methods can form thin
CMOS/ASICs. The problems in multi-layer metallization silicon layers less than 0.5 /* m thick. Both have
are advantages and disadvantages related to film thickness
- P1anarii:ation of the device (diffusion) layer and uniformity, warpage, and wafer cost. SIMOX substrates
metallization layer, suffer from heavy-metal contamination and crystalline
- Refilling via-holes and contact-holes having high defects.
aspect ratios, Although devices fabricated on SO1 substrates have
- New m1:tallization materials (migration-immunity, some problems with hot-carrier immunity, source/drain
easy-patterning, deposition process, adhesion properties), break-down voltage, and heat diffusion, device
Planalizatioin is required for a DOF margin in lithography performances have greatly improved;
process, a dry-etch margin of metal layers and reduced - reduced CY -particle noise
capacitance between the metal layers. The projected - improved switching speed (especially at low-voltage
future development for planarization is indicated operation),
schematically in Fig. 5. Device layers can be planarized - less process steps.
by (B) PSG reflow and inter-metal layers by SOG Besides SOI, high-energy ion implantation might be
film/CVD films with metal via-hole refilling. In this case, applied to conventional process technology to reduce the
the problem is step difference between the memory area cost of devices.
and logic area (absolute step-high) and also the space
between metal wiring lines.
In general, planarization is easier for narrow 4.5 Reduction of Process Cost
lines/spaces than for wide ones, so some dummy patterns One of the most serious problems for continuous growth
should be added for wide ones during the chip design. of semiconductor industries is cost. T o take DRAM as an
One advanced planarization technology that has been example, it is well known that the bit cost of DRAMS
proposed is CMP (Chemical-Mechanical Polishing). This (and SRAMs) has been reduced to 1/4 every generation,
method is very simple and is thought to be effective for known as the ;ry -rule, has shifted to bi-rule recently.
some device:<,but might be unsuitable for conventional There are many factors in costs, (1)chip area
semiconductor process lines. It is effective for ( X IA/generation), (2)process steps ( X I .3/generation.),
planarizing wide areas (global planarization) and refilling (3)equipment costlthroughput, (4)development cost
via-holes. It might also be effective for patterning some (x1.5/generation.), (5)yield, etc. So far, the increase in
metal layer such as Cu or Au which are difficult to dry- chip area has been compensated for by an increase in
etch. wafer diameter. The other factors are not dependent on
Metallization of high aspect-ratio via-holes and contact wafer diameter and must be recovered by other measures.
holes was achieved by CVD-W refill (selective The investment for process equipment has increased by
deposition or blanket/etching back) in the 0.5 p m age. 1.8-2 times every generation and is expected to be one
New methods such as Al-reflow and collimated billion dollars to produce two million 64Mb chips per
sputtering may improve step coverage. month excluding the clean rooms. (Fig. 6) The
The main problems with metallization materials are development of complex and large-scale chips takes a
related to the guaranteed electro/stress migration huge amount of human resources and facilities. Even one
immunity. Higher step coverage has been achieved using breakthrough requires investigating numerous
refractory metals (W/WSiz, MoSi2) which can be possibilities.
deposited by [CVD. Good electromigration immunity has Net probe yields have steadily declined since 1Mb
been achieved using TiW (TiN) or W/Al(Cu- DRAM generation, although gross yields have kept
Si)/TiW(TiN) or W multi-layered metallization for half- almost constant due to the use of redundancy circuits.
, m devices, but these metal wiring systems are not
U (Fig. 1) This is the warning that semiconductor process
inherently suitable for electromigration. The limit of technologies have entered danger zone. For the deep sub-
electromigraton immunity is estimated to be I x lo6 A/cr$ /U m generation to be possible the yield problem must be
so finer metal patterns will need Cu or Au, which are solved especially for logic devices. The two major causes
hard to pattern by dry etching. In this case, new of low yield are reduced process margin and
patterning technologies such as ion-milling or CMP may contamination including particles.
be necessary.
Measures devised to deal with above-mentioned five
In any case, higher integration increases the burden on
factors of rising costs are listed i n Table 2. Arnong these,
metallization technology, and it will become vital to
ultra-clean technology for better yield and cheaper
simplify the metallization processes to reduce the cost of
LSI chips. Basically, i t is very important to planarize process equipment must be reconsidered from scratch.
diffused layer:; and to process all the layers in the same Especially, reducing the particle contamination in process
equipment and controlling surface contamination directly
manner and sequentially in the same equipment.

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affect yield and should eventually lead to cheaper chips.
For process equipment, the development of single-wafer Table 1 Advanced Process Technologis
system is very important considering the trend towards
larger diameter wafers. For example, it is difficult for a
conventional batch-type LPCVD system to keep
uniformity of film thickness and quality for large
0.3-0.4p m
diameter wafers(2 8 in ). Also, the throughput of a Lithography -Excimarsource
single-wafer CVD system will be higher than that of a i-line+ #shift -New photo-resist
batch system for 28 in wafers. In addition, it is easier for 0.2 p m
p-wave
a single-wafer system to control parameters such as Dry Etching Magnetron
quality of interface and particle density which have Helicnn
strong influence on reliability, device performance and 0.3-0.4 p m
process yield. CapacitorCell STC, HSG High e dielectrics
Now, many equipment makers are developing and Trench, Fin
supplying multi-chamber deposition instruments as a
single-wafer system. In future, for cost-saving,
equipment suppliers should use standard parts,
mainframes and interfaces (both software and hardware).
-Epitaxy - SO1 (SIMOX, Bonded)
Cooperative development of advanced process equipment SubstrateTechnology - IC - Surface-roughness
between equipment suppliers and users is necessary to - High-energyI. 1. control
reduce costs and shorten the development period.
In any case, miniaturization will be expensive than - Cassette-less Cleaning .Continuoussinglewafer
Clean Technology operation
before so in the future, fine patterning, design-rich - Vapor phase cleaning (Clean Tunnel)
circuits or added value due to new materials (SOI, high
E dielectrics) and new process technologies will be
more effective than simple fine patterning. Step- by-step
miniaturization and redundancy circuits for logic LSI will
Junction Formation
Annealing I - Vapor-Phase doping

be needed.
As a result, many other important problems such as Table2 Cost Factors
reliability of scaled-down device, low temperature
processes, and shallow junction technology will be given Cost-uD Factor I Trend I Scheme
a priority.

Acknowledgments
The author wishes to express his thanks to Jun Sugiura,
Noburo Ohwada, Fumio Mizuno, Takahide Ikeda
(Device Development Center, Hitachi) and Shinji
Okazaki (CRL, Hitachi) and also members of Applied
Materials Japan, for helpful discussions.
'I
X1.2-1.3

gen
- Simple &via-s
-Ncwmatr&Is

Yield
(5)
Dccruse

" t
10
256k 1M 4M 16M 64M 256M
DRAM Generation (bit)
Fig. 1 YieldTrend

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 ~~

Density Cell Structure

Wavelength
Conventional Light Excimar Laser
06nm JMnm 2&m 193nm
g.line
+ i.linr- +KIP * ArF? -*. ?
256K

1
R= k i X- ~~~

NA Lens System
038 *035 * 0.40 *0.45 *OS0 *OS5 *0.60 ?
High NA 1M

DOF=kzx-
1
kl l k ~
I STC
Trench
Nd MaterialslProcess New Image FormationTechnologies

4M

............................................

..................................................................

I I ....
/ n .n.n ... ....
c ....... Fig. 4 Trend of DRAM Cell Structures

- Total *.*-

(Except
BuildiZ/'*'

High Reliable Metallization

Refractory Metal
Via Fill
High Reliable Interlayer
-
h /Final Protection Fine Patteming
P-SiNIOs-TEOS
Metallization (2)
TiW/AICuSiiW
Via Fill
CVD-W
Interlayer (2)
P-TEOS
IO-SOG(E.B)
IP-TEOS
16K 64K 256K IM 4M 16M 64M 256M
Metallization (1) DRAM Generation (bits)
CVD-WISpW
Fig.6 Investment Trend
I \ ~ n t e r ~ a y e r (1)
BPSGReflow

Fig. 5 PlanalizationTechnology
5

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