An Efficient Wireless Noc With Congestion-Aware Routing For Multicore Chips

An Efficient Wireless NoC with
Congestion-Aware Routing for multicore chips

Course Project Report
Submitted by
Himanshu Patel
15CS09F
National Institute of Technology, Karnataka

NOV 2015
I. A BSTRACT
Network-on-chip (NoC)
systems are becoming more
popular due to their big
advantages when compare
with systems-on-chip (SoC).
Therefore, an increasing
number of researchers and
organizations now focus on
the study and development
of NoC techniques. As a
result, so far many achievements have been gained.
Furthermore, considering the
dominant position of wireless
and the weakness of wired
communication, people also
turn to try to insert wireless
links in NoC systems in
order to solve the multi-hop
problem.This report gives a
brief description of some
outstanding developments of
NoC and WNoC (Wireless
NoC) systems, including some
important technique and the
achieved re-sults.
II. I NTRODUCTION
High-Performance Computing
(HPC)
and
multimedia-oriented applications and services demand
increasing computing power
to the systems supporting
them. Moreover, achieving
this performance with minimum power consumption has
become almost mandatory
due to cost and power constraints. In order to satisfy
both requirements, manufacturers benefit from the
advances in integration-scale
technology, and include as
many computing modules
as possible into the same
die. This leads to the design of chip multiprocessors
(CMPs) or multiprocessor
systems-on-chip. Regardless
the specific design, these
platforms require an interconnection network to support
communication between all
the processing nodes. In
general, this network must
provide high-bandwidth and

low-latency to avoid slowing
down the processing nodes
while waiting for remote
data. In that sense, Networkson-chip (NoCs)[1] are well
suited to systems with a
high number of processing
nodes. Network on chip
(NoC) is a communication
subsystem on an integrated
circuit, typically between
intellectual property (IP)
cores in a system on a chip
(SoC). NoCs can span synchronous and asynchronous
clock domains or use unclocked asynchronous logic.
Despite their advantages,
an important performance
limitation in traditional NoCs
arises from planar metal
interconnect-based multihop
links with high latency and
power consumption.
III. P OWER A NALYSIS
Techniques for power efficient computer systems can
be broadly categorized into
two types: Offline power
analysis and dynamic power
management techniques. Offline power analysis techniques are based on analytical energy models that
are incorporated into existing
performance-oriented simulators to obtain power and
performance information and
help system architects select the best system parameters during design time.
Dynamic power management
(DPM) schemes monitor system workload and adapt the
systems behavior to save energy. These techniques are
dynamic, run-time schemes
operating at different levels of
a computer system. They include Dynamic Voltage Scaling (DVS) schemes that adjust the supply voltage and
operating frequency of a processor to save power when it
is idle.
IV. P OWER A NALYSIS AND

O PTIMIZATION U SING
E NERGY M ODELS
Power optimization, just as
with performance, requires
careful design at several levels of the system architecture.
The first step toward optimizing power consumption is to
understand the sources of energy consumption at different
levels. Various energy models
have been developed and integrated with existing simulators or measurement tools to
provide accurate power estimation, which can be used to
optimize the system design.
There are three types of
models1. CPU Level Energy Models
2. Complete System Level
Energy Models
3. Interconnect Level Energy Models in Parallel Systems
A. CPU-Level Energy Models

Power consumed by the
CPU is a major part of
the total power consumption
of a computer system and
thus has been the main target of power consumption
analysis. Several power models have been developed and
integrated into existing performance simulators in order to investigate power consumption of CPU either on
a functional unit basis or
processor as a whole. two
abstraction levels; cycle-level
(or register-transfer level) and
instruction-level as described
in the following two subsections, respectively.
1) Cycle-Level CPU Energy Model: Energy consumption of a processor can
be estimated by using cyclelevel architecture simulators.
This is done by identifying the active (or busy) micro architecture level units or
blocks during every execution
cycle of the simulated processor. These cycle-by-cycle
resource usage statistics can
then be used to estimate the
power consumption.
2) Instruction-Level CPU
Energy Model: In cyclelevel techniques, coarse-grain
instruction-level power analysis techniques estimate the
total energy cost of a program by adding the energy
consumed while executing instructions of a program. Instruction by instruction energy costs, called base costs,
can be measured for individual instructions for a target processor. The base costs
of individual instructions and
the power cost of interinstruction effects are determined based on the experimental procedure using a program containing several instances of the targeted instruction (for base cost measurement) and an alternating sequence of instructions
(for inter-instruction effects
costs). Once the instructionby-instruction energy model
is constructed for a particular processor, the total energy
cost, Ep, of any given program, P, is given by:
Ep = L(Base; * N;) +
L(Inter;,j * N;,j) + L Ek
where Base; is the base
cost of instruction i and
N; is the number of executions of instruction i. Inter;,j
is the inter-instruction power
overhead when instruction i
is followed by instruction j,
and N;,j is the number of
times the (i, j) pair is executed. Finally, Ek is the
energy contribution of other
inter-instruction effects due
to pipeline stalls and cache
misses.
B. Complete
System-Level
Energy Models
There is little benefit in
studying and optimizing only
the CPU core if other components have significant effect
on or even dominate the energy consumption. Therefore,
it is necessary to consider
other critical components to
reduce the overall system energy. Above section discusses
the hardware state-level models, where the total energy
consumption of the entire
system is estimated based on
the state each device is in or
transitioning to/from. Here, it
is assumed that each device
is capable of switching into
one of several power-saving
states, such as sleep state, depending on the demand on
that particular device. This
capability is usually provided
in portable systems to extend
their lifetimes as longer as
possible. Software-based approaches presented in Section identify energy hotspots
in applications and operating system procedures and
thus allow software programmers to remove bottlenecks
or modify the software to be
energy-aware.
C. Interconnect -Level Energy Models in Parallel Systems
With the ever-increasing
demand for computing power,
processors are becoming
more and more interconnected to create large clusters
of computers communicating
through interconnection networks. Wang et al. showed
that the power consumption
of these communication components is becoming more
critical, especially with increase in network bandwidth
and capacity to the gigabit
and terabit domains. Thus,
power analysis in this area
usually targets the building
blocks inside a network

router and a switch fabric.
Bit energy model considers
the energy consumed for
each bit, moving inside the
switch fabric from the input
to the output ports, as the
summation of the bit energy
consumed on each of the
following three components:
(i) the internal node
switches that direct a packet
from one intermediate stage
to the next until it reaches the
destination port
(ii) the internal buffer
queues that store packets
with lower priorities when
contention occurs; and
(iii) the interconnect wires
that dissipate power when the
bit transmitted on the wire
flips polarity from the previous bit.
V. DYNAMIC P OWER
M ANAGEMENT (DPM)
T ECHNIQUES
While the simulation and
measurement techniques described in Section 3 aim to
optimize power performance
at design time, DPM techniques target energy consumption reduction at runtime by selectively turning
off or slowing down components when the systems is
idle or serving light workloads. For example, Dynamic
Voltage Scaling (DVS) technique operates at the CPUlevel and changes processors
supply voltage and operating frequency at run-time as
a method of power management. A similar technique,
called Dynamic Link Shutdown (DLS), operates at the
interconnect-level and puts
communication switches in a
cluster system into a lowpower mode to save energy.
DPM techniques can also be
used for shutting down idle
I/O devices, or even nodes of
server clusters.
This section discusses

DPM techniques that are
classified based on the implementation level.
1. DPM techniques applied
at the CPU-level.
2. System level DPM approaches
3. DPM techniques proposed for parallel systems
A. CPU-Level DPM
The intuition behind power
saving at the CPU-level
comes from the basic energy
consumption characteristics
of digital static CMOS circuits, which is given by
E = k * Ceff * V * V *f
where Ceff is the effective
switching capacitance of the
operation, V is the supply
voltage, and f is the clock frequency and k is constant. The
DPM techniques presented in
this section reduce the power
consumption by targeting one
or more of these parameters.
Below we discuss techniques
to reduce the switching activity of the processor, mainly at
the datapath and buses.
1. Reducing Switching Activity
2. Clock Gating
3. Dynamic Voltage Scaling (DVS)
B. Hardware Device-Based
DPM Policies
As discussed before, the
CPU does not dominate the
power consumption of the
entire system. Other system
components, such as disk
drives and displays, have
a much larger contribution.
Therefore, it is necessary to
consider all of the critical
components of the system

to effectively optimize power.
A well-known system-level
power management technique
is shutting down hard drives
and displays when they are
idle. A similar idea can also
be applied to other I/O devices to save energy. However, changing power states
of hardware components incurs not only time delay but
also energy overhead. Consequently, a device should be
put to sleep only if the energy saved justifies the overhead. Thus, the main challenge in successfully applying this technique is to know
when to shut down the devices and to wake them up.
A straightforward method is
to have individual devices
make such decisions by monitoring their own utilization.
One clear advantage of this
device-based scheme is transparency, i.e., energy saving
is achieved without involving or changing application
or system software. On the
contrary, this scheme may
perform poorly because it
is unaware of the tasks requesting the service of the
device. Software-based DPM
techniques have been proposed to alleviate this problem. Application or system
software takes full responsibility on power-related decisions assuming that devices
can operate in several low
power modes using control
interfaces such as Advanced
Configuration and Power Interface (ACPl).
VI. C OMPARISON TABLE
VII. C ONCLUSION
VIII. R EFERENCES

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An Efficient Wireless NoC with

Congestion-Aware Routing for multicore chips

National Institute of Technology, Karnataka

provide high-bandwidth and

IV. P OWER A NALYSIS AND

A. CPU-Level Energy Models

blocks inside a network

This section discusses

components of the system

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