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Part I
ANALOG ELECTRONICS
Chapter -1: Diodes and Applications
The term diode is used to represent a device or element which has two elecrodes.
These divices are characterized by the fact that they allow electric current to flow in one
direction, and block flow of current in the opposite direction. This unilateral behaviour is
predominantly used in swithching and rectification. Diode is in fact, the very first electronic
device invented. Initially, for several years vacuum tube version was in use, and were bulky
in size, required higher power for operation, and were slow. Today, we have semiconductor
diodes, which are very small in size, requires relatively low power and operates at higher
speeds. Semiconductor diodes are available in various forms and are used in wide variety of
applications. In this unit, we shall look at the operating behavior and charecteristics of
semiconductor diodes along with their typical applications such as rectifiers, voltage
regulators and some special purpouse applications.
Module 1 : Diodes
Learning Outcomes:
At the end of this module, students will be able to:
1. Explain the operation of PN junction diode under different biasing conditions.
2. Plot the I-V characteristics of the diode.
3. Define static and dynamic resistance of the diode.
4. Explain the breakdown phenomenon observed in diodes.
5. Describe the working of Zener diode and plot its I-V characteristics.
6. Explain the operation of diode as a capacitor.
1.1.1 Introduction
Materials are broadly classified as metals, insulators and semiconductors. A
semiconductor like Germanium or Silicon has electrical conductivity lying between
conductor and insulator. Semiconductors are the basic materials used in modern electronics.
For example, Diodes, Transistors, Solar cells, Light-emitting diodes (LEDs), and integrated
circuits.
Self Reading:
1.
2.
3.
4.
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cause the electrons to move from N-type material to the P-type material and holes to move
from N-type material to the P-type material. This process of movement of charge carriers
form the region of higher concentration to a lower concentration in the absence of external
electric field is called diffusion. Diffusion of charge carriers across the junction will continue
until the equilibrium condition is established. Also at the junction, N-type material will have
positively charged immobile ions and P-type material have negatively charged immobile
ions. Thus the regions on either sides of pn interface lose their charge neutrality and become
charged. For this reason it is caleld space charge region. As the region is devoid or depleted
of mobile charge carriers it is also called depletion region and is as shown in Figure. 1.1.1.
N
Figure 1.1.1. Schematic of PN junction
The space charge on either sides of the junction causes a potential difference accross
the P-N junction and it is called the barrier potential. This is the minimum amount of voltage
required to initiate flow of charge carriers across the junction. Doped germanium has a
barrier potential of about 0.3 volts where as, doped silicon has a barrier voltage of about 0.7
volts.
1.1.3 P-N junction under bias
Application of external voltage across the diode is called biasing. Depending upon
the polarity and magnitude of voltage applied, we can have three biasing conditions, as listed
below.
a) No bias or Zero bias
b) Forward bias
c) Reverse bias
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a) Zero Bias: In the absence of any bias voltage, the net flow of charge carriers in any
one direction for a semiconductor diode is zero. This occurs because minority
carriers (holes) in the N-type material will encounter barrier in the depletion region
to cross the junction and move to the P-type region. Same is the case for electrons
in P-type material. This results in depletion region with high impedance, and hence
no current flows through the diode. The built-in potential varies from 0.3 to 0.7 eV
depending upon the type of semiconductor material. A diode operated without any
biasing is shown in Figure 1.1.3.
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Self test:
1. The arrow direction in the diode symbol indicates
a. Direction of electron flow.
b. Direction of hole flow (Direction of conventional current)
c. Opposite to the direction of hole flow
d. None of the above
2. When the diode is forward biased, it is equivalent to
a. An OFF switch
b. An On switch
c. A high resistance
d. None of the above
3. The barrier potential voltage of Si diode is
a. 0.2 V
b. 0.7 V
c. 0.8 V
d. 1.0 V
4. What are the conditions under which a p-n junction diode can be destroyed ?
a. Overheating
b. A large reverse voltage
c. High forward current
d. All the above
1.1.4 I-V characteristics of diode
I-V characteristics of practical diode is shown in Figure 1.1.6. When the forward
biased voltage is applied to diode, current is initially zero and then increases sharply after
crossing the cut-in voltage.In this case,the diode behaves like a closed switch. Similarly, in
reversed biased condition, the diode behaves like an open switch and very small current flows
due to minority charge carriers, which is known as reverse saturation current. In the reverse
biased condition, beyond a particular reverse voltage, a sudden rise of current will be
observed and this voltage is called breakdown voltage.
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Figure 1.1.7. I-V characteristics of P-N junction diode under forward biased condition.
[http://www.electronics-tutorials.ws/diode/diode_3.html]
b) Reverse biased Characteristic:
In this case, PN junction offers high resistance value and practically zero current
flows through the junction diode with an increase in bias voltage. However, a very
small leakage current flows through the junction which is in the order of
microamperes (A ) for ordinary rectifier diodes.
Figure. 1.1.8. I-V characteristics of P-N junction diode under reversed biased condition.
[ http://www.electronics-tutorials.ws/diode/diode_3.html]
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If the reverse bias voltage VR applied to the diode is increased beyond certain limits
there will a large current due to avalanche effect and cause breakdown. This is shown
in figure 1.1.8.
c) The Diode Current:
The current flowing through the diode is given by the following equation.
VD
I D I 0 eVT 1
(1.1.1)
I D I0 (e
VD
VT
(1.1.2)
I D I0
(1.1.3)
(1.1.4)
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Exercise Problem 1:
1. Sketch I versus V to scale for each of the circuits shown below. Assume that the
diodes are ideal and allow V to range from -10 V to +10 V.
+
v
_
2k
i (mA)
4
3
2
1
0
-10
-5
10
v (V)
2. Sketch I versus V to scale for each of the circuits shown below. Assume that the
diodes are ideal and allow V to range from -10 V to +10 V.
Solution: Diode B is ON for v > 0 and R=1k. Diode A is on for v < 0 and R=2k.
10
i (mA)
-5
-10
-5
10
v (V)
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 12
The dynamic resistance of the diode is found using the following equation:
rd
Vd
1
slope I d
(1.1.6)
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Also, dynamic resistance is found by the derivative of the diode equation; where:
V
I D I s exp D
VT
1 ,
dI D
d V D
I s exp
dV D
dV D VT
VT
dV D
dI D
ID Is
(1.1.7)
I s
V
1
exp
V
T
VT
(1.1.8)
(1.1.9)
dV D VT
dI D
ID
(1.1.10)
rd
For Ge , =1 ; VT
T
11600
(1.1.11)
dV D
300
dI D 11600 xI D
(1.1.12)
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The simplified diode model ignores the effect of diode resistance in comparison with values
of other elements of the circuit. The voltage drop across the diode is zero.
A practical diode does offer some resistance to current flow when forward biased. Since there
is some resistance (built-in potential) , there will be some power dissipated when current
flows through a forward biased diode. Therefore, there is a practical limit to the amount of
current a diode can conduct without damage. A reverse biased diode has very high resistance
and excessive reverse bias can cause the diode to damage.
1.1.7 Equivalent circuit of diode:
Diode is often replaced by its equivalent circuit during circuit analysis and design. For
DC diode model, characteristics of an ideal diode and the modifications that were required
due to practical considerations has been considered for following cases:
(i) Ideal Diode
(ii) Second approximation of diode
(iii) Practical diode
(i) For an Ideal diode V = 0, RR = and RF = 0 as shown in Figure 1.1.14. In other words,
the ideal diode is a short in the forward bias region and an open in the reverse bias region.
A
RF = 0
A
Forward bias
RR =
A
K
V = 0
Figure 1.1.14 Equivalent circuit of Ideal diode. Reverse bias
(ii) In second approximation: V 0, RR = and RF = 0 as shown in Figure 1.1.11.
A
RF = 0
A
RR =
Forward bias
Reverse bias
V
V
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Exercise Problem 1:
1. A Silicon diode has a saturation current of 1pA at 200C. Determine (a) Diode bias
voltage when diode current is 3mA (b) Diode bias current when the temperature changes
to 1000C, for the same bias voltage.
Ans. Given: The diode current ID=3mA,
Reverse saturation current I0=1x10-12 A, Temperature T=20C = 273+20 = 293K
The diode is silicon =2
The equation for the diode current ID is given by
VD
T
293
I D I 0 eVT 1 and VT
25.25 mV
11600
11600
(a) The diode
bias voltage
I
VD VT ln 1 D 1.103V
I0
32.15 mV
11600 11600
The temperature is raised to 100C
(So the reverse saturation current I0 changes)
I 02 I 01 2
T2 T1 /10
I D 256 x10
1001020
256 pA
10 2
12
12
1.103
( 2 x 32.15 x10 3 1)
7.21 mA
2. Find the static and dynamic resistance of a P-N junction germanium diode if
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 16
the temperature is 27C and I0=1A for an applied forward bias of 0.2V.
Solution:
Given: Applied forward voltage= 0.2 V.
Reverse saturation current I0=1x10-6 A.
Temperature T=27C = 273+27 = 300K.
The diode is Ge, =1.
T
300
VT
25.86 mV
11600 11600
0.2
I D 1x10 e
2.28 mA
V
0.087 K
I
VT
1x25.86 x10 3
Dynamic resistance
11.33
I D I 0 2.28 x10 3 1x10 6
.
Static Resistance:
Solution: From the graph, find corresponding voltage for the mentioned current values.
(a)
RD= VD/ID= 0.5V/2mA= 250 .
(b)
RD= VD/ID= 0.8V/20mA= 40 .
(c)
At VD= -10V, ID= -Is= -1A (from the curve) and
RD= VD/ID= 10V/1A= 40
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remains constant. This behavior of Zener diode is used to provide a constant reference
voltage such as in the case of voltage regulation.
V
+
RR
RF
P
+
VZ
RZ
P
(a)
(b)
(c)
(d)
Figure. 1.1.17 (a) Zener diode symbol (b) equivalent circuit in forward biased condition
(c) equivalent circuit in reversed biased condition (d) equivalent circuit in breakdown
condition
1.1.10 Diode as a capacitor
Varactor diode is a special purpose diode that acts as a capacitor and always operates
in reverse-bias. It is doped to maximize the inherent capacitance of the depletion region. The
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depletion region acts as a capacitor dielectric because of its nonconductive characteristic. The
p and n regions are conductive and acts as the capacitor plates, as shown in Figure 1.1.18.
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Exercise Problems:
1. In each diode circuit shown below, find whether the diodes are forward or reverse
biased.
2. Determine the state of diode for the circuit shown below and find ID and
VD. Assume practical model for the diode.
3. Calculate the dynamic forward and reverse resistance of a PN junction diode, when
the applied voltage is 0.25V for Germanium Diode. I0 = lA and T = 300 K.
(Ans: rf=1.734; rr=390M)
4. A germanium diode has reverse saturation current of 0.19A. Assuming =1, find
the current in the diode when it is forward biased with 0.3 V at 27oC.
(Ans: 19.5mA)
5. The forward current in a Si diode is 15 mA at 27oC. If reverse saturation current is
0.24nA, what is the forward bias voltage?
(Ans: 0.93V)
6. A germanium diode carries a current of 10mA when it is forward biased with 0.2V
at 27oC. (a) Find reverse saturation current. (b) Find the bias voltage required to get a
current of 100mA.
(Ans: 4.42A, 0.259V)
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1.2.1. Introduction
Today, we cannot imagine life without electronic products like cell phones, computers,
laptops, music systems etc., in our daily lives. Some of these electronic systems work on a
constant DC voltage derived from the AC mains, while others use internal batteries, which
requires regular charging. In any case, some device which at one end receives AC voltage,
which is 230V sinusoidal signal of 50Hz as input and produces a constant DC voltage at its
output is required. This module aims at providing an insight into some of the basic circuits
which converts AC mains in to a constant DC voltage. Such circuits or devices are called
regulated power supplies.
A signal obtained from main AC power supply is purely sinusoidal that can be defined in
terms of Peak amplitude and Frequency.
Peak amplitude: The maximum amplitude of an alternating signal on either sides
measured from its zero value.
Frequency: Number of cycles that passes a given point per second. It is equal to
reciprocal of time taken to complete one full cycle.
It is mathematically expressed as V (t ) A sin(t ) and plotted as shown in Figure 1.2.1,
where Peak amplitude A= 230 2 V, = 2f radians/sec, frequency(f) =50Hz = 1/20ms.
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V (t )
1
V (t ) d (t )
Time Period 0
1
2
V (t ) d ( wt)
0
(1.2.1)
T 2
1
V (t ) d ( t )
Time Period 0
V (t )
or Vrms
V 2 (t ) d (t )
2 0
(1.2.2)
Note 1 : A pure sinusoidal signal has an average value equal to zero. It means the dc
value of this signal is zero.
1.2.2. Basic Block Diagram of DC power supply
The DC power supply converts the AC sinusoidal signal to a DC signal. The block diagram
of a basic DC power supply unit is as shown in Figure 1.2.2.
A DC regulated power supply unit consists of the following key components.
a) Step down transformer
b) Rectifier circuits
c) Filter circuit
d) Regulator
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Rectifier
circuit
Filter
circuits
DC signal
across load
Regulator
LOAD
Input AC
mains
Step down
Transformer
(a)
(b)
Figure 1.2.3: (a) Transformer core with primary and secondary windings (b)
circuit representation of a step down transformer.
A step down transformer converts a high voltage low current power to a low voltage high
current power. A step down transformer has large number of turns in primary coil compared
to the number of turns in the secondary coil. Hence in this case the secondary voltage is less
than the primary voltage and equivalently there is rise in secondary current. The ratio of
primary voltage to secondary voltage is proportional to the ratio of number of turns in the
primary to the number of turns in the secondary. The 155V AC mains applied at the primary
of a step down transformer is stepped down by ten times at the secondary as shown in Figure
1.2.4.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 25
(a)
(b)
Figure 1.2.4: (a) Primary voltage waveform with peak amplitude of 220V
(b) Stepped down version is available at the secondary with peak amplitude of 22V
Transformer used in the DC power supply units plays two important roles. First role is, as
discussed earlier, it steps down AC voltage to a suitable value and secondly it provides
electrical isolation to the low voltage low power components on the other side of the
transformer. The second equally important role is to provide electrical isolation to the low
voltage low power components on the other side of the transformer. This also provides some
amount of safety to the equipments using such DC supplies.
Note 2: The frequency of the primary voltage is equal to the frequency of the secondary
voltage.
b) Rectifier circuit:
A rectifier circuit is the heart of a DC power supply. It converts an AC sinusoidal signal that
is bidirectional (with both positive and negative amplitudes) into a signal which is
unidirectional (either only positive or only negative). Thus rectifier circuit forces the current
through the load to flow in only one direction. The rectified output is ussually a pulsating DC
voltage. Thus in general the process of converting an AC signal into pulsating DC signal is
called rectification and the circuit is called rectifier. Rectification is commonly performed
using semiconductor diodes because of its inherent unidirectional conduction property.
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The rectified output voltage with respect to the input voltage using a single diode is as shown
in Figure 1.2.5. The rectifier passes positive half cycle to the output and blocks the negative
half cycle. In the case of a full wave rectifier both half cycles will be rectified and availabe as
unidirectional puses at the output.
Note 3: The AC component of a rectified output signal is not equal to zero. That is the
rectified pulsating DC signal has both DC and AC components.
c) Filter circuit:
The pulsating DC signal is not suitable for appliances that require pure DC voltage. Filters
can be used to minimize (smooth out) the pulsations or eliminate the AC content from the
rectified signal to achieve approximately constant valued (or a DC) signal. A filter contains a
capacitor, an energy storing component that can hold the voltage to the peak value of the
rectified pulsating DC and then dissipate energy to load when the pulsating DC drops as
shown in Figure 1.2.6. Essentially, the filter minimises the ac component present at the
output of the rectifier. This increases the DC value at the output.
Note 4: The output of filter circuit is a DC signal with small AC component called ripples
d) Regulator
Regulation is defined as the ability of a system to provide near constant supply over a wide
range of load and power line fluctuating conditions. A circuit that can provide constant DC
voltage despite of variations in the mains AC power supply or load variations is called
voltage regulator.
Self test:
1. List out the appliances or electronic products used in daily life which require
DC power supply for their operation. Mention the DC values recemoneded for
their operation.
2. List and classify the appliances or electronic products which use DC and AC
power supply.
3. Explain the block diagram of a DC power supply.
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During the positive half cycle of the input waveform, voltage at node A is positive with
respect to voltage at node B, which forces the diode to be forward biased and acts as a short.
The equivalent circuit for the positive half cycle is as shown in Figure 1.2.8.This results in
current flow through the load resistance RL. Hence output voltage is approximately equal to
the secondary voltage.
Similarly during the negative half cycle, the voltage at node A is negative with respect to
node B that forces the diode to be reverse biased and acts as open circuit. The equivalent
circuit is as shown in Figure 1.2.9. This results in no current flow through the load.
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Thus the diode conducts only during positive half cycle and hence the circuit is referred as
Half Wave Rectifier. The rectified voltage is pulsating DC, which can be smoothened using
filter circuits.
Analysis of a HWR circuit
Filter performance is measured using certain standard parameters. Few of them will be
defined and analyzed for each of the filter circuits.
A. Dc voltage Vdc : The average value of the output voltage measured across the load
resistor.
B. Ripple Factor: Ripple factor is defined as the ratio of rms value of AC component to
DC component of the signal.
Vr
(1.2.3)
rms
Vdc
where Vrrms is the rms value of the ripple (AC component in the pulsating DC) and is given
by
2
Vrrms Vrms
Vdc2
(1.2.4)
Ripple factor actually measures the amount of AC content present as compared to the DC (or
average) content in the pulsating dc.
Using 1.2.3 in 1.2.4, we can write
2
Vrms
1
Vdc2
(1.2.5)
ac input power
Pac
Efficiency signifies the outcome of the rectifier circuit to output DC power in comparison to
AC input power. Thus
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V2
dc
RL
2
Vrms
RL
(1.2.6)
D. Peak Inverse Voltage (PIV): It is defined as the peak value of input voltage across the
reverse biased diode before the diode breaks down. It is essential that the diode used in
rectifier circuit should be able to withstand the voltage available across it when it is
reversed biased so that it acts as open circuit and does not enter into a breakdown state.
Computation of DC Voltage and current for HWR
Consider input signal VS Vm Sin ( t ) as the secondary voltage signal applied to the half
wave rectifier. Then Vav the average or the DC component of the voltage across the load is
can be computed using equation (1.2.1).
2
1
Vav Vdc
Vm sin (t ) d (t ) 0 d (t )
Vm
cos (t )0 Vm
2
V
V
I
dc m m
RL RL
Vdc
(1.2.7)
I dc
(1.2.8)
1
2
(Vm Sin t ) 2 d (t )
Vm2 1 cos 2 t
V
(
) d (t ) m
2 0
2
2
Using 1.2.10, and 1.2.7 in 1.2.5, the ripple factor is
Vrms
Vm
2
Vm
(1.2.9)
(1.2.10)
2
1 1.21
1
4
(1.2.11)
Vdc2
R
2 L
Vrms
RL
Vm
4 0.406 or 40.6%
2
2
Vm
2
(1.2.12)
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(b) 15V
(c) 30V
2. The average value of the half wave rectified voltage is _____% of the peak value.
(a) 63.66
(b) 31.8
(c) 3
(d) 81.2
Solved Example
1.
RMS secondary voltage of 7.07V is applied to half wave rectifier.
resistance is 800. calculate average load current.
If the load
V
I dc dc
RL
1.2.4
3.978mA
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The circuit of full wave rectifier is shown in Figure 1.2.11 with the center tap of transformer
grounded. The center tapped transformer consists of two input terminals (nodes) and three
output nodes. The extreme nodes are labelled as node A and node B. The center node is
usually used as a common reference voltage terminal relative to which all the voltages are
measured. Hence the center output node of center tapped transformer is considered to be a
common ground.
The secondary voltage observed between the extreme end nodes i.e. between node A and
node B is a stepped down voltage as shown in Figure 1.2.12(a). The voltages measured at
between node A and center node (ground) or node B and center node is half in magnitude in
comparison to the voltage measured between node A and node B. Also voltage at node A is
180 out of phase with the voltage at node B when measured relative to the center node
(ground). All these secondary waveforms are shown in Figure 1.2.12(b) and (c).
Working of Center tapped Full wave rectifier circuit
During the first half cycle, as shown in Figure 1.2.11, the voltage at node A is positive and
voltage at node B is negative measured with respect to ground. Diode D1 gets forward biased
and acts as a short whereas diode D2 is reverse biased and acts as open. Load resistor is
connected at the junction of cathodes of the two diodes D1 and D2 with respect to ground.
Considering ideal diodes, the equivalent circuit of a center tapped full wave rectifier for half
cycle when voltage at node A with respect to node B is positive is as shown in Figure 1.2.13
This results in a current flow through upper half secondary windings of transformer, diode
D1 and the load RL as shown in Figure 1.2.13. Direction of the current through the load is
towards the ground from node C. Hence the output voltage measured at node C with respect
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with respect to node B is negative is as shown in Figure 1.2.14. This results in a current flow
through lower half secondary windings of transformer, diode D2 and the load RL as shown in
Figure 1.2.14. Again note that the direction of the current through the load is towards the
ground from node C. Hence the output voltage measured at node C with respect to ground is
equal to voltage at node B measured with respect to ground.
The output waveform observed across load resistor along with voltage waveforms at node A
and node B with respect to ground is shown in Figure 1.2.15.
(1.2.13)
V av Vdc Vm sin (t ) d (t ) m cos (t )0 m
0
V
2V
2I
(1.2.14)
I dc dc m m
RL RL
Vrms
(Vm sin t ) 2 d (t )
Vm
2
and I rms
Im
2
(1.2.15)
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Vm
2 1 1 0.483
8
2Vm
Vdc2
R
2 L
Vrms
RL
(1.2.16)
2Vm
2 0.812 or 81.2%
2
Vm
(1.2.17)
Solved Example:
1. For the FWR using center tapped transformer, the primary voltage is 140sin314t volts
and the turns ratio is 10:1. Plot the waveform across each half secondary windings
and across the load resistance RL.
Self-test :
1. The average value of the signal shown in figure 1.2.15(c) is
(a) 23/2
b) 23/2
c) 23/
d) 46/
2. Choose the correct answer: (T is the time period of the input signal)
(i) In center tapped FWR, each diode is forward biased for what duration of the time
period?
(a) T/2
b) T/4
c) 3T/4
d) T
(ii)In center tapped FWR, current through the load flows for what duration of the time
period?
(a) T/2
b) T/4
c) 3T/4
d) T
3. Input AC signal of 25V peak value is to be rectifed using center tapped FWR. For
proper working it is essential to choose the diodes whose PIV rating is
(a) 5V
(b) 15V
(c) 30V
(d) both a and b
1.2.5
The bridge rectifier consists of four diodes in the form of a bridge. two parallel paths can be
represented with each path having two diodes and all diodes are directed in the same
direction as shown in Figure 1.2.16. The top path consists of diodes D3 and D1 whereas
bottom path consists of diodes D2 and D4 respectively. Load resistor is connected between
the ends of two parallel paths (i.e. node C and ground).
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During positve half cycle, node A is positive with respect to B, D1 and D2 are forward biased
whereas D3 and D4 are reverse biased as shown in Figure 1.2.18. This results in current flow
taking a closed path from node A, through D1, R-Load and D2 and from node B through the
secondary coil as indicated in Figure 1.2.18. Note that current through the load resistor flows
from node C to ground.
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During negative half cycle, node B is positive with respect to A, D3 and D4 are forward
biased whereas D1 and D2 are reverse biased as shown in Figure 1.2.19. This results in
current flow taking a closed path from node B, through D4, R-Load and D3 and from node A
through the secondary coil as indicated in Figure 1.2.19. Note that again current through the
load resistor flows from node C to ground. Thus output voltage is unidirectional for both the
half cycles.
Analysis of Bridge FWR circuit
Consider Figures 1.2.18 and 1.2.19, maximum voltage across the reverse biased diode will be
secondary peak voltage. Hence PIV rating of the diode should be greater than Vm. The Idc, Vdc,
Irms, Vrms, Ripple factor, Efficiency are same as center tapped full wave rectifier.
Self-test :
1. The average value of the full wave rectified voltage is _____% of the peak value of
secondary voltage measured at one end w.r.t. center node.
(a) 63.66
(b) 31.8
(c) 3
(d) 81.2
2. In Bridge rectifier, each diode is forward biased for what duration of the time period?
(a) T/2
b) T/4
c) 3T/4
d) T
3. In Bridge rectifier, current through the load flows for what duration of the time period?
(a) T/2
b) T/4
c) 3T/4
d) T
4. Input AC signal with 14.14V rms voltage is applied to a bridge FWR. What is the required
PIV rating of the diodes for proper working of the FWR.
(a) 5V
(b) 15V
(c) 20V
(d) both a and b
Page 36
Solved Example
2.
Find the PIV rating of the diode used for proper working of the bridge rectifier when it
is supplied with 230V, 50 Hz AC mains through a step down transformer with turns ratio
equal to 10.
Given: Input AC mains peak voltage =230V, turns ratio=10,
Solution: Secondary peak voltage Vm =230/10=23V
therefore PIV rating of diode >= Vm=23V
1.2.6
Comparison of Rectifiers
Advantages of HWR over FWR
Simple circuit
Single diode
PIV rating is V
m
Disadvantages of HWR
High ripple factor
Low efficiency
Advantages of Center tapped FWR rectifier over HWR
High Efficiency
Low ripple factor
Advantages of bridge rectifier over to centre-tap full wave rectifier:
PIV rating is Vm
Centre-tap transformer is not required
Disadvantage of bridge rectifier over to centre-tap full wave rectifier:
Need for four diodes
Comparison of rectifier circuits based on the performance parametrs is listed in Table 1.2.1,
considering the input signal Vi (t ) Vm sin(2 fi t )
Table 1.2.1: Comparison of Rectifiers
Parameters of
rectified signal
HWR
Center-tapped FWR
Bridge FWR
Vm
2Vm
2Vm
Vm
2
Vm
2
Vm
2
PIV
Vm
2Vm
Vm
Ripple factor
1.21
0.483
0.483
Efficiency
40.6%
81.2%
81.2%
Frequency fo
fi
2 fi
2 fi
Vdc
VRMS
Page 37
1.2.7
Rectifier with Filter
A capacitor filter with HWR and FWR is as shown Figure 1.2.20. The capacitor allows AC
component and blocks DC component. The capacitor filter minimizes the ripple and
increases the average value of output voltage.
In each of the positive half cycle, the capacitor charges up to the peak value of the
transformer secondary voltage, Vin. Capacitor tries to maintain this maximum value when
the input drops to zero. The capacitor will discharge through the load resistance slowly until
the input voltage again increases to a value greater than the capacitor voltage. The filtered
output waveform for both HWR and FWR is as shown in figure 1.2.21.
Figure 1.2.20: Filter circuit for (a) half wave rectifier and (b) full wave rectifier
Large value of the product CRL results in a small ripple factor. Thus increasing C or RL
(both) an approximate perfect DC voltage can be obtained.
Page 38
Figure 1.2.21: Filtered waveform (a) half wave rectifier and (b) full wave rectifier
[floyd] (c) filtered and rectified wave (d) approximation of filtered wave
The performance of the filter circuits is measured by ripple factor. The approximate filtered
waveform shown in Figure 1.2.21(d). The ripple factor for Capacitor filter for the HWR and
FWR is given by equation (1.2.18) and (1.2.19) respectively.
(1.2.18)
2 3 fCRL
1
4 3 fCR L
(1.2.19)
The corresponding dc value for HWR and FWR is given by equation (1.2.20) and (1.2.21)
respectively.
Vdc
2 f CRL
Vm
1 2 f CRL
(1.2.20)
Vdc
4 f CRL
Vm
1 4 f CRL
(1.2.21)
Note 5: Here f in equation (1.2.18) to (1.2.21) is the frequency of the input signal
Comparison of ripple factor and the output dc voltage achieved from the input
secondary Vi (t ) Vm sin(2ft) is listed in Table 1.2.2
Page 39
HWR
FWR
Vdc
2 f CRL
Vm
1 2 f CRL
4 f CRL
Vm
1 4 f CRL
Ripple factor
2 3 fCRL
4 3 fCRL
Solved Exercise:
1. A sinusoidal voltage of peak value Vi 50 sin(2 50t ) V is applied to FWR. If the
load resistance is 1000. calculate the average and RMS value of load current,
efficiency and ripple factor. Find the frequency of the output signal.
Given
Vm = 50V, f=50Hz, RL = 1000 , Rf=10
Solution:
I m
Vm
50mA
RL
I dc
2Im
31.83 mA ,
I rms
Im
35.35 mA
2
Vdc2
RL
81.2%
Efficiency 2
Vrms
RL
Ripple factor =
I dc
0.6365
I ac
Page 40
3. Find the transformer turns ratio required in India for the data given in excercise 5.
Solution:
Using equation (1.2.21), the peak value of the secondary is
V (1 4 f CRL )
=5.866
Vm dc
4 f CRL
230 2
=55
5.886
Summary
1. A pure sinusoidal signal has an average value equal to zero. It means the dc value of
this signal is zero.
2. A DC power supply unit consists of : Step down transformer, Rectifier circuits, Filter
circuit and Regulator.
3. In a HWR the diode conducts only during positive half cycle and hence the circuit is
referred as Half Wave Rectifier. The rectified voltage is pulsating DC, which can be
smoothened using filter circuits.
4. In a FWR the diodes conduct in both half cycles and hence the name Full Wave
Rectifier.
5. In a bridge rectifier there are four diodes.
6. A capacitor filter is used in rectifier circuits to remove DC components called as
ripples.
Page 41
Exercise:
1.Primary voltage is 240V, 60Hz. Turns ratio is 10:1. This transformer
supplies to bridge rectifier employing 4 identical ideal diodes. The load
resistance is 1k. Calculate average and rms load voltage, efficiency, ripple
factor, PIV rating and the frequency of output waveform.
(Ans.: 108V, 120V, 81%, 0.484, 169.7V,120HZ)
2.Repeat this problem for center tapped FWR. Comment on the results
comparing it with results of problem 1.
3.A half wave rectifier with capacitor filter is supplied from a transformer
having peak secondary voltage 20V and frequency 50Hz. The load resistance
is 560 and capacitor used is 1000F. Calculate ripple factor and dc output
voltage. Draw the filtered output and label peak and dc value.
(Ans. 0.0103, 19.65V, waveform shown in figure Ex. 3)
Figure Ex. 3
4. Repeat excercise 3 for a full wave rectifier
5. Calculate the secondary peak voltage and value of capacitor needed to
get ripple factor of 0.05, dc voltage of 30V arcoss 900 load assuming f
= 50Hz with capacitor filter HWR.
(Ans.
:
33V,
128.3F)
6. Repeat excercise 5 for a full wave rectifier.
Page 42
Learning Outcomes:
At the end of this module, students will be able to:
1.Describe the working of Zener as voltage regulator
2.Understand the IC based voltage regulator.
Page 43
If the power supply voltage drops to 10-volts from initial 12 volts as mentioned
above. The Zener diode still drops 5-volts (designed voltage) and the series resistor R will
drop 5 volts. Again, because the load is connected across the Zener diode, it will produce 5volts. Therefore, irrespective of change in line voltage, output voltage remains constant of
5V.
Self test:
1. If the series resistance increases in an unloaded Zener regulator, the Zener current
a. Decreases
b. Stays the same
c. Increases
d. Equals the voltage divided by the resistance
2. In a loaded Zener regulator, which is the largest current?
a. Series current
b. Zener current
c. Load current
d. None of these
3. If the load resistance increases in a Zener regulator, the Zener current
a. Decreases
b. Stays the same
c. Increases
d. Equals the source voltage divided by series resistance
4. A voltage regulator is a circuit which
a. Converts the ac voltage to dc voltage
b. Smoothens the ac variation in dc output voltage
c. Maintains a constant dc output voltage inspite of the fluctuations in ac input voltage or
load current
d. None of the above
Page 44
requires more current when RL is decreased, the zener diode can supply the extra current
without affecting the load voltage.
I Iz IL
I
Vin Vz
R
(1.3.1)
(1.3.2)
Vin VZ
I
(1.3.3)
Vin VZ
IZ IL
(1.3.4)
VZ
(i) For Line regulation RL is constant and IL R is also constant and Vin varies between
L
Vin(min) to Vin(max)
(ii) For Load Regulation, Vin is constant and RL varies between RLmin and RLmax and load
current is given by I Lmin
VZ
VZ
and I Lmax
R Lmax
R Lmin
Page 45
Vin(min) Vz
I min
(1.3.5)
I min I z(min) I L
Similarly when Vin=Vin(max) I max
(1.3.6)
Vin (max) VZ
R
I max I Z ( nax) I L
(1.3.7)
(1.3.8)
The selected R must be small enough to permit minimum zener current to ensure that
the diode is in its breakdown region. That is R must be small enough to ensure that minimum
current IZ(min ) flows under worst condition. This is when Vin falls to its smallest possible
value Vin(min) and IL is its largest possible value ILmax (Load Regulation). At the same time R
must be selected large enough to ensure that the current through the zener diode should not
exceed the maximum zener current Iz(max) so that power desipation in the diode will not
exceed Pz. That is the condition when Vin rises to the value of Vin(max) and load current IL to
its minimum ILmin
Therefore,
Vin(min) VZ
I zmin I Lmax
and
Vin(max) VZ
I zmax I Lmin
(1.3.9)
Applications:
As Voltage regulators
As Voltage Limiters
Wave shaping
Protection diode
Fixed reference voltage
Page 46
Page 47
To understand the Zener Regulation with a variable load (load regulation), consider the
following example.
Design a zener regulator circuit to meet the following specifications:
Load voltage=8V, input voltage=30 V, Load current=0-50 mA, Izmin= 5 mA, Pz= 1W
Vin(min) = Vin(max)= 30 V. ILmin= 0A, ILmax= 50 mA
I Z max
PZ 1
V
8
125mA , RL min o
160
Vo 8
I L max 50mA
Rmax
Vin min Vo
I L max I Z min
Rmin
Vin max Vo
I L min I Z max
30 8
0.05 0.005
30 8
0 0.125
400
176
Example Problem 1:
1. An 1N756 zener diode is used as a 12 V regulator in the circuit shown below:
What is the smallest load resistor that can be used before losing regulation? Assume the ideal
model for the zener diode?
Solutions:
The no load zener current
INL = (VIN VZ) / R = (24 V-12 V) / 470 = 25.5 mA
This is the maximum load current in regulation, therefore the minimum value of load
resistance RL(min)= VZ / INL = 12 V/ 25.5 mA = 470 .
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Note that if RL is less than 470 it will draw more of the total current away from the
zener diode and IZ will be reduced below IZK. This will cause the zener diode to come out
of break down and hence output will not be regulated.
2. A certain zener diode has a V z = 7.5 V and an Rz = 5 at a certain current. Draw the
equivalent circuit.
Solutions: The equivalent circuit is shown below.
3. When the reverse current in a particular zener diode increases from 20 mA to 30 mA,
the zener voltage changes from 5.6 V to 5.65 V. What is the resistance of this device?
Solutions:
RZ
VZ
5.65 5.6
5
I Z 30mA 20mA
4. Determine the minimum input voltage required for regulation to be established in the
figure shown below. Assume an ideal zener diode with minimum zener current = 1.5 mA
and Vz = 14 V.
Solutions:
VIN (min) VZ I ZK R 14 (1.5mA)(560) 14.8V
Page 49
Page 50
Exercise problems
Page 51
(a)
(b)
Page 52
(c)
Figure 1.4.1 (a) Circuit symbol of LED (b) Different color LEDs (c) Structure of a typical
LED
One of the common applications of the LED is in seven segment display. A common
anode seven segment display arrangement is shown in Figure 1.4.2. It can be used to display
any alphanumeric character.
LEDs are also used in burglar alarm system, digital meters, electronic display panels,
optical communication system etc. LED's are much cheaper, last nearly indefinitely, and
consume less energy. The biggest disadvantage is the cost of replacement to the consumer.
For example, in the past, if a single instrument cluster bulb went out, it could be easily
replaced. Today, if a single LED goes out on the instrument cluster, it is not replaceable. The
entire instrument cluster must be replaced.
Page 53
the illuminance. The linear response to light makes it useful photodetectors for some
applications. It is also used as the active element in light-activated switches.
(a)
(b)
(c)
Figure 1.4.3. (a) Symbol of photo diode (b) Circuit using photodiode (c) Characteristic of
photodiode. [http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/photdet.html]
Photo diodes are used as/in light detectors, demodulators, encoders, high speed counting,
switching circuits etc.
1.4.3 Optocoupler:
An optocoupler, also called opto-isolator, is an electronic component that transfers an
electrical signal or voltage from one part of a circuit to another or from one circuit to another,
while electrically isolating the two circuits from each other as shown in Figure 1.4.4. It
consists of an infrared emitting LED chip that is optically in-line with a light-sensitive silicon
semiconductor chip, all enclosed in the same package. The silicon chip could be in the form
of a photo diode, photo transistor, photo Darlington, or photo SCR(silicon controlled
rectifier).
The optocoupler application or function in the circuit is to:
Page 54
Self Test
1. A LED is a diode that gives off ...........when .........biased.
2.LED is manufactured using gallium arsenide gives ........... light.
3. How photo diode differs from rectifier diode?
4. The output voltage of Optoisolator depends upon.........
5.What is dark resistance of photo-diode ?
6. To display the digit 0 in a common anode seven segment display
(i) A must be ON
(ii) F must be OFF
(iii) G must be ON
(iv) all segments except G should be ON
Page 55
Cover - a clear glass or plastic layer that provides protection to external elements.
Transparent Adhesive - holds the glass to the rest of the solar cell.
Anti-reflective Coating - this substance is designed to prevent the light that strikes the cell
from bouncing off so that the maximum energy is absorbed into the cell.
Front Contact - Transmits the electric current.
N-Type Semiconductor Layer - This is a thin layer of silicon which has been mixed with
phosphorous to make it a better conductor.
P-Type Semiconductor Layer - This is a thin layer of silicon which has been mixed or
doped with boron to make it a better conductor.
Back Contact - Transmits the electric current.
Figure 1.4.5. Structure of solar cell
[www.solarbc.ca/sites/default/files/pdf/how_a_solar_cell_works__dec_9.pdf].
N-Layer- is often formed from silicon and a small amount of Phosphorus. Phosphorus gives
the layer of excess of electrons and therefore has a negative character. The N-layer is not a
charged layer but it has an equal number of protons and electrons. Also some of the electrons
are not held tightly to the atoms and are free to move.
P-Layer- is formed from Silicon and Boron and gives the layer a positive character because
it has a tendency to attract electrons. The P-layer is not a charged layer and it has an equal
number of protons and electrons.
P-N Junction - when the two layers are placed together, the free electrons from the N-layer
are attracted to the P-layer. At the moment of contact between the two wafers, free electrons
from the N-layer flow into the P-layer, then form a barrier to prevent more electrons from
moving from one layer to the other. This contact point and barrier is called the P-N junction.
Once the layers have been joined, there is a negative charge in the P-layer and a
positive charge in the n-layer section of the junction. This imbalance in the charge of the two
layers at the P-N junction produces an electric field between the p-layer and the N-layer. If
the PV cell is placed in the sun, radiant energy strikes the electrons in the P-N junction and
energizes them, knocking them free of their atoms. These electrons are attracted to the
positive charge in the N-layer and are repelled by the negative charge in the P-layer. A wire
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 56
can be attached from the P-layer to the N-layer to form a circuit. As the free electrons are
pushed into the N-layer by the radiant energy, they repel each other. The wire provides a path
for the electrons to flow away from each other. This flow of electrons constitutes electric
current. The electron flow provides the current, and the cells electric field causes a voltage.
With both current and voltage, power is obtained, which is the product of the two. Solar array
is shown in Figure 1.4.6.
Page 57
Since the Voc for one solar cell is approximately 0.5-0.6V, then individual cells are
connected in series as a solar panel to produce more usable voltage and power output
levels. Most solar panels are made to charge 12 V batteries and consist of 36 individual cells
(or units) in series to yield panel Voc 18-20 V. The voltage for maximum panel power
output is usually about 16-17 V.
Summary
1.
2.
3.
4.
5.
6.
Page 58
Exercise Problems:
1. Light Emitting Diodes (LED) is used in fancy electronic devices such as toys emit
A. X-rays B. Ultraviolet light C. visible light D. radio waves
2.The maximum wave length of photons that can be detected by a photo diode made of
a semiconductor of band gap 2 eV is about
3. List the applications of optocouplers and LEDs
4. What value of series resistor is required to limit the current through a LED to
10 mA with a forward voltage drop of 1.6 V when connected to a 10V supply?
(Ans: 840 )
5. Define sensitivity of the photo-diode.
6. How reverse biased voltage effects the capacitance of the varactor diode ? Explain
with the help of the curve.
Page 59
Chapter 2
BJT and Applications
The first Bipolar Junction Transistor (BJT) was demonstrated by a team of scientists at Bell
laboratories in 1947. BJT has attractive features like, small in size, light weight, low power
consumption and low operating voltages. These devices are used in applications such as
signal conditioners, amplifiers, electronic switches, oscillators, etc.
Module 1: BJT Characteristics
Learning Outcomes:
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Current directions are opposite to the flow of electrons. IE is the emitter current, IB is the base
current and IC is the collector current. Arrow head represents the direction of current flow
through emitter in the transistor symbols shown in Fig 2.1.2(b).
2.1.2 BJT Configurations
Transistor is a three terminal device. For amplifier circuit, four terminals are required,
two for input and two for output. Hence, one of the three terminals of transistor is made
common to both input and output. Accordingly, there are 3 configurations:
Common base (CB) configuration
Common emitter (CE) configuration
Common collector (CC) configuration
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(2.1.1)
When the emitter circuit is opened, there is no supply of free electrons from emitter to
collector. Even then, there will be small amount of collector current called reverse saturation
collector current I CBO .This is due to thermally generated electron-hole pairs.
Even during normal operation, I CBO is present. So,the total collector current is:
I C dc I E I CBO
Where, dc is fraction of emitter current that flows to the collector. From (2.1.2)
I I
dc C CBO
IE
(2.1.2)
( 2.1.3)
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dc
(2.1.4)
IC
IE
Also,
dc
(2.1.5)
IC
IB
(2.1.6)
dc
(2.1.7)
dc
dc
dc
( 2.1.8)
dc 1
Also,
dc
dc
1 dc
(2.1.9)
(2.1.10)
(2.1.11)
I
I C dc I B CBO
(1 dc )
1 dc
When IB = 0, IC = ICEO and is given by,
( 2.1.12)
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I CEO
I CBO
(1 dc )
(2.1.13)
Self test:
1. Obtain the relation between dc and dc .
2. Obtain the relation between ICBO and ICEO.
2.1.43.BJT Characteristics
a. Common Base Input and Output characteristics:
Input Characteristics of Common Base configuration is a plot of input current IE versus input
voltage VEB, for various constant values of output voltage VCB. As VEB is increased, IE
increases. The characteristics curve is similar to diode characteristics. If VCB is increased,
then IE shoots up early. This is due to the increase in electric field aiding the flow of
electrons from emitter. The variation is shown in Figure 2.1.6 for various values of VCB.
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c. Cut-off region: This is the region below IE=0 curve (Figure 2.1.6). In this emitter
current IE is less than zero (E-B diode is reverse biased) and collector to base voltage
VCB is positive (C-B diode is reverse biased).Transistor is said to be in OFF state
since IC is zero.
2.1.4.2 Common Emitter Input and Output Characteristics
Input Characteristics of Common Emitter configuration is a plot of input current IB versus
input voltage VBE for various values of output voltage VCE. As VBE is increased, IB increases.
The characteristics curve is similar to diode characteristics. If VCE is increased to higher
constant value, then IB decreases slightly as shown in Figure 2.1.7. This is due to Early
effect.
Output Characteristics of Common Emitter configuration is a plot of output current IC versus
output voltage VCE for various values of input current IB. The characteristics can be divided
into three regions namely, Active, Saturation and Cut off regions.
Self test:
1. Define input and output characteristics of CB and CE configuration transistor.
2. List the different regions in the output characteristics of a transistor?
3. Give the biasing conditions required for the different regions of transistor operation.
4. Define Early effect.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 65
Example Problem 1:
1. A BJT has alpha (dc) 0.996 and collector-to-base reverse sat current 1A. If Emitter
current is 10mA. Calculate <i> Collector current <ii> Base current.
Ans: <i> I C dc I E I CBO
= 0.996*10*10-3+ 10-6
= 9.96 mA.
<ii> IB = IE - IC
= 10mA 9.96mA = 40 A.
Summary
Exercises:
1. A germanium transistor with 100 has collector to base leakage current of 5A. If
the transistor is connected in common emitter configuration, find the collector
current for base currents of 0A and 40A.
(Ans: 505A, 4.505mA)
2. The reverse leakage current of transistor when connected in common base mode
is 0.1A, while in common emitter mode its 16A. Find dc and dc
(Ans: 0.993, 159)
3. Find dc for dc=100.
(Ans: 0.99)
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Biasing means application of external voltage to the device so as to make it to operate in the
required region. For transistor to work as an amplifier, it is biased in active region. Similarly
if it has to work as a switch, it must be biased either in saturation or cut-off region.
2.2.1 DC Load line and need for Biasing
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IC = VCC/RC
2.2.10
By joining these two points defined by 2.2.9 and 2.2.10, the straight line can be drawn on the
output characteristics as shown in Figure.2.2.3. The resulting line on the graph is called the
load line since it is defined by the load resistor RC. The intersection of load line with the base
current results in operating point or Q point.
The variation of the Q-point up or down the load line with varying values of IB, RC and VCC
are shown in Figure 2.2.4. With IB variation Q point moves along the load line (Figure
2.2.1(a)). If RC of the circuit is varied, the slope of the load line changes (Figure 2.2.1(b). VCC
will shift the load line keeping the slope constant (Figure 2.2.1(c)).
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Figure 2.1.1(d): Effect of an increasing value of RC on the load line and the Q-point
Figure 2.1.1(e): Effect of lower values of VCC on the load line and the Q-point
Self test:
1. Why baising is required when BJT is connected in a circuit?
2. Mention the significance of DC load line.
2.2.2 Fixed Bias
3. State the parameters which are affecting the Q point.
2.2.2 Fixed Biasing
One of the simple way of biasing the transistor is by using fixed biasing technique.
Page 69
VCC VBE
RB
2.2.2
Vcc is constant, VBE is almost constant (0.7V for silicon). So by selecting proper RB, we can
fix IB as required. Applying KVL to the collector loop, which consists of VCC, RC, collector,
emitter and ground, we get:
VCC IC RC VCE 0 or VCE VCC I C RC
2.2.3
IC is related to IB by .
2.2.4
So, VCE can be fixed by selecting proper RC.
VCE can also be written as
2.2.5
using single subscript notations, where
ground, respectively. In the case of fixed bias,
Therefore,
2.2.6
In a similar way,
2.2.7
and since
2.2.8
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Example Problem 1:
1. For a fixed bias circuit using Si transistor, RB = 240 k, RC = 2.2 k, VCC = 12 V
and = 50. Find the collector current IC and VCE. Take VBE as 0.7 V.
Solution:
From the input loop expression,
IB= 47A
IC=IB
IC=2.3mA.
Exercises:
1. A Si transistor is biased for a constant base current. If = 70, VCEQ = 11 V, RC =
2 k and VCC = 15 V, find ICQ and the value of RB required.
( Ans: 2mA,
500K)
2. Find RB and RC for a fixed bais circuit given VCC=10V with operating point
(5V,3mA). Assume = 100, VBE = 0.3V. ( Ans: 323K, 1.66K)
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Page 72
IB
VTH VBE
RTH ( 1) RE
2.2.14
2.2.15
Rearranging, we get
VCE VCC I C RC I E RE
2.2.16
VC VCC I C RC
where, VC is voltage from collector to ground and,
VE I E RE
2.2.17
2.2.18
. If
IB
Now,
VTH VBE
RE
IC I B
VTH VBE
RE
2.2.19
2.2.20
Page 73
Since equation for IC does not contain , we say that IC is independent of temperature
variation and transistor replacement.
Exercises:
1. For a self-bias circuit using silicon transistor, RE = 200 , R1 = 10K, R2 = 1K,
RC = 2K, VCC = 15 V and = 100. Find the operating point.
(Ans: IB=30.79 A,
Summary
In this module we have learnt:
1. Importance of biasing in transistors
2. Concept of load line, operating point and their significance
3. Operating point dependent on the circuit parameters such as supply voltage and
resistor values as well as operating temperatures.
4. To analyse fixed bias circuit to obtain the operating point and plot the load line.
5. Finding the equivalent circuit for self bias circuit and analyse it to obtain the Q
point.
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generally used in amplifier circuits. Positive feedback will increase the gain but decrease the
stability and bandwidth. It will be used in oscillator circuits (negative and positive feedback
significance).
CE is called emitter by-pass capacitor. It is used to provide a negative feedback signal to the
amplifier. The negative feedback in amplifiers will improve the performance such as stability,
frequency response of the amplifier. CE offers low reactance path for ac component, thus
preventing ac component from passing through RE. With this ac voltage drop across the
resistor RE is zero. The circuit is named as RC coupled amplifier without feedback as there is
no feedback signal available to the input. On the other hand if the capacitor C E is removed
from the circuit, then ac signal passes through RE, there will be ac voltage drop across it. As it
is a negative feedback, this will decrease VBE, bringing down output voltage. Hence circuit is
named as RC coupled amplifier with feedback. RL is the equivalent resistance of the load
connected at output of amplifier. As explained earlier, when input voltage varies, iB varies,
this varies the iC proportionally. Thus the output voltage is a amplified version of the input
voltage, but with a phase shift of 1800.
2.3.2 Frequency response of an amplifier
Plot of amplifier gain versus frequency of input signal is called frequency response.
Frequency of input signal is increased in steps. At each frequency, voltage gain is determined
and then plotted. It is found that gain is very small at lower frequencies and at higher
frequencies. Gain remains constant at mid frequencies. For audio amplifier, it is required that
gain should be constant over the audio frequency range from 20 Hz to 20 kHz. Bandwidth of
amplifier is defined as range of frequencies over which gain is either equal or greater than
0.707 (or 1/2) times the maximum gain. Since 20 log10(0.707) = 3, bandwidth is also
defined as range of frequencies over which gain is within 3 dB of maximum gain (in dB).
Figure 2.3.3 shows the frequency responses of RC coupled amplifier with and without
feedback. It can be observed that without feedback circuit has a larger gain but smaller
bandwidth as compared with the circuit with feedback.
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(2.3.3)
However, practically the gain will be less than calculated AV due to loading effects..
Amplifier circuits are used for increasing the strength of week signal.
The working of an RC coupled amplifier with and without feedback.
The Gain of the amplifier defined as ratio of output signal to input signal.
The frequency response is a plot of frequency v/s gain of the amplifier and defines the
bandwidth.
5. Gain of multistage amplifiers will be obtained by multiplying gain of each individual stage.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 78
Exercises:
1. An amplifier has a bandwidth of 500KHz. If the lower cut-off frequency is
500Hz, what is the upper cut-off frequency? (Ans: 500.5KHz)
2. What is the voltage gain at the lower cut-off frequency, if the mid band gain of
the amplifier is 120? (Ans: 84.84V)
3. In a three-stage amplifier, the voltage gain of first stage is 150, gain of second
stage is 300 and that of third stage is 10. Find the overall gain of the amplifier
in dB. (Ans: 113.1dB)
In the previous section we have explored the use of transistor as an amplifier, where it was
configured in active region. In this module we will study the use of transistor configured in
other regions of operation.
2.4.1 Introduction
Transistor can be made to operate as ON/OFF solid state switches. Transistor switches can
be used for controlling high power devices such as motors, solenoids or lamps, as well as
they can be used in low power digital electronics and logic gate circuits. To be specific the
transistor must operate in the extreme ends of the load line curve: i.e. in cut-off and saturation
regions. To review, in cut-off region both junctions of the transistor are reverse biased, (VBE
< 0.7V and IC = 0) whereas, in saturation region both junctions were forward biased, ( VBE >
0.7V and IC = Maximum). The operating conditions of the transistor in the cut off region and
saturation regions are listed in the table given below. Therefore transistor in cut off region
Parameters
IB
IC
VCE
Saturation region
Maximum
Maximum
Zero
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acts as a Fully-OFF switch. In saturation region the transistor acts as a Fully-ON switch.
Figure 2.4.1 Transistor as switch. (a) circuit diagram (b) and (c) are equivalent circuits when
the switch is OFF and ON respectively.
The circuit diagram of the transistor switch is as shown in Figure 2.4.1 with the equivalent
circuits. With a zero Vin signal applied to the Base of the transistor it turns OFF acting like
an open switch and zero collector current flows. With a positive Vin signal applied to the
Base of the transistor, it turns ON acting like a closed switch and maximum circuit current
flows through the device, provided the base current is large enough to drive the transistor in
to saturation.
2.4.2 Transistor as LED driver:
.
Figure. 2.4.2: LED driver circuit
The circuit of an LED driver is as shown in Figure. 2.4.2 The series resistor R is used to
provide the required base current of the transistor. With the input voltage Vin =0V, no current
flows through the base of the transistor, and hence the transistor is in cut-off region.
Therefore, with the collector current zero, the LED does not turn on. When Vin VCC, the
flow of base current through the transistor drives it to saturation and behaves like a closed
switch. The amplified collector current turns the LED on. If the Vin is directly connected to
LED through the resistor R, without any transistor, the current through the LED would be
I=Vin/R, which is not sufficient to drive the LED.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 80
Summary
In this module we have learnt:
1. The transistor can be used as switch by operating it in either saturation
region (when the switch is said to be ON) or in cut off region (when the
switch is said to be OFF).
2. The applications of transistor switch as LED driver and inverter.
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Chapter: 3
Operational Amplifier and Applications
Module-1: Operational Amplifier
Operational Amplifiers, or Op-amps as they are usually called, are one of the basic building
blocks of Electronic Circuits. Op-Amps are one of the widely used ICs (Integrated Circuits)
in electronics. The very name Operational Amplifier comes from the fact that they are used to
build circuits to perform variety of mathematical operations such as addition, subtraction,
integration, differentiation etc., Operational amplifiers exhibit properties of nearly ideal DC
amplifier and are therefore employed in a wide range of applications.
The integrated operational amplifier has gained wide acceptance as a versatile, predictable,
and economic system building block because of its small size, high reliability, and reduced
cost.
Learning Outcomes:
Draw the internal block diagram of an OP-AMP and briefly describe the functions
List and define key parameters of an OP-AMP.
Discuss OP-AMP based amplifier topologies.
Design OP-AMP based circuits for simple mathematical operations.
3.1.1 Introduction
An operational amplifier is a high gain direct coupled amplifier which can amplify signals
over a wide range of frequencies. The circuit symbol of op-amp is shown in Fig. 3.1.1, which
has two inputs and a single output. The input terminal that is marked as positive is called noninverting terminal and that marked as negative is known as inverting terminal. The output
signal of an Operational Amplifier is the amplified version of the difference between the two
signals being applied to the two inputs. One of the common IC versions of op-amp is A741.
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Page 83
shifting stage is used to eliminate the dc level. Buffer is a unity voltage gain amplifier usually
used for impedance matching.
Output stage: This stage contributes to the overall gain of the op-amp and also provides low
output impedance.
The pin diagram for a typical A741 op-amp with 8 pin DIP (Dual In-line Package) is shown
in Figure. 3.1.4.
Offset null
No connection
Inverting i/p
+Vcc
Output
-Vcc
Offset null
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When the forward bias voltage of transistor, TR1 is increased, the forward bias voltage of
transistor TR2 is reduced and vice versa. Then if the two transistors are perfectly matched,
the current flowing through the common emitter resistor, Re will remain constant.
Like the input signal, the output signal is also balanced and since the collector voltages either
swings in opposite directions (anti-phase) or in the same direction (in-phase) the output
voltage signal, taken between the two collectors is, (assuming a perfectly balanced circuit)
the zero difference between the two collector voltages.
This is known as the Common Mode of Operation with the common mode gain of the
amplifier being the output gain when the input is zero.
Ideal Operational Amplifiers also have one output (although there are ones with an additional
differential output) of low impedance that is referenced to a common ground terminal. The
op-amp rejects any common mode signals that are appearing at the inputs. That means, if an
identical signal is applied to both the inverting and non-inverting inputs then the voltage at
the output terminals due to such inputs should be zero. This is measuered by a parameter
called Common Mode Rejection Ratio (CMRR).
Common Mode Rejection Ratio (CMRR) is the ratio of the differential gain to the common
mode gain of Op-Amp.
An operational amplifier only responds to the difference between the voltages applied at its
two input terminals, known commonly as the Differential Input Voltage. If the same
voltage is applied to both the input terminals the resultant output will be zero. An Operational
Amplifiers gain is commonly known as the Open Loop Differential Gain, and is represented
as (Ao).
Op-amp specifications:
Output offset voltage (Voo): The output voltage, when both the inputs are zero is called the
output offset voltage. It is due to input offset voltage and input bias current.
Input bias current (Ib): It is the average of the current that flows into the inverting and noninverting input terminals when both of the two inputs are grounded.
Input offset current (Iio): It is the algebraic difference between the currents flowing into noninverting and inverting terminals of balanced op-amp.
Input resistance (Ri): It is the equivalent resistance that can be measured at either the
inverting or non-inverting terminal with the other terminal connected to ground.
Slew Rate(SR): It is defined as the maximum rate of change of output voltage per unit time.
i.e: SR =
max.
Supply Voltage Rejection Ratio (SVRR): The change in op-amp input offset voltage caused by
variations in one of the power supply voltage is called SVRR.
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Output resistance (Ro): The equivalent resistance observed between the output terminal and
the ground.
Common Mode Rejection Ratio (CMRR): This is a figure of merit for an op-amp. It is defined
as the ratio of the magnitude of differential gain to the common mode gain.
The CMRR in deciBels is given by
dB
(3.1.1.1)
from input 1(2) to the output under the condition that input 2(1) is grounded. This is an
important specification, as it indicates how much of the common-mode signal Vc gets
rejected from the input. A high CMRR is desirable.
The output of a differential amplifier is given by
Vo = Ad Vd + Ac Vc.
(3.1.1.2)
Where, Vd = (V1 V2) and Vc = (V1 + V2) / 2 are differential and common mode inputs
respectively. Note: V1 and V2 are the non-inverting and inverting input voltages respectively.
Ideal Practical
2*105
Unity gain BW
1MHz
Input resistance, Ri
2M
Output resistance. Ro
zero
75
CMRR
90dB
Slew rate
high
0.5 V/s
SVRR
zero
150V/V
6mv (max)
200 nA (max)
10
50000
11
10
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For ideal op-amp, the characteristic do not change with temperature. Ideally, the op-amp is
perfectly balanced, if Vo = 0, when V1 = V2
Concept of Virtual ground:
The input impedance of an ideal op-amp is infinite (Ri =), that means there is no current
flowing into the op-amp. As the differential voltage gain of an ideal op-amp is infinite, V1-V2
tends to zero. This is equivalent to virtual short between two input terminals and hence if one
of the terminals is grounded the other terminal also experiences the same potential even
though they are not electrically connected. Therefore, it is called virtual ground.
Transfer Characteristics of a typical op-amp:
The transfer characteristics of op-amp is as shown in Figure 3.1.6. In the linear region, any
change in the input difference voltage, Vid produces a proportional output voltage. The
range of input difference voltage to operate the op-amp in linear region is approximately
equal to 100 mV. Beyond 100mV of Vid, the output becomes Vsat because of very high
gain offered by the op-amp. The output will be at +Vsat if it is used in non- inverting mode or
-Vsat if it is configured in inverting mode.
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Self test:
1.A linear integrated circuit responds to
a) Analog signal
b) Digital signal
c) Neither a) nor b)
d) Both a) and b)
b) only dc signal
c) offset voltage
d) CMRR
b) decibels (dB)
c) volts/sec d) volts/mS
5. An ideal OP-AMP has
a) infinite input impedance
Summary:
1. An operational amplifier is a high gain direct coupled amplifier which can
2.
3.
4.
5.
6.
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The inverting input terminal is at virtual ground, i.e. Vg = 0. Substituting in the above
expression,
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The negative sign indicates that there is 180 phase difference between input and output
signals. The voltage gain depends only on the resistor values as long as the op-amp is in
linear region.
3.2.2 Non-inverting amplifier:
The circuit diagram for a non-inverting amplifier is shown in Figure 3.2.2
Rf
Vout Vin 1
R1
(3.2.5)
The closed loop voltage gain for non-inverting amplifier is given by,
Av = (1+ Rf /R1)
(3.2.6)
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Vout = Vin
(3.2.7)
(3.2.8)
Thus, summing amplifier produces an output voltage which is an inverted (in sign), weighted
sum of all inputs.
If R1 = R2 =.= Rn , then,
(3.2.9)
If R1 = R2 =.= Rn = Rf then
(3.2.10)
The circuit is therefore acts as an adder or summer. Strictly speaking, this circuit is acting as
an inverting adder.
3.2.5 Difference amplifier
The circuit configuration for a difference amplifier is shown in Figure.3.2.5 It produces an
output voltage which is proportional to the difference between the two inputs.
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R2
R1
(3.2.11)
R
R4
When V1=0, Vout2 V 1 2 V2
R1
R3 R4
R4
R 3 R4
If R2 / R1 = R4 / R3 then,. Vout
R2
1
R1
R2
R
1
V1 2
R1
R1
R2
(V2 V1 )
R1
(3.2.12)
(3.2.13)
(3.2.14)
The circuit is called a difference amplifier and if, R1 = R2 = R3 = R4, the above equation
simplifies to Vout V2 V1 and the circuit acts as a subtractor.
3.2.6 Integrator
The circuit for an integrator is shown in Figure. 3.2.6. It produces an output voltage which is
proportional to the integral of input voltage.
(3.2.15)
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Vout
1
Vin dt
RC 0
(3.2.16)
3.2.7 Differentiator
The differentiator circuit is shown in Figure 3.2.7. It produces an output voltage which is
proportional to the differential of input voltage.
Fig.3.2.7: Differentiator
Applying KCL at inverting terminal
C
d (Vin 0) 0 Vout
dt
R
i1 = i2
Vout RC
dVin
dt
(3.2.17)
Exercises:
1.Realize the following equations using single op.amp..
1.
(i)Vo = -10V1 (ii) Vo = +5V1 (iii) Vo = - (2V1 + 4V2) (iv) Vo = (V1 - V2)
2.Realize the following equation using op.amp.
V0= 2V1- 0.8V2 + 0.5V3
3.Design an op-amp. inverting integrator which obtains -5V at 5ms when input
signal applied is 2V dc. Assume C=0.1 F.
4.A 100mV peak to peak sine wave form voltage is applied to an op.amp.
inverting amplifier with Rf/R1 =10. Sketch the output waveform.
Summary:
1. The closed loop voltage gain Av = -(Rf/Ri). The negative sign indicates that
there is 180 phase difference between input and output signals.
2. Voltage follower is a special case of non-inverting amplifier with unity gain.
3. Summing amplifier produces an output voltage which is an inverted (in sign),
weighted sum of all inputs.
4. The circuit of an integrator produces an output voltage which is proportional
to the integral of input voltage.
5. The differentiator circuit produces an output voltage which is proportional to
the differential of input voltage.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 93
(3.3.18)
(3.3.19)
Page 94
Vout VSat
V1 V2
VSat
V1 V2
V2 Vout
R1
Vout
R1 R2
(3.3.20)
R1
R1 R2
(3.3.21)
When Vout = +Vsat, capacitor will charge towards +Vsat. When the voltage across capacitor V1
exceeds Vsat , output makes a transition to Vsat and capacitor will start discharging towards
Vsat. When the voltage across capacitor V1 becomes slightly less than (Vsat ) , output makes
a transition to +Vsat and this action repeats.
The time period of the square wave generated is
1
T= 2RC ln
1
Where
R1
R1 R2
(3.3.22)
(3.3.23)
(3.3.24)
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Exercises:
1. Design a square wave generator using OP-AMP for the following specifications:
Frequency of oscillation = 2KHz, V0 (p-p) = 11.2V. Assume C=0.1F.
2. Name some applications of comparator.
3. Draw the output waveforms of inverting and non-inverting comparator if
Vin =5sin (21000t) volts and Vref = 2 volts.
Summary:
1.
2.
The output of the op-amp in a square wave circuit will be at either positive or negative
saturation voltages (Vsat) depending on V1 and V2
Page 96
Part II
DIGITAL ELECTRONICS
Chapter - 4 : Number systems and codes
Electronic circuits and systems can be broadly classified into analog and digital. Analog
circuits are those in which voltages and currents show continuous variations with respect to
time and can take any arbitrary value of magnitude within a specified range. A digital circuit
is one in which the voltage levels assume a finite number of distinct values. In all modern
digital circuits, normally there are two discrete voltage levels, called logic 0 and logic 1.
Learning Outcomes:
At the end of this module, students will be able to:
1.
2.
3.
4.
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Self test:
1.The number of bits required to assign binary roll umbers to a class of 60
students,_______
2. The highest decimal number that can be represented with 10 binary digit i ___
3. The bases of the binary and decimal numbering systems are multiples of 2. (T/F)
4. Binary word length are multiples of _______________
4.1 Conversion of numbers: The decimal system is a more familiar system than the other
systems. So it is essential to understand the conversion of a number from any base to decimal
and vice versa. The computer systems accept the data in decimal form, whereas they store
and process the data in binary form. Therefore, it becomes necessary to convert the numbers
represented in one system into the numbers represented in another system.
4.1.1: Decimal Number System
Decimal to Binary: The given decimal number is repeatedly divided by 2, which is the base
number of binary system till quotient becomes 0 and the remainder is collected from bottom
to top. To convert the fractional part into binary, fraction part is multiplied by 2 repeatedly
and any carry in integer place is recorded. The string of integer obtained from top to bottom
gives the equivalent fraction in binary number system.
Ex1: (42)10 = (101010)2
42
divided by
2
Q=21
R=0
divided by
21
2
Q=10
R=1
divided
by
10
2
Q=5
R=0
divided by
5
2
Q=2
R=1
divided by
2
2
Q=1
R=0
Note the way the bits are read to form the binary number.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 98
Decimal to Octal: The given decimal number is repeatedly divided by 8, which is the base
number of octal system till quotient becomes 0 and the remainder is collected from bottom
to top. To convert the fractional part into octal, fraction part is multiplied by 8 repeatedly and
any carry in integer place is recorded. The string of integer obtained from top to bottom gives
the equivalent fraction in the octal number system.
divided by
divided by
8
8
Q=12
Q=1
R=1
R=4
Decimal to Hexadecimal: The given decimal number is repeatedly divided by 16, which is
the base number of hexadecimal system till quotient becomes 0 and the remainder is
collected from bottom to top. To convert the fractional part into hexadecimal, fraction part is
multiplied by 16 repeatedly and any carry in integer place is recorded. The string of integer
obtained from top to bottom gives the equivalent fraction in the hexadecimal number system.
divided by
divided by
16
16
Q=34
Q=2
R=2
R=2
6
5
5
5
2
0
Page 99
15
11
2;
B
11 ; 5
2
7
Octal to decimal: Multiply the number by its equivalent octal weights. Add the products to
get the decimal number.
Ex1: (457)8 = 4 x 82 + 5 x 81 + 7 x 80 = 4 x 64 + 5 x 8 + 7 x 1 = 256+40+7 = (303)10
Ex2: (0.246)8 = 2 x 8-1 + 4 x 8-2 + 6 x 8-3= 2 x 0.125 + 4 x 0.015625 + 6 x 0.001953125
= (0.267969)10
Ex3: (457.246)8 = (303.267969)10
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Hexadecimal to Decimal: Multiply the number by its equivalent hexadecimal weights. Add
the products to get the decimal number.
Ex1: (B40)16 = 11 x 162 + 4 x 161 + 0 x 160 = 11 x 256 + 4 x 16 + 0 x 1=(2880)10
Ex2: (0.237)16 = 2 x 16-1 + 3 x 16-2 + 7 x 16-3 = (0.138427)10
Ex3: (B40.237)16 = (2880.138427)10
Self test:
1.
2.
3.
4.
5.
6.
Addend
0
1
0
1
Sum
0
1
1
0
Carry
0
0
0
1
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Addition in Octal system: Add the digit in each column in decimal and convert this sum into
octal. Write the sum in that column and carry the carry term to the next higher significant
column.
Addend
4
1
1
7
6
Sum
1 (5+4=9 8)
0 (6+1+1=8 8)
6 (4+1+1)
2(3+7=10 8)
2(3+6+1=10 8)
Carry
1(8 is subtracted once)
1(8 is subtracted once)
0(since sum <8)
1(8 is subtracted once)
1(8 is subtracted once)
Addition in Hexadecimal system: Add the digit in each column in decimal and convert this
sum into hexadecimal number. Write the sum in that column and carry term to the next
higher significant column.
Ex1: Add (7AB.67)16 to (15C.71) 16 = (907. D8)16
Augend
7
6
B(11)
Addend
1
7
C(12)
Sum
8
6+7 = 13 (D)
11+12=23 16= 7
A(10)
10+5+1 = 16 16=0
7+1+1 = 9
Carry
0(since sum<16)
0(since sum <16)
1(16
subtracted
once)
1(16
subtracted
once)
0(since sum <16)
Self test:
1.
2.
3.
4.
(303.32421875)10 = (________) 8.
(11111011001.010101111011)2 = (
)16.
The result of 6010 + F116 - 10010012 is ________ (in decimal).
The result of 112 + 278 + 9310 - B16 is ________ (in decimal).
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Page 103
Exercises:
1. (1BC)16 = ---------(8)
Summary
1. A numeral system (or system of numeration) is a writing system for
expressing numbers, that is, a mathematical notation for representing
numbers of a given set, using digits or other symbols in a consistent manner.
2. The computer systems accept the data in decimal form, whereas they store
and process the data in binary form. Therefore, it becomes necessary to
convert the numbers represented in one system into the numbers represented
in another system.
3. The advantage of performing subtraction by complement is reduction in the
hardware. Instead of having separate digital circuits for addition and
subtraction, only adding circuits are needed.
Page 104
Module 2 - Codes
Learning Outcomes:
At the end of this module, students will be able to:
1. Discuss different types of binary codes.
2. Explain error detection using parity bit.
3. Describe error correction using hamming code.
When numbers, letters or words are represented as a specific group of symbols based on
certain rules, it is said to be encoded. The group of symbols is called a code. Codes are
represented, stored and transmitted in the form of binary bits. The codes may also use alpha
numeric characters.
Advantages of Binary Code:
Suitable for computer applications.
Used in digital communications.
Ease of circuit implementation.
Classification of binary codes
Generally codes are classified into following categories.
Weighted Codes
Non-Weighted Codes
Alphanumeric Codes
Page 105
(4.2.1)
w3, w2, w1 and w0 are the weights selected for a given BCD code:
w3
w2
w1
w0
8421
7421
4221
8421
0000
0000
0000
0000
0001
0001
0001
0111
0010
0010
0010
0110
0011
0011
0011
0101
0100
0100
1000
0100
0101
0101
0111
1011
0110
0110
1100
1010
0111
1000
1101
1001
1000
1001
1110
1000
1001
1010
1111
1111
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EXCESS-3 CODE
The Excess-3 code is also called XS-3 code. It is non-weighted code used to express decimal
numbers. The Excess-3 code words are derived from the 8421 BCD code words by adding
(0011)2 or (3)10 to each code word in 8421.
GRAY CODE
The Gray code is neither a decimal code, nor is it an arithmetic code. The essential feature of
a Gray code is that there is only a single bit difference between successive code words.
Table 4.2.2 BCD, Excess-3 and Gray code equivalent for decimal numbers
Decimal
BCD = 8421
Excess-3
Gray
0000
0011
0000
0001
0100
0001
0010
0101
0011
0011
0110
0010
0100
0111
0110
0101
1000
0111
0110
1001
0101
0111
1010
0100
1000
1011
1100
1001
1100
1101
Page 107
Odd parity: the parity bit is set to 0 or 1 at the transmitter such that the total number
of 1 bit in the word including the parity bit is an odd number.
Even parity: the parity bit is set to 0 or 1 at the transmitter such that the total number
of 1 bit in the word including the parity bit is an even number.
Table 4.2.3 BCD with Odd and Even parity
Decimal
8 4 2 1 BCD
Odd Parity
Even Parity
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Self test:
1. What is the simplest technique for detecting error in the codes?
2. What is a parity bit?
3. What is a self -complementing code? Give an example.
Page 108
1. Example: In an even parity scheme, which of the following words contain an error?
a. 10101111
Ans: No
b. 1111111
Ans: Error
c. 10100001
Ans: Error
2. Example: In an odd parity scheme, which of the following words contain an error?
a) 10110100 Ans: Error
b) 11011011 Ans: Error
c) 10101000 Ans: No
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0
1
2
3
4
5
6
7
8
9
For EXCESS 3
P1 P2 D3 P4 D5 D6 D7
0 0 0 0 0 0 0
1 1 0 1 0 0 1
0 1 0 1 0 1 1
1 0 0 0 0 1 1
1 0 0 1 1 0 0
0 1 0 0 1 0 1
1 1 0 0 1 1 0
0 0 0 1 1 1 1
1 1 1 0 0 0 0
0 0 1 1 0 0 1
P1 P2 D3 P4 D5 D6 D7
1 0 0 0 0 1 1
1 0 0 1 1 0 0
0 1 0 0 1 0 1
1 1 0 0 1 1 0
0 0 0 1 1 1 1
1 1 1 0 0 0 0
0 0 1 1 0 0 1
1 0 1 1 0 1 0
0 1 1 0 0 1 1
0 1 1 1 1 0 0
At the receiving end, the message received in the hamming code is decoded to see if any
errors have occurred. Bits 1,3,5, 7 and bits 2,3,6,7 and 4,5,6,7 are all checked for even parity.
If they all check out, there is no error. If there is an error, the error bit can be located by
forming a 3 bit binary number C3 C2 C1
C3 D4 D5 D6 D7
C 2 P2 D3 D6 D7
C1 P1 D3 D5 D7
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 110
Example: Encode data bits 1101 into 7 bit even parity hamming code.
P1
P2
D3
1
P4
D5
D6
D7
Exercises:
1. If Hamming code received is 0110001, the correct data transmitted is ----(Assume even parity scheme)
2. Consider the sequence of digits 10001001010110000011. Determine the
number being represented in each of the following BCD coding schemes:
a. 8421 code
b. Excess-3 code
c. 2 4 2 1 code
3. 7 bit even parity Hamming code for the 4 bit 1011 is __________
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History
The algebraic system known as Boolean algebra named after the mathematician George Boole.
George Boole Invented multi-valued discrete algebra (1854) and E. V. Huntington developed
its postulates and theorems (1904). Historically, the theory of switching networks (or systems)
is credited to Claude Shannon, who applied mathematical logic to describe relay circuits
(1938). Relays are controlled electromechanical switches and they have been replaced by
electronic controlled switches called logic gates. A special case of Boolean Algebra known as
Switching Algebra is a useful mathematical model for describing the combinational circuits.
a. Boolean Algebraic theorems:
These have been derived by using Boolean postulates. These laws are used to design and
analyze logic circuit mathematically. Table 5.1.1 summarizes the Boolean theorems.
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Self test:
1. Prove laws of absorption using appropriate Boolean laws
b) Principle of Duality: One more important property of Boolean algebra is called Duality
principle. The Dual of any expression can be obtained easily by the following rules.
1. Change all 0s to 1s
2. Change all 1s to 0s
3. ANDs (dots) are replaced by ORs (plus)
4. ORs (plus) are replaced by ANDs (dots)
Example 1:
No.
Boolean Expression
X+0=X
X.1=X
X+Y=Y+X
X.Y=Y.X
X+1=1
X.0=0
AB
A+B .
A.B
AB
A+B
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De Morgons Second Theorem: It states that the complement of sum of variables is equal
to product of complement of two individual variables.
i.e. A B =
A.B .
A+B
A B
A.B
Solution:
i.
ii.
iii.
F = XYZ + XYZ
= XZ (Y +Y)
= XZ
(Y+Y=1)
F = X ( X + Y )
= X.X + XY
= XY
(X.X = 0)
F = B ( A +C ) +C
= BA + BC +C
= BA + C ( 1+B )
(1+B = 1)
= BA + C
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Example 3:
i.
ii.
i)
= Y ( WZ + WZ ) +XY
= YW ( Z+Z ) + XY
(Z+Z=1)
= YW + XY
= Y ( X+W )
ii)
(B+BA = B+A)
= C ( B+A ) + ABC
= BC + AC + ABC
= BC + A ( C+CB)
= BC + A ( C+B)
= BC + AC + AB
Exercise:
F = XY+XYZ+XYZ+XYZ
ii)
F = XYZ+XY+XYZ
(Ans : XY+YZ)
(Ans: Y)
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Summary
In this module we have learnt to:
1. List the Boolean algebraic theorems
2. Simplify the given Boolean expressions by applying Boolean Algebra theorems
3. The need for simplification of Boolean Expression.
4. The Dual of any expression can be obtained easily by the following rules - 1. Change
all 0s to 1s, 2. Change all 1s to 0s, 3. ANDs (dots) are replaced by ORs (plus)
and 4. ORs (plus) are replaced by ANDs (dots).
5. De Morgons First Theorem: It states that the complement of product of variables is
equal to sum of the complements of individual variable.
6. De Morgons Second Theorem: It states that the complement of sum of variables is
equal to product of complement of two individual variables.
7. Simplification of Boolean algebraic expressions makes cost effective and more
reliable logic circuits due to lesser number of interconnections.
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Output
Y= A+B
Realization of OR gate using diodes: Two input OR gate using "diode-resistor" logic is
shown in Figure 5.2.2, where X, Y are the inputs and F is the output.
D1
X
Y
RL
D2
If X = 0 and Y = 0, then both the diodes D1 and D2 are reverse biased and thus both
the diodes are in cut-off and thus F is LOW.
If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward
biased, thus conducts and thus pulling F to HIGH
If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward
biased, thus conducts and thus pulling F to HIGH.
If X = 1 and Y = 1, then both the diodes D1 and D2 are forward biased and thus both
the diodes conduct and thus F is HIGH.
ii) AND Gate: The AND gate performs logical multiplication, and commonly known as
AND function. The AND gate has two or more inputs and a single output. The output of an
AND gate is HIGH only when all the inputs are HIGH. Even if any one of the input is LOW,
the output will be LOW. If A and B are input variables of an AND gate and Y is its output,
then Y=A.B
A
B
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Y=A.B
Realization of AND gate using diodes: Two input AND gate using "diode-resistor" logic is
shown in Figure 5.2.4, where X, Y are inputs and F is the output.
+Vcc
D1
X
RL
F
Y
D2
If X = 0 and Y = 0, then both the diodes D1 and D2 are forward biased and thus both
the diodes conduct and pulls F to LOW.
If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward
biased, thus conducts and pulls F to LOW.
If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward
biased, thus conducts and pulls F to LOW.
If X = 1 and Y = 1, then both the diodes D1 and D2 are reverse biased and thus both
the diodes are in cut-off and there is no drop in voltage at F. Thus F is HIGH.
iii) NOT Gate (Inverter): The NOT gate performs the basic logical function called
inversion or complementation. The purpose of his gate is to convert one logic level into the
opposite logic level. It has one input and one output. When a HIGH level is applied to an
inverter, a LOW level appears at the output and vice-versa.
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Output
Y= A
Realization of NOT gate using Transistors: A NOT gate using a transistor is shown in Figure
5.2.6. A represents the input and F represents the output.
+Vcc
RL
F
A
Output
Y = AB
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ii) NOR Gate: The output of the NOR gate is HIGH only when all the inputs are LOW.
A
Output
Y = A B
iii) XOR Gate or Exclusive OR gate: In this gate output is HIGH only when any one of the
input is HIGH. The circuit is also called as inequality comparator, because it produces output
when two inputs are different.
Y= A B =A B + A B
A
Output
Y = A B
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iv) XNOR Gate or Exclusive NOR Gate: XNOR gate is a gate with two or more inputs and
one output. XNOR operation is complementary of XOR operation. i.e. The output of XNOR
gate is High, when all the inputs are identical; otherwise it is low.
Output
Y = A B +AB
Self test:
1.How many two input AND and OR gates are required to realize the following expressions in addition
to inverters?
a)F1=ABC+ABCD+EF+AD
b)F2=A(B+C+D)(B+C+E)(A+B+C+E)
2.How to realize an inverter using XNOR gate?
3.List two typical applications of XOR lgate
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1. NOT operation:
A
2. AND operation:
A
B
Y=A.B
AB
3. OR operation:
A
A
AA
A
B
A+B
BB
4. NOR operation:
A
A B
A+B
B
2. AND operation:
A
A.B
A
B
3. OR operation:
A
B
A B
A+B
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4. NAND operation:
A
A
B
AB
AB
Exercise:
1. Draw the logic circuit for the Boolean expression. Y= BC+AC+ABC using
two input basic gates.
2. Show that AB+(A+B) is equivalent to AB. Also construct the corresponding
logic diagrams.
3. The most suitable gate to check whether the number of 1s in a digital word is
even or odd is
a) X-OR b) NAND c) NOR d) AND
4. Realize NOR and NAND gate using discrete components.
5. Construct an XOR gate using NAND gates only.
1.
Combinational Circuits
Sequential Circuits
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Combinational circuits are generally faster, since the operation need not have to be performed
in sequences. Combinational circuits can be constructed using Sum of Products (SOP) or
Product of Sums (POS). Sum is logically OR operation of different literals or signals. Product
is logically AND operation of different literals or signals.
a) Sequential Digital Circuits
Sequential switching circuits are those whose output levels at any instant of time are
dependent not only on the levels present at the inputs at that time, but also on the state of the
circuit, i.e on the history of the circuit. It means that sequential switching circuits have
memory. In addition to this, sequential circuits are also characterized by the presence of
feedback. Sequential circuits are therefore made of combinational circuits and memory
elements with feedback. Figure 5.2.12. represents a typical sequential circuit.
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3. Sum term: A sum term is the logical sum (OR) of literals. For example X+Y, X+Y+Z
are the sum terms where X,Y,Z are Boolean variables.
4. Sum of products (SOP): Sum of product is the logical expression in which OR of
multiple product terms are present. Each product term is the logical AND of literals.
Y+XY+XYZ is an example of SOP.
5. Product of Sums (POS): Product of sums is the logical expression in which AND of
multiple sum terms are present. Each sum term is the logical OR of literals.
(X+Y)((XY+Z)(X+Y+Z) is an example of POS.
6. Minterm: It is a special type of product (AND) term. It is a product term which
contains all the input variables that make up a Boolean expression.
7. Maxterm: It is a special type of sum (OR) term. A maxterm is a sum term that
contains all the input variables that make up a Boolean expression.
8. Canonical form: Canonical is defined as conforming to a general rule. The rule for
Boolean logic is that each term used in a boolean expression must contain all the
variables.
9. Canonical Sum of Products: A canonical SOP is a complete set of minterms that
defines when an output variable is a logical 1. Each minterm corresponds to the row
in the truth table when the output function is 1.
10. Canonical Product of Sums: A canonical POS is a complete set of maxterms that
defines when an output variable is a logical 0. Each maxterm corresponds to the row
in the truth table when the output function is 0.
Boolean algebra is used to simplify the Boolean expressions, thus reducing redundancy and
designing low cost logic circuits. Any logic expression can be implemented by logic gates.
b) Examples of combinational circuits:
i) Half Adder: An electronic combinational circuit which performs the arithmetic addition of
two binary bits is called Half Adder. In the half adder circuit, there are two inputs, addend
and augend and two outputs are Sum and Carry. The logic symbol of half adder is shown in
Figure 5.2.13 and the truth table of half adder is given in table 5.2.8.
A
Sum
Half Adder
Carry
Addend
0
1
0
1
Output
Sum
Carry
0
0
1
0
1
0
0
1
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The expression for sum and carry is given in expressions 5.2.1 and 5.2.2 respectively.
Sum= A B+A B =A B
(5.2.1)
Carry= A.B
(5.2.2)
The circuit for Half Adder using Basic Gates is shown in Figure 5.2.14
A
Sum= AB+AB =A B
Carry = A.B
Sum= AB+AB =A B
Carry = A.B
Sum
Full Adder
Carry
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Cin
Sum
Carry
The expression for sum and carry of full adder is given in expressions 5.2.3 and 5.2.4
respectively.
Sum= A B Cin+ A B Cin +A B Cin +ABCin
= A [ B Cin+ B Cin ]+A[ B Cin +BCin]
= A [B Cin]+A[ B Cin ]
= A B Cin
(5.2.3)
=B(A+Cin)+Acin
=AB+BCin+ACin
(5.2.4)
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Cin
Cin
A B
A B Cin
AB
BCin
AB+BCin+ACin
ACin
Summary
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Exercise:
1. Implement Full Adder using Basic gates.
2. Implement Full Adder using two half adders and an OR gate.
3. Simplify and realize using only NAND gates
4. F = XYZ+XYZ+YZ+ Z .
5. F = (A+ B +C) ( A +B+ C )(A+ B )
6. Simplify and realize using only NOR gates:
Y=A B C + A B C + B C +A C
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The canonical SOP and Canonical POS representation of a Boolean function are
complementary. The variables which exists in SOP representation do not appear in POS
representation. Similarly all the variables which exist in POS representation do not appear in
SOP representation. To convert from one canonical form to other canonical form, the
symbols and will be interchanged and the list of variables will be present in new form
which is actually missing from original form.
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Ex3: Determine the Boolean function from the truth table in terms of minterms. Also
give canonical POS form of the expression.
Inputs
Output
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22 map, 3 variables which is a 24 map and 4 variables which is a 44 map. These maps are
shown in Figure 5.3.1.
5.3.3 Simplification of Boolean expressions using K-map
The K-Map method may theoretically be applied for the simplification of any Boolean
expression regardless of its number of variables, but is most often used when there are fewer
than six variables because K-Maps of expressions with more than six variables are complex
and tedious to simplify. Each variable contributes two possibilities: the complemented and
un-complemented forms. It therefore organizes all possibilities of the system. The variables
are arranged in Gray code in which only one variable changes between two adjacent grid
boxes.
a) Two variable K-map
B
A
0 0
f(A,B)=A
b) Three variable K-map
Simplify the following Boolean expression using K Map.
F (A,B,C) = m(0,1,3,7)
BC
A
00
01
11
10
F = AB + BC
f(A,B,C,D)=AB+AD+C
Department of Electronics and Communication Engineering, M.I.T. Manipal.
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10 of the
1 given truth
0 table is1as follows:0
K-map
11
1
0
1
1
1
1
12
13
14
15
.
K-map generally becomes more cluttered and hard to interpret when the number of variables
increase. For expressions with larger numbers of variables, we have other algorithms. One
such algorithm is called Quine McCluskey algorithm and is suitable for automation.
Note:
When moving horizontally or vertically, only one variable changes between
adjacent squares. This property of K-map is unique and accounts for its
unusual numbering system.
In all K-maps, left and right edges are a common edge, while top and bottom
edges are also common. Thus top and bottom rows are adjacent, as are the left
and right columns.
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00
01
11
10
F = AB + AB
Summary
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Exercise:
1. Consider the truth table of a function. Transfer the outputs to the K map and
write the Boolean expression.
A
0
0
1
1
B
0
1
0
1
Y
1
1
0
1
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a) Clock Signal
A clock is derived using a special circuit that sends electrical pulses, called clock in the
context of digital applications as shown in Figure 6.1.1. Each pulse has a precise width and
there is a precise interval between pulses known as clock cycle time. Figure 6.1.2 shows
various parts of the clock signal for which the circuit will respond.
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a)
b)
Figure 6.1.3 (a): Logic diagram of Clocked SR Flip flop (b) Logical Symbol
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its
opposing inputs and is commonly used in memory circuits to store a single data bit as shown
in Figure 6.1.3 (a). The SR flip-flop actually has three inputs, Set, Reset and its current
output Q relating to its current state or history. The term Flip-flop relates to the actual
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operation of the device, as it can be flipped into one logic state (SET) or flopped back
into the opposing logic state (RESET). Figure 6.1.3 (b) shows symbolic representation of SR
Flip-Flop. The operation of S-R Flip Flop can be described as follows:
When Clock is High:
When S input is made 1 and R input is made 0, the Q output takes the state 1.
This is known as SET condition.
When S input is made 0 and R input is made 1, the Q output takes the state 0.
This is known as RESET condition.
When S = R = 0, the SR flip flop exhibits the memory. i.e. Qn+1 = Qn ; Holds the
state.
S = R = 1 is the Not allowed in S-R Flip flop.
When Clock is Low:
Irrespective of S and R inputs, the SR flip flop exhibits the memory. i.e. Qn+1 = Qn :
No change in the state.
The function of the circuit is described by the table 6.1.1. This table is called Truth Table.
Q(n+1) represents the next state of the output and Qn corresponds to the previous state.
Table 6.1.1: Truth Table of SR Flip-Flop
CLK
Q(n+1)
Mode
Qn
Previous Output
Reset
Set
Invalid
Invalid
Qn
Previous Output
Note: Practical available Flip flops are edge triggered, that means flip flop responds for clock edges
either positive edge or negative edge. Following are the symbolic representation of positive edge and
negative edge triggered flip flops. Observe the not (bubble) symbol at the clock of negative edge
triggered flip flop.
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d) D Flip-Flop:
The D flip-flop shown in Figure 6.1.4 (a) is a modification of the clocked SR flip-flop. The D
input goes directly into the S input and the complement of the D input goes to the R input.
The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is
switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear
state. The R and S inputs will be always in complimentary form, thus preventing R = S = 1
condition from occurring. When the clock (CLK) is low, previous data is stored, i.e, it
exhibits memory as shown in table 6.1.2.
a)
b)
Figure 6.1.4: (a) Logic diagram of D Flip flop (b) Logic Symbol
Table 6.1.2: Truth Table
En
Q(n+1
Mode
Reset
Set
Qn
Previous Output
e) JK Flip-Flop:
A JK flip-flop is a refinement of the SR flip-flop, in which the indeterminate state of the SR
type is defined in the JK type as shown in figure 6.1.5 (a). Inputs J and K behave like inputs S
and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the
letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flipflop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa.
a)
b)
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JK flip flop is one of the most versatile flip flop. The operation of JK flip flop can be
explained as follows:
When Clock is High:
J = K = 0 causes memory condition.
J = 0 & K = 1 causes reset condition.
J = 1 & K = 0 causes set condition.
J = K = 1 causes output to toggle. i.e. Qn+1 = Qn
When Clock is Low:
Irrespective of J & K inputs, the J-K flip flop exhibits the memory condition.
All these characteristics are summarized in Table 6.1.3
Table 6.1.3 Truth Table of JK flip-flop
CLK
Q(n+1)
Mode
Qn
Previous Output
Reset
Set
Qn
Toggle
Qn
Previous Output
f) T Flip-flop:
Figure 6.1.6 shows the logic circuit of T flip-flop in which J and K inputs of a JK flip flop are
combined and taken as a single input T. When T = 0, output of T flip-flop will remain as it
was previously. When T = 1, output of T flip-flop will be complement of its previous output
and hence this circuit is known as toggle circuit. The excitation table is as shown in Table
6.1.4.
(a)
(b)
Figure 6.1.6: (a) Logic Diagram of T Flip-flop (b) Logic symbol of T Flip-flop
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Q(n+1)
Mode
Qn
No change
Qn
Toggle
Qn
Previous Output
Self test:
5.
6.1.2 Counters:
A digital counter is a set of flip flops whose states change in response to pulses applied at the
input to the counter. In binary counter, the flip flops are interconnected such that their
combined state at any time is the binary equivalent of the total number of pulses that have
occurred up to that time. Thus a counter is used to count pulses. Each of the counts of the
counter is called state of the counter. The number of states through which the counter passes
before returning to the starting state is called modulus of the counter. In general an n-bit
counter will have n flip flops and 2n states and divides the input frequency by 2n. Hence it is
a divide by 2n counter.
a) Classification of counters
i) Synchronous and Asynchronous counters :
Counters may be synchronous or asynchronous counters as shown in Figure 6.1.7. In
Asynchronous counters, flip flops are not triggered simultaneously. Synchronous counters are
clocked such that each flip flop in the counter is triggered at the same time. This is
accomplished by connecting the same clock line to each stage of the counter. Synchronous
counters are faster than asynchronous counters because the propagation delay involved is
less.
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b) Applications of counter:
Counters are used
1.
2.
3.
4.
5.
6.
As Frequency divider,
To perform the timing function as in digital watches
To create time delays
To produce non-sequential binary counts
To generate pulse trains
To act as frequency counters.
c) Ripple Counters:
Asynchronous counters are also called as ripple counters. In ripple counters the flip flops
within the counter are not made to change the states at exactly the same time. In this counter,
JK flip flops or T flip flops are used with J and K inputs or T input of the flip flops connected
to 1. This makes the flip flop output to toggle when a clock pulse is applied. It is also called
as serial or series counters.
Example 3:
Design Two bit ripple up counter using negative edge triggered JK flip flops:
Steps:
1. Select 2 JK flip flops (number of flip flops depends upon number of bits to count).
2. Connect JK inputs to high
3. Apply the ve edge clock pulse to first JK flip flop
4. Write the truth table of 2 bit up counter as shown where Q1 and Q2 are the outputs
of 2 JK flip flops.
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Clk pulse
Q2
Q1(LSB)
5. Observe when higher bit (Q2) is changing. In this case, Q2 is changing when Q1 is
changing from logic 1 to logic 0 (At clock pulse 3). Since we require ve edge counter which
responses when clock is changing from 1 to 0 is required, connect Q1 as the clock for the
next flip flop as shown in Figure 6.1.7 (a)
Figure 6.1.7 (a) Asynchronous 2 bit up counter using -ve edge triggered flip flops (b) Timing
diagram
Working principle: For the clock pulse applied to FF1, the output of FF1 toggles. For the Q1
pulse applied to FF2, the output of FF2 toggles. Thus the 2 bit up counter counts in the order
0, 1, 2, 3, 0, 1, .Figure 6.1.7 shows a 2 bit ripple up counter using negative edge triggered
JK flip flops and its timing diagram.
Example 4:
Design Two bit ripple up counter using positive edge triggered JK flip flops:
Steps:
Steps 1and 2 are same as example 3
3 Apply the +ve edge clock pulse to first JK flip flop (Observe the Clk signal in Figure 6.1.7
4 Write the truth table of 2 bit up counter as in example 6.3
5 Observe when higher bit (Q2) is changing. In this case, Q2 is changing when Q1 is
changing from logic 1 to logic 0. Since we require +ve edge counter which responses when
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Page 146
clock is changing from 0 to 1 is required, connect Q1 (Q1 complement) as the clock for the
next flip flop (because when Q1 is changing 1 to 0 Q1 will change 0 to 1 which is the
positive edge of the clock) as shown in Figure 6.1.8
Figure 6.1.8 (a) Asynchronous 2 bit up counter using +ve edge triggered flip flops. (b)
Timing diagram.
Working principle: The output Q1 of FF1 is connected to the clock input of FF2. For the
clock pulse applied to FF1, the output of FF1 toggles. For the Q1 pulse applied to FF2, the
output of FF2 toggles. Thus the 2 bit up counter counts in the order 0, 1, 2, 3, 0, 1,
Example 5:
Design Two bit ripple down counter using negative edge triggered JK flip flops:
Steps:
Q2
Q1(LSB)
5 Observe when higher bit (Q2) is changing. In this case, Q2 is changing when Q1 is
changing from logic 0 to logic 1. Since we require ve edge counter which responses when
clock is changing from 1 to 0, connect Q1 (which changes 1 to 0 at clock pulse 3) as the
clock for the next flip flop as shown in Figure 6.1.9
(a)
(b)
Figure 6.1.9 (a) Asynchronous 2 bit down counter using -ve edge triggered flip flops. (b)
Timing diagram.
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Page 147
Working principle: The output Q1 of FF1 is connected to the clock input of FF2. For the
clock pulse applied to FF1, the output of FF1 toggles. For the Q1 pulse applied to FF2, the
output of FF2 toggles. Thus the 2 bit down counter counts in the order 0, 3, 2, 1, 0, 3
Figure 6.1.8 shows a 2 bit ripple down counter using negative edge triggered JK flip flops
and its timing diagram.
Self test:
1
2
3
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In a register data can be entered in serial form or data can also be output in serial form. Then
this register is called as shift register since data bits are shifted in the flip flops with each
clock pulse. Data can be shifted either towards right or left or even in both the directions.
When the data is shifted from left to right, it is known as right shift register. If data is shifted
right to left, it is called as left shift register. In bidirectional shift register, data can be shifted
either left to right or right to left, depending upon the mode control signal. Data transmission
in shift register is shown in Figure 6.1.10.
There are four basic types of shift registers namely, Serial in Serial out (SISO), Serial in
Parallel out (SIPO), Parallel in Parallel out (PIPO) and Parallel in Serial out (PISO) shift
registers.
a)
In SISO shift register, data input is in serial form and clock pulses are applied to each
flipflop. After each clock pulse, data moves by one position. The output can be obtained in
serial form. In this type of shift register data moves either in left or right direction.
The logic diagram of a 4 bit SISO shift right shift register is shown in Figure 6.1.11 with four
flip flops, the register can store up to four bits of data. Serial data is applied at the D input of
the FF1. The Q output of FF1 is connected to the D input of FF2, the Q output of FF2 is
connected to the D input of FF3 and the Q output of FF3 is connected to D input of FF4.
When serial data is transferred into a register, each new bit is clocked into the first flip flop
FF1 at the positive going of each clock pulse. The bit that was previously stored by FF1 is
transferred to FF2. The bit that was stored by FF2 is transferred to FF3 and so on. The bit that
was stored by the last FF4 is shifted out.
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Table 6.1.5 Data shifting in 4 bit SISO sh load the data seriallyift register for data 1010
Note: Load the data serially from LSB to MSB. i.e. 0, 1, 0, 1
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Table 6.1.6 Data shifting in 4 bit SIPO shift register for data 1010
Latch is a level triggered bi-stable multi-vibrator circuit while a flip flop is an edge triggered.
Flipflop is an electronic circuit or device which is used to store data in binary form. . Latch is a
class of flip-flops whose output responds immediately to appropriate changes in the input.
We have studied the working principle of SR, D, JK and T flip flops using NAND gates.
In binary counter, the flip flops are interconnected such that their combined state at any time
is the binary equivalent of the total number of pulses that have occurred up to that time.
Registers are digital circuits which are used to store n bit information in the same time.
Shift registers are commonly used to store digital data during arithmetic and logical operations.
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Exercises:
1. Complete the timing diagram of D flip-flop
2
3
4
5
Design mod 4 down counter using +ve edge triggered T flip flop.
Design 4 bit up counter using ve edge triggered JK flip flop with the neat
timing diagram
Compare SISO and SIPO.
How many flip flops are required for storing n bits of information.
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Part III
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e. Noise: It is a random, undesirable electrical energy that interferes with the transmitted
signal. Noise is a highly undesirable part of the communication system which must be
minimized. The noise introduced in the transmission medium is called external noise and the
noise introduced in the transmission and reception equipment is called as internal noise. The
main cause of internal noise is the thermal agitation of atoms and electrons of the electronic
components used in the equipment.
f. Receiver: The receiver block mainly consists of receiving antenna, filter, demodulator and
amplifier. The signal received from receiving antenna is filtered and desired signal is
amplified. It is further demodulated to get back the information signal. Finally an output
transducer is employed to convert back the information in electrical form to physical form.
7.1.2 Need for Modulation
In wireless communication, the free space is the transmission medium through which
electromagnetic waves carrying information propagates. A transmitting antenna at the
transmitter radiates energy into the free space and it is received at the receiver using receiving
antenna. The original signal which is called base band signal is not suitable for direct
transmission/radiation over a long distance and hence modulation is usually performed.
Modulation is a process of varying some of the characteristics of high frequency carrier wave
in accordance with the instantaneous amplitude of base band signal. After modulation the
baseband signal of low frequency is transferred to the high frequency carrier, which carries
information in the form of some variations. The three parameters of a sinusoidal carrier that
can be varied are: amplitude, phase and frequency. A given modulation scheme can result in
the variation of one or more of these parameters.
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Self- test:
1. List the key components required for electronic communication.
2. List the basic functions of radio transmitter and the corresponding functions
of the receiver.
3. Signals travel in air as -------------4. ---------- is another name for simplex communication and ----- is another
name for duplex communication.
5. Signals travel over copper cable as----6. Signals travel over fiber optic cable as----7. What frequency band is used by the AM radio broadcasting station
Mangalore?
8. State 2 practical benefits of modulation in Communication system?
Note:
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, where
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where
is the peak
=
=
=
Where,
decides the depth of modulation. If it is less than one, then AM signal is known as under
modulated signal. If it is more than one, then AM signal is known as over modulated signal.
If it is equal to one, then AM signal is known as perfect modulated signal. To obtain the
original information, modulation index should always be less than or equal to one. The effect
of modulation index on AM wave is illustrated in Figure 7.1.4
m=0.5
m=1
m=1.5
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is the Lower Side Band (LSB). For this reason this is called AM DSB (Amplitude
Modulation with Double Side Band) system. The difference between the two side band
frequencies is defined as bandwidth of AM signal. Therefore the bandwidth of AM signal is
Self -test:
1. What is a spectrum? What are all the information obtained from the spectrum of AM
signal?
2. Imagine that there is a signal with two frequency components,
they modulate a carrier with frequency
and
with
. If
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Where,
and
Or
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Example Problem 1:
1. An audio signal of
volts. Find
i.
ii.
iii.
iv.
v.
Modulation index
Sideband frequencies
Bandwidth
Total power delivered if RL = 1k
Amplitude of each side band components
Solution:
i. Modulation index: m =
Am
10
=
= 0.25
AC
40
AC2
m2
1600
(0.25)2
(1+
) =
(1+
) = 0.825 Watts
2R
2
2000
2
A
40
v. Amplitude of each sideband = m C =0.25 *
= 5V.
2
2
Example Problem 2:
Certain AM transmitter radiates 9 kW of power with carrier unmodulated and 10.125kW of
power when carrier is sinusoidally modulated. Calculate the modulation index. If another sine
wave corresponding to 40% modulation is transmitted simultaneously, determine the total
power radiated.
Solution:
i. Given: PC = 9kW
PT= 10.125kW
PT=
PT = PC { 1 +
m = 2 T 1 =0.5.
PC
PT = PC { 1 +
mt
} = 10.84kW
2
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Exercises:
1. Show that modulation index =
2.
3.
4.
5.
VMAX VMIN
, where VMAX and VMIN are maximum
VMAX VMIN
and
minimum voltage values of the envelope of AM signal.
A 360W carrier is simultaneously modulated by two audio waves with percentage
modulation of 55 and 65 respectively. Find the modulation index, total power radiated
and power in each sideband. Assume RL=1. [Ans: mt = 0.85, PT =490W, PUSB =
PLSB = 65W].
A broadcast AM transmitter radiates 10kW when the modulation percentage is 60.
How much of this is the carrier power?
[Ans: Pc=8.47 kW]
The antenna current of an AM transmitter is 8A when only carrier is transmitted, but
increases to 8.93A when carrier is modulated by a single sine wave. Find the
percentage modulation. Determine the antenna current when the depth of modulation
changes to 0.8A.
[Ans: mc=70.1%, I 9.19A]
A sinusoidal carrier of frequency 10MHz and amplitude 20V is amplitude modulated
by another sinusoidal signal of frequency 10 kHz producing 40% modulation.
Calculate the frequency of upper and lower sidebands.
[Ans: 4V, USB freq =
10.01kHz, LSB freq = 99.99kHz
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communicated. This gives rise to another form of AM known as Single Side Band (SSB)
modulation. Thus in SSB, only one side band is transmitted by suppressing the other side
band and the carrier signal. This also results in reduced transmitter power compared to DSBSC. The main disadvantage of AM-SSB is, it requires complex receiver.
Vestigial Sideband (VSB) Signal:
It is another form of AM modulation, where one sideband is completely present, and a part
(vestige) of other sideband is retained. If the carrier signal is transmitted along with the side
bands, then the recovery of the baseband signal becomes easier. This also reduces the
complexity of the receiver circuit and which in turn reduces its cost.
Note:
Carrier power
Side band
power
% of power
saving as
compared to
AM-DSB
AM-DSB
66.67%
33.33%
NIL
AM radio
broadcast
DSB-SC
NIL
33.33%
66.67%
Non-commercial
systems
SSB
NIL
16.67%
83.33%
Carrier telephony
systems, military
applications
AM Scheme
Bandwidth
Typical
Applications
Self-test:
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There are a great variety of receivers in communication systems based on the requirements
such as the modulation scheme, the operating frequency and its range. One of them is superheterodyne type, which uses frequency mixing or heterodyning to convert a received signal to
get a fixed intermediate frequency (IF). This allows the processing of signal easier as the
circuits after IF needs to be designed for narrow band of frequency. The functional block
diagram is shown in Figure 7.1.7.
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Antenna
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Summary
1. Basic principle of electronic communication, which has essentially three components:
a) Transmitter, b) Receiver and c) Channel
2. Definition of modulation, which is nothing but varying some parameter of a known signal called
carrier in accordance with the amplitude of the message signal called modulating signal.
3. Modulation is necessary for the following reasons:
a) Ease of radiation b) efficient transmission and c) supporting multiplexing
4. To draw the waveforms for amplitude modulated signal with respect to the chosen modulating
and carrier signals.
5. Modulation index gives the depth of modulation or the extent to which the carrier is modulated
by the signal and is given by
6. Draw the spectrum of AM-DSB signal for a single tone modulation and identify two sidebands
and the carrier. The bandwidth of AM DSB is given by 2fm, where fm is the maximum frequency
component of the modulating signal.
7. The power content of AM DSB is given by
8. The different types of AM signal are AM DSB with carrier, DSB SC, SSB SC, SSB with carrier and
VSB.
9. AM DSB can be demodulated by relatively simple process of envelope detection.
10. One of the popular AM reception method is called super heterodyne principle, where in the
input RF signal is translated to an IF signal by mixing or beating it with the output of local
oscillator. Since the local oscillator frequency is maintained above the incoming signal
frequency it is called Super- heterodyning.
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where
is the message
in
where
is the frequency deviation. It signifies the amount by which the carrier frequency
gets deviated.
Multiplying by
Since,
(since
Therefore, the equation of FM Signal is given by,
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Where
will have a large number of sidebands and hence larger bandwidth. Ideally, FM
signal has infinite bandwidth. However, for practical purpose, Carsons rule is followed,
which says that for good reception of FM, it is enough if those many side bands which
constitutes 98% of power is taken. This acts as the basis for estimation of bandwidth for FM.
The bandwidth for FM as per Carsons rule is given by,
Self -test:
1
2
3
4
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Example Problems:
1 Given a FM equation VFM (t) = 10 cos [2 108t +
f
5 10 3
Am
2.5
f = Kf Am = 2
= 2 kHz /V
7.5 = 15 kHz
Modulation index: =
ii)
iii)
f
=
fm
f = Kf Am = 2 10 = 20 kHz
Modulation index: = 80
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Exercises
1 A carrier of amplitude 5V and frequency 90MHz is frequency modulated by a
sinusoidal voltage of amplitude 5V and frequency 15 KHz. The frequency sensitivity is
1Hz/V. Calculate the frequency deviation and modulation index.
(Ans: f = 5Hz,
=0.0003)
2 The carrier frequency in an FM modulator is 1000 KHz. If the modulating frequency is
15 KHz, what are the first three upper sideband and lower sideband frequencies?
(Ans: 955kHz, 970kHz, 985kHz, 1015kHz,1030kHz,1045kHz)
. 3. What is the modulation index of an FM carrier of frequency 120kHz and a modulating
signal of 10 kHz?
(Ans: = 60kHz, m= 6)
Parameter
AM
FM
Amplitude of the
modulated wave
constant
Frequency of the
modulated wave
Varies
instantaneously with
the modulating signal
amplitude
Contains Carrier and
sideband frequency
components
Modulation Index
4
5
Noise immunity
Adjacent channel
interference
Bandwidth
Circuit complexity
Coverage area
Less
More
More
Less due to guard bands
Less
Less
More
More
More
Less
6
7
8
Self -test:
1.
2.
3.
4.
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Exercises
1 Explain why FM waves cover shorter distances as compared to AM?
2 What is guard band? Explain.
Summary
In this module we have learnt:
1. The definition of Frequency Modulation is a process of altering the frequency
of the carrier signal with respect to the instantaneous amplitude of the
modulating signal.
2. To draw the waveforms for frequency modulated signal with respect to the
chosen modulating and carrier signals.
3. Modulation index gives the depth of modulation and is given by
4. The bandwidth is estimated approximately by Carlson Rule given by
Bandwidth = 2(f + fm)
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Chapter-8
Introduction to digital communication
In analog communication, the message signals are continuous in nature and can take infinite
amplitude levels. When these signals are transmitted over long distances, even a small
disturbance (noise) can cause distortion in the signal. Once the signal is distorted, the noise
cannot be removed and as a result the original signal cannot be recovered perfectly at the
receiver. With digital techniques, these disturbances can be removed by detecting and
correcting the errors. Hence digital communication has more benefits as compared to analog
communication. In digital communication, the message signal is in discrete form with finite
amplitude levels. If the message signal is analog, it must be converted to digital form by the
process of Analog-to-Digital Conversion.
Module-1: Digitization of Analog signals
For any analog information to be transmitted using digital communication system, the signal
must be converted to digital form. The Analog-to-Digital conversion process comprises of
sampling, quantizing and encoding the analog signal. The digitized signal is then modulated
using digital modulation techniques.
Learning Outcomes:
At the end of this module, students will be able to:
1. State Nyquist Sampling Theorem and explain.
2. Explain qualitatively pulse amplitude modulation technique with the help of suitable
waveforms.
3. Draw and explain the general block diagram of Digital Communication system.
4. Explain qualitatively different types of digital modulation techniques with the help of
suitable waveforms.
The basic principles of Analog to Digital Conversion are as shown in Fig 8.1.1.Sampling of
analog signals is the first step used to digitize analog information. Sampling can be observed
in numerous real life applications. For example, music CDs (Compact Discs) are produced by
sampling music signal at frequent intervals followed by quantizing and encoding each
sample. Even in digital photography, periodic snapshots (samples) are taken
to capture continuous phenomena. If the sampling rate is fast enough, the human sensory
organs cannot discern the gaps between each snapshot when they are played back. This is the
principle behind motion pictures. If the sampling rate is not fast enough, there will be
distortion in the reconstructed picture obtained from the digitized samples. Therefore, while
sampling an analog signal, there is a minimum sampling rate requirement, called the Nyquist
Department of Electronics and Communication Engineering, M.I.T. Manipal.
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Sampling rate that avoids distortion in the reconstructed signal. Harry Nyquist proved the
sampling theorem which states that It is possible to reconstruct a band-limited analog signal
from periodic samples, as long as the sampling rate ( fs)is at least twice the highest frequency
component (fm)of the signal.
Mmathematicaly it can be expressed as
fs 2fm
(8.1)
Where fs is the sampling frequency and fm is highest frequency component in the signal. This
theorem is also commonly called the Nyquist criteria for sampling or Sampling theorm.
This means that , for example if a voice signal has frequencies ranging from 0 to 4kHz (Low
pass signal), then according to the Nyquist Sampling Theorem, in order to sample this signal
without distortion, the minimum required sampling rate is equal to 8kHz. If an analog signal
has frequency components ranging from 2 kHz to 5 kHz (Band pass signal), then according to
the sampling theorem, the Nyquist sampling rate is equal to twice that of the bandwidth of the
signal.ie. 2*(5-2) kHz = 6 kHz and not 10 kHz.
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Illustration of Sampling:
Example Problem:
1A.Consider the analog signal x (t) =3cos100 t. Determine the minimum sampling
rate required to avoid aliasing .
Solution:
The frequency of the analog signal can be calculated as 2fc=100.
Therefore fc=50Hz.According to the Nyquist sampling rate, the minimum sampling
rate required to avoid aliasing is fs = 100 Hz.
1B. Consider the analog signal x (t) as in problem 1A.
a) Suppose that the signal is sampled at the rate of Fs = 200 Hz, draw the signal
obtained after sampling?
b) Suppose that the signal is sampled at the rate of Fs = 75 Hz, what is the signal
obtained after sampling?
c) What is the frequency of a sinusoid that yields samples identical to those obtained
in part (b)?
Self -test:
1 If a signal is composed of frequency components up to 10 kHz., what is the minimum
frequency at which the signal should be sampled as per Nyquiest criteria?
Department of Electronics and Communication Engineering, M.I.T. Manipal.
6 kHz
12 kHz
14.4 kHz
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Exercise:
1 Consider the analog signal x (t) = 3cos50t+10sin300t-cos100t. What is the
Nyquist rate of sampling for this signal?
(Ans: 300Hz)
Note: The effect of incorrect sampling rate can be seen when the rotation of a helicopter
blade is observed. As the speed of the blade increases, our eyes are under sampling the true
speed of the blade with a rate which is limited by the human brain. Similarly, in movies, when
the motion of car wheels with increasing speed is observed, the movie camera is under
sampling the motion of car wheels by sampling at a rate equal to the fixed frames per second
of the camera. In both the examples it is observed that as the speed increases, it creates an
illusion of backward rotation. This is because in both cases the actual speed is under sampled.
For Analogy of sampling to Wagon wheel effect, visit the following link:
http://www.youtube.com/watch?v=6XwgbHjRo30
Introduction to pulse modulation techniques
Pulse modulation involves communication of information using a train of pulses as
carrier. It may be used to transmit either analog information such as continuous speech or
digital data. If the modulating signal is in analog form, it is called analog pulse
modulation technique. Some of analog pulse modulation techniques are: Pulse Amplitude
Modulation (PAM), Pulse Width Modulation (PWM) and Pulse Position Modulation
(PPM). If digital data is used to modulate a train of pulses, then it is called digital pulse
modulation technique. Some of the digital pulse modulation techniques are: Pulse Code
Modulation (PCM) and Delta Modulation (DM).
Analog Pulse modulation is a process in which continuous waveforms are sampled at
regular intervals using a train of recurrent pulses. Information regarding the signal is
transmitted only at the time of sampling along with any synchronizing pulses that may be
required. At the receiving end, the original waveforms can be reconstructed from such
samples, if the samples are taken as per the sampling theorem or Nyquist criteria . In
analog pulse modulation, the sample amplitude may be infinitely variable while in digital
pulse modulation such as PCM and DM, a code which indicates the sample amplitude
that is assigned the nearest predetermined discrete amplitude level is sent.
A pulse train has three parameters, namely, Pulse Amplitude, Pulse Width and the instant
of occurrence of the pulse Pulse Position. The information to be transmitted can be
used to vary any of these parameters according to the instantaneous amplitude of the
modulating signal. This leads to three different types of pulse modulation and they are
Pulse Amplitude Modulation, Pulse Width Modulation and Pulse Position Modulation as
shown in Fig 8.1.2.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 176
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Fig 8.1.4 shows the functional elements of a digital communication system. The function
of each block is explained as follows:
a.
Many of the real world signals are physical in nature. The device used to convert these
physical parameters to corresponding electrical signals is called input transducer.
Examples of physical parameters are voice, speech, image etc. The input transducer used
to convert voice, speech or music signal or image to an electrical signal. Examples of
input transducers are microphone, camera etc. Usually, the output signal from the
transducer will be analog in nature. This analog signal is converted into digital form by
using analog to-digital converter. The analog- to-digital conversion consists of sampling,
quantizing and encoding. In the case of the output data of a computer, the signal is
available in digital form directly.
b. Source Encoder / Decoder
The aim of the source coding is to represent the digital signal efficiently with as much
less number of bits as possible. This will reduce the bandwidth required for transmission.
Ex: Huffman coding. The source decoder performs the inverse operation of source
encoder. ie. It is used to get back the data in its original representation.
c.
d. Modulator/ Demodulator
The Modulator converts the input digital information into an electrical waveform suitable
for transmission over the communication channel. Mainly there are three types of Digital
modulation techniques viz., Amplitude Shift Keying (ASK), Frequency Shift Keying
(FSK) and Phase Shift Keying (PSK).The extraction of the digital data from the received
signal is accomplished by the demodulator.
e.
Channel
The channels are either wired such as pair of wires, coaxial cable and optical fiber or
wireless (free space) such as radio channel, satellite channel or combination of any of
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these. The communication channels have only finite bandwidth and the signal often
suffers amplitude and phase distortion as it travels over the channel in addition to
attenuation of signal. It may also get corrupted by unwanted, unpredictable electrical
signals referred to as noise. The two important parameters used to measure the channel
characteristics are Signal to Noise power Ratio (SNR) and usable bandwidth.
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transmit bit 0, the phase of the sinusoid is shifted by 180o whereas to transmit bit 1, the
phase of the sinusoidal carrier is shifted by another 180o. Thus the carrier phase shift
represents the change in the state of the information. Fig 8.1.7 shows the binary PSK
representation.
Summary
1. Sampling theorem states that It is possible to reconstruct a band-limited analog
signal from periodic samples, as long as the sampling rate is at least twice the
highest frequency component of the signal.
2. Pulse modulation involves communication of information using a train of pulses
as carrier.
3. Some of analog pulse modulation techniques are: Pulse Amplitude Modulation
(PAM), Pulse Width Modulation (PWM) and Pulse Position Modulation (PPM).
4. Digital modulation is achieved by varying either the amplitude or frequency or
phase of the carrier in accordance with the digital data to be transmitted.
5. There are three basic types of digital modulation techniques. They are:
Amplitude Shift Keying (ASK)
Frequency Shift Keying (FSK)
Phase Shift Keying (PSK)
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Multiplexer: Combines the signals from different sources to transmit on the channel.
At the receiving end, a demultiplexer is used to separate the signals.
Multiple access: When two or more users share the same channel, each user has to
transmit the signal only at a specified time or using a specific frequency band.
Source coding: If the channel has a lower bandwidth than the input signal bandwidth,
the input signal has to be processed to reduce its bandwidth so that it can be
accommodated on the channel.
Error detection and correction: If the channel is noisy, the received data will have
errors. Detection, and if possible correction, of the errors has to be done at the
receiving end. This is done through a mechanism called channel coding.
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Different packets may take different amounts of time to reach the destination and the order of
arrival of packets may be different from the one that has been sent. The packets are collected
at the destination and reordered before it is delivered.
Example: Internet
9.1.3 Types of Communication Networks:
Different networks can be used for communication purposes.
a. Local Area Network(LAN)
A local area network is a network of computers in a localized area, such as in an
office or a school. All the computers are connected to each other through the LAN via
a hub or a switch.
b. Wide Area Network(WAN)
A wide-area network covers a large geographical area and usually consists of multiple
computer networks. The Internet is a WAN which relies on a large global network of
service providers who use routers, switches, modems and servers to provide
connectivity to people and organizations around the world. It is a network of
interconnected computers that carry data, media and web pages.
c. Metropolitan Area Network (MAN)
A metropolitan area network is a larger network that usually spans several buildings
in the same city or town. It is larger than a LAN but smaller than a WAN. A MAN is
typically owned and operated by a single entity such as a government body or large
corporation.
d. Public Switched Network
The public switched network is essentially the telephones' version of the Internet. It is
a network of public circuit-switched telephones. The network today is largely digital
and includes services for both cellular and landline phones.
e. Wireless Networks
Wireless networks provide information transmission and network connectivity to
devices without cables or wires. Some examples of a wireless network include
broadcast radio, which sends data over long geographical distances and is available to
anyone with a radio who knows the frequency. Wi-Fi is a wireless network for
computers, which can access the network remotely. Bluetooth, which connects with a
nearby mobile phone, is a shorter-range version of a wireless network, which supports
transmission of voice and data but only at a distance of a few feet from the
communication device with which it works.
f. Satellite Networks
Satellite networks come in a number of different varieties. Phone companies use
satellites for data and voice transmission to mobile phones on the ground. Some
satellite networks provide navigation information (e.g.: GPS-Global Positioning
System), military surveillance or weather data. Still others provide television
programming, radio broadcasts and even broadband Internet service.
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In the bus network topology, every workstation is connected to a main cable called the bus.
Therefore, in effect, each workstation is directly connected to every other workstation in the
network.
In the star network topology, there is a central computer or server to which all the
workstations are directly connected. Every workstation is indirectly connected to every other
through the central computer.
In the ring network topology, the workstations are connected in a closed loop configuration.
Adjacent pairs of workstations are directly connected. Other pairs of workstations are
ndirectly connected, with the data passing through one or more intermediate nodes.
If a Token Ring protocol is used in a star or ring topology, the signal travels in only one
direction, carried by a so-called token from node to node.
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The mesh network topology employs either of two schemes, called full mesh and partial
mesh. In the full mesh topology, each workstation is connected directly to each of the others.
In the partial mesh topology, some workstations are connected to all the others, and some are
connected only to those other nodes with which they exchange the most data.
The tree network topology uses two or more star networks connected together. The central
computers of the star networks are connected to a main bus. Thus, a tree network is a bus
network of star networks.
Logical (or signal) topology refers to the nature of the paths the signals follow from node to
node. In many instances, the logical topology is the same as the physical topology. But this is
not always the case.
9.1.5 Network protocols and Reference models: A protocol is a set of rules that governs
how two communicating parties are to interact. In the Web browsing example, the
HTTP(Hypertext transfer protocol) protocol specifies how the Web client and server are to
interact. Many protocols are required in computer communication to tackle different issues.
Few examples for protocols are
DNS Domain Name System
FTP File Transfer Protocol
HTTP- Hypertext Transfer Protocol
TCP and UDP- Transmission Control Protocol and User Datagram Protocol
SMTP- Simple Mail Transfer Protocol
IP and Ipv6- Internet Protocol and Internet Protocol version 6
Network protocols like HTTP, TCP/IP, and SMTP provide a foundation on which the
Internet is built on.
Self -test:
1.
2.
3.
4.
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Physical layer
Data link layer
Network layer
Transport layer
Session layer
Presentation layer
Application layer
Each layer performs a specific set of functions. Each protocol layer adds a header and passes
the packet to the layer below. Because the header is interpreted only by the corresponding
layer in the receiving system, the communication is called peer-to-peer communication. Peer
means a layer at the same level.
1. Physical layer: The physical layer specifies the physical interface between devices.
This layer describes the mechanical, electrical, functional, and procedural
characteristics of the interface.
An example of the physical layer is Electronic Industries Association (EIA) RS232,
which specifies the serial communication interface. A modem is connected to the PC
through the RS232 interface.
2. Data link layer: The data link layer's job is to activate the link, maintain the link for
data transfer and deactivate the link after the data transfer is complete. Error detection
and control, and flow control are also done by the data link layer.
3. Network Layer: The important function of the network layer is to relieve the higher
layers of the need to know anything about the underlying transmission and switching
technologies. The functions of the network layer are:
Switching and routing of packets
Management of multiple data links
Negotiating with the network for priority and destination address
4. Transport Layer: The transport layer can provide two types of services namely,
connection-oriented and connectionless. In connection-oriented service, a connection
is established between the two end systems before the transfer of data. The transport
layer functionality is to ensure that data is received error-free, packets are received in
sequence, and that there is no duplication of packets. The transport layer also has to
ensure that the required quality of service is maintained. Quality of service can be
specified in terms of bit error rate or delay. In connectionless service, the packets are
transported without any guarantee of their receipt at the other end
5. Session Layer: The session layer specifies the mechanism for controlling the
dialogue in the end systems. Session layer functionality is as follows:
Dialogue discipline: whether the communication should be full duplex or half
duplex.
Department of Electronics and Communication Engineering, M.I.T. Manipal.
Page 189
Summary
1. A communication network is the infrastructure that allows two or more computers to
communicate with each other.
2. Three types of switching are generally used in communication networks namely:
Circuit switching, Message switching and Packet Switching.
3. Some of the types of communication networks are LAN, WAN, MAN, satellite
networks, wireless networks etc.
4. The physical topology of a network is the actual geometric layout of workstations.
5. A protocol is a set of rules that governs how two communicating parties are to
interact.
6. Network protocols like HTTP, TCP/IP, and SMTP provide a foundation h of on which
the Internet is built on.
7. The ISO/OSI reference model is fundamental to computer communication because it
serves as a reference model for all protocol suites.
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Learning Outcomes:
At the end of this module, students will be able to:
1. Explain the concept of basic cellular mobile communication.
2. Explain the multiple access techniques for cellular system.
3. Draw and explain the architecture of GSM system.
4. Explain the role of base station subsystem (BSS) and mobile switching center
(MSC).
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.
Figure 10.1.1: An illustration of a cellular system
Mobile phone networks are divided into thousands of overlapping, individual geographic
areas or cells each with a base station. Each mobile communicates via radio with one or more
base stations. An illustration of mobile to mobile communication is as shown in the Figure
10.1.2.
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Each mobile contains a transceiver (transmitter and receiver), an antenna, and control
circuitry. The base stations consist of several transmitters and receivers, which
simultaneously handle full duplex communications and generally have towers that support
several transmitting and receiving antennas. The base station connects the simultaneous
mobile calls via telephone lines, microwave links, or fiber-optic cables to the switching
center. The switching center coordinates the activity of all of the base stations and connects
the entire cellular system to the public telephone network.
The channels used for transmission from the base station to the mobiles are called forward or
downlink channels, and the channels used for transmission from the mobiles to the base
station are called reverse or uplink channels. The two channels responsible for call initiation
and service request are the forward control channel and reverse control channel.
Once a call is in progress, the switching center adjusts the transmitted power of the mobile
(this process is called power control) and changes the channel of the mobile and base station
(handoff) to maintain call quality as the mobile moves in and out of range of a given base
station. A call from a user can be transferred from one base station to another during the call.
This process of transferring a call from one base station frequency to another is called
handoff.
When roaming users enter an area outside their home region, special procedures are required
to provide the cellular phone service. To automatically provide roaming service, a series of
interaction is required between the home network and the visited network, using the
telephone signaling system. When the roamer enters a new area, the roamer registers in the
area by using the setup channels.
10.1.2. Multiple Access Technology:
Generally a fixed amount of frequency spectrum is allocated to a cellular system by national
regulator (In India, the Department of Telecommunications (DoT) conducts auctions of
licenses for electromagnetic spectrum). Multiple access techniques are then deployed so that
many users can share the available spectrum in an efficient manner.
In 2010, 3G and 4G telecom spectrum were auctioned in a highly competitive bidding. The winners
were awarded spectrum in September, and Tata Docomo was the first private operator to launch 3G
services in India. The Government earned 677 billion from the 3G spectrum auction. While the
broad band wireless spectrum auction generated a revenue of 385 billion. The Government earned
total revenue of over 1062 billion from both auctions. The auction took place over 34 days and
consisted of 183 rounds of bidding. The five most expensive circles were Delhi, Mumbai,
Karnataka, Tamil Nadu and Andhra Pradesh. They accounted for 65.56% of the total bids. So the
spectrum is very scarce and valuable resource.
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Figure 10.1.3 illustrates the three basic multiple access methods used in mobile
communication.
In case of FDMA, users share the available spectrum in the frequency domain and each user
is allocated a part of the frequency band, on a demand basis.
In TDMA available spectrum is partitioned into narrow frequency bands (as in FDMA),
which in turn are divided into a number of time slots. An individual user is assigned a time
slot that permits access to the frequency channel for the duration of the time slot.
The CDMA system utilizes the spread spectrum technique, whereby a spreading code (called
a Pseudo-random Noise or PN code) is used to allow multiple users to share a block of
frequency spectrum.
Self- test:
1. How call set up takes place between two mobile subscribers?
2. Explain the need for cellular concept in mobile communication.
3. Explain frequency reuse concept in cellular systems.
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Base Station Subsystem (BSS): Base Station Subsystem is composed of two parts:
Base Transceiver Station (BTS)
Base Station Controller (BSC)
Base Transceiver Station (BTS): Houses the radio transceivers that define a cell and
handles radio-link protocols with the Mobile Station
Base Station Controller (BSC): The tasks performed by BSC are
Manages Resources for BTS
Handles call set up
Location update
Handover for each MS
Network subsystem (NSS): The NSS provides the link between the cellular network and the
public switched telephone network (PSTN). The NSS controls handoffs between cells in
different BSSs, authenticates users and validates their accounts, and includes functions for
enabling worldwide roaming of mobile users.
Mobile Switching Center (MSC):
The central component of the Network Subsystem
Handles billing activities
Handover management
Communication with HLR,VLR,MSCS
Controlling of connected BSCS
Department of Electronics and Communication Engineering, M.I.T. Manipal.
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Home Location Registers (HLR): The HLR stores information, both permanent and
temporary, about each of the subscribers that belongs to it. It is the most important database
Visitor Location Registers (VLR): The VLR maintains information about subscribers that are
currently physically in the region covered by the switching center.
Authentication Center (AuC): This database is used for authentication activities of the
system; for example, it holds the authentication and encryption keys for all the subscribers in
both the home and visitor location registers.
Equipment Identity Register (EIR): The EIR keeps track of the type of equipment that exits
at the mobile station. It also plays a role in security e.g., blocking calls from stolen mobile
stations and preventing use of the network by stations that have not been approved.
Summary
1. A cellular radio system provides a wireless connection to the public telephone
network for any user location within the radio range of the system.
2. Mobile phone networks are divided into thousands of overlapping, individual
geographic areas or cells each with a base station.
3. The channels used for transmission from the base station to the mobiles are called
forward or downlink channels, and the channels used for transmission from the
mobiles to the base station are called reverse or uplink channels.
4. A call from a user can be transferred from one base station to another during the
call. The process of transferring is called handoff.
5. The three basic multiple access methods are: Frequency division multiple access
(FDMA), Time division multiple access (TDMA), Code division multiple access
(CDMA).
6. Global System for Mobile Communications (GSM), is a standard developed by the
European Telecommunications Standards Institute (ETSI) to describe protocols for
second generation digital cellular networks used by mobile phones.
Exercise:
1.
2.
3.
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