An Tda937x Ps v1.0 (E)

APPLICATION NOTE
Application information for

TV processor + P + CC decoder
TDA937X PS N2
AN01045
Version 1.0
February 2002
Philips
Semiconductors
Philips Semiconductors
Version 1.0
TDA937X PS N2
TV-processor + P + CC
Application Note
AN01045
ABSTRACT
This report gives a description of the TDA937X PS N2 version, together with application aspects.
Purchase of Philips I Ccomponents conveys

2
a license under the I C patent to use the
2
components in the I C system, provided the
2
system conforms to the I C specifications
defined by Philips.
Philips Electronics N.V. 2002

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of
the copyright owner. The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use. Publication thereof does not convey nor
imply any license under patent- or other industrial or intellectual property rights.
Version 1.0
TDA937X PS N2
Application Note
AN01045
Application Note
Application information for TV Signal

processor & P & Closed Caption decoder
TDA 937X PS N2
AN01045
Author(s):
D. Allerton
L. Bakema
D. v.d. Brul
T. Bruton
G. Folmer
P.C.T.J. Laro
D. Siersema
E. Arnold
F. Giuliano
J. Liu
T. Lee
System Application, Mainstream T.V. Solutions

Consumer ICs Nijmegen,
The Netherlands
Keywords
Embedded micro-controller
OSD
Closed Caption, VPS
Alignment free IF-PLL, Sound PLL
Synchronisation H/V
Geometry on vertical and E-W
Switches and filters
PAL/NTSC decoder
Delay line
Continuous Cathode Calibration
2
IC
Date: February 2002

3
Version 1.0
TDA937X PS N2
Application Note
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Summary
This report gives a description of the application aspects of the TDA937X, a combination of TV signal
processor plus Closed caption decoder plus embedded microprocessor in one device.
Version 1.0
TDA937X PS N2
Application Note
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CONTENTS
INTRODUCTION...................................................................................................................................... 7
DEVICE INFORMATION ......................................................................................................................... 9
PINNING CONFIGURATION................................................................................................................. 11
DEVELOPMENT TOOLS ...................................................................................................................... 13
I C CONTROL VIDEO PROCESSOR PART......................................................................................... 17
5.1
5.2
6
APPLICATION INFORMATION............................................................................................................. 41
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
INPUT CONTROL BITS.................................................................................................................. 20

OUTPUT CONTROL BITS ............................................................................................................. 35
MICROPROCESSOR ..................................................................................................................... 45
IF PART .......................................................................................................................................... 47
FM SOUND ..................................................................................................................................... 50
QSS SOUND................................................................................................................................... 55
THE NARROW BAND PLL............................................................................................................. 57
FILTERS, SWITCHES AND COLOUR DECODER ........................................................................ 59
HORIZONTAL AND VERTICAL SYNC GEOMETRY ..................................................................... 63
GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION ........ 71
YUV / RGB PROCESSING AND CONTROL.................................................................................. 77
PICTURE IMPROVEMENT FEATURES ........................................................................................ 89
SUPPLY, GROUNDING AND DECOUPLING ................................................................................ 95
EMC LAYOUT............................................................................................................................... 107
ALIGNMENTS...................................................................................................................................... 109
7.1
7.2
7.3
7.4
TUNER AGC................................................................................................................................. 109

GEOMETRY.................................................................................................................................. 110
SCREEN VOLTAGE ALIGNMENT ............................................................................................... 114
COLOUR TEMPERATURE ALIGNMENT .................................................................................... 118
BLOCK DIAGRAM .............................................................................................................................. 120
INTERNAL PINNING ........................................................................................................................... 121
10 APPLICATION EXAMPLE ( DEMO-BOARD ) .................................................................................... 128

11 REFERENCES..................................................................................................................................... 129
12 INDEX .................................................................................................................................................. 131
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TDA937X PS N2
Application Note
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Version 1.0
TDA937X PS N2
1
Application Note
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INTRODUCTION
This report gives hardware/software application information concerning the TDA937x PS N2 family.
The TDA937x PS N2 series have both microprocessor and videoprocessor functions integrated in one
single chip and this device is intended for economy TV applications with 90 and 110 picture tubes.
Several features are implemented and control of TDA937x functions/features is carried out using the
2
supported I C bus and embedded software.
The microprocessor, which uses an enhanced 80c51-microprocessor core (12MHz clock) has OTP
ROM and built in RAM and it caters for:
- Closed Caption decoding (subtitle system in USA for people with hearing impediments).
- OSD generation
- Data Capture decoding of either Line 21 Data Services (525 Timing) or Euro-Caption (625
Timing)
The videoprocessor includes all the functions necessary for TV processing such as:
- IF video processing and sound (FM + QSS).
- Sync and geometry processing.
- PAL/NTSC colour decoder.
- RGB generation and processing of signals.
The device is encapsulated in a SDIP64 package (Shrink Dual In-line, 64 pin SOT274-1) and uses
both BIMOS and CMOS technologies.
The TDA937X family has been designed in order to have a low external component count for
application and a single layer PCB technology can be used.
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TDA937X PS N2
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TDA937X PS N2
Application Note
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DEVICE INFORMATION
The TDA937X family offers complete control and small signal video processing needed for TV applications
in one device; it includes a microprocessor and a videoprocessor, both being encapsulated in a SDIP64
(Shrink Dual In-line, 64 pins) package.
The microprocessor block diagram is shown in chapter 8.
A summary of the functions/features of the microprocessor is:
Combined 55K x 8 bit OTP Micro-controller Program ROM and 4.5K x 16 bit OTP Character ROM.
0.25K x 8 bit Main Data RAM ( Mov address space).
2.25K x 8 bit Auxiliary Data RAM (Movx address space).
Additional 16 bit Timer with 8 bit pre-scaler.
4 bit software A/D convert with 4 multiplexed inputs.
Low resolution PWMs for VST.
Byte level I2C up to 400KHz.
Watchdog Timer with 16-bit pre-scaler.
Three power saving modes : Stand-by, Idle and Power-Down.
13 I/O for SDIP64 via individual addressable controls.
Programmable micro-controller I/O for Push-Pull, Open Drain, Quasi-Bidirectional & highImpedance.
OSD graphics engine with up to 48 characters in width by 16 rows.
Closed Caption style organized as 34 characters by 16 rows.
256 displayable characters.
Globally selectable character matrix: 12 x 10, 12 x 13, 12 x 16 and 16 x 18 (h x v).
Globally selectable horizontal character spacing (up to 4 pixels).
Globally selectable vertical character spacing (up to 7 TV lines).
16 DRCS at up to 16 x 18 character matrix.
16 Foreground and 16 Background display colours selectable from a palette of 64.
Enhanced display features including shadowing, underlining, overlining, italics and smoothing.
Cursor Function.
Contrast Reduction.
The videoprocessor block diagram, which is subdivided into four subsections, is shown in chapter 8
A summary of the functions/features of the videoprocessor are:
IF video & sound:
2
Multi-standard vision IF circuit with alignment free PLL demodulator and IF frequency selection by I C.
2
Internal time constant for IF AGC circuit which can be selected via I C bus.
2
The FM PLL sound demodulator can be switched between 4.5/5.5/6.0/6.5 MHz frequencies with the I C
bus. At these frequencies extra internal selectivity can be selected under critical reception conditions by
2
selecting the internal bandpass filter with the I C bus.
Types available with FM demodulator or with QSS sound output as an input for a stereo decoder..
Filters/Switches & colour decoder:
CVBS switching between the CVBS from the front end (IF) and CVBS from SCART which can also be
used as an Y/C input.
2
Integrated chroma trap, chroma bandpass (switchable center frequency with I C) and cloche filters
Integrated luminance delay line with adjustable delay time.
Peaking function including depeaking and a variable positive/negative overshoot ratio .
Integrated baseband delay line (for NTSC systems can be applied as comb filter).
ACL implemented for deviating standards having large chroma/burst ratios (>3).
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ACL function switched via I C bus.

PAL/NTSC colour decoder with fully automatic colour search system including
LATAM colour decoding for PAL M and PAL N signals.
Only one 12MHz crystal required for all internal timing e.g. in the microprocessor, Close Caption
decoder, OSD and in the video processor IF frequency, sound carrier, colour decoder and horizontal
frequency
HV sync & geometry:
Horizontal synchronization with 2 control loops and alignment free horizontal oscillator
Vertical count down circuit
Vertical driver optimized for DC coupled vertical output stages
Horizontal and vertical geometry processing
Horizontal and vertical zoom function for 16 : 9 applications
Horizontal parallelogram and bow correction for large screen picture tubes
Low stress by innovative slow start/stop of HOUT implying a gradual build-up of the EHT and deflection
energy
Only 3.3V 65mA needed for start up which simplifies the stand-by power supply
YUV/RGB processing & control:

Picture improvement features as:
dynamic skin tone
black stretching
contrast reduction possibility during mixed mode of OSD signals
2
Linear RGB/YUV/ Y PB PR with fast blanking where the synchronisation on Y signals is possible via I C
bus.
CC or OSD signals are internally supplied from the CC decoder.
Independent adjustable colour temperature for high/low light calibration.
Beam current limiting, peak white limiting and soft clipper.
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TDA937X PS N2
PINNING CONFIGURATION
P1.3/T1
64 P1.2/INT0
P1.6/SCL
63 P1.1/T0
P1.7/SDA
62 P1.0/INT1
P2.0/TPWM
61 VDDP
P3.0/ADC0/PWM0 5
60 RESET
P3.1/ADC1/PWM1 6
59 XTALOUT
P3.2/ADC2/PWM2 7
58 XTALIN
P3.3/ADC3/PWM3 8
57 OSCGND
VSSC/P
56 VDDC
P0.5 10
55 VPE
P0.6 11
54 VDDA
53 BO
VSSA 12
I.C. 13
VP2 14
DECDIG 15
PH2LF 16
PH1LF 17
GND3 18
DECBG 19
TDA937X PS N2
LEADER
Application Note
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52 GO
51 RO
50 BLKIN
49 BCLIN
48 B2/UIN/PbIN
47 G2/YIN
46 R2/VIN/PrIN
45 INSSW2
AVL/EWD 20
VDRB 21
44 AUDOUT
VDRA 22
43 C
IFIN1 23
42 CVBS/Y
IFIN2 24
41 GND1
IREF 25
40 CVBS1
VSC 26
39 VP1
AGCOUT
27
38 IFVO/SVO
AUDEEM/SIFIN1 28
37 PLLIF
DECSDEM/SIFIN2 29
36 EHTO
35 AUDEXT/QSSO
GND2 30
SNDPLL/SIFAGC 31
34 FBISO
AVL/SNDIF/ 32
REFO
33 HOUT
Figure 1: Pinning configuration
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IC version
FM PLL version
N
Y
East-west Y/N
00
01/10/11
00
01/10/11
CMB1, 0 bits
AVL
EWD
Pin 20
AUDEEM
Pin 28
DECSDEM
Pin 29
SNDPLL
Pin 31
SNDIF
REFO
AVL/SNDIF
REFO
Pin 32
AUDEXT
Pin 35
Table 1: Pin functions for various modes of operation
QSS version
N
00
Y
01/10/11
00
AVL
01/10/11
EWD
SIFIN1
SIFIN2
SIFAGC
REFO
AUDEXT
QSSO
AUDEXT
QSSO
Note
1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF
input. This function is selected by means of SIF bit in subaddress 28H.
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Version 1.0
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Application Note
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DEVELOPMENT TOOLS
To develop with the TDA937XPS/N2 family, the tools, listed below, need to be
adapted/upgraded. To order the necessary upgrades, please contact your local marketing
representative.
Emulator
Depending on the emulator brand used, the following adaptations are necessary:
HITEX
Currently, Hitex can supply a probe, namely PxTDA93xx-N2, for the TDA935X/6X/8XPS/N2 family, which is
also suitable for emulating the TDA937XPS/N2 family,
as well. This probe includes all the adapters for the processor bond-outs (SAA5512) and video processor
bond-out. (KN10161 QSS/FM).
However, existing UOC-N1 customers can upgrade their system, as well, for emulating the
TDA937XPS/N2 devices, as described below.
The HITEX with the existing PXSAA55xx probe for emulation of the TDA935X/6X/8X N1 consists of the
following PCBs:
1. Main probe PCB, ref. 7313-903-0027-2 or ref. 7313-903-0027-3
2. QFP120 Daughter board PCB, ref. 7313-903-0033-2
3. UOC Interface board, ref. 7313-903-0007-2.
In order to emulate the TDA937XPS/N2 family devices, the above boards have to be replaced
as below:
1. Main probe PCB
2. QFP120 Daughter board
3. UOC interface board
ref. 7313-903-0027-3 (Only in case version is ref. 7313-903-0027-2)

ref. 7313-903-0264-1 (replaces ref. 7313-903-0033-2)
ref. 7313-903-0317-1 (replaces ref. 7313-903-0007-2)
The new Daughter board (ref. 7313-903-2641) plugs into the main probe PCB (ref. 7313-903-0027-3)
via an array of connectors, SK1...SK8. This board can accommodate the new processor bond-outs
(SAA5512).
The new UOC interface board can accommodate the new video processor bond-out. (KN10161
QSS/FM).
BL-MTS Systems Applications Group Southampton supplies the necessary processor, video
processor bond-outs for emulation and replacement boards.
The new set of boards supports the internal reset feature of the TDA937XPS/N2 family.
Before using the probe, a set of jumpers on the Daughter board needs to be set as described below:
J1: HI
J2: HI
J3: OPEN (not used)
J4: OPEN (not used)
A brochure with information about the new probe heads and bondouts is attached to this document.
More details can be found in the Application Note PxTDA93xx-N2 available at our Support area on the
Semiconductor Internet Site http://www.semiconductors.com.
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ASHLING ULTRA 51
Ashling announced that they would no longer support the existing CTS51 system. They offer full
support for the TDA937XPS/N2 with their new Ultra-51 Ashling system. The system is supplied
with and adapter (AD-SAA55L+) to use for accommodating the microprocessor bond-out.
An additional adapter, ref. 7313-903-03171, is needed for the video-processor bond-out and it can be
requested from BL-MTS Systems Applications Group Southampton.
Information about the new probe head can be found in the attached brochure.
Display Development Studio (DDS)
The DDS is needed to generate the proper character sets and the matching with the type number of
the device.
The new version DDS 2.2 supports the new UOCN2.
PAT/PROMT tool is out of date; it is recommended to use the new PROMPT tool, which is included
within DDS 2.2 .It can be downloaded from our Support area on the Semiconductor Internet Site
http://www.semiconductors.com.
This Support area is located at http://download.semiconductors.com/protected/video/.
To apply for access, please complete the electronic form located at our Support Area:
http://downloads.semiconductors.com/unregistered/
GTV development tool
GTV release 2.0 supports the TDA937XPS/N2 family. Older releases are not suitable for the
these devices.
Bench programmer
For programming the TDA937XPS/N2 the bench programmer must be a recent version. These
versions can be easily recognized because they have a blue PCB.
Some of older bench programmer versions (with green PCB) cannot be used with the TDA937XPS/N2
PS/N1 devices, until a FPGA(s) upgrade is implemented.
Please contact the BL-MTS Systems Applications Group Southampton for more details.
TV demoboard and WIC software
For evaluation, a TV demoboard plus the latest WIC software is available for the TDA937XPS/N2
version
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5
Application Note
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I C CONTROL VIDEO PROCESSOR PART

FUNCTION
Horizontal parallelogram
Horizontal Bow
Hue
Horizontal shift (HS)
EW width (EW) (1)
EW parabola/width (PW) (1)
EW upper corner parabola (1)
EW lower corner parabola (1)
EW trapezium (TC) (1)
Vertical slope (VS)
Vertical amplitude (VA)
S-correction (SC)
Vertical shift (VSH)
Vertical zoom (VX) (1)
Black level off-set R
Black level off-set G
White point R
White point G
White point B
Peaking
Luminance delay time
Brightness
Saturation
Contrast
AGC take-over
Volume control
Colour decoder 0
Colour decoder 1
AV-switch 0
AV-switch 1
Synchronisation 0
Synchronisation 1
Deflection
Vision IF 0
Vision IF 1
Sound 0
Control 0
Control 1
Sound 1
Features 0
Features 1
SUBADDR
(HEX)
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
D7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CM3
0
0
0
0
0
0
0
SIF
AGN
0
0
0
0
0
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CM2
0
0
0
HP2
0
AFN
IFB
0
SM1
IE2
0
0
0
BPB
D5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
0
A5
A5
A5
A5
A5
CM1
0
SVO
0
FOA
FSL
DFL
IFC
0
FMWS
RBL
VSD
ADX
0
RPO1
DATA BYTE
D4
D3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
0
YD3
A4
A3
A4
A3
A4
A3
A4
A3
A4
A3
CM0
MAT
0
0
CMB1
CMB0
0
0
FOB
POC
OSO
FORF
XDT
SBL
VSW
0
IFLH
0
0
SM0
AKB
CL3
SOY
0
0
0
0
DSK
RPO0
0
D2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
YD2
A2
A2
A2
A2
A2
MUS
PSNS
INA
0
STB
FORS
AVG
AFW
AGC1
0
CL2
YUV1
AVL(2)
0
0
D1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
YD1
A1
A1
A1
A1
A1
ACL
BPS
INB
0
VIM
DL
EVG
IFS
AGC0
FMB
CL1
YUV0
QSS
0
0
D0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
YD0
A0
A0
A0
A0
A0
CB
FCO
0
RGBL
VID
NCIN
HCO(1)
STM
FFI
FMA
CL0
HBL(1)
0
BKS
0
POR
Value
20
20
00
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
00
20
20
20
20
20
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Table 2: I2C input bits

NOTE:
1. These functions are only available in versions that have the East-West drive output.
2. The AVL function is only available in versions which have no East-West drive output or when the
subcarrier output is used for the connection of the AVL capacitor (via the bits CMB1, 0 in subaddress
22hex).
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TDA937X PS N2
FUNCTION
Output status bytes
SUBADDR
(HEX)
00
01
02
Application Note
AN01045
D7
POR
XPR
SUP
D6
IFI
NDF
X
D5
LOCK
FSI
X
DATA BYTE
D4
D3
SL
CD3
IVW
WBC
QSS
AFA
D2
CD2
HBC
AFB
D1
CD1
BCF
FMW
D0
CD0
IN2
FML
Table 3: I2C output bits

The TDA937X PS N2 uses an internal IC-bus to read and write all its functions:
8AHEX : A6 A5 A4 A3 A2 A1 A0 R/W:
8BHEX : A6 A5 A4 A3 A2 A1 A0 R/W:
Write slave address:

Read slave address:
10001010
10001011
For IC-bus write-transmissions the TDA937X PS N2 has automatic sub-address increment, so multiple
data bytes can be sent in one transmission.
Acknowledge
from slave
Start
Slave address
0 Ack
R/W
=
write
acknowledge
from slave
Sub address
Ack
first sub-address
= destination of
first data byte
acknowledge
from slave
Data Byte
Ack Stop
multiple data bytes,

each acknowledged
by slave
Reading the three status bytes is done without sub-addressing. After receiving the IC-bus read address,
the TDA937X PS N2 always starts with status byte 0.
No acknowledge
acknowledge
acknowledge
from master
from slave
from master
(just clock pulse)
Start
Slave address
1 Ack
R/W
=
read
Status byte 0
Ack
Status byte 2
Nack Stop
Read 1, 2 or 3 status bytes
IC-bus start-up procedure.

The TDA937X PS N2 has many alignment-free internal circuits that are calibrated with the frequency of the
reference Xtal oscillator. To ensure correct start-up after the 3.3 Volt is applied, a start-up routine is
available which should be included in the software to run as first block. We strongly advice to use this
routine to prevent problems with initialising
1. Write all sub addresses from 00HEX to 2EHEX. When STB is written 1, the horizontal out will begin with
slow start when register 2EHEX is written, else the video processor will remain in stand-by.
2. Keep reading I2C-bus status bytes till SUP = 1 (+ 8 Volt present)
Note: When the +8 Volt is supplied via the EHT flyback transformer, this has only sense when the device
is set in operational mode (STB = 1)
Before the horizontal drive output can become active, all sub-address bytes 00HEX to 2EHEX must be loaded.
Registers or register bits, not available or defined in certain versions, must be loaded with zeros for (future)
compatibility. Only when the +8 Volt supply is present, the oscillator is calibrated. Non-successful calibration
forces SUP to 0 irrespective the + 8 Volt supply to indicate a failure.
Each time before the sub-address bytes are refreshed, the status bytes must be read. If POR=1 then the
start-up routine and step 1, 2 must be executed to restart the IC. Not following this procedure may result in
undesired conditions after power-up or a power dip (e.g. incorrect horizontal line frequency).
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Software monitoring or external I2C bus control is possible via the SCL, SDA pins at pins 2 and 3
respectively.
2
Software monitoring (I C data) between microprocessor and videoprocessor can be done by programming
ports 1.6/1.7 (SCL, SDA) as open drain and having pull up resistors on these pins. When programming the
2
2
TXT21.1 (I C Port0) then the I C data can be enabled/disabled on these pins.
2
Monitoring the I C data is only possible after the software initialisation is completed therefore when the
Drv_InitUOC() function in the UOC BOOT Library has been called.
External I2C bus control (e.g. with WIC software) of a programmed device is possible via the SCL, SDA
pins only when communication between microprocessor and videoprocessor is disabled by customer
software.
Similarly, customer software can be implemented whereby required registers for alignment etc. can be
changed (e.g. Factory Service Mode).
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Application Note
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INPUT CONTROL BITS
Reg 06 D0..5
HP
HOR. PARALLELOGRAM
CORRECTION
Corrects when the vertical lines are not orthogonal on the horizontal lines.
Reg 07 D0..5
HB
HOR. BOW CORRECTION
Corrects when the top and bottom of the vertical lines are slightly bent from the middle to left or right. This
can be used with black flatline cathode ray tubes to have optimum adjustment of vertical lines.
Reg 08 D0..5
HUE
HUE
The hue control is active when the NTSC colour system is received
Reg 09 D0..5
HS
HORIZONTAL SHIFT
Adjusts the horizontal position of the picture on the screen.
Reg 0A D0..5
EW
E-W WIDTH
Adjusts the picture width. When all higher order terms (BCP, PW, TC, UCP) are aligned, the geometry
corrections will remain correct when changing the EW register for horizontal zoom.
Reg 0B D0..5
PW
E-W PARABOLA WIDTH
UCP
E-W UPPER CORNER

PARABOLA
Adjusts the parabola correction.
Reg 0C D0..5
Adjusts the upper curve of the vertical lines.

Set UCP in neutral position before starting alignment.
Reg 0D D0..5
BCP
E-W BOTTOM CORNER

PARABOLA
Adjusts the bottom curve of the vertical lines. Set BCP in neutral position before starting alignment.
Reg 0E D0..5
TC
E-W TRAPEZIUM COR.
Adjusts the position of the vertical lines at the sides: can be bend inwards or outwards. The vertical lines
remain straight. Set in neutral position before starting alignment.
20
Version 1.0
TDA937X PS N2
Reg 0F D0..5
Application Note
AN01045
VS
VERTICAL SLOPE
Adjusts the vertical slope. This alignment is meant to compensate for spread on the value of the external
sawtooth capacitor (major) and spread on the internal reference current source (minor). This is the first
vertical alignment to execute in order to adjust the internal levels to exact nominal value. These nominal
values are important to ensure that all derived correction waveforms (vertical S and horizontal geo) are
correct. Use SBL (service blanking) for correct alignment. See also chapter geometry alignments.
Reg 10 D0..5
VA
VERTICAL AMPLITUDE
Adjusts vertical amplitude. Adjustment does affect all horizontal geometry corrections and also the vertical
S-correction. Before using VA, first align VS and VSH. Do not use for vertical zoom because overscan is not
blanked!
Reg 11 D0..5
SC
VERTICAL S-CORRECTION
VSH
VERTICAL SHIFT
Adjusts the vertical S-correction.
Reg 12 D0..5
Adjusts the vertical shift. This alignment is meant to compensate for vertical offsets like DC offset vertical
amplifier (major), mechanical offset picture tube gun (major) and internal offsets (minor). In this way, exact
landing in the vertical middle of the screen is ensured when the vertical deflection current outputs are zero.
This alignment must be carried out after alignment of VS and is important to ensure that all derived
correction waveforms (vertical S and horizontal geo) are correct. See also chapter geometry alignments.
Reg 13 D0..5
VX
VERTICAL ZOOM/EXPAND
This bit can be used to shrink the vertical amplitude (compressed 16:9 format on 4:3 tube) or expand the
vertical amplitude (4:3 format on 16:9 tube). The vertical amplitude adjustment is 1 % per step, the neutral
position is chosen such (19HEX, 25DEC) that VX = 00 gives 25 % picture height reduction (75% picture
height), suitable for displaying compressed 16:9 format on 4:3 tube. When zooming larger than 100 %,
vertical overscan larger than 106 % will be blanked to prevent picture tube damage. It is important to set VX
in neutral position before starting alignment!
Reg 14 D0..5
BLOR
BLK LEVEL OFFSET RED
Reg 15 D0..5
BLOG
BLK LEVEL OFFSET GREEN
Adjustment of an offset in the red and /or green channel to realise another colour temperature setting for
low lights as for high lights.
Reg 16..18 D0..5
WPR, G, B
WHITE POINT RGB
Adjustment of the white point setting for colour temperature at high light in order to compensate for the
phosphor efficiencies of different CRTs.
21
Version 1.0
TDA937X PS N2
Reg 19 D0..5
Application Note
AN01045
PEAK
PEAKING
The peaking on the Y signal can be adjusted with this 6 bit register
Reg 1B D0..5
BRI
BRIGHTNESS
Reg 1C D0..5
SAT
SATURATION
Reg 1D D0..5
CON
CONTRAST
Reg 1A D0..3
YD0..3
Y-DELAY
Adjusts the Y delay in order to achieve correct Y and chroma timing
Reg 1E D5..0
AGC TAKE OVER
AGC TAKE OVER POINT
Reg 1F D5..0
VOLUME CONTROL
VOLUME CONTROL
Reg 20 D0
CB
CHROMA BANDPASS
CENTRE FREQUENCY
To compensate for the roll-off at higher frequency in the SAW filter / IF part, the centre frequency of the
chroma bandpass can be shifted upwards.
0 = Centre frequency at Fsc (chroma subcarrier frequency)
1 = Centre frequency at 1.1 x Fsc (in principle used for internal mode only)
Reg 20 D1
ACL
AUTOMATIC COLOUR
LIMITING
For signals with very large chroma/burst ratio this ACL can be enabled to maintain correct colour saturation.
ACL has no influence on colour sensitivity (e.g. colour loss in VCR feature mode). It is not recommended to
use the ACL function when SECAM is identified.
0 = ACL function not enabled (for standard burst/chroma transmissions)
1 = ACL function enabled (for non-standard burst/chroma ratio)
Reg 20 D2
MUS
MATRIX USA
Selects between the two built-in NTSC matrices.

0 = Japanese NTSC matrix
1 = USA NTSC matrix
Reg 20 D3
MAT
MATRIX SELECTION
Forces PAL matrix, even when NTSC is detected.

When RGB-2 input is used, PAL matrix should be selected for correct colour reproduction (MAT = 0)
because the RGB -> YUV conversion is complementary to the PAL matrix.
0 = matrix adapted to standard (PAL matrix or by MUS selected NTSC matrix)
1 = PAL matrix
22
Version 1.0
TDA937X PS N2
Reg 20 D4..7
Application Note
AN01045
CM0..3
COLOUR DECODER MODE
These bits select one of the automatic modes or forces to one of the standards.
CM3
CM2
CM1
CM0
Colour decoder mode
0
0
0
0
PAL/NTSC
0
0
0
1
Spare
0
0
1
0
PAL
0
0
1
1
NTSC
0
1
0
0
Spare
0
1
0
1
PAL/NTSC (auto)
0
1
1
0
PAL
0
1
1
1
NTSC
1
0
0
0
PAL/NTSC(auto)
1
0
0
1
PAL/NTSC(auto)
1
0
1
0
PAL
1
0
1
1
NTSC
1
1
0
0
PAL/NTSC (auto tri-normal)
1
1
0
1
PAL/NTSC (auto)
1
1
1
0
PAL
1
1
1
1
NTSC
Table 4: Automatic colour standard manager settings
Subcarr. freq.
A
A
A
B
B
B
ABCD
C
C
C
BCD
D
D
D
Frequencies:
- A: 4.433619 MHz
- B: 3.582056 MHz (PAL N)
- C: 3.575611 MHz (PAL M)
- D: 3.579545 MHz (NTSC M)
Reg 21 D0
FCO
FORCED COLOUR ON
With this bit the colour killer function can be disabled to ensure maximum colour sensitivity under abnormal
conditions e.g. VCR trick modes. Only active when one single colour system is forced.
0 = normal colour killer function
1 = no colour killing (in forced single colour system mode only)
Reg 21 D1
BPS
BYPASS CHROMA DELAY

LINE
When active then the U, V signals bypass the built-in base band chroma delay line (e.g. for NTSC or
PALplus) and are internally amplified by 6 dB to correct the levels.
0 = Baseband chroma delay line active
1 = Bypass baseband chroma delay line
Reg 21 D2
PSNS
PAL SENSITIVITY NOISY

SIGNALS
With this bit the colour killer sensitivity level for PAL can be increased for noisy signal conditions. This
feature is intended for the ASIAN countries.
0 = Normal PAL sensitivity, killing level typical 26 dBuV
1 = Increased PAL sensitivity, killing level typical 21 dBuV
23
Version 1.0
TDA937X PS N2
Reg 22 D0, 1
Application Note
AN01045
INA, INB
INPUT SELECTION
Selects CVBS/YC video inputs.

INA
INB Selected signal
0
0
CVBS1
0
1
CVBS2/Y
1
1
Y/C
Table 5: Video input selection
Reg 22 D3, 4
CMB0, 1
COMB PIN FUNCTION
CMB1 CMB0
Function
0
0
AVL / SNIF active (depends on SIF bit)
0
1
Output voltage 2.3 Volt + subcarrier
1
0
Output voltage 0 Volt
1
1
Output voltage 4.5 volt
Table 6: Comb filter pin function selection
Reg 22 D5
SVO
SELECTED VIDEO OUT
With this bit it is possible to realise a monitor out function on pin 38.
When SVO = 0, pin 38 delivers the CVBSINT out (including sound carrier) from IF.
When SVO = 1, the signal, selected by the CVBS switch is routed to pin 38. At the same time, inside the IF
the CVBSINT out is muted by forcing VSW = 1.
To realise the monitor out function, both SVO and INA, B must be used.
SVO
INA
INB Signal on pin 38
Level pk - pk
2)
0
X
X
CVBSINT out + intercarrier sound from IF
2.5 V
3)
1
0
0
2.0 V
Internal CVBS pin 40 (not CVBSINT from IF!!)
1
0
1
External CVBS pin 42
2.0 V
1
1
0
Y (pin 42) + C (pin 43)
2.0 V
Table 7: Selected video out options and corresponding video output levels
1)
1)
The level difference is related to technical differences between IF output and needed headroom in the
CVBS switch block.
2)
Intercarrier sound only in case of mono FM versions
3)
Note that in this condition CVBSINT out from IF is muted (VSW is forced to 1 for SVO = 1).
When in this condition another CVBS signal (e.g. from a satellite tuner) is fed to the internal CVBS input pin
40, this signal will be available on pin 38.
To have CVBSINT out from IF available on pin 38, SVO must be set to 0!!
24
Version 1.0
TDA937X PS N2
Reg 23 D0
Application Note
AN01045
RGBL
RGB OUTPUTS LOW
When this bit is set high, the RGB outputs are below 1.5V. This can be applied at start-up and switch-off for
picture blanking.
0 = normal operation
1 = RGB outputs blanked, black current loop disabled.
Reg 24 D0
VID
VIDEO IDENT COUPLING
With this bit it is possible to activate a coupling between video ident (IFI) and PHI-1 loop. If this coupling is
active and no video is present (IFI = 0), the PHI-1 loop is switched to very slow. This assures a stable OSD
display under noisy conditions e.g. during search tuning or when no antenna input is connected (tuner
noise). 0 = Video ident (IFI) switches PHI-1 loop on/off
1 = No influence of the video ident (IFI) on the PHI-1 loop
Reg 24 D1
VIM
VIDEO IDENT MODE
The IF ident circuit (output IFI) can be connected to the internal CVBS input (CVBSINT) or after the input
selection switch to the selected video input for display. (see also VID reg 24 D0)
0 = Video ident circuit coupled to CVBS1INT
1 = Video ident coupled to selected CVBS or Y/C (see INA, INB)
Reg 24 D2
STB
STAND BY
When set to 1, the horizontal drive is initialised via slow start. Note that after power-up the horizontal drive
2
only will be released when POR = 0 and all I C registers are written. It is possible to set STB to 1 when only
the 3.3 Volt supply is present. In this way, the horizontal drive will be initialised via slow start and the + 8 Volt
supply can be derived from the flyback transformer. When STB is set to 0, the horizontal drive is stopped
via slow stop and the RGB outputs are set for 1 mA discharge current of the picture tube (measured via the
black current loop). When no picture tube discharge via RGB drive is needed (e.g. applications with EHT
bleeder) it is possible to force black switch-off by setting RBL = 1 together with STB = 0
0 = device in stand-by
1 = device operational
Reg 24 D3
POC
PHI ONE CONTROL
When this bit is switched to high, the PHI-1 loop is switched off completely.
In this mode very stable OSD or TEXT can be displayed, independent of the selected source. This is useful
for e.g. installation menus, blue mute, ea. It is also useful to measure the free running frequency using in
this condition.
When forcing POC = 1, immediately SL is forced 0. This has the following consequences:
- AFC information is disabled
- Vertical divider switches immediately to mode, set by FORF/FORS
- SL cannot be used to detect a valid CVBS signal on the selected input, IFI can be used for this purpose
For stable OSD during search tuning, it is better to use VID in stead of POC, see below:
0 = Synchronisation active
1 = Synchronisation not active
25
Version 1.0
TDA937X PS N2
Reg 24 D4, 5
Application Note
AN01045
FOA, FOB
FORCED PHI ONE TIME

CONSTANT
These two bits determine the speed of the phi-1-loop. It can be forced to slow and fast or set it in the
automatic mode. In auto mode a noise detector circuit can switch to slow time constant, when the signal
has too much noise.
FOA
FOB PHI 1 loop mode
1)
0
0
Auto, PHI-1 gating in slow mode
0
1
Slow, always gating (only for test purposes.)
1
0
Slow/fast depends on noise detector, always gating
1
1
Fast, no gating
Table 8: PHI-1 loop speed settings
Note:
1)
Not suitable for weak video recorder signals, because of active ph-1 gating in slow mode. Use FOA,
FOB=1,1 instead.
Suggested use of these bits:

Normal off-air reception conditions or cable:
- Use FOA/FOB = 0 0 for program numbers, VCR reception via antenna possible
- Use FOA/FOB = 1 1 for external input (VCR, DVD)
Difficult off-air reception conditions (Weak signal and/or interference):
- Use FOA/FOB = 1 0 for program nr. (optimal off-air reception due to gating)
- Use FOA/FOB = 1 1 for special program nr. (program 0) for VCR reception via antenna
- Use FOA/FOB = 1 1 for external input (VCR, DVD)
Reg 24 D6
HP2
HORIZONTAL REFERENCE
OSD FROM PHI-2
Determines where the horizontal reference for OSD positioning is taken.

0 = Ref. from PHI-1 (needed when HB and HP (see geo) are used)
1 = Ref. from PHI-2 (For problems with OSD, no HB, HP possible)
Reg 25 D0
NCIN
NO VERTICAL
COINCIDENCE
Vertical divider mode: This forces the vertical divider immediately to the search window, to speed up vertical
catching at channel change. It saves the time for the vertical divider to switch back from standard mode to
narrow window and from narrow window to search window, which takes at least 6 fields.
For optimal performance, NCIN should be set back to 0 when SL becomes 1 (sync lock, indicating a valid
input signal is detected) after forcing the vertical divider to the search window.
0 = Normal operation of the vertical divider
1 = Vertical divider switched to search window
Reg 25 D1
DL
DE-INTERLACE
0 = Interlace
1 = De-interlace
26
Version 1.0
TDA937X PS N2
Reg 25 D2, 3
Application Note
AN01045
FORS/FORF
FORCED FIELD
FREQUENCY
This forces the vertical divider in a 60 Hz mode or automatic. In auto mode it can be given a preference for
50 or 60 Hz (useful for multi-system situations when video signals are only 50 or 60 Hz) or to keep the last
detected field frequency.
FORF FORS Vertical frequency
0
0
Auto, 60 Hz if not locked
1)
0
1
60 Hz forced
2)
1
0
Auto, keep last detected frequency
1
1
Auto, 50 Hz if not locked
Table 9: Vertical frequency selection options
Note:
60 Hz is immediately forced after writing FORF, FORS, so when a 50 Hz signal is present, it will start
rolling.
2)
This mode is useful for areas where both 50 and 60 Hz signals can be received but due to bad reception
condition the signal can be lost for a short moment. In that case, vertical catching is fast and screen
disturbance remains limited, because the vertical divider does not change the vertical frequency.
1)
Reg 25 D4
OSO
OVERSCAN SWITCH OFF
Enable switch-off in vertical overscan. When switching to stand-by, the vertical deflection is kept in overscan
position at the top of the screen while during switch-off the picture tube is discharged with a fixed current so
the white drive is less visible
0 = Switch-off undefined
1 = Enable switch-off in vertical overscan function
Reg 25 D5
FSL
FIXED VERTICAL SLICING

LEVEL
Forces the slicing level during vertical synchronisation to 60 % amplitude of the sync pulse (measured from
black level). Can solve problems with decoders, which insert a wrong and varying black level during vertical
synchronisation.
Normal, the slicing level during vertical (measured from black level) is 35% at strong signal and 60% at
noisy signals (S/N < 20 dB), switched by the built-in noise detector.
0 = Automatic vertical slicing level
1 = Vertical slicing level fixed to 60% of sync amplitude
Reg 26 D0
HCO
HOR. COMPENSATION
EHT tracking mode. Selects to modulate only vertical or vertical and East-West with the voltage on pin 36.
EHT tracking compensates picture size variations due to beam current variation. HCO = 0 is useful when
East-West and vertical require different gain for the compensation. Vertical compensation can then be done
via the IC, while the East/West compensation is realised outside the IC with a different gain.
0 = EHT tracking only on vertical
1 = EHT tracking on both vertical and East-West
27
Version 1.0
TDA937X PS N2
Reg 26 D1
Application Note
AN01045
EVG
ENABLE VERTICAL GUARD
With this bit set high, a vertical guard failure will immediately blank RGBOUT to avoid damage to the picture
tube. To use this function, a vertical guard pulse has to be connected to pin 50 (BLKLIN / Vertical guard).
When no vertical guard pulse is connected to pin 50, EVG must be set to zero to prevent unwanted blanking
of RGBOUT.
0 = Only vertical guard detection (output bit NDF)
1 = Detection (output bit NDF) and protection by blanking RGBOUT
Reg 26 D2
AVG
ADJUSTMENT VG2
VOLTAGE
When this bit is set high, the vertical deflection remains running and a black bar is visible at the top of the
screen. The beam current measurement is done during the black bar.
The AVG bit can be used for Vg2 alignment.
0 = Normal operation
1 = Vg2 adjustment (WBC and HBC bits in output byte 01 can be read)
Readout of the WBC and HBC bits via OSD in the lower half of the screen can also be used.
Reg 26 D3
SBL
SERVICE BLANKING
This bit blanks the bottom half of the picture, starting exactly in the middle of the vertical scan (deflection
currents are zero). This bit is intended to align the vertical parameter VS in order to compensate for
component tolerances. See also the chapter about geometry alignment.
0 = No service blanking
1 = Service blanking active
Reg 26 D4
XDT
X-RAY DETECTION
This bit selects whether at triggering of the X-ray protection (voltage on pin 36 higher than 3.9 Volt) besides
setting XPR = 1 the device switches automatically off via the slow stop procedure with RGB drive for picture
tube discharge or that only the XPR bit is set and latched.
0 = XPR + automatic switch-off
1 = XPR only
Reg 26 D5
DFL
DISABLE FLASH PROTECT.
The flash protection function on the PHI-2 pin 16 can be disabled using this bit. In this way, unwanted
switch-off from H-out by triggering due to disturbance can be prevented when this function is not used. This
increases the robustness (H-out remains running) under conditions like ESD, flash, etc. at the cost of higher
stress for line transistor etc.
0 = Flash protection enabled
1 = Flash protection disabled
28
Version 1.0
TDA937X PS N2
Reg 26 D6
Application Note
AN01045
AFN
AFC NOT ACTIVE
The AFC information is updated every vertical retrace. Under weak signal conditions, this updating can
cause some disturbance of the AM sound output. By setting AFN = 1 the AFC updating can be disabled to
minimise the disturbance. Advice for use:
- When a PLL tuner is used and the transmitter is stable, switch-off the AFC when receiving AM sound.
- When transmitter drift is expected, enable very short the AFC once every five minutes (two fields is
enough) to retune
0 = AFC normal active, updated every vertical retrace
1 = AFC circuit switched off
Reg 27 D0
STM
SEARCH TUNING MODE
Can make the coincidence detector less sensitive, to avoid that search tuning systems stop at very weak
signals (output bit SL).
1 = Reduced dynamic sensitivity of coincidence detector (approx. 5 dB)
Note: this function is effective in static signal conditions
Reg 27 D1
IFS
IF SENSITIVITY
When switched to an external source, the cross talk of noise on the internal signal to the external signal can
be reduced. This function is mainly intended for no-antenna input conditions.
0 = Normal sensitivity
1 = Maximum gain reduced by 20 dB (sensitivity in practice 12dB less)
Reg 27 D2
AFW
AFC WINDOW
AFC window around IF centre frequency: (to optimise search-tuning speed, see also output bits AFA and
AFB).
0 = Nominal window, about 100 kHz wide
1 = Enlarged window, about 300 kHz wide
Reg 27 D4
VSW
VIDEO MUTE SWITCH
When this bit is set to high, it is possible to use the internal CVBS input pin 40 (CVBS1INT) to supply an
external CVBS signal.
1 = IF video signal switched off (pin 27 and 38 are forced to ground level)
Reg 27 D5..7
IFB, IFC
FREQUENCY SELECTION
IFB
IFC
IF frequency
0
0
58.75 MHz
0
1
45.75 MHz
1
0
38.90 MHz
1
1
38.00 MHz
Table 10: IF frequency options
These frequencies are suitable for all market areas.
Any adaptation on frequency response should be done via the SAW filter.
29
Version 1.0
TDA937X PS N2
Reg 28 D0
Application Note
AN01045
FFI
FAST FILTER IFPLL
For RF-transmitter input signals with large phase modulation. (Not suitable for overmodulation, that requires
a slow filter)
0= normal time constant for standard transmitter signals
1= fast time constant for special market areas
The function can be used for both positive and negative modulated signals.
The standard loopfilter of 390E/100nF is recommended for both settings of FFI.
Use FFI = 1 only:
- For TV sets for special market areas. Set FFI = 1 during IC-initialisation
- After sale service. Set FFI = 1 via service mode in case of specific field problems.
See also application info on the IF-PLL loopfilter pin 37 in the IF Chapter.
Reg 28 D1, 2
AGC0, 1
AGC TIME CONSTANT
With previous IC versions an external IF-AGC capacitor was used. The standard value then was 2.2uF that
is now equivalent to the norm mode, see table on next page.
The AGC speed can be adjusted with AGC1, AGC0 for:
AGC1, 0
AGC speed
00
01
0.7 x norm
Norm
10
3 x norm
11
6 x norm
Equivalent AGC
capacitor
3.1uF
2.2uF
Function
Slow AGC action, reserved if required in the field
Standard recommended setting, optimal for both
positive and negative modulation
Faster AGC for negative modulation as to
improve airplane flutter performance
Fastest AGC for negative modulation as to
improve airplane flutter performance
Table 11: AGC speed settings

Reg 28 D4
IFLH
IF LOCK HOLD
Special bit for AV mode. Prevents IF video disturbance in case LOCK becomes zero at high modulation
depth. With IFLH its possible to make the IF-PLL calibration under control of IFI and not of LOCK anymore.
0 = standard, auto calibration under control of LOCK
1 = calibration under software control, see below.
Recommended:
If VIM = 0 than define IFLH := IFI.
If VIM = 1 and in STB mode set VIM=0, so than IFLH := IFI which is same as above
If VIM = 1 and in AV mode: set IFLH=1 for no calibration at all. The IC automatically calibrates after poweron or after change of IFB and IFC.
Some risk: after a flash the PLL might need re-calibration as to avoid PLL-out lock. This re-calibration will
not occur unless also a power on reset is active.
Reg 28 D7
SIF
SOUND CARRIER IF INPUT
0 = No SIF input, pin can be used for combfilter or AVL

1 = SIF input/output available when CMB0/1 = 00 This allows insertion of external sound pass
filters, also separate SIF signal from a other source can be applied.
30
Version 1.0
TDA937X PS N2
Reg 29 D0..2
Application Note
AN01045
FMB, FMA
FM SOUND CARRIER
SELECTION
FMB FMA Frequency

0
0
5.5 MHz
0
1
6.0 MHz
1
0
4.5 MHz
1
1
6.5 MHz
Table 12: Sound carrier selection
Reg 29 D3, 6
SM0, 1
SOUND MUTE
SM1 SM0 Mute at de-emphasis pin 28

0
1
Sound enhancer ( digital acquisition pulse limiter )
1
0
Mute on
1
1
Mute off
Table 13: Sound mute options
The sound enhance option improves the sound noise behaviour under weak signal conditions. The
acquisition pulses are real time automatically muted. Recommended setting:
01 for no mute condition (when e.g. SL=1 and IFI = 1)
10 for mute condition (when e.g. SL = 0 or IFI = 0)
Note: Mute on (SM1, 0 10) sets AVL (if present) in high gain mode (15dB) for fast settling time during
channel switching.
Reg 29 D5
FMWS
FM SEARCH WINDOW
WIDTH
0 = Standard acquisition window for narrow band PLL (+ and -225kHz)

1 = Wide acquisition window for narrow band PLL (+ and -450kHz) for signals with large FM swing.
The wide window setting allows more overmodulation of the soundcarrier with FM signals.
Reg 29 D7
AGN
GAIN FM DEMODULATOR
Enables +6dB extra gain in the FM demodulator. To be used for 25kHz deviation NTSC video standard or
for specific customer needs.
0 = normal operation
1 = gain + 6dB
Note: THD figures are higher in +6dB condition.
31
Version 1.0
TDA937X PS N2
Reg 2A D0..3
Application Note
AN01045
CL0..3
CATHODE DRIVE LEVEL
This can be used to adapt the black/white drive of the RGB outputs to match the required drive level for the
picture tube.
The table gives approximated values.
CL3 CL2 CL1 CL0
Variation Cathode Drive Level
0
0
0
0
50 VBL-WH
1
0
0
0
74 VBL-WH
1
1
1
1
95 VBL-WH
Table 14: Cathode drive level
Conditions:
- Nominal CVBS input signal (1 V pk-pk at CVBS input 40 or 42)
- Nominal settings for contrast, WPA and no peaking
- Black stretch switched off
- Gain of output stage such that no clipping occurs
- Beam current limiting not active
- Tolerance on given values: +/- 3 V.
Reg 2A D4
AKB
AUTO KINE BIASING
With this bit, the automatic black current stabilisation loop can be switched off. This can be used for LCD
application and other applications without picture tubes.
0 = Automatic black-current stabilisation (ABS) loop enabled
1 = ABS loop disabled (suitable for LCD applications)
Reg 2A D5
RBL
RGB BLANKING
Controls blanking of the RGB outputs. Can be used to keep the picture black at start-up of the set until the
CCC loop is stabilised and the cathode emission is high enough to display a decent picture.
Setting RBL = 1 before switching to Stand-By prevents the RGB outputs going high and discharging the
picture tube with a white flash.
Can also be used for blanking RGB outputs when black current loop is disabled (AKB = 1) for LCD
applications.
0 = Normal picture visible
1 = RGBOUT (pins 51, 52, 53) blanked
Reg 2A D6
IE2
RGB INSERTION ENABLE

(FAST BLANKING.)
Enable fast blanking (pin 45) of YUV/RGB-2 input.

0 = Second fast blanking disabled
1 = Normal fast blanking function
Reg 2B D0
HBL
HOR. BLANKING MODE
Widens the horizontal blanking for well defined edges using underscan (e.g displaying 4:3 picture on 16:9
picture tube)
0 = Normal horizontal blanking, related to horizontal flyback pulse width
1 = Wider blanking (coupled to PHI-1)
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Reg 2B D1
Application Note
AN01045
YUV0, 1
RGB/YUV INPUT SELECTION

FOR PIN 46, 47, 48
YUV1 YUV0 Mode

0
0
RGB input activated
0
1
Spare
1
0
YUV activated
1
1
YPbPr
Table 15: RGB/YUV input selection modes
Note: For the RGB input the synchronisation has to be fed to CVBS on pin 42.
Reg 2B D4
SOY
SYNC ON Y
Reg 2B D5
VSD
VERTICAL SCAN
DISABLE
To be used for Vg2 alignment. Setting the bit =1 sets the vertical deflection to zero (line in the middle of the
screen).
The black level can be adjusted via the brightness control to the required DC level so that the correct cut-off
levels can be made at the CRT cathodes.
The Vg2 can then be adjusted so that a visible line is just shown.
For more accurate Vg2 alignment the beam current can be set to 12-20 A using the read-out bits HBC
(above / below) and WBC (beam current between 12-20 A).
These bits are only valid when VSD = 1.
0 = Normal vertical deflection
1 = Vg2 alignment mode, No vertical deflection, HBC and WBC (valid for black levels >2.5V at the
RGB outputs)
Reg 2C D1
QSS
MODE QSS AMPLIFIER
Switches the QSS amplifier on and off

0 = QSS amp not active
1 = QSS amp active
Reg 2C D2
AVL
AUTOMATIC VOLUME
LEVELING
0 = AVL not active

1 = AVL active and regulates high audio levels as e.g. from TV commercials
Reg 2C D5
ADX
AUDIO EXTERN
Switch between internal and external sound

ADX
Audio selection
0
Internal audio signal
1
External audio signal
Table 16 Audio selection options
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Reg 2D D0
Application Note
AN01045
BKS
BLACK STRETCH
This function stretches offsets in black of non-standard signals to black level

0 = Black stretch off
1 = Black stretch on (to be switched off for WPA adjust)
Reg 2D D3
DSK
DYNAMIC SKIN TONE
Enables dynamic skin tone function.

0 = off
1 = on
Reg 2E D4, 5
RPO0, 1
RATIO PRE_OVERSHOOT
RPO1
RPO0
Setting
0
0
1:1
0
1
1:1.25
1
0
1:1.5
1
1
1:1.8
Table 17: Ratio pre- and overshoot
Reg 2E D6
BPB
BANDPASS FILTER BYPASS
Bypasses the internal bandpass filter.

0 = bandpass filter switched on (default)
1 = bandpass filter bypassed
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OUTPUT CONTROL BITS
Reg 00 D0..3
CD0..3
COLOUR DETECTION
Shows the colour standard that is identified

CD3 CD2 CD1 CD0
Colour standard
0
0
0
0
no colour standard identified
0
0
0
1
NTSC
0
0
1
0
PAL
0
0
1
1
NTSC
0
1
0
0
PAL
0
1
0
1
NTSC
0
1
1
0
PAL
0
1
1
1
NTSC
1
0
0
0
PAL
Table 18: Detected colour standard
Subcarr. Freq
A
A
B
B
C
C
D
D
Frequencies:
- A: 4.433619 MHz
- B: 3.582056 MHz (PAL N)
- C: 3.575611 MHz (PAL M)
- D: 3.579545 MHz (NTSC M)
Reg 00 D4
SL
SYNC LOCK
Horizontal lock indication:

0 = Not locked
1 = PHI-1 loop locked to the incoming video signal
Reg 00 D5
LOCK
IF-PLL LOCK
The lock bit becomes one when the IF-PLL is in-lock, independent upon video contents. This means the bit
can also be used to identify sound carrier signals.
0 = PLL not locked
1 = PLL locked
Note: AFC information is only valid when LOCK=1, see related bit, IFLH
Reg 00 D6
IFI
VIDEO IF IDENT
Detects video at IF or selected source (see also VIM bit). This is a stand-alone detector that recognises
video signals, containing line frequent components.
0 = No video signal identified
1 = Video signal identified
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Reg 00 D7
Application Note
AN01045
POR
POWER ON RESET
Power on reset: Indicates detection of a power failure of the 3.3 Volt supply (including switch-off of the TV
set). It remains high until the status bytes have been read successfully to enable also to detect short power
failures. When a failure is detected, the internal data is not reliable any more and should be refreshed.
During normal operation the POR status should be read continuously, before sending any input data. During
start-up, the processor part should read the IC status until the POR bit is low, immediately followed by the
start-up procedure.
0 = Device operational
1 = Power failure detected
Reg 01 D0
IN2
RGB/YUV INPUT2 STATUS
Reflects the level on the fast blanking input pin 45.

Level is only checked during vertical retrace to enable differentiation between OSD insertion (IN2 remains
0) and full RGB/YUV sources (IN2 becomes 1)
0 = Pin 45 low (< 0.4V), no insertion
1 = Pin 45 above insertion level (>0.9V, RGB/YUVIN inserted when IE2=1)
Reg 01 D1
BCF
BLACK CURRENT LOOP

FALSE
Reflects the condition of the black current loop. Can be used at start-up or for regular check during normal
operation to indicate RGB stage malfunctioning.
0 = Black current loop is stabilised
1 = Black current loop is not stabilised
Reg 01 D2
HBC
HELP ABOVE/BELOW
BCL WINDOW
Valid when VSD = 1 (no vertical deflection). Can be used together with WBC (Window Beam Current loop)
for factory alignment of the Vg2. Reading HBC indicates which direction to turn the Vg2 potentiometer to
bring the beam current in the window of 12 - 20 A (see also WBC below).
Note that HBC switches from low to high at the moment the beam current is in the window of 12 - 20 A
(and does not toggle in the middle of the window!)
0 = below 12 A
1 = above 12 A
Reg 01 D3
WBC
BCL WINDOW
Valid when VSD = 1 (no vertical deflection). Can be used together with HBC (Helper Beam Current loop) for
factory alignment of the Vg2.
Reading WBC indicates whether the beam current is in the window of 12 - 20 A while the bit HBC
indicates whether the current is above or below the window (see also HBC above)
0 = outside window
1 = inside window (beam current 12 - 20 A)
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Reg 01 D4
Application Note
AN01045
IVW
IN VERTICAL WINDOW
Condition vertical divider window:

0 = No standard video signal detected
1 = Standard video signal detected, 522-528 or 622-628 lines/frame, vertical divider in narrow
window or standard mode
Reg 01 D5
FSI
FIELD SYNC INFORMATION
Field frequency indication of the selected CVBS signal

0 = 50 Hz
1 = 60 Hz
Reg 01 D6
NDF
NO VERTICAL DEFLECTION
This bit is set to 1 when the vertical guard pulse at pin 50 (BLKIN / Vertical guard) is wrong.
0 = Vertical deflection OK (correct guard pulse present)
1 = Failure detected in the vertical output stage (incorrect guard pulse present)
Reg 01 D7
XPR
X-RAY PROTECTION
This bit is set to 1 when an overvoltage is detected (voltage on pin 36 EHT / XPR > 3.9 Volt). When XDT is
set to 0, the horizontal drive is stopped via slow stop including RGB drive for 1 mA discharge current
measured via the black current input.
The bit is latched when the voltage on pin 36 > 3.9 Volt and can only be set to zero when the status bytes
are read after the voltage on pin 36 has dropped below 3.9 Volt. The microprocessor part should monitor
XPR and when XPR = 1 the bit STB must be set to 0. When no problem seems present, the set can be
restarted by setting STB = 1. Setting STB = 0 after XPR = 1 is essential because immediate writing STB = 1
will not release the horizontal drive.
0 = No over-voltage detected
1 = Over-voltage detected on EHT input pin 36
Reg 02 D0
FML
FM PLL LOCK
0 = No lock
1 = Indicates that the FM PLL is in lock
Reg 02 D1
FMW
FM PLL IN WINDOW
0= Indicates the PLL VCO carrier is tuned within the catching range
1= Out of window
A valid sound carrier is found when FML=1 and FMW=0.
Note: For search tuning algorithms, the sound carrier detection have to take place in a certain order to
prevent that 4.43 MHz colour carrier can be detected as 4.5 sound carrier. Recommended sequence order
is: 5.5 MHz, 6.0 MHz, 6.5 MHz, and 4.5 MHz.
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Reg 02 D2, 3
AFA
AFB
Application Note
AN01045
AFA, AFB
AFC OUTPUTS
0 = Outside window (see AFW bit)

1 = Inside window
0 = Below reference, increase tuner frequency
1 = Above reference, decrease tuner frequency
AFC output information is available for search tuning. An automatic AFC loop is achieved together with the
microprocessor and tuner. Because of the alignment free IF, AFC alignment is not required, the PLL is
calibrated fully automatically. The figure below gives the AFC bit status in relation to the incoming IFfrequency.
38.9MHz
above reference
below reference
AFB
reference
25kHz
outside window
RF too high
outside window
RF too low
AFA
normal window
IF too low
IF too high
100kHz
AFA
large window
300kHz
Figure 2: AFC output bits

AFC read-out:
- The applied IF-frequency is correct when in-window, AFA bit is "1" and AFB is (close to) altering.
- AFC information can be read-out continuously but is updated during the vertical retrace. Therefore a
minimal wait of 20ms is required between changing the tuner frequency and reading-out AFA/B.
- AFC information is only available and valid when LOCK=1. This is inherent to the alignment free
concept.
Note:
- -AFC is valid when LOCK=1. This however does not guarantee that a picture carrier is found. E.g. the
- PLL can also lock to a sound carrier. For this reason its advised to check also the sync lock bit SL.
- -AFC remains valid in full OSD mode when POC=1 (than SL=0 but that is a dont care for AFC)
- -AFC remains valid in stand-by mode when STB=0 (than SL=0 but that is a dont care for AFC) and is
useful for TV-VCR application.
- -AFA bit is forced to zero during automatic AFC calibration (takes place after signal loss). This prevents
false AFA=1 read outs and optimizes the search tuning.
AFC accuracy:
- High AFC resolution of 25kHz for both AFA and AFB (indicated by the gray area)
- The AFA window position has a fixed relation to AFB. This ensures the window width of 100 and 300kHz.
Search tuning:
- Have AFW=1 for large window. This allows larger frequency steps and faster search tuning.
- Wait for LOCK and (SL or IFI) =1 before reading AFC information.
- Increment RF frequency until AFA=1. Tune in small frequency steps until AFB just toggles.
- For non-search tuning (normal TV) operation its recommended to select the normal window, have
AFW=0.
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AN01045
Fine-tuning:
The digital AFC information provides an accurate AFC loop. Fine-tuning is possible in an open AFC loop.
Especially with PLL-tuners its easy to add a frequency offset via the microprocessor while ignoring the AFC
output bits.
Reg 02 D4
QSS
QSS/FM VERSION
This can be used to verify whether the device is a QSS or FM intercarrier type.
0 = FM intercarrier
1 = QSS
Reg 02 D7
SUP
+ 8 VOLT SUPPLY PRESENT
Indicates whether the + 8 Volt supply is present.

When low power start-up is used with only 3.3 Volt supply present, the device will be first full operational
when this bit reads 1 (and the + 8 Volt supply is present).
When during normal operation the + 8 volt drops below the detection level (about 6.2 Volts, 0.2 Volts
hysteresis) the horizontal drive is switched off. When the +8 Volt supply rises again above detection level
(about 6.4 Volts), the horizontal drive is automatically switched on via slow start. In this way, the device
recovers automatically when a short power dip on the +8 Volt is present.
When the +8 Volt is derived from the EHT flyback transformer, a drop in the + 8 volt supply can disable the
+ 8 Volt supply because the horizontal drive is switched off. To restart the horizontal drive in this condition,
first STB must be set to 0 and then to 1 again.
0 = no + 8 Volt supply present
1 = + 8 volt supply present
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AN01045
APPLICATION INFORMATION
Microprocessor General
In this chapter, especially the hardware design aspects of the Micro-Controller pins are covered. For the
programming aspects please refer to the Micro-Controller SFR registers of the embedded Micro-Controller
part as defined in the specification.
* I/O ports
Pin 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 62, 63, 64
The I/O pins of the processor can be configured in many ways. All port functions can be individually
programmed by use of the SFR registers.
Each port pin can be individually programmed in four output configurations. About detail please refer Table
1 and Table 2.
Open drain
In this mode, the port can function as in- and output. It requires an external pull-up resistor. The maximum
allowable supply voltage for this pull-up resistor is + 5 Volt.
So in this mode, it is possible to interface a 5 Volt environment like I2C with 3.3 Volt supply of the MicroController part.
Push-Pull
The push-pull mode can be used for output only. As well sinking as sourcing is active, which leads to steep
slopes. The levels are 0 and VddP, the supply voltage of the output pins on pin 61, usually 3.3 Volt.
Quasi-bidirectional
This mode is a combination of open drain and push-pull. Normally the port is configured as open drain and it
needs a pull-up resistor to the same supply voltage as VddP (usual 3.3 Volt).
Only during a low to high transition, the port is switched to push-pull operation for one clock cycle (166 ns)
to speed up the rising edge.
This is the default mode of all I/O pins after a reset.
Note: This mode cannot be used with pull-up resistors to + 5 Volt!
High impedance
This mode can be used for input only operation of the port.
Note: To minimise power consumption in stand-by, it is best to program all port pins in high impedance
mode when entering Stand-By mode.
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AN01045
Extra functions of port pins

A number of port pins have extra functionality. This extra functionality can be programmed via the SFR
registers of the Micro-Controller. In the table below, the available extra functions are listed.
[ Table 1 ] TDA935XPS/6XPS/8XPS - SDIP64 Package
2
PWM PWM
ADC
IC
Port
Pin
8mA
bus 14 bits 6 bits 8 bits
sink
current
P1.3
1
P1.6
2
SCL
P1.7
3
SDA
P2.0
4
x
P3.0
5
x
x
P3.1
6
x
x
P3.2
7
x
x
P3.3
8
x
x
P0.5
10
x
P0.6
11
x
P1.0
62
P1.1
63
P1.2
64
Int.
Timer
external
input
Tim. 1
Int. 1
Tim. 0
Int. 0
Below, a more detailed description of the extra functions is given.

- 8 mA sink current (Port 0.5, 0.6 / Pin 10, 11)
These pins have the same functionality as the general I/O pins (same 4 modes) but in addition, their current
sink capacity is 8 mA in stead of 4 mA. These pins can be used for direct drive of LEDs.
2
- I C port (Port 1.6, 1.7 / Pin 2, 3)

2
Two output pins can be programmed as SDA (pin 3, port 1.7) and SCL (pin 2, port 1.6). The I C is multi
master. The pins can be connected via pull-up resistors to the standard 5 Volt supply, commonly used for
2
I C provided the output is configured as open drain.
- 14 bits PWM (Port 2.0 / Pin 4), 6 bits PWM (Port 3.0..3.3 / Pin 5..8)
The Pulse Width Modulated outputs can be used to generate programmable DC voltage. This DC voltage
can be used for e.g. DC volume control or as DC tuning voltage for a Voltage Synthesized Tuner.
The output is a square wave with a fixed frequency and a programmable duty cycle. The duty cycle can be
varied from 0 to 100 %.
Transformation of the square wave to a DC voltage is achieved by applying an integrator network. In its
simplest form this can be a series resistor with a capacitor to ground.
Standard the output range of the PWM cannot exceed the supply voltage of VddP (3.3 Volt). When higher
voltages are needed, the port can be switched to open drain mode with a pull-up resistor to +5 Volt. Finally it
is possible to drive a transistor with in the collector a resistor to a higher supply voltage. Because the
transistor inverts the square wave at the base, the duty cycle is reversed, which has to be taken into
account in the software.
Note that the stability of the DC voltage is pending on the stability of the supply voltage. It is best to have a
high ohmic load connected to these DC voltages or at least a constant load.
The 14 bits PWM is suitable for Voltage Synthesised Tuning because of its resolution. The frequency is
23.44 kHz (repetition rate is 42.66 s), in 16383 steps (14 bit) the average high time can be programmed
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Application Note
AN01045
from 0 to 100 %. (an interleaving technique is used to achieve this high resolution, so not all high times are
equal).
The 6 bit PWM is suitable for general DC control like volume. The frequency is 46.88 kHz (repetition rate
21.33 s), in 63 steps (6 bit) the high time can be programmed from 0 to 100 %.
- ADC input (Port 3.0..3.3 / Pin 5..8)
The Analogue to Digital Convertor uses successive approximation to determine the digital value of the
offered DC signal at the input.
The resolution is 8 bits over a voltage range of 0 to 3.3 Volts, which gives 3.3 / 256 = 13 mV per step.
However, the port configuration is such, that the input range from VddP - 0.75 Volts to VddP cannot be
used. This is related to the threshold voltage of a protection transistor, needed to have the pin tolerant for
+5 Volt in open drain mode.
So the practical input range is 0 to 2.55 volts (worst case 0 to 2.25 volts with 3.0 Volt supply) with digital
output from 00 hex to C0 hex.
The inputs can be used for scanning keyboards with resistor ladder network and to determine levels at the
SCART status input.
- Interrupt 0, 1 (Port 1.2 / Pin 64, Port 1.0 / Pin 62)
The external interrupt pins can be activated by level or edge.
When programmed for level, the interrupt is active low.
When programmed for edge, interrupt 0 will only react on the negative edges of the signal while interrupt 1
will react on both positive and negative edges.
The interrupt inputs can also be programmed as gating input to enable the timer/counter. When activated, a
high level enables the timer/counter to count, a low level stops the counting. INT0 controls the gating of
Timer/counter 0 and INT1 controls the gating of Timer/counter 1.
- Timer external input 0, 1 (Port 1.1 / pin 63, Port 1.3 / Pin 1)
When configured as timer, as input the X-tal oscillator frequency divided by 12 is used. For the specified
12Mhz X-tal this means an input clock of 1 MHz.
When the internal timers are configured as counter, the counter content is increased on every negative
edge of the signal of the external timer input on pin 63 or pin 1.
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AN01045
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6.1
Application Note
AN01045
MICROPROCESSOR
Pins 58, 59, 57
XTALIN/XTALOUT/OSCGND
12 MHz crystal oscillator, ground
The crystal oscillator which operates at 12MHz supplies reference signal to different internal circuit blocks
one of them being the DCO (digital colour oscillator).
The specified Cl of the external crystal is valid for both series or parallel resonance as indicated on next
page; the TDA937X PS N2 crystal oscillator uses the third configuration.
Cl
(1)
series
resonance
Cl
2Cl
(2)
parallel
resonance
2Cl
(3)
parallel
resonance
Figure 3: Crystal configuration

The crystal is placed between pins 58 and 59 and the external capacitors Cx1, Cx2 are connected between
pins 58, 59 and the oscillator ground at pin 57.
It is very important to connect only these two capacitors to this ground pin and to leave the oscillator ground
pin floating; therefore do not connect pin 57 to the ground plane.
Example:
Saronix crystal (part no. = 9922 520 00169) has specified Cl=20pF.
With Ci=Co = 7pF in Philips demoboard then Cx1=Cx2=33pF in order to have colour symmetry.
Also low profile / SMD Saronix Xtals are available for miniature, LCD application etc.
12MHz reference
Ci
Co
276K
58
59
Cx1
57
Cx2
Figure 4: Basic crystal oscillator application

Depending upon PCB layout Ci, Co can be different; then Cx1, Cx2 has to be optimised to have a
symmetric colour catching. Avoid large ground planes in the vicinity of the crystal.
The values of Cx1=Cx2 in application should be between 12pF and 56pF, this places a restriction on the
value of Cl which the crystal manufacturer specifies.
For Ci=Co = 7pF then Cl is restricted between the values 13pF and 30pF approximately.
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AN01045
The crystal resistance should be less than 100E.

The colour catching range is internally defined and is not dependent upon the motional capacitance as is
the case with present analogue colour decoders.
The frequency tolerance should be typical +/-30ppm; larger tolerance is allowed but this leads to more
spread in colour assymmetry.
Pin 60
Reset
Power On Reset (POR)
The reset pin is coupled to the internal reset circuitry as indicated in the microprocessor block diagram.
A Power On Reset (POR) of the microprocessor occurs when VddA (3.3V at pin 54) dips below
approximately 2.5V and in order to realise this there is a internal direct hardwire communication between
both microprocessor and videoprocessor.
Also an external reset circuit in application can be implemented if necessary but is not required.
An example of an external reset circuit is given in the application diagram.
2
To prevent false I C messages to the non-volatile memory during rise or fall of the supply, also the memory
supply should be switched-off during reset. In this way, data corruption is prevented.
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6.2
Application Note
AN01045
IF PART
Pin 23, 24
IFIN1, IFIN2
IF video input
The IF input frequency range is 32 - 60 MHz.

The IF input impedance is 2 k in parallel with 3 pF.
This matches the required load for commonly used SAW filters. DC coupling is allowed, therefore no series
capacitors between SAW filter and IF input are necessary. For maximum IF performance (also for
asymmetric tuners) keep the signal path from tuner to the IF input pins as short and symmetrical as
possible.
The table below gives an example of possible SAW filters.
Type
Mode
Standard
Remarks (sound shelf and IF frequency)
K2955M Intercarrier
B/G, D/K
-20dB, IF=38.9
K2960M Intercarrier
B/G, D/K
-14dB, IF=38.9
K2962M Intercarrier
B/G
-15dB, IF=38.9
K1984M Intercarrier
B/G
-14dB, IF=38.9
M1970M Intercarrier
M/N
-14dB, IF=45.75, for FCC EIA/IS-31
M1865D Intercarrier
M/N
-13dB, IF=45.75, for FCC EIA/IS-31, SIP5D
K3953M QSS - Video
B/G, D/K, L/L
Double Nyquist Slope (38.9 and 33.9)
K9456M QSS - Sound B/G, I, D/K/L or LNICAM
Pin 1= L,
pin 2= B/G, I, D/K, L
This SAW filter needs ASYM tuner!
G3962M QSS - Video
B/G
IF=38.9
G9353M QSS Sound B/G-Nicam
Single bandpass
K9354M QSS Sound B/G, I, D/K, L
Broad single bandpass
Table 19: Siemens Matsushita SAW filter Combinations (all SIP5K packages)
Pin 27
AGCOUT
Tuner AGC output
This output pin is used to control the tuner gain for varying RF signal conditions.
The tuner AGC pin is an open collector output, which is acting as a variable current source to ground.
An external pull-up resistor determines the slope of the tuner output voltage swing and therefore the
maximum IF-input amplitude variation, called slip. Suggested pull-up resistor is 1k2, with R = 180 in
series with the pin. The exact resistor value depends on the tuner voltage control range.
Once the tuner AGC is active the IF input signal level is constant within the slip. The level on which the
tuner becomes active (Tuner take over point) can be adjusted by IC bus. With a pull-up resistor of 1k2
the slip is about 4 dB.
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Tilt
AGC voltage
Reference
pulse
100% white
Video output
signal
one field
Figure 5: Positive modulated signal with top white reference pulse
The time constant of the tuner AGC can be defined separately from the gain (pull-up resistor) setting.
Stability of the loop becomes difficult when the loop gain is too high (pull-up resistor >> 1k2). Special
attention on stability is required for reception of positive modulated signals (VITS line at 100% and video
about 50%).
Notice that when the IF-part is muted via VSW = 1, than the tuner output pin is pulled to ground level for
minimum tuner gain. After switching on again, the tuner AGC capacitor must re-charge (and also the tuner
gain). The time constant is determined by the capacitor value and pull-up resistor value.
IF-AGC actions:
Optimal IF performance is achieved with gating signals derived from the horizontal oscillator. They become
automatically active once the coincidence detector SL = 1.
In external mode the top white AGC remains available only, because in external mode the sync part is
locked to the AV signal.
Gating signals
Always available
Activated when SL = 1
Internal (RF mode)
Top white AGC
Black clamp AGC
AGC line gating
External, Decoder mode
Top white AGC
Table 20: Gating signals in the two input modes
Input mode
AGC speed
The AGC speed can be adjusted with AGC1, AGC0, see section I2C.
Pin 37
PLLIF
PLL loopfilter
The standard loopfilter configuration is R = 390 and C = 100 nF in series to ground. The loopfilter
bandwidth is 60 kHz and is chosen optimal for fast catching as well as sufficient video suppression to obtain
optimal sound performance.
2
The loopfilter time constant can be changed by I C bus function FFI (Fast filter IF-PLL). See for detailed
description of the function, chapter picture improvement.
Note:
For special market areas with large phase modulation we recommend:
Keep FFI=0 (off)
Change loopfilter
R=390E -> 1k5 (2k2 maximum)
C=100 nF -> 47nF (33 nF minimum)
Drawback: higher loopfilter bandwidth is less optimal for sound performance (video -> sound)
48
Version 1.0
TDA937X PS N2
Pin 38
Application Note
AN01045
IFVO / SVO
IF video out / selected

video out
The level of the video output signal:

Video amplitude is typical
top sync (fixed by AGC)
Selected CVBS out
B/G
2.5
2
2V
[Vpp]
[V]
[Vpp]
(When SVO=1)
Although the video output impedance is low it is recommended to avoid high frequency current in the output
due to for instance sound trap filters. This can be achieved by means of an emitter follower at the video
output with a 1k resistor in series with the base.
This pin includes a double function. When SVO = 1 than the selected CVBS signal becomes available for a
SCART monitor function. See table below.
Some remarks as regards performance issues related to pin 38.
Beat of 2.9 MHz:
In some applications a 2.9 MHz beat becomes present at the video output pin. The mechanism is that the
3rd Xtal harmonic (3 x 12 MHz) is 36 MHz is injected to the IF input path. Demodulated at 38.9 MHz results
in a beat of 2.9 MHz.
Attention points to minimize this effect:
Symmetrical path between tuner, SAW filter and IF input pins. This gives optimal common mode
rejection.
Avoid radiation of I/O ports into IF-input.
Remove capacitor of decoupling digital supply 3.3V pin 15.
Please see section Oscillator, supply, decoupling, grounding and supply startup/shutdown.
Cross talk INT->EXT aspects:
Avoid PCB tracks with video signals being close to the AV input. (voltage cross talk)
Avoid high video currents in supply lines and or ground close to IC.
Decouple collector of emitter follower(s)
Use minimal current in emitter follower(s)
At no antenna signal condition the video noise peak-peak level (approx. 4 Vpp) is higher than the normal
video amplitude (2.5 Vpp). Depending upon application this might give extra cross talk and line jitter. This
noise level can be reduced by means of IC bus
IFS = 1. This reduces the maximum IF-gain by 20 dB. In practice overall sensitivity reduction will only be 12
dB due to the combination of tuner and IF stage.
Switch-off IF part:
- Switch off the IF-part by means of IC bus command VSW = 1.
In this condition the video output pin voltage is 0V and tuner AGC output is forced low for minimal tuner
gain.
Note: after switching on again, the tuner AGC capacitor must charge again. The capacitor value and pull-up
resistor defines the time constant.
CVBS1 input pin 40 can be used as extra input pin. (This is only possible when VSW = 1 else cross links
between IF and sync part will remain active)
49
Version 1.0
TDA937X PS N2
6.3
Application Note
AN01045
FM SOUND
Pin 20, 32
AVL
Automatic volume
leveling
The Automatic volume Leveling feature is available in specific IC versions and can be switched on/off via
AVL bit (reg 2C D2).
For 90YHUVLRQVZLWKRXW(:GULYH7KH$9/FDSDFLWRUVKRXOGEHFRQQHFWHGWRSLQ20.
For 110YHUVLRQVZLWK(:SLQ32 can be selected to apply the AVL capacitor using CMB0, 1 bits (reg
nd
22 D4, 3). Other features (2 SIF, Combfilter reference output) that make use of this pin can not be
used
7KHUHFRPPHQGHGFDSDFLWRUYDOXHLV )WR )LWVRSWLPDOYDOXHLVDFRPSURPLVHEHWZHHQIDVWYROXPH

settling, AVL hold time (dynamic sound range) and harmonic distortion.
A small AVL capacitor value gives fast volume settling but reduces the dynamic sound range and
performance on harmonic distortion for mainly low audio frequencies.
A large AVL capacitor value gives maximal AVL performance but increases the volume settling time.
The active control range of the AVL pin is 1V for maximum gain and 5V for minimal gain.
During channel switching it is recommended to enable sound mute (via SM0/1).
After releasing mute the AVL is set in maximum gain, this ensures a fast settling of the volume level. Noise
peaks will not disturb the AVL function during channel switching.
The AVL circuit works properly for an AVL input signal range of approx. 100-1000 mVrms. This is called the
"boost range" and is 20 dB. Within this "boost range" any desired stabilised output level can be adjusted by
means of the volume control. An external AVL capacitor acts as "memory" and integrates the audio peak
signal. The charge (or attack) current is 1 mA, the discharge (or release) current is 200 nA. The time
constant is defined by the AVL capacitor. The DC voltage (1-5V) across the AVL capacitor controls a gain
stage that stabilises the audio output level.
Because the discharge current is very small, any leakage of the AVL pin to ground must be avoided.
Therefore a capacitor of a decent quality should be use at the AVL pin.
Specifications:
Gain at maximum boost
Gain at minimum boost
Control voltage at maximum boost
Control voltage at minimum boost
Charge (attack) current
Discharge (decay) current
Charge/discharge current ratio
+6
-14
1
5
1
200
5000
dB (relative to 500 mVrms in)

dB (relative to 500 mVrms in)
V
V
mA
nA
50
Version 1.0
TDA937X PS N2
Pin 31
Application Note
AN01045
SNDPLL
Sound PLL Loop filter
The filter components mentioned below can be used for all sound standards for optimal sound
performance. (Cs + R) // Cp
Bandwidth 3dB [kHz]
Cs
R
1.2 nF
150
3.9 k
Table 21: Loopfilter component values
Cp
330 pF
Damping
0.5
Apply these components close to the pin to minimize external disturbances.
Pin 32
AVL/REFO/SNDIF
AVL/Combfilter output/
ND
2 SIF INPUT
This pin 32 has three functions that can be selected using the CMB0/1 and SIF bits.
I.
Automatic volume leveling (AVL) function
nd
II.
2 SIF input
III.
Combfilter reference output carrier
IV.
Switching output.
I.
AVL see pin 20.

nd
II.
The 2 SIF input provides direct access to the FM demodulator input.
This option is available when CMB0/1 = 00 and SIF = 1. Set FMA/B for sound carrier frequency selection.
nd
Sensitivity of the 2 SIF input is 1 mV

Input impedance is 50k
The pin voltage must be in between 0 - 4V maximum.
This pin needs a DC path to ground, apply always 470 to 1k at this pin when using this feature.
8V
1k
2nd SIF
270
470
1k
100
CVBS
Pin 38
1k
IFVO
nd
Figure 6: 2 SIF application

nd
The 2 SIF input is intended for special applications only, as e.g.:

- For fine tuning sound performance for very extreme market areas.
- The intercarrier signal from pin 38 can be used to apply to the external sound pass filter. For PAL
BG/DK applications these external filters can be placed in parallel.
51
Version 1.0
TDA937X PS N2
Application Note
AN01045
III. and IV.

The reference output signal is only available when CMB0, 1 = 01. For the other CMB0, 1 settings this pin is
2
a switch output. See also I C chapter.
Pin 35
AUDEXT
External audio input
An external sound source can be fed into this pin via a coupling capacitor.
Maximum input voltage is 2 Vrms.

The input impedance is 25k.
The coupling capacitor for a corner frequency for instance 10 Hz is:

& [ [+][N )
Pin 29
DECSDEM
Sound decoupling
This pin requires a capacitor connected to ground. This pin serves as a low pass filter needed for the DC
feedback loop.
The de-emphasis pin determines the low pass crossover frequency.
This decoupling pin determines the high pass crossover frequency.
The pin output impedance is typical 500 so with the following formula you can calculate the capacitor
value:
) [ [&[7KHVORSHLVG%RFWDYH
The following highpass crossover frequencies are valid:
FMA/FMB FM sound standard [MHz] Decoupling capacitor High pass frequency
01
4.5
)
106 Hz
00/10/11
5.5/6.0/6.5
)
53 Hz
01
4.5
)
64 Hz
00/10/11
5.5/6.0/6.5
)
32 Hz
Table 22: Sound decoupling capacitor value for different frequencies and standards
The corner frequency for standard 4.5 MHz is two times bigger. This is due to the circuit design and is
depended of the setting of the AGN bit. The loop gain is twice as much when +6 dB amplifier is inserted for
NTSC.
Note: Capacitor values larger than 32 uF lead to long settling times before FM sound is available. (>3-4s
after 8V supply is applied).
52
Version 1.0
TDA937X PS N2
Pin 28
Application Note
AN01045
AUDEEM
I.
Audio de-emphasis
De-emphasis time constant
The de-emphasis output pin requires a capacitor to ground that defines the de-emphasis time constant.
Example:
De-emphasis time constant is 54s for a standard PAL signal.
The pin output impedance is 15k typical, the capacitor becomes
C = 54s/15k= 3.6 nF -> 3.9 nF.
The corner frequency f = 2700 Hz, the slope is 6 dB / octave.
The pin should not be loaded with high impedance as it effects the time constant.
For BTSC applications a capacitor of 33 pF is recommended.
(flat freq. Response up to 100 kHz).
The corner frequency for standard 4.5 MHz is two times bigger. This is due to the circuit design and is
related to the gain difference of the 0/ +6 dB switch in the de-emphasis signal path.
Sound
output
[mV]
Volume
MAX sound volume
+ 9 dB 1400
1000
0 dB
C=33p for
BTSC stereo
De emphasis level
500
- 6 dB/oct
+ 6 dB/oct
C=3n9
T=54s
f1
f2
100
10
100
1k
10k
100k
f [Hz]
0.3
- 71 dB
0.14
0.1
MIN sound volume

^
=mute
level
Figure 7: Frequency characteristic de-emphasis output

II.
Audio output level
Video standard or function Output level [mVrms

(AGN = 0)
(Nominal frequency
nominal condition
deviation)
PAL (50 kHz)
500
NTSC (25 kHz)
250
Table 23: Nominal output levels de-emphasis pin
53
Output level [mVrms]

(AGN = 1)
+6 dB
Not recommended
500
Version 1.0
TDA937X PS N2
Application Note
AN01045
The signal must always be buffered to avoid influence of the de-emphasis time constant.
To fulfill the SCART requirement (500 mV at 27 kHz FM swing) this signal must be amplified by 6 dB. Both
requirements can be fulfilled at the same time when the buffer is configured as an amplifier.
III.
Sound mute
The DC output level is 3.2V, also during mute.

The setting of SM1, 0 = 10 is to mute this output pin.
In normal operation we recommend setting SM1, 0 = 01, because this setting limits spike noise in weak
signal conditions. This due to the fact that in this case the acquisition help pulses of the narrow band PLL
becomes active to prevent unlocking of the sound PLL.
Pin 44
AUDOUT
Volume controlled
output
This output pin delivers the internal as well as external volume controlled audio signal. The nominal gain is
+9 dB and 7 dB, which gives a total control range of 80 dB. The output signal range is 0.14 1400 mVrms.
The bandwidth is >100 kHz, the DC level is 3V and the output impedance is 500. The output is
automatically muted in standby mode (STB = 0).
54
Version 1.0
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6.4
Application Note
AN01045
QSS SOUND
Pin 20
AVL, EW
AVL/EW drive
The AVL feature is only available in QSS versions without EW. See also Chapter: Pinning configuration, Pin
functions for various modes and the FM sound chapter.
Pin 28, 29
SIFIN1, SIFIN2
SIF input
The IF input frequency range is 32-60 MHz.

The IF input impedance is 2k in parallel with 3 pF.
This matches the required load for commonly used SAW filters. DC coupling is allowed, no series
capacitors between SAW filter and IF input are necessary.
For optimal IF-performance (even for asymmetric tuners) it is advised to:
- Make the signal path from tuner to the IF-input pins as short and symmetrical as possible.
- Make sure that the supply line is clean of the pre-amplifier used. Supply ripple will be AM demodulated.
- To prevent overloading these input pins, check:
Tuner AGC alignment
Type of SAW filter
Using QSS, better sound performance can be achieved compared to intercarrier applications. This is mainly
due to the extra selectivity of the SIF SAW filter and the lower soundcarrier suppression, see example
below.
-1 0 dB
-6 d B
-14 d B
-6d B
-2 4 dB
V ID E O
SOUND
K 2 96 0 M
SAW
PC
P C /S C ra tio : 1 8 dB
SC
PC
SC
-6d B
-1 0 dB
V ID E O
K 3 95 3 M
SAW
-6 dB
-10 d B
P C /S C ra tio : 4 dB
-0 dB
PC
SC
PC
SC
SOUND
G 93 5 3 M
SAW
Figure 8: SAW filter losses

Conclusion, with QSS the soundcarrier level is 14 dB higher compared to intercarrier SAW filter with e.g.
14d B sound shelf.
55
Version 1.0
TDA937X PS N2
Pin 31
Application Note
AN01045
SIFAGC
SIF AGC
The optimal AGC capacitor value is 2.2 F and achieves an optimal compromise between AGC speed and
AM frequency behavior. A smaller capacitor value for AM sound will increase the low corner frequency (the
harmonic distortion will not be affected, since the AGC is an average detector).
The AGC time constant is automatically adapted for positive and negative modulation. For negative
modulation the AGC time constant is 10 times faster. For maximum stability the AGC capacitor must have a
short connection to ground.
Pin 32
REFO
Combfilter output
This pin has multiple functions, which can be used in one application.
I.
II.
Combfilter reference output carrier

Switching output.
I. and II.
The reference output signal is only available when CMB0, 1 = 01. For the other CMB0, 1 settings this pin is
2
a switch output. See also I C chapter.
Pin 35
I.
QSSO/AUDEXT
QSS output/External audio input
QSS output
Provides both FM as AM modulated carriers. The signal level is controlled by the SIF AGC and kept
constant at 100 mVrms. This signal can be applied to an external (stereo) decoder. It is recommended to
buffer this pin, this prevent attenuation of the QSS signal. A high pass filter can be used to increase sound
performance. Recommended component values are C = 330 pF and R = 1K.
II.
External audio input
When CMB0, 1 = 00, this pin is an external audio input. The input level can be maximum 500 Vrms for 54%
modulation.
Pin 44
Controlled audio out
See FM chapter.
56
Version 1.0
TDA937X PS N2
6.5
Application Note
AN01045
THE NARROW BAND PLL
The new PLL concept used in the TDA937X n2 as in the previous series TDA935X/6X/8X both n1 as n2 is
introduced to simplify the application for sound modulation and is designed to be used without external
bandpass filter components. The TDA935X/6X/7X/8X n2 versions are also featured with an internal
bandpass filter (Q=16) for selectivity. For extreme market conditions additional external filers can still be
nd
applied using the 2 SIF input.
2
The NBPLL (Narrow Band PLL) has a limited locking range centred on the sound carrier selected with I C
bits FMA, FMB. The NBPLL loop selectivity is determined by the external loopfilter component values, that
also defines other parameters such as S/N ratio and THD. The chosen loopfilter component values are
always a compromise between the mentioned parameters.
The status of the NBPLL is digitally controlled and secures a holding range of 225 kHz, this can be
enlarged to 450 kHz for highly modulated carriers using FMWS. The in/out window status can be
monitored via FMW output bit. When an out of window condition is detected the NBPLL generates
acquisition pulses to speed up the locking process.
The locking status can be monitored via the FML output bit.
Sound performance of the narrowband PLL

See below the S/N characteristic graphs that show the sound performance of the narrowband PLL. As seen
clearly in the first graph, the narrowband PLL is capable to meet at least 30 dB at PC/SC = 25 dB. The
measurement is carried out in the demoboard application designed by SLE, under the following conditions:
-
RF level 60 dBuV
RF frequency 471.250 MHz
Picture content: Colour bar
PAL BG 10% rest-carrier
1 kHz tone 27 kHz deviation 0 dB reference
SAW filter K2955M (-20 dB soundshelf)
Selective S/N measurement between 22 Hz 22 kHz
Equipment: Rohde & Schwarz SFM, SAF, UPA
57
Version 1.0
TDA937X PS N2
Application Note
AN01045
Figure 9: Sound performance narrowband PLL

Limitations of the narrowband PLL
- Limitations to highly modulated soundcarrier
When the average measured VCO frequency is more than the window borders, acquisition help is
activated resulting in soundcrackling. Before this event, THD increases (the edges of the FM
demodulated frequency spectrum are being cut away), see the picture below:
Cs=4n7F, Rs=3k9, Cp=820pF
FMWS = 1
Cs=1n2F, Rs=3k9, Cp=330pF
THD
[%]
+225kHz
Frequency
Figure 10: Distortion versus increasing soundcarrier modulation

-
Acquisition help pulses

When the acquisition pulses are operating, the sound impression can be described as soundcrackling.
Tiny pulses are added onto the loopfilter signal to obtain faster catch behaviour. Because of the
significant amount of gain further up in the chain (> 50 dB), these small pulses transform to large spikes
at the volume controlled output pin.
The volume level of these spikes can be decreased using the automute (SM1, 0 = 01) function. With
FMWS = 1 (large window), less spikes are being generated.
58
Version 1.0
TDA937X PS N2
6.6
Application Note
AN01045
FILTERS, SWITCHES AND COLOUR DECODER
A complete multi-standard colour decoder is implemented whereby all world standards can be decoded.
The following colour identification algorithm is implemented
IDN IDP
PSNS
Xtal
freq
Auto mode
Forced
NTSC
Forced
PAL
0 0
x
x
kill
kill
kill
0 1
0/1
x
Kill / PAL
kill
kill / PAL
1 0
x
x
NTSC
NTSC
kill
1 1
x
ABC
PAL
NTSC
PAL
1 1
x
D
NTSC
NTSC
PAL
Table 24: Colour identification algorithm internal implementation
Notes
1
2
2
In order to maintain correct colour identification (i.e. poor VCRs, reflections, etc.) the above algorithm is
implemented where all possible combinations of IDN and IDP are covered.
IDN and IDP are the internal identification signals from the NTSC and PAL identification circuits
respectively.
This information goes to the ASM (automatic system manager) and depending upon the CM3..0 settings the
colour system is set.
For multistandard and trinorma applications it is advised to use the automode (CM3..0 = 1000).
The colour killer sensitivity level for PAL can be increased for noisy signal conditions using PSNS reg 21D2.
0 = Normal PAL sensitivity, killing level typical 26dBuV
1 = Increased PAL sensitivity, killing level typical 21 dBuV
This feature is intended for the ASIAN countries.
Note 1: PAL ident when IDN low in automode/forced PAL is only possible when PSNS=1
Note 2: In automode: PAL ident when XTAL freq A,B,C detected, NTSC ident when XTAL freq D
(3.579545 MHz) detected. In this way misidentification of NTSC as PAL is avoided.
Pin 38
IFVO/SVO
CVBS output
IFVO has a 2.2Vpp signal and after buffering, sound trap application and attenuation (for 1Vpp) it is
supplied to the CVBS1 input (pin 40).
CVBS1, CVBS or Y/C input selection is via INA, INB as indicated in table below.
INA
INB Selected signal
0
0
CVBS1 (from front end, IF)
0
1
CVBS2 (from SCART)
1
1
Y/C
(SVHS or cinch)
Table 25: Video input selection
2
CVBS or Y/C selection is independent of internal/external audio selection which uses the I C bit ADX
For example this is useful for combfilter applications where Y/C can selected together with internal audio;
nd
also switching between two sound sources while receiving CVBS signal from IF (i.e. 2 language selection),
nd
here the 2 sound source is coupled to external audio after bandpass filtering in application.
59
Version 1.0
TDA937X PS N2
Application Note
AN01045
The basic application with combfilter is shown below; also refer to application example at end of report for
application without combfilter.
2
For black/white or SECAM transmissions (detected by the CD3..0 I C bits), the TDA9181 is set in
2
transparent mode via OUTSEL by setting I C bit CMB 1 0 = 1 0
2
For PAL/NTSC colour detection (via CD3..0 I C bits), the TDA9181 is set to combfilter mode via OUTSEL
2
by setting I C bit CMB1 0 = 0 1
The OUTSEL switching signal can also be assigned to a user-defined port of the TDA937X/ if an extra port
is available; in this case the interface circuitry between REFO and OUTSEL is not necessary.
The INPSEL, SYS1 and SYS2 switching signals can be assigned to user defined output ports of the
TDA937X.
Buffer
attn.
Sound
Trap
Buffer
38
CVBS1 (1Vpp)
220nF
Y/CVBS
40
CVBS1
10nF
220nF
14 Y
12
42
To internal
circuits
Y/CVBS
Chroma
10nF
1nF
16 C
select
43
Y/CVBS ext
10nF
Chroma
To internal
circuits
1nF
9 Fsc
TDA9181
INA
INB
combfilter
5V
12K
Sandcastle/Clamppulse
15
2
11
10
OUTSEL
100K
INPSEL
SYS1
SYS2
33p
Chroma/CVBS
+ 4.5V
32
REFO from
Filters/Switches
(4.4 / 3.6 MHz)
AVL/REFO/SNDIF
47K
CMB1
CMB0
From TDA937x
user defined ports
SIF
Figure 11: Combfilter application
60
TDA937x
Version 1.0
TDA937X PS N2
Pins 40, 42
Application Note
AN01045
CVBS1, CVBS/Y
CVBS inputs
CVBS1 and CVBS/Y are advised to be 1Vpp (inclusive sync. amplitude).

The IF video output (pin 38, IFOUT/SVO) is attenuated and ac coupled to ensure a 1Vpp CVBS signal.
The noise detector will becomes active for 100mVrms noise and for CVBS1 = 1Vpp this occurs at a
S/N=20dB. The PHI1 loop switches to slow mode at a S/N=20dB to ensure stable sync performance for
noisy transmissions (less line phase jitter).
The CVBS1 and CVBS/Y source impedances should be low (100E typical) so as to have optimal sync
separator sensitivity and therefore proper compressed sync performance
All CVBS input clamps have a top sync clamp current of 100uA.
The internal clamp principle is shown below.
8V
100A
-1
CVBS input
TDA937X
3.4V
4 A
220nF
Figure 12: CVBS input clamping principle

The top sync of the CVBS is clamped to 3.3V by means of a 100uA current.
During line scan (64us) the input capacitor is discharged with a fixed current of 4uA and for charge balance,
the current during clamping must be [64 / 4] * 4uA = 64uA (sync pulse width = 4uS)
During vertical equalisation, the charge balance is different and the clamping current becomes
[64 / 60] * 4 = 4.26uA.
The value of coupling capacitor is a compromise between fast clamping action and minimum CVBS line sag
and optimum vertical sync performance.
A typical coupling capacitor of 220nF is advised.
The minimum value is 47nF.
For large source impedance in the CVBS application it is advised to use a buffer.
CVBS1 (pin 40) can be used also as a CVBS external input; in this case the IF video must be switched off
2
via I C bus bit VSW.
Pin 44
Chroma
Chroma input
The supplied chroma input burst amplitude should be nominally 300mVpp (75% colour bar).
The input is internally connected to 1.3VDC via 82K.
The external AC coupling capacitor with 82K forms a high pass filter.
The advised coupling capacitor is 1nF.
61
Version 1.0
TDA937X PS N2
Application Note
AN01045
62
Version 1.0
TDA937X PS N2
6.7
Application Note
AN01045
HORIZONTAL AND VERTICAL SYNC GEOMETRY
Pin 16
PH2LF
PHI-2 control loop
Loopfilter:
The loopfilter is intended for stabilising the position of the picture horizontally on the picture tube. This filter
is a first order filter. This pin requires a capacitor value between 1-10nF (C), the recommended value is
2.2nF. The corresponding loopgain is than reduced to 0dB for 3kHz. A value up to 10nF is allowed to make
the loop slower. To avoid disturbances in the loop, the capacitor should be connected to ground pin 18 as
short as possible.
Loopgain:
The static loopgain (K) is 150 us/us, this implies that phase variations (dt0) due to storage time variations
(dtd) are reduced by this factor of 150. This is valid only when a capacitor is connected to the PHI-2 pin. Any
resistor connected externally reduces the loopgain. For R=10M -> K=75, and for R=1M -> K=15.
Shift control range:
The picture can be centred on screen by means of the horizontal shift (HS) via IC bus. The range is
+/-2 us. The delay between the positive going Hout (line transistor switches off then) and start burstkey
pulse (ref PHI-2) must be typical XV6HHILJXUHEHORZ
CVBS
Hout
Sandcastle
td
to
to =
17S
t d
K
Figure 13: PHI-2 timing signal

The horizontal shift range is chosen large enough to compensate for centring errors with a variety of picture
tubes. Under normal conditions it is therefore possible, that active video can be shifted in the retrace period,
(resulting in a folded picture at the side). (see figure 14 on the next page)
63
Version 1.0
TDA937X PS N2
Application Note
AN01045
HS=31
foldover
HS=00
foldover
HS=63
Horizontal deflection current

flyback
scan
flyback
Figure 14: Horizontal shift

Dynamic phase compensation:
The flyback pulse width may not vary on beam current variations because it can not be compensated by the
PHI-2 loop. The phase shift error on screen will be half the flyback pulse width variation. If this demand can
not be reached in the line output stage an external compensation circuit might help to overcome such phase
variations. A current, related to the EHT voltage, can be fed back to the PHI-2 pin via a resistor, R.
+ 8V
Flash protection
+/- 6 A
1K
H
shift
Phi-2 filter
16
C I stat + I dyn
4n7
Figure 15: PHI-2 pin application
64
EHT info
voltage
Version 1.0
TDA937X PS N2
Application Note
AN01045
Two parameters are important:

-
Static sensitivity: 0.33 ms/mA This static shift (Istat) can be compensated with HS
Dynamic sensitivity: 7.6 ms/V Dynamic phase compensation [ms] = 7.6 * Idyn * t / C
In order to maintain sufficient loopgain (K) it is recommended to have R as high as possible, >1M.
The polarity of the voltage on the PHI-2 filter is chosen such, that normal used circuits to measure the EHT
voltage decrease for the beamcurrent limiting function can directly be used. In other words, the EHT info
voltage should drop when the EHT voltage drops.
Flash protection:
A flash protection becomes active when this pin is forced > 6V. The horizontal drive is switched-off
immediately. Once the voltage is < 6V the horizontal drive is switched-on again via the slow start procedure.
To avoid reaction on glitches or spikes, the minimum time the voltage has to remain above 6 Volt is 1 s
before action is taken. To prevent switch-off from the horizontal drive by disturbance on pin 16 when this
function is not used, the flash protection can be disabled by setting DFL = 1
A series resistor of 1kOhm is required for current limitation.
See also XPR function for overvoltage protection.
PHI-2 switched off:

The PHI-2 loop is switched off when the PHI-2 pin is forced externally to 1V. This is for analysis purpose
only.
Pin 17
PH1LF
PHI-1 control loop,
The function of PHI-1 control loop is to synchronise the internal reference with the incoming CVBS signal.
The loopfilter connected to pin 17 is suitable for various signal conditions like strong/weak and VCR signal.
This is achieved by switching the loopfilter time constant by changing the PHI-1 output current. Via IC bus
FOA/B, different time constants can be chosen, including an automatic mode that gives optimal
performance under varying conditions.
Most commonly used settings for FOA/FOB are:
FOA/FOB PHI-1 time constant PHI-1 gating
(1)
00
Fast/slow , auto
Yes, in slow only
(1)
10
Fast/slow
Yes
11
Fast
no
Suitable for:
(2)
Off air reception + VCR via RF (compromise)
Off air reception only, high noise immunity (gating)
Special program number 0 for VCR via RF
External input, optimal for VCR
Table 26: PHI-1 time constant settings

(1)
(2)
Fast or slow depends on whether the noise detector is activated

Not suitable for weak VCR signals via RF (this due to the active gating in slow mode)
Normal off-air reception conditions or cable:

Use FOA/FOB = 0 0 for RF reception on all program numbers, VCR reception via RF possible on all
channels
Use FOA/FOB = 1 1 for external input (VCR, laser disc)
Difficult off-air reception conditions (weak signal and/or interference):
Use FOA/FOB = 1 0 for RF reception on program numbers (optimal off-air reception due to gating)
Use FOA/FOB = 1 1 for special program number (program 0) for VCR reception via RF
Use FOA/FOB = 1 1 for external input (VCR, laser disc)
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To avoid disturbances in the loop, the filter should be connected to the ground pin 18 as closely as possible.
The recommended values for the loop filter are:
C = 4n7 (min 2.2 nF), R = 18 kOhm (max 27 kOhm), C = 1F.
The PHI-1 loop can be switched off by the IC bus function POC. When POC = 1, a valid incoming signal
can only be detected reading IFI (SL is not available). IFI should be connected to the selected video source
for this purpose. It is of course also possible to use an external ident circuit.
When VID = 0, IFI controls the PHI-1 time constant switching between normal (IFI = 1, valid signal
detected), and very slow (IFI = 0, no valid signal detected). In this way, stable OSD is obtained when no
signal is present. This mode is preferred during search tuning.
VCR performance (especially trick modes) must be checked in the fast PHI-1 mode; FOA/FOB = 1 1.
VCR head jump tests (with 16 us phase jumps) must be tested with these jumps during vertical retrace and
not during vertical scan. The sync processing includes special features as increased PHI-1 current during
vertical retrace that ensures fast settling.
Note that in auto mode (FOA/FOB = 0 0) the VCR normal play mode with head jumps during vertical
retrace is displayed correctly.
Pin 33
HOUT
Horizontal drive
This open collector output is meant to drive the horizontal deflection stage. The output is active low, i.e. the
line transistor should conduct during the low period of the output.
The different conditions of the horizontal drive output are:
- Soft start:
- After power-on and all registers are loaded
- When switching-on from stand by using STB
- After release of flash protection on pin 16 (PHI-2)
- Running:
- Normal condition, 45% off / 55% on duty cycle (45% high, 55% low)
- Soft stop:
- When switching-off to stand by using STB
- After activation overvoltage protection XPR (pin 36)
- When the voltage at the 8 Volt supply pins 14 and 39 drops below 6.2 Volt
- Disabled:
- When the 3.3 voltage drops below 2.65 Volt at supply pins 54, 56 and 61.
- Direct stop: - Forcing pin 16 (PHI-2) high activates the flash protection
For optimal sync stability it is recommended to have the output current as small as possible. This can be
achieved by a small series resistor (100 Ohm) and a low output amplitude e.g. <3V. An extra emitter
follower on the output can also be used.
Soft start:
In the N2, the start-up has been refined to further lower the stress and enable application of large picture
tubes with DAF (Dynamic Astigmatism Focus).
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Application Note
AN01045
100
75
Soft
Ton
(%)
50
57
1045
73
12
50
100
150
TIME (MS)
Figure 16: H-out Start-up

The growth of the on-time of the H-out from 0 to 100 % is divided in three parts:
1. Extra slow increase from 0 to 12 %, lasting 57 msec.
2. The purpose is to further lower the stress of the rectifiers on the secondary side of the Fly Back
Transformer (FBT). This is important for applications with high secondary power.
3. Normal increase from 12 to 75 % lasting 73 msec., comparable to N1
4. Very slow increase from 75 to 100% lasting 1045 msec.
5. This last part is related to enable the use of large picture tubes with DAF. These tubes tend to flash
when the EHT rise from around 75% to 100% is too fast. It has been proven in High End concepts that
by slowing down the EHT build-up in this region this flash problem does not occur.
The off time of the line output transistor is identical to the off time in normal operation. The starting
frequency during switch on is therefore about 2 times higher than the normal value. The on time is slowly
increased to the nominal value, the total start-up time becomes now 1175 msec.
Running:
Normal condition, 45% off / 55% on duty cycle (45% high, 55% low)
Soft stop:
During soft stop, the sequence is reversed. T-off remains 28.8 s (output level high) while the T-on (output
level is low) decreases from 35.2 s to 0 s in 43 ms. The H-out frequency increases from 15.625 kHz to 35
kHz.
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AN01045
Switch off
55%
45%
28,8s
28,8s
28,8s
1 mA picture tube discharge

during 38 ms
43 ms
Figure 17: Soft stop timing

Because the RGB outputs are set high during soft stop, the EHT capacitor of the picture tube is discharged
to below half the nominal EHT voltage. To archive this, the RGB amplifier must be able to return in a 1 mA
Iblack measurement current. For example the Philips TDA6107 RGB amplifier can handle this function.
Note: The voltages, derived from the FBT by flyback rectification, also drop to half the nominal value. So
choose scan rectification for supply voltages, which need to be kept nominal as long as possible during
switch-off (e.g. vertical deflection).
2
The internal I C registers and the H-out circuitry are fully functional when only 3.3 Volt is supplied to the
2
device. So only supplying 3.3 Volt, the I C registers of the video processor can be written and the H-out can
be switched on. From stand-by, only 3.3 Volt is needed to switch-on the H-drive pulses. This makes it
possible to switch the power supply from stand-by mode to normal mode. It also enables to supply the 8
Volts of the device from a scan rectified winding of the FBT.
Note: When using 3.3 Volt supply only during start-up, the external pull-up at pin 33 (connected after the
100 series resistor) should be connected also to the 3.3 Volt. In the design of the driver stage, this low
voltage should be taken into account.
See for soft stop, when the voltage at the 8 Volt supply pins 14 and 39 drops under the 6.2 Volt, the
description below at: 8 volt can be monitored.
The TDA937X has three supply pins for 3.3 volts. The functions are:
- Pin 54: Analogue supply (Oscillator, ADC, digital logic TV processor)
- Pin 56: Digital supply to -processor core
- Pin 61: Supply to all output ports of the -processor
When the 3.3 Volt supply voltage drops shortly (spike) below 2.65 Volts, the POR bit is set to 1. The POR
bit is latched, so the next status read will always return POR = 1, irrespective the duration of the power dip.
At the same moment, the H-out is immediately stopped. (To start-up again, the processor has to read the
2
status bytes until POR = 0. Then all I C registers have to be written (preferably setting STB = 0), because
they can be corrupted. Then the set can be started up again writing STB = 1)
The TDA937X has also two supply pins for 8 volts. The functions are:
- Pin 14: Second supply TV processor
- Pin 39: Main supply TV processor
The +8 Volt can be monitored by the SUP bit, SUP becomes 1 when the supply voltage rises above 6.4 Volt
and becomes 0 when the supply voltage drops below 6.2 Volt. Below 6.2 Volt H-out is stopped and the RGB
outputs are blanked (remain below 2.5 volts).
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Pin 34
Application Note
AN01045
FBISO
Sandcastle output/flyback input
Pin 34 is a combined input/output pin. The pin provides a three level sandcastle pulse (see figure on next
page). In this signal both burstkey pulse and vertical blanking pulse are always available, the line blanking
pulse is only present when the external flyback pulse is fed to this pin.
The line flyback pulse, fed to this pin, is used for two functions:
Input signal for the PHI-2 loop.
RGB line blanking. (Without flyback pulse blanking occurs only during the burstkey pulse)
Because of the combined input/output function, the connected circuit should be carefully designed for
optimal performance:
Flyback pulse
The selection of the flyback pulse is important. Please note that the flyback pulse width may not vary on
beam current variations because they can not be compensated by the PHI-2 loop. See further description of
pin 16. On the next page a suitable application is given for the flyback pulse generation.
speedupC
BV2
tuning
flyback C
4K7
line
transistor
27K
main
flyback C
Rs
4n7
8V2
34
flyback input/
sandcastle outp
parasitic
C
150V
To other
applications
(options)
buffer
Figure 18: Flyback input circuit

A capacitive divider in parallel to the line transistor is used to derive a flyback pulse with a height of about
150 Volts peak. In this way we ensure steep edges for optimal jitter performance and optimal blanking width
for the RGB outputs.
This pulse is limited to 8.2 Volts (Vpeak) via a resistor of 4.7 kOhm and a zenerdiode of 8.2 Volt to the ground
of the TDA937X. In the layout, care should be taken that the 30 mA peak current through the diode does not
disturb the IC application (EMC). The input current on pin 36 during flyback must be between 100 and 300
A. The internal clamping level Vclamp of pin 34 during flyback is 3 Volts. With a limited flyback pulse of 8.2
Volts, the series resistor Rs to pin 34 should be between 52 kOhm and 17 kOhm. For optimal reserve, 200
A is recommended, which leads to a value of 27 kOhm.
Vpeak
Limited flyback
pulse
5.3V
3V
2.7V
0V
Clamped flyback
V blanking
2V
Scan
Vertical retrace
3V
Clamping level
Sandcastle
at pin 34
0V
RGB blanking
t rise
Figure 19: Sandcastle pulse
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Application Note
AN01045
The slicing level for horizontal blanking of the RGB outputs lies about 300 mV lower than the clamping level
of 3 Volts. Care should be taken that at the slicing level the steep edges of the clamped flyback pulse are
not degraded by parasitic capacitance Cparasitic of pin 34 itself, devices connected to the sandcastle (e.g.
picture improvement TDA 9178) and the layout. Measured values in applications of this parasitic
capacitance range from 20 pF to 60 pF. With 27 kOhm in series, this leads to an extra delay of 500 nS to
1000 nS before RGB blanking starts. Placing a speed-up capacitor Cspeedup in parallel with Rs can
compensate the influence of this parasitic capacitance.
The correct value is:
Cspeedup = Cparasitic * Vclamp / (Vpeak - Vclamp)
The value of Cparasitic can be determined by measuring the rise time trise of the sandcastle front porch on pin
34.
Ctotal = - trise / { Rs * ln (1 - Vclamp / Vpeak)}
with
Ctotal = Cparasitic + Cmeasuring probe
An advantage of the high slicing level for horizontal blanking is that the steepness of the trailing edge of the
sandcastle pulse is not critical.
An series resistor of 270 Ohm at pin 34 improves the EMC behaviour and should be placed as close to the
pin as possible.
Loading the sandcastle output
If long tracks are connected to the sandcastle output, we advise to use a buffer (see Figure on previous
page).
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6.8
Application Note
AN01045
GEOMETRY (HORIZONTAL AND VERTICAL) AND DRIVE OF VERTICAL DEFLECTION
Pin 20
AVL, EWD
EW drive, Automatic Volume Levelling
The AVL is available in several IC versions and can be switched on/off via the AVL bit.
For 90 degrees versions without E/W drive, the AVL capacitor should be connected to pin 20.
For 110 degrees versions with E/W, pin 32 can be selected using CMB0, CMB1 to apply the AVL capacitor.
For the AVL function see chapter SOUND.
The EW drive is a current output. The output is single-ended and is fed directly to the EW-input pin 5 of the
TDA8358J. The figure below gives the EW output configuration.
U SUP
r
EW
Horizontal
Deflection
Uscan
EW
Modulator
UEW
1EW
20
VREF
600E
1EW
0 - 1200uA
U Pin20
Usup
5V
Uscan + UEW
Figure 20: EW output configuration

The DC voltage on pin 20 is determined by the East-West driver stage input and may range from
1 to 5 Volts. To prevent distortion, the voltage must always be > 1 Volt.
For the TDA 8358J, the reference voltage level (Vref) has a value of 2.5 Volts and is internally set by the
East-West stage.
It is recommended to minimise the EW-output current by means of the EW-width setting.
A minimum EW-current implies a minimum EW-voltage in the line deflection, Uew.
Doing so results in a minimum power supply voltage; Ub = Uscan + Uew
The minimum EW-current is 0mA and can not be negative. This implies that for the EW-current a margin
has to be taken into account for negative current corrections as EHT tracking and trapezium. This margin
can be made with the EW-width setting.
Note that for 16:9 displays another optimum is necessary to enable zoom functionality.
For a correct EHT tracking (compensation of picture height and width for variation of the EHT voltage due to
beam current loading), the tracking must be the same on vertical and EW. The tracking on vertical is +/-5%
(internally fixed) and should also be +/-5% on EW. This EW tracking is determined by Rew.
When we simplify the deflection to a linear system, with picture width direct proportional to the voltage over
the deflection yoke, following formulas give the relations.
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Application Note
AN01045
Uscan = Usup - Uew
(Uew = Iew * Rew + VDC pin 15)
Uscan = - Uew = - Iew * Rew

Uscan
Uscan
-Iew
Rew *
Uscan
(both sides divided by Uscan)
According the device specification:
dIew = 100A for dUscan / Uscan = 5%

Rew can be determined now by:
Uscan
Rew = 5% *
100A
= 500 * Uscan
Rew = 500 /V * Uscan
(for same tracking on vertical and EW)
Example: for a horizontal scan: Uscan = 150V -> Rew = 500 * 150 = 75k.
If Rew < 75k this will decrease the gain and results in less EW correction w.r.t. vertical
If Rew > 75k this will increase the gain and results in more EW correction w.r.t. vertical
In practice the picture width will increase more than the increase of the voltage over the deflection yoke, due
to the applied S correction. This gain factor can vary from 1.3 to almost 2, pending on the flatness of the
tube face and the required S correction. Therefore Rew has to be tuned to the specific application.
It is also possible to use an external circuit to correct the horizontal width for EHT changes. In this case,
HCO should be set to 0. Note that the EHT tracking for horizontal non linear corrections (parabola, corner
parabola, trapezium) always remains active. Only the EHT tracking for picture width is switched off.
See further the section regarding EW geometry adjustments.
Pin 22,21
VRDA, VRDB
Vertical drive
The vertical drive has a current output. The output is balanced which ensures a good common mode
behaviour with temperature and makes the output signal less sensitive for disturbances.
The figure on the next page gives the vertical drive signals with the vertical output stage TDA8358J.
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Application Note
AN01045
TDA8358J
Vdrive-
INA
100
i1
RCV1
2.2k 1nF
22
1nF
Vdrive+
INB
100
i2
21
1nF
RCV2
2.2k
2
1nF
Figure 21: Vertical drive application
i2 (p-p)
637.5
i2 (bias)
400 uA
i2
165.2
0
i1 (p-p)
637.5
i1 (bias)
400 uA
i1
162.5
0
t
Figure 22: Vertical Driver Current
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Application Note
AN01045
Vi (dif)(p-p)
1403 mV
Vi (dif)(bias)
880 mV
Vdrive+
358 mV
0
Vi (dif)(p-p)
1403 mV
Vi (dif)(bias)
880 mV
Vdrive-
358 mV
0
t
Figure 23: Vertical drive signals with TDA8358J

The output voltage is determined by the input resistor RCV1,2 and the output current.
Uout = iout pp * RCV1,2 = 475App * 2.2k = 1.045Vpp
Important for the TDA937X is that the voltage at the driver pins does not exceed 4V.
The value for RCV1,2 = 2k to 2.2k and is determined by the TDA8357J / TDA8358J / TDA8359J.
RCV1,2 and the input capacitors of 1nF must be connected closely to pin 1 and 2 of the TDA8357J /
TDA8358J / TDA8359J for optimal EMC behaviour.
The series resistors of 100 and the HF blocking capacitors of 1nF also improve the EMC behaviour.
Pin 26
VSC
Vertical sawtooth capacitor
This pin requires a capacitor to ground of 100nF +/- 5%. Short connection to the ground pin 18 of the
TDA937X is required. Important: For this capacitor, a type with good temperature behaviour, long term
stability and low leakage must be chosen. Change of the capacitance value due to temperature and/or
ageing leads to a proportional change in vertical amplitude. Tolerance of the external capacitor can be
compensated by means of the vertical slope adjustment of IC bus function VS. The charge current can be
fine tuned with +/- 20%.
The optimal sawtooth amplitude is 3.0 V and is determined by the external capacitor and charge current.
For R = 39k at pin 20, the vertical slope VS = 1F and field frequency = 50Hz, the charge current is 16 A.
For 60Hz the charge current is increased by 19%. The sawtooth bottom-level is 2.3V.
The vertical retrace time is determined by the discharge current of 1mA and lasts about 5 horizontal lines.
Spurious signals on the sawtooth:
Because the sawtooth signal at this pin represents the deflection current, every disturbance influences the
deflection. Notice that 3.0 Vpp ramp amplitude corresponds to approx. 300 lines. Thus dVramp=10mV/line in
one field. Due to interlacing this figure becomes 5mV/line over 2 fields. Or, 1mV disturbance on the
sawtooth means 1/5 = 20% interlace error. Thus, for proper interlacing special attention is required on
grounding from components, related to the vertical sawtooth and the connection to the inputs from the
vertical deflection driver.
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Pin 25
Application Note
AN01045
IREF
Reference current
This pin requires a resistor to ground. The optimal reference current is 100A, which is determined by this
resistor. The voltage on this pin is 3.9 Volts, which leads to the recommended resistor value of 3.9V / 100A
= 39k +/- 2%. A short connection of this resistor to the ground pin 18 of the IC is recommended for EMC
behaviour.
Important: Like the vertical sawtooth capacitor, also for this resistor a type with good temperature
behaviour and long term stability must be chosen. Change of the resistance value due to temperature
and/or ageing leads to a proportional change in vertical amplitude and E/W geometry settings.
The 100A reference current should not be changed because the geometry processor is optimised for this
current. Furthermore the output current of vertical drive and EW are proportional to this current.
Pin 36
EHTO
EHT tracking, Overvoltage protection
The input range for EHT tracking is 1.2 - 2.8V, for a compensation of +/-5% on vertical and/or EW.
The tracking on EW can be switched on/off by HCO, see paragraph above.
The nominal voltage of pin 36 for no compensation is 2V.
The EHT feedback signal must be filtered in order to prevent disturbances in vertical and/or EW deflection.
A compromise has to be determined for tracking speed on normal EHT variation and ripple immunity.
The overvoltage protection is activated when the voltage on pin 36 exceeds 3.9V typical. To prevent false
triggering by glitches or spikes, the voltage must at least remain 1 s above 3.9 Volt to activate the function.
The result is: XPR is set to 1 (and latched) and can be read by the processor
The following procedure is executed:
- The vertical deflection is set to the top of the screen (2 ms)
When OSO = 0, the vertical scan will continue from the top of the screen
When OSO = 1, the vertical drive will remain at the top of the screen
- The horizontal output is disabled after slow stop (43 ms)
- At the same time the RGB drive discharges the picture tube with 1 mA (38 ms)
- The device is set in stand-by mode.
To restart the H-out, write first STB = 0 and then STB = 1.
This function is normally used in USA to switch-off the set when an external detection circuit measures a
too high EHT level. It is also a safe way to switch-off the set when fault conditions are detected. The
function can also be used to switch-off the set using an early warning detector when the supply voltage
starts dropping due to switch-off using the mains switch. In that case, care must be taken that the 3.3 Volt
supply and the 8 Volt supply remain long enough above reset level (2.65 Volt and 6.2 Volt respectively) to
complete the switch-off procedure (45 ms). When the vertical deflection has to be kept at the top of the
screen (OSO = 1) also the vertical deflection supply should remain high enough.
When the function is not used, the switch-off procedure can be disabled by setting XDT = 1. Under this
condition, XPR is still set so the processor part can take the appropriate action when needed.
The 16:9/ 4:3 zoom function
Special linear zoom facilities on both Vertical and East-West gives the possibility to adapt the picture size
for both 16:9 and 4:3 screens, see figure on next page. When zoom is used, the geometry remains correct
in both vertical and horizontal direction. By programming the vertical slope, VS, subtitles at the bottom part
of the picture can be made visible while the picture position at the top of the screen remains fixed (subtitle
mode).
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Application Note
AN01045
Scale factor for H or V Vert. adjust with VX (1% /step)

133% (4/3)
58
100% (1)
25
75% (3/4)
0
Table 27: H/V settings for aspect ratios 16:9 and 4:3
picture 16:9
Hor. Adjust with EW (0.55% / step)

Preset + 18
Preset
Preset - 14
Zoom compress
V : 75%
Zoom expand
H : 133%
Vertical scroll
picture 4:3
subtitle
Zoom expand
Vscroll
subtitle
Shift up/down, V-size constant

H : 133%
V : 133%
picture 16:9
Subtitle mode
Vslope
Zoom expand
Subtitle
Move up bottom, top remains
H : 133%
V : 133%
Vertical scroll
Zoom expand
picture 16:9
Vscroll
H : 133%
V : 133%
Vslope
subtitle
Shift up/down, V-size constant

subtitle mode
subtitle
subtitle
Move up bottom, top remains
Figure 24: Expand and compress mode behaviour
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TDA937X PS N2
6.9
Application Note
AN01045
YUV / RGB PROCESSING AND CONTROL
Pin 45
INSSW2
Insertion input
The voltage on pin 45 and the I C bit IE2 determine whether YUVINT or RGB2 / YPbPr / YUV is selected.
The following tables indicate the selection process.
2
I C bit YUV=0
BLKIN pin 45
BLKIN< 0.4V
0.9V<BLKIN< 3V
0.9V<BLKIN<3V
Table 28
IC function
IE2= *
IE2 = 0
IE2 = 1
Selected sources:
Internal YUV signals
R2;G2;B2 signals
IC function
IE2= *
IE2 = 0
IE2 = 1
Selected sources:
external YUV signals
I C bit YUV=1
BLKIN pin 45
BLKIN < 0.4V
0.9V<BLKIN< 3V
0.9V<BLKIN<3V
Table 29
The YUVINT signals are always selected whenever VPIN45 < 0.4V and is independent of the status of the I C
bit IE2.
RGB2 / YPbPr / YUV signals are selected when VPIN45 > 0.9V with either full or fast insertion being possible.
Full insertion uses the IN2 status to set the IE2 bit; since IN2 status is updated every field blanking period
during the red measuring line period. Full insertion then occurs in the following field.
Fast insertion can be used for OSD applications (note IE2 = 1); also OSD can be displayed in mixed or full
mode (mixed mode, then OSD information also present at insertion pin; for full mode, then DC voltage >
0.9V on insertion pin). Here the OSD is immediately displayed and the IN2 status bit is not of importance.
The insertion pin should be driven from a source impedance which is < 560E
A resistance can be put continuously on pin 45 to ground (100K to ground); pin 45 will rise above 0.9V;
2
using only the IE2 I C busbit then it is possible is used to toggle between YUVINT and RGB2/YPbPr mode
via software.
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Application Note
AN01045
Pins 46, 47, 48
RGB2 / YPbPr / YUV inputs

2
External selection of the RGB2 / YPbPr / YUV inputs is done via I C bits YUV1, YUV0 according to the
following table on the next page.
YUV1
YUV0
MODE
0
0
RGB2 input selected
0
1
Spare
1
0
YUV input selected
1
1
YPbPr input selected
Table 30: YUV mode settings
For RGB2 selection, the nominal input RGB amplitudes is 700mV, for synchronisation a signal must be
2
connected to the relevant CVBS/Y input and I C bit SOY = 0
For YUV selection the nominal input signals for a colour bar with 100% saturation
Y
U=
V=
-(B-Y)
-(R-Y)
1.4 Vpp (1 Vblack-white)

1.78 Vpp
1.4 Vpp
=
=
=
For YPbPr selection the nominal input signals for a colour bar with 100% saturation
Y
Pb =
Pr =
=
=
=
1.0 Vpp
0.7 Vpp
0.7 Vpp
The external RGB2 / YPbPr / YUV signals must be AC coupled.

The RGB2 / YPbPr / YUV signals are clamped to approximately 2V during burstkey period.
The coupling capacitors are a compromise between fast clamping minimum line sag and capacitors of 10nF
or greater can be used.
The source impedance of the RGB2 / YPbPr / YUV signals should be minimised for correct clamping
operation.
For the RGB2 / YPbPr / YUV signals then saturation control acts on the UV signals and black stretch, white
stretch and transfer ratio features act on the Y signal.
It is advised to minimise the track length to the RGB2 / YPbPr / YUV input pins.
Adequate ground shielding of the RGB2 / YPbPr / YUV signal tracks is advised for good interference
immunity.
For YPbPr / YUV modes, the Y signal at pin 47 is internally coupled to the sync circuits and microprocessor
2
when I C bit SOY = 1
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Version 1.0
TDA937X PS N2
Pin 49
Application Note
AN01045
BCL
Beam Current Limiting
For protection of both CRT and LOT against large beam currents, then the average beam current is
monitored as shown in circuit below.
EHT tracking
for horizontal
and vertical
(2V-0.8V)
+8V
2V
100K
120K
36
overvoltage
protection(XPR)
1n
27K
+
3.9V
LOT
EHT
Contrast
3.3V
0.5-1nF
+8V
I-Beam
1-1.5mA
49
3V
>33
220K
10K
30A
6K8
47nF
2n2
Bright
PWL
220
control current
Imax=4mA
+
2V
Figure 25: Basic BCL application

The EHT impedance of 1M and CRT tube 0.5nF is matched with 6K8 and 47nF on the overwind of the LOT
in application so as to have a similar waveform of the EHT information to allow proper BCL action.
The steepness of the waveform on the 47nF can be increased by choosing a higher voltage source than 8V
and larger resistance than 6K8 (note IBEAM flows through 6K8 to CRT capacitor).
High frequency ringing can be filtered to ground via the 47nF capacitor.
The transistor integrator gives fast attack and slow decay times for average beam currents between 1mA to
1.5mA. Furthermore the transistor allows a simpler application with the EHT compensation to pin 36.
The average beam current in the CRT is thus controlled by the external changing voltage on the 3.3uF
capacitor (at pin 49) which originates in the overwind of the LOT; the external voltage on pin 49 first acts on
the contrast and then eventually on the brightness.
The peak white limiting control is implemented internally and the maximum PWL discharge current that
can flow internally is 4mA; the PWL current discharges the external 3u3 capacitor at pin 49 in order to
reduce contrast/brightness dependent upon the input CVBS peak signal.
The internal charge current at the pin is approximately 30uA.
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The detection level of the PWL is on the Y signal and begins at a level of Y= 0.7V BLACK-WHITE for maximum
contrast ( note that Y = 1VBLACK-WHITE also equivalent to 1Vpp or 0.7V BLACK-WHITE CVBS input signal).
When contrast is decreased for example by 6 dB, the operation level of the PWL will also begin to operate
for 6dB extra input Y signal.
To prevent the PWL acting on short video input peaks (e.g. subtitling) or high frequency video, the PWL
only operates when the duration of the peak exceeds 2 s. The soft clipper takes care of the short
peaks/high frequency input, while the PWL acts on the input video peaks which have longer duration.
The soft Clipper operation and PWL detection occurs simultaneously. The PWL / soft Clipper characteristic
curve is indicated below.
4.0
3.0
RGBout
(Vb-w)
Soft
clipper
2.0
1.0
20
40
60
80
08Hex
100
120
130
YIN(IRE)
PWL setting
Figure 26: PWL / Soft clipper characteristic

BCL limiting of the OSD signals internally coupled from the microprocessor to the videoprocessor is
present.
Finally it is advised to have a short return loop to ground for the external BCL capacitor because of the high
input impedance of the pin to prevent interference or coupling from other signals and for PWL current of
4mA.
A capacitor value of > 3.3uF is recommended.
EHT compensation:
The DC information at the bottom of the EHT winding contains information about the EHT voltage. When
the EHT voltage decreases, due to high beam currents, picture width and height increases.
With lower EHT accelerator voltage, electrons travel longer in the deflection fields. This involves more
o
deflection. It can be compensated dynamically via the picture width (EW for 110 tubes) and vertical drive
(bit HCO=1).
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The EHT information is fed via a filter to the UOC EHT-tracking pin 36. Internally this signal modulates the
current of the E/W output and of the vertical drive outputs. The time constant of the filter determines the
dynamic behaviour of the EW compensation. For a correct compensation, the tracking in horizontal (EW)
and vertical direction should be the same. The tracking sensitivity for vertical is set internally in the UOC to
%
o
6.25 /Volt input voltage at the EHT tracking pin 36. For 110 tubes the horizontal tracking sensitivity should
be made the same. For each deflection system the EHT tracking has to be carefully sorted out by trial,
because it depends on the used EHT transformer and picture tube capacitance.
o
For 90 tubes the horizontal increase of deflection can be compensated by modulating the supply voltage
for the deflection with the EHT information.
Pin 50
BLKIN
Black Current input

Vertical Guard input
This pin has functions for beam current measurement and control and vertical guard detection and
blanking.
It receives beam current information from the CRT and controls it to 8uA and 40uA on alternate fields for
the 2 point loop during the measurement.
It is important to limit the current into the pin outside the measurement times to less than 250uA; this can be
achieved by introducing a series resistance and clamping zener at the CRT PCB.
Since the black current is high ohmic, some filtering can be added by having a capacitor close to the pin
(<1nF).
The amount of filtering should not interfere with the measuring times (50% => 75% of measurement
lines).The input signal for vertical guard should be less than 900usec wide for both 50Hz and 60Hz systems
in order not to interfere with the measurement pulses.
The position of the measurement pulses are:
50Hz
60Hz
lines 17 - 20 (odd field)

lines 17 - 20 (odd field)
and
and
lines 329-332 (even field) are visible

lines 279-282 (even field) are visible
A pulse amplitude of >3.75V is required since the detection level is typical 3.45V.
Since capacitance on pin is usually present for extra filtering, then the source impedance of the vertical
guard pulse must be low in order to prevent excessive integration, especially on the falling edge.
If no pulse is detected and the pulse is too wide (>900usecs) then the information is coupled through to the
RGB blanking via the I2C busbit EVG.
A basic application of the pin is shown below including application with the CRT and vertical guard pulse.
Vertical guard
voltage pulse
R1
R2
BLKIN
50
I-beam current
from CRT
Figure 27: Black current input basic application with vertical guard
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Pins 51, 52, 53
RGB outputs
The RGB outputs drive the video output stages from pins 51, 52 and 53 respectively. For nominal input
signals (i.e. CVBS/S-VHS, -(B-Y)/-(R-Y), OSD inputs) and for nominal control settings, the RGB output
signal amplitudes are typically 2V BLACK-WHITE.
The DC level of the complete RGB signals, at RGB outputs, can be varied by varying VG2. The DC gain of
the video output amplifiers should be then chosen so that the DC level at RGB outputs during measurement
is approximately 2.5V when the VG2 DC control setting and cathode DC voltage are in their nominal
operating region. Over the complete range of VG2 the cathode voltage should be above the cut-off of the
CRT in order to avoid extra leakage during leakage measurement.
DC level
at R output
3.5 V
VG2 MIN
2.5 V
VG2 NOM
1.5 V
VG2 MAX
0V
Figure 28: RGB measuring pulses

It is advised to minimise the capacitive load of the output pins, therefore resistors (100) are recommended
in series with the RGB outputs (pin 51,52 and 53.)
The output impedance of the RGB outputs is typically 330 ohms per channel with a maximum
output current of typical 5mA ( peak white).
In the RGB processing, the RGB signals are controlled on
- contrast,
- brightness
- whitepoint adjustment (separate RGB amplitude adjustment per channel)
- cathode drive level (simultaneous RGB amplitude adjustment)
Via the IC bus commands (CONTRAST, BRIGHTNESS, WHITE-POINT RGB) these functions can be
controlled.
The contrast can be changed over a 18dB gain range by means of the IC bus command (CONTRAST: 00 -> 63). Nominal contrast setting is realised with an IC bus setting CONTRAST = 32.
The brightness can be changed , over a of DC-level of 0.7V at the RGBOUTPUT (w.r.t to nominal). by means
of the IC bus command (BRIGHTNESS: 00 -> 63).
The white-point adjustment can be done separately for high- and low light.
White-point adjustment for high-light, a +/-3dB gain per channel (w.r.t to nominal RGBOUTPUT black/white
amplitude) is possible via the IC bus commands (WHITE POINT RGB: 00 -> 63). Nominal high-light
adjustment settings are realised with IC bus settings WHITE POINT RGB = 32.
White-point adjustment for low-light, is possible for the red and green channels. The black levels can be
changed by +/-160mV (w.r.t to nominal RGOUTPUT black level) via the IC bus commands (BLOR/BLOG: 00
-> 63). Nominal low-light adjustment settings are realised with IC bus settings BLOR/BLOG = 32.
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RGB output stages

Looking at the RGB output signals in the figure below several DC-levels can be seen. The DC-levels of the
H- and V-blanking are 0.5V below nominal black level of the video signal.
At the end of the vertical blanking (line 17,18,19,20) the measuring pulses for Continuous Cathode
Calibration (CCC) loop or two point black current stabilisation can be observed.
These measuring pulses have three DC-levels:
-A DC-level of -0.1V with respect to nominal black level during the leakage measurement (LO). This level is
chosen so that it lies close to the black level in order to have an accurate measurement close to the cut off
voltage of the picture tube.
-A pulse of +0,25V with respect to nominal black level, corresponding with a cathode current of 8A
-A pulse of +0,50V above nominal black level which corresponds with a cathode current of 40A.
The pulse-levels of +0.25V and +0.50V can only be measured on alternating fields.
The RGB blanking level tracks with the DC level of the black current measurement pulses. The total video
2
signal (except the measuring pulses for the CCC-loop) can be blanked by activating the I C function RBL
(RGB blanking).
LO
LR
LG
LB
+0.25V
0V
Nominal Black level
-0.1V
Blanking
-0.5V
DC-levels of R-output during the black current measurement pulse

+0.38V
0V
Nominal Black level
-0.1V
Blanking
-0.5V
DC-levels of R-output during the cathode drive current measurement pulse
Figure 29: DC-levels at RGB outputs
The Continuous Cathode Calibration (CCC) loop (or two point stabilisation loop) is an auto-tuning loop
which stabilises the black level (offset) as well as the cathode drive level (gain) of each gun of the CRT
sequentially and independently on alternating fields. The benefit of the CCC-loop can be explained by the
figure below.
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no stabilisation
offset
-no offset compensation

-gain spread
one point stabilisation
gain
spread
Ik
Application Note
AN01045
gain
spread
Ik
two point stabilisation
Ik
VRo
VRo
black current
measurement pulse
VRo
black current
measurement pulse
-gain spread
cathode drive current

measurement pulse
Figure 30: CCC-loop correction mechanisms

This figure shows the cathode current (IK) as function of one of the three video output signals (in this case
the red output) of the one chip.
In case of no stabilisation, the transfer characteristic changes as function of temperature and ageing of the
tube. This results in an offset and gain error (see above figure A).One point stabilisation corrects for offset
variations and a two point stabilisation corrects for both offset and gain spreads as illustrated in figure C
above.
The CCC-loop can be divided into two loops:
-a black level stabilisation loop (offset compensation)
-a cathode drive stabilisation loop (gain compensation)
For the principal of the black current stabilisation loop please refer to application note AN95043 of the
TDA8375.
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TDA937X
Rfeedback
51,52,53 Rdrive
RGB
RGB-outputs
TDA61XX
Rcutoff
drive
correction
offset
correction
Vref.
* D1
LR,LG,LB
40uA
8uA
fieldswitch
10Kohm
50
Black current
input
Figure 31: Basic application of the CCC-loop with the TDA610X

Above the basic application of the CCC-loop with RGB amplifiers is given. In the figure the main two loops
of black level stabilisation and cathode drive stabilisation are shown. The two loops are being stabilised on
alternating fields by means of a field switch. The leakage measurement is carried out every field.
The main difference between the two loops is:
During black level stabilisation internal black level clamps ensure that the DC-levels at RGB-outputs are
independently and sequentially changed so that always 8A flows to the black current input (pin 50).
During the 3L measurement pulses for the black current offset levels. The black current offset correction
signals are stored in an internal capacitor.
During the cathode drive current stabilisation, internal multipliers ensure that the cathode drive level for the
three guns of the CRT are independently and sequentially stabilised so that 40A feedback current flows to
the black current input during the 3L measurement pulses for the drive levels. The correction for the drive
signals are stored in an internal capacitor.
The drive levels at the three cathodes of the tube are always adjusted by the CCC-loop such that the
feedback current is 40A. This means that the gain of the RGB-amplifier, e.g. TDA610X family, is NOT
determining the drive level to the CRT anymore. In order to change the cathode levels at the picture tube
2
four I C bits are added CL3..0.
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The table below shows the corresponding drive levels:

CL3 CL2 CL1
CL0
0
0
0
0
0
1
1
1
1
1
1
1
Table 31: Cathode drive levels
Variation Cathode Drive Level

50VBL-Wh
75VBL-Wh
95VBL-Wh
Changing the cathode level at the picture tube is achieved in the following way:
The CL0123 bits vary the amplitude of the RGB channels together with the internal measurement pulses
generated in a programmable pulse generator. During the 3 measurement lines (LR,LG,LB) these pulse
levels are inserted on the RGB video signals.
Cathode drive level can be adjusted between 50-95V by changing the CL0123 bits. The CL0123 bits are
adjustable in 15 steps and each step result in 3.5V change at the cathode.
TDA935X
Rfeedback
RGB
51,52,53 Rdrive
WPA -RGB
L0,1,2,3
RGB-outputs
Programmable
TDA61XX
Rcutoff
measuring
pulse level
generator
drive
correction
LR,LG,LB
offset
correction
Vref.
* D1
LR,LG,LB
40uA
8uA
fieldswitch
50
Black current
input
10Kohm
Figure 32: Main blocks of the CCC-loop

The drive correction signals (Dr, Dg, Db) will change the gain of the multipliers such that internal generated
measurement pulse give a drive current measurement pulse at the cathode of the CRT corresponding with
a current of 40A. This 40A current will be feedback to the black current input.
The drive correction signals(Dr,Dg,Db) will be stored internally so that, after the 3 measurementpulses(LR,LG,LB), the actual RGB-video signals will have the same multiplication factor as determined
during the drive current measurement pulses.
The same procedure takes place during black current measurement except now the measurement pulses
are adapted such that a 8A cathode current is measured by adding the offset correction signals (Br, Bg ,
Bb) to the RGB-signals. By means of the field switch the programmable measurement pulse level
generator switches the internal measurement pulse level corresponding with a 40A cathode to a internal
level corresponding with a 8A cathode current.
Changing the WPR/WPG/WPB registers works on the same way as changing the CL0123 bits except for
these three registers act on each individual RGB signal where the CL0123 bits act on all three RGB-signals
together.
So when changing the registers the internal generated measurement pulses are adapted at the input of the
CCC-multiplier. The CCC-loop adjust itself so that the black current measurement pulses at the black
current input are constant (8A and 40A).
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Start up behaviour of the CCC-loop

After H-out is released the RGB-outputs can be blanked (see RBL and RGBL bits). When the CCC-loop is
active, the 250mV and 500mV measuring pulses are present at the RGB-outputs.
The picture tube is warmed up via the 250mV and 500mV measuring pulses but due to the fact that the
tube is cold the corresponding 8A and 40A pulses are not present at the black current input so the gain
as well as the offset is set to maximum by the CCC-loop. This means that the amplitude of the 3 measuring
pulses is maximum at the RGB outputs (with RBL=1, the actual scan reminds at blanking level). By means
of these pulse the tube is warmed up. At the moment that the tube is warm the CCC-loop starts to measure
8A and 40A at the black current input pin and at that moment BCF becomes 0 which will be followed by
releasing the RGB-outputs.
2
For applications without a picture tube the CCC-loop can be switched off by means of the I C control bit
AKB (Auto Kine Biasing).
Fixed beam current discharge:

When the set is switched off or switched to stand-by by setting STB = 0, the RGB outputs are set for a fixed
beam current of 1 mA to discharge the picture tube (during switch-off) in a controlled way.
During the switch-off-period the vertical deflection can be placed in an overscan position by setting the
OSObit to 1 so that the discharge is not visible on the screen. In this case the switch off procedure is as
follows:
-
The vertical deflection is immediately directed to the top of the screen (within max. 2 ms fly-back time)
The RGB outputs are set for a beam current of 1 mA (measured via the black current input)
OSO = 1 (the vertical deflection stays in the overscan position)
OSO = 0 (the vertical deflection operates normal)
The advantage of the fixed beam current switch-off is:

No bleeder resistor for discharge needed (cost)
The delta discharge voltage is controlled. It is advised to keep the delta discharge voltage below
500V/ms for better EMC behaviour.
The discharge current of 1mA is controlled by the black current loop and it is possible to discharge with
higher current by connecting a current divider on black current loop.
Over the series resistor (10K) at the black current input diodes should be placed in order to make the
discharge current of 1mA possible via the black current input. Without this diodes the voltage drop over the
series resistor is too high (voltage drop: 1mA X 10K =10V) so the fixed beam current switch-off function
will not perform correctly.
The 1mA discharge current is during 38ms after switch-off is detected. During this time the supply voltage of
the IC should not drop down below 6.7V. This level is indicated with the SUP-bit. When the supply voltage
drops below 6.4V than the SUP-bit become 0.
When the set is switched off then a supply sense circuit has to be made in order to trigger the fixed beam
current switch-off function . For this triggering it is best to monitor when the scan supply voltage for the
horizontal deflection stage starts to decrease (or another supply which start to decrease very fast after
switch off). The output signal of the scan supply sense circuit has to be applied to the (EHTO-pin) and XDT
has to be set to 0 to enable the switch-off. Under normal operation the output signal of this circuit has to be
below the 1V.
An example of a scan supply sense circuit is given on the next page.
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AN01045
V scan supply horizontal deflection

+5V
330K
+ 22
2.4V
47K
to EHTO
pin
15K
Figure 33: Scan supply sense circuit

This circuit detects when the scan supply voltage starts to decrease and can generate a signal for the fixed
beam current discharge function.
It is important that the +5V in this circuit remains stable during the slow stop procedure SUP
It is important that the 8V does not dip under 6.7V (SUP generated) during the slow switch off duration of
38ms; the RGB outputs will remain high then once the 8V supply is above 6.7V
When a bleeder resistor is used to discharge the picture tube than it is not needed to use the fixed beam
current discharge function. In this case the RGB output can be blanked by making RBL bit 1 during the
switch off
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AN01045
6.10 PICTURE IMPROVEMENT FEATURES
FFI function
This feature improves IF video performance for excessive phase modulation that might occur in some
market areas (i.e. India).
For normal modulation, the standard loop filter is applied.
For phase modulation (FM modulation of the IF carrier) and over modulation, the requirements of the IF
PLL loop filter are contradictory.
Phase modulation requires the loop response to be fast in order to follow the phase modulation while over
modulation requires a slow response in order that there is no reaction to temporary phase inversions (180
phase jumps) in carrier when the modulation depth exceeds 100%
When the I2C busbit FFI = 1, the IF PLL time constant remains normal for low carrier level, while for high
carrier levels the IF PLL time constant is increased. In this way a better compromise between phase
modulation and over modulation is achieved as shown below.
Note: When the I2C busbit FFI = 1, this had NO influence on search tuning speed.
High carrier
amplitude :
Adapted PLL time
constant
Better for phase
modulation (FM)
Low carrier
amplitude :
Normal PLL time
constant
Better for over
modulation
FFI = 1 :PLL time constant automatically adapted to carrier level

Better behaviour for phase modulation (FM) and over modulation
Figure 34: FFI principle
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Peaking function, ratio pre-shoot / overshoot:

A block diagram is shown to indicate the principle.
Y-signal
summing
stage
RP1.0
peaking
function
Ratio
preshoot
overshoot
Min.
peaking
Vout
Max.
peaking
Vin
Figure 35: Peaking operation principle

The peaking function can be made asymmetric in black direction via the I2C busbits RP1, RP0 as indicated
in the following table.
RPO1 RPO0
0
0
0
1
1
0
1
1
Table 32
Ratio Preshoot Overshoot

1:1
1 : 1.25
1 : 1.5
1 : 1.8
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The peaking control gives peaking in both directions (i.e. pos. / neg. peaking) as indicated in peaking control
curve as below.
80
60
40
20
0
0
10
20
40
30
-20
DAC (HEX)
Figure 36: Peaking control curve
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Black Stretch:
The black stretcher is a peak detector which detects the incoming luminance signal between 0 and 50IRE. It
operates in a window defined for 50Hz and 60Hz systems as follows:
The window is at 3us after begin line scan and ends 3us before end line scan; it continues for
- 300 lines beginning at line 131 to 431 for 50Hz systems
- 256 lines beginning at line 131 to 387 for 60Hz systems.
As the amount of black in the video increases then the black stretcher is eventually switched off (this is for
approximately 10% black in the total signal.
The incoming peak level (towards black) of the Y signal (0 50IRE) is internally stored in a capacitor with
an attack/delay time constant of approximately 200ms and depending upon the difference of the blanking
level and the stored grey level, is the Y signal stretched towards black according to the black level
characteristic shown below.
OUTPUT (IRE)
100
80
60
40
20
Max. black
level shift
(Y-signal)
INPUT (IRE)
0
level shift
at 15% of
peak white
20
40
60
80
100
-20
Figure 37: Transfer characteristic of black stretch.

The black stretch performance can be judged by having a black pluge with grey background.
Switching on and off the black pluge results in black stretching in the grey signal and also the attack/decay
time constants can be measured at the RGB outputs.
Note: The size of the black pluge must be small enough so that the black stretcher stays operating; if the
black pluge exceeds approximately 5% of the total video signal, the black stretcher switches off.
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Dynamic skin control

Since the human eye is very sensitive to skin tone, then this features allows dynamic skin tone correction of
colours/hues in the skin tone region.
The U and V signals are detected in a window around the skin tone region and within this window correction
shifts the skin colour to a correction angle in the UV plane as shown in the dynamic skin control
characteristic shown below.
The amount of correction is dependent upon the amplitudes of the incoming YUV signals and a correction
angle of 45 (+/- 22.5) degrees is valid for a signal amplitude of 75% and having a colour saturation of
50%.
In principle tones at the outer parts of the detection window and near the skin tone point will be hardly
corrected and tones in between this will be corrected most will be corrected most; also for small or high
saturated colours then correction is also less (for 50% saturated colours, correction is most).
The feature can be switched on/off via the I2C busbit DSK.
V
red
fully saturated colours
I-axis
yellow
U
Figure 38: Dynamic skin control
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AN01045
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Application Note
AN01045
6.11 SUPPLY, GROUNDING AND DECOUPLING
Pin 54, 56, 61
VddA / VddC / VddP
3.3 Volt Supplies
The TDA937X PS N2 has three supply pins for 3.3 volts. The functions are:
Pin 54 (VddA) : Analog supply (Oscillator, ADC, digital logic TV processor)
Pin 56 (VddC) : Digital supply to processor core
Pin 61 (VddP) : Supply to all output ports of the processor
In the demo board there is separate decoupling for all the 3.3V supply pins.
It is possible to combine the VddC and VddP decoupling for PCB layout optimisation.
It is advised to have separate decoupling for VddA.
The decoupling capacitors should be positioned as close to the pins as possible and grounded to the
ground plane under the IC.
During normal operation as in stand-by, all 3.3 Volt supply pins must be supplied.
2
Note that when 3.3 Volt is supplied, also the I C registers of the video processor can be written and the Hout can be activated to start-up.
A low cost 3.3 V regulator circuit is shown at end of chapter where the 3.3 V is derived from an existing 5 V
supply
Pin 14, 39
VP2 / VP1
8 Volt supplies
This voltage supplies the analog part of the video processor. The current consumption is divided equally
between the two pins.
Short supply decoupling is important for both pins, for pin 14 with external capacitor to ground pin 18, for pin
39 with external capacitor to ground pin 41. Take care that at switch-on of the +8 Volt supply the rise time at
both pins is about equal.
In stand-by condition the 8V IC-supply can be switched off as to save energy. When the 3.3 Volt supply is
2
present, still all I C registers of the video processor can be written and the H-out can be activated to startup.
This enables to supply the +8 Volts from scan rectification of a winding of the FBT.
The +8 Volt can be monitored by the SUP bit, SUP becomes 1 when the supply voltage rises above 6.5 Volt
and becomes 0 when the supply voltage drops below 6.2 Volt. Below 6.2 Volt H-out is stopped and the RGB
outputs are blanked (remain below 8V)
Pin 15
DECDIG
Digital Decoupling
This pin decouples the internal digital supply voltage of the video processor and minimises the disturbance
to the sensitive analogue parts.
For optimal decoupling use a capacitor of 220 nF with minimum track length to VssA (pin 12) which is the
main digital ground of the video processor.
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Pin 19
Application Note
AN01045
DECBG
Bandgap decoupling
The bandgap circuit provides a very stable and temperature independent reference voltage.
This reference voltage (4.0 V) ensures optimal performance of the analogue video processor part of the
TDA937X PS N2 and is used in almost all functional circuit blocks. Short decoupling to ground pin 18 of the
external capacitor is important.
For best performance, a capacitor value of 2.2 F in parallel with a high frequent decoupling capacitor
(100nF or 22nF) is recommended.
Pin 9, 12,
Pins 18, 30, 41
VssC/P , VssA
GND3 / GND2 / GND1
Ground microprocessor
Ground videoprocessor
The TDA937X N2 PS has 5 ground pins. The functions are:

Pin 9 (VssC/P)
Digital ground processor core and peripherals
Pin 12 (VssA)
Analog ground processor and digital ground TV processor
Pin 18 (GND3)
Analog ground 3 of videoprocessor
Pin 30 (GND2)
Analog ground 2 of videoprocessor
Pin 41 (GND1)
Analog ground of videoprocessor
In the layout, it is best to design a ground plane underneath the IC and connect all ground pins as short as
possible to this ground plane. Note that the ground plane should have a low impedance, no bridge wires or
0 Ohm SMDs are allowed. Low ohmic connection of all ground pins is very important for performance.
A ground plane gives following advantages:
optimal connection between all ground pins
easy grounding of peripherals (short connection of single components to ground when SMDs are used)
no other signal tracks under the IC (radiation)
optimal for EMC
For easy routing, it is possible to make an outside connection from the ground plane via pin 55 (VPE).
Grounding of this pin has no consequences for operation and in this way a ground is available for supply
decoupling of the supply pins 54, 56 and 61.
Note: Do not connect pin 57 (oscillator ground) to the ground plane. See below.
Pin 57
OSCGND
Ground oscillator
This ground pin is only intended to use for connecting the two capacitors of the oscillator. This pin should be
left floating. No other components should be connected to this pin.
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Application Note
AN01045
All Pins
Pin protection for ESD
All IC-pins have internal protection diodes, one to supply and

one to ground for ESD protection, see
Under normal operation and supply-off condition these diodes
may not conduct. Otherwise excessive current can flow through
these diodes and/or internal circuit parts and the IC will be
damaged.
positive
All ESD protection diodes meet the specification of both Human

body and Machine model. Nevertheless for safe operation each PinX
pin voltage should remain in between:
For processor related pins:
Normal IC operation and supply is 3.3V:
(1)
4.0V
No supply (0 V) :
0.7V
For video processor related pins:
- normal IC operation and supply is 8V:
- in stand-by condition and supply is 0V:
- 0.7V.+
internal pin
circuitry
Ground
- 0.7V.+
Figure 39: ESD pin protection
- 0.7V.+ 8.7V
- 0.7V.+ 0.7V
(2)
(1) processor I/O pins, configured as open drain, can handle +5 Volt e.g. when connected via pull-up
2
resistors to the + 5 Volt for I C..
(2) The tuner AGC output pin 27 may have a higher voltage, V27 < Vcc + 1V. This makes the application with
the tuner more easy.
Note:
- When the supply =0V avoid that IC pins are supplied by external connected components.
We have had no problems so far when the continuous protection diode current is less than 1mA.
- Maximum voltage for CVBS/Y input pins is 5.5V. This to avoid parasitic effect at the pin.
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Supply start-up, shutdown, I C, protections

2
The coherence between supply voltage, I C and the protections is given under the following conditions:
3.3 Volt
8 Volt when supplied from the main supply
8 Volt when supplied from the Flyback Transformer, using Low Voltage Startup
3.3 Volt supply
A POR generation is directly coupled with the VddA 3.3 V supply at pin 54
A POR can be generated from:
- External reset pulse at pin 60
- Internal POR from video processor when VddA dips less than approximately 2.5V.
- Internal POR from uprocessor when VddA is typically 2V (refer to report for exact details)
For further details of POR generation internal architecture see Reference [9]
The internal POR generation for the video processor is treated in the following description.
We will cover the 4 different situations as given in the picture below.
3.3
2.65
Supply
3.3 V
POR
* Reset to 0 first status register read after the voltage on 3.3 Volt supply pins is above 2.65 Volt
I2C
bus
** When POR = 1, read till POR = 0 and rewrite all I2C registers with STB = 0. Then set STB = 1
STB
Hout
Reset
Condition
Reset
Condition
Slow
Start
Reset
Condition
Slow
Start
Slow
Start
Figure 40: POR generation for internal videoprocessor

1. When the 3.3 supply line rises, the processor has to read continues the POR bit. When it is possible to
2
read (I C hardware is functional) the POR bit will read 1 as long as the 3.3 Volt supply voltage is below
2.65 Volts. The first read of POR after the moment the 3.3 Volt supply rises above 2.65 Volts will still
return POR = 1 but resets POR to 0. The next read will return POR = 0.
2
Once POR = 0, all I C registers have to be written, preferably keeping the set in stand-by writing STB =
0.
After this initialisation the H-out can be started by writing STB = 1. The H-out will start to run according the
1)
slow start procedure and continues in normal mode.
2. When the 3.3 Volt supply voltage drops shortly (spike) below 2.65 Volts, the POR bit is set to 1. The
POR bit is latched, so the next status read will always return POR = 1, irrespective the duration of the
power dip.
At the same moment, the H-out is immediately stopped. The reason for this action is that the contents of
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all I C registers cannot be guaranteed any more once the 3.3 Volt supply voltage drops below 2.65 Volt.
2
To prevent unpredictable behaviour due to wrong I C settings, the device is put in reset condition.
2
To start-up again, the processor has to read the status bytes until POR = 0. Then all I C registers have
to be written (preferably setting STB = 0), because they can be corrupted.
Then the set can be started up again writing STB = 1.
3. When the 3.3 Volt supply drops below 2.65 Volts, immediately the H-out is stopped and the device is put
in reset condition.
4. Once the voltage rises again above 2.65 Volts, the procedure is the same as written under 1.
2
Note that the 3.3 Volt supply is key for basic operation of the processor part, the digital part (I C
registers) and the H-out drive circuit. Checking the 3.3 Volt supply reading POR and taking appropriate
action when POR =1 has absolute priority over all other matters.
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8 Volt, when supplied from the main supply
Slow
Start
Slow
Stop
8
6.4
6.2
Supply
8V
SUP
STB
Hout
Slow
Start
Slow
Start
Slow
Stop
1 mA
disch
RGB
Slow
Start
Slow
Stop
1 mA
disch
6V
V pin 16
PHI 2
3.9 V
V pin 36
EHTO
XPR
* Reset to 0 first status register read after the voltage on pin 36 is below 3.9 Volt
Figure 41: 8 Volt supply from main supply

2
1. We assume that the 3.3 Volt supply is ok and all I C registers have been written.
When the 8 Volt supply rises, the SUP bit will toggle from 0 to 1 once the level reaches 6.4 Volt.
We advice to check this bit to ensure that the power supply is functioning properly.
At the moment STB is written 1, the H-out will start according the slow start procedure and continue
running in normal mode.
Note that it is allowed to write STB = 1 before the 8 Volt is present (only 3.3 Volt present). In that case,
the H-out will start according the Low Voltage Start-up procedure including slow start.
However, first when the 8 Volt is present, all other circuits will be functional and the CCC loop will start to
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stabilise the RGB drive.

2. The moment the 8 Volt supply drops below 6.2 Volts SUP is set to 0, the H-out is switched off using the
1)
slow stop procedure and the RGB outputs are immediately blanked.
When the 8 Volt supply rises again (suppose the drop was due to a short overload condition of the
supply), at 6.4 Volts SUP becomes 1, H-out starts again via the slow start procedure and the CCC loop
will stabilise the RGB drive.
So when a short dip occurs in the 8 Volt supply, the IC will restart itself without any intervenience of the
processor part. When required, the processor can always take action by monitoring the SUP bit
The SUP bit is reflecting the actual condition of the 8 Volt supply line. It is not latched. To prevent
unstable behaviour, SUP becomes 1 at 6.4 Volt and returns to 0 at 6.2 Volt
Note that we assume that the 3.3 Volt supply remains stable under the above condition, else a complete
2
start-up is needed (POR check and writing all I C registers)!
3. The flash protection can be activated by pulling the voltage at the PHI-2 pin 16 above 6 volts using an
external flash detection circuit. To prevent reaction on glitches or spikes, the time pin 16 has to be kept
above 6 Volt is 1 s. After 1 s the H-out is immediately stopped to protect the line transistor and the
RGB outputs are blanked.
When the voltage level on pin 16 drops again below 6 Volt, the H-out will start again via the slow start
procedure and the RGB outputs are released
The flash protection is hard wired to ensure reliable behaviour under condition of heavy disturbance. The
status cannot be read by the processor part.
To prevent false triggering when it is not used, the flash protection can be disabled setting the bit DFL to
1.
4. The X-ray protection is activated by pulling the voltage on pin 36 above 3.9 Volt using an external
detection circuit. Also here the voltage has to be kept at least 1 s above 3.9 Volt to prevent reaction on
glitches and spikes. After 1 s the following happens:
- XPR is set to 1
- The vertical deflection is set to the top of the screen (takes 2 ms).
If OSO is set to 1, the vertical deflection drive is kept at the top of the screen.
If OSO is set to 0, the vertical deflection will keep running from the top of the screen down.
- Then the H-out is stopped according the slow stop procedure (43 ms)
- At the same time the RGB outputs are set to discharge the picture tube with 1 mA during 38 ms
- The device is set in stand-by condition.
The protection is generally used for two purposes.
The first is by an external circuit, measuring the EHT of the picture tube. In USA, the regulations
prescribe to shut down the TV set when the EHT runs too high to prevent too high levels of X-ray
radiation. A simple circuit measuring the height of the flyback pulse from an FBT winding does the job.
The second is to initiate a defined switch-off when the power supply is switched off using the mains
switch. Using an early warning detection circuit, the switch-off procedure can be activated by hardware.
When using this feature, one should take care that the 8 Volt and the 3.3 Volt remain above reset level
(6.2 Volt and 2.65 Volt respectively) and when OSO is set to 1 also the vertical deflection voltage
remains high enough to keep the deflection on top of the screen during 45 ms after triggering.
The XPR is latched, and only when the bit is read while the voltage at pin 36 is below 3.9 Volt again,
XPR is set to 0. When XPR reads 0 again, the set can only be switched on again by first writing STB = 0
and then STB = 1. Failing to toggle the STB bit will keep the set in stand-by mode!
The switch-off procedure can be disabled by writing XDT = 1. In that case, still XPR will be set to 1 and
latched when the voltage at pin 36 is pulled above 3.9 Volt larger than 1 s. The processor can take the
appropriate action when reading XPR = 1. Also when this feature is not used we advice to set XDT = 1 to
prevent false triggering.
5. When writing STB = 0, the device goes to standby mode via the same procedure as described above:
The vertical deflection is set to the top of the screen (takes 2 ms).
If OSO is set to 1, the vertical deflection drive is kept at the top of the screen.
If OSO is set to 0, the vertical deflection will keep running from the top of the screen down.
Then the H-out is stopped according the slow stop procedure (43 ms)
At the same time the RGB outputs are set to discharge the picture tube with 1 mA during 38 ms
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Application Note
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The device is set in stand-by condition.
8 Volt, when supplied from the Flyback Transformer (scan rectification) using Low Volt. Startup
The main difference with 8 Volts from the main supply is that the presence of the 8 Volt supply is now
pending on the availability of the H-out drive.
2
1. The 3.3 Volt is ok and all I C registers are written. Then the Low Voltage Startup is initiated by writing
STB = 1. H-out will start according the slow start procedure. The secondary voltages of the FBT will rise
and when the 8 Volt supply reaches the level of 6.4 Volts, SUP becomes 1. At that moment the RGB
outputs are released and the device is fully functional.
2. When the 8 Volt supply drops below 6.2 Volts (e.g. due to a short overload), SUP is set to 0, the RGB
outputs are blanked and the H-out is stopped via the slow stop procedure. Because the H-out stops, also
the 8 Volt supply will not be present any more.
The processor part can detect this condition by monitoring the SUP bit. To restart the device using the
Low Voltage Startup, write first STB = 0 followed by STB = 1. The STB bit has to be toggled to re-enable
the Low Voltage start-up. Only writing STB = 1 has no effect.
3. When the flash protection is activated by pulling the voltage at pin 16 above 6 Volt, the H-out is
immediately stopped and the RGB outputs are blanked.
Because the H-out stops, also the 8 Volt supply will go down and when the voltage reaches 6.2 Volt,
SUP is set to 1 which can be monitored by the processor part. To reinitialise the Low voltage Startup
write STB = 0 followed by STB = 1. The procedure is identical as described in point 2 above.
For details about the flash protection, please refer to point 3 in the "8 Volt supplied from main supply"
section.
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3
Slow
Start
Slow
Stop
8
6.4
6.2
Supply
8V
SUP
STB
Hout
Slow
Start
Slow
Start
Slow
Stop
1 mA
disch
RGB
Slow
Start
Slow
Stop
1 mA
disch
6V
V pin 16
PHI 2
3.9 V
V pin 36
EHTO
XPR
* Reset to 0 first status register read after the voltage on pin 36 is below 3.9 Volt
Figure 42: 8 Volt supplied from Flyback Transformer

4. The stop procedure when the voltage on pin 36 is pulled above 3.9 Volt is the same as described in
point 4 of the section "8 Volt supplied from main supply". Also the details of the X-ray protection can be
found here.
The difference is that also the 8 Volt drops because the H-out is switched off.
The processor part can use XPR and SUP to check this condition. To restart, STB has to be written 0
and then 1 again to reinitialise the Low Voltage Startup.
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When the X-ray protection is used to switch-off the set when the mains switch is switched off, extra care
has to be taken that the 8 Volt supply remains long enough above 6.2 Volts to finish the switch-off
procedure (45 ms). In practice, a very early warning is needed to reach this timing.
5. When STB is set to 0, the device switches off according the procedure as described in point 5 of the
previous section. Also now the 8 Volt goes down when the H-out is completely stopped. When using
scan rectification for the 8 Volt supply, the 8 Volt will still be present during almost the complete slow
stop time.
General
As can be seen, some status bytes are reset to 0 the first status read when the fault condition is cleared
(POR, XPR). So it is important to have in the software a status byte read routine which checks each read
the relevant bits so the appropriate action can be taken and no bit set is cleared by accident.
Low cost 3.3 Volt regulator circuit

The recent advances in CMOS process manufacturing techniques and processes have made it possible to
fabricate Very Large Scale Integrated (VLSI) circuits which not only consume less power but in addition
demonstrate lower radiated electrical noise (EMC). The microcontroller section of the TDA937X devices
requires a 3.3 V power supply, rather than the more common 5 V supply.
In the reference application example you can find a circuit to generate this 3.3 V supply in target
applications that uses a 5 V supply.
It is not advisable to use a zener regulator for regulation over the required load current range, a large
power-type zener would be required. This is due to the relatively large zener dynamic resistance exhibited
by smaller (300 mW) power zener devices.
Additionally, if a power-type zener is employed, the standing or quiescent current consumption would be
unacceptably large. The cost of these devices also makes this an unattractive proposition. For the above
reasons, simple zener regulators do not provide a suitable solution.
Power supply rail filtering of the 3.3 and 5 V supplies is recommended through the use of LC type filters.
Typical component values for the filtering are in the region of 5 - 10 H for inductors and 10 - 100 nF for
capacitors. These components are for high frequent filtering only, in addition 10 to 100 F capacitors are
needed in parallel as supply buffer.
Simple Discrete Linear Regulator

The circuit 105 provides a solution for generating a stable 3.3 V supply from an existing regulated 5.0 V
supply.
The main features are:
Stable output voltage over the load current range of 3 to 65 mA.
Output voltage accuracy principally dependent on the accuracy of the zener diode (available in 5%, 2%
or 1% tolerances).
Low quiescent current.
Low drop-out.
Input voltage intolerance (supply voltage rejection ratio).
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AN01045
Circuit Description:
+5V
R1
1k
R2
560
Q2
BC548
Q1
BC548
+ 3V3
D1
BZX79C2V7
0V
Figure 43: Schematic of 3.3V regulator circuit

Diode D1 provides a reference voltage for the circuit. The current flowing through D1 is typically 5.0 mA, this
being the sum of the currents flowing through resistors R2 and R1. The base of transistor Q1 will be
maintained at approximately one VBE higher than the zener voltage, ie: 3.3 V.
Since the emitter of transistor Q2 is also 3.3 V, the base of Q2 will be at approximately 3.9 V. This means
that Q1 is in its linear region, acting as a common emitter amplifier. The gain of this stage is its collector
load resistor R1 divided by the dynamic resistance of the zener (typically 30 Ohm).
Transistor Q2 is an emitter-follower stage, lowering the open-loop output impedance of the circuit.
The 3.3 V output should be linked into the reset and EEPROM.
Circuit Components
All resistors can be 5% tolerance parts, since their absolute value does not influence the circuit
characteristics greatly. The zener diode can be 5% tolerance also, although under the extremes of load
current and input voltage variation it is possible for the output voltage to fall below the minimum supply
voltage of 3.0 V for the microcontroller. If these extremes are foreseen a closer tolerance part, such as 2%,
should be used.
Components are leaded type components, suitable alternative surface-mount components are the
BZX84C2V7 (D1) and BC848 (Q1 and Q2).
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Parameter
Output voltage
Value
Minimum Typical
3.31
3.15
Units
Maximum
3.45
Output Current
90
mA
Quiescent current consumption
5.0
mA
0.8
Output Resistance
Table 34: Regulator specifications
(Tamb = 20 C, Vs = 5.0 V)
1 At Io = 60 mA, using 5% tolerance zener.
2 1 mA < Io < 80 mA.
Voltage Regulation
(Io=60mA)
5.6
5.5
5.4
5.3
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
Vs (V)
3.1
3.15
3.2
3.25
3.3
3.35
3.4
3.45
Vo
Figure 44: Voltage Regulation
Output Characteristic
(Vs=5.0)
3.5
3
2.5
2
o (V)
1.5
1
0.5
0
0
20
40
60
80
100
Io (mA)
Figure 45: Output Characteristic
106
120
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6.12 EMC LAYOUT

This brings us the final layout around UOC. It is important to visualise all signal loops, especially those for
high frequencies. Although other patterns are possible, only the equipotential ring approach makes it
possible to solve EMC problems without introducing another one. This avoids costly redesigns during
television chassis development.
Future EMC demands will be more severe. It may become necessary to use multi-layer PCB. The principles
in this chapter remain valid, only the equipotential ring will then become a ground layer. The common IC
packages will be Quad Flat Pack (QFP) instead of Shrunk DIL (SDIL). Smaller SMD-type components will
be commonplace.
Guard Ring
1
Xtal
Vertical
Amplifier
1
2
Tuner
Iblack
Local
reference
ground
IF-PLL
loop
filter
IF
SAW
RGB
to
CRT
Vertical
ref.
Figure 46: Final EMC optimized UOC ground pattern
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7.1
Application Note
AN01045
ALIGNMENTS
TUNER AGC
The tuner take over point can be adjusted in 64 steps in a range of 0.4mV to 150mV typical. Resolution
becomes approximately 51dB/64 is 0.8dB/step.
Method 1:
Apply a (e.g. 1mVrms in the example below) RF signal to the aerial input of the tuner. Increase by IC bus
the take over setting such that the voltage at the tuner output pin 27 (MP1) drops 1V below its maximum
voltage.
Method 2:
An alternative method is to align for a certain tuner IF-output level (MP2, e.g. 100mVrms in the example
below)
Such a method is more accurate in case the maximum tuner IF-output level is important.
Notice:
- This adjustment requires a compromise between S/N ratio and intermodulation. The intermodulation will
increase when the tuner output amplitude becomes too high. See tuner specification, often < 107dBV.
- The IF-amplitude variation (slip) depends on the tuner AGC loop gain, see tuner output pin 27.
- The 1mV also depends on tuner gain and SAW filter insertion losses, see figure below.
Tuner
SAW filter
0
MP2
IF-input
14
RF
input
gain
0-40 dB
tuner
output
20
IF input
Onechip
insertion losses
14+6=20dB
MP1
Tuner AGC out
Figure 47: Tuner AGC; RF to IF signal path.

RF input
Tuner gain
Tuner output
1 mV
+40 dB
100 mV
60 dBV
+40 dB
100 dBV
Table 35: Signal attenuation/gain values in front end
109
SAW
-20 dB
-20 dB
IF input
10 mV
80 dBV
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Application Note
AN01045
GEOMETRY
Alignment of horizontal and vertical geometry

In the types which are intended for 90 picture tubes the following geometry parameters can be adjusted:
- Horizontal shift
- Vertical amplitude
- Vertical slope
- S-correction
- Vertical shift
The types which are intended for 110 picture tubes have an East-West control circuit in stead of the AVL
function. The additional controls for these types are:
-
EW width
EW parabola width
EW upper and lower corner parabola correction
EW trapezium correction
Vertical zoom
Horizontal parallelogram and bow correction.
For optimal geometry, it is important to align the vertical and horizontal registers in the correct sequence. If
certain registers are not available (e.g. no E/W) these steps can be omitted.
FUNCTION
Horizontal
parallelogram
Horizontal Bow
Horizontal shift
EW width
EW parabola/width
EW upper corner
parabola
EW lower corner
parabola
EW trapezium
Vertical slope
Vertical amplitude
S-correction
Vertical shift
Vertical zoom
Deflection
SUBADDR
(HEX)
06
D7
0
D6
0
D5
A5
HB
HS
EW
PW
UCP
07
09
0A
0B
0C
0
0
0
0
0
0
0
0
0
0
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
BCP
0D
A5
TC
VS
VA
SC
VSH
VX
0E
0F
10
11
12
13
26
0
0
0
0
0
0
OSVE
0
0
0
0
0
0
AFN
A5
A5
A5
A5
A5
A5
DFL
HP
DATA BYTE
D4
D3
A4
A3
D2
A2
D1
A1
D0
A0
POR
Value
20
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
20
20
20
20
20
A4
A3
A2
A1
A0
20
A4
A4
A4
A4
A4
A4
XDT
A3
A3
A3
A3
A3
A3
SBL
A2
A2
A2
A2
A2
A2
AVG
A1
A1
A1
A1
A1
A1
EVG
A0
A0
A0
A0
A0
A0
1
HCO
20
20
20
20
20
20
00
Table 37: Geometry registers

1) These function is only available in versions which have the East-West drive output.
It is however very important to align always VS (vertical slope) and VSH (vertical shift) as indicated below to
ensure correct performance under all circumstances. Because these registers are meant to compensate for
the tolerances of the total deflection system, the spreads as found in practice do not allow loading these
registers with a fixed value without aligning.
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START
Adjust HS
Load registers
for
zoom and scroll
Adjust EW
Set VX
Adjust PW
Set SC
Adjust TC
Apply video pattern
Adjust UCP
Set SBL = 1
Adjust BCP
Adjust VS
Set SBL = 0
Adjust HP
Adjust VSH
Adjust HB
END
Adjust VA
Figure 48: Adjusting the picture tube

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Load registers for zoom and scroll with the correct value
Special linear zoom facilities on both Vertical and East-West gives the possibility to adapt the picture size
for both 16:9 and 4:3 screens. When zoom is used, the geometry remains correct in both vertical and
horizontal direction. By programming the vertical slope, VS, subtitles at the bottom part of the picture can be
made visible while the picture position at the top of the screen remains fixed.
H/V settings for aspect ratios as 16:9 and 4:3:
Scale factor for H or V
Vert. adjust with VX (1% /step)
Hor. Adjust with EW (0.55% / step)
133% (4/3)
58
preset + 18
100% (1)
25
preset
75% (3/4)
preset - 14
Table 38: H/V settings for 16:9 and 4:3

Set VX (vertical expand, reg. 13 hex, bit D5..0)
If not set correct, the specified zoom range is not valid. Also problems can occur with too early blanking at
the top or bottom of the screen.
Set SC (S-correction, reg. 11 hex, bit D5..0) to a predetermined value
The value of the vertical S-correction is related to the screen curvature and once determined this will not
change for the same model picture tube. For each different tube model, a specific S-correction value has to
be determined.
The needed value of this register can range between 0 and 63, pending on the screen curvature. There is
no problem when the determined value is close to the end of the adjustment range, because there is no
spread.
Apply a video pattern with a horizontal line in the middle (e.g. a crosshatch pattern)
Set SBL = 1 (service blanking, reg. 26 hex, bit D3) to switch-on the service blanking
The service blanking blanks the bottom half of the picture. The blanking starts at the point where the
differential current of the vertical drive outputs becomes zero, so at the point where the vertical deflection is
zero.
Adjust VS (vertical slope, reg. 0F hex, bit D5..0) to centre the picture.
Align VS till the horizontal line in the centre of the video signal is just at the position where the blanking
starts. This alignment is very important, because it calibrates the peak-to peak value of the generated
sawtooth VSC at pin 26. Several other correction signals are derived from this sawtooth.
This alignment compensates for the following spreads:
Spread on the component value of the sawtooth capacitor at pin 26 (major)
Spread on the sawtooth current (minor)
Set SBL = 0 (service blanking, reg. 26 hex, bit D3) to switch-off the service blanking
Adjust VSH (vertical shift, reg. 12 hex, bit D5..0) to centre the picture.
Align VSH till the picture is centred. If the picture tube has a marking in the middle, it is also possible to align
the horizontal line in the middle with the markings.
This alignment is important to obtain the correct waveforms for the East-west correction signals and the
right S-correction.
This alignment compensates for the following spreads:
DC-offset of the vertical deflection amplifier (major)
Vertical mechanical offset of the picture tube gun (minor)
DC offset of the vertical drive outputs (minor)
112
Version 1.0
TDA937X PS N2
Application Note
AN01045
After these alignments the system has been made tolerance free which ensures
correct performance.
Adjust VA (vertical amplitude, reg. 10 hex, bit D5..0) to correct picture height.
Align VA till the picture height is correct. Think about overscan.
The three alignments above influence the horizontal East-West waveforms, so it is important to carry out
these vertical alignments first before starting the horizontal (East-West) alignments.
Adjust HS (horizontal shift, reg. 09 hex, bit D5..0) to centre the picture horizontal.
Align HS till the picture is horizontally centred
Adjust EW (East-West width, reg. 0A hex, bit D5..0) to correct picture width.
Align EW amplitude to adjust the correct width (use the width of the horizontal line in the centre to determine
the final picture width)
Adjust PW (parabola width, reg. 0B hex, bit D5..0) to correct the East-West parabola.
Align PW to straighten the vertical lines at the sides.
Adjust TC (trapezium correction, reg. 0E hex, bit D5..0) to correct trapezium form.
Align TC to set the lines at the sides vertical.
Adjust UCP (upper corner parabola, reg. 0C hex, bit D5..0) to correct top corner.
Align UCP to straighten the top of the vertical lines at the sides.
Adjust BCP (bottom corner parabola, reg. 0D hex, bit D5..0) to correct bottom corner.
Align BCP to straighten the bottom of the vertical lines at the sides.
Adjust HP (horizontal parallelogram, reg.06 hex, bit D5..0) to correct parallelogram form. Align HP to set
vertical lines orthogonal to the horizontal lines.
Adjust HB (horizontal bow, reg. 07 hex, bit D5..0) to correct bow form.
Align HB to straighten the vertical lines across the whole picture in the same direction.
The order of aligning the horizontal parameters is not so critical, once the vertical alignment is done
correctly.
It is of course always possible before starting alignment to load all geometry registers with values, close to
the expected value, to save time during the alignment.
113
Version 1.0
TDA937X PS N2
7.3
Application Note
AN01045
SCREEN VOLTAGE ALIGNMENT
Below four methods are given for adjustment of the VG2 voltage:
1. Measure the lowest black current measurement pulses at the cathode of the picture tube.
Normally when aligning VG2 the cut off voltage is set about 5V lower than the cut off voltage, specified
for that picture tube.
2. The VG2 can also be adjusted on the way described in application note AN96070 of the TDA837X-N3
par .3.9
Except there are now two levels of black current measuring pulses. The black current measuring pulse
with the lowest DC-level should be adjusted to 2.5V (or better to the DC-level of the Vref at the input of
the TDA610X family).
2
3. The VG2 voltage can be adjusted by using I C bit VSD in combination with Brightness control and VSW
bit. When this bit is activated the vertical scan is switched off so a horizontal line is displayed on the
screen. At the same time the CCC-loop must be disabled. The amplitude of the horizontal line is a
function of the brightness control. An amplitude of the black level of 2.5V is present at the RGB-outputs
when the brightness is in nominal position 32. In order to use this alignment the value of the brightness
control has to be determined first and can only be applied for black levels from 2.5V and higher
If a RGB-amplifier, like TDA6101 or TDA6106, is used with an external reference voltage, the DC-gain
of the RGB-Amplifier is determined by means of external resistors. Then brightness control must be set
to nominal position in case the ref. Voltage is equal to 2.5V. If the ref voltage at the RGB-amplifier is not
equal 2.5V then brightness control should be set off centre and can be calculate by means of the
following formula:
Brightness control setting = (( Uref RGB-amplifier - 2.5V) /23 mV ) + 32 =
Uref RGB-amplifier
2.5V
23 mV
Figure 21
: The chosen reference voltage at the RGB-amplifier

: amplitude of the horizontal line in case VSD bit is active
: one step of the brightness range in mV.
: nominal value of brightness control
Example: Substituting Uref RGB-amplifier = 2.7V in the formula results in:

Brightness control setting = ((2.7- 2.5V) /23mV) + 32 41
A RGB-amplifier, like TDA6107 or TDA6108, which have a fixed cut off voltage, for the mentioned
amplifiers this value is 130V and this value corresponds with the cut off voltage of the used picture tube
then the brightness control setting should be set to the nominal position of 32. But if the cut off of the
used picture tube is different from this 130V then Vg2 can be aligned by means of the VSD and VSW bit
with the following procedure:
From the device specification of the tube the cut off voltage and the optimum VG2 voltage are given.
The VG2 should be set to this optimum voltage by aligning the pot-meter on the LOT and measuring
this voltage on the same time by means of a high voltage probe and a multimeter or a 100:1 probe
and oscilloscope.
Set the VSD and the VSW bits to 1 then measure the voltage of the horizontal line on the cathode of
the tube with oscilloscope (w.r.t. ground).
Align the brightness control such that the amplitude level of horizontal line is equal to the cut off
voltage given in the device specification. Notice the value of the brightness control, with this value
the VG2 alignment can be completed.
114
Version 1.0
TDA937X PS N2
Application Note
AN01045
Beware of the fact that finding the correct brightness control setting should only be carried out once (during
development of the set). Perhaps it is possible to add an option in the service menu in which the brightness
control setting is directly set to the right value corresponding with the correct cut off voltage for the used
picture tube whenever the VSD bit is activated.
Finally the alignment procedure of VG2 for production is as follows:
Turn the potentiometer on the LOT to min VG2 voltage to protect the tube
Set the VSD and VSW bits to 1 and the brightness to the determined pre-set value.
Adjust the Vg2 potentiometer so that a horizontal (white) line is just visible on the screen.
Now the VG2 is correctly adjusted without the use of measuring equipment.
From these four steps only the value of the brightness control is important for production of the set.
2
4. The VG2 voltage can be adjusted by using I C bit AVG in combination with Brightness control and WBC
and HBC bits, see below. When enabling the alignment with the bit AVG, the vertical deflection remains
running and the current measurement is done in a few lines in the top of the screen. It is possible to display
via OSD the status of bits HBC and WBC on the other part of the screen. This can be used in a factory
alignment set-up
The alignment procedure of VG2 is as follows (see figure on the next page)
Define the value of the brightness control as described above
Set the brightness control to this determined preset value
Set the BLOR and BLOG (black level offset) to nominal = 20 hex.
Align the VG2 voltage and check HBC (Height Black Current)-bit and WBC (Window Black Current)-bit
until WBC = 1 and HBC=1.
Set the AVG = 0.
The colour temperature can now be aligned for lowlight and highlight separately.
HBC = 0
(below window)
WBC
Window
12uA
HBC = 1
(above window)
20uA
HBC
WBC
Figure 49: HBC and WBC bits waveform

CONDITION
WBC
0
Black current stabilisation outside window
1
Black current stabilisation inside window
HBC
0
Black current stabilisation below window
1
Black current stabilisation above window
Table 39: WBC and HBC setting for Vg2 alignment
115
Version 1.0
TDA937X PS N2
Application Note
AN01045
START
Set the brightness

to the pre-set value
Enable the AVG bit

(AVG-bit is "1")
Adjust VG2 voltage
Check HBC bit

HBC=1
HBC=0
Decrease the VG2 voltage
Increase the VG2 voltage
Check WBC bit
Check WBC bit
WBC=0
WBC=0
WBC=1
WBC=1
Set AVG bit = 0
END
Figure 50: VG2 alignment procedure
116
Version 1.0
TDA937X PS N2
Application Note
AN01045
lowest Vbcmp = Vref => VG2 correctly adjusted
Rfeedback
GND
GND
RGB ouputs
51,52,53
Rdrive
_
Rcutoff
TDA610X
+
Vref
2.5V
Vg2
Black current
input
50
Figure 51: VG2 alignment
In the figure above Vbcmp means DC-level of the black current measurement pulse.
117
Version 1.0
TDA937X PS N2
7.4
Application Note
AN01045
COLOUR TEMPERATURE ALIGNMENT
The colour temperature has to be seperately aligned for lowlight and highlight.
2
2
The lowlight is aligned via the I C registers BLOR/G (black level off-set) and highlight is aligned via the I C
registers WPR,G,B ( white point R,G,B).
For a correct alignment the following is necessary :
Use a high quality video generator (a service generator is not preferred)
Be sure that the picture tube is adequate degaussed.
Vg2 should be aligned.
All settings should be set to nominal value .
Set Black Stretch (BKS) off
Colour temperature alignment for the highlight:
Use a (PAL) signal with saturation = minimum (setting 00 in the IIC menu), contrast = nominal (setting
32 in the I2C menu) and Black Level Offset = nominal (setting 32 in the I2C menu).
Take a grey picture with 30 cd/m
Align with WPR/WPB/WPG bits the colour temperature for the highlight (WPA registers 16,17,18).
Colour temperature alignment for the lowlight:
Use a PAL signal with saturation = minimum (setting 00 in the IIC menu) and contrast = nominal (setting
32 in the IIC menu)
Take a grey picture with 1 cd/m
Align with the BLOR en BLOG bits the colour temperature for low light (Black Level Offset registers 14
and 15)
Black stretch can be switched on after alignment.
End of the high- and low-light alignments.
118
Version 1.0
TDA937X PS N2
Application Note
AN01045
119
Version 1.0
TDA937X PS N2
8
Application Note
AN01045
BLOCK DIAGRAM
120
Version 1.0
TDA937X PS N2
TV-processor + P with Teletext
Application Note
AN01045
2x 8 m A LE D s
cu rrent sin ks
P0.5
P0 .6
10
C V B S /Y from
F ilters/s w itche s
62
Tim e r
0
I/P
P 1.1
E xte rn al
in te rrup t
0
P 1.2
63
64
H from s ync
D ata
S lice r
D a ta
V from s ync
R os d
D isp lay
G en era tor
C ha racter
ROM
M atrix
12* 9
12*1 0
12*1 3
12*1 6
16*1 8
U n it
D a ta
D ec o der
T im in g
T im e r
1
I/P
SCL
SDA
P 1.3
P 1 .6
P 1.7
po rt 1 d riv ers
D isp lay
T im ing
D e c od er
CSI
11
E xte rn al
inte rru pt
1
P 1.0
port 0
to Y U V /R G B
pro c essin g &
con tro l
Gosd
Bosd
drive rs
IN T
8 mA
1
sink /source
T im e r
0
inp u t
T im e r
1
in pu t
IN T
0
SCL
SDA
inte rna l
I2 C
I/O
M em o ry
In te rface
I/O
P ro gram
A ux iliary
M ain
RAM
RAM
80C 5 1
M em ory
256 B
CPU
3 2k B -----55 kB
2.2 5 kB
14
B it
PW Ms
6
B it
PW M
8
B it
ADC
D isp lay
RAM
1 .25 k B
F RE F to IF v id eo & s ou nd
H V s yn c, D ec od er
1 2M H z
oscilla tor
55
V P E (O T P -program ing)
port 2
d rive rs
CPU
R es e t
2V
W atchdo g
Tim ing
&
C on trol
port 3 d rive rs
tim e r
PO R
fro m syn c
57
58
59
56
VDD C
61
12
60
VDD P
R es et
V S S C /P
54
VDD A
VSSA
S igna ls to othe r circu it bloc ks in re d

TD A 9 37 x P S N 2 S D IP 6 4
m ic rop roc es so r
4
P2 .0
TP W M
P 3.0
P 3.1
ADC0 ADC1
PW M0 PW M1
inp u t
inpu t
P 3.2
P 3.3
A DC 2 A DC 3
PWM2 PWM3
inpu t
inpu t
Version 1.0
TDA937X PS N2
Application Note
AN01045
DECSDEM
IFOUT/SVO
PLLIF
37
IFLH
Calibrator
Offset IF
demodulator
PLL
Fref from
microprocessor
fsc
SNDPLL
38
PLL
lock
det.
LOCK
AFC
AFA
AFB
VCO
31
29
selected CVBS
from Filters/Switches
VSW
AFW
IFB,IFC
FMW
FML
FFI
FMW
FML
detector
SVO
23
IF amplifier
IFIN1
IFIN2
PC
38.9 MHz
Video
0-5MHz
SIF
LPF
38.9MHz
1
Video
buffer
24
IFS
SM0
SM1
AGC
BPF
0/+6
dB
LPF
FMWS
FMA
FMB
FM 5.5MHz
AGN
VCO
Automatic volume level

+9dB
AVL
-71dB
ADX
Volume control
REF0 from
Filters/Switches
+4.5V
(4.4/3.6 MHz)
Gating signal
from HVsync
AGC
AVL
1
AGCOUT
AGC
speed
LPF
AGC
take-over
Signals to other cicuit blocks in red
SIF
AGC0
AGC1
35
Frequency indication refers to B/G standard
CMB0
CMB1
VSW
AUDEXT
44
AUDOUT
Video
AGC
detect.
AUDEEM
Narrow band PLL
BPF
Audio switch
27
28
3V
Sound demodulator
33.4MHz
15K
Pre-amplifier
BPB
FMA
FMB
SC
33.4 MHz
video
demodulator
**20
32
AVL/REFO/SNDIF
TDA937x PS N2 SDIP64
UOCplus IF video+sound
(FM version)
** Only in 90 degrees versions without EW drive
AVL/EWD
Version 1.0
TDA937X PS N2
Application Note
AN01045
IFOUT/SVO
PLLIF
Fref from
37
IFLH microprocessor
Offset IF
demodulator
PLL
Calibrator
fsc
38
PLL
lock
det.
LOCK
AFC
AFA
AFB
VCO
selected CVBS
from Filters/Switches
VSW
AFW
IFB,IFC
FFI
SVO
IF amplifier
23
IFIN1
PC IFIN2
38.9 MHz
Video
demodulator
Video
0-5MHz
LPF
38.9MHz
CMB1, 0
Video
buffer
24
IFS
REF0 from
filters/switches
(4.4/3.6 MHz)
32
REFO
sv
4.5V
Sound demodulator
28
SIF amplifier
33.4MHz
SIFIN1
SC
SIFIN2
33.4 MHz
+10dB
BPF
AM sound
demodulator
29
LPF
33.4MHz
Automatic volume level
Sound
AGC
detect.
44
LPF
AUD out
AVL
CMB1, 0
Volume control
AVL
Gating signal
from HVsync
AGC
27
Video
AGC
AGC
speed
detect.
AGCOUT
AGC take-over
LPF
AGC0
AGC1
VSW
31
Frequency indication refers to B/G standard
Signals to other circuit blocks in red
35
AUDEXT/QSSO
SIFAGC
UOCplus IF video+sound
(QSS version)
20
AVL/EW
Version 1.0
TDA937X PS N2
CVBS/Y to HVsync
& microprocessor
CVBS/Y
or Y
selection
Application Note
AN01045
Y from YUV/RGB
processing + control
FCO
CM3..CM0
CD3..CD0
IDN
SOY
Chroma trap
IN A
IN B
IDP
Automatic
System
Manager
0-360ns
VIM
IFI
no burst
(automode)
YD3..0
Video
ident
PF1,PF0
RPO1,RPO0
160ns
IFI to
HV sync
Yint to YUV/RGB
processing & control
Peaking
Tuning
H/2
PSNS
Peaking
HUE,
CM3..CM0
1 bit
42
F REF from
microprocessor
DDS
converter
Y/CVBS
Chroma
Digital
Filter
Y/CVBS
43
CVBS1
Y/CVBS2
40
CVBS1
selected CVBS
to IF video & sound
Chroma
select
chroma/CVBS
burst
detec.
ACC
chroma
detec.
ACL
H90O
REFO to
IF video & sound
(4.4 / 3.6 MHz)
H0O
Multiplier
Low
pass
filter
ACL
IDN
6dB
Uint to YUV/RGB
Bandpass
1H delay
Chroma (PAL/NTSC)
INA
INB
CB
Low
pass
filter
H/2
Tuning
IDP
6dB
Vint to YUV/RGB
Multiplier
1H delay
Tuning filter
BPS
Tuning
REFO
SV
Filters/switches + decoder
Version 1.0
TDA937X PS N2
Application Note
AN01045
PH1LF
PH2LF
H signal
to microprocessor
17
V ID
P OC
FOA
FOB
33
2.5V
POR to
microprocessor
HP2
Ref. PHI2
Horizontal
VCO
1600 Fh
Timing
SL
Calibration
system
Coincidence
detector
Flash
protection
HSH
HB
HP
F REF from
microprocessor
6.5V
Slowstart
&
Stop
PHI2
detector
: 1600
Burstkey
VD DA
54
H-out
Low Voltage
Slow
Hout
Slowstart STB Stop
Vcal
STM
16
Gating signal
to IF video & sound
IFI from
Filters
switches
PHI1
detector
HOUT
enable
Direct
Stop
Hout
H-out
Slow
Stop
8V
14, 39
SUP
4V
6V
DECDIG
15
DFL
3.5V
Ref. PHI1
HBL
WBF 3..0
WBR 3..0
Blanking
generation
RGB blank1
to YUV/RGB
DECBG
19
12M Hz
F REF from
detector microprocessor
Hsync
22
Vertical
geometry
processor
SN1
SN0
CVBS/Y from
Filters/switches
Noise
detector
IVW
FSI
Hsync
separation
Vsync
separation
FSL
Vertical
divider
FORF,FORS
NCIN,DL
VA,VX
VSH,SC
SBL,OSVE
FSI
OSO,VS
Sandcastle
generator
+/-5%
Vertical
tracking
V signal to
microprocessor
Iref
RGB blank2
to YUV/RGB
(due to SBL & VX)
Overvoltage
detector
XPR
enable
VRDB
21
RGB blank3
to YUV/RGB
Hout Slow Stop
XDT
Vertical
sawtooth
generator
vertical retrace pulse
VRDA
36
EHTO
Usaw
HCO
EW
tracking
UCP,BCP,TC
EW,PW
+/-5%
*20
EW geometry
processor
AVL/EW D
* Only in 110 degrees versions with EW drive

34
26
25
sv
FBISO
IREF
VSC
TDA937x PS N2 S DIP64
HV sync +geometry
Version 1.0
TDA937X PS N2
Insertion
input
Application Note
AN01045
45
RGBblank 1, 2, 3
R2/Pr/Vin
G2/Y/Yin
B2/Pb/Uin
46
47
48
DSK
IE2 IN2
YUV1,0
Vext
RGB or YPbPr
to YUV
Uext
conversion
or
Yext
YUV transfer
YUV
U
int./ext.
selection Y
V
Input
Clamps
MAT,MUS
Saturation
Dynamic
Skin
Control
R-Y
R -Y
G-Y
/
B -Y
matrix B-Y
Contrast
RBL
51
R
RGB
adder
+
clamps
PWL
&
soft
clipper
RGB
select
blender
G
B
RGB
blanking
Yint Uint Vint

from Filters/switches
Fblank
Rosd Gosd Bosd
RGB
output
stages
drive
correction
GREEN output
53
offset
correction
RGBL,WPR,
WPG,WPB,CL3..0
CCC
measurement
pulse
generator
LR,LG,LB
8uA
20uA
field LR,LG,LB
switch
black stretch
BCL
&
PWL
PWL
RGB blanking
field switch
BKS
LO
Leakage
compensator
EVG
Vertical
guard
detector
CRT
warm
detector
Fixed
Beamcurrent
Discharge
VG2
window
49
NDF
BCF
WBC,HBC
AVG
50
FB K
Beam current limiter (BCL)
YUV/RGB processing + control
RED output
52
BLUE output
Half-tone
Y to
Filters/switches
BLR3..0
BLG3..0
AKB
Brightness
Black current input/

vertical guard
Version 1.0
TDA937X PS N2
Application Note
AN01045
INTERNAL PINNING
VDDC
VDDP
Pin 1,4,
5,10, 11
VDDP
820
Pins 2,3
VDDP
VDDP
VDDC
235
VDDP
360
235
360
VSSC/P
VSSC/P
VDDP
8V
* VDDP (Pin 61 ) is 3.3V digital supply to

* VDDC (Pin 56 ) is 3.3V digital supply to
+/- 100 uA
820
Pins 6,7,8
CAL
8V
VDDP
235
360
SI
VDDP
10K
270
Pin 13
270
VSSC/P
2,3V
digital ground video processor

Pin 12
analog ground TXT decoder
Pin18,30,41
Pin 14
VDDC
VDDP
analog grounds + video processor*
8V
digital ground of
core +periphery
Pin 9
8V
(2nd supply voltage
to video processor)
8V
15K
Pin 15
8V
8V
8V
8V
48K
8V
270
270
FLASH
LEVEL
5.3V
5V (supply for embedded

delay line)
100pF
8V
Pin 16
pin 7 earth
5V
+
-
121
(supply for
digital circuits)
Version 1.0
TDA937X PS N2
Application Note
AN01045
8V
8V
270
270
Pin 17
+
4V
dF
Hor Osc
+
4V
3.3V
4.7V
no coincidence
8V
8V
8V
30
8V
230
100uA
Pin 19
8V
40K
8V 500
Pin 20
1mA
max
AVL
100
4V bandgap ref.
for analog circuits
0.2mA
5Vzener
AVL/EW
>
12 X
8V
Pin 23
8V
1K
100
Pin 21,22
1.8V
8V
8V
IDC=400uA
3pF
1K
Isawtooth=+/- 250uA typ.

Pin 24
122
3mA
Version 1.0
TDA937X PS N2
Application Note
AN01045
8V
8V
8V
Iref
10
100
Pin 26
Pin 25
+
5V
vert.
flyback
3,9V
8V
1K
8V
8V
30
Pin 27
30
Pin 28
AUDEEM
(FM version)
100
muteswitch
8V
8V
10K
8V
7.5K
Pin 28
SIF1
(QSS version)
i ac
i dc=200uA
1K
1.8V
8V
7.5K
3.2V
3.2V
28uA
100uA
3pF
8V
1K
Pin 29
SIF2
(QSS version)
8V
8V
8V
270
Pin 29
DECSDEM
(FM version)
3K8
270
100 uA
14 uA
digital ground video

Pin 12
analog ground TXT
Pin18,30,41
analog grounds + video
123
14 uA
Version 1.0
TDA937X PS N2
Application Note
AN01045
2.5mA/25mA
100
Pin 31
(QSS version)
2.5mA/25mA
80
8V
8V
100uA
30
Pin 31
(FM version)
Vref
40mA
100
1.7V
2.7V
100uA
50uA
1K5
8V
30
to FM demodulator
0.2mA 3mA
Pin 32
5V
2p5
100
AVL
Ref out
max.
1 mA
4V7
1mA
5V
1V4
muteswitch
8V
10K
7.5K
iac
idc =200uA
7.5K
3.2V
3.2V
28uA
3.3V
13K
10
Pin 33
PROTECTION
124
100uA
Version 1.0
TDA937X PS N2
Application Note
AN01045
8V
8V
4.6V
+
-
BURSTKEY
270
8V
2.5V
PHI2 ACT.
Pin 34
8V
8V
3.0V
V BLANK
8V
270
V control
8V
4K
30
Pin 37
2uA
8V
BURSTKEY
30K
100
10pF
8V
500
8pF
30
Pin 35
100
800uA
QSSO
AM
2V5
12.5K
12.5K
12.5K
3.7V
100uA
8V
8V
IF <
video
8V
270
Pin 36
<
Pin 38
5K
8V
XPR
3,9V
1,8mA
2V
Pin 39
125
8V
(main supply voltage
video processor)
selected
CVBS
Version 1.0
TDA937X PS N2
Application Note
AN01045
digital ground video processor

Pin 12
decoder luma, sync, text

8V
analog ground TXT decoder
decoder chroma
Pin18,30,41
analog grounds + video processor*
1k
Pins 40, 42
sync clamp
1k
8V
4 uA
500
dummy clamp
switch control
30
Pin 44
800 uA
40k
8V
insertion
vref = 4V
8V
8V
500k
decoder/luma
270
Pin 43
270
10pF
100k
Pin 45
4V
8V
8V
8V
25 uA
no insertion
Pins 46,47,48
8V
100
270
8V
8V
Imax=4mA(PWL)
Pin 49
8V
brightness
2V
100
contrast
burstkey
8V
V/I
I leakage
Vref=2,5V
Pin 50
270
8V
2 mA
3,65
vert. guard
126
8 A
20 A
Version 1.0
TDA937X PS N2
8V
Application Note
AN01045
VDDC
8V
Pin 51,52,53
270
VDDP
Pin 54
3.3V (analog supply

to TXT decoder)
2 mA
VSSC/P
VDDP
Pin 55
3.3V (digital supply to

video processor)
VDDC
VDDP
VDDC
2.70pF
Pin 59
Pin 58
Pin 56
276 K
3.3V (digital supply

to core)
0.9pF
VSSC/P
VSSC/P
VSSC/P
VSSC/P
* internal input capacitance @ Pin 58 = 7pF

* internal output capacitance @ Pin 59 = 7pF
* OSC GND (Pin 57) connected internally to VSSC/P (
VDDC
VDDP
1110
Pin 60
235
701
VDDC
VSSC/P
VDDP
VDDP
Pins 62,
63,64
820
Pin 61
VDDP
235
360
3.3V (digital supply

to periphery)
VDDP
VSSC/P
VSSC/P
127
Version 1.0
TDA937X PS N2
10
Application Note
AN01045
APPLICATION EXAMPLE ( DEMO-BOARD )
128
C132
15
16
2.2nF
C34
220uF
25V
1uF
63V
C139
18k
C121
100uF
L102
10uH
2x2k2
BeamCurr
BeamCurr
B2in
G2in
Gnd3
19
2.2uF
63V
20
C147
R2in
DecBG
46
Fbl2in
AVL/EWdr
TR107
BC548
FL100
TPT02B
5.5+5.74+6.5
TRP
FblIn
IfVout
TR108
BC558
470
R184
1k
C156
100
Z1
BZX79C
33V
3n3
IfGnd
+5V
10uH
C162
10uF
35V
SOUND SAW
220
R202
IFVout
AgcOut
PllLf
30
Gnd2
EHT
AudExt
QssOut/AmOut
R205
R207
680
R206
3.9k
C169
820pF
FbiSo
32 Avl/SndIf/RefO/
AmOut/AudDeem
C170
4.7nF
Hout
R198
100k
R197
390
37
TRP
R2
C171
47uF
16V
1.2k
TR1
BC548
R1
27k
J2
France Only
R3
5.6k
J4
C166
1nF
J102
+Vstb
34
ExtIn_QssOut
2.2uF
R209
33
Optional
+8V
Mout
SOUND-1
PHILIPS
2x 8W Audio Amplifier
Gnd
+15
+3.3
10
IC105
**
**
OUT
C7
330nF
IN
GND
+8V
Date Changed:
330nF
C164
100uF
6.3V
+5
11
Gnd
12
Stby
Stby
J108
R204
On
22k
Engineer:
E.C.P Arnold
PHILIPS
Thursday, October 7, 1999
C9
+8
OnNoff
SEMICONDUCTORS
PS-SLE
Receiver Group
5
+15V
330nF
TR109
BC548
Audio-gnd
AVL= 4u7
Deemph= 3n3
IC104
SOUND-2
10uF
R4
C8
IN
GND
UA7805UC
10uF
1k
+3Stb
**
C6
J105
SndIf
+14
Hdrive
100
+45
OUT
**
330nF
Hflyback
R210
MIC29150_3.3BT
+5V
R201
27k
35
+8V
120k
P1
FM only QSS only
75
BeamCurr
36
P118
x
2.2uF
12k
D100
BAT85
Ver
C4
100pF
8.2uH
16V
47uF
C163
R191
+8V
+Vvert
R190
11
12
Supply
P3
Cvbs3/C
SvhsCin
C5
10uF
R10
3.3k
C161
100uF
38
R208
1
L1
10uH
27k
2.7k
C160
22nF
C168
31 SndPll/
SifAgc
220
3
L108
R199
29 DecsDem/
SIFin2
SvhsYin
CvbsInt
Gnd
+8V
+8V
C157
100nF
22nF
SCL
TR2
BC548
470
R8
180
IfVout
39
P114
P115
10uF
C165
SDA
Vp1
VScap
28 AudDeem/
SIFin1
If
R200
26
27
L109
**
100nF
IfVout
NC
+45V
P2
Cvbs2/Y
R196
C159
10uF
35V
CvbsInt
40
470
+45V
NC
P103
4.7
100
R7
39k
R193
CvbsInt
Iref
R11
R9
10
21
C158
100uF
6.3V
25
R177
75
EWdrive
Gnd
20
TR106
BC548
7
8
+8V
P117
R194
J100
SndIf
41
R173
75
P110
75
+8V
Gnd1
IFin2
NC
SvhsYin
220nF
24
Ext_Qss_Intc
+8V
ExtIn_QssOut
C154
19
R180
1k
4
3
2
1
17
Out
P100
R187
100
AudOut
Cvbs/Yin
IFin1
C153
220nF
SvhsCin
1nF
42
C
3
16
C141
10uF
35V
P111
IC1012
100
P116
10
CvbsInt
C152
IfGnd
100
43
Ext_Qss_Intc
IfGnd
23
1nF
1nF
J103
C151
C150
Cin
VdrA
If
TRP
AudOut
R76
22
Hor
1
BeamCurr
C126
100pF
47
R188
120
R5
44
+5V
Idrive+
AudOut
VdrB
PGND1
14
R174
CvbsInt2V
21
100
+15V
R73
12
OUT1+
R160
3.3k
18
TRP
3
330
R6
Idrive-
3
2
1
15
R172
+8V
C146
10uF
R181
45
75
100
4.7uH
R179
180
C143
10uF
RedIn
100
OUT1-
P107
R156
10k
R169
R176
47
L106
R175
4.7
GreIn
R182
11
Hdrive
+8V
BluIn
22nF
RIGHT
13
Beam Current info
+8V
22nF
R162
C131
100pF
Integration for AVERAGE
BCL
C142
OUT2-
Lin
11
100
R168
220
10
12
R163
2.2nF
1k
C138
PGND2
Hflyback
48
47
75
FblIn
Iblack
Vguard
Phi1
R153
C125
100pF
C129
49
9
10
StatAv
RedIn
220k
C145
22nF
Asymm. tuner
AGC
R159
10nF
13
100
Red Out
47k
GreIn
TR105
BC558
C117
Rin
C122
100pF
OUT2+
1
2
3
1k
100
C123
100pF
P106
**
R150
R155
C48
2x2n2
C47
R83
R82
50
39k
VC2
LEFT
47k
6
R152
Green Out
100
51
75
TR104
BC548
BCL
R164
R147
R148
CRT
100
BCL
+Vmem
Blue Out
52
R145
4
BluIn
SGND
7
1
2
3
47K
1k
330
C116
100pF
Z101
2V4
100
1.2uH
R158
100
C144
C2
4.7uF
50V
AVL capacitor
R137
10k
Reset generator,
Supply voltage guard
and NV-memory supply switch
+Vstb
22nF
R71
If
Phi2
TR101
BC558
R144
4.7nF
L107
Iblack
DecDig
R132
10k
22nF
22nF
R125
10k
VOLUME
R136
R139
Reset
+Vstb
10uH
C119
R126
4.7k
P105
330
Lout
BC558
L101
54
C111
100pF
Rout
56
C118
R134
R130
100
TR102
VI(2)
470nF
C109
100pF
4u7
17
18
11
Rout
Vp2
R171
C137
Ver
IF
Gout
SecPll
S1007
R129
100
Reset
S100
57
53
S1006
TDA7057AQ
X100
12MHz
VP
**
C106
Vol
R128
10k
C115
33pF
100
220nF
**
FL101
K2955
UV1316-MK2
Bout
S1005
Supply Guard Circuit
C113
33pF
58
SDA
22nF
100
TN100
VssA
S1004
SCL
100uF
16V
J1
Vtun
VddA
6/8
12
C134
C136
EWdrive
Adr
P0.6
5/8
VI(1)
470nF
R120
+Vstb
Reset
59
55
4/8
11
C133
SCL
VPE
+15V
nc
C105
220uF
3/8
NC
R114
4.7k **
C101
R113
10k
Lmain
C112
10uF
R167
+Vvert
Vi +
SDA
P0.5
SOT274-s
1.9
1.9
R49
R50
10uH
C33
100nF
Vi -
[V+]
VddC
Rmain
C108
100uF
60
VC1
2
nc
VDD
Isupp=1mA
Rout
220nF
**
14
V+
VssC/P
1.5k
10
13
L104
C24
47uF
100V
ic
OscGnd
2/8
S1003
1/8
S1002
S1001
Service
+Vstb
R161
C128
11
12
100nF
OutB
+33V
10
+8V
+45V
10
Ver
IfGnd
P3.3/ADC3
nc
Vol
IC100
Lout
Bnd1
NFR25
Vp
XtalIn
WP
Bnd0
R55
BZX79C
15V
P3.2/ADC2
820
470
Rin
100
Defl.
VERT
12k
C20
GND
R74
XtalOut
C3
61 22nF
R149
StatAv
390k
Px.x/PWMx
L100
10uH
C107
22nF
P108
Vflb
Z1005
Reset
R1089
47
Vguard
TDA8357J
Vertical Amplifier
R146
OutA
Px.x/PWMx
330
220
100k
+Vmem
Guard
1.2k
R135
10k
VddP
P2.0/TPWM
180
SCL1
R1088
R1087
SCL
VSS
62
100
2.7k
Keyb
R123
R1086
R1085
R119
3.3k
Lin
R131
P1.0/Int1
P1.7/SDA
R1084
R118
3.3k
TPWM
R138
Av
R25
330
100
R127
P109
R35
1
SDA1
100
R1090
220
SDA
47nF
P1.1/T0
P1.6/SCL
63
100
P104
9 R34
100
SDA
100
TR1006
BC548
R1075
R105
Gnd
Analogue scanned local keyboard
100
C114
470nF
Feedb.
R122
15k
**
Rc5N
SCL
Vol
C7
R121
15k
R107
R117
R116
+Vstb
IC1008
64
SCL1
Rmain
7
8
P1.2/Int0
P1.3/T1
R103
100
SDA1
D1035
TSOP1836
LED-3R
Standby / Blink-LED
Lmain
R111
3.3k
Out
IC103
R110
3.3k
10uF
35V
R1064
560
D1034
Infra-Red receiver
Vs
R1059
C1060
100
22uF
6.3V
1
2
3
4
Keyb
+Vstb
Rc5N
Gnd
Mout
+5V
SDA
Keyb
SCL1
SDA1
+Vstb
C100
SCL
Gnd
+5V
SDA
Service
SCL1
SDA1
+3.3V
+Vstb
1
2
3
4
11
SCL
100
I2C-bus
R112
1.2k
OnNoff
10
P101
R104
Local
Keyboard
P1011
+5V
P102
Local
Keyboard
Keyb
R203
15k
8x256 byte
+Vmem
PCF8598CP
12
Time Changed:
Drawn by:
E.C.P. Arnpld
Changed by:
L.Bakema/T.Bruton
6:02:05 pm
7
Philips Semiconductors B.V.

Eindhoven The Netherlands
F
Size:
A3
Sheet Name:
TDA955x/6x/8x PS N1
Small signal panel
Project:
Drwg: 130 - 1 / 3
PR31843
8
Version 1.0
TDA937X PS N2
11
Application Note
AN01045
REFERENCES
[1]
TDA955x/6x/8x H/N1 series TV signal processor-Teletext decoder with embedded -controller

Device specification ver. 1.11, 2001 29 Aug, Philips Semiconductors
[2]
Application information for TV signal processor + P+TXT TDA93xx

AN98093, June 2000, F. Bremer, T. Bruton, A. Kenc, P. Laro, J. Luijckx, S. Reed, R. Vermeulen
[3]
PR33491 The TDA95XX QFP80 demonstration board

AN00072, 2000-12-01, E.C.P Arnold, E. Winkelmuller, T Hummelink, J. van Nieuwenburg
[4]
TDA8357J Full bridge vertical deflection output circuit in LVDMOS

Data sheet (preliminary specification), 1999-11-10, Philips Semiconductors
[5]
TDA6107Q Triple video output amplifier

Data sheet (product specification), 1999-10-26, Philips Semiconductors
[6]
TDA7057AQ 2*8W stereo BTL audio output amplifier with DC volume control
Data sheet (product specification), 1998-04-07, Philips Semiconductors
[7]
TDA935x/6x/8x TV-processor +P with Teletext Changeover N1-N2 Version 1.6a

AN200xx, 2001 April, P. Laro, Philips Semiconductors
[8]
Development tools for TDA95XX-N2 UOC devices Version 1.1

SPG/AN00009 March 03, 2000, F Giuliano, Philips Semiconductors
[9]
Reset behaviour of the 2 generation ultimate one chip TDA95XXH/N1, TDA95XXPS/N1,

TDA937X/N2, TDA957XH/N1 and TDA93XXPS/N2 Initialisation of the device Version 1.0
SPG/AN01003 April 02, 2001, F Giuliano, Philips Semiconductors
[10]
TV microcontroller Bench programmer Version 1.0

SPG/UM00010 April 14, 2000, D Pregon, Philips Semiconductors
[11]
PxTDA93XX-N2 Hitex Probe Version 1.0

SPG/AN01009 September 10, 2001, S Vaughan, F Giuliano, Philips Semiconductors
[12]
Application report for combfilters, multistandard TDA9181, NTSC TDA9183

AN99034.1, July 2000, F. Bremer, T. Bruton
nd
129
Version 1.0
TDA937X PS N2
Application Note
AN01045
130
Version 1.0
TDA937X PS N2
12
Application Note
AN01045
INDEX
Microprocessor
45
Development tools
Emulator tools
OSD Power on reset,
I/O Ports
Crystal oscillator
Supply, ground, decoupling
13
13
46
41
45
95, 96
I2C BITS
17
ACL
ADX
AFA
AFB
AFN
AFW
AGC0, 1
AGN
AKB
AVG
AVL
BCF
BKS
BLOG
BLOR
BPB
BPS
CB
CL0..3
CD0..3
CM0..3
CMB0, 1
DFL
DL
DSK
EVG
EW
FCO
FFI
FMB, FMA
FML
FMW
FMWS
FOA, FOB
FORS/FORF
FSI
FSL
HBC
HBL
HCO
HP2
22
33
38
38
29
29
30
31
32
28
33
36
34
21
21
34
23
22
32
35
23
24
28
26
34
28
20
23
30
31
37
37
31
26
27
37
27
36
32
27
26
HS
IE2
IFB, IFC
IFI
IFLH
IFS
IN2
INA, INB
IVW
LOCK
MAT
MUS
NCIN
NDF
OSO
POC
POR
PSNS
PW
QSS
RBL
RGBL
RPO0, 1
SBL
SC
SIF
SL
SM0, 1
SOY
STB
STM
SUP
SVO
TC
VA
VID
VIM
VS
VSD
VSH
VSW
131
20
32
29
35
30
29
36
24
37
35
22
22
26
37
27
25
36
23
20
33
32
25
34
28
21
30
35
31
33
25
29
39
24
20
21
25
25
21
33
21
29
Version 1.0
TDA937X PS N2
VX
WBC
WPR, G, B
XDT
Application Note
AN01045
21
36
21
28
XPR
YD0..3
YUV0, 1
IF
47
Alignment
AGC take over
IFPLL Filter
Mute video
Overmodulation, phase modulation, FFI
SAW filter
109
48
49
89
47, 55
Sound
50, 55
nd
2 SIF input
Automatic Volume Levelling
De-emphasis
Decoupling sound
FM sound
Mute
Narrow band PLL
Quasi split sound (QSS)
SIF AGC
SIF input
Volume control
51
50
53
52
50
54
57
55
56
55
54
Filters/Switches + Colour Decoder
59
Colour decoder
PAL, NTSC, SECAM
Combfilter application
Coring video dependent
Crystal oscillator
CVBS input selection
Peaking
59
60
90
45
61
90
H/V Sync + Geometry
63
16:9 Zoom
Flash protection
Geometry
Alignment
EHT tracking
EW geometry
Horizontal Slow start/stop
Overvoltage Detection
Phi-1 loop
Phi-2 loop
Sandcastle
Vertical sawtooth
IREF, VSC application
75
65, 101, 102
110
75
71
98
101
65
63
69
74
75, 74
132
37
22
33
Version 1.0
TDA937X PS N2
Application Note
AN01045
YUV/RGB processing
77
Beam current limiting

Black current stabilisation loop
Drive correction
Leakage current measurement
Black stretch
Fixed beam current discharge
Peak white limiting
Skin tone
Soft clipper
Vertical guard
VG2 Alignment
YPbPr, RGB selection
79
83
85
82
92
87
79
93
80
81
114
77
133
Philips Semiconductors a worldwide company

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
Germany: Hammerbrookstrae 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,
Tel: +36 1 382 1700, Fax: +36 1 382 1800
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,

Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Philips Electronics N.V. 2001
Internet: http://www.semiconductors.philips.com
SCB 71
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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APPLICATION NOTE

Application information for

Purchase of Philips I Ccomponents conveys

Philips Electronics N.V. 2002

Application information for TV Signal

System Application, Mainstream T.V. Solutions

Date: February 2002

DEVICE INFORMATION ......................................................................................................................... 9

DEVELOPMENT TOOLS ...................................................................................................................... 13

I C CONTROL VIDEO PROCESSOR PART......................................................................................... 17

INPUT CONTROL BITS.................................................................................................................. 20

TUNER AGC................................................................................................................................. 109

BLOCK DIAGRAM .............................................................................................................................. 120

INTERNAL PINNING ........................................................................................................................... 121

10 APPLICATION EXAMPLE ( DEMO-BOARD ) .................................................................................... 128

A summary of the functions/features of the microprocessor is:

ACL function switched via I C bus.

HV sync & geometry:

YUV/RGB processing & control:

Figure 1: Pinning configuration

ref. 7313-903-0027-3 (Only in case version is ref. 7313-903-0027-2)

I C CONTROL VIDEO PROCESSOR PART

Table 2: I2C input bits

Output status bytes

Table 3: I2C output bits

Write slave address:

multiple data bytes,

Read 1, 2 or 3 status bytes

IC-bus start-up procedure.

INPUT CONTROL BITS

HOR. BOW CORRECTION

Adjusts the horizontal position of the picture on the screen.

E-W PARABOLA WIDTH

E-W UPPER CORNER

Adjusts the parabola correction.

Adjusts the upper curve of the vertical lines.

E-W BOTTOM CORNER

E-W TRAPEZIUM COR.

Adjusts the vertical S-correction.

BLK LEVEL OFFSET RED

BLK LEVEL OFFSET GREEN

Reg 16..18 D0..5

WHITE POINT RGB

Adjusts the Y delay in order to achieve correct Y and chroma timing

AGC TAKE OVER

AGC TAKE OVER POINT

Selects between the two built-in NTSC matrices.

Forces PAL matrix, even when NTSC is detected.

COLOUR DECODER MODE

BYPASS CHROMA DELAY

PAL SENSITIVITY NOISY

Selects CVBS/YC video inputs.

COMB PIN FUNCTION

SELECTED VIDEO OUT

RGB OUTPUTS LOW

VIDEO IDENT COUPLING

VIDEO IDENT MODE

7KHUHFRPPHQGHGFDSDFLWRUYDOXHLV )WR )LWVRSWLPDOYDOXHLVDFRPSURPLVHEHWZHHQIDVWYROXPH