MCV 14 A

MCV14A
Data Sheet
14-Pin, 8-Bit Flash Microcontroller
2009 Microchip Technology Inc.
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Preliminary
DS41338B
Note the following details of the code protection feature on Microchip devices:
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DS41338B-page ii
Preliminary
MCV14A
14-Pin, 8-Bit Flash Microcontroller
High-Performance RISC CPU:
Low-Power Features/CMOS Technology:
Only 33 Single-Word Instructions

All Single-Cycle Instructions except for Program
Branches which are Two-Cycle
Two-Level Deep Hardware Stack
Direct, Indirect and Relative Addressing modes
for Data and Instructions
Operating Speed:
- DC 20 MHz crystal oscillator
- DC 200 ns instruction cycle
On-chip Flash Program Memory
- 1024 x 12
General Purpose Registers (SRAM)
- 67 x 8
Flash Data Memory
- 64 x 8
Standby current:
- 100 nA @ 2.0V, typical
Operating current:
- 15 A @ 32 kHz, 2.0V, typical
- 170 A @ 4 MHz, 2.0V, typical
Watchdog Timer current:
- 1 A @ 2.0V, typical
- 7 A @ 5.0V, typical
High Endurance Program and Flash Data Memory
cells
- 100,000 write Program Memory endurance
- 1,000,000 write Flash Data Memory endurance
- Program and Flash Data retention: >40 years
Fully static design
Wide operating voltage range: 2.0V to 5.5V
- Wide temperature range
- Industrial: -40C to +85C
Special Microcontroller Features:

Peripheral Features:
8 MHz precision internal oscillator

- Factory calibrated to 1%
In-Circuit Serial Programming (ICSP)
In-Circuit Debugging (ICD) Support
Power-On Reset (POR)
Device Reset Timer (DRT)
Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
Programmable Code Protection
Multiplexed MCLR Input Pin
Internal Weak Pull-ups on I/O Pins
Power-Saving Sleep mode
Wake-Up from Sleep on Pin Change
Selectable Oscillator Options:
- INTRC: 4 MHz or 8 MHz precision Internal
RC oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High-speed crystal/resonator
- LP:
Power-saving, low-frequency crystal
- EC:
High-speed external clock input
Program
Memory
12 I/O Pins
- 11 I/O pins with individual direction control
- 1 input-only pin
- High current sink/source for direct LED drive
- Wake-up on change
- Weak pull-ups
8-bit Real-time Clock/Counter (TMR0) with 8-bit
Programmable Prescaler
Two Analog Comparators
- Comparator inputs and output accessible
externally
- One comparator with 0.6V fixed on-chip
absolute voltage reference (VREF)
- One comparator with programmable on-chip
voltage reference (VREF)
Analog-to-Digital (A/D) Converter
- 8-bit resolution
- 3-channel external programmable inputs
- 1-channel internal input to internal absolute
0.6 voltage reference
Data Memory
Device
MCV14A
Flash (words)
SRAM (bytes)
Flash
(bytes)
1024
67
64
I/O
Comparators
Timers 8-bit
8-bit A/D
Channels
12
Preliminary
DS41338B-page 1
MCV14A
14-PIN PDIP AND SOIC DIAGRAM
VDD
RB5/OSC1/CLKIN
2
3
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RC5/T0CKI
4
5
RC4/C2OUT
RC3
DS41338B-page 2
MCV14A
FIGURE 1:
14
13
VSS
12
RB1/C1IN-/AN1/ICSPCLK
11
RB2/C1OUT/AN2
10
RC0/C2IN+
RC1/C2IN-
RC2/CVREF
Preliminary
RB0/C1IN+/AN0/ICSPDAT
MCV14A
Table of Contents
1.0 General Description..................................................................................................................................................................... 5
2.0 Architectural Overview ................................................................................................................................................................ 9
3.0 Memory Organization ................................................................................................................................................................ 11
4.0 Flash Data Memory ................................................................................................................................................................... 19
5.0 I/O Port ...................................................................................................................................................................................... 23
6.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 29
7.0 Special Features of the CPU..................................................................................................................................................... 35
8.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 49
9.0 Comparator(s) ........................................................................................................................................................................... 53
10.0 Comparator Voltage Reference Module.................................................................................................................................... 59
11.0 Electrical Characteristics ........................................................................................................................................................... 61
12.0 Packaging Information............................................................................................................................................................... 75
The Microchip Web Site ...................................................................................................................................................................... 97
Index ................................................................................................................................................................................................... 79
Product Identification System ............................................................................................................................................................. 81
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Preliminary
DS41338B-page 3
MCV14A
NOTES:
DS41338B-page 4
Preliminary
MCV14A
1.0
GENERAL DESCRIPTION
1.1
The MCV14A device from Microchip Technology is

low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontrollers. It employs a RISC
architecture with only 33 single-word/single-cycle
instructions. All instructions are single cycle (200 s)
except for program branches, which take two cycles.
The MCV14A device delivers performance an order of
magnitude higher than their competitors in the same
price category. The 12-bit wide instructions are highly
symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The
easy-to-use and easy to remember instruction set
reduces development time significantly.
The MCV14A product is equipped with special features
that reduce system cost and power requirements. The
Power-on Reset (POR) and Device Reset Timer (DRT)
eliminate the need for external Reset circuitry. There
are four oscillator configurations to choose from,
including INTRC Internal Oscillator mode and the
power-saving LP (Low-Power) Oscillator mode. PowerSaving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability.
Applications
The MCV14A device fits in applications ranging from

personal care appliances and security systems to lowpower remote transmitters/receivers. The Flash technology makes customizing application programs
(transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make these microcontrollers perfect for
applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the MCV14A device very versatile even in areas
where no microcontroller use has been considered
before (e.g., timer functions, logic and PLDs in larger
systems and coprocessor applications).
The MCV14A device is available in the cost-effective

Flash programmable version, which is suitable for
production in any volume. The customer can take full
advantage of Microchips price leadership in Flash
programmable microcontrollers, while benefiting from
the Flash programmable flexibility.
The MCV14A product is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a C compiler, a low-cost development programmer and a full featured programmer. All the tools
are supported on PC and compatible machines.
TABLE 1-1:
FEATURES AND MEMORY OF MCV14A

MCV14A
Clock
Maximum Frequency of Operation (MHz)
Memory
Flash Program Memory

SRAM Data Memory (bytes)
67
Flash Data Memory

Peripherals
64
Timer Module(s)
TMR0
Wake-up from Sleep on Pin Change

Features
20
1024
Yes
I/O Pins
11
Input Pins
Internal Pull-ups
Yes
In-Circuit Serial Programming
Yes
Number of Instructions
33
Packages
14-pin PDIP and SOIC
The MCV14A device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and
precision internal oscillator.
The MCV14A device uses serial programming with data pin RB0 and clock pin RB1.
Preliminary
DS41338B-page 5
MCV14A
NOTES:
DS41338B-page 6
Preliminary
MCV14A
2.0
ARCHITECTURAL OVERVIEW
The high performance of the MCV14A device can be

attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the MCV14A device uses a Harvard architecture
in which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architectures where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have
all single-word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all
instructions (33) execute in a single cycle (200 ns @
20 MHz, 1 s @ 4 MHz) except for program
branches.
The MCV14A device contains an 8-bit ALU and

working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are twos
complement in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Table 2-1 below lists memory supported by the

MCV14A device.
Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
TABLE 2-1:
A simplified block diagram is shown in Figure 2-2, with

the corresponding device pins described in Table 2-2.
MCV14A MEMORY
Program
Memory
Data Memory
Device
MCV14A
Flash
(words)
SRAM
(bytes)
Flash
(bytes)
1024
67
64
The MCV14A device can directly or indirectly address

its register files and data memory. All Special Function
Registers (SFR), including the PC, are mapped in the
data memory. The MCV14A device has a highly orthogonal (symmetrical) instruction set that makes it possible
to carry out any operation, on any register, using any
Addressing mode. This symmetrical nature and lack of
special optimal situations make programming with the
MCV14A device simple, yet efficient. In addition, the
learning curve is reduced significantly.
Preliminary
DS41338B-page 7
MCV14A
FIGURE 2-1:
MCV14A BLOCK DIAGRAM
11
Flash Program
Memory
1K x 12
Flash Data
Memory
64x8
Program
Bus
Data Bus
Program Counter
PORTB
RB0/ICSPDAT
RB1/ICSPCLK
RB2
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
RAM
67
bytes
File
Registers
STACK1
STACK2
12
RAM Addr (1)
PORTC
Addr MUX
Instruction Reg
Direct Addr
5-7
RC0
RC1
RC2
RC3
RC4
RC5/T0CKI
Indirect
Addr
FSR Reg
STATUS Reg
8
Comparator 1
MUX
Device Reset
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decode and
Control
Power-on
Reset
Timing
Generation
Watchdog
Timer
Internal RC
Clock
C1IN+
C1INC1OUT
VREF
ALU
Comparator 2
8
W Reg
C2IN+
C2INC2OUT
CVREF
CVREF
CVREF
Timer0
MCLR
VDD, VSS
8-bit ADC
AN0
AN1
AN2
VREF
DS41338B-page 8
Preliminary
MCV14A
TABLE 2-2:
MCV14A PINOUT DESCRIPTION
Name
RB0//C1IN+/AN0/
ICSPDAT
RB1/C1IN-/AN1/
ICSPCLK
RB2/C1OUT/AN2
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
RC0/C2IN+
RC1/C2INRC2/CVREF
RC3
RC4/C2OUT
RC5/T0CKI
Function
Input
Type
RB0
TTL
C1IN+
AN
Output
Type
Description
CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.
Comparator 1 input.
ADC channel input.
AN0
AN
ICSPDAT
ST
CMOS ICSP mode Schmitt Trigger.
RB1
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.
C1IN-
AN
Comparator 1 input.
ADC channel input.
AN1
AN
ICSPCLK
ST
CMOS ICSP mode Schmitt Trigger.
RB2
TTL
CMOS Bidirectional I/O pin.
C1OUT
CMOS Comparator 1 output.
AN2
AN
ADC channel input.
RB3
TTL
Input pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.
MCLR
ST
Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation or the device
will enter Programming mode. Weak pull-up always on if
configured as MCLR.
VPP
HV
Programming voltage input.
RB4
TTL
OSC2
XTAL
CLKOUT
CMOS EXTRC/INTRC CLKOUT pin (FOSC/4).
RB5
TTL
OSC1
XTAL
CLKIN
ST
RC0
TTL
C2IN+
AN
RC1
TTL
C2IN-
AN
RC2
TTL
CVREF
RC3
TTL

Oscillator crystal output. Connections to crystal or resonator in
Crystal Oscillator mode (XT, HS and LP modes only, PORTB
in other modes).
Oscillator crystal input.
External clock source input.
CMOS Bidirectional I/O port.
Comparator 2 input.
Comparator 2 input.

AN
Programmable Voltage Reference output.
RC4
TTL
C2OUT
CMOS Comparator 2 output.

RC5
TTL
T0CKI
ST
Timer0 Schmitt Trigger input pin.
VDD
VDD
Positive supply for logic and I/O pins.
VSS
VSS
Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, = Not used, TTL = TTL input,
ST = Schmitt Trigger input, HV = High Voltage
Preliminary
DS41338B-page 9
MCV14A
2.1
Clocking Scheme/Instruction
Cycle
2.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 2-1).
The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 2-2 and Example 2-1.
A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 2-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 1
Fetch INST (PC)

Execute INST (PC 1)
EXAMPLE 2-1:
PC + 2
Fetch INST (PC + 1)

Execute INST (PC)
Fetch INST (PC + 2)

Execute INST (PC + 1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
Fetch 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTB, BIT1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is flushed from the pipeline, while the new instruction is being fetched and then executed.
DS41338B-page 10
Preliminary
MCV14A
MEMORY ORGANIZATION
3.1
Program Memory Organization for

the MCV14A
The MCV14A device has an 11-bit Program Counter

(PC) capable of addressing a 2K x 12 program memory
space. Program memory is partitioned into user memory,
data memory and configuration memory spaces.
The user memory space is the on-chip user program
memory. As shown in Figure 3-1, it extends from 0x000
to 0x3FF and partitions into pages, including Reset
vector at address 0x3FF.
Data Memory
Space
The MCV14A memories are organized into program

memory and data memory (SRAM).The self-writable
portion of the program memory called Flash data memory is located at addresses at 400h-43Fh. All Program
mode commands that work on the normal Flash memory work on the Flash data memory. This includes bulk
erase, row/column/cycling toggles, Load and Read
data commands (Refer to Section 4.0 Flash Data
Memory for more details). For devices with more than
512 bytes of program memory, a paging scheme is
used. Program memory pages are accessed using one
STATUS register bit. For the MCV14A, with data memory register files of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
User Memory
Space
FIGURE 3-1:
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
000h
1FFh
200h
3FEh
3FFh
400h
Flash Data Memory

User ID Locations
Backup OSCCAL
Locations
Configuration Memory
Space
3.0
43Fh
440h
443h
444h
447h
448h
Reserved
49Fh
4A0h
Unimplemented
7FEh
Configuration Word
7FFh
The data memory space is the Flash data memory

block and is located at addresses PC = 400h-43Fh. All
Program mode commands that work on the normal
Flash memory work on the Flash data memory block.
This includes bulk erase, Load and Read data
commands.
The Configuration Memory Space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The User I.D. locations extend from 0x440
through 0x443. The Backup OSCCAL locations extend
from 0x444 through 0x447. The Configuration Word is
physically located at 0x7FF.
Preliminary
DS41338B-page 11
MCV14A
3.2
3.2.1
Data Memory (SRAM and FSRs)
Data memory is composed of registers or bytes of

SRAM. Therefore, data memory for a device is
specified by its register file. The register file is divided
into two functional groups: Special Function Registers
(SFR) and General Purpose Registers (GPR).
The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register
(FSR). See Section 3.8 Indirect Data Addressing:
INDF and FSR Registers.
The Special Function Registers are registers used by

the CPU and peripheral functions for controlling
desired operations of the MCV14A. See Figure 3-2 for
details.
3.2.2
The Special Function Registers can be classified into

two sets. The Special Function Registers associated
with the core functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
REGISTER FILE MAP
FSR<6:5>
00
01
20h
File Address
10
40h
11
60h
00h
INDF(1)
INDF(1)
INDF(1)
INDF(1)
01h
TMR0
EECON
TMR0
EECON
02h
PCL
PCL
PCL
PCL
03h
STATUS
STATUS
STATUS
STATUS
04h
FSR
FSR
FSR
FSR
05h
OSCCAL
EEDATA
OSCCAL
EEDATA
06h
PORTB
EEADR
PORTB
EEADR
07h
PORTC
PORTC
PORTC
PORTC
08h
CM1CON0
CM1CON0
CM1CON0
CM1CON0
09h
ADCON0
ADCON0
ADCON0
ADCON0
0Ah
0Bh
ADRES
CM2CON0
ADRES
CM2CON0
ADRES
CM2CON0
ADRES
CM2CON0
0Ch
VRCON
VRCON
VRCON
VRCON
0Dh
General
Purpose
Registers
0Fh
10h
Addresses map back to

addresses in Bank 0.
4Fh
6Fh
2Fh
30h
General
Purpose
Registers
1Fh
50h
General
Purpose
Registers
3Fh
Bank 0
Note 1:
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the
operation of the device (Table 3-1).
The MCV14A register file is composed of 13 Special

Function Registers and 41 General Purpose Registers
FIGURE 3-2:
GENERAL PURPOSE REGISTER

FILE
70h
General
Purpose
Registers
5Fh
Bank 1
General
Purpose
Registers
7Fh
Bank 2
Bank 3
Not a physical register. See Section 3.8 Indirect Data Addressing: INDF and FSR Registers.
DS41338B-page 12
Preliminary
MCV14A
3.2.3
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the
operation of the device (Table 3-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the core functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 3-1:
Addr
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Page #
N/A
TRIS
--11 1111
23
N/A
OPTION
Contains control bits to configure Timer0 and Timer0/WDT prescaler
1111 1111
15
00h
INDF
Uses contents of FSR to Address Data Memory (not a physical register)
xxxx xxxx
18
01h/41h
TMR0
Timer0 Module Register
xxxx xxxx
29
02h(1)
PCL
Low order 8 bits of PC
1111 1111
17
03h
STATUS
0001 1xxx
14
04h
FSR
05h/45h
OSCCAL
06h/46h
07h
RBWUF
I/O Control Register (PORTB, PORTC)
CWUF
PA0
TO
PD
DC
Indirect Data Memory Address Pointer
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
23
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
24
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
53
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
1111 1100
51
xxxx xxxx
52
0Ah
ADRES
CAL0
18
PORTC
CM1CON0
CAL1
16
PORTB
ADCON0
CAL2
1111 111-
CAL5
08h
CAL3
CAL6
09h
CAL4
100x xxxx
ADC Conversion Result
0Bh
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
54
0Ch
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
000- 0000
59
FREE
WRERR
WREN
WR
RD
---0 0000
20
21h/61h
EECON
25h/65h
EEDATA
26h/66h
EEADR
Legend:
Note 1:
x = unknown, u = unchanged, = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused
The upper byte of the Program Counter is not directly accessible. See Section 3.6 Program Counter for an explanation of how to
access these bits.
SELF READ/WRITE DATA
SELF READ/WRITE ADDRESS
Preliminary
xxxx xxxx
19
--xx xxxx
19
DS41338B-page 13
MCV14A
3.3
STATUS Register
For example, CLRF STATUS, will clear the upper three

bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.
Therefore, it is recommended that only BCF, BSF and

MOVWF instructions be used to alter the STATUS
register. These instructions do not affect the Z, DC or C
bits from the STATUS register.
The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 3-1:
STATUS: STATUS REGISTER
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RBWUF
CWUF
PA0
TO
PD
DC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
RBWUF: Wake-up from Sleep on Pin Change bit

1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6
CWUF: Wake-up from Sleep on Comparator Change bit

1 = Reset due to wake-up from Sleep on comparator change
0 = After power-up or other Reset
bit 5
PA0: Program Page Preselect bit

1 = Page 1 (000h-1FFh)
0 = Page 0 (200h-3FFh)
bit 4
TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF:
SUBWF:
RRF or RLF:
1 = A carry occurred
1 = A borrow did not occur
Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
DS41338B-page 14
Preliminary
MCV14A
3.4
OPTION Register
The OPTION register is a 8-bit wide, write-only register,

which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
Note:
By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION
register. A Reset sets the OPTION<7:0> bits.
REGISTER 3-2:
If TRIS bit is set to 0, the wake-up on

change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of RBPU and RBWU).
OPTION: OPTION REGISTER
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
RBWU
RBPU
T0CS(1)
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
RBWU: Enable Wake-up On Pin Change bit

1 = Disabled
0 = Enabled
bit 6
RBPU: Enable Weak Pull-ups bit

1 = Disabled
0 = Enabled
bit 5
T0CS: Timer0 Clock Source Select bit(1)

1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Note 1:
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
x = Bit is unknown
If the T0CS bit is set to 1, it will override the TRIS function on the T0CKI pin.
Preliminary
DS41338B-page 15
MCV14A
3.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used

to calibrate the 8 MHz internal oscillator macro. It
contains 7 bits of calibration that uses a twos
complement scheme for controlling the oscillator speed.
See Register 3-3 for details.
REGISTER 3-3:
OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-1
CAL<6:0>: Oscillator Calibration bits

0111111 = Maximum frequency
0000001
0000000 = Center frequency
1111111
1000000 = Minimum frequency
bit 0
Unimplemented: Read as 0
DS41338B-page 16
Preliminary
x = Bit is unknown
MCV14A
3.6
3.6.1
Program Counter
EFFECTS OF RESET
As a program instruction is executed, the Program

Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The PC is set upon a Reset, which means that the PC

addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
For a GOTO instruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS
register provides page information to bit 9 of the PC
(Figure 3-3).
The STATUS register page preselect bits are cleared

upon a Reset, which means that page 0 is pre-selected.
For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 3-3).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
Note:
Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
FIGURE 3-3:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTO Instruction
10 9 8 7
PC
0
PCL
Therefore, upon a Reset, a GOTO instruction will

automatically cause the program to jump to page 0 until
the value of the page bits is altered.
3.7
The MCV14A device has a 2-deep, 12-bit wide

hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack
1 into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
program memory.
Note 1: There are no Status bits to indicate Stack
Overflows or Stack Underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
Instruction Word
PA0
Stack
0
Status
CALL or Modify PCL Instruction

10 9 8 7
PC
0
PCL
Instruction Word
Reset to 0
PA0
0
Status
Preliminary
DS41338B-page 17
MCV14A
3.8
Indirect Data Addressing: INDF

and FSR Registers
FSR<7> is unimplemented and read as 1.

A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 3-1.
The INDF Register is not a physical register.

Addressing INDF actually addresses the register
whose address is contained in the FSR Register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 3-1:
Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF Register indirectly results in a
no-operation (although Status bits may be affected).
NEXT
The FSR is 8-bit wide register. It is used in conjunction

with the INDF Register to indirectly address the data
memory area.
INCF
BTFSC
GOTO
CONTINUE
:
:
The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.
FSR<6:5> are the bank select bits and are used to
select the bank to be addressed (00 = Bank 0,
01 = Bank 1, 10 = Bank 2, 11 = Bank 3).
FIGURE 3-4:
(FSR)
6
MOVLW
MOVWF
CLRF
HOW TO CLEAR RAM

USING INDIRECT
ADDRESSING
0x10
FSR
INDF
;initialize pointer
;to RAM
;clear INDF
;register
;inc pointer
;all done?
;NO, clear next
FSR,F
FSR,4
NEXT
;YES, continue
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(opcode)
4
bank select
Indirect Addressing
(FSR)
0
location select
00
01
10
11
bank
select
location select
00h
Data
Memory(1)
0Ch
0Dh
Addresses map back to
addresses in Bank 0.
0Fh
10h
2Fh
4Fh
6Fh
1Fh
3Fh
5Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register map detail see Figure 3-2.
DS41338B-page 18
Preliminary
MCV14A
4.0
FLASH DATA MEMORY
The data memory is the Flash data memory block,

which attaches to the user Flash program memory. It is
located at addresses 0x400-0x43F, as shown in Figure
5-1.
This Flash data memory block consists of 8 rows and
has self-write capability of up to 64 bytes. This memory
block is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are three SFRs used to read
and write this memory:
EEDATA (Register 4-1)
EEADR (Register 4-2)
EECON (Register 4-3)
EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEDATA location
being accessed. The effective program counter is
EEADR + 400h with only the lower 8 bits of each word
being readable or writable.
EEADR = 00h, PC = 400h
EEADR = 01h, PC = 401h
The Flash data memory allows byte read and write, and
during the operations of read and write cycles, the CPU
stalls.
The timing for all self-writes and erases is controlled by
the internal timing block of the program memory (see
Section 11.0
Electrical
Characteristics,
Table 11-11). The write/erase voltages are generated
by an on-chip charge pump rated to operate over the
voltage range of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash data memory and
read the program memory. When code-protected, the
device programmer can no longer access data or
program memory.
REGISTER 4-1:
EEDATA: FLASH DATA REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EEDATA7
EEDATA6
EEDATA5
EEDATA4
EEDATA3
EEDATA2
EEDATA1
EEDATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
EEDATA<7:0>: 8-bits of data to be read from/written to data Flash
REGISTER 4-2:
EEADR: FLASH ADDRESS REGISTER
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Do not use
bit 5-0
EEADR<5:0>: 6-bits of data to be read from/written to data Flash
Preliminary
x = Bit is unknown
DS41338B-page 19
MCV14A
REGISTER 4-3:
EECON: FLASH CONTROL REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Do not use
bit 4
FREE: Flash Data Memory Row Erase Enable Bit

1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write
will be performed. This bit is cleared at the completion of the erase operation.
0 = Perform write only
bit 3
WRERR: Write Error Flag bit

1 = A write operation terminated prematurely (by device Reset)
0 = Write operation completed successfully
bit 2
WREN: Write Enable bit

1 = Allows write cycle to Flash data memory
0 = Inhibits write cycle to Flash data memory
bit 1
WR: Write Control bit

1 = Initiate a erase or write cycle
0 = Write/Erase cycle is complete
bit 0
RD: Read Control bit

1 = Initiate a read of Flash data memory
0 = Do not read Flash data memory
DS41338B-page 20
Preliminary
MCV14A
4.1
EXAMPLE 4-2:
Reading Data Memory
To read a memory location, the user must write the

address to be read into the EEADR register and then
set the RD bit in the EECON register. The data will be
available in the next instruction cycle.
EXAMPLE 4-1:
FLASH DATA MEMORY

READ
BSF
FSR,5
;SWITCH TO BANK 1
MOVLW
EE_ADR_READ ;LOAD ADDRESS TO READ
BSF
EECON,RD
;INITITATE THE READ
INSTRUCTION
;IS DECODED
MOVF
EEDATA,W
;GET NEW DATA
Note: Only a BSF command will work to enable the

Flash data memory read documented in
Example 4-1. No other sequence of commands will work, no exceptions.
4.2
Erasing a Data Memory Row
In order to write new data to the Flash data memory,

the program memory row that is being addressed by
EEADR<5:0> must be erased.
To prevent a spurious row erasure, a specific
sequence must be executed to initiate the erase to the
program memory. The sequence is as follows:
- Set the FREE bit (enable Flash data memory
row erase)
- Set the WREN bit (enable writes to the Flash
data memory array)
- Set the WR bit (initiates the row erase of the
Flash data memory array)
BSF
MOVLW
MOVWF
BSF
BSF
BSF
xxx
ERASE DATA MEMORY

ROW
FSR,5
EE_ADR_ERASE
EEADR
EECON,FREE
EECON,WREN
EECON,WR
;SWITCH TO BANK 1
;LOAD ADDRESS TO ERASE
;LOAD ADDRESS TO SFR
;SELECT ERASE
;ENABL FLASH PROGING
;INITITATE ERASE
;NEXT INSTRUCTION
Note: The FREE bit may be set by any command

normally used by the core. However, the
WREN and WR bits can only be set using a
series of BSF commands, as documented in
Example 4-2. No other sequence of
commands will work, no exceptions.
4.3
Writing a Data Memory Word
To write a memory location, the user must write the

address to be written to into the EEADR register. He
must then load the data to be written into the EEDATA
register. Once the data and address have been
loaded, a specific sequence must be executed to
initiate the write to the program memory. The
sequence is as follows:
Set the WREN bit (enable writes to the Flash data
memory array)
Set the WR bit (initiates the write to the Flash data
memory array)
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
If the WREN bit is not set in the instruction cycle after

the FREE bit is set, the FREE bit will be cleared in
hardware.
This sequence is to prevent an accidental write to the

Flash memory.
If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in
hardware.
Both of these sequences is to prevent an accidental
erase of the Flash data memory.
Preliminary
DS41338B-page 21
MCV14A
EXAMPLE 4-3:
DATA MEMORY WRITE
4.4
BSF
FSR,5
MOVLW EE_ADR_WRITE
;SWITCH TO BANK 1
;LOAD ADDRESS TO
;WRITE
MOVWF EEADR
;INTO EEADR
;REGISTER
MOVLW EE_DATA_TO_WRITE;LOAD DATA TO
MOVWF EEDATA
;INTO EEDATA
;REGISTER
BSF
EECON,WREN
;ENABLE WRITES
BSF
EECON,WR
;START WRITE
;SEQUENCE
NOP
;WAIT AS READ
;INSTRUCTION
;IS DECODED
NOP
;INSTRUCTION
IGNORED
DATA MEMORY OPERATION

DURING CODE-PROTECT
Data memory can be code-protected by programming

the CPDF bit in the Configuration Word (Register 7-1)
to 0.
Note 1: Only a series of BSF commands will work

to enable the memory write sequence
documented in Example 4-3. No other
sequence of commands will work, no
exceptions.
2: For reads, erases and writes to the Flash
data memory, there is no need to insert a
NOP into the user code as is done on
mid-range devices. The instruction immediately following the BSF EECON,WR/RD
will be fetched and executed properly.
DS41338B-page 22
Preliminary
MCV14A
5.0
I/O PORT
5.2
PORTC is a 6-bit I/O register. Only the low-order 6 bits

are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as 0s.
As with any other register, the I/O register(s) can be

written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pins Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at highimpedance) since the I/O control registers are all set.
5.1
5.3
TRIS Register
The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f
instruction. A 1 from a TRIS register bit puts the corresponding output driver in a High-Impedance mode. A
0 puts the contents of the output data latch on the
selected pins, enabling the output buffer. The exceptions are RB3, which is input only and the T0CKI pin,
which may be controlled by the OPTION register. See
Register 3-2 and Register 3-3.
PORTB
PORTB is a 6-bit I/O register. Only the low-order 6 bits

are used (RB<5:0>). Bits 7 and 6 are unimplemented
and read as 0s. Please note that RB3 is an input only
pin. The Configuration Word can set several I/Os to
alternate functions. When acting as alternate functions,
the pins will read as 0 during a port read. Pins RB0,
RB1, RB3 and RB4 can be configured with weak pullups and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin selectable. If RB3/MCLR is configured as MCLR, weak pullup is always on and wake-up on change for this pin is
not enabled.
TABLE 5-1:
PORTC
The TRIS register is write-only and is set (output

drivers disabled) upon Reset.
WEAK PULL-UP ENABLED PINS
Device
RB0 Weak Pull-up
MCV14A
Yes
RB1 Weak Pull-up RB3 Weak Pull-up(1)

Yes
RB4 Weak Pull-up
Yes
Yes
Note 1: When MCLREN = 1, the weak pull-up on RB3/MCLR is always enabled.
REGISTER 5-1:
PORTB: PORTB REGISTER
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
RB<5:0>: PORTB I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.
Preliminary
x = Bit is unknown
DS41338B-page 23
MCV14A
REGISTER 5-2:
PORTC: PORTC REGISTER
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
RC<5:0>: PORTC I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.
DS41338B-page 24
Preliminary
x = Bit is unknown
MCV14A
5.4
FIGURE 5-1:
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All port pins, except RB3 which is input only,
may be used for both input and output operations. For
input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF PORTB, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except RB3) can be programmed individually as
input or output.
MCV14A EQUIVALENT
CIRCUIT FOR A SINGLE
I/O PIN
Data
Bus
D
WR
Port
W
Reg
TRIS f
Q
Data
Latch
CK
VDD VDD
Q
N
D
I/O
pin
Q
TRIS
Latch
CK
VSS
VSS
Reset
RD Port
Preliminary
DS41338B-page 25
MCV14A
TABLE 5-2:
Addr
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
RBWU
RBPU
N/A
TRIS
N/A
OPTION
03h
STATUS
06h
PORTB
07h
PORTC
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
--11 1111
--11 1111
1111 1111
1111 1111
TOCS
TOSE
PSA
PS2
PS1
PS0
PA0
TO
PD
DC
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
--uu uuuu
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
RBWUF CWUF
0001 1xxx q00q quuu(1)
Legend: Shaded cells are not used by PORT registers, read as 0. = unimplemented, read as 0, x = unknown,
u = unchanged,
q = depends on condition.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 5-3:
I/O PINS ORDER OF PRECEDENCE
Priority
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC4
RC5
1
2
3
AN0
C1IN+
TRISB
AN1
C1INTRISB
AN2
C1OUT
TRISB
RB3/MCLR
C2IN+
TRISC
C2INTRISC
CVREF
TRISC
C2OUT
TRISC
T0CKI
TRISC
DS41338B-page 26
Preliminary
MCV14A
5.5
EXAMPLE 5-1:
I/O Programming Considerations
5.5.1
BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and rewrite the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit 5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit 0) and it is defined as an input at
this time, the input signal present on the pin itself would
be read into the CPU and rewritten to the data latch of
this particular pin, overwriting the previous content. As
long as the pin stays in the Input mode, no problem
occurs. However, if bit 0 is switched into Output mode
later on, the content of the data latch may now be
unknown.
;Initial PORTB Settings

;PORTB<5:3> Inputs
;PORTB<2:0> Outputs
;
;
PORTB latch PORTB pins
;
------------------BCF
PORTB, 5 ;--01 -ppp
--11 pppp
BCF
PORTB, 4 ;--10 -ppp
--11 pppp
MOVLW 007h;
TRIS
PORTB
;--10 -ppp
--11 pppp
;
Note 1: The user may have expected the pin values to
be --00 pppp. The 2nd BCF caused RB5 to
be latched as the pin value (High).
5.5.2
A pin actively outputting a high or a low should not be

driven from external devices at the same time in order
to change the level on this pin (wired OR, wired
AND). The resulting high output currents may damage
the chip.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
Fetched
SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-2).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
FIGURE 5-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT(e.g., MCV14A)
MOVWF PORTB
PC + 1
MOVF PORTB, W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
This example shows a write to PORTB

followed by a read from PORTB.
NOP
NOP
Data setup time = (0.25 TCY TPD)

where: TCY = instruction cycle.
RB<5:0>
TPD = propagation delay

Port pin
written here
Instruction
Executed
MOVWF PORTB
(Write to PORTB)
Port pin
sampled here
MOVF PORTB,W
(Read PORTB)
Therefore, at higher clock frequencies, a

write followed by a read may be problematic.
NOP
Preliminary
DS41338B-page 27
MCV14A
NOTES:
DS41338B-page 28
Preliminary
MCV14A
6.0
TIMER0 MODULE AND TMR0

REGISTER
The Timer0 module has the following features:
8-bit timer/counter register, TMR0

Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0

module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
There are two types of Counter mode. The first Counter

mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CS bit (OPTION<5>), setting
the C1T0CS bit (CM1CON0<4>) and setting the
C1OUTEN bit (CM1CON0<6>). In this mode, Timer0
will increment either on every rising or falling edge of
pin T0CKI. The T0SE bit (OPTION<4>) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 6.1 Using Timer0 with
an External Clock.
The second Counter mode uses the output of the
comparator to increment Timer0. It can be entered in
two different ways. The first way is selected by setting
the T0CS bit (OPTION<5>), and clearing the C1T0CS
bit (CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does
not affect this mode of operation). This enables an
internal connection between the comparator and the
Timer0.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 Prescaler details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM

Data Bus
Comparator
Output
FOSC/4
PSOUT
1
1
1
T0CKI
pin
Programmable
Prescaler(2)
T0SE(1)
T0CS(1)
8
Sync with
Internal
Clocks
TMR0 Reg
PSOUT
(2 cycle delay) Sync
PSA(1)
3
PS2(1), PS1(1), PS0(1)
C1T0CS(3)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer.
3: The C1T0CS bit is in the CM1CON0 register.
Preliminary
DS41338B-page 29
MCV14A
FIGURE 6-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC 1
Instruction
Fetch
PC
PC + 1
MOVWF TMR0
T0
Timer0
T0 + 1
T0 + 2
Instruction
Executed
PC + 4
PC + 5
PC + 6
NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0 + 2
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
Read TMR0
reads NT0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC 1
Instruction
Fetch
PC
PC + 1
MOVWF TMR0
T0
Timer0
PC + 2
T0 + 1
Name
PC + 4
PC + 5
NT0
Read TMR0
reads NT0
Write TMR0
executed
TABLE 6-1:
PC + 3
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Executed
Addr
PC + 3
NT0
Write TMR0
executed
FIGURE 6-3:
PC
(Program
Counter)
PC + 2
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
NT0 + 1
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
Read TMR0
reads NT0
REGISTERS ASSOCIATED WITH TIMER0

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
All Other
Resets
xxxx xxxx
uuuu uuuu
1111 1111
uuuu uuuu
01h
TMR0
08h
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
0Bh
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
uuuu uuuu
N/A
OPTION
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
N/A
TRIS(1)
--11 1111
--11 1111
Legend:
Note 1:
Timer0 8-bit Real-Time Clock/Counter
Value on
Power-On
Reset
Shaded cells are not used by Timer0. = unimplemented, x = unknown, u = unchanged.

The TRIS of the T0CKI pin is overridden when T0CS = 1.
DS41338B-page 30
Preliminary
MCV14A
6.1
Using Timer0 with an External

Clock
When an external clock input is used for Timer0, it must

meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2 TOSC (and a small RC delay of 2 Tt0H) and low
for at least 2 TOSC (and a small RC delay of 2 Tt0H).
Refer to the electrical specification of the desired
device.
FIGURE 6-4:
When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling requirement, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least 4 TOSC (and a small RC delay of 4 Tt0H)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or

Prescaler Output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)

Timer0
Note 1:
T0
T0 + 1
T0 + 2
Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = 4 TOSC max.
2:
External clock if no prescaler selected; prescaler output otherwise.
3:
The arrows indicate the points in time where sampling occurs.
Preliminary
DS41338B-page 31
MCV14A
6.2
EXAMPLE 6-1:
Prescaler
An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 7.6 Watchdog Timer (WDT)). For simplicity, this counter is
being referred to as prescaler throughout this data
sheet.
Note:
The prescaler may be used by either the

Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a Reset, the prescaler contains all 0s.
6.2.1
SWITCHING PRESCALER
ASSIGNMENT
CHANGING PRESCALER
(TIMER0 WDT)
CLRWDT
;Clear WDT
CLRF
TMR0
;Clear TMR0 & Prescaler
MOVLW 00xx1111b ;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
CLRWDT
;PS<2:0> are 000 or 001
MOVLW 00xx1xxxb ;Set Postscaler to
OPTION
;desired WDT rate
To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
EXAMPLE 6-2:
CLRWDT
MOVLW
xxxx0xxx
CHANGING PRESCALER
(WDT TIMER0)
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
The prescaler assignment is fully under software

control (i.e., it can be changed on-the-fly during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 61) must be executed when changing the prescaler
assignment from Timer0 to the WDT.
DS41338B-page 32
Preliminary
MCV14A
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY (= FOSC/4)
Data Bus
0
Comparator
Output
0
1
M
U
X
1
0
1
T0CKI
Pin
M
U
X
T0SE(1)
T0CS(1)
Sync
2
Cycles
TMR0 Reg
PSA(1)
C1TOCS
Watchdog
Timer
8-bit Prescaler
M
U
X
8
PS<2:0>(1)
8-to-1 MUX
(1)
PSA
WDT Enable bit
0
MUX
PSA(1)
WDT
Time-out
Note 1:
T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
Preliminary
DS41338B-page 33
MCV14A
NOTES:
DS41338B-page 34
Preliminary
MCV14A
7.0
SPECIAL FEATURES OF THE

CPU
What sets a microcontroller apart from other

processors are special circuits that deal with the needs
of
real-time
applications.
The
MCV14A
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide
power-saving operating modes and offer code
protection. These features are:
Oscillator Selection
Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
Watchdog Timer (WDT)
Sleep
Code Protection
ID Locations
Clock Out
The MCV14A device has a Watchdog Timer, which can

be shut off only through Configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
HS, XT or LP selectable oscillator options, there is
always an 18 ms (nominal) delay provided by the
Device Reset Timer (DRT), intended to keep the chip in
Reset until the crystal oscillator is stable. If using
INTRC or EXTRC, there is a 1 ms delay only on VDD
power-up. With this timer on-chip, most applications
need no external Reset circuitry.
The Sleep mode is designed to offer a very low current
Power-Down mode. The user can wake-up from Sleep
through a change on input pins or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4/8 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of Configuration bits are
used to select various options.
7.1
Configuration Bits
The MCV14A Configuration Words consist of 12 bits.

Configuration bits can be programmed to select various
device configurations. Three bits are for the selection of
the oscillator type; one bit is the Watchdog Timer
enable bit, one bit is the MCLR enable bit and one bit is
for code protection (Register 7-1).
Preliminary
DS41338B-page 35
MCV14A
REGISTER 7-1:
CPDF
CONFIG: CONFIGURATION WORD REGISTER
IOSCFS
MCLRE
CP
WDTE
FOSC2
FOSC1
bit 7
bit 0
bit 7
CPDF: Code Protection bit Flash Data Memory

1 = Code protection off
0 = Code protection on
bit 6
IOSCFS: Internal Oscillator Frequency Select bit

1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 5
MCLRE: Master Clear Enable bit

1 = RB3/MCLR pin functions as MCLR
0 = RB3/MCLR pin functions as RB3, MCLR internally tied to VDD
bit 4
CP: Code Protection bit User Program Memory

1 = Code protection off
0 = Code protection on
bit 3
WDTE: Watchdog Timer Enable bit

1 = WDT enabled
0 = WDT disabled
bit 2-0
FOSC<2:0>: Oscillator Selection bits

000 = LP oscillator and 18 ms DRT
001 = XT oscillator and 18 ms DRT
010 = HS oscillator and 18 ms DRT
011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT(1)
100 = INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT(1)
101 = INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT(1)
110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT(1)
111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT(1)
Note 1:
FOSC0
DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in acceptable operation. Refer to Section 11.1 DC Characteristics: MCV14A (Industrial) and Section 11.2
DC Characteristics: MCV14A for VDD rise time and stability requirements for this mode of operation.
DS41338B-page 36
Preliminary
MCV14A
7.2
FIGURE 7-1:
Oscillator Configurations
7.2.1
OSCILLATOR TYPES
The MCV14A device can be operated in up to six different Oscillator modes. The user can program up to three
Configuration bits (FOSC<2:0>). To select one of these
modes:
LP:
XT:
HS:
INTRC:
EXTRC:
EC:
7.2.2
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
Internal 4/8 MHz Oscillator
External Resistor/Capacitor
External High-Speed Clock Input
C1(1)
RS(2)
RF(3)
To internal
logic
OSC2
C2(1)
Note 1:
In HS, XT or LP modes, a crystal or ceramic resonator

is connected to the RB5/OSC1/CLKIN and
RB4/OSC2/CLKOUT pins to establish oscillation
(Figure 7-1). The MCV14A oscillator designs require
the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS, XT or LP modes, the
device can have an external clock source drive the
RB5/OSC1/CLKIN pin (Figure 7-2). This pin should be
left open and unloaded. Also when using this mode, the
external clock should observe the frequency limits for
the Clock mode chosen (HS, XT or LP).
Note 1: This device has been designed to perform to the parameters of its data sheet.
It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance characteristics than its earlier version. These
differences may cause this device to
perform differently in your application
than the earlier version of this device.
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
MCV14A
Sleep
XTAL
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
OSC1
2:
3:
See Capacitor Selection tables for

recommended values of C1 and C2.
A series resistor (RS) may be required for AT
strip cut crystals.
RF approx. value = 10 M.
FIGURE 7-2:
EXTERNAL CLOCK INPUT

OPERATION (HS, XT, LP
OR EC OSC
CONFIGURATION)
EC, HS, XT, LP

Clock From
ext. system
RB5/OSC1/CLKIN
MCV14A
OSC2/CLKOUT/RB4
Note 1:
OSC2/CLKOUT/RB4(1)
RB4 is available in EC mode only.
TABLE 7-1:
CAPACITOR SELECTION FOR

CERAMIC RESONATORS
Osc
Type
Resonator
Freq.
XT
4.0 MHz
30 pF
30 pF
HS
16 MHz
10-47 pF
10-47 pF
Note 1:
Preliminary
Cap. Range
C1
Cap. Range
C2
These values are for design guidance

only. Since each resonator has its own
characteristics, the user should consult
the resonator manufacturer for
appropriate values of external
components.
DS41338B-page 37
MCV14A
TABLE 7-2:
CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR(2)
Osc
Type
Resonator
Freq.
Cap. Range
C1
Cap. Range
C2
LP
32 kHz(1)
15 pF
15 pF
XT
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
20 MHz
15-47 pF
15-47 pF
HS
Note 1:
2:
Figure 7-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 7-4:
For VDD > 4.5V, C1 = C2 30 pF is

recommended.
These values are for design guidance
only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own
characteristics, the user should consult
the crystal manufacturer for appropriate
values of external components.
330
EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT
Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 k resistor provides the
negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit
could be used for external oscillator designs.
FIGURE 7-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
CLKIN
74AS04
MCV14A
10k
XTAL
10k
20 pF
To Other
Devices
330
74AS04
74AS04
74AS04
CLKIN
0.1 mF
MCV14A
XTAL
7.2.4
7.2.3
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used.
Figure 7-5 shows how the R/C combination is
connected to the MCV14A device. For REXT values
below 3.0 k, the oscillator operation may become
unstable, or stop completely. For very high REXT values
(e.g., 1 M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 5.0 k and 100 k.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
Section 11.0 Electrical Characteristics shows RC
frequency variation from part-to-part due to normal
process variation. The variation is larger for larger values of R (since leakage current variation will affect RC
frequency more for large R) and for smaller values of C
(since variation of input capacitance will affect RC
frequency more).
20 pF
DS41338B-page 38
Preliminary
MCV14A
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
FIGURE 7-5:
EXTERNAL RC
OSCILLATOR MODE
VDD
REXT
OSC1
Internal
clock
CEXT
MCV14A
VSS
FOSC/4
OSC2/CLKOUT
7.2.5
INTERNAL 4/8 MHz RC

OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz

(nominal) system clock at VDD = 5V and 25C, (see
Section 11.0 Electrical Characteristics for
information on variation over voltage and temperature).
In addition, a calibration instruction is programmed into
the last address of memory, which contains the
calibration value for the internal RC oscillator. This
location is always non-code protected, regardless of
the code-protect settings. This value is programmed as
a MOVLW XX instruction where XX is the calibration
value, and is placed at the Reset vector. This will load
the W register with the calibration value upon Reset
and the PC will then roll over to the users program at
address 0x000. The user then has the option of writing
the value to the OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
trim the internal oscillator to remove process variation
from the oscillator frequency.
Note:
Erasing the device will also erase the

pre-programmed internal calibration value
for the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
For the MCV14A device, only bits <7:1> of OSCCAL

are used for calibration. See Register 3-3 for more
information.
Note:
Preliminary
The bit 0 of the OSCCAL register is

unimplemented and should be written as
0 when modifying OSCCAL for
compatibility with future devices.
DS41338B-page 39
MCV14A
7.3
Reset
The device differentiates between various kinds of

Reset:
Power-on Reset (POR)

MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Time-out Reset during normal operation
WDT Time-out Reset during Sleep
Wake-up from Sleep on pin change
TABLE 7-3:
Register
W
Some registers are not reset in any way, they are

unknown on POR and unchanged in any other Reset.
Most other registers are reset to Reset state on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and RBWUF bits. They are set or cleared
differently in different Reset situations. These bits are
used in software to determine the nature of Reset. See
Table 7-3 for a full description of Reset states of all
registers.
RESET CONDITIONS FOR REGISTERS

Address
Power-on Reset
MCLR Reset, WDT Time-out,

Wake-up On Pin Change
qqqq qqq0(1)
qqqq qqq0(1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
FSR
04h
100x xxxx
1uuu uuuu
OSCCAL
05h
1111 111-
uuuu uuu-
PORTB
06h
--xx xxxx
--uu uuuu
PORTC
07h
--xx xxxx
--uu uuuu
CMICON0
08h
q111 1111
quuu uuuu
ADCON0
09h
1111 1100
1111 1100
ADRES
0Ah
xxxx xxxx
uuuu uuuu
CM2CON0
0Bh
q111 1111
quuu uuuu
VRCON
0Ch
001-1111
uuu-uuuu
OPTION
1111 1111
1111 1111
TRISB
--11 1111
--11 1111
qq0q quuu(2)
TRISC
--11 1111
--11 1111
EECON
21h/61h
---0 x000
---0 q000
EEDATA
25h/65h
xxxx xxxx
uuuu uuuu
EEADR
26h/66h
--xx xxxx
--uu uuuu
Legend: u = unchanged, x = unknown, = unimplemented bit, read as 0, q = value depends on condition.

Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of
memory.
2: See Table 7-4 for Reset value for specific conditions.
DS41338B-page 40
Preliminary
MCV14A
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h
PCL Addr: 02h
Power-on Reset
0001 1xxx
1111 1111
MCLR Reset during normal operation
000u uuuu
1111 1111
MCLR Reset during Sleep
0001 0uuu
1111 1111
WDT Reset during Sleep
0000 0uuu
1111 1111
WDT Reset normal operation
0000 uuuu
1111 1111
Wake-up from Sleep on pin change
1001 0uuu
1111 1111
Legend: u = unchanged, x = unknown, = unimplemented bit, read as 0.
Preliminary
DS41338B-page 41
MCV14A
7.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the

1 state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 7-6.
FIGURE 7-6:
MCLR SELECT
A power-up example where MCLR is held low is shown

in Figure 7-8. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
RBWU
RB3/MCLR/VPP
MCLRE
7.4
The Power-on Reset circuit and the Device Reset

Timer (see Section 7.5 Device Reset Timer (DRT))
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms or 1 ms, it will
reset the Reset latch and thus end the on-chip Reset
signal.
Internal MCLR
Power-on Reset (POR)
The MCV14A device incorporates an on-chip

Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the RB3/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as RB3.
An internal weak pull-up resistor is implemented using
a transistor (refer to Table 11-5 for the pull-up resistor
ranges). This will eliminate external RC components
usually needed to create a Power-on Reset. A
maximum rise time for VDD is specified. See
Section 11.0 Electrical Characteristics for details.
When the device starts normal operation (exit the
Reset condition), device operating parameters
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
parameters are met.
In Figure 7-9, the on-chip Power-on Reset feature is

being used (MCLR and VDD are tied together or the pin
is programmed to be RB3. The VDD is stable before the
start-up timer times out and there is no problem in getting a proper Reset. However, Figure 7-10 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 7-9).
Note:
When the device starts normal operation

(exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Notes

AN522 Power-Up Considerations (DS00522) and
AN607 Power-up Trouble Shooting (DS00607).
A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 7-7.
DS41338B-page 42
Preliminary
MCV14A
FIGURE 7-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
RB3/MCLR/VPP
MCLR Reset
MCLRE
Start-up Timer
WDT Reset
WDT Time-out
Pin Change
Sleep
(10 s, 1.125 ms
or 18 ms)
CHIP Reset
Wake-up on pin Change Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 7-8:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME
FIGURE 7-9:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Preliminary
DS41338B-page 43
MCV14A
FIGURE 7-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS41338B-page 44
Preliminary
MCV14A
7.5
TABLE 7-5:
Device Reset Timer (DRT)
On the MCV14A device, the DRT runs any time the

device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 7-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a Reset condition after MCLR has reached
a logic high (VIH MCLR) level. Programming
RB3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/or
space restricted applications, as well as allowing the use
of the RB3/MCLR/VPP pin as a general purpose input.
The Device Reset Time delays will vary from
chip-to-chip due to VDD, temperature and process
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 7.8.2 Wake-up
from Sleep, Notes 1, 2 and 3.
7.6
Oscillator
Configuration
TYPICAL DRT PERIODS

POR Reset
Subsequent
Resets
18 ms
18 ms
EC
1.125 ms
10 s
INTOSC, EXTRC
1.125 ms
10 s
HS, XT, LP
7.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the RB5/OSC1/CLKIN pin and
the internal 4/8 MHz oscillator. This means that the
WDT will run even if the main processor clock has been
stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently
programming the configuration WDTE
Section 7.1 Configuration Bits).
MCV14A Programming Specifications
how to access the Configuration Word.
disabled by
as a 0 (see
Refer to the
to determine
Preliminary
DS41338B-page 45
MCV14A
FIGURE 7-11:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source

(Figure 6-1)
0
1
Watchdog
Time
M
U
X
Postscaler
8-to-1 MUX
PS<2:0>(1)
PSA
WDT Enable
Configuration
Bit
To Timer0 (Figure 6-4)

0
1
MUX
PSA(1)
WDT Time-out
Note 1:
TABLE 7-6:
Address
N/A
PSA, PS<2:0> are bits in the OPTION register.
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer.
DS41338B-page 46
Preliminary
MCV14A
7.7
Time-out Sequence, Power-down

and Wake-up from Sleep Status
Bits (TO, PD, RBWUF)
The TO, PD and RBWUF bits in the STATUS register

can be tested to determine if a Reset condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
7.8.2
The device can wake-up from Sleep through one of

the following events:
An external Reset input on RB3/MCLR/VPP pin,
when configured as MCLR.
A Watchdog Timer Time-out Reset (if WDT was
enabled).
A change on input pin RB0, RB1, RB3 or RB4
when wake-up on change is enabled.
1.
2.
3.
TABLE 7-7:
TO/PD/RBWUF STATUS
AFTER RESET
RBWUF
TO
PD
Reset Caused By
WDT wake-up from Sleep
WDT time-out (not from

Sleep)
MCLR wake-up from Sleep
Power-up
MCLR not during Sleep
Wake-up from Sleep on pin

change
7.8
These events cause a device Reset. The TO, PD and

RBWUF bits can be used to determine the cause of
device Reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The RBWUF bit indicates a change in state while in
Sleep at pins RB0, RB1, RB3 or RB4 (since the last file
or bit operation on RB port).
Note:
Legend: u = unchanged
Note 1: The TO, PD and RBWUF bits maintain
their status (u) until a Reset occurs. A
low-pulse on the MCLR input does not
change the TO, PD and RBWUF Status
bits.
WAKE-UP FROM SLEEP
Caution: Right before entering Sleep,

read the input pins. When in Sleep,
wake-up occurs when the values at the
pins change from the state they were in at
the last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.
Power-down Mode (Sleep)
A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).
7.8.1
SLEEP
The Power-Down mode is entered by executing a

SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
Note:
A Reset generated by a WDT time-out

does not drive the MCLR pin low.
For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the
RB3/MCLR/VPP pin must be at a logic high level if
MCLR is enabled.
Preliminary
DS41338B-page 47
MCV14A
7.9
FIGURE 7-12:
Program Verification/Code
Protection
If the code protection bit has not been programmed, the

on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
External
Connector
Signals
The last memory location can be read regardless of the

code protection bit setting on the MCV14A device.
7.10
ID Locations
Four memory locations are designated as ID locations

where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as 0s.
7.11
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
MCV14A
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB1
Data I/O
RB0
VDD
To Normal
Connections
The MCV14A microcontroller can be serially

programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom
firmware, to be programmed.
The devices are placed into a Program/Verify mode by
holding the RB1 and RB0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH. RB1 becomes the
programming clock and B0 becomes the programming
data. Both RB1 and RB0 are Schmitt Trigger inputs in
this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read.
A typical In-Circuit Serial Programming connection is
shown in Figure 7-12.
DS41338B-page 48
Preliminary
MCV14A
8.0
ANALOG-TO-DIGITAL (A/D)
CONVERTER
Note:
The A/D Converter allows conversion of an analog

signal into an 8-bit digital signal.
8.1
Clock Divisors
The ADC has 4 clock source settings ADCS<1:0>.

There are 3 divisor values 16, 8 and 4. The fourth
setting is INTOSC with a divisor of 4. These settings
will allow a proper conversion when using an external
oscillator at speeds from 20 MHz to 350 kHz. Using an
external oscillator at a frequency below 350 kHz
requires the ADC oscillator setting to be INTOSC/4
(ADCS<1:0> = 11) for valid ADC results.
The ADC requires 13 TAD periods to complete a
conversion. The divisor values do not affect the number
of TAD periods required to perform a conversion. The
divisor values determine the length of the TAD period.
When the ADCS<1:0> bits are changed while an ADC
conversion is in process, the new ADC clock source will
not be selected until the next conversion is started. This
clock source selection will be lost when the device
enters Sleep.
Note:
8.1.1
The ADC clock is derived from the instruction clock. The ADCS divisors are then
applied to create the ADC clock
VOLTAGE REFERENCE
There is no external voltage reference for the ADC. The

ADC reference voltage will always be VDD.
8.1.2
ANALOG MODE SELECTION
The ANS<1:0> bits are used to configure pins for

analog input. Upon any Reset, ANS<1:0> defaults to
11. This configures pins AN0, AN1 and AN2 as analog
inputs. The comparator output, C1OUT, will override
AN2 as an input if the comparator output is enabled.
Pins configured as analog inputs are not available for
digital output. Users should not change the ANS bits
while a conversion is in process. ANS bits are active
regardless of the condition of ADON.
8.1.3
It is the users responsibility to ensure that

use of the ADC and comparator simultaneously on the same pin, does not
adversely affect the signal being
monitored or adversely effect device
operation.
When the CHS<1:0> bits are changed during an ADC

conversion, the new channel will not be selected until
the current conversion is completed. This allows the
current conversion to complete with valid results. All
channel selection information will be lost when the
device enters Sleep.
TABLE 8-1:
CHANNEL SELECT (ADCS)

BITS AFTER AN EVENT
Event
MCLR
ADCS<1:0>
11
Conversion completed
CS<1:0>
Conversion terminated
CS<1:0>
Power-on
11
Wake from Sleep
11
8.1.4
THE GO/DONE BIT
The GO/DONE bit is used to determine the status of a

conversion, to start a conversion and to manually halt
a conversion in process. Setting the GO/DONE bit
starts a conversion. When the conversion is complete,
the ADC module clears the GO/DONE bit. A conversion can be terminated by manually clearing the GO/
DONE bit while a conversion is in process. Manual termination of a conversion may result in a partially converted result in ADRES.
The GO/DONE bit is cleared when the device enters
Sleep, stopping the current conversion. The ADC does
not have a dedicated oscillator, it runs off of the instruction clock. Therefore, no conversion can occur in sleep.
The GO/DONE bit cannot be set when ADON is clear.
ADC CHANNEL SELECTION
The CHS bits are used to select the analog channel to

be sampled by the ADC. The CHS<1:0> bits can be
changed at any time without adversely effecting a conversion. To acquire an analog signal the CHS<1:0>
selection must match one of the pin(s) selected by the
ANS<1:0> bits. When the ADC is on (ADON = 1) and a
channel is selected that is also being used by the
comparator, then both the comparator and the ADC will
see the analog voltage on the pin.
Preliminary
DS41338B-page 49
MCV14A
8.1.5
SLEEP
This ADC does not have a dedicated ADC clock, and

therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE and ADON bit will be cleared.
This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the
nature of the conversion process, the ADRES may contain a partial conversion. At least 1 bit must have been
converted prior to Sleep to have partial conversion data
in ADRES. The ADCS and CHS bits are reset to their
default condition; ANS<1:0> = 11 and CHS<1:0> = 11.
For accurate conversions, TAD must meet the
following:
500 ns < TAD < 50 s
TAD = 1/(FOSC/divisor)
Shaded areas indicate TAD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/8 for the ADC clock source.
TABLE 8-2:
Source
TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
ADCS
<1:0>
Divisor
20
MHz
16
MHz
11
.5 s
1 s
INTOSC
8 MHz 4 MHz 1 MHz
500
kHz
350
kHz
200
kHz
100
kHz
32 kHz
FOSC
10
.2 s
.25 s
.5 s
1 s
4 s
8 s
11 s
20 s
40 s
125 s
FOSC
01
.4 s
.5 s
1 s
2 s
8 s
16 s
23 s
40 s
80 s
250 s
FOSC
00
16
.8 s
1 s
2 s
4 s
16 s
32 s
46 s
80 s
160 s
500 s
TABLE 8-3:
EFFECTS OF SLEEP ON ADCON0

ANS1
Entering
Sleep
ANS0
Unchanged Unchanged
Wake or
Reset
DS41338B-page 50
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
Preliminary
MCV14A
8.1.6
ANALOG CONVERSION RESULT

REGISTER
right shifts of the leading one have taken place, the

conversion is complete; the leading one has been
shifted out and the GO/DONE bit is cleared.
The ADRES register contains the results of the last

conversion. These results are present during the
sampling period of the next analog conversion process.
After the sampling period is over, ADRES is cleared
(= 0). A leading one is then right shifted into the
ADRES to serve as an internal conversion complete
bit. As each bit weight, starting with the MSB, is
converted, the leading one is shifted right and the
converted bit is stuffed into ADRES. After a total of 9
REGISTER 8-1:
If the GO/DONE bit is cleared in software during a

conversion, the conversion stops. The data in ADRES
is the partial conversion result. This data is valid for the
bit weights that have been converted. The position of
the leading one determines the number of bits that
have been converted. The bits that were not converted
before the GO/DONE was cleared are unrecoverable.
ADCON0: A/D CONTROL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
ANS<1:0>: ADC Analog Input Pin Select bits(1), (2), (5)

00 = No pins configured for analog input
01 = AN2 configured as an analog input
10 = AN2 and AN0 configured as analog inputs
11 = AN2, AN1 and AN0 configured as analog inputs
bit 5-4
ADCS<1:0>: ADC Conversion Clock Select bits

00 = FOSC/16
01 = FOSC/8
10 = FOSC/4
11 = INTOSC/4
bit 3-2
CHS<1:0>: ADC Channel Select bits(3, 5)

00 = Channel AN0
01 = Channel AN1
10 = Channel AN2
11 = 0.6V absolute voltage reference
bit 1
GO/DONE: ADC Conversion Status bit(4)

1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared
by hardware when the ADC is done converting.
0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion.
bit 0
ADON: ADC Enable bit

1 = ADC module is operating
0 = ADC module is shut-off and consumes no power
Note 1:
When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin
function previously defined. The only exception to this is the comparator, where the analog input to the comparator and
the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator
input does not affect their application.
2:
The ANS<1:0> bits are active regardless of the condition of ADON.
3:
CHS<1:0> bits default to 11 after any Reset.
4:
If the ADON bit is clear, the GO/DONE bit cannot be set.
5:
C1OUT, when enabled, overrides AN2.
Preliminary
DS41338B-page 51
MCV14A
REGISTER 8-2:
ADRES: ADDRESS REGISTER
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
EXAMPLE 8-1:
PERFORMING AN
ANALOG-TO-DIGITAL
CONVERSION
EXAMPLE 8-2:
;Sample code operates out of BANK0
loop0
MOVLW 0xF1
;configure A/D
MOVWF ADCON0
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for DONE
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
loop1
;setup for read of

;channel 1
GOTO loop1
loop2
BSF ADCON0, 3 ;setup for read of

BCF ADCON0, 2 ;channel 2
GOTO loop2
CHANNEL SELECTION
CHANGE DURING
CONVERSION
MOVLW 0xF1
MOVWF ADCON0
BSF ADCON0, 1
BSF ADCON0, 2
;configure A/D
loop0
;start conversion
;setup for read of
;channel 1
GOTO loop0
loop1

BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
GOTO loop1
BSF ADCON0, 2
DS41338B-page 52
x = Bit is unknown
loop2
Preliminary

GOTO loop2
CLRF ADCON0
;optional: returns
;pins to Digital mode and turns off
;the ADC module
MCV14A
9.0
COMPARATOR(S)
This device contains two comparators

comparator voltage reference.
REGISTER 9-1:
and
CM1CON0: COMPARATOR C1 CONTROL REGISTER
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
C1OUT: Comparator Output bit

1 = VIN+ > VIN0 = VIN+ < VIN-
bit 6
C1OUTEN: Comparator Output Enable bit(1), (2)

1 = Output of comparator is NOT placed on the C1OUT pin
0 = Output of comparator is placed in the C1OUT pin
bit 5
C1POL: Comparator Output Polarity bit(2)

1 = Output of comparator is not inverted
0 = Output of comparator is inverted
bit 4
C1T0CS: Comparator TMR0 Clock Source bit(2)

1 = TMR0 clock source selected by T0CS control bit
0 = Comparator output used as TMR0 clock source
bit 3
C1ON: Comparator Enable bit

1 = Comparator is on
0 = Comparator is off
bit 2
C1NREF: Comparator Negative Reference Select bit(2)

1 = C1IN- pin
0 = 0.6V VREF
bit 1
C1PREF: Comparator Positive Reference Select bit(2)

1 = C1IN+ pin
0 = C1IN- pin
bit 0
C1WU: Comparator Wake-up On Change Enable bit(2)

1 = Wake-up On Comparator Change is disabled
0 = Wake-up On Comparator Change is enabled
Note 1:
x = Bit is unknown
Overrides T0CS bit for TRIS control of RB2.
2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have
precedence.
Preliminary
DS41338B-page 53
MCV14A
REGISTER 9-2:
CM2CON0: COMPARATOR C2 CONTROL REGISTER
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
C2OUT: Comparator Output bit

1 = VIN+ > VIN0 = VIN+ < VIN-
bit 6
C2OUTEN: Comparator Output Enable bit(1), (2)

1 = Output of comparator is NOT placed on the C2OUT pin
0 = Output of comparator is placed in the C2OUT pin
bit 5
C2POL: Comparator Output Polarity bit(2)

1 = Output of comparator not inverted
0 = Output of comparator inverted
bit 4
C2PREF2: Comparator Positive Reference Select bit(2)

1 = C1IN+ pin
0 = C2IN- pin
bit 3
C2ON: Comparator Enable bit

1 = Comparator is on
0 = Comparator is off
bit 2
C2NREF: Comparator Negative Reference Select bit(2)

1 = C2IN- pin
0 = CVREF
bit 1
C2PREF1: Comparator Positive Reference Select bit(2)

1 = C2IN+ pin
0 = C2PREF2 controls analog input selection
bit 0
C2WU: Comparator Wake-up on Change Enable bit(2)

1 = Wake-up on Comparator change is disabled
0 = Wake-up on Comparator change is enabled.
x = Bit is unknown
Note 1: Overrides TOCS bit for TRIS control of RC4.

2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have
precedence.
DS41338B-page 54
Preliminary
MCV14A
FIGURE 9-1:
COMPARATORS BLOCK DIAGRAM

RB2/C1OUT
C1PREF
C1IN+
C1OUTEN
+
C1IN-
0
C1OUT (Register)
1
-
VREF
(0.6V)
0
C1NREF
C1POL
C1ON
T0CKI
T0CKI Pin
C1T0CS
RC4/C2OUT
C2PREF1
C2IN+
READ
CM1CON0
C2OUTEN
1
+
0
C2OUT (Register)
0
C2PREF2
C2IN-
C2POL
C2ON
1
0
CVREF
C2NREF
C1WU
S
CWUF
READ
CM2CON0
C2WU
Preliminary
DS41338B-page 55
MCV14A
9.1
Comparator Operation
A single comparator is shown in Figure 9-2 along with

the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. The shaded area of the output of
the comparator in Figure 9-2 represent the uncertainty
due to input offsets and response time. See Table 11-2
for Common Mode Voltage.
FIGURE 9-2:
SINGLE COMPARATOR
VIN+
VIN-
Result
Note:
9.5
Analog levels on any pin that is defined as

a digital input may cause the input buffer
to consume more current than is specified.
Comparator Wake-up Flag
The Comparator Wake-up Flag is set whenever all of

the following conditions are met:
C1WU = 0 (CM1CON0<0>) or
C2WU = 0 (CM2CON0<0>)
CM1CON0 or CM2CON0 has been read to latch
the last known state of the C1OUT and C2OUT bit
(MOVF CM1CON0, W)
Device is in Sleep
The output of a comparator has changed state
The wake-up flag may be cleared in software or by
another device Reset.
9.6
VIN-
Comparator Operation During

Sleep
VIN+
When the comparator is enabled it is active. To

minimize power consumption while in Sleep mode, turn
off the comparator before entering Sleep.
Result
9.7
9.2
Comparator Reference
An internal reference signal may be used depending on

the comparator operating mode. The analog signal that
is present at VIN- is compared to the signal at VIN+, and
the digital output of the comparator is adjusted accordingly (Figure 9-2). Please see Section 10.0 Comparator Voltage Reference Module for internal
reference specifications.
9.3
Comparator Response Time
Response time is the minimum time after selecting a

new reference voltage or input source before the
comparator output is to have a valid level. If the
comparator inputs are changed, a delay must be used
to allow the comparator to settle to its new state.
Please see Table 11-3 for comparator response time
specifications.
9.4
Effects of Reset
A Power-on Reset (POR) forces the CM2CON0

register to its Reset state. This forces the Comparator
input pins to analog Reset mode. Device current is
minimized when analog inputs are present at Reset
time.
9.8
Analog Input Connection

Considerations
A simplified circuit for an analog input is shown in

Figure 9-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
Comparator Output
The comparator output is read through the CM1CON0

or CM2CON0 register. This bit is read-only. The
comparator output may also be used externally, see
Figure 9-2.
DS41338B-page 56
Preliminary
MCV14A
FIGURE 9-3:
ANALOG INPUT MODE

VDD
VT = 0.6V
RS < 10 K
RIC
AIN
CPIN
5 pF
VA
VT = 0.6V
ILEAKAGE
500 nA
VSS
Legend:
TABLE 9-1:
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the Pin
Interconnect Resistance
Source Impedance
Analog Voltage
REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
Value on All
Other Resets
STATUS
RBWUF
CWUF
PA0
TO
PD
DC
0001 1xxx
qq0q quuu
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
uuuu uuuu
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
uuuu uuuu
--11 1111
--11 1111
Name
TRIS
Legend:
x = Unknown, u = Unchanged, = Unimplemented, read as 0, q = Depends on condition.
Preliminary
DS41338B-page 57
MCV14A
NOTES:
DS41338B-page 58
Preliminary
MCV14A
10.0
COMPARATOR VOLTAGE
REFERENCE MODULE
10.2
The Comparator Voltage Reference module also

allows the selection of an internally generated voltage
reference for one of the C2 comparator inputs. The
VRCON register (Register 10-1) controls the Voltage
Reference module shown in Figure 10-1.
10.1
Configuring The Voltage

Reference
The voltage reference can output 32 voltage levels; 16

in a high range and 16 in a low range.
Equation 10-1 determines the output voltages:
EQUATION 10-1:
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to

construction of the module. The transistors on the top
and bottom of the resistor ladder network (Figure 10-1)
keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the
VREN bit (VRCON<7>). When disabled, the reference
voltage is VSS when VR<3:0> is 0000 and the VRR
(VRCON<5>) bit is set. This allows the comparator to
detect a zero-crossing and not consume the CVREF
module current.
The voltage reference is VDD derived and, therefore,
the CVREF output changes with fluctuations in VDD.
The tested absolute accuracy of the comparator
voltage reference can be found in Section 11.2 DC
Characteristics: MCV14A.
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD

VRR = 0 (high range):
CVREF = (VDD/4) + (VR<3:0> x VDD/32)
REGISTER 10-1:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
VREN: CVREF Enable bit

1 = CVREF is powered on
0 = CVREF is powered down, no current is drawn
bit 6
VROE: CVREF Output Enable bit(1)

1 = CVREF output is enabled
0 = CVREF output is disabled
bit 5
VRR: CVREF Range Selection bit

1 = Low range
0 = High range
bit 4
bit 3-0
VR<3:0> CVREF Value Selection bit

When VRR = 1: CVREF= (VR<3:0>/24)*VDD
When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD
x = Bit is unknown
Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the
CVREF pin.
2: CVREF controls for ratio metric reference applies to Comparator 2.
Preliminary
DS41338B-page 59
MCV14A
FIGURE 10-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages
8R
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator 2
Input
VR<3:0>
RC2/CVREF
VREN
VR<3:0> = 0000
VRR
VROE
TABLE 10-1:
Name
VRCON
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
Value on all
other Resets
000- 0000
VREN
VROE
VRR
VR3
VR2
VR1
VR0
000- 0000
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
1111 1111
uuuu uuuu
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
uuuu uuuu
Legend:
x = unknown, u = unchanged, = unimplemented, read as 0.
DS41338B-page 60
Preliminary
MCV14A
11.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()

Ambient temperature under bias............................................................................................................ -40C to +85C
Storage temperature ............................................................................................................................ -65C to +150C
Voltage on VDD with respect to VSS ............................................................................................................... 0 to +6.5V
Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) .................................................................................................................................. 700 mW
Max. current out of VSS pin ................................................................................................................................ 200 mA
Max. current into VDD pin ................................................................................................................................... 150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................20 mA
Max. output current sunk by any I/O pin .............................................................................................................. 25 mA
Max. output current sourced by any I/O pin ......................................................................................................... 25 mA
Max. output current sourced by I/O port .............................................................................................................. 75 mA
Max. output current sunk by I/O port ................................................................................................................... 75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOL x IOL)
NOTICE:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Preliminary
DS41338B-page 61
MCV14A
MCV14A VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
FIGURE 11-1:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
INTOSC
ONLY
2.5
2.0
0
20
10
25
Frequency (MHz)
FIGURE 11-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE
Oscillator Mode
LP
XT
XTRC
INTOSC
EC
HS
0
200 kHz
4 MHz
8 MHz
20 MHz
Frequency
DS41338B-page 62
Preliminary
MCV14A
11.1
DC Characteristics: MCV14A (Industrial)

Standard Operating Conditions (unless otherwise specified)
Operating Temperature 40C TA +85C (industrial)
DC Characteristics
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
See Figure 11-1
D002
VDR
RAM Data Retention Voltage(2)
1.5*
Device in Sleep mode
D003
VPOR
VDD Start Voltage to ensure

Power-on Reset
Vss
See Section 7.4 Power-on

Reset (POR) for details
D004
SVDD
VDD Rise Rate to ensure

Power-on Reset
0.05*
V/ms
See Section 7.4 Power-on

Reset (POR) for details
D010
IDD
Supply Current(3,4)
175
400
250
700
A
mA
FOSC = 4 MHz, VDD = 2.0V

250
0.75
450
1.2
A
mA

1.8
2.5
mA
11
38
22
55
A
A
FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V
D020
IPD
Power-down Current(5)
0.1
0.35
1.2
2.2
A
A
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current(5)
1.0
7.0
3.0
16.0
A
A
VDD = 2.0V
VDD = 5.0V
D023
ICMP
Comparator Current(5)
15
60
26
76
A
A
VDD = 2.0V (per comparator)

VDD = 5.0V (per comparator)
D022
IVREF
VREF Current(5)
30
75
75
135
A
A
VDD = 2.0V (high range)

VDD = 5.0V (high range)
D023
IFVR
Internal 0.6V Fixed Voltage

Reference Current(5)
100
120
175
205
VDD = 2.0V (reference and 1

comparator enabled)
VDD = 5.0V (reference and 1
comparator enabled)
120
150
2.0V
200
250
5.0V
D024
IAD
A/D Conversion Current
* These parameters are characterized but not tested.

Note 1: Data in the Typical (Typ) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in Active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =
VDD; WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
6: Does not include current through REXT. The current through the resistor can be estimated by the formula:
I = VDD/2REXT (mA) with REXT in k.
Preliminary
DS41338B-page 63
MCV14A
11.2
DC Characteristics: MCV14A
TABLE 11-1:
DC CHARACTERISTICS: MCV14A (Industrial)

Operating temperature
-40C TA +85C (industrial)
Operating voltage VDD range as described in DC spec.
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Min
Typ
Max
Units
Conditions
Input Low Voltage

I/O ports
D030
with TTL buffer
D030A
Vss
0.8V
For all 4.5 VDD 5.5V
Vss
0.15 VDD
Otherwise
D031
with Schmitt Trigger buffer
Vss
0.15 VDD
D032
MCLR, T0CKI
Vss
0.15 VDD
D033
OSC1 (EXTRC mode), EC(1)
Vss
0.15 VDD
D033
OSC1 (HS mode)
Vss
0.3 VDD
OSC1 (XT and LP modes)
Vss
0.3
2.0
VDD
4.5 VDD 5.5V
0.25VDD
+ 0.8V
VDD
Otherwise
For entire VDD range
D033
VIH
Input High Voltage

I/O ports
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
0.85VDD
VDD
D042
MCLR, T0CKI
0.85VDD
VDD
D042A
OSC1 (EXTRC mode), EC(1)
0.85VDD
VDD
D042A
OSC1 (HS mode)
0.7VDD
VDD
D043
OSC1 (XT and LP modes)
1.6
VDD
PORTB weak pull-up current(4)
50
250
400
D070
IPUR
IIL
VDD = 5V, VPIN = VSS
Input Leakage Current(2)
D060
I/O ports
Vss VPIN VDD, Pin at high-impedance
D061
RB3/MCLR(3)
0.7
Vss VPIN VDD
D063
OSC1
Vss VPIN VDD, XT, HS and LP osc

configuration
D080
I/O ports
0.6
IOL = 8.5 mA, VDD = 4.5V, 40C to +85C
D083
CLKOUT
0.6
IOL = 1.6 mA, VDD = 4.5V, 40C to +85C
D090
I/O ports(2)
VDD 0.7
IOH = -3.0 mA, VDD = 4.5V, 40C to +85C
D092
CLKOUT
VDD 0.7
IOH = -1.3 mA, VDD = 4.5V, 40C to +85C

In XT, HS and LP modes when external clock is
used to drive OSC1.
Output Low Voltage
Output High Voltage
Capacitive Loading Specs on Output Pins

D100
D101
OSC2 pin
15
pF
All I/O pins and OSC2
50
pF
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
MCV14A be driven with external clock in RC mode.
2: Negative current is defined as coming out of the pin.
3: This spec. applies to RB3/MCLR configured as RB3 with internal pull-up disabled.
4: This spec applies to all weak pull-up devices, including the weak pull-up found on RB3/MCLR. The current value listed will
be the same whether or not the pin is configured as RB3 with pull-up enabled or as MCLR.
DS41338B-page 64
Preliminary
MCV14A
TABLE 11-2:
COMPARATOR SPECIFICATIONS.
Comparator Specifications
Standard Operating Conditions (unless otherwise stated)

Operating temperature
-40C to 85C
Characteristics
Sym
Min
Typ
Max
Units
0.70
Internal Voltage Reference
VIVRF
0.50
0.60
Input offset voltage
VOS
5.0
10
mV
Input common mode voltage*
VCM
VDD 1.5
CMRR*
Response Time
(1)*
Comparator Mode Change to

Output Valid*
CMRR
55
db
TRT
150
400
ns
TMC2COV
10
Comments

Note 1: Response time measured with one comparator input at (VDD 1.5)/2 while the other input transitions from
VSS to VDD 1.5V.
TABLE 11-3:
Sym
CVRES
*
Note 1:
2:
COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS

Min
Typ
Max
Units
Resolution
Characteristics
VDD/24*
VDD/32
LSb
LSb
Low Range (VRR = 1)

High Range (VRR = 0)
Comments
Absolute Accuracy(2)
1/2*
1/2*
LSb
LSb
Low Range (VRR = 1)

High Range (VRR = 0)
Unit Resistor Value (R)
2K*
Settling Time(1)
10*
These parameters are characterized but not tested.

Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
Do not use reference externally when VDD < 2.7V. Under this condition, reference should only be used
with comparator Voltage Common mode observed.
Preliminary
DS41338B-page 65
MCV14A
TABLE 11-4:
A/D CONVERTER CHARACTERISTICS:
A/D Converter Specifications

Param
No.
A01
Sym
Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C TA +85C
Characteristic
Min
Typ
Max
Units
bit
Conditions
NR
Resolution
Integral Error
1.5
-1< EDNL 1.7
1.5
LSb VDD = 5.0V
-0.7
+2.2
LSb VDD = 5.0V
A03
EINL
A04
EDNL Differential Error
A06
EOFF Offset Error
A07
EGN
Gain Error
A10
Monotonicity
A25
VAIN
Analog Input
Voltage
VSS
A30
ZAIN
Recommended
Impedance of
Analog Voltage
Source
(1)
LSb VDD = 5.0V

LSb No missing codes to 8 bits
VDD = 5.0V
VDD
10
guaranteed
VSS VAIN VDD

Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
TABLE 11-5:
VDD (Volts)
RB0/RB1
2.0
5.5
RB3
2.0
5.5
PULL-UP RESISTOR RANGES

Temperature (C)
Min
Typ
Max
Units
-40
25
85
125
-40
25
85
125
73K
73K
82K
86K
15K
15K
19K
23K
105K
113K
123K
132k
21K
22K
26k
29K
186K
187K
190K
190K
33K
34K
35K
35K
-40
25
85
125
-40
25
85
125
63K
77K
82K
86K
16K
16K
24K
26K
81K
93K
96k
100K
20k
21K
25k
27K
96K
116K
116K
119K
22K
23K
28K
29K
DS41338B-page 66
Preliminary
MCV14A
11.3
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T Time
Lowercase subscripts (pp) and their meanings:

pp
2
to
mc
MCLR
ck
CLKOUT
osc
Oscillator
cy
Cycle time
os
OSC1
drt
Device Reset Timer
t0
T0CKI
io
I/O port
wdt
Watchdog Timer
Uppercase letters and their meanings:

S
F
Fall
Period
High
Rise
Invalid (high-impedance)
Valid
Low
High-impedance
FIGURE 11-3:
LOAD CONDITIONS
Legend:
pin
CL
VSS
CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
Preliminary
DS41338B-page 67
MCV14A
FIGURE 11-4:
EXTERNAL CLOCK TIMING

Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
TABLE 11-6:
EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS

Operating Temperature -40C TA +85C (industrial),
Operating Voltage VDD range is described in Section 11.1 DC
Characteristics: MCV14A (Industrial)
Param
No.
Characteristic
Min
Typ(1)
Max
External CLKIN Frequency(2)
DC
MHz XT Oscillator mode
DC
20
MHz HS Oscillator mode
DC
200
kHz
1A
Sym
FOSC
Oscillator Frequency
TOSC
External CLKIN
(2)
Period(2)
Oscillator Period(2)
Units
Conditions
LP Oscillator mode
MHz EXTRC Oscillator mode
0.1
MHz XT Oscillator mode
20
MHz HS Oscillator mode
200
kHz
250
ns
XT Oscillator mode
50
ns
HS Oscillator mode
LP Oscillator mode
LP Oscillator mode
250
ns
EXTRC Oscillator mode
250
10,000
ns
XT Oscillator mode
50
250
ns
HS Oscillator mode
LP Oscillator mode
TCY
Instruction Cycle Time
200
4/FOSC
ns
TosL,
TosH
Clock in (OSC1) Low or High

Time
50*
ns
XT Oscillator
2*
LP Oscillator
10*
ns
HS Oscillator
TosR,
TosF
Clock in (OSC1) Rise or Fall

Time
25*
ns
XT Oscillator
50*
ns
LP Oscillator
15*
ns
HS Oscillator
*
Note 1:
2:

Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for
design guidance only and are not tested.
All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. When an external clock
input is used, the max cycle time limit is DC (no clock) for all devices.
DS41338B-page 68
Preliminary
MCV14A
TABLE 11-7:
CALIBRATED INTERNAL RC FREQUENCIES
AC CHARACTERISTICS

Operating Temperature -40C TA +85C (industrial),
Operating Voltage VDD range is described in
Section 11.1 DC Characteristics: MCV14A (Industrial)
Param
No.
Freq
Min
Tolerance
F10
Sym
FOSC
Characteristic
Internal Calibrated
INTOSC Frequency(1)
Typ
Max
Units
Conditions
1%
7.92
8.00
8.08
MHz 3.5V, +25C
5%
7.60
8.00
8.40
MHz 2.0V VDD 5.5V

-40C TA +85C (Ind.)

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
Preliminary
DS41338B-page 69
MCV14A
FIGURE 11-5:
I/O TIMING
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 11-8:
TIMING REQUIREMENTS

AC
Operating Temperature -40C TA +85C (industrial)
CHARACTERISTICS Operating Voltage VDD range is described in Section 11.1 DC Characteristics: MCV14A
(Industrial)
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
17
TOSH2IOV
OSC1 (Q1 cycle) to Port Out Valid(2), (3)
100*
ns
18
TOSH2IOI
OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time)(2)
ns
19
TIOV2OSH
Port Input Valid to OSC1 (I/O in setup time)
ns
20
TIOR
Port Output Rise Time(3)
10
50**
ns
21
TIOF
Port Output Fall Time(3)
10
58**
ns
Legend:
*
**
Note 1:
2:
3:
TBD = To Be Determined.
These parameters are design targets and are not tested.
Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Measurements are taken in EXTRC mode.
See Figure 11-3 for loading conditions.
DS41338B-page 70
Preliminary
MCV14A
FIGURE 11-6:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out(2)
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pin(1)
Note 1:
2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
Runs in MCLR or WDT Reset only in XT, LP and HS modes.
TABLE 11-9:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER

AC CHARACTERISTICS
Param
No.
Max
Units
Conditions
Characteristic
30
TMCL
MCLR Pulse Width (low)
2000*
ns
VDD = 5.0V
31
TWDT
Watchdog Timer Time-out Period

(no prescaler)
9*
18*
30*
ms
VDD = 5.0V (Industrial)
32
TDRT
Device Reset Timer Period
9*
18*
30*
ms
VDD = 5.0V (Industrial)
34
TIOZ
I/O High-impedance from MCLR

low
2000*
ns
*
Note 1:
Min
Typ(1)
Sym

Preliminary
DS41338B-page 71
MCV14A
FIGURE 11-7:
TIMER0 CLOCK TIMINGS
T0CKI
40
41
42
TABLE 11-10: TIMER0 CLOCK REQUIREMENT

AC CHARACTERISTICS
Param
Sym
No.
40
41
42
*
Note 1:
Tt0H
Tt0L
Tt0P
Characteristic
T0CKI High Pulse
Width
T0CKI Low Pulse
Width
T0CKI Period
Min
No Prescaler
With Prescaler
No Prescaler
With Prescaler
Typ(1) Max Units
0.5 TCY + 20*
ns
10*
ns
0.5 TCY + 20*
ns
10*
ns
20 or TCY + 40* N
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)

DS41338B-page 72
Preliminary
MCV14A
TABLE 11-11: FLASH DATA MEMORY WRITE/ERASE TIME
AC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ(1)
Max
Units
43
TDW
Flash Data Memory

Write Cycle Time
3.5
ms
44
TDE
Flash Data Memory

Erase Cycle Time
3.5
ms
*
Note 1:
Conditions

Preliminary
DS41338B-page 73
MCV14A
NOTES:
DS41338B-page 74
Preliminary
MCV14A
12.0
PACKAGING INFORMATION
12.1
Package Marking Information
14-Lead PDIP (300 mil)
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCV14A
-I/PG e3 0215
0410017
Example
14-Lead SOIC (3.90 mm)
MCV14A-E
/SLG0125
0431017
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard MCV device marking consists of Microchip part number, year code, week code, and traceability
code. For MCV device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
Preliminary
DS41338B-page 75
MCV14A
14-Lead Plastic Dual In-Line (P) 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
NOTE 1
E1
D
E
A2
L
A1
b1
b
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
NOM
MAX
14
Pitch
Top to Seating Plane
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
.735
.750
.775
Tip to Seating Plane
.115
.130
.150
Lead Thickness
.008
.010
.015
b1
.045
.060
.070
.014
.018
.022
eB
Upper Lead Width

Lower Lead Width
Overall Row Spacing
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-005B
DS41338B-page 76
Preliminary
MCV14A
14-Lead Plastic Small Outline (SL) Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
e
h
A2
A1
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
14
Pitch
Overall Height
1.27 BSC
Molded Package Thickness
A2
1.25
Standoff
A1
0.10
0.25
Overall Width
Molded Package Width
E1
3.90 BSC
Overall Length
8.65 BSC
1.75
6.00 BSC
Chamfer (optional)
0.25
0.50
Foot Length
0.40
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
0.17
0.25
Lead Width
0.31
0.51
Mold Draft Angle Top
15
Mold Draft Angle Bottom
15
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-065B
Preliminary
DS41338B-page 77
MCV14A
APPENDIX A:
REVISION HISTORY
Revision A (November 2007)

Original release of this document.
Revision B (June 2009)
Revised Table 7-3: Reset Conditions for Registers;
11.1 DC Characteristics; Table 11-2: Comparator Specifications; Table 11-4: A/D Converter Characteristics;
Table 11-11: Flash Data Memory Write/Erase Time.
DS41338B-page 78
Preliminary
MCV14A
INDEX
A
A/D
POR
Specifications.............................................................. 66
ALU ....................................................................................... 7
Device Reset Timer (DRT) ................................... 35, 45

PD............................................................................... 47
Power-on Reset (POR)............................................... 35
TO............................................................................... 47
PORTB ............................................................................... 23
PORTC ............................................................................... 23
Power-down Mode.............................................................. 47
Prescaler ............................................................................ 32
Program Counter ................................................................ 17
B
Block Diagram
Comparator for the MCV14A ...................................... 55
On-Chip Reset Circuit ................................................. 43
Timer0......................................................................... 29
TMR0/WDT Prescaler................................................. 33
Watchdog Timer.......................................................... 46
Q
Q cycles .............................................................................. 10
Carry ..................................................................................... 7
Clocking Scheme ................................................................ 10
Code Protection ............................................................ 35, 48
CONFIG1 Register.............................................................. 36
Configuration Bits................................................................ 35
D
Digit Carry ............................................................................. 7
E
Errata .................................................................................... 3
F
Flash Data Memory
Code Protection .......................................................... 22
FSR ..................................................................................... 18
Fuses. See Configuration Bits
R
RC Oscillator....................................................................... 38
Read-Modify-Write.............................................................. 27
Register File Map
MCV14A ..................................................................... 12
Registers
CONFIG1 (Configuration Word Register 1)................ 36
Special Function ................................................... 12, 13
Reset .................................................................................. 35
S
Sleep ............................................................................ 35, 47
Special Features of the CPU .............................................. 35
Special Function Registers ........................................... 12, 13
Stack................................................................................... 17
STATUS Register ............................................................... 49
Status Register ............................................................... 7, 14
I/O Interfacing ..................................................................... 25

I/O Ports .............................................................................. 23
I/O Programming Considerations........................................ 27
ID Locations .................................................................. 35, 48
INDF.................................................................................... 18
Indirect Data Addressing..................................................... 18
Instruction Cycle ................................................................. 10
Instruction Flow/Pipelining .................................................. 10
Loading of PC ..................................................................... 17
Wake-up from Sleep ........................................................... 47

Watchdog Timer (WDT)................................................ 35, 45
Period ......................................................................... 45
Programming Considerations ..................................... 45
WWW, On-Line Support ....................................................... 3
M
Memory Map
MCV14A...................................................................... 11
Memory Organization.......................................................... 11
Flash Data Memory..................................................... 19
Program Memory (MCV14A) ...................................... 11
Timer0
Timer0 ........................................................................ 29
Timer0 (TMR0) Module .............................................. 29
TMR0 with External Clock .......................................... 31
Timing Diagrams and Specifications .................................. 68
Timing Parameter Symbology and Load Conditions .......... 67
TRIS Register ..................................................................... 23
Z
Zero bit ................................................................................. 7
O
Option Register ................................................................... 15
OSC selection ..................................................................... 35
OSCCAL Register ............................................................... 16
Oscillator Configurations ..................................................... 37
Oscillator Types
HS ............................................................................... 37
LP................................................................................ 37
RC............................................................................... 37
XT ............................................................................... 37
Preliminary
DS41338B-page 79
MCV14A
NOTES:
DS41338B-page 80
Preliminary
MCV14A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
MCV14A
MCV14AT(1)
Temperature
Range:
Package:
P
SL
Pattern:
Special Requirements
MCV14A-I/SN = Industrial Temp., SOIC

package
MCV14A-I/P = Industrial Temp., PDIP package
-40C to +85C (Industrial)
=
=
Plastic (PDIP)
14L Small Outline, 3.90 mm (SOIC)
Note 1:
Preliminary
= in tape and reel SOIC package only
DS41338B-page 81
WORLDWIDE SALES AND SERVICE

AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office

Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
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Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu

Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/26/09
DS41338B-page 82
Preliminary

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The MCV14A device fits in applications ranging from

The MCV14A device is available in the cost-effective

FEATURES AND MEMORY OF MCV14A

Maximum Frequency of Operation (MHz)

Flash Program Memory

Flash Data Memory

Wake-up from Sleep on Pin Change

In-Circuit Serial Programming

14-pin PDIP and SOIC

2009 Microchip Technology Inc.

Downloaded from DatasheetLib.com - datasheet search engine

Downloaded from DatasheetLib.com - datasheet search engine

2009 Microchip Technology Inc.

The high performance of the MCV14A device can be

The MCV14A device contains an 8-bit ALU and

Table 2-1 below lists memory supported by the

Depending on the instruction executed, the ALU may

A simplified block diagram is shown in Figure 2-2, with

The MCV14A device can directly or indirectly address

2009 Microchip Technology Inc.

Downloaded from DatasheetLib.com - datasheet search engine

MCV14A BLOCK DIAGRAM

RAM Addr (1)

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2009 Microchip Technology Inc.

MCV14A PINOUT DESCRIPTION

CMOS Bidirectional I/O pin. Can be software programmed for internal

ADC channel input.

CMOS ICSP mode Schmitt Trigger.

CMOS Bidirectional I/O pin. Can be software programmed for internal

ADC channel input.

CMOS ICSP mode Schmitt Trigger.

CMOS Bidirectional I/O pin.

CMOS Comparator 1 output.

ADC channel input.

Input pin. Can be software programmed for internal weak