Final Sample Questions Fall 2015

UNIVERSITY OF NEW YORK, TIRANA
Computer Organization and Systems Architecture

Sample Final Exam Questions
General Information
Allowed time will be 3 hours

Contributes 30% to the course final grade
Exam paper will be organized in two sections:
o Section A (50%) will consist of multiple choice (20%) and short essay (30%)
questions
o Section B (50%) will consist of exercises
Covered material will be from after Midterm till the last lecture.
Closed notes, closed textbook policy
Week 8 The Processor; Logic Design Conventions; Building the Datapath

Why do the memory-reference instructions in MIPS need to use the ALU? Illustrate with
an example.
The data written to the register file in the CPU can come from two different sources.
Which are they? Give an example MIPS instruction for each case.
Mention three elements of the datapath whose operation is controlled by control lines.
Which are the different scenarios in the operation of each of those components?
Which datapath elements are used by the CPU to fetch the next instruction form the
memory?
Why is a sign-extension unit needed in the datapath and how is it used?
A multiplexor is needed to select between the outputs of two different ALUs to write to
the PC register. What does the output of each of the two ALUs represent? When is each
of those outputs used?
Week 9 The Processor; Building the Control; Pipelining
Consider the SW Rt, Offset(Rs) MIPS instruction.
o What are values of the RegWrite, MemRead, MemWrite, Branch and ALUSrc
control signals generated by the control unit?
o Which resources (blocks) perform a useful function for this instruction?
Address:
Rr. Kodra e Diellit, Selit
Tirana, Albania
Telephone: +355-(0)445 12345

Web site: http://www.unyt.edu.al

Is the 4-bit control input for the ALU completely determined by the opcode field of (a)
memory-access instructions, (b) branch instructions, (c) R-type instructions? In the
case(s) when this field is not adequate, which other field is also used?
What is the role of the RegDst control signal, which datapath element does it control, and
what is its effect when asserted and when deasserted?
Is the PCSrc control signal completely determined from the opcode field of the
instruction? Why or why not?
The main control block in the CPU is fully determined by a truth table with six inputs and
nine outputs. Where do the input bits come from?
If there are five stages in a pipelined processor, what is the ideal increase in throughput?
Is there an improvement in the execution time of a single instruction? Discuss why
throughput is more significant than the execution time of single instructions.
What are structural hazards? Explain why in MIPS structural hazards are avoided by
using two separate memories for instructions and data.
What is a data hazard? Illustrate with an example from MIPS.
Does forwarding (bypassing) completely eliminate stalls in the pipeline? Explain with an
example.
Consider the following figure, comparing nonpipelined versus pipelined execution of
three instructions. Give at least two reasons why we do not get the expected five-fold
increase in throughput from the five stages, but 2400 ps versus 1400 ps.
Address:
Tirana, Albania
Telephone: +355-(0)445 12345


Week 10 The Memory Hierarchy; Caching

Which are the two types of locality (of reference)?
Explain how the memory hierarchy takes advantage of temporal and spatial locality,
illustrating each case with one Java code example.
Write a sketch of the memory hierarchy in computer systems, explaining how speed, size
and cost vary as we move between the levels.
Explain the terms hit rate, miss rate and miss penalty.
How does increasing the block size affect cache performance?
Handling writes with a write buffer (for cache-memory consistence) stalls may occur
even when the average rate at which writes are generated is less than the rate at which the
memory can accept them. How can this occur?
Consider the following list of 32-bit memory address references, given as word
addresses: {3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253}. For each of these
references, identify the binary address, the tag, and the index given a direct-mapped
cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the
cache is initially empty.
Week 11 - Cache performance, associative caches, multi-level caches, virtual memory

A particular processor has the following characteristics: clock speed of 1GHz, base CPI
of 2.0 cycles (assuming no memory stalls), main memory access 100ns and cache miss
rate is 4%. What is the average CPI of the processor?
Find the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock
cycles, a miss rate of 0.05 misses per instruction, and a cache access time (including hit
detection) of 1 clock cycle. Assume that the read and write miss penalties are the same
and ignore other write stalls.
What are the advantages and disadvantages of fully-associative caches compared to
direct-mapped caches?
Assume there are three small caches, each consisting of four one-word blocks. One cache
is fully associative, a second is two-way set-associative, and the third is direct mapped.
Find the number of misses for each cache organization given the following sequence of
block addresses: 0, 8, 0, 6, and 8. Assume a LRU (least recently used) scheme is used to
choose which block to replace.
How many comparators are needed to locate a block (a) in a direct-mapped cache, (b) in
a four-way set-associative cache, and (c) in a fully associative cache of 16 blocks?
How does the number of tag bits differ if we increase the associativity of a cache?
Address:
Tirana, Albania
Telephone: +355-(0)445 12345


Suppose we add a L2 cache between the L1 cache and the main memory. How does it
affect (if it does) the following?
o Hit rate in the L1 cache
o Miss penalty in the L1 cache
o Overall performance of the memory hierarchy
Give at least two reasons for implementing virtual memory in computer systems.
What is the role of the page table in virtual memory systems?
What is the process of translating a virtual address generated by the CPU to a physical
address?
Assume a computer system contains 1 GB of physical memory and a page size of 4 KB.
What is the number of physical pages? If 32-bit virtual addresses are used, what is the
number of virtual pages and what is the increase in memory available to programs?
What is the role of the Translation Lookaside Buffer (TLB)?
Week 12 - Storage and other I/O Topics

A particular I/O device has a Mean Time To Failure of 10 years and Mean Time to
Replacement of 5 days. Calculate its availability.
A hard disk has average seek time 9ms, 7200 revolutions per minute, disk transfer rate of
30 MBytes/sec and controller transfer rate of 500 MBits/sec. What is the average time to
read or write a 1KB sector to this hard disk?
Which are the best case and worst case scenarios for seek times in hard drives? How do
advertised seek times compare to the actual seek times?
Compare and contrast NOR flash and NAND flash storage.
What is the difference between a synchronous and asynchronous bus?
Is polling appropriate for a keyboard input device? If yes explain. If not, what is the
solution?
Which device would benefit more from DMA: an optical mouse or a Wi-Fi network
card? Explain why.
Explain what happens when a device completes its DMA operation.
Week 13 - Multicores, Multiprocessors and Clusters
Does an application have to be concurrent in order to benefit from a multiprocessor?
Explain the terms serial, parallel, sequential and concurrent.
Is a multicore microprocessor classified as a single processor, a shared memory
multiprocessor (SMP), or as a cluster?
Address:
Tirana, Albania
Telephone: +355-(0)445 12345


Which of the following cases of parallelism require extra effort from application
programmers:
o Job-level parallelism
o Instruction-level parallelism
o Parallel processing program
80% of a program running in a quad-core CPU can be parallelized. What is the maximum
speed-up? What would be the maximum speed-up if the number of cores approached
infinity?
Give at least two reasons why the maximum speedup predicted by Amdahls law could
not be achieved.
Suppose you want to perform two sums: one is a sum of 5 scalar variables, and one is a
matrix sum of a pair of two-dimensional arrays, with dimensions 50 by 50. What speedup do you get with 4, versus 10, versus 100 processors?
If there are three parallel threads, A, B and C, running the following code in a SMP
computer:
x = x + 5;
System.out.println(x);
what are their possible interleaving scenarios and what are the possible outputs, if x is
initially 0? Which should be the correct value?
Which are some of the drawbacks of clusters over SMPs?
Describe grid computing.
Week 14 - Digital Computer Logic

What is the distinction between combinational blocks and sequential blocks in logic
circuits?
Consider a logic function with three inputs, A, B, and C, and two outputs, D and E. The
function is defined as follows: D is true if exactly one input is true, and E is true if either
B is true, or both A and C are true. Show the truth table for this function.
Show the logic equations for the logic functions D and E in the previous example.
Often, in diagrams, the NAND gate is drawn as below:
Explain why.
Address:
Tirana, Albania
Telephone: +355-(0)445 12345


Which logic function is implemented by the following circuit?
Draw the block diagram and the truth table for a 2-bit input decoder.
Given that a two-input multiplexor is defined by the equation:

Implement it in a diagram, by using AND, OR and NOT (bubbles) gates.
Show the sum-of-products representation for the following truth table for D, from three
inputs A, B, and C:
A
B
C
D
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
Implement the above sum-of-products function for D with a programmable logic array in
a diagram.
Explain why do we consider a ROM as a combinational circuit?
Draw the truth table and write the sum-of-products equation for an adder hardware for the
CarryOut signal, with inputs being two bits (a and b) and a CarryIn signal.
What is edge-triggered clocking?
How can we convert the following S-R latch:
into a D latch controlled by a single data (D) bit (rather than two S-R bits) and a clock
signal that is either asserted or not?
Address:
Tirana, Albania
Telephone: +355-(0)445 12345


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UNIVERSITY OF NEW YORK, TIRANA

Computer Organization and Systems Architecture

Allowed time will be 3 hours

Week 8 The Processor; Logic Design Conventions; Building the Datapath

Telephone: +355-(0)445 12345

Telephone: +355-(0)445 12345

Week 10 The Memory Hierarchy; Caching

Week 11 - Cache performance, associative caches, multi-level caches, virtual memory

Telephone: +355-(0)445 12345

Week 12 - Storage and other I/O Topics

Telephone: +355-(0)445 12345

Week 14 - Digital Computer Logic

Telephone: +355-(0)445 12345

Which logic function is implemented by the following circuit?

Given that a two-input multiplexor is defined by the equation:

Telephone: +355-(0)445 12345

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