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    STLD Question Bank

    Uploaded by

    Satish Bojjawar
    The document contains 15 questions related to digital logic design topics including Boolean algebra, logic gates, combinational logic circuits, sequential circuits, finite state machines, and counters. It asks students to simplify Boolean expressions, implement logic functions, design combinational circuits like multiplexers and decoders, analyze sequential circuits like flip-flops and counters, and model systems as finite state machines. The questions cover fundamental concepts and require applying techniques like Karnaugh maps, state tables and diagrams to analyze and design digital logic circuits and sequential systems.

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    © All Rights Reserved
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    STLD Question Bank

    Uploaded by

    Satish Bojjawar
    1K views11 pages
    The document contains 15 questions related to digital logic design topics including Boolean algebra, logic gates, combinational logic circuits, sequential circuits, finite state machines, and counters. It asks students to simplify Boolean expressions, implement logic functions, design combinational circuits like multiplexers and decoders, analyze sequential circuits like flip-flops and counters, and model systems as finite state machines. The questions cover fundamental concepts and require applying techniques like Karnaugh maps, state tables and diagrams to analyze and design digital logic circuits and sequential systems.

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    switching theory and logic design

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    The document contains 15 questions related to digital logic design topics including Boolean algebra, logic gates, combinational logic circuits, sequential circuits, finite state machines, and counters. It asks students to simplify Boolean expressions, implement logic functions, design combinational circuits like multiplexers and decoders, analyze sequential circuits like flip-flops and counters, and model systems as finite state machines. The questions cover fundamental concepts and require applying techniques like Karnaugh maps, state tables and diagrams to analyze and design digital logic circuits and sequential systems.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    1K views11 pages

    STLD Question Bank

    Uploaded by

    Satish Bojjawar
    The document contains 15 questions related to digital logic design topics including Boolean algebra, logic gates, combinational logic circuits, sequential circuits, finite state machines, and counters. It asks students to simplify Boolean expressions, implement logic functions, design combinational circuits like multiplexers and decoders, analyze sequential circuits like flip-flops and counters, and model systems as finite state machines. The questions cover fundamental concepts and require applying techniques like Karnaugh maps, state tables and diagrams to analyze and design digital logic circuits and sequential systems.

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    © All Rights Reserved
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    of 11

    17.

    Question Bank
    UNIT- I
    1. a. Simplify the following Boolean expressions.
    i.AC + ABC + AC to three literals
    ii. (xy + z) + z + xy + wz to three literals
    iii.AB(D + CD) + B(A +ACD) to one literal iv.
    (A + C)(A + C)(A + B + CD) to four literals
    b. Obtain the complement of the following Boolean expressions.
    i.BCD + (B + C + D) + B CDE
    ii.AB + (AC) + (AB + C)
    iii.ABC + A'BC + ABC + ABC
    iv.AB + (AC) + ABC
    2. a. Draw the NAND logic diagram that implements the complement of the function.
    F(A,B,C,D) = (0,1,2,3,4,8,9,12)
    b.Obtain the complement of the following Boolean expressions.
    i.AB + A(B + C) + B(B + D)
    ii.A + B + ABC [4]
    c.Obtain the dual of the following Boolean expressions
    i.AB + ABC + ABCD + ABCDE
    ii.ABEF + ABEF + ABEF
    3. a.Express the following functions in sum of Minterms and product of Maxterms.
    i.F (A,B,C,D) = BD + AD + BD
    ii.F(x,y,z) = (xy + z)(xz + y)

    b. Obtain the complement of the following Boolean expressions. [8]


    i.(AB + AC)(BC + BC)(ABC)

    ii.ABC + ABC + ABC


    iii.(ABC)(A + B + C)
    iv.A + BC (A + B + C)
    4. Simplify the following Boolean expressions to Minimum no. of literals.
    a.ABC+AB+ABC b.
    (BC+AD)(AB+CD)
    c.xyz+xz
    d.xy+x(wz+wz)
    5. Obtain the Dual of the following Boolean expressions.
    a.AB+A(B+C)+B(B+D)
    b.A+B+ABC
    c.AB+ABC+ABCD+ABCDE
    d.ABEF+ABEF+ABEF
    6. Express the following functions in sum of minterms and product of maxterms.
    a.(xy+z) (y+xz)
    b.BD+AD+BD
    7.Obtain the complement of the following Boolean expressions
    a.ABC+ABD+AB
    b.ABC+ABC?+ABCD
    c.ABCD+ABCD+ABCD
    .d. AB+ABC
    8. Simplify the following Boolean expressions
    a.AC+ABC+AC to three literals b.
    (xy+z)+z+xy+wz to three literals
    c.AB(D+CD)+B(A+ACD) to one literal
    d.(A+C)(A+C)(A+B+CD) to four literals

    9. Obtain the complement of the following Boolean expressions


    a.BCD+(B+C+D)+BCDE
    b.AB+(AC)+(AB+C)
    c.ABC+ABC+ABC+ABC
    d.AB+(AC)+ABC

    10. For the given Boolean function F=xyz+xyz+wxy+wxy+wxy


    a. Draw the logic diagram
    b. Simplify the function to minimal literals using Boolean algebra.
    11. Obtain the Dual of the following Boolean expressions
    a. ABC+ABD+AB
    b.ABC+ABC+ABCD
    12. State and prove the following Boolean laws:
    a.Commutative
    b.Associative
    c.Distributive
    13. Find the complement of the following Boolean functions and reduce them to
    Minimum number of literals: a.
    (bc+ ad) (ab + cd)
    b.bd + abc + acd + abc
    c.Which gate can be used as parity checker? Why?
    14. a.Simplify the following Boolean functions to minimum number of literals:
    i.( a + b ) ( a + b )
    ii.y(wz + wz) + xy
    b.Prove that AND-OR network is equivalent to NAND-NAND network.
    c.State Duality theorem. List Boolean laws and their Duals.

    15.a.State Duality theorem. List Boolean laws and their Duals.


    b.Simplify the following Boolean functions to minimum number of literals:
    i.F = ABC + ABC + AB
    ii.F = (A+B) (A+B)
    c.Realize XOR gate using minimum number of NAND gates
    17. a.State and prove Boolean laws related to OR, AND, NOT gates
    b.Given Boolean expression AB+AB = C. Show that AC+AC = B.
    c.Prove that OR-AND network is equivalent to NOR-NOR network.
    UNIT - II
    18. Implement the following functions using appropriate DECODER
    a.F1 = m(2,4,6,8,12)
    b.F2 =m(1,3,6,7,9,10)
    c.F3 = m(1,3,4,5,6,9,12,14)
    d.F4 =m(2,4,8)
    19. Prove the following identities by writing the truth tables for both sides:
    a.X.(Y + Z) = (X.Y) +(X .Z)
    b.(X.Y.Z) = X + Y +Z
    c.X.(X +Y) = X
    d.X + XY = X + Y
    20. Define the following terms
    a.Boolean function
    b.Sum of products form
    c.Product of sum form
    d.Dont care conditions
    1. (a) Write short note on prime implicant chart.

    (b) Minimize following function using Tabular minimization.


    F (A, B, C, D) = m(6, 7, 8, 9) + d(10, 11, 12, 13, 14, 15).
    2.(a) Design a logic circuit Using minimum number of Basic gates for the following Boolean
    expression.

    (b) Reduce the following expression using Karnaugh map. (B A + AB + AB )


    (c) Find the out put of a four variable K-map, when all the cells are filled with logic LOW.
    3.(a) Simplify the Boolean function using K-map
    F= Pm(0, 1, 2, 4, 7, 8, 12, 14, 15, 16, 17, 18, 20, 24, 28, 30, 31) [10]
    (b) Simplify the Boolean expression using K-map

    4.(a) Reduce the following function using K- map and implement it in AOI logic as
    well as NOR logic F= M(0, 1, 2, 3, 4, 7)
    (b) What do you mean by K-map? Name its advantages and disadvantages
    5.(a) Reduce the following function using K- map and implement it in AOI logic as
    well as NOR logic F= M(0, 1, 2, 3, 4, 7)
    (b) What do you mean by K-map? Name its advantages and disadvantages
    6.For the truth table given below , find the minimal expression for the out put (Y) using K-map
    A
    0
    0
    0
    0
    0
    0

    B
    0
    0
    0
    0
    1
    1

    C
    0
    0
    1
    1
    0
    0

    D
    0
    1
    0
    1
    0
    1

    Y
    1
    0
    1
    0
    1
    1

    A
    0
    0
    1
    1
    1

    B
    1
    1
    0
    0
    0

    C
    1
    1
    0
    0
    1

    D
    0
    1
    0
    1
    0

    Y
    1
    0
    0
    1
    0

    A
    1
    1
    1
    1
    1

    B
    0
    1
    1
    1
    1

    C
    1
    0
    0
    1
    1

    D
    1
    0
    1
    0
    1

    Y
    0
    1
    0
    1
    0

    b) Expand A+BC+ABD+ ABCD to Minterms and Max terms.


    7.(a) What is a cell of a K-map? What is meant by pair, a quad, and an octet of a map and how many
    variables are eliminated?
    (b) Reduce the following function using K- map and implement it using NAND
    Logic. F= m(0, 2, 3, 4, 5, 6, )

    8.(a) What do you mean by dont care combinations?


    (b) What you mean by min terms and max terms of Boolean expressions.
    (c) Simplify the Boolean function using K-map
    F= m(0, 1, 3, 4, 5, 6, 7, 8, 9) + d(10, 11, 12, 13, 14, 15)
    9.(a) What are the advantages of Tabulation method over K-map?
    (b) Simplify the following Boolean function using Tabulation method.
    Y(A,B,C,D) = (2,3,5,7,8,10,12,13)
    10.Simplify the following Boolean expressions using K-map and implement them using NOR gates:
    (a) F(ABCD) = ABC+AC+ACD
    (b) F(WXYZ) = WXYZ + WXYZ+WXYZ+WXYZ

    1. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five NAND gates
    and the EXCLUSIVE ?OR circuit made by four NAND gates as shown in figure have any static
    Hazard or Dynamic Hazard?
    2.

    2. A circuit receives a 4-bit Excess-3 code. Design a minimal circuit to detect the decimal numbers 0,
    1, 4, 6, 7 and 8.
    3. (a) Implement the following Boolean function using a 8:1 multiplexer considering C as the input
    and A,B,C as selection lines. F(ABCD) = AB +BD+ BCD
    (b) Draw the Gate level diagram of a Decimal to BCD encoder.
    4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates.
    (b) Draw the logic diagram of a single bit comparator
    5. (a) Design a combinational logic to subtract one bit from the other. Draw the logic diagram using
    NAND and NOR gates.
    (b) Explain the working of a serial adder

    6.(a) Implement the following multiple output combinational logic using a 4 line to
    16 line Decoder
    Y1= ABCD + ABCD+ ABCD+ABCD+ABCD+ABCD
    Y2=ABCD+ABCD+ABCD+ABCD
    Y3=ABCD+ABCD+ABCD
    (b) Explain the terms Multiplexing and De multiplexing.
    7. A combinational circuit is defined by the following three functions
    F1 = xy+xyz F2=x+y F3 = xy+xy
    Design the circuit with a decoder and external gates.
    8. (a) Design 4-bit odd parity generator. Mention truth table.
    (b) Using 4 MSI circuits construct a binary parallel adder to add two 16-bit binary numbers. Label all
    carries between the MSI circuits.
    9. (a) Implement the following Boolean functions using decoder and OR gates:
    F1(A,B,C,D) = (2,4,7,9)
    F2(A,B,C,D) = (10,13,14,15)
    10.(a) What is decoder? Construct 3*8 decoder using logic gates and truth table.
    (b) What is Encoder? Design Octal to Binary Encoder.

    UNIT- III
    1. Classify the required circuits into synchronous, asynchronous, pulse mode with suitable
    examples.
    2. Draw the circuit of JK master slave flip-flop with active high clear & active low preset &
    explain.
    3. Draw the circuit of master slave RS flip-flop & explain its operation with the help of truth table.
    4. Discuss the disadvantages due to level triggering.
    5. Convert T flip-flop to D flip-flop.
    6. What is the advantage of choosing D flip flop in sequential circuits. Explain with an example.
    UNIT- IV
    7. Compare synchronous & asynchronous circuits
    8. Using a shift register how do you obtain a circular shift.
    9. Design & implement 2 bit comparator using logic gates.
    10. Draw the block diagram of a 4-bit serial adder & explain its operation.
    11. Design of MOD- N Synchrounous Counter.
    12. Design ripple and Johnson ring counter.
    UNIT- V
    1. Draw the diagram of melay type FSM for serial adder..

    2.
    3.
    4.
    5.

    Draw the circuit for moore type ASM


    Distinguish between melay&moore machines
    Explain merger chart methods of minimal convertible.
    A clocked sequential circuit is provided with a single input x & single output z. Whenever the
    input produces a string of pulses 111 or 000 & at the end pof the sequence it produces an
    output z=1 & overlapping is allowed. Obtain state diagram.
    6. Explain the following related to sequential circuits with suitable examples. State diagram.
    7. Design a sequence detector that detects the overlapping sequence of 011010 using T flip
    flops.
    8. Obtain the state table & state diagram for a sequence detector to recognize the occurrence of
    sequence bits 110 & 001.
    9. Design a synchronous sequential circuit that has one input x & one output z. The circuit adds
    the bits that are coming on the input x & produces the sum bit on the output z. Design such a
    serial adder circuit using T flip flops.
    10. Obtain state table & state diagram for a sequence detector to recognize the occurrence of
    sequence bits 110 & 001. Design the logic circuit using JK flip flops.
    11. Explain in detail block diagram of ASM chart.
    12. Show that 8 exit paths in an ASM block emanating from the decision boxes that check the 8
    possible binary values of three control variables x, y,z.
    13. Explain in detail melay state diagram & ASM chart with an example.
    14. Draw the state diagram of sequence detector which is designed to detect the pattern 1001 &
    allowing the overlapping in the input sequences.
    15. Design a sequential logic circuit of a 4 bit counter to start counting from 0000 to 1000 & this
    process should go on. Draw the ASM chart & design the data processing unit.
    16. Design the ASM chart, data path circuit, control circuit using multiplexers for binary
    multiplier.
    17. Design a synchronous sequential circuit which goes through the following
    states1,3,5,3,6,1,3,5.
    18. Design control circuit for ASM chart using D flip flop & decoder.
    19. Draw the portion of an ASM chart that specifies the conditional operation to increment the
    register R during the state T1 & transfer to the state T2, if control inputs z & y are 1 & 0
    respectively.
    20. Design a synchronous sequential circuit that works as a decade counter.

    18. Assignment topics


    UNIT-I
    1) (a) Convert the following (258)10 = ( ? ) 2 = ( ? ) 8 = ( ? ) 16
    (b) Generate the hamming code for the data 1011.
    2) (a) State and prove the duality theorem.
    (b)Reduce the following Boolean expression using theorems.
    F = ABC+ABC+ABC+ABC+ABC
    3) (a) 11011 + 101101
    (b) 101011 110011 using 2s complement
    4) What are Universal Gates? Realize all the logic gates using NAND.
    5) A receiver with even parity Hamming code is received the data as 101110110100.
    Determine the correct code and what is the original message.
    6) (a) Convert the following into canonical form F = AB+C
    (b)Reduce the following Boolean expression using theorems.
    F = [A+ (BC)]+ (AB+ABC)
    7) (a) Convert the following (527)10 = ( ? ) Gray = ( ? ) BCD = ( ? ) XS-3
    (b)Generate the hamming code for the data 1101.
    8) What are universal gates? Realize all logic gates using NOR Gates.

    UNIT-II
    1). Simplify the following expressions using K-Map and realize with NAND gates. F =
    M (1, 2, 3, 8, 9, 10, 11, 14). d (7,15)
    2). Design the logic circuit that coverts 4 bit binary data to gray code.
    3) Simplify the following expressions using K-Map and realize with NAND gates.
    F = m (0,2,5,9,15) + d(6,7,8,10,12,13)
    4) Implement the following using 8X1 MUX. F = (0, 1, 3, 4, 6, 8, 15)
    5) Simplify the following expressions using K-Map and realize with NOR gates. F =
    ABC + ABC + ABC +ABC + ABC.

    6) Design and explain 3 to 8 decoder.


    7) Minimize the following function using tabular method and find the essentials.
    8) Realize 16X1 MUX using two 4X 1 MUX.
    UNIT-III
    1. What is the drawback of JK Flip Flop. How is it eliminated in Master Slave J-K Flip-Flop. Explain
    with state diagram and characteristic table.
    2. Write the differences between synchronous and asynchronous counters.
    3. Convert JK Flip Flop to D Flip Flop and T Flip Flop.
    4. Differentiate between latch and flip-flop.
    5. Define: characteristics table, excitation table, race around condition.
    6. Compare combinational and sequential circuit from all aspects.

    UNIT-IV
    1.
    2.
    3.
    4.

    Design a modulo - 10 ripple counter and explain its timing diagram.

    Design a Mod-6 asynchronous counter using J-K Flip Flops.


    Differentiate between Combinational and Sequential Circuits with examples.
    Design a Decade counter using SR Flip Flops.

    Unit V
    1. Differentiate between Mealy and Moore machine with examples.

    2. Find the equivalence partition and reduced table for the given state machine.
    P.S
    N.S. , O/P
    X=0
    X=1
    A
    B,0
    E,0
    B
    E,0
    D,0
    C
    D,1
    A,0
    D
    B,1
    E,0
    E
    C,0
    D,0
    3. Find the minimal cover table for the given machine using Merger graph.
    P.S
    N.S,Z
    00
    01
    11
    10
    A
    A,0
    --,-E,-B,1
    B
    E, -C,1
    B,---,-C
    --,-B,0
    --,1
    D,0
    D
    A,0
    --,-F,1
    B,-E
    B,0
    --,-B,0
    --,--

    --,--

    C,1

    --,0

    C,1

    4. Convert the following Mealy machine into a corresponding Moore machine.


    state table is given. prepare examples

    5. What are the capabilities and limitations of FSMs?


    6. Construct the compatibility graph and obtain the minimal cover table for given machine.

    PS
    A
    B
    C
    D
    E
    F

    NS,Z
    X1
    --,-B,0
    E,0
    B,0
    F,1
    A,0

    X2
    F,0
    C,0
    A,1
    D,0
    D,0
    --,--

    7. Obtain set of maximal compatibles for machine shown using Merger table.
    PS
    NS,Z
    X1
    X2
    A
    E,0
    B,0
    B
    F,0
    A,0
    C
    E,C,0
    D
    F,1
    D,0
    E
    C,1
    C,0
    F
    D,B,0
    8. Draw and explain an ASM chart of a binary multiplier.
    9. Draw an ASM chart and state table for 2 bit UP/DOWN Counter having control input M, if M = 1;
    UP Counting & M = 0; DOWN Counting. The circuit has to generate output 1 whenever the count
    becomes minimum or maximum.
    10. What are the salient features of an ASM chart.
    11. What are the notations used in the ASM Chart.

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