Common expectations from customers are:

1. Introduction.
2. Projects/Work/PnR tool experience.
3. Challenges/Problems
4. Solutions/possible fixes of point 3.

Interview questions by our customers :

INTERVIEW QUESTIONS FROM ALTERA

1. Briefly introduce about you and your work related challenges you faced.
2. Which EDA you used Cadence or ICC, have you used CCOPT?
3. Explain basic block level flow.
4. How did you decide, whether placement quality is good?
-> Based on the setup timing and congestion.
5. What challenges you faced in CTS?

6. What is the benefits of Multipoint CTS?

7. What is the drawback of Multipoint CTS?

8. When and how in pnr flow, you do hold fixing?

-> Generally hold fixing we do after CTS is built up. Hold fixing is done by upsizing the
combination cells and addition of buffer.

My Question : Why we are not doing hold fixing during placemnent.

9. What are advantages/disadvantages of fixing hold before and after CTS?

10. Why do you use endcap cells?

11. What is hard blockage?
-> Hard blockage is used for instructing the tool to not place any kind of cells within the hard
blockage region defined . Generally it is used around macros for making routing resources
available for pins of memories.
12. How do you fix congestion?
13. What will be the reason of having timing bad around ~250ps, and has no congestion?
-> High logic depth.
-> lot of detoring due to bad memory placement.
14. How will you reduce delay in such case?
15. How do you fix hold violations?
16. What is cross-talk issue?
17. What are Aggressor and Victim, What type of issue will exists if both propogate in
same direction, How will you fix Hold?
18. What is Antenna Violation, What techniques you implement to solve it?
19. What not lower metal layer for fixing Antenna? Where will you add diode?
20. What is GBA and PBA mode of timing analysis?
21. Why not using PBA in complete PnR flow?
22. What are OCV, AOCV, SOCV, POCV?
 23. What got changed from 28nm to 16nm? What new DRC you faced?
24. Why do we use Endcap cells? Explain it's significance.
25. What is a hard blockage?
26. How do you fix congestion?
27. If timing looks bad, say 250ps, There is no congestion problem.
How do you fix it at placement stage ?
28. How can you fix hold violations?
29. What is cross talk? Define Agressor and Victim.
30. What is Antenna Violation?
31. How can you fix Antenna violations? In layer hopping can you
use lower metal layers?
32. Where would you add diode to fix antenna violations?

1. What is the size of your block

2. Not the gate count, its X, Y dimension
3. What is the biggest block & run time
4. Setup violation how will you fix it
5. Hold violation fix
6. Full cycle path & half cycle path, which is easy to fix hold violation . Is
there any advantage in fixing hold violations with half cycle path.
7. How comfortable working with ICCII gui ?
8. Difference between soft & hard placement blockage?
9. What is Float pins?
10. If I want to early the clock in macro, using CTS how can we do it ?
11. Signal integrity effects, did u fix any ECO, cross talk ?
12. How did you generate ECOs
13. How many scenarios u will define in DMSA ECO stage ? few selected or all ?
14. Setup scenario is failing, hold is passing, 14 scenarios (8 setup & 8 hold) are
passing (both setup & hold), 2 scenarios are failing with setup. So how many
scenarios u will set for PT DMSA ECO run? Will u setup just the failing 2
scenarios or the worst-case scenarios?
15. If you give only the setup scenarios (2), what happened to hold
scenarios? Atleast one setup and hold scenario should be defined. So
that it will try to check setup & hold and fix them accordingly
16. Experience in ICC DRC fixes. Did you run any PV tool for sign-off
17. What are the inputs to ICV? Routed GDS/Oasis

18. Current project

19. Challenges faced during project on 16nm node
20. Timing issue in block
21. Models used for hierarchical block
22. What is abstract model? How do prepare it?
23. Do we need clock db for pt?
24. How did you modelled clock latency for sub blocks?
25. Explain set up and hold fixing ways.
26. Is it possible to have same endpoint failing setup and hold? If it is how to fix
that ?
27. On what parameters does cell delay depends?
28. If we delay capture clk latency to meet setup violation, what will be the
effect on immediate connected flops.
29. What are the inputs to cts?
30. What is physical topographical synthesis?
31. How you do post route setup fixing?
32. What happens if we change VT type to LVT?
33. What are float pins?
34. From one Macro to its connected Registers, lot of setup fails observed, how
to fix these fails? How do you fix it using Tool, which command?
35. What are clock spec file contains? Value of Skew value
36. Uncertainty value at placement and at pt .Are they same or different? If yes
then why?
37. What is crosstalk, effects of crosstalk
38. By crosstalk noise we get setup/hold violation?
39. What is useful skew? How to use it ?
40. What kind of constraint you specify to tool to use useful skew.

1. Current project and challenges

2. How do you switch between two tools (eg. ICC and encounter) and what are the inputs?
3. Def Contents
4. Difference between hvt, lvt and ulvt .How does it affects the power.
5. How you do eco and in which tool?
6. What things solved in pt?
7. If I want to early my clock for one of the macros how I can do it? (we use float pins)
8. How someone decides to delay/early clock for macro(regarding macro pins if required).
9. What celtic library contains?
10. If congestion occurs, how you solve. (Using GUI also)
11. How you will solve setup violation if nothing more we can do in data path.
12. Ways to fix setup and hold violations

Questions asked by synopsys :

Experience in ICC
o Role + responsibility
o On which flow have worked?
o Congestion reason and solutions ; how you provide partial blockage?
o Suppose we are having 200 x 200 um area, we provide partial blockage of
30% blk and 70% plc allowed, all the cells seat in the middle of blockage ?
What can be done ? (As the area is larger provide smaller partial
blk so spreading will be uniform)
o What is keepout margin, cell padding and float pins?
o Input to cts (skew, transition etc)
o Have you done cts building ? how?
o What is skew?
o If we are having hold violations in design, by decreasing the freq can we do
tapeout of the chip ? why?
o On what parameters cell delay depends?
o Dc topo synthesis
o Ways to fix Setup violations
o What you will check after inserting buffer to capture flop ? (setup,hold
margin ).What will be checked on what flops?
o Define hold time.Scenario given and asked foe effect on hold time.
o Inputs to cts
o Why we use special buffer for cts?
o What is duty cycle distortion ?
o Float pins, why used?
o What is structured clock and its Advantages and disadvantages.
o Why we have multiple clocks ports in structured clock.
o What is crosstalk noise and how it impact timing (setup/hold) ?
o IR drop violations : reason and how we fix it ?
o If there is IR drop issue can we tapeout the chip by decreasing the freq?
o What is crosstalk delay?
o Explain CRPR, why we add derates /OCV to design.
o For how many scenarios you solved the timing?
o CTS challenges in any projects
What is macro modelling ?
6. Float pins ? Can float pins be used for std cells also?
7. What is crosstalk noise and how it impact timing (setup/hold) ?
8. Chip level experience
2. How do you switch between two tools (eg. ICC and encounter) and what
are the inputs?
3. Def Contents
4. Difference between hvt,lvt and ulvt .How does it affects the power.
5. How you do eco and in which tool?
6. What things solved in pt?
7. If I want to early my clock for one of the macros how I can do it? ( we use
float pins)
8. How someone decides to delay/early clock for macro(regarding macro pins
if required).
9. What celtic library contains?
10. If congestion occurs, how you solve .(using GUI also)
11. How you will solve setup violation if nothing more we can do in data
path.
12. Ways to fix setup and hold violations

What is the size of your block

Not the gate count, its X, Y dimention
What is the biggest block & run time
Setup violation how will you fix it
 Hold violation fix
Fullcycle path & half cycle path, which is easy to fix hold violation . is there any advantage
in fixing hold violations with half_cycle path.
How comfortable working with ICCII gui ?
Difference between soft & hard placement blockage ?
What is Float pins ?
If I want to early the clock in macro, using CTS how can we do it ?
Signal integrity effects, did u fix any ECO, cross talk ?
How did you generate ECOs
How many scenarios u will define in DMSA ECO stage ? few selected or all ?
Setup scenario is failing, hold is passing, 14 scenarios (8 setup & 8 hold) are passing (both
setup & hold), 2 scenarios are failing with setup. So how many scenarios u will set for PT
DMSA ECO run ? Will u setup just the failing 2 scenarios or the worstcase scenarios.
If you give only the setup scenarios (2), what happened to hold scenarios. Atleast one
setup and hold scenario should be defined. So that it will try to check setup & hold and
fix them accordingly
Experience in ICC DRC fixes. Did you run any PV tool for sign-off
What are the inputs to ICV ? Routed GDS/Oasis

1) Most recent experience you had in place and route side can you let me know which tools or
which part of the flow you have taken in that project
2) Let me break my questions in of these stage in placement, routing, CTS
3) What all does tool do if we are giving place_opt?
4) Have you had any experience in any technology node, 20nm and below?
5) From which foundry is it TSMC or SAMSUNG?
6) For this lower node we had some specific rule so that technology style to accommodate this
for placement step. Do you know happened to know what they might?
Means technology rules with respect to placement? (standard cell aspect rules)
7) Have you seen any rule like minimum VTH rule, like minimum width VTH had with. Example
like: cell which takes only 2 placement stage and I place it all by itself is it legal placement?
8) Now CTS, we uses clock_opt for CTS, can you describe the same means what does ICC do
when we are giving clock_opt?
9) Do you know which commend we use for defining the skew target?
10) How about once we finish CTS, after that clock_opt means what kind of optimization happen?
11) Now route_opt, what steps happen in route_opt?
12) route_opt -initial_route what ICC does it?
13) After detail routing I see degradation, like skew and transition violations in clock tree. Is there
a way out after detail routing to fix?
14) How about some advance rules in routing for lower technology? And compare with 28nm 45nm
15) Is there any rule which comes in 16nm and 14nm but it wasn't appearing in 20nm or 28nm.
rules means spicing or end-of-line
16) How about double-pattern?
17) Did you do routing also in TSMC16nm or 14nm?
18) For lower layers, how do you accommodate one net in 2 masks?
19) How are you with scripting?
20) How much you know TCL(detail in TCL)
21) How complicated place and route flows you have worked on?
22) For how much % you have to come up with flows? OR for how much % you to start with
scratch with flow?
23) Do you create a flow or is it ready to go?
24) How fast you can pick up any new tool?
25) How difficult to switch from ASTRO to ICC?
26) How much experience do you have with ICV?
27) Do you have experience with in Synopsys ICV or stand alone ICV?
28) How you rate your experience in ICC?
29) What is the most challenging issue you faced in ICC during any of those acoustic periods?
30) Lets say you are done with placement, you are very near to close timing at placement with idle
clock, and now you go to the CTS and then you do CTS optimization, and you see lots of clock
enable timing violations, so now how will debug this issue or what you can do at placement
stage that you can overcome this timing issue?
31) You done with CTS and post CTS optimization but timing is not closed and lots of hold
violations is there? So what you will do at CTS stage to improve hold timing.
32) Have you worked on any Low Power projects?
33) In case of Multi domain design using UPF, check_mv_design is clean before placement and
after placement it throws lots of errors and warnings saying Always ON net is driven by normal
cell. How you will debug these issues?
34) Lets say, you are done with routing and design is clean for timing and DRC. Then you take it to
PT and you see there are lots of max_trans violations (in the range of 40ps 50ps), so how you
will fix this violations?
35) I have completed Place & Route and tool is complaining about 100 transition violations so
how will you fix these violations? I dont want to do it manually, is there any other technique to
do fix this?
36) Have you tried to solve above issue with the tool (not by inserting buffer)?
37) I close timing in ICC through routing stage and now I would like to optimize it for leakage in
ICC. What should you do for leakage_opt?
38) I want to improve the dynamic power in ICC what all the things we can do in placement stage?
39) How to improve dynamic power at routing stage?