S2 LP
S2 LP
S2 LP
Contents
1 Description....................................................................................... 8
2 Detailed functional description ...................................................... 9
3 Typical application diagram and pin description ........................ 11
3.1 Pin diagram ..................................................................................... 13
3.2 Pin description................................................................................. 13
4 Specifications ................................................................................ 15
4.1 Absolute maximum ratings .............................................................. 15
4.2 Operating range .............................................................................. 15
4.3 Thermal properties .......................................................................... 15
4.4 Power consumption ......................................................................... 16
4.5 General characterization ................................................................. 17
4.6 Frequency synthesizer .................................................................... 18
4.7 Crystal oscillator .............................................................................. 18
4.8 RF receiver...................................................................................... 19
4.8.1 Blocking and selectivity at 433 MHz ................................................. 20
4.8.2 Sensitivity at 433 MHz ...................................................................... 21
4.8.3 Blocking and selectivity at 868 MHz ................................................. 21
4.8.4 Sensitivity at 868 MHz ...................................................................... 22
4.8.5 Blocking and selectivity at 920 MHz ................................................. 22
4.8.6 Sensitivity at 920 MHz ...................................................................... 23
4.9 RF transmitter ................................................................................. 23
4.9.1 Harmonic emission at 433 MHz ....................................................... 24
4.9.2 Harmonic emission at 868 MHz ....................................................... 24
4.9.3 Harmonic emission at 915 MHz ....................................................... 25
4.10 Digital interface specification ........................................................... 25
4.11 Battery indicator .............................................................................. 26
5 Block description .......................................................................... 27
5.1 Power management ........................................................................ 27
5.2 Power On Reset .............................................................................. 28
5.3 RF synthesizer ................................................................................ 29
5.3.1 RF channel frequency settings ......................................................... 30
5.4 Digital modulator ............................................................................. 31
5.4.1 Frequency modulation ...................................................................... 31
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Description of the external components of the typical application diagrams .............................. 12
Table 3: Pinout .......................................................................................................................................... 13
Table 4: Absolute maximum ratings ......................................................................................................... 15
Table 5: Operating range .......................................................................................................................... 15
Table 6: Thermal data ............................................................................................................................... 15
Table 7: Low-power states power consumption ....................................................................................... 16
Table 8: Power consumption in reception TA = 25C, VDD = 3.0 V, fc = 868 MHz ................................. 16
Table 9: Power consumption in transmission fc= 920 MHz ...................................................................... 16
Table 10: Power consumption in transmission fc= 868 MHz .................................................................... 17
Table 11: Power consumption in transmission fc= 434 MHz .................................................................... 17
Table 12: General characteristics ............................................................................................................. 17
Table 13: Data rate with different coding options ..................................................................................... 17
Table 14: Frequency synthesizer parameters .......................................................................................... 18
Table 15: Crystal oscillator characteristics ............................................................................................... 19
Table 16: Ultra-low power RC oscillator ................................................................................................... 19
Table 17: RF receiver characteristics ....................................................................................................... 20
Table 18: Blocking and selectivity at 433 MHz ......................................................................................... 20
Table 19: Sensitivity at 433 MHz .............................................................................................................. 21
Table 20: Blocking and selectivity at 868 MHz ......................................................................................... 21
Table 21: Sensitivity at 868 MHz .............................................................................................................. 22
Table 22: Blocking and selectivity at 920 MHz ......................................................................................... 22
Table 23: Sensitivity at 920 MHz .............................................................................................................. 23
Table 24: RF transmitter characteristics ................................................................................................... 23
Table 25: PA impedance .......................................................................................................................... 23
Table 26: Regulatory standards ................................................................................................................ 24
Table 27: Harmonic emission at 433 MHz ................................................................................................ 24
Table 28: Harmonic emission at 868 MHz ................................................................................................ 24
Table 29: Harmonic emission at 915 MHz ................................................................................................ 25
Table 30: Digital SPI input, output and GPIO specification ...................................................................... 25
Table 31: Battery indicator and low battery detector ................................................................................ 26
Table 32: SMPS output voltage ................................................................................................................ 27
Table 33: POR parameters ....................................................................................................................... 28
Table 34: Charge pump words ................................................................................................................. 29
Table 35: Resolution frequency ................................................................................................................ 30
Table 36: Channel spacing resolution ...................................................................................................... 31
Table 37: Modulation scheme................................................................................................................... 31
Table 38: Constellation mapping 2-(G)FSK .............................................................................................. 32
Table 39: Constellation mapping 4-(G)FSK .............................................................................................. 32
Table 40: PA Bessel filter words ............................................................................................................... 34
Table 41: Channel filter words .................................................................................................................. 39
Table 42: RX timer stop condition configuration ....................................................................................... 40
Table 43: CS mode description ................................................................................................................ 41
Table 44: RCO Frequency ........................................................................................................................ 46
Table 45: States ........................................................................................................................................ 49
Table 46: Commands................................................................................................................................ 49
Table 47: Response time .......................................................................................................................... 50
Table 48: BASIC packet format ................................................................................................................ 51
Table 49: Preamble field selection............................................................................................................ 51
Table 50: STack packet ............................................................................................................................ 53
Table 51: 802.15.4g packet ...................................................................................................................... 54
Table 52: PHR frame ................................................................................................................................ 55
Table 53: UART over the air packet format .............................................................................................. 55
List of figures
Figure 1: Simplified S2-LP block diagram................................................................................................. 10
Figure 2: Suggested application diagram (embedded SMPS used) ........................................................ 11
Figure 3: Suggested application diagram (embedded SMPS not used) .................................................. 12
Figure 4: Pin diagram, 4 mm x 4 mm QFN24 package ............................................................................ 13
Figure 5: Power on reset timing and limits................................................................................................ 28
Figure 6: Direct polar mode ...................................................................................................................... 35
Figure 7: Output power ramping configuration ......................................................................................... 44
Figure 8: Threshold in FIFO ...................................................................................................................... 45
Figure 9: State diagram ............................................................................................................................ 48
Figure 10: data whitening scheme ............................................................................................................ 59
Figure 11: data whitening scheme 802.15.4g ........................................................................................... 60
Figure 12: Automatic retransmission scenario ......................................................................................... 63
Figure 13: Common RX operation ............................................................................................................ 64
Figure 14: LDC RX operation ................................................................................................................... 64
Figure 15: LDC in TX with auto-ack .......................................................................................................... 66
Figure 16: LDC in RX with auto-ack ......................................................................................................... 66
Figure 17: Fast RX termination mode with LDC ....................................................................................... 67
Figure 18: Fast Rx termination: CS detection ........................................................................................... 67
Figure 19: Flowchart of the S2-LP CSMA procedure ............................................................................... 68
Figure 20: CSMA if channel is free (timeline) ........................................................................................... 69
Figure 21: CSMA with persistent mode if channel is busy (timeline) ....................................................... 70
Figure 22: CSMA with non-persistent mode if channel is busy (timeline) ................................................ 70
Figure 23: CSMA with non-persistent mode if channel becomes free (timeline)...................................... 70
Figure 24: SPI write sequence .................................................................................................................. 71
Figure 25: SPI read sequence .................................................................................................................. 72
Figure 26: SPI command sequence ......................................................................................................... 72
Figure 27: QFN24L (4x4 mm) package outline ........................................................................................ 87
1 Description
The S2-LP is a high performance ultra-low power RF transceiver, intended for RF wireless
applications in the sub-1 GHz band. It is designed to operate in both the license-free ISM
and SRD frequency bands at 433, 868 and 920 MHz, but can also be programmed to
operate at other additional frequencies in the 430-470 MHz, 860-940 MHz bands.
The S2-LP supports different modulation schemes: 2(G)FSK, 4(G)FSK, OOK and ASK.
The air data rate is programmable from 0.3 to 500 kbps.
The S2-LP can be used in systems with channel spacing of 12.5/25 kHz enabling the
narrow band operations.
The S2-LP shows an RF link budget higher than 140 dB for long communication ranges
and meets the regulatory requirements applicable in territories worldwide, including
Europe, Japan, China and the USA.
The receiver architecture is low-IF conversion, the received RF signal is amplified by a two-
stage low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the
intermediate frequency (IF). LNA and IF amplifiers make up the RX front-end (RXFE) and
have programmable gain. At IF, the ADCs digitalize the I/Q signals. The demodulated data
go to an external MCU either through the 128-byte RX FIFO, readable via SPI, or directly
using a programmable GPIO pin.
The transmitter part of the S2-LP is based on direct synthesis of the RF frequency. The
power amplifier (PA) input is the LO generated by the RF synthesizer, while the output level
can be configured between -30 dBm and +14 dBm (+16 dBm in boost mode), at pin level
with 0.5 dB steps.
The data to be transmitted can be provided by an external MCU either through the 128-
byte TX FIFO writable via SPI, or directly using a programmable GPIO pin. The S2-LP
supports frequency hopping, TX/RX and antenna diversity switch control, extending the link
range and improving performance.
The S2-LP has a very efficient power management (PM) system. An integrated switched
mode power supply (SMPS) regulator allows operation from a battery voltage ranging from
+1.8 V to +3.6 V, and with power conversion efficiency of 90%.
A crystal must be connected between XIN and XOUT. It is digitally configurable to operate
with different crystals. As an alternative, an external clock signal can be used to feed XIN
for proper operation. The S2-LP also has an integrated low-power RC oscillator, generating
the 34.7 kHz signal used as a clock for the slowest timeouts.
A standard 4-pin SPI bus is used to communicate with the external MCU. Four configurable
general purpose I/Os are available.
DIGITAL INTERFACE
C0
VR DIG
GPIO 3
GPIO 2
GPIO 1
GPIO 0
CSn
24 23 22 21 20 19
VSMPS2
VDD SMPS SCLK
VBATT 1 18
C1
SMPS1 SDI
2 S2-LPQTR 17
SMPS2 SDO
3 16
XOUT VDD DIG/RX
VBATT C17
4 15
C2
XTAL XIN RX-
5 14
SDN RX+ C13 C14 L5
6 13
C3 C11
SHUTDOWN
7 8 9 10 11 12 L3
VR SYNTH
VDD ANA/SYNTH
VREF VCO
VR RF
VDD TX/VCO
TX
C10 L6
C4 C6
C5 L7
VSMPS2 C16
VBATT
VBATT
C28
L8 L9 L10 C21
Figure 3: "Suggested application diagram (embedded SMPS not used)" shows the SMPS-
OFF mode application diagram, it allows to improve the sensitivity paying that with an
increasing of the power consumption.
DIGITAL INTERFACE
C0
VR DIG
GPIO 3
GPIO 2
GPIO 1
GPIO 0
CSn
24 23 22 21 20 19
VBATT 1 18
SMPS1 SDI
3 16
XOUT VDD DIG/RX
VBATT C17
4 15
C2
XTAL XIN RX-
5 14
SDN RX+ C13 C14 L5
6 13
C3 C11
SHUTDOWN
7 8 9 10 11 12 L3
VR SYNTH
VDD ANA/SYNTH
VREF VCO
VR RF
VDD TX/VCO
TX
C10 L6
C4 C6
C5 L7
VSMPS2 C16
VBATT
VBATT
C28
L8 L9 L10 C21
4 Specifications
4.1 Absolute maximum ratings
Absolute maximum ratings are those values above which damage to the device may occur.
Functional operation under these conditions is not implied. All voltages refer to GND.
Table 4: Absolute maximum ratings
Parameter Min. Typ. Max. Unit
Supply and SMPS pins -0.3 +3.9
DC voltage on VREG pins -0.3 +3.9
DC voltage on digital input pins -0.3 +3.9
DC voltage on digital output pins -0.3 +3.9 V
DC voltage on ground pins -0.3 +3.9
DC voltage on analog pins -0.3 +1.8
DC voltage on TX pin -0.3 +3.9
Storage temperature range -40 +105 C
VESD-HBM -500 +500 V
Notes:
(1)Using 2-FSK 2.4 kHz DEV, DR=1.2 kbps, 4 bytes preamble and 8kHz ch. filter. Where the receiver wakes up at
regular intervals to look for an incoming packet.
(2)Using 2-FSK 20 kHz DEV, DR=38.4 kbps, 24 bytes preamble and 100kHz ch. filter. Where the receiver wakes
up at regular intervals to look for an incoming packet.
(3)Check for data packet every 1 second in LDC mode. 2-FSK 1.2 kHz DEV and 8kHz ch. filter, DR=1.2 kbps,
internal RC oscillator used as sleep timer. Sniff timer enabled.
(4)Check for data packet every 1 second in LDC mode. 2-FSK 20 kHz DEV, DR=38.4 kbps and 100 kHz ch. filter,
internal 34.6 kHz RC oscillator used as sleep timer. Sniff timer enabled.
Notes:
(1)SMPS output voltage 1.8 V
Notes:
(1)SMPS output voltage 1.8 V
If "Manchester" or "3-out-of-6" or FEC coding options are enabled the actual bit rate is
affected as follows
Table 13: Data rate with different coding options
Coding option 4(G)FSK Data rate [kbps]
NRZ 500
FEC 250
Manchester 250
3-out-of-6 333.3
Notes:
(1)Including
initial tolerance, crystal loading, aging, and temperature dependence. The acceptable crystal tolerance
depends on RF frequency and channel spacing/bandwidth.
(2)Startup times are crystal dependent. The crystal oscillator trans-conductance can be tuned to compensate the
variation of crystal oscillator series resistance
Notes:
(1)Depending on the crystal frequency, the reported value is referring to 50MHz.
4.8 RF receiver
Characteristics measured over recommended operating conditions unless otherwise
specified. All typical values are referred to 25 C temperature, VBAT = 3.0 V, no frequency
offset in the RX signal. All performance is referred to a 50 antenna connector, via the
reference design.
4.9 RF transmitter
Characteristics measured over recommended operating conditions unless otherwise
specified. All typical values are referred to 25 C temperature, VBAT = 3.0 V. All
performance is referred to a 50 antenna connector, via the reference design.
Table 24: RF transmitter characteristics
Parameter Test conditions Typ. Unit
Maximum output power CW @ antenna level 14
Maximum output power in boost mode CW @ antenna level 16 dBm
Minimum output power CW @ antenna level -30
Output power step 0.5 dB
5 Block description
5.1 Power management
The S2-LP integrates a high efficiency step-down converter cascaded with LDOs meant to
supply both analog and digital parts. However, an LDO directly fed by the external battery
provides a controlled voltage to the data interface block.
S2-LPs Power Management (PM) strategy, besides the basic functionality of providing
different blocks with proper supplies, faces two main constraints: the first one is to
implement such a power distribution with maximum efficiency, and the second one is to
guarantee the isolation among critical blocks.
The efficiency target is obtained by using a Switch Mode Power Supply (SMPS) which
converts the battery voltage (1.8 V - 3.6 V) to a lower voltage (settable from 1.1 V to 1.8 V)
with efficiency higher than 90%.
The SMPS output voltage can be controlled by the SET_SMPS_LVL field in the
PM_CONF0 register. The relation between the SET_SMPS_LVL and the VOUT of the SMPS
is given by the following table:
Table 32: SMPS output voltage
SET_SMPS_LVL SMPS Output Voltage
000b 1.1 V
001b 1.2 V
010b 1.3 V
011b 1.4 V
100b 1.5 V
101b 1.6 V
110b 1.7 V
111b 1.8 V
The SMPS output voltage can be controlled in TX only or for both RX and TX according to
the SMPS_LVL_MODE bit of the PM_CONF1 register.
1: SMPS output level will depend upon the value in PM_CONFIG register just in TX
state, while in RX state it will be fixed to 1.4 V.
0: SMPS output level will depend upon the value written in the PM_CONFIG0 register
(SET_SMPS_LEVEL field) both in RX and TX state.
The SMPS switching frequency is settable by the 2 registers PM_CONF3 and PM_CONF2.
If the KRM_EN is 0, then the digital divider by 4 enabled. In this case SMPS' switching
frequency is:
Equation 1
=
4
At RESET, all the registers are at their default values. A software command SRES allows
to generate an internal RESET of the S2-LP.
Table 33: POR parameters
Parameter Typ. Unit
Reset startup threshold voltage 0.5 V
Reset pulse width 0.7 ms
Power on VDD slope 2.0 V/ms
It is recommended to drive the SDN pin correctly to guarantee a correct battery profile.
5.3 RF synthesizer
A crystal connected to XIN and XOUT provides a clock signal to the frequency synthesizer.
The allowed clock signal frequency is either 24, 25, 26, 48, 50, or 52 MHz.
As an alternative, an external clock signal feeds XIN for proper operation. In this option,
XOUT can be left either floating or tied to ground.
Since the digital macro cannot be clocked at that double frequency (48, 50 or 52 MHz), a
divided clock is used in this case (see Section 4.7: "Crystal oscillator").
The integrated phase locked loop (PLL) is capable to synthesize a band of frequencies
from 430 to 470 MHz or from 860 to 940 MHz, providing the LO signal for the RX chain and
the input signal for the PA in the TX chain.
Frequency tolerance and startup times depend on the crystal used, although some tuning
of the latter parameter is possible through registers from 13.2 mS to 43 mS.
Depending on the RF frequency and channel used, a very high accurate crystal or TCXO
can be required.
The RF synthesizer implements fractional sigma delta architecture to allow fast settling and
narrow channel spacing. It is fully integrated, and it uses a multi-band VCO to cover the
whole frequency range. All internal calibrations are automatic.
According to the frequency synthesized the user must set the charge pump current
according to the LO frequency variations, in order to have a constant loop bandwidth. The
charge pump current is controlled by the PLL_CP_ISEL field (SYNT3 register) and the
PLL_PFD_SPLIT_EN (SYNTH_CONFIG2). These fields should be set in the following way:
Table 34: Charge pump words
VCO Freq (MHz) fxo (MHz) PLL_CP_ISEL PLL_PFD_SPLIT_EN ICP (A)
3760 50 010 0 120
3760 25 001 1 200
3460 50 011 0 140
3460 25 010 1 240
The S2-LP provides an automatic and very fast calibration procedure for the frequency
synthesizer. If not disabled, it performs the calibration each time the synthesizer is required
to lock to the programmed RF channel frequency (transaction from READY to
LOCK/TX/RX or from RX to TX and vice versa). After completion, the S2-LP uses the
calibration word and is stored in registers.
In order to get the synthesizer locked with the calibration procedure disabled, the correct
calibration words must be previously stored in registers by user for TX and RX respectively.
The advantage is reduce the LOCK setting time.
The transition time enables the S2-LP for frequency hopping operation due to its reduced
response time and very quick programming synthesizer.
The fc is the frequency related to the channel specified. RF channels can be defined using
the CHSPACE and CHNUM registers. In this way, it is possible to change faster the
channel by changing just an 8-bits register, allowing the setting of 256 channels and
frequency-hopping sequences. The actual channel spacing is from 793 Hz to 202342 Hz in
793 Hz steps for the 26 MHz configuration and from 1587 to 404685 Hz in 1587 Hz steps
for the 52 MHz configuration.
( 8)
_ = 0
= 219
( 1)
( (256 + _) 2 8)
_ > 0
{219
Where is the XTAL oscillation frequency, D is the reference divider and B is the band
selector.
The frequency deviation programmed corresponds to the deviation of the outer
constellation symbols. The deviation of the inner symbols is 1/3 of such programmed
values as reported in where 4 options are available.
Furthermore, in the 4-(G)FSK it is also possible to swap the symbols using the
4FSK_SYM_SWAP field (register PCKTCTRL3) as follows:
S0 =< b7b6 >
When 4FSK_SYM_SWAP = 0: {S1 =< b5b4 >
S2 =< b3b2 >
S3 =< b1b0 >
S0 =< b6b7 >
When 4FSK_SYM_SWAP = 1: {S1 =< b4b5 >
S2 =< b2b3 >
S3 =< b0b1 >
The actual interpolation factor achieved may be limited by the minimal frequency
resolution of the frequency synthesizer.
The FIR ramping modes are used in a mutually exclusive way with the digital
ramping. When the digital ramping is used, the FIR ramping should be disabled.
Vice versa, if the FIR ramping is used, the digital one is not used.
As for the normal TX operations, the TX_FIFO samples are consumed and a management
of the TX_FIFO_THRESHOLD is needed to perform transmissions longer than 128
samples.
The transmission is never automatically stopped and a specific command SABORT should
be given to terminate it.
This function is suitable to implement differential binary phase shift keying modulation
(DBPSK) such as the data modulation used by the SigFox protocol.
5.4.4.2 PN9
It is possible to set a Pseudo Random Binary Sequence 9 (PN9) as data source for the
modulator. In this way, these data will be continuously modulated until a SABORT
command is sent to the device.
The TXSOURCE field (of the PCKTCTRL1 register) must be set to 0x03.
5.5 Receiver
The S2-LP contains a low-power low-IF receiver able to amplify the input signal and
provide it to the ADC with a proper signal to noise ratio. The RF antenna signal is
converted to a differential one by an external balun, which performs an impedance
transformation also. The receiver gain can be programmed to accommodate the ADC input
signal within its dynamic range. After the down-conversion at IF, a first order filter is
implemented to attenuate the out-of-band blockers.
For frequency modulation, the measurement time is normally set to a few s in order to
achieve fast settling of the algorithm.
For amplitude, to avoid an unstable behavior, the measure time must be larger than the
duration of the longest train of 0 symbols expected during the preamble/synchronization
word.
The default value for such parameter is 0x2.
Hold time: this parameter sets a wait time for the algorithm to let the signal level to settle
after a change in the attenuation level.
12
The actual time is = _, ranging from about 0.5 s to about 32 s.
The actual filter bandwidth for any digital clock frequency can be obtained by multiplying
the values in the tables below by the factor . The bandwidth values are intended as
26000000
double-sided.
5.5.8.3 PQI
The preamble quality indicator (PQI) is intended to provide a measurement of the reliability
of the preamble detected. The PQI is increased by 1 every time a bit inversion occurs,
5.5.8.4 SQI
The synchronization quality indicator (SQI) is a measurement of the best correlation
between the received SYNC word and the expected one. This indicator is calculated as the
peak cross-correlation between the received data stream and the expected SYNC word. If
the SQI_EN = 1b, the running peak SQI is compared to a threshold value and the SYNC
valid IRQ is asserted as soon as the threshold is passed. The SYNC quality threshold is
equal to SYNC_LEN 2 x SQI_TH (with SQI_TH = 0, 1, 7). When SQI_TH = 0b, perfect
match is required. It is recommended the SQI check always enabled. The peak SQI value
can be read from the register SQI[5:0] and represents the peak value from 0 to 32, while
the bit SQI[6], when equal to 1 indicates that the SQI peak value refers to the secondary
SYNC word.
5.5.9 CS blanking
The CS blanking feature prevents data to be received if the RSSI level on the air is below
the RSSI threshold (set by the RSSI_TH field). The feature can be enabled through the
CS_BLANKING bit in the ANT_SELECT_CONF register.
5.6.1 PA configuration
The PA output power level is programmable in 0.5 dB steps. The user can store up to eight
output levels to provide flexible PA power ramp-up and ramp-down at the start and end of a
frequency modulation transmission as well as ASK modulation shaping.
With the digital power-ramping enabled (PA_RAMP_EN = 1 in the PA_POWER0 register)
the ramp starts from the minimum output power programmed and stops at the programmed
maximum value, thus a maximum of 8 steps can be set up as shown in Figure 7. The
interpolation factor ranges from 64 down to 1 depending on the actual data rate. The
assumption is that output power monotonically decrease. Each step is held for a
programmable time interval expressed in terms of bit period units (T b/8), maximum value is
3 (which means 4Tb/8=Tb/2). Therefore, the PA ramp may last up to 4 Tb (about 3.3 ms if
the bit rate is 1.2 kbit/s).
The set of eight levels is used to shape the ASK signal. In this case, the modulator works
as a counter that counts when transmitting a one and down when transmitting a zero. The
counter counts at a rate equal to 8 times the symbol rate (in this case, the step width is
fixed by symbol rate).
For OOK modulation, the signal is abruptly switched between two levels only: no power
and maximum. This mode is obtained setting the PA_RAMP_EN=0.
With the digital power-ramping, the digital PA interpolation can be enabled through the
PA_INTERP_EN field of the MOD1 register.
When this feature is enabled, the power values specified in the PA_POWER registers are
linearly interpolated by the modulator before being applied to the PA.
The mathematical interpolation factor applied at each output sample is 64 for data rates
64
corresponding to DATA_RATE_E < 5, it is then automatically scaled as __5 and it
2
is automatically disabled for DATA_RATE_E = 11.
The TX FIFO has two programmable thresholds (see figure above). An interrupt event
occurs when the data in the TX FIFO reaches any of these thresholds. The first threshold is
the FIFO Almost Full threshold, TX_AF_THR registers. The value in this field corresponds
to the desired threshold value in number of bytes + 2. When empty locations (free) amount
inside the TX FIFO reaches this threshold limit, an interrupt to the MCU is generated so it
can send a TX command to transmit the contents of the TX FIFO. The second threshold for
TX is the FIFO Almost Empty threshold, TX_AE_THR register. When the data being
shifted out of the TX FIFO reaches the Almost Empty threshold, an interrupt will be
generated also. The MCU could to switch out of TX mode or fill new data into the TX FIFO.
The RX FIFO has two programmable thresholds (see figure above). The first threshold is
the FIFO Almost Full threshold, RX_AF_THR0 registers. The value in this register
corresponds to the desired threshold value in number of bytes. When empty locations
(free) amount inside the RX FIFO reaches this threshold limit, an interrupt will be generated
to the MCU. The MCU should then start to read the data from the RX FIFO. The second
threshold for RX is the FIFO Almost Empty threshold, RX_AE_THR register. When the
data being shifted out of the RX FIFO reaches the Almost Empty threshold, an interrupt will
be generated also. The MCU will need to switch on RX mode to fill with new data the RX
FIFO or stop to read after the number of byte indicated by the RX_AE_THR register.
In order to enable the RX_FIFO thresholds interrupts, the bit FIFO_GPIO_OUT_MUX_SEL
(PROTOCOL2 register) must be set to 1. To enable the TX_FIFO thresholds interrupts the
FIFO_GPIO_OUT_MUX_SEL must be set to 0.
The FIFO controller will detect overflow or underflow in the RX FIFO and overflow or
underflow in the TX FIFO. It is the responsibility of the MCU to avoid TX FIFO overflow
since the MCU only can decide to writing on the TX FIFO. A TX FIFO overflow will result in
an error in the TX FIFO content, while an underflow results in the continuous transmission
of the last byte stored in the TX FIFO. Likewise, when reading the RX FIFO the MCU must
avoid reading the RX FIFO after its empty condition is reached, since a RX FIFO underflow
will result in an error in the data read out of the RX FIFO.
When an overflow or an underflow is detected, the MCU has to issue a SABORT and a
FLUSHTXFIFO/ FLUSHRXFIFO command before resuming the normal transceiver activity.
For each FIFO, when one of these errors is detected an interrupt will be generated to the
MCU.
6 Operating modes
The S2-LP is provided with a built-in main controller which controls the switching between
the two main operating modes: transmitter (TX) and receiver (RX), driven by SPI
commands.
In shutdown condition (the S2-LP can be switched on/off with the external pin SDN), no
internal supply is generated, and all stored data and configurations are lost.
From shutdown, the S2-LP can be switched on going to READY state, where the reference
clock signal is available.
From READY state, the S2-LP can be moved to LOCK state to generate the high precision
LO signal and then in TX or RX modes. Switching from RX to TX and vice versa can
happen only by passing through the LOCK state. This operation is managed by the main
controller through a single user command (TX or RX). At the end of the operations, the S2-
LP can return to READY state or can go to SLEEP state, having a very low power
consumption.
SLEEP state can be configured to retain the FIFOs content or not enabling very low power
mode. If also no wake up timer is required, the S2-LP can be moved from READY to
STANDBY state, which has the lowest possible current consumption.
Figure 9: State diagram
Three states: READY, STANDBY and LOCK may be defined as stable state.
All other states are transient, which means that, in a typical configuration, the controller
remains in those states, at most for any timeout timer duration. Also the READY and LOCK
states behave as transients when they are not directly accessed with the specific
commands (for example, when LOCK is temporarily used before reaching the TX or RX
states).
Notes:
(1)Other
codes are invalid and are an indication of an error condition due to bad registers configuration and/or
hardware issue in the application board hosting.
Commands are used in the S2-LP to change the operating mode and to use its
functionality. A command is sent on the SPI interface and may be followed by any other
SPI access without pulling CSn high. A command code is the second byte to be sent on the
MOSI pin (the first byte must be 0x80). The commands are immediately valid after SPI
transfer completion (no need for any CSn positive edge).
The transition time enables the S2-LP for frequency hopping operation due to its
reduced response time and very quick programming synthesizer. The response
time depends on frequency of the clock in digital domain, from 24 MHz to 26 MHz.
Sync: the pattern that identify the start of the frame can be configured in value with a
programmable length from 0 to 32 bits, in steps of 1-bit length. The setting is done by
the register SYNC_LENGTH. The S2LP supports dual synchronization with a either a
primary or a secondary synchronization word. The binary content of the primary SYNC
In particular:
MS is always set to 0b (mode switch not supported).
R1-R0 are always set to 00b
FCS is set to:
0b if CRC mode 3 is selected.
1b if CRC mode 5 is selected.
DW is set to:
0b if whitening is disabled, register WHIT_EN = 0.
1b if whitening is enabled, register WHIT_EN = 1.
L10-L0 are set equal to the 11 bits LSB of the packet length registers set by using the
two registers PCKTLENx (x= 1, 2) as: PCKTLEN1 256 + PCKTLEN0. The packet
length is from 0 to 65535 bytes (MHR + MAC Payload + CRC), then LEN_WID = 1b (2
bytes length field transmitted).
Payload: the main data from transmitter with a max length up to 65535 supported by
the embedded automatic packet handler.
CRC: can optionally be calculated on the transmitted data (PHR, MHR + MAC
Payload) and appended at the end of the payload (see Section 7.9: "CRC")
In the 802.5.4g the CRC, named FCS in the standard, is considered part of the PSDU
(PHY payload) hence the packet length, must include the 2 or 4 CRC bytes:
If the packet length programmed in PCKTLEN1 and PCKTLEN0 is L and CRC
mode is 3, then L-2 bytes will be read/written from/to the TX/RX FIFO and
interpreted as MHR + MAC Payload, 2 bytes CRC will automatically be calculated
and inserted at the end of the packet in transmission and stripped in reception.
If the packet length programmed in PCKTLEN1 and PCKTLEN0 is L and CRC
mode is 5, then L-4 bytes will be read/written from/to the TX/RX FIFO and
interpreted as MHR + MAC Payload, 4 bytes CRC will automatically be calculated
and inserted at the end of the packet in transmission and stripped in reception.
If CRC mode is 0, then L bytes will be read/written from/to the TX/RX FIFO and
interpreted as MHR + MAC Payload + MCS. In this case no CRC calculation,
insertion/stripping is done, and it is the responsibility of the MAC layer to process
it.
For CRC mode 3, according to the standard specifications, the CRC output is
complemented to 1 before transmission.
For CRC mode 5, if the payload length is less than 4 bytes then the payload is zero-padded
to reach a minimum length of 4 bytes. The padding bits are only used to compute the CRC
and are not transmitted on-air. The reverse operation is automatically performed on the
receiver.
Preamble: the preamble is fully programmable to fit the W-MBUS protocol. The generic
setting is a pair of 01 or 10 from 1 pair to 1024 pairs (max 256 bytes).
Sync: the pattern that identify the start of the frame is fully programmable to fit the W-
MBUS protocol. The generic setting is in value with a programmable length from 1 bit to 64
bytes, in steps of 1-bit length.
Data blocks: the data coding can be fully programmed in NRZ, Manchester or 3-out-of-6.
Postamble: The packet postamble allows inserting a certain number of 01 bit pairs at the
end of the data packet. The number of postamble bit pairs can be set through the
MBUS_PSTMBL register depending on the chosen sub-mode according to the W-MBUS
protocol.
7.8.1.1 Interleaving
In order to improve the effectiveness of convolutional encoding, matrix interleaving is
applied to the encoded data at the output of the convolutional encoder.
The symbols from the output of the encoder are written raw-wise into a 4x4 matrix buffer
starting from the upper-left cell and read column-wise starting from the lower-right cell.
aThere is no explicit way to signal that a packet is an ACK packet or not. If, after having sent a packet requiring
acknowledgement, the transmitter receives a packet from the receiver with the same sequence number, it shall
assume that this is an ACK packet.
Notes:
(1)The LDC timer can be scaled by 1, 2, 4 or 8.
Using the LDC mode, the S2-LP will wake up periodically saving a lot of power.
Figure 14: LDC RX operation
On each wake-up slot, the S2-LP will enter in TX only if the TX-FIFO is not empty,
otherwise the TX slot will be skipped with the device remaining in SLEEP.
In this case, the TX-FIFO must be retained during the SLEEP state, thus, the SLEEP_B
must be selected setting the SLEEP_MODE_SEL bit to 1.
In case of RX the device will enter in RX and wait for a packet, if it is received, an ack will
be immediately transmitted back.
Figure 16: LDC in RX with auto-ack
If the carrier is present, it will be possible to receive the entire frame because the RX
timeout stop condition is switched to the normal mechanism of PQI/SQI and SYNC can be
detected:
Figure 18: Fast Rx termination: CS detection
In order to ensure that TX frame is always captured, it is advisable to set wake-up time to
less than the preamble time.
To avoid any wait synchronization between different channel contenders, which may cause
successive failing CCA operations, the back-off wait time is calculated randomly inside a
contention window. The back-off time BO is expressed as a multiple of back-off time units
(BU). The contention window is calculated on the basis of the binary exponential back-off
(BEB) technique, which doubles the size of the window at each back-off retry (stored in the
NB counter):
= (6 + rand(0: 2(+1) ) ( + 1))
During this time, the S2-LP is kept in the SLEEP state. If this CSMA mode is used, the user
must set the SLEEP_MODE_SEL bit to 1 in order to guarantee the FIFO retention during
the SLEEP phase.
If the channel is busy and persistent_mode bit is 1, the device will check the channel
continuously in Tcca periods.
When the channel becomes free, it must assert channel free for a number of
NUM._OF_CCA_PERIOD (T. listen) before transmitting:
If the channel is busy and persistent_mode bit is 0, the device will check the channel for the
Tcca period. At the end, being the CS (carrier sense) signal high, it will switch in SLEEP for
a randomic time that can last = (6 + rand(0: 2(+1) ) ( + 1)), with
NB=0.
At the end of this period, it will again switch to RX for another Tcca, then sleep and so on
until the number of backoff set is reached. At that point, an interrupt MAX_BO_REACHED
will be notified to the MCU:
Figure 22: CSMA with non-persistent mode if channel is busy (timeline)
Finally, if the channel becomes free (for example during one of the SLEEP times), the
device must assert channel free for a number of NUM._OF_CCA_PERIOD (T. listen)
before transmitting:
Figure 23: CSMA with non-persistent mode if channel becomes free (timeline)
9 MCU interface
Communication with the MCU goes through a standard 4 wires SPI interface and 4 GPIOs
(plus SHUTDOWN pin).
MCU can performs the following operations:
Program the S2-LP in different operating modes by sending commands
Read data from the RX FIFO and write data into the TX FIFO
Configure the S2-LP through the registers
Retrieve information from the S2-LP
Get interrupt requests and signals from the GPIO pins
Apply external signals to the GPIO pins
Put the S2-LP in SHUTDOWN state or exit from SHUTDOWN state.
SCLK
(CPOL =0)
(CPHA =0)
CSn
A/C W/R
MOSI 0 0 0 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Header Byte Spirit1 Memory Map Address Data written to Address Data written to Address+1
Tri-State
SCLK
CSn
A/C W/R
MOSI 1 0 0 0 0 0 0 0 C7 C6 C5 C4 C3 C2 C1 C0
Tri-State
SCLK
CSn
A/C W/R
MOSI 1 0 0 0 0 0 0 0 C7 C6 C5 C4 C3 C2 C1 C0
Tri-State
Concerning the first byte, the MSB is an A/C bit (Address/Commands: 0 indicates that the
following byte is an address, 1 indicates that the following byte is a command code), while
the LSB is a W/R bit (Write/Read: 1 indicates a read operation). All other bits must be zero.
Read and write operations are persistently executed while CSn is kept active (low), the
address is automatically incremented (burst mode).
Accessing the FIFO is done as usual with the read and write commands, by putting, as
address, the code 0xFF. Burst mode is available to access the sequence of bytes in the
FIFO. Clearly, RX-FIFO is accessed with a read operation, TX-FIFO with a write operation.
9.2 Interrupts
In order to notify the MCU of a certain number of events an interrupt signal is generated on
a selectable GPIO. The following events trigger an interrupt to the MCU:
Table 56: Interrupts list
Bit Events group Interrupt event
0 RX data ready
1 RX data discarded (upon filtering)
Packet oriented
2 TX data sent
3 Max. re-TX reached
Notes:
(1)The interrupt flag n.15 is set (and consequently the interrupt request) only when the XO clock is available for the
state machine. This time may be delayed compared to the actual timer expiration. However, the real time event
can be sensed putting the end-of-counting signal on a GPIO output.
(2)The interrupt flag n.16 is set each time the S2-LP goes to READY state and the XO has completed its setting
transient (XO ready condition detected).
All interrupts are reported on a set of interrupt status registers and are individually
maskable. The interrupt status register must be cleared upon a read event from the MCU.
The status of all the interrupts are reported in the IRQ_STATUS register: bits are high for
the events that have generated any interrupts. The interrupts are individually maskable
using the IRQ_MASK registers: if the mask bit related to a particular event is programmed
at 0, that event does not generate any interrupt request.
10 Register contents
Table 59: Register contents
Name Addr Default Bit Field name Description
2 RESERVED -
GPIO0_CONF 00 0A GPIO0 Mode:
01b: Digital Input
1:0 GPIO_MODE
10b: Digital Output Low Power
11b: Digital Output High Power
2 RESERVED -
GPIO1_CONF 01 A2 GPIO1 Mode:
01b: Digital Input1
1:0 GPIO_MODE
0b: Digital Output Low Power
11b: Digital Output High Power
2 RESERVED -
GPIO2_CONF 02 A2 GPIO2 Mode:
01b: Digital Input
1:0 GPIO_MODE
10b: Digital Output Low Power
11b: Digital Output High Power
2 RESERVED -
Modulation type:
0: 2-FSK
1: 4-FSK
2: 2-GFSK BT=1
7:4 MOD_TYPE 3: 4-GFSK BT=1
MOD2 10 77 5: ASK/OOK
7: unmodulated
10: 2-GFSK BT=0.5
12: 4-GFSK BT=0.5
4:0 RESERVED -
7:4 AFC_FAST_GAIN The AFC loop gain in fast mode (2's log).
AFC0 16 25
3:0 AFC_SLOW_GAIN The AFC loop gain in slow mode (2's log).
1:0 RESERVED -
7:6 RESERVED -
0: disabled
7 AGC_ENABLE
1: enabled
AGCCTRL0 1E 8C
6 RESERVED -
5:0 HOLD_TIME Hold time for after gain adjustment for the AGC.
7 RESERVED -
2:0 RESERVED -
Format of packet:
0: Basic
1: 802.15.4g
7:6 PCKT_FRMT 2: UART OTA
3: Stack
(see section 6 )
RX mode:
PCKTCTRL3 2E 20
0: normal mode
5:4 RX_MODE
1: direct through FIFO
2: direct through GPIO
7:6 RESERVED -
CRC field:
0: no CRC field
1: CRC using poly 0x07
7:5 CRC_MODE 2: CRC using poly 0x8005
3: CRC using poly 0x1021
4: CRC using poly 0x864CBF
5: CRC using poly 0x04C011BB7
Tx source data:
0: normal mode
PCKTCTRL1 30 2C
3:2 TXSOURCE 1: direct through FIFO
2: direct through GPIO
3: PN9
In TX mode:
0 select the primary SYNC word
1 SECOND_SYNC_SEL 1 select the secondary SYNC word.
0 RESERVED -
7 RESERVED -
FIFO_CONFIG3 3C 30
6:0 RX_AFTHR Set the RX FIFO almost full threshold.
7 RESERVED -
FIFO_CONFIG2 3D 30
6:0 RX_AETHR Set the RX FIFO almost empty threshold.
7 RESERVED -
FIFO_CONFIG1 3E 30
6:0 TX_AFTHR Set the TX FIFO almost full threshold.
FIFO_CONFIG0 3F 30 7 RESERVED -
7 RESERVED -
5 RESERVED -
TIMERS1 4A 01 7:0 LDC_RELOAD_PRSC Prescaler value for reload operation of wake up timer.
TIMERS0 4B 00 7:0 LDC_RELOAD_CNTR Counter value for reload operation of wake up timer.
PA_POWER8 5A 01 7 RESERVED -
7 RESERVED -
PA_POWER7 5B 0C
6:0 PA_LEVEL_7 Output power level for 7th slot.
7 RESERVED -
PA_POWER6 5C 18
6:0 PA_LEVEL_6 Output power level for 6th slot.
7 RESERVED -
PA_POWER5 5D 24
6:0 PA_LEVEL_5 Output power level for 5th slot.
7 RESERVED -
PA_POWER4 5E 30
6:0 PA_LEVEL_4 Output power level for 4th slot.
7 RESERVED -
PA_POWER3 5F 48
6:0 PA_LEVEL_3 Output power level for 3rd slot.
7 RESERVED -
PA_POWER2 60 60
6:0 PA_LEVEL_2 Output power level for 2nd slot.
7 RESERVED -
PA_POWER1 61 00
6:0 PA_LEVEL_1 Output power level for 1st slot.
4:3 PA_RAMP_STEP_LEN Set the step width (unit: 1/8 of bit period).
7:4 RESERVED -
FIR configuration:
00b: filtering
3:2 FIR_CFG
PA_CONFIG1 63 03 01b: ramping
10b: switching (see Section 5.4.2.1)
0 RESERVED -
7:2 RESERVED -
7:3 RESERVED -
1:0 RESERVED -
7:6 RESERVED -
3:0 RESERVED -
7 RESERVED -
VCO_CALIBR_IN1 6A 40 VCO Cbank frequency calibration word to be used in
6:0 VCO_CALFREQ_TX
TX.
7 RESERVED -
VCO_CALIBR_IN0 6B 40 VCO Cbank frequency calibration word to be used in
6:0 VCO_CALFREQ_RX
RX.
7:5 RESERVED -
3:0 RESERVED -
0: reference signal from XO circuit
7 EXT_REF 1: reference signal from XIN pin.
7:6 RESERVED -
4:0 RESERVED -
0: divider by 4 enabled (SMPS' switching
frequency is FSW=Fdig/4)
7 KRM_EN 1: rate multiplier enabled (SMPS' switching
PM_CONF3 76 20 frequency is FSW=KRM*Fdig/(2^15).
7 RESERVED -
1:0 RESERVED -
7 RESERVED -
3:1 RESERVED -
0: SLEEP without FIFO retention (SLEEP A)
0 SLEEP_MODE_SEL 1: SLEEP with FIFO retention (SLEEP B).
7:5 RESERVED -
7:4 RESERVED -
VCO_CALIBR_OUT1 99 00 VCO magnitude calibration output word (binary coding
3:0 VCO_CAL_AMP_OUT
internally converted from thermometric coding).
7 RESERVED -
7:6 RESERVED -
7:3 RESERVED -
RX_PCKT_LEN1 A4 00 7:0 RX_PCKT_LEN[14:8] MSB value of the length of the packet received.
RX_PCKT_LEN0 A5 00 7:0 RX_PCKT_LEN[7:0] LSB value of the length of the packet received.
11 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
12 Revision history
Table 61: Document revision history
Date Version Changes
08-Nov-2016 1 Initial release.
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